module MultiPortFifo_in4_out4(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  output  io_enq_1_ready,
  input   io_enq_1_valid,
  output  io_enq_2_ready,
  input   io_enq_2_valid,
  output  io_enq_3_ready,
  input   io_enq_3_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_deq_1_ready,
  output  io_deq_1_valid,
  input   io_deq_2_ready,
  output  io_deq_2_valid,
  input   io_deq_3_ready,
  output  io_deq_3_valid,
  input   io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_2; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_3; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_4; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_5; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_6; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_7; // @[MultiPortFifo.scala 58:30]
  reg [2:0] rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg [2:0] wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [3:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = 3'h1 == _io_enq_0_ready_T[2:0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_2 = 3'h2 == _io_enq_0_ready_T[2:0] ? buf_valid_2 : _GEN_1; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_3 = 3'h3 == _io_enq_0_ready_T[2:0] ? buf_valid_3 : _GEN_2; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_4 = 3'h4 == _io_enq_0_ready_T[2:0] ? buf_valid_4 : _GEN_3; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_5 = 3'h5 == _io_enq_0_ready_T[2:0] ? buf_valid_5 : _GEN_4; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_6 = 3'h6 == _io_enq_0_ready_T[2:0] ? buf_valid_6 : _GEN_5; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_7 = 3'h7 == _io_enq_0_ready_T[2:0] ? buf_valid_7 : _GEN_6; // @[MultiPortFifo.scala 64:{94,94}]
  wire [2:0] _io_enq_1_ready_T_1 = wr_ptr + 3'h1; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_9 = 3'h1 == _io_enq_1_ready_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_10 = 3'h2 == _io_enq_1_ready_T_1 ? buf_valid_2 : _GEN_9; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_11 = 3'h3 == _io_enq_1_ready_T_1 ? buf_valid_3 : _GEN_10; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_12 = 3'h4 == _io_enq_1_ready_T_1 ? buf_valid_4 : _GEN_11; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_13 = 3'h5 == _io_enq_1_ready_T_1 ? buf_valid_5 : _GEN_12; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_14 = 3'h6 == _io_enq_1_ready_T_1 ? buf_valid_6 : _GEN_13; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_15 = 3'h7 == _io_enq_1_ready_T_1 ? buf_valid_7 : _GEN_14; // @[MultiPortFifo.scala 64:{94,94}]
  wire [2:0] _io_enq_2_ready_T_1 = wr_ptr + 3'h2; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_17 = 3'h1 == _io_enq_2_ready_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_18 = 3'h2 == _io_enq_2_ready_T_1 ? buf_valid_2 : _GEN_17; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_19 = 3'h3 == _io_enq_2_ready_T_1 ? buf_valid_3 : _GEN_18; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_20 = 3'h4 == _io_enq_2_ready_T_1 ? buf_valid_4 : _GEN_19; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_21 = 3'h5 == _io_enq_2_ready_T_1 ? buf_valid_5 : _GEN_20; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_22 = 3'h6 == _io_enq_2_ready_T_1 ? buf_valid_6 : _GEN_21; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_23 = 3'h7 == _io_enq_2_ready_T_1 ? buf_valid_7 : _GEN_22; // @[MultiPortFifo.scala 64:{94,94}]
  wire [2:0] _io_enq_3_ready_T_1 = wr_ptr + 3'h3; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_25 = 3'h1 == _io_enq_3_ready_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_26 = 3'h2 == _io_enq_3_ready_T_1 ? buf_valid_2 : _GEN_25; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_27 = 3'h3 == _io_enq_3_ready_T_1 ? buf_valid_3 : _GEN_26; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_28 = 3'h4 == _io_enq_3_ready_T_1 ? buf_valid_4 : _GEN_27; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_29 = 3'h5 == _io_enq_3_ready_T_1 ? buf_valid_5 : _GEN_28; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_30 = 3'h6 == _io_enq_3_ready_T_1 ? buf_valid_6 : _GEN_29; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_31 = 3'h7 == _io_enq_3_ready_T_1 ? buf_valid_7 : _GEN_30; // @[MultiPortFifo.scala 64:{94,94}]
  wire [3:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _GEN_33 = 3'h1 == _io_deq_0_valid_T[2:0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_34 = 3'h2 == _io_deq_0_valid_T[2:0] ? buf_valid_2 : _GEN_33; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_35 = 3'h3 == _io_deq_0_valid_T[2:0] ? buf_valid_3 : _GEN_34; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_36 = 3'h4 == _io_deq_0_valid_T[2:0] ? buf_valid_4 : _GEN_35; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_37 = 3'h5 == _io_deq_0_valid_T[2:0] ? buf_valid_5 : _GEN_36; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_38 = 3'h6 == _io_deq_0_valid_T[2:0] ? buf_valid_6 : _GEN_37; // @[MultiPortFifo.scala 65:{94,94}]
  wire [2:0] _io_deq_1_valid_T_1 = rd_ptr + 3'h1; // @[MultiPortFifo.scala 65:78]
  wire  _GEN_41 = 3'h1 == _io_deq_1_valid_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_42 = 3'h2 == _io_deq_1_valid_T_1 ? buf_valid_2 : _GEN_41; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_43 = 3'h3 == _io_deq_1_valid_T_1 ? buf_valid_3 : _GEN_42; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_44 = 3'h4 == _io_deq_1_valid_T_1 ? buf_valid_4 : _GEN_43; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_45 = 3'h5 == _io_deq_1_valid_T_1 ? buf_valid_5 : _GEN_44; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_46 = 3'h6 == _io_deq_1_valid_T_1 ? buf_valid_6 : _GEN_45; // @[MultiPortFifo.scala 65:{94,94}]
  wire [2:0] _io_deq_2_valid_T_1 = rd_ptr + 3'h2; // @[MultiPortFifo.scala 65:78]
  wire  _GEN_49 = 3'h1 == _io_deq_2_valid_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_50 = 3'h2 == _io_deq_2_valid_T_1 ? buf_valid_2 : _GEN_49; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_51 = 3'h3 == _io_deq_2_valid_T_1 ? buf_valid_3 : _GEN_50; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_52 = 3'h4 == _io_deq_2_valid_T_1 ? buf_valid_4 : _GEN_51; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_53 = 3'h5 == _io_deq_2_valid_T_1 ? buf_valid_5 : _GEN_52; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_54 = 3'h6 == _io_deq_2_valid_T_1 ? buf_valid_6 : _GEN_53; // @[MultiPortFifo.scala 65:{94,94}]
  wire [2:0] _io_deq_3_valid_T_1 = rd_ptr + 3'h3; // @[MultiPortFifo.scala 65:78]
  wire  _GEN_57 = 3'h1 == _io_deq_3_valid_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_58 = 3'h2 == _io_deq_3_valid_T_1 ? buf_valid_2 : _GEN_57; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_59 = 3'h3 == _io_deq_3_valid_T_1 ? buf_valid_3 : _GEN_58; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_60 = 3'h4 == _io_deq_3_valid_T_1 ? buf_valid_4 : _GEN_59; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_61 = 3'h5 == _io_deq_3_valid_T_1 ? buf_valid_5 : _GEN_60; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_62 = 3'h6 == _io_deq_3_valid_T_1 ? buf_valid_6 : _GEN_61; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_96 = 3'h0 == _io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_97 = 3'h1 == _io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_98 = 3'h2 == _io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_99 = 3'h3 == _io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_100 = 3'h4 == _io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_101 = 3'h5 == _io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_102 = 3'h6 == _io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_103 = 3'h7 == _io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_72 = _T ? 3'h0 == _io_enq_0_ready_T[2:0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_73 = _T ? 3'h1 == _io_enq_0_ready_T[2:0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_74 = _T ? 3'h2 == _io_enq_0_ready_T[2:0] | buf_valid_2 : buf_valid_2; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_75 = _T ? 3'h3 == _io_enq_0_ready_T[2:0] | buf_valid_3 : buf_valid_3; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_76 = _T ? 3'h4 == _io_enq_0_ready_T[2:0] | buf_valid_4 : buf_valid_4; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_77 = _T ? 3'h5 == _io_enq_0_ready_T[2:0] | buf_valid_5 : buf_valid_5; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_78 = _T ? 3'h6 == _io_enq_0_ready_T[2:0] | buf_valid_6 : buf_valid_6; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_79 = _T ? 3'h7 == _io_enq_0_ready_T[2:0] | buf_valid_7 : buf_valid_7; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_80 = 3'h0 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_72; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_81 = 3'h1 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_73; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_82 = 3'h2 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_74; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_83 = 3'h3 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_75; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_84 = 3'h4 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_76; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_85 = 3'h5 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_77; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_86 = 3'h6 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_78; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_87 = 3'h7 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_79; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_88 = _T_1 ? _GEN_80 : _GEN_72; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_89 = _T_1 ? _GEN_81 : _GEN_73; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_90 = _T_1 ? _GEN_82 : _GEN_74; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_91 = _T_1 ? _GEN_83 : _GEN_75; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_92 = _T_1 ? _GEN_84 : _GEN_76; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_93 = _T_1 ? _GEN_85 : _GEN_77; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_94 = _T_1 ? _GEN_86 : _GEN_78; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_95 = _T_1 ? _GEN_87 : _GEN_79; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_184 = _T ? _GEN_96 | _GEN_88 : _GEN_88; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_185 = _T ? _GEN_97 | _GEN_89 : _GEN_89; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_186 = _T ? _GEN_98 | _GEN_90 : _GEN_90; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_187 = _T ? _GEN_99 | _GEN_91 : _GEN_91; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_188 = _T ? _GEN_100 | _GEN_92 : _GEN_92; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_189 = _T ? _GEN_101 | _GEN_93 : _GEN_93; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_190 = _T ? _GEN_102 | _GEN_94 : _GEN_94; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_191 = _T ? _GEN_103 | _GEN_95 : _GEN_95; // @[MultiPortFifo.scala 97:34]
  wire  _T_3 = io_deq_1_ready & io_deq_1_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_192 = 3'h0 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_184; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_193 = 3'h1 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_185; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_194 = 3'h2 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_186; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_195 = 3'h3 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_187; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_196 = 3'h4 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_188; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_197 = 3'h5 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_189; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_198 = 3'h6 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_190; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_199 = 3'h7 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_191; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_200 = _T_3 ? _GEN_192 : _GEN_184; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_201 = _T_3 ? _GEN_193 : _GEN_185; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_202 = _T_3 ? _GEN_194 : _GEN_186; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_203 = _T_3 ? _GEN_195 : _GEN_187; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_204 = _T_3 ? _GEN_196 : _GEN_188; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_205 = _T_3 ? _GEN_197 : _GEN_189; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_206 = _T_3 ? _GEN_198 : _GEN_190; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_207 = _T_3 ? _GEN_199 : _GEN_191; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_296 = _T ? _GEN_96 | _GEN_200 : _GEN_200; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_297 = _T ? _GEN_97 | _GEN_201 : _GEN_201; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_298 = _T ? _GEN_98 | _GEN_202 : _GEN_202; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_299 = _T ? _GEN_99 | _GEN_203 : _GEN_203; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_300 = _T ? _GEN_100 | _GEN_204 : _GEN_204; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_301 = _T ? _GEN_101 | _GEN_205 : _GEN_205; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_302 = _T ? _GEN_102 | _GEN_206 : _GEN_206; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_303 = _T ? _GEN_103 | _GEN_207 : _GEN_207; // @[MultiPortFifo.scala 97:34]
  wire  _T_5 = io_deq_2_ready & io_deq_2_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_304 = 3'h0 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_296; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_305 = 3'h1 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_297; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_306 = 3'h2 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_298; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_307 = 3'h3 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_299; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_308 = 3'h4 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_300; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_309 = 3'h5 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_301; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_310 = 3'h6 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_302; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_311 = 3'h7 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_303; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_312 = _T_5 ? _GEN_304 : _GEN_296; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_313 = _T_5 ? _GEN_305 : _GEN_297; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_314 = _T_5 ? _GEN_306 : _GEN_298; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_315 = _T_5 ? _GEN_307 : _GEN_299; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_316 = _T_5 ? _GEN_308 : _GEN_300; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_317 = _T_5 ? _GEN_309 : _GEN_301; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_318 = _T_5 ? _GEN_310 : _GEN_302; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_319 = _T_5 ? _GEN_311 : _GEN_303; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_408 = _T ? _GEN_96 | _GEN_312 : _GEN_312; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_409 = _T ? _GEN_97 | _GEN_313 : _GEN_313; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_410 = _T ? _GEN_98 | _GEN_314 : _GEN_314; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_411 = _T ? _GEN_99 | _GEN_315 : _GEN_315; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_412 = _T ? _GEN_100 | _GEN_316 : _GEN_316; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_413 = _T ? _GEN_101 | _GEN_317 : _GEN_317; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_414 = _T ? _GEN_102 | _GEN_318 : _GEN_318; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_415 = _T ? _GEN_103 | _GEN_319 : _GEN_319; // @[MultiPortFifo.scala 97:34]
  wire  _T_7 = io_deq_3_ready & io_deq_3_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_416 = 3'h0 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_408; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_417 = 3'h1 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_409; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_418 = 3'h2 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_410; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_419 = 3'h3 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_411; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_420 = 3'h4 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_412; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_421 = 3'h5 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_413; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_422 = 3'h6 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_414; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_423 = 3'h7 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_415; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_424 = _T_7 ? _GEN_416 : _GEN_408; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_425 = _T_7 ? _GEN_417 : _GEN_409; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_426 = _T_7 ? _GEN_418 : _GEN_410; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_427 = _T_7 ? _GEN_419 : _GEN_411; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_428 = _T_7 ? _GEN_420 : _GEN_412; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_429 = _T_7 ? _GEN_421 : _GEN_413; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_430 = _T_7 ? _GEN_422 : _GEN_414; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_431 = _T_7 ? _GEN_423 : _GEN_415; // @[MultiPortFifo.scala 98:34]
  wire  _T_8 = io_enq_1_ready & io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_520 = _T_8 ? 3'h0 == _io_enq_1_ready_T_1 | _GEN_424 : _GEN_424; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_521 = _T_8 ? 3'h1 == _io_enq_1_ready_T_1 | _GEN_425 : _GEN_425; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_522 = _T_8 ? 3'h2 == _io_enq_1_ready_T_1 | _GEN_426 : _GEN_426; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_523 = _T_8 ? 3'h3 == _io_enq_1_ready_T_1 | _GEN_427 : _GEN_427; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_524 = _T_8 ? 3'h4 == _io_enq_1_ready_T_1 | _GEN_428 : _GEN_428; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_525 = _T_8 ? 3'h5 == _io_enq_1_ready_T_1 | _GEN_429 : _GEN_429; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_526 = _T_8 ? 3'h6 == _io_enq_1_ready_T_1 | _GEN_430 : _GEN_430; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_527 = _T_8 ? 3'h7 == _io_enq_1_ready_T_1 | _GEN_431 : _GEN_431; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_528 = 3'h0 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_520; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_529 = 3'h1 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_521; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_530 = 3'h2 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_522; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_531 = 3'h3 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_523; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_532 = 3'h4 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_524; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_533 = 3'h5 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_525; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_534 = 3'h6 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_526; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_535 = 3'h7 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_527; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_536 = _T_1 ? _GEN_528 : _GEN_520; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_537 = _T_1 ? _GEN_529 : _GEN_521; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_538 = _T_1 ? _GEN_530 : _GEN_522; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_539 = _T_1 ? _GEN_531 : _GEN_523; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_540 = _T_1 ? _GEN_532 : _GEN_524; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_541 = _T_1 ? _GEN_533 : _GEN_525; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_542 = _T_1 ? _GEN_534 : _GEN_526; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_543 = _T_1 ? _GEN_535 : _GEN_527; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_632 = _T_8 ? 3'h0 == _io_enq_1_ready_T_1 | _GEN_536 : _GEN_536; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_633 = _T_8 ? 3'h1 == _io_enq_1_ready_T_1 | _GEN_537 : _GEN_537; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_634 = _T_8 ? 3'h2 == _io_enq_1_ready_T_1 | _GEN_538 : _GEN_538; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_635 = _T_8 ? 3'h3 == _io_enq_1_ready_T_1 | _GEN_539 : _GEN_539; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_636 = _T_8 ? 3'h4 == _io_enq_1_ready_T_1 | _GEN_540 : _GEN_540; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_637 = _T_8 ? 3'h5 == _io_enq_1_ready_T_1 | _GEN_541 : _GEN_541; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_638 = _T_8 ? 3'h6 == _io_enq_1_ready_T_1 | _GEN_542 : _GEN_542; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_639 = _T_8 ? 3'h7 == _io_enq_1_ready_T_1 | _GEN_543 : _GEN_543; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_640 = 3'h0 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_632; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_641 = 3'h1 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_633; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_642 = 3'h2 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_634; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_643 = 3'h3 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_635; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_644 = 3'h4 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_636; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_645 = 3'h5 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_637; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_646 = 3'h6 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_638; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_647 = 3'h7 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_639; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_648 = _T_3 ? _GEN_640 : _GEN_632; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_649 = _T_3 ? _GEN_641 : _GEN_633; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_650 = _T_3 ? _GEN_642 : _GEN_634; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_651 = _T_3 ? _GEN_643 : _GEN_635; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_652 = _T_3 ? _GEN_644 : _GEN_636; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_653 = _T_3 ? _GEN_645 : _GEN_637; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_654 = _T_3 ? _GEN_646 : _GEN_638; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_655 = _T_3 ? _GEN_647 : _GEN_639; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_744 = _T_8 ? 3'h0 == _io_enq_1_ready_T_1 | _GEN_648 : _GEN_648; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_745 = _T_8 ? 3'h1 == _io_enq_1_ready_T_1 | _GEN_649 : _GEN_649; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_746 = _T_8 ? 3'h2 == _io_enq_1_ready_T_1 | _GEN_650 : _GEN_650; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_747 = _T_8 ? 3'h3 == _io_enq_1_ready_T_1 | _GEN_651 : _GEN_651; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_748 = _T_8 ? 3'h4 == _io_enq_1_ready_T_1 | _GEN_652 : _GEN_652; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_749 = _T_8 ? 3'h5 == _io_enq_1_ready_T_1 | _GEN_653 : _GEN_653; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_750 = _T_8 ? 3'h6 == _io_enq_1_ready_T_1 | _GEN_654 : _GEN_654; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_751 = _T_8 ? 3'h7 == _io_enq_1_ready_T_1 | _GEN_655 : _GEN_655; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_752 = 3'h0 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_744; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_753 = 3'h1 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_745; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_754 = 3'h2 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_746; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_755 = 3'h3 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_747; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_756 = 3'h4 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_748; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_757 = 3'h5 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_749; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_758 = 3'h6 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_750; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_759 = 3'h7 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_751; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_760 = _T_5 ? _GEN_752 : _GEN_744; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_761 = _T_5 ? _GEN_753 : _GEN_745; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_762 = _T_5 ? _GEN_754 : _GEN_746; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_763 = _T_5 ? _GEN_755 : _GEN_747; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_764 = _T_5 ? _GEN_756 : _GEN_748; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_765 = _T_5 ? _GEN_757 : _GEN_749; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_766 = _T_5 ? _GEN_758 : _GEN_750; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_767 = _T_5 ? _GEN_759 : _GEN_751; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_856 = _T_8 ? 3'h0 == _io_enq_1_ready_T_1 | _GEN_760 : _GEN_760; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_857 = _T_8 ? 3'h1 == _io_enq_1_ready_T_1 | _GEN_761 : _GEN_761; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_858 = _T_8 ? 3'h2 == _io_enq_1_ready_T_1 | _GEN_762 : _GEN_762; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_859 = _T_8 ? 3'h3 == _io_enq_1_ready_T_1 | _GEN_763 : _GEN_763; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_860 = _T_8 ? 3'h4 == _io_enq_1_ready_T_1 | _GEN_764 : _GEN_764; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_861 = _T_8 ? 3'h5 == _io_enq_1_ready_T_1 | _GEN_765 : _GEN_765; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_862 = _T_8 ? 3'h6 == _io_enq_1_ready_T_1 | _GEN_766 : _GEN_766; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_863 = _T_8 ? 3'h7 == _io_enq_1_ready_T_1 | _GEN_767 : _GEN_767; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_864 = 3'h0 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_856; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_865 = 3'h1 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_857; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_866 = 3'h2 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_858; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_867 = 3'h3 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_859; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_868 = 3'h4 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_860; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_869 = 3'h5 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_861; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_870 = 3'h6 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_862; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_871 = 3'h7 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_863; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_872 = _T_7 ? _GEN_864 : _GEN_856; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_873 = _T_7 ? _GEN_865 : _GEN_857; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_874 = _T_7 ? _GEN_866 : _GEN_858; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_875 = _T_7 ? _GEN_867 : _GEN_859; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_876 = _T_7 ? _GEN_868 : _GEN_860; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_877 = _T_7 ? _GEN_869 : _GEN_861; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_878 = _T_7 ? _GEN_870 : _GEN_862; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_879 = _T_7 ? _GEN_871 : _GEN_863; // @[MultiPortFifo.scala 98:34]
  wire  _T_16 = io_enq_2_ready & io_enq_2_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_968 = _T_16 ? 3'h0 == _io_enq_2_ready_T_1 | _GEN_872 : _GEN_872; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_969 = _T_16 ? 3'h1 == _io_enq_2_ready_T_1 | _GEN_873 : _GEN_873; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_970 = _T_16 ? 3'h2 == _io_enq_2_ready_T_1 | _GEN_874 : _GEN_874; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_971 = _T_16 ? 3'h3 == _io_enq_2_ready_T_1 | _GEN_875 : _GEN_875; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_972 = _T_16 ? 3'h4 == _io_enq_2_ready_T_1 | _GEN_876 : _GEN_876; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_973 = _T_16 ? 3'h5 == _io_enq_2_ready_T_1 | _GEN_877 : _GEN_877; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_974 = _T_16 ? 3'h6 == _io_enq_2_ready_T_1 | _GEN_878 : _GEN_878; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_975 = _T_16 ? 3'h7 == _io_enq_2_ready_T_1 | _GEN_879 : _GEN_879; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_976 = 3'h0 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_968; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_977 = 3'h1 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_969; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_978 = 3'h2 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_970; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_979 = 3'h3 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_971; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_980 = 3'h4 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_972; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_981 = 3'h5 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_973; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_982 = 3'h6 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_974; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_983 = 3'h7 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_975; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_984 = _T_1 ? _GEN_976 : _GEN_968; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_985 = _T_1 ? _GEN_977 : _GEN_969; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_986 = _T_1 ? _GEN_978 : _GEN_970; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_987 = _T_1 ? _GEN_979 : _GEN_971; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_988 = _T_1 ? _GEN_980 : _GEN_972; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_989 = _T_1 ? _GEN_981 : _GEN_973; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_990 = _T_1 ? _GEN_982 : _GEN_974; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_991 = _T_1 ? _GEN_983 : _GEN_975; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1080 = _T_16 ? 3'h0 == _io_enq_2_ready_T_1 | _GEN_984 : _GEN_984; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1081 = _T_16 ? 3'h1 == _io_enq_2_ready_T_1 | _GEN_985 : _GEN_985; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1082 = _T_16 ? 3'h2 == _io_enq_2_ready_T_1 | _GEN_986 : _GEN_986; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1083 = _T_16 ? 3'h3 == _io_enq_2_ready_T_1 | _GEN_987 : _GEN_987; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1084 = _T_16 ? 3'h4 == _io_enq_2_ready_T_1 | _GEN_988 : _GEN_988; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1085 = _T_16 ? 3'h5 == _io_enq_2_ready_T_1 | _GEN_989 : _GEN_989; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1086 = _T_16 ? 3'h6 == _io_enq_2_ready_T_1 | _GEN_990 : _GEN_990; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1087 = _T_16 ? 3'h7 == _io_enq_2_ready_T_1 | _GEN_991 : _GEN_991; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1088 = 3'h0 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1080; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1089 = 3'h1 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1081; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1090 = 3'h2 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1082; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1091 = 3'h3 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1083; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1092 = 3'h4 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1084; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1093 = 3'h5 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1085; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1094 = 3'h6 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1086; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1095 = 3'h7 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1087; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1096 = _T_3 ? _GEN_1088 : _GEN_1080; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1097 = _T_3 ? _GEN_1089 : _GEN_1081; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1098 = _T_3 ? _GEN_1090 : _GEN_1082; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1099 = _T_3 ? _GEN_1091 : _GEN_1083; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1100 = _T_3 ? _GEN_1092 : _GEN_1084; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1101 = _T_3 ? _GEN_1093 : _GEN_1085; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1102 = _T_3 ? _GEN_1094 : _GEN_1086; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1103 = _T_3 ? _GEN_1095 : _GEN_1087; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1192 = _T_16 ? 3'h0 == _io_enq_2_ready_T_1 | _GEN_1096 : _GEN_1096; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1193 = _T_16 ? 3'h1 == _io_enq_2_ready_T_1 | _GEN_1097 : _GEN_1097; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1194 = _T_16 ? 3'h2 == _io_enq_2_ready_T_1 | _GEN_1098 : _GEN_1098; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1195 = _T_16 ? 3'h3 == _io_enq_2_ready_T_1 | _GEN_1099 : _GEN_1099; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1196 = _T_16 ? 3'h4 == _io_enq_2_ready_T_1 | _GEN_1100 : _GEN_1100; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1197 = _T_16 ? 3'h5 == _io_enq_2_ready_T_1 | _GEN_1101 : _GEN_1101; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1198 = _T_16 ? 3'h6 == _io_enq_2_ready_T_1 | _GEN_1102 : _GEN_1102; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1199 = _T_16 ? 3'h7 == _io_enq_2_ready_T_1 | _GEN_1103 : _GEN_1103; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1200 = 3'h0 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1192; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1201 = 3'h1 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1193; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1202 = 3'h2 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1194; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1203 = 3'h3 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1195; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1204 = 3'h4 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1196; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1205 = 3'h5 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1197; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1206 = 3'h6 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1198; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1207 = 3'h7 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1199; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1208 = _T_5 ? _GEN_1200 : _GEN_1192; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1209 = _T_5 ? _GEN_1201 : _GEN_1193; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1210 = _T_5 ? _GEN_1202 : _GEN_1194; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1211 = _T_5 ? _GEN_1203 : _GEN_1195; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1212 = _T_5 ? _GEN_1204 : _GEN_1196; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1213 = _T_5 ? _GEN_1205 : _GEN_1197; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1214 = _T_5 ? _GEN_1206 : _GEN_1198; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1215 = _T_5 ? _GEN_1207 : _GEN_1199; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1304 = _T_16 ? 3'h0 == _io_enq_2_ready_T_1 | _GEN_1208 : _GEN_1208; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1305 = _T_16 ? 3'h1 == _io_enq_2_ready_T_1 | _GEN_1209 : _GEN_1209; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1306 = _T_16 ? 3'h2 == _io_enq_2_ready_T_1 | _GEN_1210 : _GEN_1210; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1307 = _T_16 ? 3'h3 == _io_enq_2_ready_T_1 | _GEN_1211 : _GEN_1211; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1308 = _T_16 ? 3'h4 == _io_enq_2_ready_T_1 | _GEN_1212 : _GEN_1212; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1309 = _T_16 ? 3'h5 == _io_enq_2_ready_T_1 | _GEN_1213 : _GEN_1213; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1310 = _T_16 ? 3'h6 == _io_enq_2_ready_T_1 | _GEN_1214 : _GEN_1214; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1311 = _T_16 ? 3'h7 == _io_enq_2_ready_T_1 | _GEN_1215 : _GEN_1215; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1312 = 3'h0 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_1304; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1313 = 3'h1 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_1305; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1314 = 3'h2 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_1306; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1315 = 3'h3 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_1307; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1316 = 3'h4 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_1308; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1317 = 3'h5 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_1309; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1318 = 3'h6 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_1310; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1319 = 3'h7 == _io_deq_3_valid_T_1 ? 1'h0 : _GEN_1311; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1320 = _T_7 ? _GEN_1312 : _GEN_1304; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1321 = _T_7 ? _GEN_1313 : _GEN_1305; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1322 = _T_7 ? _GEN_1314 : _GEN_1306; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1323 = _T_7 ? _GEN_1315 : _GEN_1307; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1324 = _T_7 ? _GEN_1316 : _GEN_1308; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1325 = _T_7 ? _GEN_1317 : _GEN_1309; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1326 = _T_7 ? _GEN_1318 : _GEN_1310; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1327 = _T_7 ? _GEN_1319 : _GEN_1311; // @[MultiPortFifo.scala 98:34]
  wire  _T_24 = io_enq_3_ready & io_enq_3_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_1416 = _T_24 ? 3'h0 == _io_enq_3_ready_T_1 | _GEN_1320 : _GEN_1320; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1417 = _T_24 ? 3'h1 == _io_enq_3_ready_T_1 | _GEN_1321 : _GEN_1321; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1418 = _T_24 ? 3'h2 == _io_enq_3_ready_T_1 | _GEN_1322 : _GEN_1322; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1419 = _T_24 ? 3'h3 == _io_enq_3_ready_T_1 | _GEN_1323 : _GEN_1323; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1420 = _T_24 ? 3'h4 == _io_enq_3_ready_T_1 | _GEN_1324 : _GEN_1324; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1421 = _T_24 ? 3'h5 == _io_enq_3_ready_T_1 | _GEN_1325 : _GEN_1325; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1422 = _T_24 ? 3'h6 == _io_enq_3_ready_T_1 | _GEN_1326 : _GEN_1326; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1423 = _T_24 ? 3'h7 == _io_enq_3_ready_T_1 | _GEN_1327 : _GEN_1327; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1424 = 3'h0 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_1416; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1425 = 3'h1 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_1417; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1426 = 3'h2 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_1418; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1427 = 3'h3 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_1419; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1428 = 3'h4 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_1420; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1429 = 3'h5 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_1421; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1430 = 3'h6 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_1422; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1431 = 3'h7 == _io_deq_0_valid_T[2:0] ? 1'h0 : _GEN_1423; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1432 = _T_1 ? _GEN_1424 : _GEN_1416; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1433 = _T_1 ? _GEN_1425 : _GEN_1417; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1434 = _T_1 ? _GEN_1426 : _GEN_1418; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1435 = _T_1 ? _GEN_1427 : _GEN_1419; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1436 = _T_1 ? _GEN_1428 : _GEN_1420; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1437 = _T_1 ? _GEN_1429 : _GEN_1421; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1438 = _T_1 ? _GEN_1430 : _GEN_1422; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1439 = _T_1 ? _GEN_1431 : _GEN_1423; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1528 = _T_24 ? 3'h0 == _io_enq_3_ready_T_1 | _GEN_1432 : _GEN_1432; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1529 = _T_24 ? 3'h1 == _io_enq_3_ready_T_1 | _GEN_1433 : _GEN_1433; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1530 = _T_24 ? 3'h2 == _io_enq_3_ready_T_1 | _GEN_1434 : _GEN_1434; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1531 = _T_24 ? 3'h3 == _io_enq_3_ready_T_1 | _GEN_1435 : _GEN_1435; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1532 = _T_24 ? 3'h4 == _io_enq_3_ready_T_1 | _GEN_1436 : _GEN_1436; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1533 = _T_24 ? 3'h5 == _io_enq_3_ready_T_1 | _GEN_1437 : _GEN_1437; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1534 = _T_24 ? 3'h6 == _io_enq_3_ready_T_1 | _GEN_1438 : _GEN_1438; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1535 = _T_24 ? 3'h7 == _io_enq_3_ready_T_1 | _GEN_1439 : _GEN_1439; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1536 = 3'h0 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1528; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1537 = 3'h1 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1529; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1538 = 3'h2 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1530; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1539 = 3'h3 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1531; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1540 = 3'h4 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1532; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1541 = 3'h5 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1533; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1542 = 3'h6 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1534; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1543 = 3'h7 == _io_deq_1_valid_T_1 ? 1'h0 : _GEN_1535; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1544 = _T_3 ? _GEN_1536 : _GEN_1528; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1545 = _T_3 ? _GEN_1537 : _GEN_1529; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1546 = _T_3 ? _GEN_1538 : _GEN_1530; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1547 = _T_3 ? _GEN_1539 : _GEN_1531; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1548 = _T_3 ? _GEN_1540 : _GEN_1532; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1549 = _T_3 ? _GEN_1541 : _GEN_1533; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1550 = _T_3 ? _GEN_1542 : _GEN_1534; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1551 = _T_3 ? _GEN_1543 : _GEN_1535; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1640 = _T_24 ? 3'h0 == _io_enq_3_ready_T_1 | _GEN_1544 : _GEN_1544; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1641 = _T_24 ? 3'h1 == _io_enq_3_ready_T_1 | _GEN_1545 : _GEN_1545; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1642 = _T_24 ? 3'h2 == _io_enq_3_ready_T_1 | _GEN_1546 : _GEN_1546; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1643 = _T_24 ? 3'h3 == _io_enq_3_ready_T_1 | _GEN_1547 : _GEN_1547; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1644 = _T_24 ? 3'h4 == _io_enq_3_ready_T_1 | _GEN_1548 : _GEN_1548; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1645 = _T_24 ? 3'h5 == _io_enq_3_ready_T_1 | _GEN_1549 : _GEN_1549; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1646 = _T_24 ? 3'h6 == _io_enq_3_ready_T_1 | _GEN_1550 : _GEN_1550; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1647 = _T_24 ? 3'h7 == _io_enq_3_ready_T_1 | _GEN_1551 : _GEN_1551; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1648 = 3'h0 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1640; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1649 = 3'h1 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1641; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1650 = 3'h2 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1642; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1651 = 3'h3 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1643; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1652 = 3'h4 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1644; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1653 = 3'h5 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1645; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1654 = 3'h6 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1646; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1655 = 3'h7 == _io_deq_2_valid_T_1 ? 1'h0 : _GEN_1647; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_1656 = _T_5 ? _GEN_1648 : _GEN_1640; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1657 = _T_5 ? _GEN_1649 : _GEN_1641; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1658 = _T_5 ? _GEN_1650 : _GEN_1642; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1659 = _T_5 ? _GEN_1651 : _GEN_1643; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1660 = _T_5 ? _GEN_1652 : _GEN_1644; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1661 = _T_5 ? _GEN_1653 : _GEN_1645; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1662 = _T_5 ? _GEN_1654 : _GEN_1646; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1663 = _T_5 ? _GEN_1655 : _GEN_1647; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_1752 = _T_24 ? 3'h0 == _io_enq_3_ready_T_1 | _GEN_1656 : _GEN_1656; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1753 = _T_24 ? 3'h1 == _io_enq_3_ready_T_1 | _GEN_1657 : _GEN_1657; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1754 = _T_24 ? 3'h2 == _io_enq_3_ready_T_1 | _GEN_1658 : _GEN_1658; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1755 = _T_24 ? 3'h3 == _io_enq_3_ready_T_1 | _GEN_1659 : _GEN_1659; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1756 = _T_24 ? 3'h4 == _io_enq_3_ready_T_1 | _GEN_1660 : _GEN_1660; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1757 = _T_24 ? 3'h5 == _io_enq_3_ready_T_1 | _GEN_1661 : _GEN_1661; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1758 = _T_24 ? 3'h6 == _io_enq_3_ready_T_1 | _GEN_1662 : _GEN_1662; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_1759 = _T_24 ? 3'h7 == _io_enq_3_ready_T_1 | _GEN_1663 : _GEN_1663; // @[MultiPortFifo.scala 97:34]
  wire [1:0] _rd_ptr_T_1 = _T_3 ? 2'h2 : {{1'd0}, _T_1}; // @[Mux.scala 101:16]
  wire [1:0] _rd_ptr_T_2 = _T_5 ? 2'h3 : _rd_ptr_T_1; // @[Mux.scala 101:16]
  wire [2:0] _rd_ptr_T_3 = _T_7 ? 3'h4 : {{1'd0}, _rd_ptr_T_2}; // @[Mux.scala 101:16]
  wire [2:0] _rd_ptr_T_5 = rd_ptr + _rd_ptr_T_3; // @[MultiPortFifo.scala 106:26]
  wire [1:0] _wr_ptr_T_1 = _T_8 ? 2'h2 : {{1'd0}, _T}; // @[Mux.scala 101:16]
  wire [1:0] _wr_ptr_T_2 = _T_16 ? 2'h3 : _wr_ptr_T_1; // @[Mux.scala 101:16]
  wire [2:0] _wr_ptr_T_3 = _T_24 ? 3'h4 : {{1'd0}, _wr_ptr_T_2}; // @[Mux.scala 101:16]
  wire [2:0] _wr_ptr_T_5 = wr_ptr + _wr_ptr_T_3; // @[MultiPortFifo.scala 107:26]
  wire  _T_39 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_enq_0_ready = ~_GEN_7; // @[MultiPortFifo.scala 64:94]
  assign io_enq_1_ready = ~_GEN_15; // @[MultiPortFifo.scala 64:94]
  assign io_enq_2_ready = ~_GEN_23; // @[MultiPortFifo.scala 64:94]
  assign io_enq_3_ready = ~_GEN_31; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = 3'h7 == _io_deq_0_valid_T[2:0] ? buf_valid_7 : _GEN_38; // @[MultiPortFifo.scala 65:{94,94}]
  assign io_deq_1_valid = 3'h7 == _io_deq_1_valid_T_1 ? buf_valid_7 : _GEN_46; // @[MultiPortFifo.scala 65:{94,94}]
  assign io_deq_2_valid = 3'h7 == _io_deq_2_valid_T_1 ? buf_valid_7 : _GEN_54; // @[MultiPortFifo.scala 65:{94,94}]
  assign io_deq_3_valid = 3'h7 == _io_deq_3_valid_T_1 ? buf_valid_7 : _GEN_62; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h0 == _io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_1752;
      end
    end else begin
      buf_valid_0 <= _GEN_1752;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h1 == _io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_1753;
      end
    end else begin
      buf_valid_1 <= _GEN_1753;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h2 == _io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_2 <= _GEN_1754;
      end
    end else begin
      buf_valid_2 <= _GEN_1754;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h3 == _io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_3 <= _GEN_1755;
      end
    end else begin
      buf_valid_3 <= _GEN_1755;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_4 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_4 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h4 == _io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_4 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_4 <= _GEN_1756;
      end
    end else begin
      buf_valid_4 <= _GEN_1756;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_5 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_5 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h5 == _io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_5 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_5 <= _GEN_1757;
      end
    end else begin
      buf_valid_5 <= _GEN_1757;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_6 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_6 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h6 == _io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_6 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_6 <= _GEN_1758;
      end
    end else begin
      buf_valid_6 <= _GEN_1758;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_7 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_7 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h7 == _io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_7 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_7 <= _GEN_1759;
      end
    end else begin
      buf_valid_7 <= _GEN_1759;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 3'h0; // @[MultiPortFifo.scala 60:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      rd_ptr <= 3'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      rd_ptr <= _rd_ptr_T_5; // @[MultiPortFifo.scala 106:16]
    end
    if (reset) begin // @[MultiPortFifo.scala 61:27]
      wr_ptr <= 3'h0; // @[MultiPortFifo.scala 61:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      wr_ptr <= 3'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      wr_ptr <= _wr_ptr_T_5; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_1_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_1_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_1_valid & ~io_enq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_1_valid & ~io_enq_1_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_2_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_2_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_2_valid & ~io_enq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_2_valid & ~io_enq_1_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_2_valid & ~io_enq_2_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_2_valid & ~io_enq_2_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_3_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_3_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_3_valid & ~io_enq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_3_valid & ~io_enq_1_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_3_valid & ~io_enq_2_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_3_valid & ~io_enq_2_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_3_valid & ~io_enq_3_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_3_valid & ~io_enq_3_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_1_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_1_valid & ~io_deq_0_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_1_valid & ~io_deq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_1_valid & ~io_deq_1_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_2_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_2_valid & ~io_deq_0_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_2_valid & ~io_deq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_2_valid & ~io_deq_1_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_2_valid & ~io_deq_2_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_2_valid & ~io_deq_2_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_3_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_3_valid & ~io_deq_0_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_3_valid & ~io_deq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_3_valid & ~io_deq_1_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_3_valid & ~io_deq_2_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_3_valid & ~io_deq_2_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_39 & ~(~(io_deq_3_valid & ~io_deq_3_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_3_valid & ~io_deq_3_valid)) & _T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & _T_39 & ~_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T & (_T_8 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_16 & _T_39 & ~_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T & (_T_16 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_16 & _T_39 & ~_T_8) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_8 & (_T_16 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_24 & _T_39 & ~_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T & (_T_24 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_24 & _T_39 & ~_T_8) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_8 & (_T_24 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_24 & _T_39 & ~_T_16) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_16 & (_T_24 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3 & _T_39 & ~_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1 & (_T_3 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & _T_39 & ~_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1 & (_T_5 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & _T_39 & ~_T_3) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3 & (_T_5 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_7 & _T_39 & ~_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1 & (_T_7 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_7 & _T_39 & ~_T_3) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3 & (_T_7 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_7 & _T_39 & ~_T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_5 & (_T_7 & _T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  buf_valid_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  buf_valid_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  buf_valid_4 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  buf_valid_5 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  buf_valid_6 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  buf_valid_7 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  rd_ptr = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  wr_ptr = _RAND_9[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TagRAM(
  input         clock,
  input         io_addrr,
  input         io_addrw,
  input  [26:0] io_dataw,
  output [26:0] io_datar,
  input         io_enw,
  input         io_enr
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  reg [26:0] tagMem [0:1]; // @[CacheRAM.scala 152:27]
  wire  tagMem_io_datar_MPORT_en; // @[CacheRAM.scala 152:27]
  wire  tagMem_io_datar_MPORT_addr; // @[CacheRAM.scala 152:27]
  wire [26:0] tagMem_io_datar_MPORT_data; // @[CacheRAM.scala 152:27]
  wire [26:0] tagMem_MPORT_data; // @[CacheRAM.scala 152:27]
  wire  tagMem_MPORT_addr; // @[CacheRAM.scala 152:27]
  wire  tagMem_MPORT_mask; // @[CacheRAM.scala 152:27]
  wire  tagMem_MPORT_en; // @[CacheRAM.scala 152:27]
  reg  tagMem_io_datar_MPORT_en_pipe_0;
  reg  tagMem_io_datar_MPORT_addr_pipe_0;
  assign tagMem_io_datar_MPORT_en = tagMem_io_datar_MPORT_en_pipe_0;
  assign tagMem_io_datar_MPORT_addr = tagMem_io_datar_MPORT_addr_pipe_0;
  assign tagMem_io_datar_MPORT_data = tagMem[tagMem_io_datar_MPORT_addr]; // @[CacheRAM.scala 152:27]
  assign tagMem_MPORT_data = io_dataw;
  assign tagMem_MPORT_addr = io_addrw;
  assign tagMem_MPORT_mask = 1'h1;
  assign tagMem_MPORT_en = io_enw;
  assign io_datar = tagMem_io_datar_MPORT_data; // @[CacheRAM.scala 164:18 165:14]
  always @(posedge clock) begin
    if (tagMem_MPORT_en & tagMem_MPORT_mask) begin
      tagMem[tagMem_MPORT_addr] <= tagMem_MPORT_data; // @[CacheRAM.scala 152:27]
    end
    tagMem_io_datar_MPORT_en_pipe_0 <= io_enr;
    if (io_enr) begin
      tagMem_io_datar_MPORT_addr_pipe_0 <= io_addrr;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    tagMem[initvar] = _RAND_0[26:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  tagMem_io_datar_MPORT_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  tagMem_io_datar_MPORT_addr_pipe_0 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IF2(
  input         clock,
  input         reset,
  input         io_if2_req_bits_isActive_0,
  input         io_if2_req_bits_isActive_1,
  input         io_if2_req_bits_isActive_2,
  input         io_if2_req_bits_isActive_3,
  input         io_if2_resp_0_ready,
  input         io_if2_resp_1_ready,
  input         io_if2_resp_2_ready,
  input         io_if2_resp_3_ready,
  input         io_mmu_if_valid,
  input  [63:0] io_mmu_if_bits_paddr,
  input         io_mmu_if_bits_is_paging_fault,
  input         io_mmu_if_bits_is_access_fault,
  input         io_icache_get_ready,
  output        io_icache_get_valid,
  output        io_icache_access_ready,
  input         io_icache_access_valid,
  input  [2:0]  io_icache_access_bits_opcode,
  input  [2:0]  io_icache_access_bits_size,
  input         io_flush,
  input         io_ifence
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  ibuf_clock; // @[IF2.scala 73:20]
  wire  ibuf_reset; // @[IF2.scala 73:20]
  wire  ibuf_io_enq_0_ready; // @[IF2.scala 73:20]
  wire  ibuf_io_enq_0_valid; // @[IF2.scala 73:20]
  wire  ibuf_io_enq_1_ready; // @[IF2.scala 73:20]
  wire  ibuf_io_enq_1_valid; // @[IF2.scala 73:20]
  wire  ibuf_io_enq_2_ready; // @[IF2.scala 73:20]
  wire  ibuf_io_enq_2_valid; // @[IF2.scala 73:20]
  wire  ibuf_io_enq_3_ready; // @[IF2.scala 73:20]
  wire  ibuf_io_enq_3_valid; // @[IF2.scala 73:20]
  wire  ibuf_io_deq_0_ready; // @[IF2.scala 73:20]
  wire  ibuf_io_deq_0_valid; // @[IF2.scala 73:20]
  wire  ibuf_io_deq_1_ready; // @[IF2.scala 73:20]
  wire  ibuf_io_deq_1_valid; // @[IF2.scala 73:20]
  wire  ibuf_io_deq_2_ready; // @[IF2.scala 73:20]
  wire  ibuf_io_deq_2_valid; // @[IF2.scala 73:20]
  wire  ibuf_io_deq_3_ready; // @[IF2.scala 73:20]
  wire  ibuf_io_deq_3_valid; // @[IF2.scala 73:20]
  wire  ibuf_io_flush; // @[IF2.scala 73:20]
  wire  tagRAM_0_clock; // @[IF2.scala 183:54]
  wire  tagRAM_0_io_addrr; // @[IF2.scala 183:54]
  wire  tagRAM_0_io_addrw; // @[IF2.scala 183:54]
  wire [26:0] tagRAM_0_io_dataw; // @[IF2.scala 183:54]
  wire [26:0] tagRAM_0_io_datar; // @[IF2.scala 183:54]
  wire  tagRAM_0_io_enw; // @[IF2.scala 183:54]
  wire  tagRAM_0_io_enr; // @[IF2.scala 183:54]
  wire  _T = io_icache_access_ready & io_icache_access_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _beats1_decode_T_1 = 11'hf << io_icache_access_bits_size; // @[package.scala 234:77]
  wire [3:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  beats1_decode = _beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  beats1_opdata = io_icache_access_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  beats1 = beats1_opdata & beats1_decode; // @[Edges.scala 220:14]
  reg  counter; // @[Edges.scala 228:27]
  wire  counter1 = counter - 1'h1; // @[Edges.scala 229:28]
  wire  first = ~counter; // @[Edges.scala 230:25]
  wire  last = counter | ~beats1; // @[Edges.scala 231:37]
  wire  is_trans_done = last & _T; // @[Edges.scala 232:22]
  reg  kill_trans; // @[IF2.scala 71:27]
  wire  cl_sel = io_mmu_if_bits_paddr[4]; // @[IF2.scala 79:36]
  wire [26:0] tag_sel = io_mmu_if_bits_paddr[31:5]; // @[IF2.scala 80:37]
  reg  is_valid_1_0; // @[IF2.scala 180:25]
  reg  is_valid_0_0; // @[IF2.scala 180:25]
  wire  _GEN_4 = cl_sel ? is_valid_1_0 : is_valid_0_0; // @[IF2.scala 189:{42,42}]
  wire  res_0 = tagRAM_0_io_datar == tag_sel & _GEN_4; // @[IF2.scala 189:42]
  wire  is_hit = |res_0; // @[IF2.scala 86:33]
  reg [3:0] icache_state_qout; // @[IF2.scala 98:34]
  reg  fault_lock; // @[IF2.scala 100:27]
  wire  is_access_fault = io_mmu_if_valid & io_mmu_if_bits_is_access_fault; // @[IF2.scala 117:38]
  wire  is_paging_fault = io_mmu_if_valid & io_mmu_if_bits_is_paging_fault; // @[IF2.scala 118:38]
  wire  _T_1 = io_mmu_if_bits_is_access_fault | io_mmu_if_bits_is_paging_fault; // @[MMU.scala 77:34]
  wire  _T_3 = ~io_flush; // @[IF2.scala 121:58]
  wire  _T_5 = ibuf_io_enq_0_ready & ibuf_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_1 = io_mmu_if_valid & _T_1 & ~io_flush & _T_5 | fault_lock; // @[IF2.scala 121:105 100:27 121:92]
  wire  _T_10 = ~reset; // @[IF2.scala 123:9]
  wire  _icache_state_dnxt_T = icache_state_qout == 4'h0; // @[IF2.scala 133:26]
  wire  _icache_state_dnxt_T_7 = ~fault_lock; // @[IF2.scala 134:102]
  wire  _icache_state_dnxt_T_8 = io_mmu_if_valid & ~_T_1 & _T_3 & ibuf_io_enq_3_ready & ~fault_lock; // @[IF2.scala 134:100]
  wire  _icache_state_dnxt_T_10 = icache_state_qout == 4'h1; // @[IF2.scala 135:26]
  wire  _icache_state_dnxt_T_11 = io_icache_get_ready & io_icache_get_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _icache_state_dnxt_T_12 = _icache_state_dnxt_T_11 ? 2'h2 : 2'h1; // @[IF2.scala 138:26]
  wire [1:0] _icache_state_dnxt_T_13 = is_hit ? 2'h0 : _icache_state_dnxt_T_12; // @[IF2.scala 137:14]
  wire [1:0] _icache_state_dnxt_T_14 = io_flush ? 2'h0 : _icache_state_dnxt_T_13; // @[IF2.scala 136:12]
  wire  _icache_state_dnxt_T_15 = icache_state_qout == 4'h2; // @[IF2.scala 139:26]
  wire [1:0] _icache_state_dnxt_T_16 = is_trans_done ? 2'h0 : 2'h2; // @[IF2.scala 140:14]
  wire  _icache_state_dnxt_T_17 = _icache_state_dnxt_T & _icache_state_dnxt_T_8; // @[Mux.scala 27:73]
  wire [1:0] _icache_state_dnxt_T_18 = _icache_state_dnxt_T_10 ? _icache_state_dnxt_T_14 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _icache_state_dnxt_T_19 = _icache_state_dnxt_T_15 ? _icache_state_dnxt_T_16 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_11 = {{1'd0}, _icache_state_dnxt_T_17}; // @[Mux.scala 27:73]
  wire [1:0] _icache_state_dnxt_T_20 = _GEN_11 | _icache_state_dnxt_T_18; // @[Mux.scala 27:73]
  wire [1:0] _icache_state_dnxt_T_21 = _icache_state_dnxt_T_20 | _icache_state_dnxt_T_19; // @[Mux.scala 27:73]
  wire [3:0] icache_state_dnxt = {{2'd0}, _icache_state_dnxt_T_21}; // @[IF2.scala 131:21 97:31]
  wire  _tagRAM_0_io_enw_T_1 = icache_state_dnxt == 4'h0; // @[IF2.scala 245:73]
  wire  _tagRAM_0_io_enw_T_5 = ~kill_trans; // @[IF2.scala 245:103]
  wire  _tagRAM_0_io_enw_T_8 = _icache_state_dnxt_T_15 & icache_state_dnxt == 4'h0 & ~kill_trans & _T_3; // @[IF2.scala 245:115]
  wire  _GEN_5 = ~cl_sel | is_valid_0_0; // @[IF2.scala 180:25 266:{30,30}]
  wire  _GEN_6 = cl_sel | is_valid_1_0; // @[IF2.scala 180:25 266:{30,30}]
  reg [63:0] REG; // @[IF2.scala 300:21]
  reg  REG_1; // @[IF2.scala 300:108]
  reg  REG_2; // @[IF2.scala 300:131]
  wire  _ibuf_io_enq_0_valid_T_1 = _tagRAM_0_io_enw_T_5 & io_mmu_if_valid; // @[IF2.scala 361:18]
  wire  _ibuf_io_enq_0_valid_T_2 = icache_state_qout != 4'h0; // @[IF2.scala 361:56]
  wire  _ibuf_io_enq_0_valid_T_6 = _tagRAM_0_io_enw_T_5 & io_mmu_if_valid & icache_state_qout != 4'h0 &
    _tagRAM_0_io_enw_T_1 & ibuf_io_enq_3_ready; // @[IF2.scala 361:92]
  wire  _ibuf_io_enq_0_valid_T_16 = _ibuf_io_enq_0_valid_T_1 & _T_1 & _icache_state_dnxt_T_7; // @[IF2.scala 362:62]
  wire  _GEN_20 = _tagRAM_0_io_enw_T_1 | _icache_state_dnxt_T ? 1'h0 : kill_trans; // @[IF2.scala 373:72 374:16 71:27]
  wire  _GEN_21 = io_flush & _ibuf_io_enq_0_valid_T_2 | _GEN_20; // @[IF2.scala 371:48 372:16]
  MultiPortFifo_in4_out4 ibuf ( // @[IF2.scala 73:20]
    .clock(ibuf_clock),
    .reset(ibuf_reset),
    .io_enq_0_ready(ibuf_io_enq_0_ready),
    .io_enq_0_valid(ibuf_io_enq_0_valid),
    .io_enq_1_ready(ibuf_io_enq_1_ready),
    .io_enq_1_valid(ibuf_io_enq_1_valid),
    .io_enq_2_ready(ibuf_io_enq_2_ready),
    .io_enq_2_valid(ibuf_io_enq_2_valid),
    .io_enq_3_ready(ibuf_io_enq_3_ready),
    .io_enq_3_valid(ibuf_io_enq_3_valid),
    .io_deq_0_ready(ibuf_io_deq_0_ready),
    .io_deq_0_valid(ibuf_io_deq_0_valid),
    .io_deq_1_ready(ibuf_io_deq_1_ready),
    .io_deq_1_valid(ibuf_io_deq_1_valid),
    .io_deq_2_ready(ibuf_io_deq_2_ready),
    .io_deq_2_valid(ibuf_io_deq_2_valid),
    .io_deq_3_ready(ibuf_io_deq_3_ready),
    .io_deq_3_valid(ibuf_io_deq_3_valid),
    .io_flush(ibuf_io_flush)
  );
  TagRAM tagRAM_0 ( // @[IF2.scala 183:54]
    .clock(tagRAM_0_clock),
    .io_addrr(tagRAM_0_io_addrr),
    .io_addrw(tagRAM_0_io_addrw),
    .io_dataw(tagRAM_0_io_dataw),
    .io_datar(tagRAM_0_io_datar),
    .io_enw(tagRAM_0_io_enw),
    .io_enr(tagRAM_0_io_enr)
  );
  assign io_icache_get_valid = _icache_state_dnxt_T_10 & ~is_hit & _T_3; // @[IF2.scala 282:62]
  assign io_icache_access_ready = 1'h1; // @[IF2.scala 290:26]
  assign ibuf_clock = clock;
  assign ibuf_reset = reset;
  assign ibuf_io_enq_0_valid = _tagRAM_0_io_enw_T_5 & io_mmu_if_valid & icache_state_qout != 4'h0 & _tagRAM_0_io_enw_T_1
     & ibuf_io_enq_3_ready & io_if2_req_bits_isActive_0 | _ibuf_io_enq_0_valid_T_16; // @[IF2.scala 361:222]
  assign ibuf_io_enq_1_valid = _ibuf_io_enq_0_valid_T_6 & io_mmu_if_bits_paddr[2:1] <= 2'h2 & io_if2_req_bits_isActive_1
    ; // @[IF2.scala 365:217]
  assign ibuf_io_enq_2_valid = _ibuf_io_enq_0_valid_T_6 & io_mmu_if_bits_paddr[2:1] <= 2'h1 & io_if2_req_bits_isActive_2
    ; // @[IF2.scala 365:217]
  assign ibuf_io_enq_3_valid = _ibuf_io_enq_0_valid_T_6 & io_mmu_if_bits_paddr[2:1] <= 2'h0 & io_if2_req_bits_isActive_3
    ; // @[IF2.scala 365:217]
  assign ibuf_io_deq_0_ready = io_if2_resp_0_ready; // @[IF2.scala 75:15]
  assign ibuf_io_deq_1_ready = io_if2_resp_1_ready; // @[IF2.scala 75:15]
  assign ibuf_io_deq_2_ready = io_if2_resp_2_ready; // @[IF2.scala 75:15]
  assign ibuf_io_deq_3_ready = io_if2_resp_3_ready; // @[IF2.scala 75:15]
  assign ibuf_io_flush = io_flush; // @[IF2.scala 74:17]
  assign tagRAM_0_clock = clock;
  assign tagRAM_0_io_addrr = io_mmu_if_bits_paddr[4]; // @[IF2.scala 238:47]
  assign tagRAM_0_io_addrw = io_mmu_if_bits_paddr[4]; // @[IF2.scala 239:47]
  assign tagRAM_0_io_dataw = io_mmu_if_bits_paddr[31:5]; // @[IF2.scala 80:37]
  assign tagRAM_0_io_enw = _icache_state_dnxt_T_15 & icache_state_dnxt == 4'h0 & ~kill_trans & _T_3; // @[IF2.scala 245:115]
  assign tagRAM_0_io_enr = _icache_state_dnxt_T | _icache_state_dnxt_T_10; // @[IF2.scala 242:52]
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        counter <= beats1;
      end else begin
        counter <= counter1;
      end
    end
    if (reset) begin // @[IF2.scala 71:27]
      kill_trans <= 1'h0; // @[IF2.scala 71:27]
    end else begin
      kill_trans <= _GEN_21;
    end
    if (reset) begin // @[IF2.scala 180:25]
      is_valid_1_0 <= 1'h0; // @[IF2.scala 180:25]
    end else if (io_ifence) begin // @[IF2.scala 270:23]
      is_valid_1_0 <= 1'h0; // @[IF2.scala 271:23]
    end else if (_tagRAM_0_io_enw_T_8) begin // @[IF2.scala 265:91]
      is_valid_1_0 <= _GEN_6;
    end
    if (reset) begin // @[IF2.scala 180:25]
      is_valid_0_0 <= 1'h0; // @[IF2.scala 180:25]
    end else if (io_ifence) begin // @[IF2.scala 270:23]
      is_valid_0_0 <= 1'h0; // @[IF2.scala 271:23]
    end else if (_tagRAM_0_io_enw_T_8) begin // @[IF2.scala 265:91]
      is_valid_0_0 <= _GEN_5;
    end
    if (reset) begin // @[IF2.scala 98:34]
      icache_state_qout <= 4'h0; // @[IF2.scala 98:34]
    end else begin
      icache_state_qout <= icache_state_dnxt; // @[IF2.scala 98:34]
    end
    if (reset) begin // @[IF2.scala 100:27]
      fault_lock <= 1'h0; // @[IF2.scala 100:27]
    end else if (io_flush) begin // @[IF2.scala 120:20]
      fault_lock <= 1'h0; // @[IF2.scala 120:33]
    end else begin
      fault_lock <= _GEN_1;
    end
    REG <= io_mmu_if_bits_paddr; // @[IF2.scala 300:21]
    REG_1 <= kill_trans; // @[IF2.scala 300:108]
    REG_2 <= io_flush; // @[IF2.scala 300:131]
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(is_access_fault & is_paging_fault))) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IF2.scala:123 assert( ~(is_access_fault & is_paging_fault) )\n"
            ); // @[IF2.scala 123:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(is_access_fault & is_paging_fault)) & ~reset) begin
          $fatal; // @[IF2.scala 123:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_icache_state_dnxt_T_10 & _T_10)) begin
          $fatal; // @[IF2.scala 193:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_10 & ~(~(REG != io_mmu_if_bits_paddr & _icache_state_dnxt_T_15 & ~REG_1 & ~REG_2))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, req paddr cannot change without flush.\n    at IF2.scala:300 assert( ~((RegNext(io.mmu_if.bits.paddr) =/= io.mmu_if.bits.paddr) & icache_state_qout === 2.U & ~RegNext(kill_trans) & ~RegNext(io.flush)), \"Assert Failed, req paddr cannot change without flush.\" )\n"
            ); // @[IF2.scala 300:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(REG != io_mmu_if_bits_paddr & _icache_state_dnxt_T_15 & ~REG_1 & ~REG_2)) & _T_10) begin
          $fatal; // @[IF2.scala 300:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_ifence & _T_10 & _T_3) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IF2.scala:377 when( io.ifence ) { assert(io.flush) }\n"); // @[IF2.scala 377:29]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~io_flush & (io_ifence & _T_10)) begin
          $fatal; // @[IF2.scala 377:29]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  kill_trans = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  is_valid_1_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  is_valid_0_0 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  icache_state_qout = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  fault_lock = _RAND_5[0:0];
  _RAND_6 = {2{`RANDOM}};
  REG = _RAND_6[63:0];
  _RAND_7 = {1{`RANDOM}};
  REG_1 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  REG_2 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RePort(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  output  io_enq_1_ready,
  input   io_enq_1_valid,
  output  io_enq_2_ready,
  input   io_enq_2_valid,
  output  io_enq_3_ready,
  input   io_enq_3_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_deq_1_ready,
  output  io_deq_1_valid,
  input   io_deq_2_ready,
  output  io_deq_2_valid,
  input   io_deq_3_ready,
  output  io_deq_3_valid
);
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = io_enq_1_ready & io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  _T_2 = io_enq_2_ready & io_enq_2_valid; // @[Decoupled.scala 52:35]
  wire  _T_3 = io_enq_3_ready & io_enq_3_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _T_4 = _T + _T_1; // @[Bitwise.scala 51:90]
  wire [1:0] _T_6 = _T_2 + _T_3; // @[Bitwise.scala 51:90]
  wire [2:0] _T_8 = _T_4 + _T_6; // @[Bitwise.scala 51:90]
  wire  _T_10 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_11 = io_deq_1_ready & io_deq_1_valid; // @[Decoupled.scala 52:35]
  wire  _T_12 = io_deq_2_ready & io_deq_2_valid; // @[Decoupled.scala 52:35]
  wire  _T_13 = io_deq_3_ready & io_deq_3_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _T_14 = _T_10 + _T_11; // @[Bitwise.scala 51:90]
  wire [1:0] _T_16 = _T_12 + _T_13; // @[Bitwise.scala 51:90]
  wire [2:0] _T_18 = _T_14 + _T_16; // @[Bitwise.scala 51:90]
  assign io_enq_0_ready = io_deq_0_ready; // @[RePort.scala 80:69]
  assign io_enq_1_ready = io_deq_1_ready; // @[RePort.scala 80:91]
  assign io_enq_2_ready = io_deq_2_ready; // @[RePort.scala 80:91]
  assign io_enq_3_ready = io_deq_3_ready; // @[RePort.scala 80:91]
  assign io_deq_0_valid = _T_8 > 3'h0; // @[RePort.scala 79:81]
  assign io_deq_1_valid = _T_8 > 3'h1; // @[RePort.scala 79:81]
  assign io_deq_2_valid = _T_8 > 3'h2; // @[RePort.scala 79:81]
  assign io_deq_3_valid = _T_8 > 3'h3; // @[RePort.scala 79:81]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_8 == _T_18)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_8 == _T_18) & ~reset) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module Queue(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_9 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_9 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module BTB(
  input   clock,
  input   reset,
  output  io_req_ready,
  input   io_req_valid,
  input   io_resp_ready,
  output  io_resp_valid,
  output  io_isReady
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  bypassFifo_clock; // @[BTB.scala 41:26]
  wire  bypassFifo_reset; // @[BTB.scala 41:26]
  wire  bypassFifo_io_enq_ready; // @[BTB.scala 41:26]
  wire  bypassFifo_io_enq_valid; // @[BTB.scala 41:26]
  wire  bypassFifo_io_deq_ready; // @[BTB.scala 41:26]
  wire  bypassFifo_io_deq_valid; // @[BTB.scala 41:26]
  reg  por_reset; // @[BTB.scala 46:28]
  reg [1:0] reset_cl; // @[Counter.scala 61:40]
  wire  wrap_wrap = reset_cl == 2'h3; // @[Counter.scala 73:24]
  wire [1:0] _wrap_value_T_1 = reset_cl + 2'h1; // @[Counter.scala 77:24]
  wire  reset_end = por_reset & wrap_wrap; // @[Counter.scala 136:24 137:12]
  wire  _GEN_4 = reset_end ? 1'h0 : por_reset; // @[BTB.scala 48:23 46:28 48:35]
  reg  bypassFifo_io_enq_valid_REG; // @[BTB.scala 74:37]
  Queue bypassFifo ( // @[BTB.scala 41:26]
    .clock(bypassFifo_clock),
    .reset(bypassFifo_reset),
    .io_enq_ready(bypassFifo_io_enq_ready),
    .io_enq_valid(bypassFifo_io_enq_valid),
    .io_deq_ready(bypassFifo_io_deq_ready),
    .io_deq_valid(bypassFifo_io_deq_valid)
  );
  assign io_req_ready = bypassFifo_io_enq_ready; // @[BTB.scala 75:16]
  assign io_resp_valid = bypassFifo_io_deq_valid; // @[BTB.scala 77:17]
  assign io_isReady = ~por_reset; // @[BTB.scala 49:19]
  assign bypassFifo_clock = clock;
  assign bypassFifo_reset = reset;
  assign bypassFifo_io_enq_valid = bypassFifo_io_enq_valid_REG; // @[BTB.scala 74:27]
  assign bypassFifo_io_deq_ready = io_resp_ready; // @[BTB.scala 78:27]
  always @(posedge clock) begin
    por_reset <= reset | _GEN_4; // @[BTB.scala 46:{28,28}]
    if (reset) begin // @[Counter.scala 61:40]
      reset_cl <= 2'h0; // @[Counter.scala 61:40]
    end else if (por_reset) begin // @[Counter.scala 136:24]
      reset_cl <= _wrap_value_T_1; // @[Counter.scala 77:15]
    end
    bypassFifo_io_enq_valid_REG <= io_req_ready & io_req_valid; // @[Decoupled.scala 52:35]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  por_reset = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  reset_cl = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  bypassFifo_io_enq_valid_REG = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_1(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_10 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_10 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module BIM(
  input   clock,
  input   reset,
  output  io_req_ready,
  input   io_req_valid,
  input   io_resp_ready,
  output  io_resp_valid,
  output  io_isReady
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  bypassFifo_clock; // @[BIM.scala 87:26]
  wire  bypassFifo_reset; // @[BIM.scala 87:26]
  wire  bypassFifo_io_enq_ready; // @[BIM.scala 87:26]
  wire  bypassFifo_io_enq_valid; // @[BIM.scala 87:26]
  wire  bypassFifo_io_deq_ready; // @[BIM.scala 87:26]
  wire  bypassFifo_io_deq_valid; // @[BIM.scala 87:26]
  reg  por_reset; // @[BIM.scala 37:26]
  reg [2:0] reset_cl; // @[Counter.scala 61:40]
  wire  wrap_wrap = reset_cl == 3'h7; // @[Counter.scala 73:24]
  wire [2:0] _wrap_value_T_1 = reset_cl + 3'h1; // @[Counter.scala 77:24]
  wire  reset_end = por_reset & wrap_wrap; // @[Counter.scala 136:24 137:12]
  wire  _GEN_4 = reset_end ? 1'h0 : por_reset; // @[BIM.scala 39:21 37:26 39:33]
  reg  bypassFifo_io_enq_valid_REG; // @[BIM.scala 89:37]
  Queue_1 bypassFifo ( // @[BIM.scala 87:26]
    .clock(bypassFifo_clock),
    .reset(bypassFifo_reset),
    .io_enq_ready(bypassFifo_io_enq_ready),
    .io_enq_valid(bypassFifo_io_enq_valid),
    .io_deq_ready(bypassFifo_io_deq_ready),
    .io_deq_valid(bypassFifo_io_deq_valid)
  );
  assign io_req_ready = bypassFifo_io_enq_ready; // @[BIM.scala 89:161]
  assign io_resp_valid = bypassFifo_io_deq_valid; // @[BIM.scala 90:17]
  assign io_isReady = ~por_reset; // @[BIM.scala 40:17]
  assign bypassFifo_clock = clock;
  assign bypassFifo_reset = reset;
  assign bypassFifo_io_enq_valid = bypassFifo_io_enq_valid_REG; // @[BIM.scala 89:27]
  assign bypassFifo_io_deq_ready = io_resp_ready; // @[BIM.scala 90:167]
  always @(posedge clock) begin
    por_reset <= reset | _GEN_4; // @[BIM.scala 37:{26,26}]
    if (reset) begin // @[Counter.scala 61:40]
      reset_cl <= 3'h0; // @[Counter.scala 61:40]
    end else if (por_reset) begin // @[Counter.scala 136:24]
      reset_cl <= _wrap_value_T_1; // @[Counter.scala 77:15]
    end
    bypassFifo_io_enq_valid_REG <= io_req_ready & io_req_valid; // @[Decoupled.scala 52:35]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  por_reset = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  reset_cl = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  bypassFifo_io_enq_valid_REG = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MultiPortFifo_in1_out1(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = _io_enq_0_ready_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_6 = _T ? ~_io_enq_0_ready_T[0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_7 = _T ? _io_enq_0_ready_T[0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_9 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_enq_0_ready = ~_GEN_1; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = _io_deq_0_valid_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_6;
      end
    end else begin
      buf_valid_0 <= _GEN_6;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_7;
      end
    end else begin
      buf_valid_1 <= _GEN_7;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      rd_ptr <= rd_ptr + _T_1; // @[MultiPortFifo.scala 106:16]
    end
    if (reset) begin // @[MultiPortFifo.scala 61:27]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      wr_ptr <= wr_ptr + _T; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rd_ptr = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wr_ptr = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RePort_1(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  assign io_enq_0_ready = io_deq_0_ready; // @[RePort.scala 80:69]
  assign io_deq_0_valid = _T > 1'h0; // @[RePort.scala 79:81]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T == _T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T == _T_1) & ~reset) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module ZipPort(
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  output  io_enq_1_ready,
  input   io_enq_1_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
  assign io_enq_0_ready = ~io_enq_0_valid & io_enq_1_valid ? 1'h0 : io_deq_0_ready; // @[RePort.scala 235:64 242:23]
  assign io_enq_1_ready = ~io_enq_0_valid & io_enq_1_valid & io_deq_0_ready; // @[RePort.scala 235:64 243:23]
  assign io_deq_0_valid = ~io_enq_0_valid & io_enq_1_valid | io_enq_0_valid; // @[RePort.scala 235:64 236:23]
endmodule
module MultiPortFifo_in1_out1_1(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_flush
);
  wire  fifo_clock; // @[MultiPortFifo.scala 124:24]
  wire  fifo_reset; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_enq_0_ready; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_enq_0_valid; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_deq_0_ready; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_deq_0_valid; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_flush; // @[MultiPortFifo.scala 124:24]
  wire  rePortIn_clock; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_reset; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_enq_0_ready; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_enq_0_valid; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_deq_0_ready; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_deq_0_valid; // @[MultiPortFifo.scala 125:28]
  wire  zipPort_io_enq_0_ready; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_enq_0_valid; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_enq_1_ready; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_enq_1_valid; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_deq_0_ready; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_deq_0_valid; // @[MultiPortFifo.scala 126:27]
  wire  _T = zipPort_io_enq_1_ready & zipPort_io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  _T_8 = ~reset; // @[MultiPortFifo.scala 161:13]
  MultiPortFifo_in1_out1 fifo ( // @[MultiPortFifo.scala 124:24]
    .clock(fifo_clock),
    .reset(fifo_reset),
    .io_enq_0_ready(fifo_io_enq_0_ready),
    .io_enq_0_valid(fifo_io_enq_0_valid),
    .io_deq_0_ready(fifo_io_deq_0_ready),
    .io_deq_0_valid(fifo_io_deq_0_valid),
    .io_flush(fifo_io_flush)
  );
  RePort_1 rePortIn ( // @[MultiPortFifo.scala 125:28]
    .clock(rePortIn_clock),
    .reset(rePortIn_reset),
    .io_enq_0_ready(rePortIn_io_enq_0_ready),
    .io_enq_0_valid(rePortIn_io_enq_0_valid),
    .io_deq_0_ready(rePortIn_io_deq_0_ready),
    .io_deq_0_valid(rePortIn_io_deq_0_valid)
  );
  ZipPort zipPort ( // @[MultiPortFifo.scala 126:27]
    .io_enq_0_ready(zipPort_io_enq_0_ready),
    .io_enq_0_valid(zipPort_io_enq_0_valid),
    .io_enq_1_ready(zipPort_io_enq_1_ready),
    .io_enq_1_valid(zipPort_io_enq_1_valid),
    .io_deq_0_ready(zipPort_io_deq_0_ready),
    .io_deq_0_valid(zipPort_io_deq_0_valid)
  );
  assign io_enq_0_ready = rePortIn_io_enq_0_ready; // @[MultiPortFifo.scala 128:23]
  assign io_deq_0_valid = zipPort_io_deq_0_valid; // @[MultiPortFifo.scala 142:27]
  assign fifo_clock = clock;
  assign fifo_reset = reset;
  assign fifo_io_enq_0_valid = rePortIn_io_deq_0_valid; // @[MultiPortFifo.scala 129:23]
  assign fifo_io_deq_0_ready = zipPort_io_enq_0_ready; // @[MultiPortFifo.scala 132:27]
  assign fifo_io_flush = io_flush; // @[MultiPortFifo.scala 148:21]
  assign rePortIn_clock = clock;
  assign rePortIn_reset = reset;
  assign rePortIn_io_enq_0_valid = _T ? 1'h0 : io_enq_0_valid; // @[MultiPortFifo.scala 128:23 151:44 152:36]
  assign rePortIn_io_deq_0_ready = fifo_io_enq_0_ready; // @[MultiPortFifo.scala 129:23]
  assign zipPort_io_enq_0_valid = fifo_io_deq_0_valid; // @[MultiPortFifo.scala 132:27]
  assign zipPort_io_enq_1_valid = io_enq_0_valid; // @[MultiPortFifo.scala 136:33]
  assign zipPort_io_deq_0_ready = io_deq_0_ready; // @[MultiPortFifo.scala 142:27]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_8) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module MultiPortFifo_in1_out1_2(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = _io_enq_0_ready_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_6 = _T ? ~_io_enq_0_ready_T[0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_7 = _T ? _io_enq_0_ready_T[0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_9 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_enq_0_ready = ~_GEN_1; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = _io_deq_0_valid_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_6;
      end
    end else begin
      buf_valid_0 <= _GEN_6;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_7;
      end
    end else begin
      buf_valid_1 <= _GEN_7;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      rd_ptr <= rd_ptr + _T_1; // @[MultiPortFifo.scala 106:16]
    end
    if (reset) begin // @[MultiPortFifo.scala 61:27]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      wr_ptr <= wr_ptr + _T; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rd_ptr = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wr_ptr = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RePort_2(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  assign io_enq_0_ready = io_deq_0_ready; // @[RePort.scala 80:69]
  assign io_deq_0_valid = _T > 1'h0; // @[RePort.scala 79:81]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T == _T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T == _T_1) & ~reset) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module ZipPort_1(
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  output  io_enq_1_ready,
  input   io_enq_1_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
  assign io_enq_0_ready = ~io_enq_0_valid & io_enq_1_valid ? 1'h0 : io_deq_0_ready; // @[RePort.scala 235:64 242:23]
  assign io_enq_1_ready = ~io_enq_0_valid & io_enq_1_valid & io_deq_0_ready; // @[RePort.scala 235:64 243:23]
  assign io_deq_0_valid = ~io_enq_0_valid & io_enq_1_valid | io_enq_0_valid; // @[RePort.scala 235:64 236:23]
endmodule
module MultiPortFifo_in1_out1_3(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_flush
);
  wire  fifo_clock; // @[MultiPortFifo.scala 124:24]
  wire  fifo_reset; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_enq_0_ready; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_enq_0_valid; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_deq_0_ready; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_deq_0_valid; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_flush; // @[MultiPortFifo.scala 124:24]
  wire  rePortIn_clock; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_reset; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_enq_0_ready; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_enq_0_valid; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_deq_0_ready; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_deq_0_valid; // @[MultiPortFifo.scala 125:28]
  wire  zipPort_io_enq_0_ready; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_enq_0_valid; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_enq_1_ready; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_enq_1_valid; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_deq_0_ready; // @[MultiPortFifo.scala 126:27]
  wire  zipPort_io_deq_0_valid; // @[MultiPortFifo.scala 126:27]
  wire  _T = zipPort_io_enq_1_ready & zipPort_io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  _T_8 = ~reset; // @[MultiPortFifo.scala 161:13]
  MultiPortFifo_in1_out1_2 fifo ( // @[MultiPortFifo.scala 124:24]
    .clock(fifo_clock),
    .reset(fifo_reset),
    .io_enq_0_ready(fifo_io_enq_0_ready),
    .io_enq_0_valid(fifo_io_enq_0_valid),
    .io_deq_0_ready(fifo_io_deq_0_ready),
    .io_deq_0_valid(fifo_io_deq_0_valid),
    .io_flush(fifo_io_flush)
  );
  RePort_2 rePortIn ( // @[MultiPortFifo.scala 125:28]
    .clock(rePortIn_clock),
    .reset(rePortIn_reset),
    .io_enq_0_ready(rePortIn_io_enq_0_ready),
    .io_enq_0_valid(rePortIn_io_enq_0_valid),
    .io_deq_0_ready(rePortIn_io_deq_0_ready),
    .io_deq_0_valid(rePortIn_io_deq_0_valid)
  );
  ZipPort_1 zipPort ( // @[MultiPortFifo.scala 126:27]
    .io_enq_0_ready(zipPort_io_enq_0_ready),
    .io_enq_0_valid(zipPort_io_enq_0_valid),
    .io_enq_1_ready(zipPort_io_enq_1_ready),
    .io_enq_1_valid(zipPort_io_enq_1_valid),
    .io_deq_0_ready(zipPort_io_deq_0_ready),
    .io_deq_0_valid(zipPort_io_deq_0_valid)
  );
  assign io_enq_0_ready = rePortIn_io_enq_0_ready; // @[MultiPortFifo.scala 128:23]
  assign io_deq_0_valid = zipPort_io_deq_0_valid; // @[MultiPortFifo.scala 142:27]
  assign fifo_clock = clock;
  assign fifo_reset = reset;
  assign fifo_io_enq_0_valid = rePortIn_io_deq_0_valid; // @[MultiPortFifo.scala 129:23]
  assign fifo_io_deq_0_ready = zipPort_io_enq_0_ready; // @[MultiPortFifo.scala 132:27]
  assign fifo_io_flush = io_flush; // @[MultiPortFifo.scala 148:21]
  assign rePortIn_clock = clock;
  assign rePortIn_reset = reset;
  assign rePortIn_io_enq_0_valid = _T ? 1'h0 : io_enq_0_valid; // @[MultiPortFifo.scala 128:23 151:44 152:36]
  assign rePortIn_io_deq_0_ready = fifo_io_enq_0_ready; // @[MultiPortFifo.scala 129:23]
  assign zipPort_io_enq_0_valid = fifo_io_deq_0_valid; // @[MultiPortFifo.scala 132:27]
  assign zipPort_io_enq_1_valid = io_enq_0_valid; // @[MultiPortFifo.scala 136:33]
  assign zipPort_io_deq_0_ready = io_deq_0_ready; // @[MultiPortFifo.scala 142:27]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_8) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module MultiPortFifo_in1_out1_4(
  input   clock,
  input   reset,
  output  io_deq_0_valid
);
  wire  _T_9 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_deq_0_valid = 1'h0; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module RePort_3(
  input   clock,
  input   reset,
  output  io_deq_0_valid
);
  assign io_deq_0_valid = 1'h0; // @[RePort.scala 79:81]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_deq_0_valid)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_deq_0_valid) & ~reset) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module MultiPortFifo_in1_out1_5(
  input   clock,
  input   reset,
  output  io_deq_0_valid
);
  wire  fifo_clock; // @[MultiPortFifo.scala 124:24]
  wire  fifo_reset; // @[MultiPortFifo.scala 124:24]
  wire  fifo_io_deq_0_valid; // @[MultiPortFifo.scala 124:24]
  wire  rePortIn_clock; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_reset; // @[MultiPortFifo.scala 125:28]
  wire  rePortIn_io_deq_0_valid; // @[MultiPortFifo.scala 125:28]
  wire  _T_8 = ~reset; // @[MultiPortFifo.scala 161:13]
  MultiPortFifo_in1_out1_4 fifo ( // @[MultiPortFifo.scala 124:24]
    .clock(fifo_clock),
    .reset(fifo_reset),
    .io_deq_0_valid(fifo_io_deq_0_valid)
  );
  RePort_3 rePortIn ( // @[MultiPortFifo.scala 125:28]
    .clock(rePortIn_clock),
    .reset(rePortIn_reset),
    .io_deq_0_valid(rePortIn_io_deq_0_valid)
  );
  assign io_deq_0_valid = 1'h0; // @[MultiPortFifo.scala 142:27]
  assign fifo_clock = clock;
  assign fifo_reset = reset;
  assign rePortIn_clock = clock;
  assign rePortIn_reset = reset;
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_8) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module MultiPortFifo_in4_out1(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  output  io_enq_1_ready,
  input   io_enq_1_valid,
  output  io_enq_2_ready,
  input   io_enq_2_valid,
  output  io_enq_3_ready,
  input   io_enq_3_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_2; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_3; // @[MultiPortFifo.scala 58:30]
  reg [1:0] rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg [1:0] wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [2:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = 2'h1 == _io_enq_0_ready_T[1:0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_2 = 2'h2 == _io_enq_0_ready_T[1:0] ? buf_valid_2 : _GEN_1; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_3 = 2'h3 == _io_enq_0_ready_T[1:0] ? buf_valid_3 : _GEN_2; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_enq_1_ready_T_1 = wr_ptr + 2'h1; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_5 = 2'h1 == _io_enq_1_ready_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_6 = 2'h2 == _io_enq_1_ready_T_1 ? buf_valid_2 : _GEN_5; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_7 = 2'h3 == _io_enq_1_ready_T_1 ? buf_valid_3 : _GEN_6; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_enq_2_ready_T_1 = wr_ptr + 2'h2; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_9 = 2'h1 == _io_enq_2_ready_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_10 = 2'h2 == _io_enq_2_ready_T_1 ? buf_valid_2 : _GEN_9; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_11 = 2'h3 == _io_enq_2_ready_T_1 ? buf_valid_3 : _GEN_10; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_enq_3_ready_T_1 = wr_ptr + 2'h3; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_13 = 2'h1 == _io_enq_3_ready_T_1 ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_14 = 2'h2 == _io_enq_3_ready_T_1 ? buf_valid_2 : _GEN_13; // @[MultiPortFifo.scala 64:{94,94}]
  wire  _GEN_15 = 2'h3 == _io_enq_3_ready_T_1 ? buf_valid_3 : _GEN_14; // @[MultiPortFifo.scala 64:{94,94}]
  wire [2:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _GEN_17 = 2'h1 == _io_deq_0_valid_T[1:0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _GEN_18 = 2'h2 == _io_deq_0_valid_T[1:0] ? buf_valid_2 : _GEN_17; // @[MultiPortFifo.scala 65:{94,94}]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_24 = _T ? 2'h0 == _io_enq_0_ready_T[1:0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_25 = _T ? 2'h1 == _io_enq_0_ready_T[1:0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_26 = _T ? 2'h2 == _io_enq_0_ready_T[1:0] | buf_valid_2 : buf_valid_2; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_27 = _T ? 2'h3 == _io_enq_0_ready_T[1:0] | buf_valid_3 : buf_valid_3; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_28 = 2'h0 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_24; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_29 = 2'h1 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_25; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_30 = 2'h2 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_26; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_31 = 2'h3 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_27; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_32 = _T_1 ? _GEN_28 : _GEN_24; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_33 = _T_1 ? _GEN_29 : _GEN_25; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_34 = _T_1 ? _GEN_30 : _GEN_26; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_35 = _T_1 ? _GEN_31 : _GEN_27; // @[MultiPortFifo.scala 98:34]
  wire  _T_2 = io_enq_1_ready & io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_160 = _T_2 ? 2'h0 == _io_enq_1_ready_T_1 | _GEN_32 : _GEN_32; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_161 = _T_2 ? 2'h1 == _io_enq_1_ready_T_1 | _GEN_33 : _GEN_33; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_162 = _T_2 ? 2'h2 == _io_enq_1_ready_T_1 | _GEN_34 : _GEN_34; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_163 = _T_2 ? 2'h3 == _io_enq_1_ready_T_1 | _GEN_35 : _GEN_35; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_164 = 2'h0 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_160; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_165 = 2'h1 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_161; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_166 = 2'h2 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_162; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_167 = 2'h3 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_163; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_168 = _T_1 ? _GEN_164 : _GEN_160; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_169 = _T_1 ? _GEN_165 : _GEN_161; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_170 = _T_1 ? _GEN_166 : _GEN_162; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_171 = _T_1 ? _GEN_167 : _GEN_163; // @[MultiPortFifo.scala 98:34]
  wire  _T_4 = io_enq_2_ready & io_enq_2_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_296 = _T_4 ? 2'h0 == _io_enq_2_ready_T_1 | _GEN_168 : _GEN_168; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_297 = _T_4 ? 2'h1 == _io_enq_2_ready_T_1 | _GEN_169 : _GEN_169; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_298 = _T_4 ? 2'h2 == _io_enq_2_ready_T_1 | _GEN_170 : _GEN_170; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_299 = _T_4 ? 2'h3 == _io_enq_2_ready_T_1 | _GEN_171 : _GEN_171; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_300 = 2'h0 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_296; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_301 = 2'h1 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_297; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_302 = 2'h2 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_298; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_303 = 2'h3 == _io_deq_0_valid_T[1:0] ? 1'h0 : _GEN_299; // @[MultiPortFifo.scala 98:{57,57}]
  wire  _GEN_304 = _T_1 ? _GEN_300 : _GEN_296; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_305 = _T_1 ? _GEN_301 : _GEN_297; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_306 = _T_1 ? _GEN_302 : _GEN_298; // @[MultiPortFifo.scala 98:34]
  wire  _GEN_307 = _T_1 ? _GEN_303 : _GEN_299; // @[MultiPortFifo.scala 98:34]
  wire  _T_6 = io_enq_3_ready & io_enq_3_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_432 = _T_6 ? 2'h0 == _io_enq_3_ready_T_1 | _GEN_304 : _GEN_304; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_433 = _T_6 ? 2'h1 == _io_enq_3_ready_T_1 | _GEN_305 : _GEN_305; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_434 = _T_6 ? 2'h2 == _io_enq_3_ready_T_1 | _GEN_306 : _GEN_306; // @[MultiPortFifo.scala 97:34]
  wire  _GEN_435 = _T_6 ? 2'h3 == _io_enq_3_ready_T_1 | _GEN_307 : _GEN_307; // @[MultiPortFifo.scala 97:34]
  wire [1:0] _GEN_52 = {{1'd0}, _T_1}; // @[MultiPortFifo.scala 106:26]
  wire [1:0] _rd_ptr_T_2 = rd_ptr + _GEN_52; // @[MultiPortFifo.scala 106:26]
  wire [1:0] _wr_ptr_T_1 = _T_2 ? 2'h2 : {{1'd0}, _T}; // @[Mux.scala 101:16]
  wire [1:0] _wr_ptr_T_2 = _T_4 ? 2'h3 : _wr_ptr_T_1; // @[Mux.scala 101:16]
  wire [2:0] _wr_ptr_T_3 = _T_6 ? 3'h4 : {{1'd0}, _wr_ptr_T_2}; // @[Mux.scala 101:16]
  wire [2:0] _wr_ptr_T_5 = _io_enq_0_ready_T + _wr_ptr_T_3; // @[MultiPortFifo.scala 107:26]
  wire [2:0] _GEN_569 = io_flush ? 3'h0 : _wr_ptr_T_5; // @[MultiPortFifo.scala 107:16 87:23 90:16]
  wire  _T_15 = ~reset; // @[MultiPortFifo.scala 161:13]
  wire [2:0] _GEN_54 = reset ? 3'h0 : _GEN_569; // @[MultiPortFifo.scala 61:{27,27}]
  assign io_enq_0_ready = ~_GEN_3; // @[MultiPortFifo.scala 64:94]
  assign io_enq_1_ready = ~_GEN_7; // @[MultiPortFifo.scala 64:94]
  assign io_enq_2_ready = ~_GEN_11; // @[MultiPortFifo.scala 64:94]
  assign io_enq_3_ready = ~_GEN_15; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = 2'h3 == _io_deq_0_valid_T[1:0] ? buf_valid_3 : _GEN_18; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (2'h0 == _io_deq_0_valid_T[1:0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_432;
      end
    end else begin
      buf_valid_0 <= _GEN_432;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (2'h1 == _io_deq_0_valid_T[1:0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_433;
      end
    end else begin
      buf_valid_1 <= _GEN_433;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (2'h2 == _io_deq_0_valid_T[1:0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_2 <= _GEN_434;
      end
    end else begin
      buf_valid_2 <= _GEN_434;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (2'h3 == _io_deq_0_valid_T[1:0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_3 <= _GEN_435;
      end
    end else begin
      buf_valid_3 <= _GEN_435;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 2'h0; // @[MultiPortFifo.scala 60:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      rd_ptr <= 2'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      rd_ptr <= _rd_ptr_T_2; // @[MultiPortFifo.scala 106:16]
    end
    wr_ptr <= _GEN_54[1:0]; // @[MultiPortFifo.scala 61:{27,27}]
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_1_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_1_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_1_valid & ~io_enq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_1_valid & ~io_enq_1_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_2_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_2_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_2_valid & ~io_enq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_2_valid & ~io_enq_1_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_2_valid & ~io_enq_2_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_2_valid & ~io_enq_2_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_3_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_3_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_3_valid & ~io_enq_1_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_3_valid & ~io_enq_1_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_3_valid & ~io_enq_2_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_3_valid & ~io_enq_2_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_3_valid & ~io_enq_3_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_3_valid & ~io_enq_3_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_15 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_15) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & _T_15 & ~_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T & (_T_2 & _T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_4 & _T_15 & ~_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T & (_T_4 & _T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_4 & _T_15 & ~_T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2 & (_T_4 & _T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & _T_15 & ~_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T & (_T_6 & _T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & _T_15 & ~_T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2 & (_T_6 & _T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & _T_15 & ~_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_4 & (_T_6 & _T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  buf_valid_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  buf_valid_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  rd_ptr = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  wr_ptr = _RAND_5[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IF3(
  input         clock,
  input         reset,
  output        io_if3_req_0_ready,
  input         io_if3_req_0_valid,
  input  [15:0] io_if3_req_0_bits_instr,
  input         io_if3_req_0_bits_isRedirect,
  output        io_if3_req_1_ready,
  input         io_if3_req_1_valid,
  input  [15:0] io_if3_req_1_bits_instr,
  input         io_if3_req_1_bits_isFault,
  input         io_if3_req_1_bits_isRedirect,
  output        io_if3_req_2_ready,
  input         io_if3_req_2_valid,
  input  [15:0] io_if3_req_2_bits_instr,
  input         io_if3_req_2_bits_isFault,
  input         io_if3_req_2_bits_isRedirect,
  output        io_if3_req_3_ready,
  input         io_if3_req_3_valid,
  input  [15:0] io_if3_req_3_bits_instr,
  input         io_if3_req_3_bits_isFault,
  input         io_if3_req_3_bits_isRedirect,
  input         io_if3_resp_0_ready,
  input         io_btbResp_0_ready,
  input         io_bimResp_0_ready,
  input         io_if4Redirect_valid,
  input         io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  wire  combPDT_clock; // @[IF3.scala 52:23]
  wire  combPDT_reset; // @[IF3.scala 52:23]
  wire  combPDT_io_enq_0_ready; // @[IF3.scala 52:23]
  wire  combPDT_io_enq_0_valid; // @[IF3.scala 52:23]
  wire  combPDT_io_enq_1_ready; // @[IF3.scala 52:23]
  wire  combPDT_io_enq_1_valid; // @[IF3.scala 52:23]
  wire  combPDT_io_enq_2_ready; // @[IF3.scala 52:23]
  wire  combPDT_io_enq_2_valid; // @[IF3.scala 52:23]
  wire  combPDT_io_enq_3_ready; // @[IF3.scala 52:23]
  wire  combPDT_io_enq_3_valid; // @[IF3.scala 52:23]
  wire  combPDT_io_deq_0_ready; // @[IF3.scala 52:23]
  wire  combPDT_io_deq_0_valid; // @[IF3.scala 52:23]
  wire  combPDT_io_deq_1_ready; // @[IF3.scala 52:23]
  wire  combPDT_io_deq_1_valid; // @[IF3.scala 52:23]
  wire  combPDT_io_deq_2_ready; // @[IF3.scala 52:23]
  wire  combPDT_io_deq_2_valid; // @[IF3.scala 52:23]
  wire  combPDT_io_deq_3_ready; // @[IF3.scala 52:23]
  wire  combPDT_io_deq_3_valid; // @[IF3.scala 52:23]
  wire  btb_clock; // @[IF3.scala 56:19]
  wire  btb_reset; // @[IF3.scala 56:19]
  wire  btb_io_req_ready; // @[IF3.scala 56:19]
  wire  btb_io_req_valid; // @[IF3.scala 56:19]
  wire  btb_io_resp_ready; // @[IF3.scala 56:19]
  wire  btb_io_resp_valid; // @[IF3.scala 56:19]
  wire  btb_io_isReady; // @[IF3.scala 56:19]
  wire  bim_clock; // @[IF3.scala 57:19]
  wire  bim_reset; // @[IF3.scala 57:19]
  wire  bim_io_req_ready; // @[IF3.scala 57:19]
  wire  bim_io_req_valid; // @[IF3.scala 57:19]
  wire  bim_io_resp_ready; // @[IF3.scala 57:19]
  wire  bim_io_resp_valid; // @[IF3.scala 57:19]
  wire  bim_io_isReady; // @[IF3.scala 57:19]
  wire  btbFifo_clock; // @[IF3.scala 60:24]
  wire  btbFifo_reset; // @[IF3.scala 60:24]
  wire  btbFifo_io_enq_0_ready; // @[IF3.scala 60:24]
  wire  btbFifo_io_enq_0_valid; // @[IF3.scala 60:24]
  wire  btbFifo_io_deq_0_ready; // @[IF3.scala 60:24]
  wire  btbFifo_io_deq_0_valid; // @[IF3.scala 60:24]
  wire  btbFifo_io_flush; // @[IF3.scala 60:24]
  wire  bimFifo_clock; // @[IF3.scala 61:24]
  wire  bimFifo_reset; // @[IF3.scala 61:24]
  wire  bimFifo_io_enq_0_ready; // @[IF3.scala 61:24]
  wire  bimFifo_io_enq_0_valid; // @[IF3.scala 61:24]
  wire  bimFifo_io_deq_0_ready; // @[IF3.scala 61:24]
  wire  bimFifo_io_deq_0_valid; // @[IF3.scala 61:24]
  wire  bimFifo_io_flush; // @[IF3.scala 61:24]
  wire  tageFifo_clock; // @[IF3.scala 62:24]
  wire  tageFifo_reset; // @[IF3.scala 62:24]
  wire  tageFifo_io_deq_0_valid; // @[IF3.scala 62:24]
  wire  if3_resp_fifo_clock; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_reset; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_enq_0_ready; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_enq_0_valid; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_enq_1_ready; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_enq_1_valid; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_enq_2_ready; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_enq_2_valid; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_enq_3_ready; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_enq_3_valid; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_deq_0_ready; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_deq_0_valid; // @[IF3.scala 67:29]
  wire  if3_resp_fifo_io_flush; // @[IF3.scala 67:29]
  reg  pipeLineLock; // @[IF3.scala 54:29]
  wire  predictor_ready = btb_io_isReady & bim_io_isReady; // @[IF3.scala 65:40]
  wire  is_instr32_0 = io_if3_req_0_bits_instr[1:0] == 2'h3; // @[IF3.scala 81:54]
  wire  is_instr32_1 = io_if3_req_1_bits_instr[1:0] == 2'h3; // @[IF3.scala 81:54]
  wire  is_instr32_2 = io_if3_req_2_bits_instr[1:0] == 2'h3; // @[IF3.scala 81:54]
  wire  is_instr32_3 = io_if3_req_3_bits_instr[1:0] == 2'h3; // @[IF3.scala 81:54]
  wire  isPassThrough_1 = is_instr32_0 | io_if3_req_0_bits_isRedirect; // @[IF3.scala 86:51]
  wire  _T_3 = ~isPassThrough_1; // @[IF3.scala 86:30]
  wire  isPassThrough_2 = is_instr32_1 & ~isPassThrough_1 | io_if3_req_1_bits_isRedirect; // @[IF3.scala 86:51]
  wire  _T_6 = ~isPassThrough_2; // @[IF3.scala 86:30]
  wire  _T_8 = is_instr32_2 & ~isPassThrough_2 | io_if3_req_2_bits_isRedirect; // @[IF3.scala 86:51]
  wire  isPassThrough_3 = is_instr32_3 | _T_8; // @[IF3.scala 89:27 90:24]
  wire [15:0] _reAlignPreDecode_0_info16_is_jalr_T = io_if3_req_1_bits_instr & 16'he07f; // @[IF3.scala 345:34]
  wire  reAlignPreDecode_0_info16_is_jalr = 16'h8002 == _reAlignPreDecode_0_info16_is_jalr_T & io_if3_req_1_bits_instr[
    11:7] != 5'h0; // @[IF3.scala 345:66]
  wire [15:0] _reAlignPreDecode_0_info16_is_branch_T = io_if3_req_1_bits_instr & 16'hc003; // @[IF3.scala 346:34]
  wire  reAlignPreDecode_0_info16_is_branch = 16'hc001 == _reAlignPreDecode_0_info16_is_branch_T; // @[IF3.scala 346:34]
  wire [31:0] _reAlignPreDecode_0_T = {io_if3_req_1_bits_instr,io_if3_req_0_bits_instr}; // @[Cat.scala 33:92]
  wire  reAlignPreDecode_0_info32_is_jalr = _reAlignPreDecode_0_T[6:0] == 7'h67; // @[IF3.scala 371:39]
  wire  reAlignPreDecode_0_info32_is_branch = _reAlignPreDecode_0_T[6:0] == 7'h63; // @[IF3.scala 372:39]
  wire [31:0] _reAlignPreDecode_0_info32_is_fencei_T = _reAlignPreDecode_0_T & 32'h707f; // @[IF3.scala 375:35]
  wire  reAlignPreDecode_0_info32_is_fencei = 32'h100f == _reAlignPreDecode_0_info32_is_fencei_T; // @[IF3.scala 375:35]
  wire [31:0] _reAlignPreDecode_0_info32_is_sfencevma_T = _reAlignPreDecode_0_T & 32'hfe007fff; // @[IF3.scala 376:38]
  wire  reAlignPreDecode_0_info32_is_sfencevma = 32'h12000073 == _reAlignPreDecode_0_info32_is_sfencevma_T; // @[IF3.scala 376:38]
  wire  _reAlignPreDecode_0_T_1_is_jalr = io_if3_req_1_bits_isFault ? reAlignPreDecode_0_info16_is_jalr :
    reAlignPreDecode_0_info32_is_jalr; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_0_T_1_is_branch = io_if3_req_1_bits_isFault ? reAlignPreDecode_0_info16_is_branch :
    reAlignPreDecode_0_info32_is_branch; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_0_T_1_is_fencei = io_if3_req_1_bits_isFault ? 1'h0 : reAlignPreDecode_0_info32_is_fencei; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_0_T_1_is_sfencevma = io_if3_req_1_bits_isFault ? 1'h0 : reAlignPreDecode_0_info32_is_sfencevma
    ; // @[IF3.scala 107:37]
  wire  _reAlign_0_valid_T = io_if3_req_0_ready & io_if3_req_0_valid; // @[Decoupled.scala 52:35]
  wire  _reAlign_0_valid_T_1 = io_if3_req_1_ready & io_if3_req_1_valid; // @[Decoupled.scala 52:35]
  wire  _reAlign_0_valid_T_4 = ~pipeLineLock; // @[IF3.scala 112:100]
  wire  _reAlign_0_valid_T_5 = _reAlign_0_valid_T & _reAlign_0_valid_T_1 & predictor_ready & ~pipeLineLock; // @[IF3.scala 112:98]
  wire [15:0] _reAlignPreDecode_0_info16_is_branch_T_2 = io_if3_req_0_bits_instr & 16'hc003; // @[IF3.scala 346:34]
  wire  reAlignPreDecode_0_info16_1_is_branch = 16'hc001 == _reAlignPreDecode_0_info16_is_branch_T_2; // @[IF3.scala 346:34]
  wire  reAlignPreDecode_0_is_branch = is_instr32_0 ? _reAlignPreDecode_0_T_1_is_branch :
    reAlignPreDecode_0_info16_1_is_branch; // @[IF3.scala 102:31 107:31 138:31]
  wire [15:0] _reAlignPreDecode_0_info16_is_jalr_T_5 = io_if3_req_0_bits_instr & 16'he07f; // @[IF3.scala 345:34]
  wire  reAlignPreDecode_0_info16_1_is_jalr = 16'h8002 == _reAlignPreDecode_0_info16_is_jalr_T_5 &
    io_if3_req_0_bits_instr[11:7] != 5'h0; // @[IF3.scala 345:66]
  wire  reAlignPreDecode_0_is_jalr = is_instr32_0 ? _reAlignPreDecode_0_T_1_is_jalr :
    reAlignPreDecode_0_info16_1_is_jalr; // @[IF3.scala 102:31 107:31 138:31]
  wire  _reAlign_0_ready_T = combPDT_io_enq_0_ready & btb_io_req_ready; // @[IF3.scala 202:53]
  wire  _GEN_332 = reAlignPreDecode_0_is_jalr ? _reAlign_0_ready_T : combPDT_io_enq_0_ready; // @[IF3.scala 179:11 196:27]
  wire  _reAlign_0_ready_T_1 = combPDT_io_enq_0_ready & bim_io_req_ready; // @[IF3.scala 213:53]
  wire  reAlign_0_ready = reAlignPreDecode_0_is_branch ? _reAlign_0_ready_T_1 : _GEN_332; // @[IF3.scala 207:27]
  wire  _io_if3_req_0_ready_T_2 = reAlign_0_ready & predictor_ready & _reAlign_0_valid_T_4; // @[IF3.scala 113:73]
  wire  _io_if3_req_0_ready_T_3 = reAlign_0_ready & predictor_ready & _reAlign_0_valid_T_4 & io_if3_req_1_valid; // @[IF3.scala 113:89]
  wire  _T_15 = ~reset; // @[IF3.scala 132:17]
  wire  _reAlign_0_valid_T_21 = _reAlign_0_valid_T & predictor_ready & _reAlign_0_valid_T_4; // @[IF3.scala 143:75]
  wire  reAlignPreDecode_0_is_fencei = is_instr32_0 & _reAlignPreDecode_0_T_1_is_fencei; // @[IF3.scala 102:31 107:31 138:31]
  wire  reAlignPreDecode_0_is_sfencevma = is_instr32_0 & _reAlignPreDecode_0_T_1_is_sfencevma; // @[IF3.scala 102:31 107:31 138:31]
  wire  reAlign_0_valid = is_instr32_0 ? _reAlign_0_valid_T_5 : _reAlign_0_valid_T_21; // @[IF3.scala 102:31]
  wire  _GEN_34 = is_instr32_0 & _io_if3_req_0_ready_T_2; // @[IF3.scala 102:31]
  wire [15:0] _reAlignPreDecode_1_info16_is_jalr_T = io_if3_req_2_bits_instr & 16'he07f; // @[IF3.scala 345:34]
  wire  reAlignPreDecode_1_info16_is_jalr = 16'h8002 == _reAlignPreDecode_1_info16_is_jalr_T & io_if3_req_2_bits_instr[
    11:7] != 5'h0; // @[IF3.scala 345:66]
  wire [15:0] _reAlignPreDecode_1_info16_is_branch_T = io_if3_req_2_bits_instr & 16'hc003; // @[IF3.scala 346:34]
  wire  reAlignPreDecode_1_info16_is_branch = 16'hc001 == _reAlignPreDecode_1_info16_is_branch_T; // @[IF3.scala 346:34]
  wire [31:0] _reAlignPreDecode_1_T = {io_if3_req_2_bits_instr,io_if3_req_1_bits_instr}; // @[Cat.scala 33:92]
  wire  reAlignPreDecode_1_info32_is_jalr = _reAlignPreDecode_1_T[6:0] == 7'h67; // @[IF3.scala 371:39]
  wire  reAlignPreDecode_1_info32_is_branch = _reAlignPreDecode_1_T[6:0] == 7'h63; // @[IF3.scala 372:39]
  wire [31:0] _reAlignPreDecode_1_info32_is_fencei_T = _reAlignPreDecode_1_T & 32'h707f; // @[IF3.scala 375:35]
  wire  reAlignPreDecode_1_info32_is_fencei = 32'h100f == _reAlignPreDecode_1_info32_is_fencei_T; // @[IF3.scala 375:35]
  wire [31:0] _reAlignPreDecode_1_info32_is_sfencevma_T = _reAlignPreDecode_1_T & 32'hfe007fff; // @[IF3.scala 376:38]
  wire  reAlignPreDecode_1_info32_is_sfencevma = 32'h12000073 == _reAlignPreDecode_1_info32_is_sfencevma_T; // @[IF3.scala 376:38]
  wire  _reAlignPreDecode_1_T_1_is_jalr = io_if3_req_2_bits_isFault ? reAlignPreDecode_1_info16_is_jalr :
    reAlignPreDecode_1_info32_is_jalr; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_1_T_1_is_branch = io_if3_req_2_bits_isFault ? reAlignPreDecode_1_info16_is_branch :
    reAlignPreDecode_1_info32_is_branch; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_1_T_1_is_fencei = io_if3_req_2_bits_isFault ? 1'h0 : reAlignPreDecode_1_info32_is_fencei; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_1_T_1_is_sfencevma = io_if3_req_2_bits_isFault ? 1'h0 : reAlignPreDecode_1_info32_is_sfencevma
    ; // @[IF3.scala 107:37]
  wire  _reAlign_1_valid_T_1 = io_if3_req_2_ready & io_if3_req_2_valid; // @[Decoupled.scala 52:35]
  wire  _reAlign_1_valid_T_5 = _reAlign_0_valid_T_1 & _reAlign_1_valid_T_1 & predictor_ready & ~pipeLineLock; // @[IF3.scala 112:98]
  wire  is_lock_pipe_0 = reAlignPreDecode_0_is_fencei | reAlignPreDecode_0_is_sfencevma; // @[frontend.scala 100:32]
  wire  _GEN_74 = is_instr32_1 ? _reAlignPreDecode_1_T_1_is_branch : reAlignPreDecode_0_info16_is_branch; // @[IF3.scala 102:31 107:31 138:31]
  wire  reAlignPreDecode_1_is_branch = _T_3 & _GEN_74; // @[IF3.scala 101:33 97:25]
  wire  _GEN_73 = is_instr32_1 ? _reAlignPreDecode_1_T_1_is_jalr : reAlignPreDecode_0_info16_is_jalr; // @[IF3.scala 102:31 107:31 138:31]
  wire  reAlignPreDecode_1_is_jalr = _T_3 & _GEN_73; // @[IF3.scala 101:33 97:25]
  wire  _GEN_268 = reAlignPreDecode_0_is_jalr ? combPDT_io_enq_1_ready : combPDT_io_enq_1_ready & btb_io_req_ready; // @[IF3.scala 197:100 179:11 202:26]
  wire  _GEN_271 = reAlignPreDecode_1_is_jalr ? _GEN_268 : combPDT_io_enq_1_ready; // @[IF3.scala 179:11 196:27]
  wire  _GEN_274 = reAlignPreDecode_0_is_branch ? _GEN_271 : combPDT_io_enq_1_ready & bim_io_req_ready; // @[IF3.scala 208:103 213:26]
  wire  _GEN_277 = reAlignPreDecode_1_is_branch ? _GEN_274 : _GEN_271; // @[IF3.scala 207:27]
  wire  _GEN_291 = reAlignPreDecode_0_is_jalr ? 1'h0 : _GEN_277; // @[IF3.scala 242:100 245:28]
  wire  _GEN_297 = reAlignPreDecode_1_is_jalr ? _GEN_291 : _GEN_277; // @[IF3.scala 241:27]
  wire  _GEN_303 = reAlignPreDecode_0_is_branch ? 1'h0 : _GEN_297; // @[IF3.scala 252:103 255:28]
  wire  _GEN_309 = reAlignPreDecode_1_is_branch ? _GEN_303 : _GEN_297; // @[IF3.scala 251:27]
  wire  _GEN_326 = ~reAlign_0_ready ? 1'h0 : _GEN_309; // @[IF3.scala 271:44 272:26]
  wire  reAlign_1_ready = is_lock_pipe_0 ? 1'h0 : _GEN_326; // @[IF3.scala 234:29 237:26]
  wire  _io_if3_req_1_ready_T_11 = reAlign_1_ready & predictor_ready & _reAlign_0_valid_T_4; // @[IF3.scala 113:73]
  wire  _io_if3_req_1_ready_T_12 = reAlign_1_ready & predictor_ready & _reAlign_0_valid_T_4 & io_if3_req_2_valid; // @[IF3.scala 113:89]
  wire  _reAlign_1_valid_T_21 = _reAlign_0_valid_T_1 & predictor_ready & _reAlign_0_valid_T_4; // @[IF3.scala 143:75]
  wire  _GEN_78 = is_instr32_1 & _reAlignPreDecode_1_T_1_is_fencei; // @[IF3.scala 102:31 107:31 138:31]
  wire  _GEN_79 = is_instr32_1 & _reAlignPreDecode_1_T_1_is_sfencevma; // @[IF3.scala 102:31 107:31 138:31]
  wire  _GEN_82 = is_instr32_1 ? _reAlign_1_valid_T_5 : _reAlign_1_valid_T_21; // @[IF3.scala 102:31]
  wire  _GEN_83 = is_instr32_1 ? _io_if3_req_1_ready_T_12 : _io_if3_req_1_ready_T_11; // @[IF3.scala 102:31]
  wire  _GEN_84 = is_instr32_1 & _io_if3_req_1_ready_T_11; // @[IF3.scala 102:31]
  wire  reAlignPreDecode_1_is_fencei = _T_3 & _GEN_78; // @[IF3.scala 101:33 97:25]
  wire  reAlignPreDecode_1_is_sfencevma = _T_3 & _GEN_79; // @[IF3.scala 101:33 97:25]
  wire  _GEN_100 = _T_3 & _GEN_82; // @[IF3.scala 101:33 95:22]
  wire [15:0] _reAlignPreDecode_2_info16_is_jalr_T = io_if3_req_3_bits_instr & 16'he07f; // @[IF3.scala 345:34]
  wire  reAlignPreDecode_2_info16_is_jalr = 16'h8002 == _reAlignPreDecode_2_info16_is_jalr_T & io_if3_req_3_bits_instr[
    11:7] != 5'h0; // @[IF3.scala 345:66]
  wire [15:0] _reAlignPreDecode_2_info16_is_branch_T = io_if3_req_3_bits_instr & 16'hc003; // @[IF3.scala 346:34]
  wire  reAlignPreDecode_2_info16_is_branch = 16'hc001 == _reAlignPreDecode_2_info16_is_branch_T; // @[IF3.scala 346:34]
  wire [31:0] _reAlignPreDecode_2_T = {io_if3_req_3_bits_instr,io_if3_req_2_bits_instr}; // @[Cat.scala 33:92]
  wire  reAlignPreDecode_2_info32_is_jalr = _reAlignPreDecode_2_T[6:0] == 7'h67; // @[IF3.scala 371:39]
  wire  reAlignPreDecode_2_info32_is_branch = _reAlignPreDecode_2_T[6:0] == 7'h63; // @[IF3.scala 372:39]
  wire [31:0] _reAlignPreDecode_2_info32_is_fencei_T = _reAlignPreDecode_2_T & 32'h707f; // @[IF3.scala 375:35]
  wire  reAlignPreDecode_2_info32_is_fencei = 32'h100f == _reAlignPreDecode_2_info32_is_fencei_T; // @[IF3.scala 375:35]
  wire [31:0] _reAlignPreDecode_2_info32_is_sfencevma_T = _reAlignPreDecode_2_T & 32'hfe007fff; // @[IF3.scala 376:38]
  wire  reAlignPreDecode_2_info32_is_sfencevma = 32'h12000073 == _reAlignPreDecode_2_info32_is_sfencevma_T; // @[IF3.scala 376:38]
  wire  _reAlignPreDecode_2_T_1_is_jalr = io_if3_req_3_bits_isFault ? reAlignPreDecode_2_info16_is_jalr :
    reAlignPreDecode_2_info32_is_jalr; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_2_T_1_is_branch = io_if3_req_3_bits_isFault ? reAlignPreDecode_2_info16_is_branch :
    reAlignPreDecode_2_info32_is_branch; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_2_T_1_is_fencei = io_if3_req_3_bits_isFault ? 1'h0 : reAlignPreDecode_2_info32_is_fencei; // @[IF3.scala 107:37]
  wire  _reAlignPreDecode_2_T_1_is_sfencevma = io_if3_req_3_bits_isFault ? 1'h0 : reAlignPreDecode_2_info32_is_sfencevma
    ; // @[IF3.scala 107:37]
  wire  _reAlign_2_valid_T_1 = io_if3_req_3_ready & io_if3_req_3_valid; // @[Decoupled.scala 52:35]
  wire  _reAlign_2_valid_T_5 = _reAlign_1_valid_T_1 & _reAlign_2_valid_T_1 & predictor_ready & ~pipeLineLock; // @[IF3.scala 112:98]
  wire  is_lock_pipe_1 = reAlignPreDecode_1_is_fencei | reAlignPreDecode_1_is_sfencevma; // @[frontend.scala 100:32]
  wire  _GEN_121 = is_instr32_2 ? _reAlignPreDecode_2_T_1_is_branch : reAlignPreDecode_1_info16_is_branch; // @[IF3.scala 102:31 107:31 138:31]
  wire  reAlignPreDecode_2_is_branch = _T_6 & _GEN_121; // @[IF3.scala 101:33 97:25]
  wire  _T_98 = reAlignPreDecode_0_is_branch | reAlignPreDecode_1_is_branch; // @[IF3.scala 252:94]
  wire  _GEN_120 = is_instr32_2 ? _reAlignPreDecode_2_T_1_is_jalr : reAlignPreDecode_1_info16_is_jalr; // @[IF3.scala 102:31 107:31 138:31]
  wire  reAlignPreDecode_2_is_jalr = _T_6 & _GEN_120; // @[IF3.scala 101:33 97:25]
  wire  _T_97 = reAlignPreDecode_0_is_jalr | reAlignPreDecode_1_is_jalr; // @[IF3.scala 242:92]
  wire  _GEN_220 = _T_97 ? combPDT_io_enq_2_ready : combPDT_io_enq_2_ready & btb_io_req_ready; // @[IF3.scala 197:100 179:11 202:26]
  wire  _GEN_223 = reAlignPreDecode_2_is_jalr ? _GEN_220 : combPDT_io_enq_2_ready; // @[IF3.scala 179:11 196:27]
  wire  _GEN_226 = _T_98 ? _GEN_223 : combPDT_io_enq_2_ready & bim_io_req_ready; // @[IF3.scala 208:103 213:26]
  wire  _GEN_229 = reAlignPreDecode_2_is_branch ? _GEN_226 : _GEN_223; // @[IF3.scala 207:27]
  wire  _GEN_241 = reAlignPreDecode_0_is_jalr | reAlignPreDecode_1_is_jalr ? 1'h0 : _GEN_229; // @[IF3.scala 242:100 245:28]
  wire  _GEN_245 = reAlignPreDecode_2_is_jalr ? _GEN_241 : _GEN_229; // @[IF3.scala 241:27]
  wire  _GEN_249 = reAlignPreDecode_0_is_branch | reAlignPreDecode_1_is_branch ? 1'h0 : _GEN_245; // @[IF3.scala 252:103 255:28]
  wire  _GEN_253 = reAlignPreDecode_2_is_branch ? _GEN_249 : _GEN_245; // @[IF3.scala 251:27]
  wire  _GEN_264 = ~reAlign_0_ready ? 1'h0 : _GEN_253; // @[IF3.scala 271:44 272:26]
  wire  _GEN_265 = ~reAlign_1_ready ? 1'h0 : _GEN_264; // @[IF3.scala 271:44 272:26]
  wire  _GEN_287 = is_lock_pipe_1 ? 1'h0 : _GEN_265; // @[IF3.scala 234:29 237:26]
  wire  _GEN_293 = reAlignPreDecode_0_is_jalr ? 1'h0 : _GEN_287; // @[IF3.scala 242:100 245:28]
  wire  _GEN_299 = reAlignPreDecode_1_is_jalr ? _GEN_293 : _GEN_287; // @[IF3.scala 241:27]
  wire  _GEN_305 = reAlignPreDecode_0_is_branch ? 1'h0 : _GEN_299; // @[IF3.scala 252:103 255:28]
  wire  _GEN_311 = reAlignPreDecode_1_is_branch ? _GEN_305 : _GEN_299; // @[IF3.scala 251:27]
  wire  reAlign_2_ready = is_lock_pipe_0 ? 1'h0 : _GEN_311; // @[IF3.scala 234:29 237:26]
  wire  _io_if3_req_2_ready_T_14 = reAlign_2_ready & predictor_ready & _reAlign_0_valid_T_4; // @[IF3.scala 113:73]
  wire  _io_if3_req_2_ready_T_15 = reAlign_2_ready & predictor_ready & _reAlign_0_valid_T_4 & io_if3_req_3_valid; // @[IF3.scala 113:89]
  wire  _reAlign_2_valid_T_15 = _reAlign_1_valid_T_1 & predictor_ready & _reAlign_0_valid_T_4; // @[IF3.scala 143:75]
  wire  _GEN_125 = is_instr32_2 & _reAlignPreDecode_2_T_1_is_fencei; // @[IF3.scala 102:31 107:31 138:31]
  wire  _GEN_126 = is_instr32_2 & _reAlignPreDecode_2_T_1_is_sfencevma; // @[IF3.scala 102:31 107:31 138:31]
  wire  _GEN_129 = is_instr32_2 ? _reAlign_2_valid_T_5 : _reAlign_2_valid_T_15; // @[IF3.scala 102:31]
  wire  _GEN_130 = is_instr32_2 ? _io_if3_req_2_ready_T_15 : _io_if3_req_2_ready_T_14; // @[IF3.scala 102:31]
  wire  _GEN_131 = is_instr32_2 & _io_if3_req_2_ready_T_14; // @[IF3.scala 102:31]
  wire  reAlignPreDecode_2_is_fencei = _T_6 & _GEN_125; // @[IF3.scala 101:33 97:25]
  wire  reAlignPreDecode_2_is_sfencevma = _T_6 & _GEN_126; // @[IF3.scala 101:33 97:25]
  wire  _GEN_146 = _T_6 & _GEN_129; // @[IF3.scala 101:33 95:22]
  wire  _GEN_148 = _T_6 & _GEN_131; // @[IF3.scala 101:33]
  wire  _reAlign_3_valid_T_3 = _reAlign_2_valid_T_1 & predictor_ready & _reAlign_0_valid_T_4; // @[IF3.scala 143:75]
  wire  is_lock_pipe_2 = reAlignPreDecode_2_is_fencei | reAlignPreDecode_2_is_sfencevma; // @[frontend.scala 100:32]
  wire  _GEN_157 = is_instr32_3 ? 1'h0 : reAlignPreDecode_2_info16_is_branch; // @[IF3.scala 102:31 97:25 138:31]
  wire  reAlignPreDecode_3_is_branch = ~isPassThrough_3 & _GEN_157; // @[IF3.scala 101:33 97:25]
  wire  _T_88 = reAlignPreDecode_0_is_branch | reAlignPreDecode_1_is_branch | reAlignPreDecode_2_is_branch; // @[IF3.scala 252:94]
  wire  _GEN_156 = is_instr32_3 ? 1'h0 : reAlignPreDecode_2_info16_is_jalr; // @[IF3.scala 102:31 97:25 138:31]
  wire  reAlignPreDecode_3_is_jalr = ~isPassThrough_3 & _GEN_156; // @[IF3.scala 101:33 97:25]
  wire  _T_86 = reAlignPreDecode_0_is_jalr | reAlignPreDecode_1_is_jalr | reAlignPreDecode_2_is_jalr; // @[IF3.scala 242:92]
  wire  _GEN_185 = _T_86 ? combPDT_io_enq_3_ready : combPDT_io_enq_3_ready & btb_io_req_ready; // @[IF3.scala 197:100 179:11 202:26]
  wire  _GEN_188 = reAlignPreDecode_3_is_jalr ? _GEN_185 : combPDT_io_enq_3_ready; // @[IF3.scala 179:11 196:27]
  wire  _GEN_191 = _T_88 ? _GEN_188 : combPDT_io_enq_3_ready & bim_io_req_ready; // @[IF3.scala 208:103 213:26]
  wire  _GEN_194 = reAlignPreDecode_3_is_branch ? _GEN_191 : _GEN_188; // @[IF3.scala 207:27]
  wire  _GEN_204 = reAlignPreDecode_0_is_jalr | reAlignPreDecode_1_is_jalr | reAlignPreDecode_2_is_jalr ? 1'h0 :
    _GEN_194; // @[IF3.scala 242:100 245:28]
  wire  _GEN_206 = reAlignPreDecode_3_is_jalr ? _GEN_204 : _GEN_194; // @[IF3.scala 241:27]
  wire  _GEN_208 = reAlignPreDecode_0_is_branch | reAlignPreDecode_1_is_branch | reAlignPreDecode_2_is_branch ? 1'h0 :
    _GEN_206; // @[IF3.scala 252:103 255:28]
  wire  _GEN_210 = reAlignPreDecode_3_is_branch ? _GEN_208 : _GEN_206; // @[IF3.scala 251:27]
  wire  _GEN_215 = ~reAlign_0_ready ? 1'h0 : _GEN_210; // @[IF3.scala 271:44 272:26]
  wire  _GEN_216 = ~reAlign_1_ready ? 1'h0 : _GEN_215; // @[IF3.scala 271:44 272:26]
  wire  _GEN_217 = ~reAlign_2_ready ? 1'h0 : _GEN_216; // @[IF3.scala 271:44 272:26]
  wire  _GEN_239 = is_lock_pipe_2 ? 1'h0 : _GEN_217; // @[IF3.scala 234:29 237:26]
  wire  _GEN_243 = reAlignPreDecode_0_is_jalr | reAlignPreDecode_1_is_jalr ? 1'h0 : _GEN_239; // @[IF3.scala 242:100 245:28]
  wire  _GEN_247 = reAlignPreDecode_2_is_jalr ? _GEN_243 : _GEN_239; // @[IF3.scala 241:27]
  wire  _GEN_251 = reAlignPreDecode_0_is_branch | reAlignPreDecode_1_is_branch ? 1'h0 : _GEN_247; // @[IF3.scala 252:103 255:28]
  wire  _GEN_255 = reAlignPreDecode_2_is_branch ? _GEN_251 : _GEN_247; // @[IF3.scala 251:27]
  wire  _GEN_289 = is_lock_pipe_1 ? 1'h0 : _GEN_255; // @[IF3.scala 234:29 237:26]
  wire  _GEN_295 = reAlignPreDecode_0_is_jalr ? 1'h0 : _GEN_289; // @[IF3.scala 242:100 245:28]
  wire  _GEN_301 = reAlignPreDecode_1_is_jalr ? _GEN_295 : _GEN_289; // @[IF3.scala 241:27]
  wire  _GEN_307 = reAlignPreDecode_0_is_branch ? 1'h0 : _GEN_301; // @[IF3.scala 252:103 255:28]
  wire  _GEN_313 = reAlignPreDecode_1_is_branch ? _GEN_307 : _GEN_301; // @[IF3.scala 251:27]
  wire  reAlign_3_ready = is_lock_pipe_0 ? 1'h0 : _GEN_313; // @[IF3.scala 234:29 237:26]
  wire  _io_if3_req_3_ready_T_11 = reAlign_3_ready & predictor_ready & _reAlign_0_valid_T_4; // @[IF3.scala 144:73]
  wire  _GEN_165 = is_instr32_3 ? 1'h0 : _reAlign_3_valid_T_3; // @[IF3.scala 102:31 95:22]
  wire  _GEN_166 = is_instr32_3 ? _GEN_148 : _io_if3_req_3_ready_T_11; // @[IF3.scala 102:31]
  wire  _GEN_181 = ~isPassThrough_3 & _GEN_165; // @[IF3.scala 101:33 95:22]
  wire  _btb_io_req_valid_T = io_flush | io_if4Redirect_valid; // @[IF3.scala 200:59]
  wire  _GEN_203 = reAlignPreDecode_0_is_jalr | reAlignPreDecode_1_is_jalr | reAlignPreDecode_2_is_jalr ? 1'h0 :
    _GEN_181; // @[IF3.scala 242:100 244:28]
  wire  _GEN_205 = reAlignPreDecode_3_is_jalr ? _GEN_203 : _GEN_181; // @[IF3.scala 241:27]
  wire  _GEN_207 = reAlignPreDecode_0_is_branch | reAlignPreDecode_1_is_branch | reAlignPreDecode_2_is_branch ? 1'h0 :
    _GEN_205; // @[IF3.scala 252:103 254:28]
  wire  _GEN_209 = reAlignPreDecode_3_is_branch ? _GEN_207 : _GEN_205; // @[IF3.scala 251:27]
  wire  _GEN_238 = is_lock_pipe_2 ? 1'h0 : _GEN_209; // @[IF3.scala 234:29 236:26]
  wire  _GEN_242 = reAlignPreDecode_0_is_jalr | reAlignPreDecode_1_is_jalr ? 1'h0 : _GEN_238; // @[IF3.scala 242:100 244:28]
  wire  _GEN_246 = reAlignPreDecode_2_is_jalr ? _GEN_242 : _GEN_238; // @[IF3.scala 241:27]
  wire  _GEN_250 = reAlignPreDecode_0_is_branch | reAlignPreDecode_1_is_branch ? 1'h0 : _GEN_246; // @[IF3.scala 252:103 254:28]
  wire  _GEN_254 = reAlignPreDecode_2_is_branch ? _GEN_250 : _GEN_246; // @[IF3.scala 251:27]
  wire  _GEN_288 = is_lock_pipe_1 ? 1'h0 : _GEN_254; // @[IF3.scala 234:29 236:26]
  wire  _GEN_294 = reAlignPreDecode_0_is_jalr ? 1'h0 : _GEN_288; // @[IF3.scala 242:100 244:28]
  wire  _GEN_300 = reAlignPreDecode_1_is_jalr ? _GEN_294 : _GEN_288; // @[IF3.scala 241:27]
  wire  _GEN_306 = reAlignPreDecode_0_is_branch ? 1'h0 : _GEN_300; // @[IF3.scala 252:103 254:28]
  wire  _GEN_312 = reAlignPreDecode_1_is_branch ? _GEN_306 : _GEN_300; // @[IF3.scala 251:27]
  wire  reAlign_3_valid = is_lock_pipe_0 ? 1'h0 : _GEN_312; // @[IF3.scala 234:29 236:26]
  wire  _btb_io_req_valid_T_2 = reAlign_3_valid & ~(io_flush | io_if4Redirect_valid); // @[IF3.scala 200:46]
  wire  _GEN_183 = _T_86 ? 1'h0 : reAlign_3_valid & ~(io_flush | io_if4Redirect_valid); // @[IF3.scala 197:100 185:20 200:26]
  wire  _GEN_186 = reAlignPreDecode_3_is_jalr & _GEN_183; // @[IF3.scala 185:20 196:27]
  wire  _GEN_189 = _T_88 ? 1'h0 : _btb_io_req_valid_T_2; // @[IF3.scala 208:103 186:20 211:26]
  wire  _GEN_192 = reAlignPreDecode_3_is_branch & _GEN_189; // @[IF3.scala 186:20 207:27]
  wire  _GEN_240 = reAlignPreDecode_0_is_jalr | reAlignPreDecode_1_is_jalr ? 1'h0 : _GEN_146; // @[IF3.scala 242:100 244:28]
  wire  _GEN_244 = reAlignPreDecode_2_is_jalr ? _GEN_240 : _GEN_146; // @[IF3.scala 241:27]
  wire  _GEN_248 = reAlignPreDecode_0_is_branch | reAlignPreDecode_1_is_branch ? 1'h0 : _GEN_244; // @[IF3.scala 252:103 254:28]
  wire  _GEN_252 = reAlignPreDecode_2_is_branch ? _GEN_248 : _GEN_244; // @[IF3.scala 251:27]
  wire  _GEN_286 = is_lock_pipe_1 ? 1'h0 : _GEN_252; // @[IF3.scala 234:29 236:26]
  wire  _GEN_292 = reAlignPreDecode_0_is_jalr ? 1'h0 : _GEN_286; // @[IF3.scala 242:100 244:28]
  wire  _GEN_298 = reAlignPreDecode_1_is_jalr ? _GEN_292 : _GEN_286; // @[IF3.scala 241:27]
  wire  _GEN_304 = reAlignPreDecode_0_is_branch ? 1'h0 : _GEN_298; // @[IF3.scala 252:103 254:28]
  wire  _GEN_310 = reAlignPreDecode_1_is_branch ? _GEN_304 : _GEN_298; // @[IF3.scala 251:27]
  wire  reAlign_2_valid = is_lock_pipe_0 ? 1'h0 : _GEN_310; // @[IF3.scala 234:29 236:26]
  wire  _btb_io_req_valid_T_5 = reAlign_2_valid & ~(io_flush | io_if4Redirect_valid); // @[IF3.scala 200:46]
  wire  _GEN_218 = _T_97 ? _GEN_186 : reAlign_2_valid & ~(io_flush | io_if4Redirect_valid); // @[IF3.scala 197:100 200:26]
  wire  _GEN_221 = reAlignPreDecode_2_is_jalr ? _GEN_218 : _GEN_186; // @[IF3.scala 196:27]
  wire  _GEN_224 = _T_98 ? _GEN_192 : _btb_io_req_valid_T_5; // @[IF3.scala 208:103 211:26]
  wire  _GEN_227 = reAlignPreDecode_2_is_branch ? _GEN_224 : _GEN_192; // @[IF3.scala 207:27]
  wire  _GEN_290 = reAlignPreDecode_0_is_jalr ? 1'h0 : _GEN_100; // @[IF3.scala 242:100 244:28]
  wire  _GEN_296 = reAlignPreDecode_1_is_jalr ? _GEN_290 : _GEN_100; // @[IF3.scala 241:27]
  wire  _GEN_302 = reAlignPreDecode_0_is_branch ? 1'h0 : _GEN_296; // @[IF3.scala 252:103 254:28]
  wire  _GEN_308 = reAlignPreDecode_1_is_branch ? _GEN_302 : _GEN_296; // @[IF3.scala 251:27]
  wire  reAlign_1_valid = is_lock_pipe_0 ? 1'h0 : _GEN_308; // @[IF3.scala 234:29 236:26]
  wire  _btb_io_req_valid_T_8 = reAlign_1_valid & ~(io_flush | io_if4Redirect_valid); // @[IF3.scala 200:46]
  wire  _GEN_266 = reAlignPreDecode_0_is_jalr ? _GEN_221 : reAlign_1_valid & ~(io_flush | io_if4Redirect_valid); // @[IF3.scala 197:100 200:26]
  wire  _GEN_269 = reAlignPreDecode_1_is_jalr ? _GEN_266 : _GEN_221; // @[IF3.scala 196:27]
  wire  _GEN_272 = reAlignPreDecode_0_is_branch ? _GEN_227 : _btb_io_req_valid_T_8; // @[IF3.scala 208:103 211:26]
  wire  _GEN_275 = reAlignPreDecode_1_is_branch ? _GEN_272 : _GEN_227; // @[IF3.scala 207:27]
  wire  _btb_io_req_valid_T_11 = reAlign_0_valid & ~(io_flush | io_if4Redirect_valid); // @[IF3.scala 200:46]
  wire  _T_105 = reAlign_0_ready & reAlign_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_108 = reAlign_1_ready & reAlign_1_valid; // @[Decoupled.scala 52:35]
  wire  _T_111 = reAlign_2_ready & reAlign_2_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_401 = is_lock_pipe_0 & _T_105 | is_lock_pipe_1 & _T_108 | is_lock_pipe_2 & _T_111 | pipeLineLock; // @[IF3.scala 329:{113,128} 54:29]
  RePort combPDT ( // @[IF3.scala 52:23]
    .clock(combPDT_clock),
    .reset(combPDT_reset),
    .io_enq_0_ready(combPDT_io_enq_0_ready),
    .io_enq_0_valid(combPDT_io_enq_0_valid),
    .io_enq_1_ready(combPDT_io_enq_1_ready),
    .io_enq_1_valid(combPDT_io_enq_1_valid),
    .io_enq_2_ready(combPDT_io_enq_2_ready),
    .io_enq_2_valid(combPDT_io_enq_2_valid),
    .io_enq_3_ready(combPDT_io_enq_3_ready),
    .io_enq_3_valid(combPDT_io_enq_3_valid),
    .io_deq_0_ready(combPDT_io_deq_0_ready),
    .io_deq_0_valid(combPDT_io_deq_0_valid),
    .io_deq_1_ready(combPDT_io_deq_1_ready),
    .io_deq_1_valid(combPDT_io_deq_1_valid),
    .io_deq_2_ready(combPDT_io_deq_2_ready),
    .io_deq_2_valid(combPDT_io_deq_2_valid),
    .io_deq_3_ready(combPDT_io_deq_3_ready),
    .io_deq_3_valid(combPDT_io_deq_3_valid)
  );
  BTB btb ( // @[IF3.scala 56:19]
    .clock(btb_clock),
    .reset(btb_reset),
    .io_req_ready(btb_io_req_ready),
    .io_req_valid(btb_io_req_valid),
    .io_resp_ready(btb_io_resp_ready),
    .io_resp_valid(btb_io_resp_valid),
    .io_isReady(btb_io_isReady)
  );
  BIM bim ( // @[IF3.scala 57:19]
    .clock(bim_clock),
    .reset(bim_reset),
    .io_req_ready(bim_io_req_ready),
    .io_req_valid(bim_io_req_valid),
    .io_resp_ready(bim_io_resp_ready),
    .io_resp_valid(bim_io_resp_valid),
    .io_isReady(bim_io_isReady)
  );
  MultiPortFifo_in1_out1_1 btbFifo ( // @[IF3.scala 60:24]
    .clock(btbFifo_clock),
    .reset(btbFifo_reset),
    .io_enq_0_ready(btbFifo_io_enq_0_ready),
    .io_enq_0_valid(btbFifo_io_enq_0_valid),
    .io_deq_0_ready(btbFifo_io_deq_0_ready),
    .io_deq_0_valid(btbFifo_io_deq_0_valid),
    .io_flush(btbFifo_io_flush)
  );
  MultiPortFifo_in1_out1_3 bimFifo ( // @[IF3.scala 61:24]
    .clock(bimFifo_clock),
    .reset(bimFifo_reset),
    .io_enq_0_ready(bimFifo_io_enq_0_ready),
    .io_enq_0_valid(bimFifo_io_enq_0_valid),
    .io_deq_0_ready(bimFifo_io_deq_0_ready),
    .io_deq_0_valid(bimFifo_io_deq_0_valid),
    .io_flush(bimFifo_io_flush)
  );
  MultiPortFifo_in1_out1_5 tageFifo ( // @[IF3.scala 62:24]
    .clock(tageFifo_clock),
    .reset(tageFifo_reset),
    .io_deq_0_valid(tageFifo_io_deq_0_valid)
  );
  MultiPortFifo_in4_out1 if3_resp_fifo ( // @[IF3.scala 67:29]
    .clock(if3_resp_fifo_clock),
    .reset(if3_resp_fifo_reset),
    .io_enq_0_ready(if3_resp_fifo_io_enq_0_ready),
    .io_enq_0_valid(if3_resp_fifo_io_enq_0_valid),
    .io_enq_1_ready(if3_resp_fifo_io_enq_1_ready),
    .io_enq_1_valid(if3_resp_fifo_io_enq_1_valid),
    .io_enq_2_ready(if3_resp_fifo_io_enq_2_ready),
    .io_enq_2_valid(if3_resp_fifo_io_enq_2_valid),
    .io_enq_3_ready(if3_resp_fifo_io_enq_3_ready),
    .io_enq_3_valid(if3_resp_fifo_io_enq_3_valid),
    .io_deq_0_ready(if3_resp_fifo_io_deq_0_ready),
    .io_deq_0_valid(if3_resp_fifo_io_deq_0_valid),
    .io_flush(if3_resp_fifo_io_flush)
  );
  assign io_if3_req_0_ready = is_instr32_0 ? _io_if3_req_0_ready_T_3 : _io_if3_req_0_ready_T_2; // @[IF3.scala 102:31]
  assign io_if3_req_1_ready = _T_3 ? _GEN_83 : _GEN_34; // @[IF3.scala 101:33]
  assign io_if3_req_2_ready = _T_6 ? _GEN_130 : _T_3 & _GEN_84; // @[IF3.scala 101:33]
  assign io_if3_req_3_ready = ~isPassThrough_3 ? _GEN_166 : _T_6 & _GEN_131; // @[IF3.scala 101:33]
  assign combPDT_clock = clock;
  assign combPDT_reset = reset;
  assign combPDT_io_enq_0_valid = is_instr32_0 ? _reAlign_0_valid_T_5 : _reAlign_0_valid_T_21; // @[IF3.scala 102:31]
  assign combPDT_io_enq_1_valid = is_lock_pipe_0 ? 1'h0 : _GEN_308; // @[IF3.scala 234:29 236:26]
  assign combPDT_io_enq_2_valid = is_lock_pipe_0 ? 1'h0 : _GEN_310; // @[IF3.scala 234:29 236:26]
  assign combPDT_io_enq_3_valid = is_lock_pipe_0 ? 1'h0 : _GEN_312; // @[IF3.scala 234:29 236:26]
  assign combPDT_io_deq_0_ready = if3_resp_fifo_io_enq_0_ready; // @[IF3.scala 70:24]
  assign combPDT_io_deq_1_ready = if3_resp_fifo_io_enq_1_ready; // @[IF3.scala 70:24]
  assign combPDT_io_deq_2_ready = if3_resp_fifo_io_enq_2_ready; // @[IF3.scala 70:24]
  assign combPDT_io_deq_3_ready = if3_resp_fifo_io_enq_3_ready; // @[IF3.scala 70:24]
  assign btb_clock = clock;
  assign btb_reset = reset;
  assign btb_io_req_valid = reAlignPreDecode_0_is_jalr ? _btb_io_req_valid_T_11 : _GEN_269; // @[IF3.scala 196:27]
  assign btb_io_resp_ready = btbFifo_io_enq_0_ready; // @[IF3.scala 393:22]
  assign bim_clock = clock;
  assign bim_reset = reset;
  assign bim_io_req_valid = reAlignPreDecode_0_is_branch ? _btb_io_req_valid_T_11 : _GEN_275; // @[IF3.scala 207:27]
  assign bim_io_resp_ready = bimFifo_io_enq_0_ready; // @[IF3.scala 394:22]
  assign btbFifo_clock = clock;
  assign btbFifo_reset = reset;
  assign btbFifo_io_enq_0_valid = btb_io_resp_valid; // @[IF3.scala 393:22]
  assign btbFifo_io_deq_0_ready = io_btbResp_0_ready; // @[IF3.scala 397:19]
  assign btbFifo_io_flush = io_flush | io_if4Redirect_valid; // @[IF3.scala 401:33]
  assign bimFifo_clock = clock;
  assign bimFifo_reset = reset;
  assign bimFifo_io_enq_0_valid = bim_io_resp_valid; // @[IF3.scala 394:22]
  assign bimFifo_io_deq_0_ready = io_bimResp_0_ready; // @[IF3.scala 398:19]
  assign bimFifo_io_flush = io_flush | io_if4Redirect_valid; // @[IF3.scala 402:33]
  assign tageFifo_clock = clock;
  assign tageFifo_reset = reset;
  assign if3_resp_fifo_clock = clock;
  assign if3_resp_fifo_reset = reset;
  assign if3_resp_fifo_io_enq_0_valid = combPDT_io_deq_0_valid; // @[IF3.scala 70:24]
  assign if3_resp_fifo_io_enq_1_valid = combPDT_io_deq_1_valid; // @[IF3.scala 70:24]
  assign if3_resp_fifo_io_enq_2_valid = combPDT_io_deq_2_valid; // @[IF3.scala 70:24]
  assign if3_resp_fifo_io_enq_3_valid = combPDT_io_deq_3_valid; // @[IF3.scala 70:24]
  assign if3_resp_fifo_io_deq_0_ready = io_if3_resp_0_ready; // @[IF3.scala 71:15]
  assign if3_resp_fifo_io_flush = io_if4Redirect_valid | io_flush; // @[IF3.scala 69:49]
  always @(posedge clock) begin
    if (reset) begin // @[IF3.scala 54:29]
      pipeLineLock <= 1'h0; // @[IF3.scala 54:29]
    end else if (_btb_io_req_valid_T) begin // @[IF3.scala 328:42]
      pipeLineLock <= 1'h0; // @[IF3.scala 328:57]
    end else begin
      pipeLineLock <= _GEN_401;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (is_instr32_0 & ~reset & ~(_reAlign_0_valid_T == _reAlign_0_valid_T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF3.scala:132 assert(io.if3_req(i).fire === io.if3_req(i+1).fire)\n"); // @[IF3.scala 132:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_reAlign_0_valid_T == _reAlign_0_valid_T_1) & (is_instr32_0 & ~reset)) begin
          $fatal; // @[IF3.scala 132:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_reAlign_0_valid_T & io_if3_req_0_bits_isRedirect & _T_15 & ~_reAlign_0_valid_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\n    at IF3.scala:160 when( io.if3_req(i).fire  & io.if3_req(i).bits.isRedirect ) { assert(io.if3_req(i+1).fire, \"Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\") }\n"
            ); // @[IF3.scala 160:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_reAlign_0_valid_T_1 & (_reAlign_0_valid_T & io_if3_req_0_bits_isRedirect & _T_15)) begin
          $fatal; // @[IF3.scala 160:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_if3_req_0_valid & io_if3_req_0_bits_isRedirect & _T_15 & ~(~(io_if3_req_1_valid &
          io_if3_req_1_bits_isRedirect))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, No succession isRedirect will appear\n    at IF3.scala:161 when( io.if3_req(i).valid & io.if3_req(i).bits.isRedirect ) { assert( ~(io.if3_req(i+1).valid & io.if3_req(i+1).bits.isRedirect), \"Assert Failed at IF3, No succession isRedirect will appear\" ) }\n"
            ); // @[IF3.scala 161:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_if3_req_1_valid & io_if3_req_1_bits_isRedirect)) & (io_if3_req_0_valid & io_if3_req_0_bits_isRedirect
           & _T_15)) begin
          $fatal; // @[IF3.scala 161:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3 & is_instr32_1 & ~reset & ~(_reAlign_0_valid_T_1 == _reAlign_1_valid_T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF3.scala:132 assert(io.if3_req(i).fire === io.if3_req(i+1).fire)\n"); // @[IF3.scala 132:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_reAlign_0_valid_T_1 == _reAlign_1_valid_T_1) & (_T_3 & is_instr32_1 & ~reset)) begin
          $fatal; // @[IF3.scala 132:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_reAlign_0_valid_T_1 & io_if3_req_1_bits_isRedirect & _T_15 & ~_reAlign_1_valid_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\n    at IF3.scala:160 when( io.if3_req(i).fire  & io.if3_req(i).bits.isRedirect ) { assert(io.if3_req(i+1).fire, \"Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\") }\n"
            ); // @[IF3.scala 160:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_reAlign_1_valid_T_1 & (_reAlign_0_valid_T_1 & io_if3_req_1_bits_isRedirect & _T_15)) begin
          $fatal; // @[IF3.scala 160:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_if3_req_1_valid & io_if3_req_1_bits_isRedirect & _T_15 & ~(~(io_if3_req_2_valid &
          io_if3_req_2_bits_isRedirect))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, No succession isRedirect will appear\n    at IF3.scala:161 when( io.if3_req(i).valid & io.if3_req(i).bits.isRedirect ) { assert( ~(io.if3_req(i+1).valid & io.if3_req(i+1).bits.isRedirect), \"Assert Failed at IF3, No succession isRedirect will appear\" ) }\n"
            ); // @[IF3.scala 161:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_if3_req_2_valid & io_if3_req_2_bits_isRedirect)) & (io_if3_req_1_valid & io_if3_req_1_bits_isRedirect
           & _T_15)) begin
          $fatal; // @[IF3.scala 161:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & is_instr32_2 & ~reset & ~(_reAlign_1_valid_T_1 == _reAlign_2_valid_T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF3.scala:132 assert(io.if3_req(i).fire === io.if3_req(i+1).fire)\n"); // @[IF3.scala 132:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_reAlign_1_valid_T_1 == _reAlign_2_valid_T_1) & (_T_6 & is_instr32_2 & ~reset)) begin
          $fatal; // @[IF3.scala 132:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_reAlign_1_valid_T_1 & io_if3_req_2_bits_isRedirect & _T_15 & ~_reAlign_2_valid_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\n    at IF3.scala:160 when( io.if3_req(i).fire  & io.if3_req(i).bits.isRedirect ) { assert(io.if3_req(i+1).fire, \"Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\") }\n"
            ); // @[IF3.scala 160:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_reAlign_2_valid_T_1 & (_reAlign_1_valid_T_1 & io_if3_req_2_bits_isRedirect & _T_15)) begin
          $fatal; // @[IF3.scala 160:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_if3_req_2_valid & io_if3_req_2_bits_isRedirect & _T_15 & ~(~(io_if3_req_3_valid &
          io_if3_req_3_bits_isRedirect))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, No succession isRedirect will appear\n    at IF3.scala:161 when( io.if3_req(i).valid & io.if3_req(i).bits.isRedirect ) { assert( ~(io.if3_req(i+1).valid & io.if3_req(i+1).bits.isRedirect), \"Assert Failed at IF3, No succession isRedirect will appear\" ) }\n"
            ); // @[IF3.scala 161:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_if3_req_3_valid & io_if3_req_3_bits_isRedirect)) & (io_if3_req_2_valid & io_if3_req_2_bits_isRedirect
           & _T_15)) begin
          $fatal; // @[IF3.scala 161:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_reAlign_2_valid_T_1 & _T_15 & ~(~io_if3_req_3_bits_isRedirect)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, never Redirect at last-entry!\n    at IF3.scala:163 when( io.if3_req(i).fire ) { assert( ~io.if3_req(i).bits.isRedirect, \"Assert Failed at IF3, never Redirect at last-entry!\" ) }\n"
            ); // @[IF3.scala 163:42]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_if3_req_3_bits_isRedirect) & (_reAlign_2_valid_T_1 & _T_15)) begin
          $fatal; // @[IF3.scala 163:42]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pipeLineLock = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RAS(
  input         clock,
  input         reset,
  input         io_enq_valid,
  input  [38:0] io_enq_bits_target,
  input         io_deq_ready,
  output        io_deq_valid,
  output [38:0] io_deq_bits_target,
  input         io_flush
);
`ifdef RANDOMIZE_MEM_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [63:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [38:0] buf_target [0:3]; // @[RAS.scala 43:18]
  wire  buf_target_io_deq_bits_MPORT_en; // @[RAS.scala 43:18]
  wire [1:0] buf_target_io_deq_bits_MPORT_addr; // @[RAS.scala 43:18]
  wire [38:0] buf_target_io_deq_bits_MPORT_data; // @[RAS.scala 43:18]
  wire [38:0] buf_target_MPORT_data; // @[RAS.scala 43:18]
  wire [1:0] buf_target_MPORT_addr; // @[RAS.scala 43:18]
  wire  buf_target_MPORT_mask; // @[RAS.scala 43:18]
  wire  buf_target_MPORT_en; // @[RAS.scala 43:18]
  reg [2:0] btm_ptr; // @[RAS.scala 44:26]
  reg [2:0] top_ptr; // @[RAS.scala 45:26]
  wire  is_empty = btm_ptr == top_ptr; // @[RAS.scala 50:29]
  wire  is_full = btm_ptr[1:0] == top_ptr[1:0] & btm_ptr[2] != top_ptr[2]; // @[RAS.scala 51:61]
  wire [2:0] _btm_ptr_T_1 = btm_ptr + 3'h1; // @[RAS.scala 66:30]
  wire [2:0] _top_ptr_T_1 = top_ptr + 3'h1; // @[RAS.scala 68:28]
  wire  _T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire [2:0] _top_ptr_T_3 = top_ptr - 3'h1; // @[RAS.scala 71:28]
  reg [38:0] io_deq_bits_REG_target; // @[RAS.scala 76:29]
  assign buf_target_io_deq_bits_MPORT_en = 1'h1;
  assign buf_target_io_deq_bits_MPORT_addr = top_ptr[1:0] - 2'h1;
  assign buf_target_io_deq_bits_MPORT_data = buf_target[buf_target_io_deq_bits_MPORT_addr]; // @[RAS.scala 43:18]
  assign buf_target_MPORT_data = io_enq_bits_target;
  assign buf_target_MPORT_addr = top_ptr[1:0];
  assign buf_target_MPORT_mask = 1'h1;
  assign buf_target_MPORT_en = io_enq_valid;
  assign io_deq_valid = ~is_empty; // @[RAS.scala 75:22]
  assign io_deq_bits_target = io_deq_bits_REG_target; // @[RAS.scala 76:19]
  always @(posedge clock) begin
    if (buf_target_MPORT_en & buf_target_MPORT_mask) begin
      buf_target[buf_target_MPORT_addr] <= buf_target_MPORT_data; // @[RAS.scala 43:18]
    end
    if (reset) begin // @[RAS.scala 44:26]
      btm_ptr <= 3'h0; // @[RAS.scala 44:26]
    end else if (io_flush) begin // @[RAS.scala 59:20]
      btm_ptr <= 3'h0; // @[RAS.scala 60:15]
    end else if (io_enq_valid) begin // @[RAS.scala 64:27]
      if (is_full) begin // @[RAS.scala 65:23]
        btm_ptr <= _btm_ptr_T_1; // @[RAS.scala 66:19]
      end
    end
    if (reset) begin // @[RAS.scala 45:26]
      top_ptr <= 3'h0; // @[RAS.scala 45:26]
    end else if (io_flush) begin // @[RAS.scala 59:20]
      top_ptr <= 3'h0; // @[RAS.scala 61:15]
    end else if (_T) begin // @[RAS.scala 70:27]
      top_ptr <= _top_ptr_T_3; // @[RAS.scala 71:17]
    end else if (io_enq_valid) begin // @[RAS.scala 64:27]
      top_ptr <= _top_ptr_T_1; // @[RAS.scala 68:17]
    end
    io_deq_bits_REG_target <= buf_target_io_deq_bits_MPORT_data; // @[RAS.scala 76:29]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {2{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    buf_target[initvar] = _RAND_0[38:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  btm_ptr = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  top_ptr = _RAND_2[2:0];
  _RAND_3 = {2{`RANDOM}};
  io_deq_bits_REG_target = _RAND_3[38:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MultiPortFifo_in1_out1_6(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = _io_enq_0_ready_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_6 = _T ? ~_io_enq_0_ready_T[0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_7 = _T ? _io_enq_0_ready_T[0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_9 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_enq_0_ready = ~_GEN_1; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = _io_deq_0_valid_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_6;
      end
    end else begin
      buf_valid_0 <= _GEN_6;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_7;
      end
    end else begin
      buf_valid_1 <= _GEN_7;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      rd_ptr <= rd_ptr + _T_1; // @[MultiPortFifo.scala 106:16]
    end
    if (reset) begin // @[MultiPortFifo.scala 61:27]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      wr_ptr <= wr_ptr + _T; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rd_ptr = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wr_ptr = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MultiPortFifo_in1_out1_7(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = _io_enq_0_ready_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_6 = _T ? ~_io_enq_0_ready_T[0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_7 = _T ? _io_enq_0_ready_T[0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_9 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_enq_0_ready = ~_GEN_1; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = _io_deq_0_valid_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_6;
      end
    end else begin
      buf_valid_0 <= _GEN_6;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_7;
      end
    end else begin
      buf_valid_1 <= _GEN_7;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      rd_ptr <= rd_ptr + _T_1; // @[MultiPortFifo.scala 106:16]
    end
    if (reset) begin // @[MultiPortFifo.scala 61:27]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      wr_ptr <= wr_ptr + _T; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rd_ptr = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wr_ptr = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MultiPortFifo_in1_out1_8(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  input   io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = _io_enq_0_ready_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_6 = _T ? ~_io_enq_0_ready_T[0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_7 = _T ? _io_enq_0_ready_T[0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_9 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_enq_0_ready = ~_GEN_1; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = _io_deq_0_valid_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_6;
      end
    end else begin
      buf_valid_0 <= _GEN_6;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_7;
      end
    end else begin
      buf_valid_1 <= _GEN_7;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      rd_ptr <= rd_ptr + _T_1; // @[MultiPortFifo.scala 106:16]
    end
    if (reset) begin // @[MultiPortFifo.scala 61:27]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (io_flush) begin // @[MultiPortFifo.scala 87:23]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      wr_ptr <= wr_ptr + _T; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rd_ptr = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wr_ptr = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RePort_4(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  assign io_enq_0_ready = io_deq_0_ready; // @[RePort.scala 80:69]
  assign io_deq_0_valid = _T > 1'h0; // @[RePort.scala 79:81]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T == _T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T == _T_1) & ~reset) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module RePort_5(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  assign io_enq_0_ready = io_deq_0_ready; // @[RePort.scala 80:69]
  assign io_deq_0_valid = _T > 1'h0; // @[RePort.scala 79:81]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T == _T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T == _T_1) & ~reset) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module ReDirect_1(
  input   io_enq_0_valid,
  input   io_enq_0_bits_bim_p,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  output  io_deq_0_bits_bim_p,
  input   io_mapper_0
);
  assign io_deq_0_valid = io_mapper_0 & io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign io_deq_0_bits_bim_p = io_mapper_0 & io_enq_0_bits_bim_p; // @[RePort.scala 160:21 180:{28,40}]
endmodule
module ReDirect_2(
  input         io_enq_0_valid,
  input  [38:0] io_enq_0_bits_target,
  input         io_deq_0_ready,
  output        io_deq_0_valid,
  output [38:0] io_deq_0_bits_target,
  input         io_mapper_0
);
  assign io_deq_0_valid = io_mapper_0 & io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign io_deq_0_bits_target = io_mapper_0 ? io_enq_0_bits_target : 39'h0; // @[RePort.scala 160:21 180:{28,40}]
endmodule
module IF4(
  input         clock,
  input         reset,
  output        io_if4_req_0_ready,
  input         io_if4_req_0_valid,
  input         io_if4_req_0_bits_isRVC,
  input  [31:0] io_if4_req_0_bits_instr,
  input  [38:0] io_if4_req_0_bits_pc,
  input         io_if4_req_0_bits_isRedirect,
  input  [38:0] io_if4_req_0_bits_target,
  input         io_btbResp_0_valid,
  input  [38:0] io_btbResp_0_bits_target,
  input         io_bimResp_0_valid,
  input         io_bimResp_0_bits_bim_p,
  input         io_if4_resp_0_ready,
  input         io_bftq_ready,
  input         io_jftq_ready,
  input         io_flush
);
  wire  ras_clock; // @[IF4.scala 49:19]
  wire  ras_reset; // @[IF4.scala 49:19]
  wire  ras_io_enq_valid; // @[IF4.scala 49:19]
  wire [38:0] ras_io_enq_bits_target; // @[IF4.scala 49:19]
  wire  ras_io_deq_ready; // @[IF4.scala 49:19]
  wire  ras_io_deq_valid; // @[IF4.scala 49:19]
  wire [38:0] ras_io_deq_bits_target; // @[IF4.scala 49:19]
  wire  ras_io_flush; // @[IF4.scala 49:19]
  wire  instr_fifo_clock; // @[IF4.scala 50:26]
  wire  instr_fifo_reset; // @[IF4.scala 50:26]
  wire  instr_fifo_io_enq_0_ready; // @[IF4.scala 50:26]
  wire  instr_fifo_io_enq_0_valid; // @[IF4.scala 50:26]
  wire  instr_fifo_io_deq_0_ready; // @[IF4.scala 50:26]
  wire  instr_fifo_io_deq_0_valid; // @[IF4.scala 50:26]
  wire  instr_fifo_io_flush; // @[IF4.scala 50:26]
  wire  bftq_clock; // @[IF4.scala 51:20]
  wire  bftq_reset; // @[IF4.scala 51:20]
  wire  bftq_io_enq_0_ready; // @[IF4.scala 51:20]
  wire  bftq_io_enq_0_valid; // @[IF4.scala 51:20]
  wire  bftq_io_deq_0_ready; // @[IF4.scala 51:20]
  wire  bftq_io_deq_0_valid; // @[IF4.scala 51:20]
  wire  bftq_io_flush; // @[IF4.scala 51:20]
  wire  jftq_clock; // @[IF4.scala 52:20]
  wire  jftq_reset; // @[IF4.scala 52:20]
  wire  jftq_io_enq_0_ready; // @[IF4.scala 52:20]
  wire  jftq_io_enq_0_valid; // @[IF4.scala 52:20]
  wire  jftq_io_deq_0_ready; // @[IF4.scala 52:20]
  wire  jftq_io_deq_0_valid; // @[IF4.scala 52:20]
  wire  jftq_io_flush; // @[IF4.scala 52:20]
  wire  bRePort_clock; // @[IF4.scala 55:23]
  wire  bRePort_reset; // @[IF4.scala 55:23]
  wire  bRePort_io_enq_0_ready; // @[IF4.scala 55:23]
  wire  bRePort_io_enq_0_valid; // @[IF4.scala 55:23]
  wire  bRePort_io_deq_0_ready; // @[IF4.scala 55:23]
  wire  bRePort_io_deq_0_valid; // @[IF4.scala 55:23]
  wire  jRePort_clock; // @[IF4.scala 56:23]
  wire  jRePort_reset; // @[IF4.scala 56:23]
  wire  jRePort_io_enq_0_ready; // @[IF4.scala 56:23]
  wire  jRePort_io_enq_0_valid; // @[IF4.scala 56:23]
  wire  jRePort_io_deq_0_ready; // @[IF4.scala 56:23]
  wire  jRePort_io_deq_0_valid; // @[IF4.scala 56:23]
  wire  bimRedirect_mdl_io_enq_0_valid; // @[RePort.scala 188:21]
  wire  bimRedirect_mdl_io_enq_0_bits_bim_p; // @[RePort.scala 188:21]
  wire  bimRedirect_mdl_io_deq_0_ready; // @[RePort.scala 188:21]
  wire  bimRedirect_mdl_io_deq_0_valid; // @[RePort.scala 188:21]
  wire  bimRedirect_mdl_io_deq_0_bits_bim_p; // @[RePort.scala 188:21]
  wire  bimRedirect_mdl_io_mapper_0; // @[RePort.scala 188:21]
  wire  btbRedirect_mdl_io_enq_0_valid; // @[RePort.scala 188:21]
  wire [38:0] btbRedirect_mdl_io_enq_0_bits_target; // @[RePort.scala 188:21]
  wire  btbRedirect_mdl_io_deq_0_ready; // @[RePort.scala 188:21]
  wire  btbRedirect_mdl_io_deq_0_valid; // @[RePort.scala 188:21]
  wire [38:0] btbRedirect_mdl_io_deq_0_bits_target; // @[RePort.scala 188:21]
  wire  btbRedirect_mdl_io_mapper_0; // @[RePort.scala 188:21]
  wire [15:0] _preDecodeAgn_info16_is_jal_T = io_if4_req_0_bits_instr[15:0] & 16'he003; // @[IF3.scala 344:34]
  wire  preDecodeAgn_info16_is_jal = 16'ha001 == _preDecodeAgn_info16_is_jal_T; // @[IF3.scala 344:34]
  wire [15:0] _preDecodeAgn_info16_is_jalr_T = io_if4_req_0_bits_instr[15:0] & 16'he07f; // @[IF3.scala 345:34]
  wire  _preDecodeAgn_info16_is_jalr_T_3 = io_if4_req_0_bits_instr[11:7] != 5'h0; // @[IF3.scala 345:82]
  wire  preDecodeAgn_info16_is_jalr = 16'h8002 == _preDecodeAgn_info16_is_jalr_T & io_if4_req_0_bits_instr[11:7] != 5'h0
    ; // @[IF3.scala 345:66]
  wire [15:0] _preDecodeAgn_info16_is_branch_T = io_if4_req_0_bits_instr[15:0] & 16'hc003; // @[IF3.scala 346:34]
  wire  preDecodeAgn_info16_is_branch = 16'hc001 == _preDecodeAgn_info16_is_branch_T; // @[IF3.scala 346:34]
  wire [15:0] _preDecodeAgn_info16_is_call_T = io_if4_req_0_bits_instr[15:0] & 16'hf07f; // @[IF3.scala 347:34]
  wire  preDecodeAgn_info16_is_call = 16'h9002 == _preDecodeAgn_info16_is_call_T & _preDecodeAgn_info16_is_jalr_T_3; // @[IF3.scala 347:66]
  wire [15:0] _preDecodeAgn_info16_is_return_T = io_if4_req_0_bits_instr[15:0] & 16'hfdff; // @[IF3.scala 348:34]
  wire  preDecodeAgn_info16_is_return = 16'h8082 == _preDecodeAgn_info16_is_return_T; // @[IF3.scala 348:34]
  wire [51:0] _preDecodeAgn_info16_imm_T_2 = io_if4_req_0_bits_instr[12] ? 52'hfffffffffffff : 52'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _preDecodeAgn_info16_imm_T_11 = {_preDecodeAgn_info16_imm_T_2,io_if4_req_0_bits_instr[12],
    io_if4_req_0_bits_instr[8],io_if4_req_0_bits_instr[10:9],io_if4_req_0_bits_instr[6],io_if4_req_0_bits_instr[7],
    io_if4_req_0_bits_instr[2],io_if4_req_0_bits_instr[11],io_if4_req_0_bits_instr[5:3],1'h0}; // @[Cat.scala 33:92]
  wire [54:0] _preDecodeAgn_info16_imm_T_14 = io_if4_req_0_bits_instr[12] ? 55'h7fffffffffffff : 55'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _preDecodeAgn_info16_imm_T_20 = {_preDecodeAgn_info16_imm_T_14,io_if4_req_0_bits_instr[12],
    io_if4_req_0_bits_instr[6:5],io_if4_req_0_bits_instr[2],io_if4_req_0_bits_instr[11:10],io_if4_req_0_bits_instr[4:3],1'h0
    }; // @[Cat.scala 33:92]
  wire [63:0] _preDecodeAgn_info16_imm_T_21 = preDecodeAgn_info16_is_jal ? _preDecodeAgn_info16_imm_T_11 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _preDecodeAgn_info16_imm_T_23 = preDecodeAgn_info16_is_branch ? _preDecodeAgn_info16_imm_T_20 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] preDecodeAgn_info16_imm = _preDecodeAgn_info16_imm_T_21 | _preDecodeAgn_info16_imm_T_23; // @[Mux.scala 27:73]
  wire  preDecodeAgn_info32_is_jal = io_if4_req_0_bits_instr[6:0] == 7'h6f; // @[IF3.scala 370:39]
  wire  preDecodeAgn_info32_is_jalr = io_if4_req_0_bits_instr[6:0] == 7'h67; // @[IF3.scala 371:39]
  wire  preDecodeAgn_info32_is_branch = io_if4_req_0_bits_instr[6:0] == 7'h63; // @[IF3.scala 372:39]
  wire [4:0] _preDecodeAgn_info32_is_call_T_2 = io_if4_req_0_bits_instr[11:7] & 5'h1b; // @[IF3.scala 373:78]
  wire  preDecodeAgn_info32_is_call = (preDecodeAgn_info32_is_jal | preDecodeAgn_info32_is_jalr) & 5'h1 ==
    _preDecodeAgn_info32_is_call_T_2; // @[IF3.scala 373:60]
  wire [4:0] _preDecodeAgn_info32_is_return_T_1 = io_if4_req_0_bits_instr[19:15] & 5'h1b; // @[IF3.scala 374:59]
  wire  preDecodeAgn_info32_is_return = preDecodeAgn_info32_is_jalr & 5'h1 == _preDecodeAgn_info32_is_return_T_1 &
    io_if4_req_0_bits_instr[19:15] != io_if4_req_0_bits_instr[11:7]; // @[IF3.scala 374:82]
  wire [43:0] _preDecodeAgn_info32_imm_T_2 = io_if4_req_0_bits_instr[31] ? 44'hfffffffffff : 44'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _preDecodeAgn_info32_imm_T_6 = {_preDecodeAgn_info32_imm_T_2,io_if4_req_0_bits_instr[19:12],
    io_if4_req_0_bits_instr[20],io_if4_req_0_bits_instr[30:21],1'h0}; // @[Cat.scala 33:92]
  wire [51:0] _preDecodeAgn_info32_imm_T_9 = io_if4_req_0_bits_instr[31] ? 52'hfffffffffffff : 52'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _preDecodeAgn_info32_imm_T_11 = {_preDecodeAgn_info32_imm_T_9,io_if4_req_0_bits_instr[31:20]}; // @[Cat.scala 33:92]
  wire [63:0] _preDecodeAgn_info32_imm_T_18 = {_preDecodeAgn_info32_imm_T_9,io_if4_req_0_bits_instr[7],
    io_if4_req_0_bits_instr[30:25],io_if4_req_0_bits_instr[11:8],1'h0}; // @[Cat.scala 33:92]
  wire [63:0] _preDecodeAgn_info32_imm_T_19 = preDecodeAgn_info32_is_jal ? _preDecodeAgn_info32_imm_T_6 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _preDecodeAgn_info32_imm_T_20 = preDecodeAgn_info32_is_jalr ? _preDecodeAgn_info32_imm_T_11 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _preDecodeAgn_info32_imm_T_21 = preDecodeAgn_info32_is_branch ? _preDecodeAgn_info32_imm_T_18 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _preDecodeAgn_info32_imm_T_22 = _preDecodeAgn_info32_imm_T_19 | _preDecodeAgn_info32_imm_T_20; // @[Mux.scala 27:73]
  wire [63:0] preDecodeAgn_info32_imm = _preDecodeAgn_info32_imm_T_22 | _preDecodeAgn_info32_imm_T_21; // @[Mux.scala 27:73]
  wire  preDecodeAgn_0_is_jal = io_if4_req_0_bits_isRVC ? preDecodeAgn_info16_is_jal : preDecodeAgn_info32_is_jal; // @[IF4.scala 58:46]
  wire  preDecodeAgn_0_is_jalr = io_if4_req_0_bits_isRVC ? preDecodeAgn_info16_is_jalr : preDecodeAgn_info32_is_jalr; // @[IF4.scala 58:46]
  wire  preDecodeAgn_0_is_branch = io_if4_req_0_bits_isRVC ? preDecodeAgn_info16_is_branch :
    preDecodeAgn_info32_is_branch; // @[IF4.scala 58:46]
  wire  preDecodeAgn_0_is_call = io_if4_req_0_bits_isRVC ? preDecodeAgn_info16_is_call : preDecodeAgn_info32_is_call; // @[IF4.scala 58:46]
  wire  preDecodeAgn_0_is_return = io_if4_req_0_bits_isRVC ? preDecodeAgn_info16_is_return :
    preDecodeAgn_info32_is_return; // @[IF4.scala 58:46]
  wire [63:0] preDecodeAgn_0_imm = io_if4_req_0_bits_isRVC ? preDecodeAgn_info16_imm : preDecodeAgn_info32_imm; // @[IF4.scala 58:46]
  wire  _tage_decode_T_3 = ~reset; // @[TAGE.scala 262:13]
  wire  _isRedirect_0_T = preDecodeAgn_0_is_branch & bimRedirect_mdl_io_deq_0_bits_bim_p; // @[IF4.scala 123:19]
  wire  _isRedirect_0_T_1 = preDecodeAgn_0_is_branch & bimRedirect_mdl_io_deq_0_bits_bim_p | preDecodeAgn_0_is_jal; // @[IF4.scala 123:35]
  wire  isRedirect_0 = _isRedirect_0_T_1 | preDecodeAgn_0_is_jalr; // @[IF4.scala 124:15]
  wire [38:0] _jalr_pc_T_1 = preDecodeAgn_0_is_return & ras_io_deq_valid ? ras_io_deq_bits_target :
    btbRedirect_mdl_io_deq_0_bits_target; // @[IF4.scala 129:18]
  wire [24:0] _jalr_pc_v64_T_2 = _jalr_pc_T_1[38] ? 25'h1ffffff : 25'h0; // @[Bitwise.scala 77:12]
  wire [63:0] jalr_pc_0 = {_jalr_pc_v64_T_2,_jalr_pc_T_1}; // @[Cat.scala 33:92]
  wire  _ras_io_deq_ready_T = io_if4_req_0_ready & io_if4_req_0_valid; // @[Decoupled.scala 52:35]
  wire [2:0] _ras_io_enq_bits_target_T = io_if4_req_0_bits_isRVC ? 3'h2 : 3'h4; // @[IF4.scala 139:32]
  wire [38:0] _GEN_21 = {{36'd0}, _ras_io_enq_bits_target_T}; // @[IF4.scala 139:27]
  wire [38:0] _ras_io_enq_bits_target_T_2 = io_if4_req_0_bits_pc + _GEN_21; // @[IF4.scala 139:27]
  wire [63:0] _GEN_22 = {{25'd0}, io_if4_req_0_bits_pc}; // @[IF4.scala 146:47]
  wire [63:0] _redirectTarget_0_T_2 = _GEN_22 + preDecodeAgn_0_imm; // @[IF4.scala 146:47]
  wire [63:0] _redirectTarget_0_T_5 = _isRedirect_0_T ? _redirectTarget_0_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _redirectTarget_0_T_6 = preDecodeAgn_0_is_jal ? _redirectTarget_0_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _redirectTarget_0_T_7 = preDecodeAgn_0_is_jalr ? jalr_pc_0 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _redirectTarget_0_T_8 = _redirectTarget_0_T_5 | _redirectTarget_0_T_6; // @[Mux.scala 27:73]
  wire [63:0] redirectTarget_0 = _redirectTarget_0_T_8 | _redirectTarget_0_T_7; // @[Mux.scala 27:73]
  RAS ras ( // @[IF4.scala 49:19]
    .clock(ras_clock),
    .reset(ras_reset),
    .io_enq_valid(ras_io_enq_valid),
    .io_enq_bits_target(ras_io_enq_bits_target),
    .io_deq_ready(ras_io_deq_ready),
    .io_deq_valid(ras_io_deq_valid),
    .io_deq_bits_target(ras_io_deq_bits_target),
    .io_flush(ras_io_flush)
  );
  MultiPortFifo_in1_out1_6 instr_fifo ( // @[IF4.scala 50:26]
    .clock(instr_fifo_clock),
    .reset(instr_fifo_reset),
    .io_enq_0_ready(instr_fifo_io_enq_0_ready),
    .io_enq_0_valid(instr_fifo_io_enq_0_valid),
    .io_deq_0_ready(instr_fifo_io_deq_0_ready),
    .io_deq_0_valid(instr_fifo_io_deq_0_valid),
    .io_flush(instr_fifo_io_flush)
  );
  MultiPortFifo_in1_out1_7 bftq ( // @[IF4.scala 51:20]
    .clock(bftq_clock),
    .reset(bftq_reset),
    .io_enq_0_ready(bftq_io_enq_0_ready),
    .io_enq_0_valid(bftq_io_enq_0_valid),
    .io_deq_0_ready(bftq_io_deq_0_ready),
    .io_deq_0_valid(bftq_io_deq_0_valid),
    .io_flush(bftq_io_flush)
  );
  MultiPortFifo_in1_out1_8 jftq ( // @[IF4.scala 52:20]
    .clock(jftq_clock),
    .reset(jftq_reset),
    .io_enq_0_ready(jftq_io_enq_0_ready),
    .io_enq_0_valid(jftq_io_enq_0_valid),
    .io_deq_0_ready(jftq_io_deq_0_ready),
    .io_deq_0_valid(jftq_io_deq_0_valid),
    .io_flush(jftq_io_flush)
  );
  RePort_4 bRePort ( // @[IF4.scala 55:23]
    .clock(bRePort_clock),
    .reset(bRePort_reset),
    .io_enq_0_ready(bRePort_io_enq_0_ready),
    .io_enq_0_valid(bRePort_io_enq_0_valid),
    .io_deq_0_ready(bRePort_io_deq_0_ready),
    .io_deq_0_valid(bRePort_io_deq_0_valid)
  );
  RePort_5 jRePort ( // @[IF4.scala 56:23]
    .clock(jRePort_clock),
    .reset(jRePort_reset),
    .io_enq_0_ready(jRePort_io_enq_0_ready),
    .io_enq_0_valid(jRePort_io_enq_0_valid),
    .io_deq_0_ready(jRePort_io_deq_0_ready),
    .io_deq_0_valid(jRePort_io_deq_0_valid)
  );
  ReDirect_1 bimRedirect_mdl ( // @[RePort.scala 188:21]
    .io_enq_0_valid(bimRedirect_mdl_io_enq_0_valid),
    .io_enq_0_bits_bim_p(bimRedirect_mdl_io_enq_0_bits_bim_p),
    .io_deq_0_ready(bimRedirect_mdl_io_deq_0_ready),
    .io_deq_0_valid(bimRedirect_mdl_io_deq_0_valid),
    .io_deq_0_bits_bim_p(bimRedirect_mdl_io_deq_0_bits_bim_p),
    .io_mapper_0(bimRedirect_mdl_io_mapper_0)
  );
  ReDirect_2 btbRedirect_mdl ( // @[RePort.scala 188:21]
    .io_enq_0_valid(btbRedirect_mdl_io_enq_0_valid),
    .io_enq_0_bits_target(btbRedirect_mdl_io_enq_0_bits_target),
    .io_deq_0_ready(btbRedirect_mdl_io_deq_0_ready),
    .io_deq_0_valid(btbRedirect_mdl_io_deq_0_valid),
    .io_deq_0_bits_target(btbRedirect_mdl_io_deq_0_bits_target),
    .io_mapper_0(btbRedirect_mdl_io_mapper_0)
  );
  assign io_if4_req_0_ready = bRePort_io_enq_0_ready & jRePort_io_enq_0_ready & instr_fifo_io_enq_0_ready; // @[IF4.scala 254:76]
  assign ras_clock = clock;
  assign ras_reset = reset;
  assign ras_io_enq_valid = preDecodeAgn_0_is_call & _ras_io_deq_ready_T; // @[IF4.scala 135:16]
  assign ras_io_enq_bits_target = preDecodeAgn_0_is_call ? _ras_io_enq_bits_target_T_2 : 39'h0; // @[Mux.scala 101:16]
  assign ras_io_deq_ready = preDecodeAgn_0_is_return & _ras_io_deq_ready_T; // @[IF4.scala 132:65]
  assign ras_io_flush = io_flush; // @[IF4.scala 212:16]
  assign instr_fifo_clock = clock;
  assign instr_fifo_reset = reset;
  assign instr_fifo_io_enq_0_valid = io_if4_req_0_ready & io_if4_req_0_valid; // @[Decoupled.scala 52:35]
  assign instr_fifo_io_deq_0_ready = io_if4_resp_0_ready; // @[IF4.scala 237:15]
  assign instr_fifo_io_flush = io_flush; // @[IF4.scala 264:23]
  assign bftq_clock = clock;
  assign bftq_reset = reset;
  assign bftq_io_enq_0_valid = bRePort_io_deq_0_valid; // @[IF4.scala 241:15]
  assign bftq_io_deq_0_ready = io_bftq_ready; // @[IF4.scala 238:11]
  assign bftq_io_flush = io_flush; // @[IF4.scala 265:17]
  assign jftq_clock = clock;
  assign jftq_reset = reset;
  assign jftq_io_enq_0_valid = jRePort_io_deq_0_valid; // @[IF4.scala 242:15]
  assign jftq_io_deq_0_ready = io_jftq_ready; // @[IF4.scala 239:11]
  assign jftq_io_flush = io_flush; // @[IF4.scala 266:17]
  assign bRePort_clock = clock;
  assign bRePort_reset = reset;
  assign bRePort_io_enq_0_valid = _ras_io_deq_ready_T & preDecodeAgn_0_is_branch; // @[IF4.scala 247:51]
  assign bRePort_io_deq_0_ready = bftq_io_enq_0_ready; // @[IF4.scala 241:15]
  assign jRePort_clock = clock;
  assign jRePort_reset = reset;
  assign jRePort_io_enq_0_valid = _ras_io_deq_ready_T & preDecodeAgn_0_is_jalr; // @[IF4.scala 248:51]
  assign jRePort_io_deq_0_ready = jftq_io_enq_0_ready; // @[IF4.scala 242:15]
  assign bimRedirect_mdl_io_enq_0_valid = io_bimResp_0_valid; // @[RePort.scala 190:9]
  assign bimRedirect_mdl_io_enq_0_bits_bim_p = io_bimResp_0_bits_bim_p; // @[RePort.scala 190:9]
  assign bimRedirect_mdl_io_deq_0_ready = preDecodeAgn_0_is_branch & _ras_io_deq_ready_T; // @[IF4.scala 221:43]
  assign bimRedirect_mdl_io_mapper_0 = io_if4_req_0_bits_isRVC ? preDecodeAgn_info16_is_branch :
    preDecodeAgn_info32_is_branch; // @[IF4.scala 58:46]
  assign btbRedirect_mdl_io_enq_0_valid = io_btbResp_0_valid; // @[RePort.scala 190:9]
  assign btbRedirect_mdl_io_enq_0_bits_target = io_btbResp_0_bits_target; // @[RePort.scala 190:9]
  assign btbRedirect_mdl_io_deq_0_ready = preDecodeAgn_0_is_jalr & _ras_io_deq_ready_T; // @[IF4.scala 220:43]
  assign btbRedirect_mdl_io_mapper_0 = io_if4_req_0_bits_isRVC ? preDecodeAgn_info16_is_jalr :
    preDecodeAgn_info32_is_jalr; // @[IF4.scala 58:46]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _tage_decode_T_3) begin
          $fatal; // @[TAGE.scala 264:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~isRedirect_0 & _tage_decode_T_3 & ~(redirectTarget_0 == 64'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF4.scala:173 when( ~isRedirect(i) ) { assert( redirectTarget(i) === 0.U ) }\n"); // @[IF4.scala 173:36]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(redirectTarget_0 == 64'h0) & (~isRedirect_0 & _tage_decode_T_3)) begin
          $fatal; // @[IF4.scala 173:36]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_if4_req_0_valid & ~io_if4_req_0_bits_isRedirect & _tage_decode_T_3 & ~(io_if4_req_0_bits_target == 39'h0)
          ) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF4.scala:174 when( io.if4_req(i).valid & ~io.if4_req(i).bits.isRedirect ) { assert( io.if4_req(i).bits.target === 0.U ) }\n"
            ); // @[IF4.scala 174:74]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(io_if4_req_0_bits_target == 39'h0) & (io_if4_req_0_valid & ~io_if4_req_0_bits_isRedirect &
          _tage_decode_T_3)) begin
          $fatal; // @[IF4.scala 174:74]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_tage_decode_T_3 & ~(~(btbRedirect_mdl_io_deq_0_ready & ~btbRedirect_mdl_io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF4.scala:224 assert( ~(btbRedirect(i).ready  & ~btbRedirect(i).valid) )\n"); // @[IF4.scala 224:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(btbRedirect_mdl_io_deq_0_ready & ~btbRedirect_mdl_io_deq_0_valid)) & _tage_decode_T_3) begin
          $fatal; // @[IF4.scala 224:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_tage_decode_T_3 & ~(~(bimRedirect_mdl_io_deq_0_ready & ~bimRedirect_mdl_io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF4.scala:225 assert( ~(bimRedirect(i).ready  & ~bimRedirect(i).valid) )\n"); // @[IF4.scala 225:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(bimRedirect_mdl_io_deq_0_ready & ~bimRedirect_mdl_io_deq_0_valid)) & _tage_decode_T_3) begin
          $fatal; // @[IF4.scala 225:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module RePort_6(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  assign io_enq_0_ready = io_deq_0_ready; // @[RePort.scala 80:69]
  assign io_deq_0_valid = _T > 1'h0; // @[RePort.scala 79:81]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T == _T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T == _T_1) & ~reset) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module MultiPortFifo_in1_out1_9(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = _io_enq_0_ready_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_6 = _T ? ~_io_enq_0_ready_T[0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_7 = _T ? _io_enq_0_ready_T[0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _rd_ptr_T_2 = rd_ptr + _T_1; // @[MultiPortFifo.scala 106:26]
  wire  _wr_ptr_T_2 = wr_ptr + _T; // @[MultiPortFifo.scala 107:26]
  wire  _T_9 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_enq_0_ready = ~_GEN_1; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = _io_deq_0_valid_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_6;
      end
    end else begin
      buf_valid_0 <= _GEN_6;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_7;
      end
    end else begin
      buf_valid_1 <= _GEN_7;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else begin
      rd_ptr <= _rd_ptr_T_2;
    end
    if (reset) begin // @[MultiPortFifo.scala 61:27]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else begin
      wr_ptr <= _wr_ptr_T_2;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rd_ptr = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wr_ptr = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MultiPortFifo_in1_out1_10(
  input   clock,
  input   reset,
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_deq_0_ready,
  output  io_deq_0_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg  buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] _io_enq_0_ready_T = {{1'd0}, wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  _GEN_1 = _io_enq_0_ready_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] _io_deq_0_valid_T = {{1'd0}, rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  _T = io_enq_0_ready & io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_6 = _T ? ~_io_enq_0_ready_T[0] | buf_valid_0 : buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _GEN_7 = _T ? _io_enq_0_ready_T[0] | buf_valid_1 : buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  _T_1 = io_deq_0_ready & io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _rd_ptr_T_2 = rd_ptr + _T_1; // @[MultiPortFifo.scala 106:26]
  wire  _wr_ptr_T_2 = wr_ptr + _T; // @[MultiPortFifo.scala 107:26]
  wire  _T_9 = ~reset; // @[MultiPortFifo.scala 161:13]
  assign io_enq_0_ready = ~_GEN_1; // @[MultiPortFifo.scala 64:94]
  assign io_deq_0_valid = _io_deq_0_valid_T[0] ? buf_valid_1 : buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  always @(posedge clock) begin
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_0 <= _GEN_6;
      end
    end else begin
      buf_valid_0 <= _GEN_6;
    end
    if (reset) begin // @[MultiPortFifo.scala 58:30]
      buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (_T_1) begin // @[MultiPortFifo.scala 98:34]
      if (_io_deq_0_valid_T[0]) begin // @[MultiPortFifo.scala 98:57]
        buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        buf_valid_1 <= _GEN_7;
      end
    end else begin
      buf_valid_1 <= _GEN_7;
    end
    if (reset) begin // @[MultiPortFifo.scala 60:27]
      rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else begin
      rd_ptr <= _rd_ptr_T_2;
    end
    if (reset) begin // @[MultiPortFifo.scala 61:27]
      wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else begin
      wr_ptr <= _wr_ptr_T_2;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_enq_0_valid & ~io_enq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_enq_0_valid & ~io_enq_0_valid)) & ~reset) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(io_deq_0_valid & ~io_deq_0_valid))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_deq_0_valid & ~io_deq_0_valid)) & _T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buf_valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rd_ptr = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wr_ptr = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Rename(
  input   clock,
  input   reset,
  output  io_rnReq_0_ready,
  input   io_rnReq_0_valid,
  input   io_rnReq_0_bits_lsu_isa_flw,
  input   io_rnReq_0_bits_lsu_isa_fld,
  input   io_rnReq_0_bits_privil_isa_ecall,
  input   io_rnReq_0_bits_privil_isa_ebreak,
  input   io_rnReq_0_bits_privil_isa_mret,
  input   io_rnReq_0_bits_privil_isa_uret,
  input   io_rnReq_0_bits_privil_isa_sret,
  input   io_rnReq_0_bits_privil_isa_dret,
  input   io_rnReq_0_bits_privil_isa_hfence_vvma,
  input   io_rnReq_0_bits_privil_isa_hfence_gvma,
  input   io_rnReq_0_bits_privil_isa_hlv_b,
  input   io_rnReq_0_bits_privil_isa_hlv_bu,
  input   io_rnReq_0_bits_privil_isa_hlv_h,
  input   io_rnReq_0_bits_privil_isa_hlv_hu,
  input   io_rnReq_0_bits_privil_isa_hlvx_hu,
  input   io_rnReq_0_bits_privil_isa_hlv_w,
  input   io_rnReq_0_bits_privil_isa_hlvx_wu,
  input   io_rnReq_0_bits_privil_isa_hsv_b,
  input   io_rnReq_0_bits_privil_isa_hsv_h,
  input   io_rnReq_0_bits_privil_isa_hsv_w,
  input   io_rnReq_0_bits_privil_isa_hlv_wu,
  input   io_rnReq_0_bits_privil_isa_hlv_d,
  input   io_rnReq_0_bits_privil_isa_hsv_d,
  input   io_rnReq_0_bits_privil_isa_is_access_fault,
  input   io_rnReq_0_bits_privil_isa_is_paging_fault,
  input   io_rnReq_0_bits_fpu_isa_fmadd_s,
  input   io_rnReq_0_bits_fpu_isa_fmsub_s,
  input   io_rnReq_0_bits_fpu_isa_fnmsub_s,
  input   io_rnReq_0_bits_fpu_isa_fnmadd_s,
  input   io_rnReq_0_bits_fpu_isa_fadd_s,
  input   io_rnReq_0_bits_fpu_isa_fsub_s,
  input   io_rnReq_0_bits_fpu_isa_fmul_s,
  input   io_rnReq_0_bits_fpu_isa_fdiv_s,
  input   io_rnReq_0_bits_fpu_isa_fsqrt_s,
  input   io_rnReq_0_bits_fpu_isa_fsgnj_s,
  input   io_rnReq_0_bits_fpu_isa_fsgnjn_s,
  input   io_rnReq_0_bits_fpu_isa_fsgnjx_s,
  input   io_rnReq_0_bits_fpu_isa_fmin_s,
  input   io_rnReq_0_bits_fpu_isa_fmax_s,
  input   io_rnReq_0_bits_fpu_isa_fcvt_w_s,
  input   io_rnReq_0_bits_fpu_isa_fcvt_wu_s,
  input   io_rnReq_0_bits_fpu_isa_fmv_x_w,
  input   io_rnReq_0_bits_fpu_isa_feq_s,
  input   io_rnReq_0_bits_fpu_isa_flt_s,
  input   io_rnReq_0_bits_fpu_isa_fle_s,
  input   io_rnReq_0_bits_fpu_isa_fclass_s,
  input   io_rnReq_0_bits_fpu_isa_fcvt_s_w,
  input   io_rnReq_0_bits_fpu_isa_fcvt_s_wu,
  input   io_rnReq_0_bits_fpu_isa_fmv_w_x,
  input   io_rnReq_0_bits_fpu_isa_fcvt_l_s,
  input   io_rnReq_0_bits_fpu_isa_fcvt_lu_s,
  input   io_rnReq_0_bits_fpu_isa_fcvt_s_l,
  input   io_rnReq_0_bits_fpu_isa_fcvt_s_lu,
  input   io_rnReq_0_bits_fpu_isa_fmadd_d,
  input   io_rnReq_0_bits_fpu_isa_fmsub_d,
  input   io_rnReq_0_bits_fpu_isa_fnmsub_d,
  input   io_rnReq_0_bits_fpu_isa_fnmadd_d,
  input   io_rnReq_0_bits_fpu_isa_fadd_d,
  input   io_rnReq_0_bits_fpu_isa_fsub_d,
  input   io_rnReq_0_bits_fpu_isa_fmul_d,
  input   io_rnReq_0_bits_fpu_isa_fdiv_d,
  input   io_rnReq_0_bits_fpu_isa_fsqrt_d,
  input   io_rnReq_0_bits_fpu_isa_fsgnj_d,
  input   io_rnReq_0_bits_fpu_isa_fsgnjn_d,
  input   io_rnReq_0_bits_fpu_isa_fsgnjx_d,
  input   io_rnReq_0_bits_fpu_isa_fmin_d,
  input   io_rnReq_0_bits_fpu_isa_fmax_d,
  input   io_rnReq_0_bits_fpu_isa_fcvt_s_d,
  input   io_rnReq_0_bits_fpu_isa_fcvt_d_s,
  input   io_rnReq_0_bits_fpu_isa_feq_d,
  input   io_rnReq_0_bits_fpu_isa_flt_d,
  input   io_rnReq_0_bits_fpu_isa_fle_d,
  input   io_rnReq_0_bits_fpu_isa_fclass_d,
  input   io_rnReq_0_bits_fpu_isa_fcvt_w_d,
  input   io_rnReq_0_bits_fpu_isa_fcvt_wu_d,
  input   io_rnReq_0_bits_fpu_isa_fcvt_d_w,
  input   io_rnReq_0_bits_fpu_isa_fcvt_d_wu,
  input   io_rnReq_0_bits_fpu_isa_fcvt_l_d,
  input   io_rnReq_0_bits_fpu_isa_fcvt_lu_d,
  input   io_rnReq_0_bits_fpu_isa_fmv_x_d,
  input   io_rnReq_0_bits_fpu_isa_fcvt_d_l,
  input   io_rnReq_0_bits_fpu_isa_fcvt_d_lu,
  input   io_rnReq_0_bits_fpu_isa_fmv_d_x,
  input   io_rnReq_0_bits_fpu_isa_fcsr_rw,
  input   io_rnReq_0_bits_fpu_isa_fcsr_rs,
  input   io_rnReq_0_bits_fpu_isa_fcsr_rc,
  input   io_rnReq_0_bits_fpu_isa_fcsr_rwi,
  input   io_rnReq_0_bits_fpu_isa_fcsr_rsi,
  input   io_rnReq_0_bits_fpu_isa_fcsr_rci,
  input   io_rnRsp_0_ready,
  input   io_xRename_0_req_ready,
  output  io_xRename_0_req_valid,
  input   io_fRename_0_req_ready,
  output  io_fRename_0_req_valid,
  input   io_rod_i_0_ready
);
  wire  rnRspReport_clock; // @[Rename.scala 42:27]
  wire  rnRspReport_reset; // @[Rename.scala 42:27]
  wire  rnRspReport_io_enq_0_ready; // @[Rename.scala 42:27]
  wire  rnRspReport_io_enq_0_valid; // @[Rename.scala 42:27]
  wire  rnRspReport_io_deq_0_ready; // @[Rename.scala 42:27]
  wire  rnRspReport_io_deq_0_valid; // @[Rename.scala 42:27]
  wire  rnRspFifo_clock; // @[Rename.scala 43:25]
  wire  rnRspFifo_reset; // @[Rename.scala 43:25]
  wire  rnRspFifo_io_enq_0_ready; // @[Rename.scala 43:25]
  wire  rnRspFifo_io_enq_0_valid; // @[Rename.scala 43:25]
  wire  rnRspFifo_io_deq_0_ready; // @[Rename.scala 43:25]
  wire  rnRspFifo_io_deq_0_valid; // @[Rename.scala 43:25]
  wire  reOrder_fifo_i_clock; // @[Rename.scala 48:21]
  wire  reOrder_fifo_i_reset; // @[Rename.scala 48:21]
  wire  reOrder_fifo_i_io_enq_0_ready; // @[Rename.scala 48:21]
  wire  reOrder_fifo_i_io_enq_0_valid; // @[Rename.scala 48:21]
  wire  reOrder_fifo_i_io_deq_0_ready; // @[Rename.scala 48:21]
  wire  reOrder_fifo_i_io_deq_0_valid; // @[Rename.scala 48:21]
  wire  _rnRspReport_io_enq_0_valid_T = io_rnReq_0_ready & io_rnReq_0_valid; // @[Decoupled.scala 52:35]
  wire  _rnRspReport_io_enq_0_valid_T_21 = io_rnReq_0_bits_privil_isa_ecall | io_rnReq_0_bits_privil_isa_ebreak |
    io_rnReq_0_bits_privil_isa_mret | io_rnReq_0_bits_privil_isa_uret | io_rnReq_0_bits_privil_isa_sret |
    io_rnReq_0_bits_privil_isa_dret | io_rnReq_0_bits_privil_isa_hfence_vvma | io_rnReq_0_bits_privil_isa_hfence_gvma |
    io_rnReq_0_bits_privil_isa_hlv_b | io_rnReq_0_bits_privil_isa_hlv_bu | io_rnReq_0_bits_privil_isa_hlv_h |
    io_rnReq_0_bits_privil_isa_hlv_hu | io_rnReq_0_bits_privil_isa_hlvx_hu | io_rnReq_0_bits_privil_isa_hlv_w |
    io_rnReq_0_bits_privil_isa_hlvx_wu | io_rnReq_0_bits_privil_isa_hsv_b | io_rnReq_0_bits_privil_isa_hsv_h |
    io_rnReq_0_bits_privil_isa_hsv_w | io_rnReq_0_bits_privil_isa_hlv_wu | io_rnReq_0_bits_privil_isa_hlv_d |
    io_rnReq_0_bits_privil_isa_hsv_d | io_rnReq_0_bits_privil_isa_is_access_fault; // @[riscv_isa.scala 248:187]
  wire  _rnRspReport_io_enq_0_valid_T_22 = _rnRspReport_io_enq_0_valid_T_21 | io_rnReq_0_bits_privil_isa_is_paging_fault
    ; // @[riscv_isa.scala 249:21]
  wire  _io_xRename_0_req_valid_T_1 = io_rnReq_0_bits_lsu_isa_flw | io_rnReq_0_bits_lsu_isa_fld; // @[riscv_isa.scala 166:20]
  wire  _io_xRename_0_req_valid_T_10 = io_rnReq_0_bits_fpu_isa_fmadd_s | io_rnReq_0_bits_fpu_isa_fmsub_s |
    io_rnReq_0_bits_fpu_isa_fnmsub_s | io_rnReq_0_bits_fpu_isa_fnmadd_s | io_rnReq_0_bits_fpu_isa_fadd_s |
    io_rnReq_0_bits_fpu_isa_fsub_s | io_rnReq_0_bits_fpu_isa_fmul_s | io_rnReq_0_bits_fpu_isa_fdiv_s |
    io_rnReq_0_bits_fpu_isa_fsqrt_s | io_rnReq_0_bits_fpu_isa_fmadd_d; // @[riscv_isa.scala 414:91]
  wire  _io_xRename_0_req_valid_T_19 = _io_xRename_0_req_valid_T_10 | io_rnReq_0_bits_fpu_isa_fmsub_d |
    io_rnReq_0_bits_fpu_isa_fnmsub_d | io_rnReq_0_bits_fpu_isa_fnmadd_d | io_rnReq_0_bits_fpu_isa_fadd_d |
    io_rnReq_0_bits_fpu_isa_fsub_d | io_rnReq_0_bits_fpu_isa_fmul_d | io_rnReq_0_bits_fpu_isa_fdiv_d |
    io_rnReq_0_bits_fpu_isa_fsqrt_d | io_rnReq_0_bits_fpu_isa_fsgnj_s; // @[riscv_isa.scala 415:91]
  wire  _io_xRename_0_req_valid_T_22 = _io_xRename_0_req_valid_T_19 | io_rnReq_0_bits_fpu_isa_fsgnjn_s |
    io_rnReq_0_bits_fpu_isa_fsgnjx_s | io_rnReq_0_bits_fpu_isa_fsgnj_d; // @[riscv_isa.scala 416:35]
  wire  _io_xRename_0_req_valid_T_25 = _io_xRename_0_req_valid_T_22 | io_rnReq_0_bits_fpu_isa_fsgnjn_d |
    io_rnReq_0_bits_fpu_isa_fsgnjx_d | io_rnReq_0_bits_fpu_isa_fmin_s; // @[riscv_isa.scala 417:35]
  wire  _io_xRename_0_req_valid_T_28 = _io_xRename_0_req_valid_T_25 | io_rnReq_0_bits_fpu_isa_fmax_s |
    io_rnReq_0_bits_fpu_isa_fmin_d | io_rnReq_0_bits_fpu_isa_fmax_d; // @[riscv_isa.scala 418:30]
  wire  _io_xRename_0_req_valid_T_29 = _io_xRename_0_req_valid_T_25 | io_rnReq_0_bits_fpu_isa_fmax_s |
    io_rnReq_0_bits_fpu_isa_fmin_d | io_rnReq_0_bits_fpu_isa_fmax_d | io_rnReq_0_bits_fpu_isa_fcvt_s_w; // @[riscv_isa.scala 418:39]
  wire  _io_xRename_0_req_valid_T_33 = _io_xRename_0_req_valid_T_29 | io_rnReq_0_bits_fpu_isa_fcvt_s_wu |
    io_rnReq_0_bits_fpu_isa_fcvt_d_w | io_rnReq_0_bits_fpu_isa_fcvt_d_wu | io_rnReq_0_bits_fpu_isa_fcvt_s_l; // @[riscv_isa.scala 419:49]
  wire  _io_xRename_0_req_valid_T_37 = _io_xRename_0_req_valid_T_33 | io_rnReq_0_bits_fpu_isa_fcvt_s_lu |
    io_rnReq_0_bits_fpu_isa_fcvt_d_l | io_rnReq_0_bits_fpu_isa_fcvt_d_lu | io_rnReq_0_bits_fpu_isa_fcvt_s_d; // @[riscv_isa.scala 420:49]
  wire  _io_xRename_0_req_valid_T_39 = _io_xRename_0_req_valid_T_37 | io_rnReq_0_bits_fpu_isa_fcvt_d_s |
    io_rnReq_0_bits_fpu_isa_fmv_w_x; // @[riscv_isa.scala 421:25]
  wire  _io_xRename_0_req_valid_T_40 = _io_xRename_0_req_valid_T_39 | io_rnReq_0_bits_fpu_isa_fmv_d_x; // @[riscv_isa.scala 422:13]
  wire  _io_xRename_0_req_valid_T_41 = _io_xRename_0_req_valid_T_1 | _io_xRename_0_req_valid_T_40; // @[riscv_isa.scala 794:20]
  wire  _io_xRename_0_req_valid_T_42 = ~_io_xRename_0_req_valid_T_41; // @[riscv_isa.scala 800:16]
  wire  _T = io_fRename_0_req_ready & io_fRename_0_req_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = io_xRename_0_req_ready & io_xRename_0_req_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _T_2 = _T + _T_1; // @[Bitwise.scala 51:90]
  wire  _T_6 = ~reset; // @[Rename.scala 84:40]
  wire  _T_36 = _io_xRename_0_req_valid_T_28 | io_rnReq_0_bits_fpu_isa_feq_s; // @[riscv_isa.scala 517:49]
  wire  _T_42 = _T_36 | io_rnReq_0_bits_fpu_isa_flt_s | io_rnReq_0_bits_fpu_isa_fle_s | io_rnReq_0_bits_fpu_isa_feq_d |
    io_rnReq_0_bits_fpu_isa_flt_d | io_rnReq_0_bits_fpu_isa_fle_d | io_rnReq_0_bits_fpu_isa_fclass_s; // @[riscv_isa.scala 518:73]
  wire  _T_44 = _T_42 | io_rnReq_0_bits_fpu_isa_fclass_d | io_rnReq_0_bits_fpu_isa_fmv_x_w; // @[riscv_isa.scala 519:25]
  wire  _T_48 = _T_44 | io_rnReq_0_bits_fpu_isa_fmv_w_x | io_rnReq_0_bits_fpu_isa_fmv_x_d |
    io_rnReq_0_bits_fpu_isa_fmv_d_x | io_rnReq_0_bits_fpu_isa_fcvt_s_w; // @[riscv_isa.scala 520:49]
  wire  _T_52 = _T_48 | io_rnReq_0_bits_fpu_isa_fcvt_s_wu | io_rnReq_0_bits_fpu_isa_fcvt_l_s |
    io_rnReq_0_bits_fpu_isa_fcvt_lu_s | io_rnReq_0_bits_fpu_isa_fcvt_s_l; // @[riscv_isa.scala 521:49]
  wire  _T_56 = _T_52 | io_rnReq_0_bits_fpu_isa_fcvt_s_lu | io_rnReq_0_bits_fpu_isa_fcvt_s_d |
    io_rnReq_0_bits_fpu_isa_fcvt_d_s | io_rnReq_0_bits_fpu_isa_fcvt_w_d; // @[riscv_isa.scala 522:49]
  wire  _T_62 = _T_56 | io_rnReq_0_bits_fpu_isa_fcvt_wu_d | io_rnReq_0_bits_fpu_isa_fcvt_d_w |
    io_rnReq_0_bits_fpu_isa_fcvt_d_wu | io_rnReq_0_bits_fpu_isa_fcvt_l_d | io_rnReq_0_bits_fpu_isa_fcvt_lu_d |
    io_rnReq_0_bits_fpu_isa_fcvt_d_l; // @[riscv_isa.scala 523:73]
  wire  _T_66 = _T_62 | io_rnReq_0_bits_fpu_isa_fcvt_d_lu | io_rnReq_0_bits_fpu_isa_fcvt_w_s |
    io_rnReq_0_bits_fpu_isa_fcvt_wu_s | io_rnReq_0_bits_fpu_isa_fcsr_rw; // @[riscv_isa.scala 524:49]
  wire  _T_71 = _T_66 | io_rnReq_0_bits_fpu_isa_fcsr_rs | io_rnReq_0_bits_fpu_isa_fcsr_rc |
    io_rnReq_0_bits_fpu_isa_fcsr_rwi | io_rnReq_0_bits_fpu_isa_fcsr_rsi | io_rnReq_0_bits_fpu_isa_fcsr_rci; // @[riscv_isa.scala 525:61]
  wire  _GEN_0 = _rnRspReport_io_enq_0_valid_T & _T_6; // @[Rename.scala 157:15]
  RePort_6 rnRspReport ( // @[Rename.scala 42:27]
    .clock(rnRspReport_clock),
    .reset(rnRspReport_reset),
    .io_enq_0_ready(rnRspReport_io_enq_0_ready),
    .io_enq_0_valid(rnRspReport_io_enq_0_valid),
    .io_deq_0_ready(rnRspReport_io_deq_0_ready),
    .io_deq_0_valid(rnRspReport_io_deq_0_valid)
  );
  MultiPortFifo_in1_out1_9 rnRspFifo ( // @[Rename.scala 43:25]
    .clock(rnRspFifo_clock),
    .reset(rnRspFifo_reset),
    .io_enq_0_ready(rnRspFifo_io_enq_0_ready),
    .io_enq_0_valid(rnRspFifo_io_enq_0_valid),
    .io_deq_0_ready(rnRspFifo_io_deq_0_ready),
    .io_deq_0_valid(rnRspFifo_io_deq_0_valid)
  );
  MultiPortFifo_in1_out1_10 reOrder_fifo_i ( // @[Rename.scala 48:21]
    .clock(reOrder_fifo_i_clock),
    .reset(reOrder_fifo_i_reset),
    .io_enq_0_ready(reOrder_fifo_i_io_enq_0_ready),
    .io_enq_0_valid(reOrder_fifo_i_io_enq_0_valid),
    .io_deq_0_ready(reOrder_fifo_i_io_deq_0_ready),
    .io_deq_0_valid(reOrder_fifo_i_io_deq_0_valid)
  );
  assign io_rnReq_0_ready = io_xRename_0_req_ready & io_fRename_0_req_ready & reOrder_fifo_i_io_enq_0_ready &
    rnRspFifo_io_enq_0_ready; // @[Rename.scala 91:92]
  assign io_xRename_0_req_valid = _rnRspReport_io_enq_0_valid_T & _io_xRename_0_req_valid_T_42; // @[Rename.scala 60:52]
  assign io_fRename_0_req_valid = _rnRspReport_io_enq_0_valid_T & _io_xRename_0_req_valid_T_41; // @[Rename.scala 67:52]
  assign rnRspReport_clock = clock;
  assign rnRspReport_reset = reset;
  assign rnRspReport_io_enq_0_valid = _rnRspReport_io_enq_0_valid_T & ~_rnRspReport_io_enq_0_valid_T_22; // @[Rename.scala 57:53]
  assign rnRspReport_io_deq_0_ready = rnRspFifo_io_enq_0_ready; // @[Rename.scala 44:20]
  assign rnRspFifo_clock = clock;
  assign rnRspFifo_reset = reset;
  assign rnRspFifo_io_enq_0_valid = rnRspReport_io_deq_0_valid; // @[Rename.scala 44:20]
  assign rnRspFifo_io_deq_0_ready = io_rnRsp_0_ready; // @[Rename.scala 45:20]
  assign reOrder_fifo_i_clock = clock;
  assign reOrder_fifo_i_reset = reset;
  assign reOrder_fifo_i_io_enq_0_valid = io_rnReq_0_ready & io_rnReq_0_valid; // @[Decoupled.scala 52:35]
  assign reOrder_fifo_i_io_deq_0_ready = io_rod_i_0_ready; // @[Rename.scala 49:16]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_2 <= 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, rename should be one-hot\n    at Rename.scala:84 for ( j <- 0 until rnChn ) { assert( PopCount( Seq(io.fRename(j).req.fire, io.xRename(j).req.fire)) <= 1.U, \"Assert Failed, rename should be one-hot\" ) }\n"
            ); // @[Rename.scala 84:40]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_2 <= 2'h1) & ~reset) begin
          $fatal; // @[Rename.scala 84:40]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_rnRspReport_io_enq_0_valid_T & _T_6 & ~(~_T_71)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Rename.scala:157 assert(io.rnReq(i).bits.fpu_isa.is_fpu === false.B)\n"); // @[Rename.scala 157:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_T_71) & (_rnRspReport_io_enq_0_valid_T & _T_6)) begin
          $fatal; // @[Rename.scala 157:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_0 & ~_io_xRename_0_req_valid_T_42) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Rename.scala:158 assert(io.rnReq(i).bits.is_fwb === false.B)\n"
            ); // @[Rename.scala 158:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_io_xRename_0_req_valid_T_42 & (_rnRspReport_io_enq_0_valid_T & _T_6)) begin
          $fatal; // @[Rename.scala 158:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module Queue_2(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_22 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_22 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_3(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_25 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_25 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_4(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_23 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_23 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_5(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_15 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_15 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_6(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_52 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_52 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Issue(
  input        clock,
  input        reset,
  output       io_dptReq_0_ready,
  input        io_dptReq_0_valid,
  input        io_dptReq_0_bits_alu_isa_lui,
  input        io_dptReq_0_bits_alu_isa_auipc,
  input        io_dptReq_0_bits_alu_isa_addi,
  input        io_dptReq_0_bits_alu_isa_addiw,
  input        io_dptReq_0_bits_alu_isa_slti,
  input        io_dptReq_0_bits_alu_isa_sltiu,
  input        io_dptReq_0_bits_alu_isa_xori,
  input        io_dptReq_0_bits_alu_isa_ori,
  input        io_dptReq_0_bits_alu_isa_andi,
  input        io_dptReq_0_bits_alu_isa_slli,
  input        io_dptReq_0_bits_alu_isa_slliw,
  input        io_dptReq_0_bits_alu_isa_srli,
  input        io_dptReq_0_bits_alu_isa_srliw,
  input        io_dptReq_0_bits_alu_isa_srai,
  input        io_dptReq_0_bits_alu_isa_sraiw,
  input        io_dptReq_0_bits_alu_isa_add,
  input        io_dptReq_0_bits_alu_isa_addw,
  input        io_dptReq_0_bits_alu_isa_sub,
  input        io_dptReq_0_bits_alu_isa_subw,
  input        io_dptReq_0_bits_alu_isa_sll,
  input        io_dptReq_0_bits_alu_isa_sllw,
  input        io_dptReq_0_bits_alu_isa_slt,
  input        io_dptReq_0_bits_alu_isa_sltu,
  input        io_dptReq_0_bits_alu_isa_xor,
  input        io_dptReq_0_bits_alu_isa_srl,
  input        io_dptReq_0_bits_alu_isa_srlw,
  input        io_dptReq_0_bits_alu_isa_sra,
  input        io_dptReq_0_bits_alu_isa_sraw,
  input        io_dptReq_0_bits_alu_isa_or,
  input        io_dptReq_0_bits_alu_isa_and,
  input        io_dptReq_0_bits_alu_isa_wfi,
  input        io_dptReq_0_bits_bru_isa_jal,
  input        io_dptReq_0_bits_bru_isa_jalr,
  input        io_dptReq_0_bits_bru_isa_beq,
  input        io_dptReq_0_bits_bru_isa_bne,
  input        io_dptReq_0_bits_bru_isa_blt,
  input        io_dptReq_0_bits_bru_isa_bge,
  input        io_dptReq_0_bits_bru_isa_bltu,
  input        io_dptReq_0_bits_bru_isa_bgeu,
  input        io_dptReq_0_bits_lsu_isa_lb,
  input        io_dptReq_0_bits_lsu_isa_lh,
  input        io_dptReq_0_bits_lsu_isa_lw,
  input        io_dptReq_0_bits_lsu_isa_ld,
  input        io_dptReq_0_bits_lsu_isa_lbu,
  input        io_dptReq_0_bits_lsu_isa_lhu,
  input        io_dptReq_0_bits_lsu_isa_lwu,
  input        io_dptReq_0_bits_lsu_isa_sb,
  input        io_dptReq_0_bits_lsu_isa_sh,
  input        io_dptReq_0_bits_lsu_isa_sw,
  input        io_dptReq_0_bits_lsu_isa_sd,
  input        io_dptReq_0_bits_lsu_isa_fence,
  input        io_dptReq_0_bits_lsu_isa_fence_i,
  input        io_dptReq_0_bits_lsu_isa_sfence_vma,
  input        io_dptReq_0_bits_lsu_isa_lr_w,
  input        io_dptReq_0_bits_lsu_isa_sc_w,
  input        io_dptReq_0_bits_lsu_isa_amoswap_w,
  input        io_dptReq_0_bits_lsu_isa_amoadd_w,
  input        io_dptReq_0_bits_lsu_isa_amoxor_w,
  input        io_dptReq_0_bits_lsu_isa_amoand_w,
  input        io_dptReq_0_bits_lsu_isa_amoor_w,
  input        io_dptReq_0_bits_lsu_isa_amomin_w,
  input        io_dptReq_0_bits_lsu_isa_amomax_w,
  input        io_dptReq_0_bits_lsu_isa_amominu_w,
  input        io_dptReq_0_bits_lsu_isa_amomaxu_w,
  input        io_dptReq_0_bits_lsu_isa_lr_d,
  input        io_dptReq_0_bits_lsu_isa_sc_d,
  input        io_dptReq_0_bits_lsu_isa_amoswap_d,
  input        io_dptReq_0_bits_lsu_isa_amoadd_d,
  input        io_dptReq_0_bits_lsu_isa_amoxor_d,
  input        io_dptReq_0_bits_lsu_isa_amoand_d,
  input        io_dptReq_0_bits_lsu_isa_amoor_d,
  input        io_dptReq_0_bits_lsu_isa_amomin_d,
  input        io_dptReq_0_bits_lsu_isa_amomax_d,
  input        io_dptReq_0_bits_lsu_isa_amominu_d,
  input        io_dptReq_0_bits_lsu_isa_amomaxu_d,
  input        io_dptReq_0_bits_lsu_isa_flw,
  input        io_dptReq_0_bits_lsu_isa_fsw,
  input        io_dptReq_0_bits_lsu_isa_fld,
  input        io_dptReq_0_bits_lsu_isa_fsd,
  input        io_dptReq_0_bits_csr_isa_rw,
  input        io_dptReq_0_bits_csr_isa_rs,
  input        io_dptReq_0_bits_csr_isa_rc,
  input        io_dptReq_0_bits_csr_isa_rwi,
  input        io_dptReq_0_bits_csr_isa_rsi,
  input        io_dptReq_0_bits_csr_isa_rci,
  input        io_dptReq_0_bits_mul_isa_mul,
  input        io_dptReq_0_bits_mul_isa_mulh,
  input        io_dptReq_0_bits_mul_isa_mulhsu,
  input        io_dptReq_0_bits_mul_isa_mulhu,
  input        io_dptReq_0_bits_mul_isa_div,
  input        io_dptReq_0_bits_mul_isa_divu,
  input        io_dptReq_0_bits_mul_isa_rem,
  input        io_dptReq_0_bits_mul_isa_remu,
  input        io_dptReq_0_bits_mul_isa_mulw,
  input        io_dptReq_0_bits_mul_isa_divw,
  input        io_dptReq_0_bits_mul_isa_divuw,
  input        io_dptReq_0_bits_mul_isa_remw,
  input        io_dptReq_0_bits_mul_isa_remuw,
  input        io_dptReq_0_bits_fpu_isa_fmadd_s,
  input        io_dptReq_0_bits_fpu_isa_fmsub_s,
  input        io_dptReq_0_bits_fpu_isa_fnmsub_s,
  input        io_dptReq_0_bits_fpu_isa_fnmadd_s,
  input        io_dptReq_0_bits_fpu_isa_fadd_s,
  input        io_dptReq_0_bits_fpu_isa_fsub_s,
  input        io_dptReq_0_bits_fpu_isa_fmul_s,
  input        io_dptReq_0_bits_fpu_isa_fdiv_s,
  input        io_dptReq_0_bits_fpu_isa_fsqrt_s,
  input        io_dptReq_0_bits_fpu_isa_fsgnj_s,
  input        io_dptReq_0_bits_fpu_isa_fsgnjn_s,
  input        io_dptReq_0_bits_fpu_isa_fsgnjx_s,
  input        io_dptReq_0_bits_fpu_isa_fmin_s,
  input        io_dptReq_0_bits_fpu_isa_fmax_s,
  input        io_dptReq_0_bits_fpu_isa_fcvt_w_s,
  input        io_dptReq_0_bits_fpu_isa_fcvt_wu_s,
  input        io_dptReq_0_bits_fpu_isa_fmv_x_w,
  input        io_dptReq_0_bits_fpu_isa_feq_s,
  input        io_dptReq_0_bits_fpu_isa_flt_s,
  input        io_dptReq_0_bits_fpu_isa_fle_s,
  input        io_dptReq_0_bits_fpu_isa_fclass_s,
  input        io_dptReq_0_bits_fpu_isa_fcvt_l_s,
  input        io_dptReq_0_bits_fpu_isa_fcvt_lu_s,
  input        io_dptReq_0_bits_fpu_isa_fmadd_d,
  input        io_dptReq_0_bits_fpu_isa_fmsub_d,
  input        io_dptReq_0_bits_fpu_isa_fnmsub_d,
  input        io_dptReq_0_bits_fpu_isa_fnmadd_d,
  input        io_dptReq_0_bits_fpu_isa_fadd_d,
  input        io_dptReq_0_bits_fpu_isa_fsub_d,
  input        io_dptReq_0_bits_fpu_isa_fmul_d,
  input        io_dptReq_0_bits_fpu_isa_fdiv_d,
  input        io_dptReq_0_bits_fpu_isa_fsqrt_d,
  input        io_dptReq_0_bits_fpu_isa_fsgnj_d,
  input        io_dptReq_0_bits_fpu_isa_fsgnjn_d,
  input        io_dptReq_0_bits_fpu_isa_fsgnjx_d,
  input        io_dptReq_0_bits_fpu_isa_fmin_d,
  input        io_dptReq_0_bits_fpu_isa_fmax_d,
  input        io_dptReq_0_bits_fpu_isa_fcvt_s_d,
  input        io_dptReq_0_bits_fpu_isa_fcvt_d_s,
  input        io_dptReq_0_bits_fpu_isa_feq_d,
  input        io_dptReq_0_bits_fpu_isa_flt_d,
  input        io_dptReq_0_bits_fpu_isa_fle_d,
  input        io_dptReq_0_bits_fpu_isa_fclass_d,
  input        io_dptReq_0_bits_fpu_isa_fcvt_w_d,
  input        io_dptReq_0_bits_fpu_isa_fcvt_wu_d,
  input        io_dptReq_0_bits_fpu_isa_fcvt_l_d,
  input        io_dptReq_0_bits_fpu_isa_fcvt_lu_d,
  input        io_dptReq_0_bits_fpu_isa_fmv_x_d,
  input  [5:0] io_dptReq_0_bits_phy_rs1,
  input  [5:0] io_dptReq_0_bits_phy_rs2,
  input  [5:0] io_dptReq_0_bits_phy_rs3,
  input        io_alu_iss_exe_0_ready,
  input        io_mul_iss_exe_0_ready,
  input        io_bru_iss_exe_ready,
  input        io_csr_iss_exe_ready,
  input        io_lsu_iss_exe_ready,
  input  [1:0] io_irgLog_0,
  input  [1:0] io_irgLog_1,
  input  [1:0] io_irgLog_2,
  input  [1:0] io_irgLog_3,
  input  [1:0] io_irgLog_4,
  input  [1:0] io_irgLog_5,
  input  [1:0] io_irgLog_6,
  input  [1:0] io_irgLog_7,
  input  [1:0] io_irgLog_8,
  input  [1:0] io_irgLog_9,
  input  [1:0] io_irgLog_10,
  input  [1:0] io_irgLog_11,
  input  [1:0] io_irgLog_12,
  input  [1:0] io_irgLog_13,
  input  [1:0] io_irgLog_14,
  input  [1:0] io_irgLog_15,
  input  [1:0] io_irgLog_16,
  input  [1:0] io_irgLog_17,
  input  [1:0] io_irgLog_18,
  input  [1:0] io_irgLog_19,
  input  [1:0] io_irgLog_20,
  input  [1:0] io_irgLog_21,
  input  [1:0] io_irgLog_22,
  input  [1:0] io_irgLog_23,
  input  [1:0] io_irgLog_24,
  input  [1:0] io_irgLog_25,
  input  [1:0] io_irgLog_26,
  input  [1:0] io_irgLog_27,
  input  [1:0] io_irgLog_28,
  input  [1:0] io_irgLog_29,
  input  [1:0] io_irgLog_30,
  input  [1:0] io_irgLog_31,
  input  [1:0] io_irgLog_32,
  input  [1:0] io_irgLog_33,
  input  [1:0] io_frgLog_0,
  input  [1:0] io_frgLog_1,
  input  [1:0] io_frgLog_2,
  input  [1:0] io_frgLog_3,
  input  [1:0] io_frgLog_4,
  input  [1:0] io_frgLog_5,
  input  [1:0] io_frgLog_6,
  input  [1:0] io_frgLog_7,
  input  [1:0] io_frgLog_8,
  input  [1:0] io_frgLog_9,
  input  [1:0] io_frgLog_10,
  input  [1:0] io_frgLog_11,
  input  [1:0] io_frgLog_12,
  input  [1:0] io_frgLog_13,
  input  [1:0] io_frgLog_14,
  input  [1:0] io_frgLog_15,
  input  [1:0] io_frgLog_16,
  input  [1:0] io_frgLog_17,
  input  [1:0] io_frgLog_18,
  input  [1:0] io_frgLog_19,
  input  [1:0] io_frgLog_20,
  input  [1:0] io_frgLog_21,
  input  [1:0] io_frgLog_22,
  input  [1:0] io_frgLog_23,
  input  [1:0] io_frgLog_24,
  input  [1:0] io_frgLog_25,
  input  [1:0] io_frgLog_26,
  input  [1:0] io_frgLog_27,
  input  [1:0] io_frgLog_28,
  input  [1:0] io_frgLog_29,
  input  [1:0] io_frgLog_30,
  input  [1:0] io_frgLog_31,
  input  [1:0] io_frgLog_32,
  input  [1:0] io_frgLog_33,
  input        io_irgRsp_0_valid,
  input  [5:0] io_irgRsp_0_bits_phy,
  input        io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_91;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
  reg [31:0] _RAND_94;
  reg [31:0] _RAND_95;
  reg [31:0] _RAND_96;
  reg [31:0] _RAND_97;
  reg [31:0] _RAND_98;
  reg [31:0] _RAND_99;
  reg [31:0] _RAND_100;
  reg [31:0] _RAND_101;
  reg [31:0] _RAND_102;
  reg [31:0] _RAND_103;
  reg [31:0] _RAND_104;
  reg [31:0] _RAND_105;
  reg [31:0] _RAND_106;
  reg [31:0] _RAND_107;
  reg [31:0] _RAND_108;
  reg [31:0] _RAND_109;
  reg [31:0] _RAND_110;
  reg [31:0] _RAND_111;
  reg [31:0] _RAND_112;
  reg [31:0] _RAND_113;
  reg [31:0] _RAND_114;
  reg [31:0] _RAND_115;
  reg [31:0] _RAND_116;
  reg [31:0] _RAND_117;
  reg [31:0] _RAND_118;
  reg [31:0] _RAND_119;
  reg [31:0] _RAND_120;
  reg [31:0] _RAND_121;
  reg [31:0] _RAND_122;
  reg [31:0] _RAND_123;
  reg [31:0] _RAND_124;
  reg [31:0] _RAND_125;
  reg [31:0] _RAND_126;
  reg [31:0] _RAND_127;
  reg [31:0] _RAND_128;
  reg [31:0] _RAND_129;
  reg [31:0] _RAND_130;
  reg [31:0] _RAND_131;
  reg [31:0] _RAND_132;
  reg [31:0] _RAND_133;
  reg [31:0] _RAND_134;
  reg [31:0] _RAND_135;
  reg [31:0] _RAND_136;
  reg [31:0] _RAND_137;
  reg [31:0] _RAND_138;
  reg [31:0] _RAND_139;
  reg [31:0] _RAND_140;
  reg [31:0] _RAND_141;
  reg [31:0] _RAND_142;
  reg [31:0] _RAND_143;
  reg [31:0] _RAND_144;
  reg [31:0] _RAND_145;
  reg [31:0] _RAND_146;
  reg [31:0] _RAND_147;
  reg [31:0] _RAND_148;
  reg [31:0] _RAND_149;
  reg [31:0] _RAND_150;
  reg [31:0] _RAND_151;
  reg [31:0] _RAND_152;
  reg [31:0] _RAND_153;
  reg [31:0] _RAND_154;
  reg [31:0] _RAND_155;
  reg [31:0] _RAND_156;
  reg [31:0] _RAND_157;
  reg [31:0] _RAND_158;
  reg [31:0] _RAND_159;
  reg [31:0] _RAND_160;
  reg [31:0] _RAND_161;
  reg [31:0] _RAND_162;
  reg [31:0] _RAND_163;
  reg [31:0] _RAND_164;
  reg [31:0] _RAND_165;
  reg [31:0] _RAND_166;
  reg [31:0] _RAND_167;
  reg [31:0] _RAND_168;
  reg [31:0] _RAND_169;
  reg [31:0] _RAND_170;
  reg [31:0] _RAND_171;
  reg [31:0] _RAND_172;
  reg [31:0] _RAND_173;
  reg [31:0] _RAND_174;
  reg [31:0] _RAND_175;
  reg [31:0] _RAND_176;
  reg [31:0] _RAND_177;
  reg [31:0] _RAND_178;
  reg [31:0] _RAND_179;
  reg [31:0] _RAND_180;
  reg [31:0] _RAND_181;
  reg [31:0] _RAND_182;
  reg [31:0] _RAND_183;
  reg [31:0] _RAND_184;
  reg [31:0] _RAND_185;
  reg [31:0] _RAND_186;
  reg [31:0] _RAND_187;
  reg [31:0] _RAND_188;
  reg [31:0] _RAND_189;
  reg [31:0] _RAND_190;
  reg [31:0] _RAND_191;
  reg [31:0] _RAND_192;
  reg [31:0] _RAND_193;
  reg [31:0] _RAND_194;
  reg [31:0] _RAND_195;
  reg [31:0] _RAND_196;
  reg [31:0] _RAND_197;
  reg [31:0] _RAND_198;
  reg [31:0] _RAND_199;
  reg [31:0] _RAND_200;
  reg [31:0] _RAND_201;
  reg [31:0] _RAND_202;
  reg [31:0] _RAND_203;
  reg [31:0] _RAND_204;
  reg [31:0] _RAND_205;
  reg [31:0] _RAND_206;
  reg [31:0] _RAND_207;
  reg [31:0] _RAND_208;
  reg [31:0] _RAND_209;
  reg [31:0] _RAND_210;
`endif // RANDOMIZE_REG_INIT
  wire  aluIssFifo_0_clock; // @[Issue.scala 605:11]
  wire  aluIssFifo_0_reset; // @[Issue.scala 605:11]
  wire  aluIssFifo_0_io_enq_ready; // @[Issue.scala 605:11]
  wire  aluIssFifo_0_io_enq_valid; // @[Issue.scala 605:11]
  wire  aluIssFifo_0_io_deq_ready; // @[Issue.scala 605:11]
  wire  aluIssFifo_0_io_deq_valid; // @[Issue.scala 605:11]
  wire  mulIssFifo_0_clock; // @[Issue.scala 671:13]
  wire  mulIssFifo_0_reset; // @[Issue.scala 671:13]
  wire  mulIssFifo_0_io_enq_ready; // @[Issue.scala 671:13]
  wire  mulIssFifo_0_io_enq_valid; // @[Issue.scala 671:13]
  wire  mulIssFifo_0_io_deq_ready; // @[Issue.scala 671:13]
  wire  mulIssFifo_0_io_deq_valid; // @[Issue.scala 671:13]
  wire  bruIssFifo_clock; // @[Issue.scala 743:26]
  wire  bruIssFifo_reset; // @[Issue.scala 743:26]
  wire  bruIssFifo_io_enq_ready; // @[Issue.scala 743:26]
  wire  bruIssFifo_io_enq_valid; // @[Issue.scala 743:26]
  wire  bruIssFifo_io_deq_ready; // @[Issue.scala 743:26]
  wire  bruIssFifo_io_deq_valid; // @[Issue.scala 743:26]
  wire  csrIssFifo_clock; // @[Issue.scala 809:26]
  wire  csrIssFifo_reset; // @[Issue.scala 809:26]
  wire  csrIssFifo_io_enq_ready; // @[Issue.scala 809:26]
  wire  csrIssFifo_io_enq_valid; // @[Issue.scala 809:26]
  wire  csrIssFifo_io_deq_ready; // @[Issue.scala 809:26]
  wire  csrIssFifo_io_deq_valid; // @[Issue.scala 809:26]
  wire  lsuIssFifo_clock; // @[Issue.scala 872:26]
  wire  lsuIssFifo_reset; // @[Issue.scala 872:26]
  wire  lsuIssFifo_io_enq_ready; // @[Issue.scala 872:26]
  wire  lsuIssFifo_io_enq_valid; // @[Issue.scala 872:26]
  wire  lsuIssFifo_io_deq_ready; // @[Issue.scala 872:26]
  wire  lsuIssFifo_io_deq_valid; // @[Issue.scala 872:26]
  reg  bufValid_0; // @[Issue.scala 61:29]
  reg  bufValid_1; // @[Issue.scala 61:29]
  reg  bufInfo_0_alu_isa_lui; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_auipc; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_addi; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_addiw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_slti; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_sltiu; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_xori; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_ori; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_andi; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_slli; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_slliw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_srli; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_srliw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_srai; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_sraiw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_add; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_addw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_sub; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_subw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_sll; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_sllw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_slt; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_sltu; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_xor; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_srl; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_srlw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_sra; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_sraw; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_or; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_and; // @[Issue.scala 62:25]
  reg  bufInfo_0_alu_isa_wfi; // @[Issue.scala 62:25]
  reg  bufInfo_0_bru_isa_jal; // @[Issue.scala 62:25]
  reg  bufInfo_0_bru_isa_jalr; // @[Issue.scala 62:25]
  reg  bufInfo_0_bru_isa_beq; // @[Issue.scala 62:25]
  reg  bufInfo_0_bru_isa_bne; // @[Issue.scala 62:25]
  reg  bufInfo_0_bru_isa_blt; // @[Issue.scala 62:25]
  reg  bufInfo_0_bru_isa_bge; // @[Issue.scala 62:25]
  reg  bufInfo_0_bru_isa_bltu; // @[Issue.scala 62:25]
  reg  bufInfo_0_bru_isa_bgeu; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_lb; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_lh; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_lw; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_ld; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_lbu; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_lhu; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_lwu; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_sb; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_sh; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_sw; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_sd; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_fence; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_fence_i; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_sfence_vma; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_lr_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_sc_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoswap_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoadd_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoxor_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoand_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoor_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amomin_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amomax_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amominu_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amomaxu_w; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_lr_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_sc_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoswap_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoadd_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoxor_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoand_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amoor_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amomin_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amomax_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amominu_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_amomaxu_d; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_flw; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_fsw; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_fld; // @[Issue.scala 62:25]
  reg  bufInfo_0_lsu_isa_fsd; // @[Issue.scala 62:25]
  reg  bufInfo_0_csr_isa_rw; // @[Issue.scala 62:25]
  reg  bufInfo_0_csr_isa_rs; // @[Issue.scala 62:25]
  reg  bufInfo_0_csr_isa_rc; // @[Issue.scala 62:25]
  reg  bufInfo_0_csr_isa_rwi; // @[Issue.scala 62:25]
  reg  bufInfo_0_csr_isa_rsi; // @[Issue.scala 62:25]
  reg  bufInfo_0_csr_isa_rci; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_mul; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_mulh; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_mulhsu; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_mulhu; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_div; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_divu; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_rem; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_remu; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_mulw; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_divw; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_divuw; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_remw; // @[Issue.scala 62:25]
  reg  bufInfo_0_mul_isa_remuw; // @[Issue.scala 62:25]
  reg [5:0] bufInfo_0_phy_rs1; // @[Issue.scala 62:25]
  reg [5:0] bufInfo_0_phy_rs2; // @[Issue.scala 62:25]
  reg [5:0] bufInfo_0_phy_rs3; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_lui; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_auipc; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_addi; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_addiw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_slti; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_sltiu; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_xori; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_ori; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_andi; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_slli; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_slliw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_srli; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_srliw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_srai; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_sraiw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_add; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_addw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_sub; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_subw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_sll; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_sllw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_slt; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_sltu; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_xor; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_srl; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_srlw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_sra; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_sraw; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_or; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_and; // @[Issue.scala 62:25]
  reg  bufInfo_1_alu_isa_wfi; // @[Issue.scala 62:25]
  reg  bufInfo_1_bru_isa_jal; // @[Issue.scala 62:25]
  reg  bufInfo_1_bru_isa_jalr; // @[Issue.scala 62:25]
  reg  bufInfo_1_bru_isa_beq; // @[Issue.scala 62:25]
  reg  bufInfo_1_bru_isa_bne; // @[Issue.scala 62:25]
  reg  bufInfo_1_bru_isa_blt; // @[Issue.scala 62:25]
  reg  bufInfo_1_bru_isa_bge; // @[Issue.scala 62:25]
  reg  bufInfo_1_bru_isa_bltu; // @[Issue.scala 62:25]
  reg  bufInfo_1_bru_isa_bgeu; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_lb; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_lh; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_lw; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_ld; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_lbu; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_lhu; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_lwu; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_sb; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_sh; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_sw; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_sd; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_fence; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_fence_i; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_sfence_vma; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_lr_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_sc_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoswap_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoadd_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoxor_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoand_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoor_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amomin_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amomax_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amominu_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amomaxu_w; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_lr_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_sc_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoswap_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoadd_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoxor_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoand_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amoor_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amomin_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amomax_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amominu_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_amomaxu_d; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_flw; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_fsw; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_fld; // @[Issue.scala 62:25]
  reg  bufInfo_1_lsu_isa_fsd; // @[Issue.scala 62:25]
  reg  bufInfo_1_csr_isa_rw; // @[Issue.scala 62:25]
  reg  bufInfo_1_csr_isa_rs; // @[Issue.scala 62:25]
  reg  bufInfo_1_csr_isa_rc; // @[Issue.scala 62:25]
  reg  bufInfo_1_csr_isa_rwi; // @[Issue.scala 62:25]
  reg  bufInfo_1_csr_isa_rsi; // @[Issue.scala 62:25]
  reg  bufInfo_1_csr_isa_rci; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_mul; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_mulh; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_mulhsu; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_mulhu; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_div; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_divu; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_rem; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_remu; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_mulw; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_divw; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_divuw; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_remw; // @[Issue.scala 62:25]
  reg  bufInfo_1_mul_isa_remuw; // @[Issue.scala 62:25]
  reg [5:0] bufInfo_1_phy_rs1; // @[Issue.scala 62:25]
  reg [5:0] bufInfo_1_phy_rs2; // @[Issue.scala 62:25]
  reg [5:0] bufInfo_1_phy_rs3; // @[Issue.scala 62:25]
  reg  isOpReady_0_0; // @[Issue.scala 65:25]
  reg  isOpReady_0_1; // @[Issue.scala 65:25]
  reg  isOpReady_1_0; // @[Issue.scala 65:25]
  reg  isOpReady_1_1; // @[Issue.scala 65:25]
  wire  _entrySel_T = ~bufValid_0; // @[Issue.scala 69:43]
  wire  entrySel_0 = ~bufValid_0 ? 1'h0 : 1'h1; // @[Issue.scala 69:26]
  wire  _io_dptReq_0_ready_T_1 = ~bufValid_1; // @[Issue.scala 78:59]
  wire  _T = io_dptReq_0_ready & io_dptReq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_198 = ~entrySel_0; // @[Issue.scala 82:23 89:{36,36}]
  wire  _GEN_0 = ~entrySel_0 | bufValid_0; // @[Issue.scala 82:23 89:{36,36}]
  wire  _GEN_1 = entrySel_0 | bufValid_1; // @[Issue.scala 82:23 89:{36,36}]
  wire  _GEN_396 = _T ? _GEN_0 : bufValid_0; // @[Issue.scala 82:23 88:38]
  wire  _GEN_397 = _T ? _GEN_1 : bufValid_1; // @[Issue.scala 82:23 88:38]
  wire  bufValidDnxt_0_0 = io_flush ? 1'h0 : _GEN_396; // @[Issue.scala 86:22 87:23]
  wire  bufValidDnxt_0_1 = io_flush ? 1'h0 : _GEN_397; // @[Issue.scala 86:22 87:23]
  wire  _GEN_1200 = _GEN_198 | isOpReady_0_0; // @[Issue.scala 122:{36,36} 65:25]
  wire  _GEN_1201 = entrySel_0 | isOpReady_1_0; // @[Issue.scala 122:{36,36} 65:25]
  wire  _GEN_1204 = ~entrySel_0 ? 1'h0 : isOpReady_0_0; // @[Issue.scala 125:{36,36} 65:25]
  wire  _GEN_1205 = entrySel_0 ? 1'h0 : isOpReady_1_0; // @[Issue.scala 125:{36,36} 65:25]
  wire  _GEN_1206 = io_dptReq_0_bits_phy_rs1 == 6'h21 ? _GEN_1200 : _GEN_1204; // @[Issue.scala 121:58]
  wire  _GEN_1207 = io_dptReq_0_bits_phy_rs1 == 6'h21 ? _GEN_1201 : _GEN_1205; // @[Issue.scala 121:58]
  wire  _GEN_1210 = _GEN_198 | isOpReady_0_1; // @[Issue.scala 128:{36,36} 65:25]
  wire  _GEN_1211 = entrySel_0 | isOpReady_1_1; // @[Issue.scala 128:{36,36} 65:25]
  wire  _GEN_1214 = ~entrySel_0 ? 1'h0 : isOpReady_0_1; // @[Issue.scala 131:{36,36} 65:25]
  wire  _GEN_1215 = entrySel_0 ? 1'h0 : isOpReady_1_1; // @[Issue.scala 131:{36,36} 65:25]
  wire  _GEN_1216 = io_dptReq_0_bits_phy_rs2 == 6'h21 ? _GEN_1210 : _GEN_1214; // @[Issue.scala 127:58]
  wire  _GEN_1217 = io_dptReq_0_bits_phy_rs2 == 6'h21 ? _GEN_1211 : _GEN_1215; // @[Issue.scala 127:58]
  wire  _GEN_1230 = _T ? _GEN_1206 : isOpReady_0_0; // @[Issue.scala 120:31 65:25]
  wire  _GEN_1231 = _T ? _GEN_1207 : isOpReady_1_0; // @[Issue.scala 120:31 65:25]
  wire  _GEN_1234 = _T ? _GEN_1216 : isOpReady_0_1; // @[Issue.scala 120:31 65:25]
  wire  _GEN_1235 = _T ? _GEN_1217 : isOpReady_1_1; // @[Issue.scala 120:31 65:25]
  reg  ageMatrixW_0_0; // @[Issue.scala 156:23]
  reg  ageMatrixW_0_1; // @[Issue.scala 156:23]
  reg  ageMatrixW_1_1; // @[Issue.scala 156:23]
  wire  ageMatrixR_1_0 = ~ageMatrixW_0_1; // @[Issue.scala 161:27]
  wire  _GEN_1242 = _GEN_198 | ageMatrixW_0_0; // @[Issue.scala 156:23 171:{44,44}]
  wire  _GEN_1244 = _GEN_198 | ageMatrixW_0_1; // @[Issue.scala 156:23 171:{44,44}]
  wire  _GEN_1245 = entrySel_0 | ageMatrixW_1_1; // @[Issue.scala 156:23 171:{44,44}]
  wire [1:0] _GEN_1255 = 6'h1 == bufInfo_0_phy_rs1 ? io_irgLog_1 : io_irgLog_0; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1256 = 6'h2 == bufInfo_0_phy_rs1 ? io_irgLog_2 : _GEN_1255; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1257 = 6'h3 == bufInfo_0_phy_rs1 ? io_irgLog_3 : _GEN_1256; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1258 = 6'h4 == bufInfo_0_phy_rs1 ? io_irgLog_4 : _GEN_1257; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1259 = 6'h5 == bufInfo_0_phy_rs1 ? io_irgLog_5 : _GEN_1258; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1260 = 6'h6 == bufInfo_0_phy_rs1 ? io_irgLog_6 : _GEN_1259; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1261 = 6'h7 == bufInfo_0_phy_rs1 ? io_irgLog_7 : _GEN_1260; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1262 = 6'h8 == bufInfo_0_phy_rs1 ? io_irgLog_8 : _GEN_1261; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1263 = 6'h9 == bufInfo_0_phy_rs1 ? io_irgLog_9 : _GEN_1262; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1264 = 6'ha == bufInfo_0_phy_rs1 ? io_irgLog_10 : _GEN_1263; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1265 = 6'hb == bufInfo_0_phy_rs1 ? io_irgLog_11 : _GEN_1264; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1266 = 6'hc == bufInfo_0_phy_rs1 ? io_irgLog_12 : _GEN_1265; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1267 = 6'hd == bufInfo_0_phy_rs1 ? io_irgLog_13 : _GEN_1266; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1268 = 6'he == bufInfo_0_phy_rs1 ? io_irgLog_14 : _GEN_1267; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1269 = 6'hf == bufInfo_0_phy_rs1 ? io_irgLog_15 : _GEN_1268; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1270 = 6'h10 == bufInfo_0_phy_rs1 ? io_irgLog_16 : _GEN_1269; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1271 = 6'h11 == bufInfo_0_phy_rs1 ? io_irgLog_17 : _GEN_1270; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1272 = 6'h12 == bufInfo_0_phy_rs1 ? io_irgLog_18 : _GEN_1271; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1273 = 6'h13 == bufInfo_0_phy_rs1 ? io_irgLog_19 : _GEN_1272; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1274 = 6'h14 == bufInfo_0_phy_rs1 ? io_irgLog_20 : _GEN_1273; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1275 = 6'h15 == bufInfo_0_phy_rs1 ? io_irgLog_21 : _GEN_1274; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1276 = 6'h16 == bufInfo_0_phy_rs1 ? io_irgLog_22 : _GEN_1275; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1277 = 6'h17 == bufInfo_0_phy_rs1 ? io_irgLog_23 : _GEN_1276; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1278 = 6'h18 == bufInfo_0_phy_rs1 ? io_irgLog_24 : _GEN_1277; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1279 = 6'h19 == bufInfo_0_phy_rs1 ? io_irgLog_25 : _GEN_1278; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1280 = 6'h1a == bufInfo_0_phy_rs1 ? io_irgLog_26 : _GEN_1279; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1281 = 6'h1b == bufInfo_0_phy_rs1 ? io_irgLog_27 : _GEN_1280; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1282 = 6'h1c == bufInfo_0_phy_rs1 ? io_irgLog_28 : _GEN_1281; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1283 = 6'h1d == bufInfo_0_phy_rs1 ? io_irgLog_29 : _GEN_1282; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1284 = 6'h1e == bufInfo_0_phy_rs1 ? io_irgLog_30 : _GEN_1283; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1285 = 6'h1f == bufInfo_0_phy_rs1 ? io_irgLog_31 : _GEN_1284; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1286 = 6'h20 == bufInfo_0_phy_rs1 ? io_irgLog_32 : _GEN_1285; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1287 = 6'h21 == bufInfo_0_phy_rs1 ? io_irgLog_33 : _GEN_1286; // @[Issue.scala 217:{37,37}]
  wire  _canIOpReq_0_0_T = _GEN_1287 == 2'h3; // @[Issue.scala 217:37]
  wire  _canIOpReq_0_0_T_3 = ~isOpReady_0_0; // @[Issue.scala 219:7]
  wire  _canIOpReq_0_0_T_4 = _canIOpReq_0_0_T & _canIOpReq_0_0_T_3; // @[Issue.scala 218:23]
  wire [5:0] bufReqNum_0_0 = bufInfo_0_phy_rs1; // @[Issue.scala 144:21 63:26]
  wire  _canIOpReq_0_0_T_6 = io_irgRsp_0_valid & io_irgRsp_0_bits_phy == bufReqNum_0_0; // @[Issue.scala 219:55]
  wire  canIOpReq_0_0 = _canIOpReq_0_0_T_4 & ~(io_irgRsp_0_valid & io_irgRsp_0_bits_phy == bufReqNum_0_0); // @[Issue.scala 219:24]
  wire [1:0] _GEN_1289 = 6'h1 == bufInfo_0_phy_rs2 ? io_irgLog_1 : io_irgLog_0; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1290 = 6'h2 == bufInfo_0_phy_rs2 ? io_irgLog_2 : _GEN_1289; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1291 = 6'h3 == bufInfo_0_phy_rs2 ? io_irgLog_3 : _GEN_1290; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1292 = 6'h4 == bufInfo_0_phy_rs2 ? io_irgLog_4 : _GEN_1291; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1293 = 6'h5 == bufInfo_0_phy_rs2 ? io_irgLog_5 : _GEN_1292; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1294 = 6'h6 == bufInfo_0_phy_rs2 ? io_irgLog_6 : _GEN_1293; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1295 = 6'h7 == bufInfo_0_phy_rs2 ? io_irgLog_7 : _GEN_1294; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1296 = 6'h8 == bufInfo_0_phy_rs2 ? io_irgLog_8 : _GEN_1295; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1297 = 6'h9 == bufInfo_0_phy_rs2 ? io_irgLog_9 : _GEN_1296; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1298 = 6'ha == bufInfo_0_phy_rs2 ? io_irgLog_10 : _GEN_1297; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1299 = 6'hb == bufInfo_0_phy_rs2 ? io_irgLog_11 : _GEN_1298; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1300 = 6'hc == bufInfo_0_phy_rs2 ? io_irgLog_12 : _GEN_1299; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1301 = 6'hd == bufInfo_0_phy_rs2 ? io_irgLog_13 : _GEN_1300; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1302 = 6'he == bufInfo_0_phy_rs2 ? io_irgLog_14 : _GEN_1301; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1303 = 6'hf == bufInfo_0_phy_rs2 ? io_irgLog_15 : _GEN_1302; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1304 = 6'h10 == bufInfo_0_phy_rs2 ? io_irgLog_16 : _GEN_1303; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1305 = 6'h11 == bufInfo_0_phy_rs2 ? io_irgLog_17 : _GEN_1304; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1306 = 6'h12 == bufInfo_0_phy_rs2 ? io_irgLog_18 : _GEN_1305; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1307 = 6'h13 == bufInfo_0_phy_rs2 ? io_irgLog_19 : _GEN_1306; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1308 = 6'h14 == bufInfo_0_phy_rs2 ? io_irgLog_20 : _GEN_1307; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1309 = 6'h15 == bufInfo_0_phy_rs2 ? io_irgLog_21 : _GEN_1308; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1310 = 6'h16 == bufInfo_0_phy_rs2 ? io_irgLog_22 : _GEN_1309; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1311 = 6'h17 == bufInfo_0_phy_rs2 ? io_irgLog_23 : _GEN_1310; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1312 = 6'h18 == bufInfo_0_phy_rs2 ? io_irgLog_24 : _GEN_1311; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1313 = 6'h19 == bufInfo_0_phy_rs2 ? io_irgLog_25 : _GEN_1312; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1314 = 6'h1a == bufInfo_0_phy_rs2 ? io_irgLog_26 : _GEN_1313; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1315 = 6'h1b == bufInfo_0_phy_rs2 ? io_irgLog_27 : _GEN_1314; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1316 = 6'h1c == bufInfo_0_phy_rs2 ? io_irgLog_28 : _GEN_1315; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1317 = 6'h1d == bufInfo_0_phy_rs2 ? io_irgLog_29 : _GEN_1316; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1318 = 6'h1e == bufInfo_0_phy_rs2 ? io_irgLog_30 : _GEN_1317; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1319 = 6'h1f == bufInfo_0_phy_rs2 ? io_irgLog_31 : _GEN_1318; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1320 = 6'h20 == bufInfo_0_phy_rs2 ? io_irgLog_32 : _GEN_1319; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1321 = 6'h21 == bufInfo_0_phy_rs2 ? io_irgLog_33 : _GEN_1320; // @[Issue.scala 222:{37,37}]
  wire  _canIOpReq_0_1_T = _GEN_1321 == 2'h3; // @[Issue.scala 222:37]
  wire  _canIOpReq_0_1_T_3 = ~isOpReady_0_1; // @[Issue.scala 224:7]
  wire  _canIOpReq_0_1_T_4 = _canIOpReq_0_1_T & _canIOpReq_0_1_T_3; // @[Issue.scala 223:23]
  wire [5:0] bufReqNum_0_1 = bufInfo_0_phy_rs2; // @[Issue.scala 145:21 63:26]
  wire  _canIOpReq_0_1_T_6 = io_irgRsp_0_valid & io_irgRsp_0_bits_phy == bufReqNum_0_1; // @[Issue.scala 224:55]
  wire  canIOpReq_0_1 = _canIOpReq_0_1_T_4 & ~(io_irgRsp_0_valid & io_irgRsp_0_bits_phy == bufReqNum_0_1); // @[Issue.scala 224:24]
  wire [1:0] _GEN_1323 = 6'h1 == bufInfo_1_phy_rs1 ? io_irgLog_1 : io_irgLog_0; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1324 = 6'h2 == bufInfo_1_phy_rs1 ? io_irgLog_2 : _GEN_1323; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1325 = 6'h3 == bufInfo_1_phy_rs1 ? io_irgLog_3 : _GEN_1324; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1326 = 6'h4 == bufInfo_1_phy_rs1 ? io_irgLog_4 : _GEN_1325; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1327 = 6'h5 == bufInfo_1_phy_rs1 ? io_irgLog_5 : _GEN_1326; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1328 = 6'h6 == bufInfo_1_phy_rs1 ? io_irgLog_6 : _GEN_1327; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1329 = 6'h7 == bufInfo_1_phy_rs1 ? io_irgLog_7 : _GEN_1328; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1330 = 6'h8 == bufInfo_1_phy_rs1 ? io_irgLog_8 : _GEN_1329; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1331 = 6'h9 == bufInfo_1_phy_rs1 ? io_irgLog_9 : _GEN_1330; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1332 = 6'ha == bufInfo_1_phy_rs1 ? io_irgLog_10 : _GEN_1331; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1333 = 6'hb == bufInfo_1_phy_rs1 ? io_irgLog_11 : _GEN_1332; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1334 = 6'hc == bufInfo_1_phy_rs1 ? io_irgLog_12 : _GEN_1333; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1335 = 6'hd == bufInfo_1_phy_rs1 ? io_irgLog_13 : _GEN_1334; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1336 = 6'he == bufInfo_1_phy_rs1 ? io_irgLog_14 : _GEN_1335; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1337 = 6'hf == bufInfo_1_phy_rs1 ? io_irgLog_15 : _GEN_1336; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1338 = 6'h10 == bufInfo_1_phy_rs1 ? io_irgLog_16 : _GEN_1337; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1339 = 6'h11 == bufInfo_1_phy_rs1 ? io_irgLog_17 : _GEN_1338; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1340 = 6'h12 == bufInfo_1_phy_rs1 ? io_irgLog_18 : _GEN_1339; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1341 = 6'h13 == bufInfo_1_phy_rs1 ? io_irgLog_19 : _GEN_1340; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1342 = 6'h14 == bufInfo_1_phy_rs1 ? io_irgLog_20 : _GEN_1341; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1343 = 6'h15 == bufInfo_1_phy_rs1 ? io_irgLog_21 : _GEN_1342; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1344 = 6'h16 == bufInfo_1_phy_rs1 ? io_irgLog_22 : _GEN_1343; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1345 = 6'h17 == bufInfo_1_phy_rs1 ? io_irgLog_23 : _GEN_1344; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1346 = 6'h18 == bufInfo_1_phy_rs1 ? io_irgLog_24 : _GEN_1345; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1347 = 6'h19 == bufInfo_1_phy_rs1 ? io_irgLog_25 : _GEN_1346; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1348 = 6'h1a == bufInfo_1_phy_rs1 ? io_irgLog_26 : _GEN_1347; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1349 = 6'h1b == bufInfo_1_phy_rs1 ? io_irgLog_27 : _GEN_1348; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1350 = 6'h1c == bufInfo_1_phy_rs1 ? io_irgLog_28 : _GEN_1349; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1351 = 6'h1d == bufInfo_1_phy_rs1 ? io_irgLog_29 : _GEN_1350; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1352 = 6'h1e == bufInfo_1_phy_rs1 ? io_irgLog_30 : _GEN_1351; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1353 = 6'h1f == bufInfo_1_phy_rs1 ? io_irgLog_31 : _GEN_1352; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1354 = 6'h20 == bufInfo_1_phy_rs1 ? io_irgLog_32 : _GEN_1353; // @[Issue.scala 217:{37,37}]
  wire [1:0] _GEN_1355 = 6'h21 == bufInfo_1_phy_rs1 ? io_irgLog_33 : _GEN_1354; // @[Issue.scala 217:{37,37}]
  wire  _canIOpReq_1_0_T = _GEN_1355 == 2'h3; // @[Issue.scala 217:37]
  wire  _canIOpReq_1_0_T_3 = ~isOpReady_1_0; // @[Issue.scala 219:7]
  wire  _canIOpReq_1_0_T_4 = _canIOpReq_1_0_T & _canIOpReq_1_0_T_3; // @[Issue.scala 218:23]
  wire [5:0] bufReqNum_1_0 = bufInfo_1_phy_rs1; // @[Issue.scala 144:21 63:26]
  wire  _canIOpReq_1_0_T_6 = io_irgRsp_0_valid & io_irgRsp_0_bits_phy == bufReqNum_1_0; // @[Issue.scala 219:55]
  wire  canIOpReq_1_0 = _canIOpReq_1_0_T_4 & ~(io_irgRsp_0_valid & io_irgRsp_0_bits_phy == bufReqNum_1_0); // @[Issue.scala 219:24]
  wire [1:0] _GEN_1357 = 6'h1 == bufInfo_1_phy_rs2 ? io_irgLog_1 : io_irgLog_0; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1358 = 6'h2 == bufInfo_1_phy_rs2 ? io_irgLog_2 : _GEN_1357; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1359 = 6'h3 == bufInfo_1_phy_rs2 ? io_irgLog_3 : _GEN_1358; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1360 = 6'h4 == bufInfo_1_phy_rs2 ? io_irgLog_4 : _GEN_1359; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1361 = 6'h5 == bufInfo_1_phy_rs2 ? io_irgLog_5 : _GEN_1360; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1362 = 6'h6 == bufInfo_1_phy_rs2 ? io_irgLog_6 : _GEN_1361; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1363 = 6'h7 == bufInfo_1_phy_rs2 ? io_irgLog_7 : _GEN_1362; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1364 = 6'h8 == bufInfo_1_phy_rs2 ? io_irgLog_8 : _GEN_1363; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1365 = 6'h9 == bufInfo_1_phy_rs2 ? io_irgLog_9 : _GEN_1364; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1366 = 6'ha == bufInfo_1_phy_rs2 ? io_irgLog_10 : _GEN_1365; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1367 = 6'hb == bufInfo_1_phy_rs2 ? io_irgLog_11 : _GEN_1366; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1368 = 6'hc == bufInfo_1_phy_rs2 ? io_irgLog_12 : _GEN_1367; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1369 = 6'hd == bufInfo_1_phy_rs2 ? io_irgLog_13 : _GEN_1368; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1370 = 6'he == bufInfo_1_phy_rs2 ? io_irgLog_14 : _GEN_1369; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1371 = 6'hf == bufInfo_1_phy_rs2 ? io_irgLog_15 : _GEN_1370; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1372 = 6'h10 == bufInfo_1_phy_rs2 ? io_irgLog_16 : _GEN_1371; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1373 = 6'h11 == bufInfo_1_phy_rs2 ? io_irgLog_17 : _GEN_1372; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1374 = 6'h12 == bufInfo_1_phy_rs2 ? io_irgLog_18 : _GEN_1373; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1375 = 6'h13 == bufInfo_1_phy_rs2 ? io_irgLog_19 : _GEN_1374; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1376 = 6'h14 == bufInfo_1_phy_rs2 ? io_irgLog_20 : _GEN_1375; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1377 = 6'h15 == bufInfo_1_phy_rs2 ? io_irgLog_21 : _GEN_1376; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1378 = 6'h16 == bufInfo_1_phy_rs2 ? io_irgLog_22 : _GEN_1377; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1379 = 6'h17 == bufInfo_1_phy_rs2 ? io_irgLog_23 : _GEN_1378; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1380 = 6'h18 == bufInfo_1_phy_rs2 ? io_irgLog_24 : _GEN_1379; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1381 = 6'h19 == bufInfo_1_phy_rs2 ? io_irgLog_25 : _GEN_1380; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1382 = 6'h1a == bufInfo_1_phy_rs2 ? io_irgLog_26 : _GEN_1381; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1383 = 6'h1b == bufInfo_1_phy_rs2 ? io_irgLog_27 : _GEN_1382; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1384 = 6'h1c == bufInfo_1_phy_rs2 ? io_irgLog_28 : _GEN_1383; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1385 = 6'h1d == bufInfo_1_phy_rs2 ? io_irgLog_29 : _GEN_1384; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1386 = 6'h1e == bufInfo_1_phy_rs2 ? io_irgLog_30 : _GEN_1385; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1387 = 6'h1f == bufInfo_1_phy_rs2 ? io_irgLog_31 : _GEN_1386; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1388 = 6'h20 == bufInfo_1_phy_rs2 ? io_irgLog_32 : _GEN_1387; // @[Issue.scala 222:{37,37}]
  wire [1:0] _GEN_1389 = 6'h21 == bufInfo_1_phy_rs2 ? io_irgLog_33 : _GEN_1388; // @[Issue.scala 222:{37,37}]
  wire  _canIOpReq_1_1_T = _GEN_1389 == 2'h3; // @[Issue.scala 222:37]
  wire  _canIOpReq_1_1_T_3 = ~isOpReady_1_1; // @[Issue.scala 224:7]
  wire  _canIOpReq_1_1_T_4 = _canIOpReq_1_1_T & _canIOpReq_1_1_T_3; // @[Issue.scala 223:23]
  wire [5:0] bufReqNum_1_1 = bufInfo_1_phy_rs2; // @[Issue.scala 145:21 63:26]
  wire  _canIOpReq_1_1_T_6 = io_irgRsp_0_valid & io_irgRsp_0_bits_phy == bufReqNum_1_1; // @[Issue.scala 224:55]
  wire  canIOpReq_1_1 = _canIOpReq_1_1_T_4 & ~(io_irgRsp_0_valid & io_irgRsp_0_bits_phy == bufReqNum_1_1); // @[Issue.scala 224:24]
  wire [1:0] _GEN_1391 = 6'h1 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_1 : io_irgLog_0; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1392 = 6'h2 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_2 : _GEN_1391; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1393 = 6'h3 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_3 : _GEN_1392; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1394 = 6'h4 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_4 : _GEN_1393; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1395 = 6'h5 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_5 : _GEN_1394; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1396 = 6'h6 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_6 : _GEN_1395; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1397 = 6'h7 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_7 : _GEN_1396; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1398 = 6'h8 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_8 : _GEN_1397; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1399 = 6'h9 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_9 : _GEN_1398; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1400 = 6'ha == io_dptReq_0_bits_phy_rs1 ? io_irgLog_10 : _GEN_1399; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1401 = 6'hb == io_dptReq_0_bits_phy_rs1 ? io_irgLog_11 : _GEN_1400; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1402 = 6'hc == io_dptReq_0_bits_phy_rs1 ? io_irgLog_12 : _GEN_1401; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1403 = 6'hd == io_dptReq_0_bits_phy_rs1 ? io_irgLog_13 : _GEN_1402; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1404 = 6'he == io_dptReq_0_bits_phy_rs1 ? io_irgLog_14 : _GEN_1403; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1405 = 6'hf == io_dptReq_0_bits_phy_rs1 ? io_irgLog_15 : _GEN_1404; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1406 = 6'h10 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_16 : _GEN_1405; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1407 = 6'h11 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_17 : _GEN_1406; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1408 = 6'h12 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_18 : _GEN_1407; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1409 = 6'h13 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_19 : _GEN_1408; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1410 = 6'h14 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_20 : _GEN_1409; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1411 = 6'h15 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_21 : _GEN_1410; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1412 = 6'h16 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_22 : _GEN_1411; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1413 = 6'h17 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_23 : _GEN_1412; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1414 = 6'h18 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_24 : _GEN_1413; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1415 = 6'h19 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_25 : _GEN_1414; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1416 = 6'h1a == io_dptReq_0_bits_phy_rs1 ? io_irgLog_26 : _GEN_1415; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1417 = 6'h1b == io_dptReq_0_bits_phy_rs1 ? io_irgLog_27 : _GEN_1416; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1418 = 6'h1c == io_dptReq_0_bits_phy_rs1 ? io_irgLog_28 : _GEN_1417; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1419 = 6'h1d == io_dptReq_0_bits_phy_rs1 ? io_irgLog_29 : _GEN_1418; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1420 = 6'h1e == io_dptReq_0_bits_phy_rs1 ? io_irgLog_30 : _GEN_1419; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1421 = 6'h1f == io_dptReq_0_bits_phy_rs1 ? io_irgLog_31 : _GEN_1420; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1422 = 6'h20 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_32 : _GEN_1421; // @[Issue.scala 232:{44,44}]
  wire [1:0] _GEN_1423 = 6'h21 == io_dptReq_0_bits_phy_rs1 ? io_irgLog_33 : _GEN_1422; // @[Issue.scala 232:{44,44}]
  wire  _canIOpPostReq_0_0_T_1 = io_dptReq_0_bits_phy_rs1 != 6'h21; // @[Issue.scala 233:33]
  wire  _canIOpPostReq_0_0_T_2 = _GEN_1423 == 2'h3 & _canIOpPostReq_0_0_T_1; // @[Issue.scala 232:56]
  wire  _canIOpPostReq_0_0_T_6 = io_dptReq_0_bits_fpu_isa_fmadd_s | io_dptReq_0_bits_fpu_isa_fmsub_s |
    io_dptReq_0_bits_fpu_isa_fnmsub_s | io_dptReq_0_bits_fpu_isa_fnmadd_s | io_dptReq_0_bits_fpu_isa_fmadd_d; // @[riscv_isa.scala 391:51]
  wire  _canIOpPostReq_0_0_T_10 = _canIOpPostReq_0_0_T_6 | io_dptReq_0_bits_fpu_isa_fmsub_d |
    io_dptReq_0_bits_fpu_isa_fnmsub_d | io_dptReq_0_bits_fpu_isa_fnmadd_d | io_dptReq_0_bits_fpu_isa_fadd_s; // @[riscv_isa.scala 392:51]
  wire  _canIOpPostReq_0_0_T_15 = _canIOpPostReq_0_0_T_10 | io_dptReq_0_bits_fpu_isa_fsub_s |
    io_dptReq_0_bits_fpu_isa_fmul_s | io_dptReq_0_bits_fpu_isa_fdiv_s | io_dptReq_0_bits_fpu_isa_fsqrt_s |
    io_dptReq_0_bits_fpu_isa_fadd_d; // @[riscv_isa.scala 393:63]
  wire  _canIOpPostReq_0_0_T_20 = _canIOpPostReq_0_0_T_15 | io_dptReq_0_bits_fpu_isa_fsub_d |
    io_dptReq_0_bits_fpu_isa_fmul_d | io_dptReq_0_bits_fpu_isa_fdiv_d | io_dptReq_0_bits_fpu_isa_fsqrt_d |
    io_dptReq_0_bits_fpu_isa_fsgnj_s; // @[riscv_isa.scala 394:63]
  wire  _canIOpPostReq_0_0_T_23 = _canIOpPostReq_0_0_T_20 | io_dptReq_0_bits_fpu_isa_fsgnjn_s |
    io_dptReq_0_bits_fpu_isa_fsgnjx_s | io_dptReq_0_bits_fpu_isa_fsgnj_d; // @[riscv_isa.scala 395:39]
  wire  _canIOpPostReq_0_0_T_26 = _canIOpPostReq_0_0_T_23 | io_dptReq_0_bits_fpu_isa_fsgnjn_d |
    io_dptReq_0_bits_fpu_isa_fsgnjx_d | io_dptReq_0_bits_fpu_isa_fmin_s; // @[riscv_isa.scala 396:39]
  wire  _canIOpPostReq_0_0_T_30 = _canIOpPostReq_0_0_T_26 | io_dptReq_0_bits_fpu_isa_fmax_s |
    io_dptReq_0_bits_fpu_isa_fmin_d | io_dptReq_0_bits_fpu_isa_fmax_d | io_dptReq_0_bits_fpu_isa_fmv_x_w; // @[riscv_isa.scala 397:51]
  wire  _canIOpPostReq_0_0_T_32 = _canIOpPostReq_0_0_T_30 | io_dptReq_0_bits_fpu_isa_fmv_x_d |
    io_dptReq_0_bits_fpu_isa_feq_s; // @[riscv_isa.scala 398:27]
  wire  _canIOpPostReq_0_0_T_35 = _canIOpPostReq_0_0_T_32 | io_dptReq_0_bits_fpu_isa_flt_s |
    io_dptReq_0_bits_fpu_isa_fle_s | io_dptReq_0_bits_fpu_isa_feq_d; // @[riscv_isa.scala 399:39]
  wire  _canIOpPostReq_0_0_T_38 = _canIOpPostReq_0_0_T_35 | io_dptReq_0_bits_fpu_isa_flt_d |
    io_dptReq_0_bits_fpu_isa_fle_d | io_dptReq_0_bits_fpu_isa_fclass_s; // @[riscv_isa.scala 400:39]
  wire  _canIOpPostReq_0_0_T_40 = _canIOpPostReq_0_0_T_38 | io_dptReq_0_bits_fpu_isa_fclass_d |
    io_dptReq_0_bits_fpu_isa_fcvt_w_s; // @[riscv_isa.scala 401:27]
  wire  _canIOpPostReq_0_0_T_44 = _canIOpPostReq_0_0_T_40 | io_dptReq_0_bits_fpu_isa_fcvt_wu_s |
    io_dptReq_0_bits_fpu_isa_fcvt_l_s | io_dptReq_0_bits_fpu_isa_fcvt_lu_s | io_dptReq_0_bits_fpu_isa_fcvt_w_d; // @[riscv_isa.scala 402:51]
  wire  _canIOpPostReq_0_0_T_48 = _canIOpPostReq_0_0_T_44 | io_dptReq_0_bits_fpu_isa_fcvt_wu_d |
    io_dptReq_0_bits_fpu_isa_fcvt_l_d | io_dptReq_0_bits_fpu_isa_fcvt_lu_d | io_dptReq_0_bits_fpu_isa_fcvt_s_d; // @[riscv_isa.scala 403:51]
  wire  _canIOpPostReq_0_0_T_49 = _canIOpPostReq_0_0_T_48 | io_dptReq_0_bits_fpu_isa_fcvt_d_s; // @[riscv_isa.scala 404:15]
  wire  _canIOpPostReq_0_0_T_50 = ~_canIOpPostReq_0_0_T_49; // @[Issue.scala 234:7]
  wire  canIOpPostReq_0_0 = _canIOpPostReq_0_0_T_2 & _canIOpPostReq_0_0_T_50; // @[Issue.scala 233:50]
  wire [1:0] _GEN_1425 = 6'h1 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_1 : io_irgLog_0; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1426 = 6'h2 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_2 : _GEN_1425; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1427 = 6'h3 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_3 : _GEN_1426; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1428 = 6'h4 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_4 : _GEN_1427; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1429 = 6'h5 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_5 : _GEN_1428; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1430 = 6'h6 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_6 : _GEN_1429; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1431 = 6'h7 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_7 : _GEN_1430; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1432 = 6'h8 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_8 : _GEN_1431; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1433 = 6'h9 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_9 : _GEN_1432; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1434 = 6'ha == io_dptReq_0_bits_phy_rs2 ? io_irgLog_10 : _GEN_1433; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1435 = 6'hb == io_dptReq_0_bits_phy_rs2 ? io_irgLog_11 : _GEN_1434; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1436 = 6'hc == io_dptReq_0_bits_phy_rs2 ? io_irgLog_12 : _GEN_1435; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1437 = 6'hd == io_dptReq_0_bits_phy_rs2 ? io_irgLog_13 : _GEN_1436; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1438 = 6'he == io_dptReq_0_bits_phy_rs2 ? io_irgLog_14 : _GEN_1437; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1439 = 6'hf == io_dptReq_0_bits_phy_rs2 ? io_irgLog_15 : _GEN_1438; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1440 = 6'h10 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_16 : _GEN_1439; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1441 = 6'h11 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_17 : _GEN_1440; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1442 = 6'h12 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_18 : _GEN_1441; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1443 = 6'h13 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_19 : _GEN_1442; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1444 = 6'h14 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_20 : _GEN_1443; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1445 = 6'h15 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_21 : _GEN_1444; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1446 = 6'h16 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_22 : _GEN_1445; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1447 = 6'h17 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_23 : _GEN_1446; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1448 = 6'h18 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_24 : _GEN_1447; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1449 = 6'h19 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_25 : _GEN_1448; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1450 = 6'h1a == io_dptReq_0_bits_phy_rs2 ? io_irgLog_26 : _GEN_1449; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1451 = 6'h1b == io_dptReq_0_bits_phy_rs2 ? io_irgLog_27 : _GEN_1450; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1452 = 6'h1c == io_dptReq_0_bits_phy_rs2 ? io_irgLog_28 : _GEN_1451; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1453 = 6'h1d == io_dptReq_0_bits_phy_rs2 ? io_irgLog_29 : _GEN_1452; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1454 = 6'h1e == io_dptReq_0_bits_phy_rs2 ? io_irgLog_30 : _GEN_1453; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1455 = 6'h1f == io_dptReq_0_bits_phy_rs2 ? io_irgLog_31 : _GEN_1454; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1456 = 6'h20 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_32 : _GEN_1455; // @[Issue.scala 238:{44,44}]
  wire [1:0] _GEN_1457 = 6'h21 == io_dptReq_0_bits_phy_rs2 ? io_irgLog_33 : _GEN_1456; // @[Issue.scala 238:{44,44}]
  wire  _canIOpPostReq_0_1_T_1 = io_dptReq_0_bits_phy_rs2 != 6'h21; // @[Issue.scala 239:33]
  wire  _canIOpPostReq_0_1_T_2 = _GEN_1457 == 2'h3 & _canIOpPostReq_0_1_T_1; // @[Issue.scala 238:56]
  wire  _canIOpPostReq_0_1_T_51 = _canIOpPostReq_0_1_T_2 & _canIOpPostReq_0_0_T_50; // @[Issue.scala 239:50]
  wire  _canIOpPostReq_0_1_T_52 = io_dptReq_0_bits_lsu_isa_fsw | io_dptReq_0_bits_lsu_isa_fsd; // @[riscv_isa.scala 164:20]
  wire  canIOpPostReq_0_1 = _canIOpPostReq_0_1_T_51 & ~_canIOpPostReq_0_1_T_52; // @[Issue.scala 240:42]
  wire  maskCondSelIRS1_0_0 = _entrySel_T | ~canIOpReq_0_0; // @[Issue.scala 256:49]
  wire  maskCondSelIRS2_0_0 = _entrySel_T | ~canIOpReq_0_1; // @[Issue.scala 257:49]
  wire  maskCondSelIRS1_0_1 = _io_dptReq_0_ready_T_1 | ~canIOpReq_1_0; // @[Issue.scala 256:49]
  wire  maskCondSelIRS2_0_1 = _io_dptReq_0_ready_T_1 | ~canIOpReq_1_1; // @[Issue.scala 257:49]
  wire  _maskCondSelIRS1_0_2_T_1 = ~_T; // @[Issue.scala 260:45]
  wire  maskCondSelIRS1_0_2 = ~_T | ~canIOpPostReq_0_0; // @[Issue.scala 260:64]
  wire  maskCondSelIRS2_0_2 = _maskCondSelIRS1_0_2_T_1 | ~canIOpPostReq_0_1; // @[Issue.scala 261:64]
  wire  _matrixOut_0_0_T = ~maskCondSelIRS1_0_0; // @[Issue.scala 200:46]
  wire  matrixOut__0_0 = ageMatrixW_0_0 & ~maskCondSelIRS1_0_0 | maskCondSelIRS1_0_0; // @[Issue.scala 200:60]
  wire  _matrixOut_0_1_T = ~maskCondSelIRS1_0_1; // @[Issue.scala 200:46]
  wire  matrixOut__0_1 = ageMatrixW_0_1 & ~maskCondSelIRS1_0_1 | maskCondSelIRS1_0_0; // @[Issue.scala 200:60]
  wire  _matrixOut_0_2_T = ~maskCondSelIRS1_0_2; // @[Issue.scala 200:46]
  wire  matrixOut__1_0 = ageMatrixR_1_0 & ~maskCondSelIRS1_0_0 | maskCondSelIRS1_0_1; // @[Issue.scala 200:60]
  wire  matrixOut__1_1 = ageMatrixW_1_1 & ~maskCondSelIRS1_0_1 | maskCondSelIRS1_0_1; // @[Issue.scala 200:60]
  wire  matrixOut__2_0 = ~maskCondSelIRS1_0_0 | maskCondSelIRS1_0_2; // @[Issue.scala 200:60]
  wire  matrixOut__2_1 = ~maskCondSelIRS1_0_1 | maskCondSelIRS1_0_2; // @[Issue.scala 200:60]
  wire  _matrixOut_0_0_T_3 = ~maskCondSelIRS2_0_0; // @[Issue.scala 200:46]
  wire  matrixOut_1_0_0 = ageMatrixW_0_0 & ~maskCondSelIRS2_0_0 | maskCondSelIRS2_0_0; // @[Issue.scala 200:60]
  wire  _matrixOut_0_1_T_3 = ~maskCondSelIRS2_0_1; // @[Issue.scala 200:46]
  wire  matrixOut_1_0_1 = ageMatrixW_0_1 & ~maskCondSelIRS2_0_1 | maskCondSelIRS2_0_0; // @[Issue.scala 200:60]
  wire  _matrixOut_0_2_T_3 = ~maskCondSelIRS2_0_2; // @[Issue.scala 200:46]
  wire  matrixOut_1_1_0 = ageMatrixR_1_0 & ~maskCondSelIRS2_0_0 | maskCondSelIRS2_0_1; // @[Issue.scala 200:60]
  wire  matrixOut_1_1_1 = ageMatrixW_1_1 & ~maskCondSelIRS2_0_1 | maskCondSelIRS2_0_1; // @[Issue.scala 200:60]
  wire  matrixOut_1_2_0 = ~maskCondSelIRS2_0_0 | maskCondSelIRS2_0_2; // @[Issue.scala 200:60]
  wire  matrixOut_1_2_1 = ~maskCondSelIRS2_0_1 | maskCondSelIRS2_0_2; // @[Issue.scala 200:60]
  wire  _T_33 = ~matrixOut__0_0 & ~matrixOut__0_1 & _matrixOut_0_0_T; // @[Issue.scala 278:66]
  wire  _T_39 = ~matrixOut__1_0 & ~matrixOut__1_1 & _matrixOut_0_1_T; // @[Issue.scala 278:66]
  wire  _T_45 = ~matrixOut__2_0 & ~matrixOut__2_1 & _matrixOut_0_2_T; // @[Issue.scala 278:66]
  wire [1:0] _T_46 = _T_39 + _T_45; // @[Bitwise.scala 51:90]
  wire [1:0] _GEN_204 = {{1'd0}, _T_33}; // @[Bitwise.scala 51:90]
  wire [2:0] _T_48 = _GEN_204 + _T_46; // @[Bitwise.scala 51:90]
  wire  _T_50 = _T_48[1:0] == 2'h1; // @[Issue.scala 278:101]
  wire  _T_51 = matrixOut__0_0 & matrixOut__0_1 & maskCondSelIRS1_0_0 & (matrixOut__1_0 & matrixOut__1_1 &
    maskCondSelIRS1_0_1) & (matrixOut__2_0 & matrixOut__2_1 & maskCondSelIRS1_0_2) | _T_50; // @[Issue.scala 277:92]
  wire  _T_53 = ~reset; // @[Issue.scala 276:11]
  wire  _T_81 = ~matrixOut_1_0_0 & ~matrixOut_1_0_1 & _matrixOut_0_0_T_3; // @[Issue.scala 283:66]
  wire  _T_87 = ~matrixOut_1_1_0 & ~matrixOut_1_1_1 & _matrixOut_0_1_T_3; // @[Issue.scala 283:66]
  wire  _T_93 = ~matrixOut_1_2_0 & ~matrixOut_1_2_1 & _matrixOut_0_2_T_3; // @[Issue.scala 283:66]
  wire [1:0] _T_94 = _T_87 + _T_93; // @[Bitwise.scala 51:90]
  wire [1:0] _GEN_205 = {{1'd0}, _T_81}; // @[Bitwise.scala 51:90]
  wire [2:0] _T_96 = _GEN_205 + _T_94; // @[Bitwise.scala 51:90]
  wire  _T_98 = _T_96[1:0] == 2'h1; // @[Issue.scala 283:101]
  wire  _T_99 = matrixOut_1_0_0 & matrixOut_1_0_1 & maskCondSelIRS2_0_0 & (matrixOut_1_1_0 & matrixOut_1_1_1 &
    maskCondSelIRS2_0_1) & (matrixOut_1_2_0 & matrixOut_1_2_1 & maskCondSelIRS2_0_2) | _T_98; // @[Issue.scala 282:93]
  wire [5:0] bufReqNum_0_2 = bufInfo_0_phy_rs3; // @[Issue.scala 146:21 63:26]
  wire [5:0] bufReqNum_1_2 = bufInfo_1_phy_rs3; // @[Issue.scala 146:21 63:26]
  wire [1:0] _GEN_1663 = 6'h1 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_1 : io_frgLog_0; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1664 = 6'h2 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_2 : _GEN_1663; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1665 = 6'h3 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_3 : _GEN_1664; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1666 = 6'h4 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_4 : _GEN_1665; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1667 = 6'h5 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_5 : _GEN_1666; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1668 = 6'h6 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_6 : _GEN_1667; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1669 = 6'h7 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_7 : _GEN_1668; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1670 = 6'h8 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_8 : _GEN_1669; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1671 = 6'h9 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_9 : _GEN_1670; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1672 = 6'ha == io_dptReq_0_bits_phy_rs1 ? io_frgLog_10 : _GEN_1671; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1673 = 6'hb == io_dptReq_0_bits_phy_rs1 ? io_frgLog_11 : _GEN_1672; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1674 = 6'hc == io_dptReq_0_bits_phy_rs1 ? io_frgLog_12 : _GEN_1673; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1675 = 6'hd == io_dptReq_0_bits_phy_rs1 ? io_frgLog_13 : _GEN_1674; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1676 = 6'he == io_dptReq_0_bits_phy_rs1 ? io_frgLog_14 : _GEN_1675; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1677 = 6'hf == io_dptReq_0_bits_phy_rs1 ? io_frgLog_15 : _GEN_1676; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1678 = 6'h10 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_16 : _GEN_1677; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1679 = 6'h11 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_17 : _GEN_1678; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1680 = 6'h12 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_18 : _GEN_1679; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1681 = 6'h13 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_19 : _GEN_1680; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1682 = 6'h14 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_20 : _GEN_1681; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1683 = 6'h15 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_21 : _GEN_1682; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1684 = 6'h16 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_22 : _GEN_1683; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1685 = 6'h17 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_23 : _GEN_1684; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1686 = 6'h18 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_24 : _GEN_1685; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1687 = 6'h19 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_25 : _GEN_1686; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1688 = 6'h1a == io_dptReq_0_bits_phy_rs1 ? io_frgLog_26 : _GEN_1687; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1689 = 6'h1b == io_dptReq_0_bits_phy_rs1 ? io_frgLog_27 : _GEN_1688; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1690 = 6'h1c == io_dptReq_0_bits_phy_rs1 ? io_frgLog_28 : _GEN_1689; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1691 = 6'h1d == io_dptReq_0_bits_phy_rs1 ? io_frgLog_29 : _GEN_1690; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1692 = 6'h1e == io_dptReq_0_bits_phy_rs1 ? io_frgLog_30 : _GEN_1691; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1693 = 6'h1f == io_dptReq_0_bits_phy_rs1 ? io_frgLog_31 : _GEN_1692; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1694 = 6'h20 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_32 : _GEN_1693; // @[Issue.scala 356:{44,44}]
  wire [1:0] _GEN_1695 = 6'h21 == io_dptReq_0_bits_phy_rs1 ? io_frgLog_33 : _GEN_1694; // @[Issue.scala 356:{44,44}]
  wire  _canFOpPostReq_0_0_T_2 = _GEN_1695 == 2'h3 & _canIOpPostReq_0_0_T_1; // @[Issue.scala 356:56]
  wire  canFOpPostReq_0_0 = _canFOpPostReq_0_0_T_2 & _canIOpPostReq_0_0_T_49; // @[Issue.scala 357:50]
  wire [1:0] _GEN_1697 = 6'h1 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_1 : io_frgLog_0; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1698 = 6'h2 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_2 : _GEN_1697; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1699 = 6'h3 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_3 : _GEN_1698; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1700 = 6'h4 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_4 : _GEN_1699; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1701 = 6'h5 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_5 : _GEN_1700; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1702 = 6'h6 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_6 : _GEN_1701; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1703 = 6'h7 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_7 : _GEN_1702; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1704 = 6'h8 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_8 : _GEN_1703; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1705 = 6'h9 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_9 : _GEN_1704; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1706 = 6'ha == io_dptReq_0_bits_phy_rs2 ? io_frgLog_10 : _GEN_1705; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1707 = 6'hb == io_dptReq_0_bits_phy_rs2 ? io_frgLog_11 : _GEN_1706; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1708 = 6'hc == io_dptReq_0_bits_phy_rs2 ? io_frgLog_12 : _GEN_1707; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1709 = 6'hd == io_dptReq_0_bits_phy_rs2 ? io_frgLog_13 : _GEN_1708; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1710 = 6'he == io_dptReq_0_bits_phy_rs2 ? io_frgLog_14 : _GEN_1709; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1711 = 6'hf == io_dptReq_0_bits_phy_rs2 ? io_frgLog_15 : _GEN_1710; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1712 = 6'h10 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_16 : _GEN_1711; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1713 = 6'h11 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_17 : _GEN_1712; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1714 = 6'h12 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_18 : _GEN_1713; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1715 = 6'h13 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_19 : _GEN_1714; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1716 = 6'h14 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_20 : _GEN_1715; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1717 = 6'h15 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_21 : _GEN_1716; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1718 = 6'h16 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_22 : _GEN_1717; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1719 = 6'h17 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_23 : _GEN_1718; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1720 = 6'h18 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_24 : _GEN_1719; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1721 = 6'h19 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_25 : _GEN_1720; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1722 = 6'h1a == io_dptReq_0_bits_phy_rs2 ? io_frgLog_26 : _GEN_1721; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1723 = 6'h1b == io_dptReq_0_bits_phy_rs2 ? io_frgLog_27 : _GEN_1722; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1724 = 6'h1c == io_dptReq_0_bits_phy_rs2 ? io_frgLog_28 : _GEN_1723; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1725 = 6'h1d == io_dptReq_0_bits_phy_rs2 ? io_frgLog_29 : _GEN_1724; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1726 = 6'h1e == io_dptReq_0_bits_phy_rs2 ? io_frgLog_30 : _GEN_1725; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1727 = 6'h1f == io_dptReq_0_bits_phy_rs2 ? io_frgLog_31 : _GEN_1726; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1728 = 6'h20 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_32 : _GEN_1727; // @[Issue.scala 362:{44,44}]
  wire [1:0] _GEN_1729 = 6'h21 == io_dptReq_0_bits_phy_rs2 ? io_frgLog_33 : _GEN_1728; // @[Issue.scala 362:{44,44}]
  wire  _canFOpPostReq_0_1_T_2 = _GEN_1729 == 2'h3 & _canIOpPostReq_0_1_T_1; // @[Issue.scala 362:56]
  wire  _canFOpPostReq_0_1_T_51 = _canIOpPostReq_0_0_T_49 | _canIOpPostReq_0_1_T_52; // @[Issue.scala 364:41]
  wire  canFOpPostReq_0_1 = _canFOpPostReq_0_1_T_2 & _canFOpPostReq_0_1_T_51; // @[Issue.scala 363:50]
  wire [1:0] _GEN_1731 = 6'h1 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_1 : io_frgLog_0; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1732 = 6'h2 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_2 : _GEN_1731; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1733 = 6'h3 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_3 : _GEN_1732; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1734 = 6'h4 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_4 : _GEN_1733; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1735 = 6'h5 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_5 : _GEN_1734; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1736 = 6'h6 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_6 : _GEN_1735; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1737 = 6'h7 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_7 : _GEN_1736; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1738 = 6'h8 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_8 : _GEN_1737; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1739 = 6'h9 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_9 : _GEN_1738; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1740 = 6'ha == io_dptReq_0_bits_phy_rs3 ? io_frgLog_10 : _GEN_1739; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1741 = 6'hb == io_dptReq_0_bits_phy_rs3 ? io_frgLog_11 : _GEN_1740; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1742 = 6'hc == io_dptReq_0_bits_phy_rs3 ? io_frgLog_12 : _GEN_1741; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1743 = 6'hd == io_dptReq_0_bits_phy_rs3 ? io_frgLog_13 : _GEN_1742; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1744 = 6'he == io_dptReq_0_bits_phy_rs3 ? io_frgLog_14 : _GEN_1743; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1745 = 6'hf == io_dptReq_0_bits_phy_rs3 ? io_frgLog_15 : _GEN_1744; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1746 = 6'h10 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_16 : _GEN_1745; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1747 = 6'h11 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_17 : _GEN_1746; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1748 = 6'h12 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_18 : _GEN_1747; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1749 = 6'h13 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_19 : _GEN_1748; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1750 = 6'h14 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_20 : _GEN_1749; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1751 = 6'h15 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_21 : _GEN_1750; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1752 = 6'h16 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_22 : _GEN_1751; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1753 = 6'h17 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_23 : _GEN_1752; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1754 = 6'h18 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_24 : _GEN_1753; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1755 = 6'h19 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_25 : _GEN_1754; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1756 = 6'h1a == io_dptReq_0_bits_phy_rs3 ? io_frgLog_26 : _GEN_1755; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1757 = 6'h1b == io_dptReq_0_bits_phy_rs3 ? io_frgLog_27 : _GEN_1756; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1758 = 6'h1c == io_dptReq_0_bits_phy_rs3 ? io_frgLog_28 : _GEN_1757; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1759 = 6'h1d == io_dptReq_0_bits_phy_rs3 ? io_frgLog_29 : _GEN_1758; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1760 = 6'h1e == io_dptReq_0_bits_phy_rs3 ? io_frgLog_30 : _GEN_1759; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1761 = 6'h1f == io_dptReq_0_bits_phy_rs3 ? io_frgLog_31 : _GEN_1760; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1762 = 6'h20 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_32 : _GEN_1761; // @[Issue.scala 368:{44,44}]
  wire [1:0] _GEN_1763 = 6'h21 == io_dptReq_0_bits_phy_rs3 ? io_frgLog_33 : _GEN_1762; // @[Issue.scala 368:{44,44}]
  wire  _canFOpPostReq_0_2_T_1 = io_dptReq_0_bits_phy_rs3 != 6'h21; // @[Issue.scala 369:33]
  wire  _canFOpPostReq_0_2_T_2 = _GEN_1763 == 2'h3 & _canFOpPostReq_0_2_T_1; // @[Issue.scala 368:56]
  wire  canFOpPostReq_0_2 = _canFOpPostReq_0_2_T_2 & _canIOpPostReq_0_0_T_49; // @[Issue.scala 369:50]
  wire  maskCondSelFRS1_0_2 = _maskCondSelIRS1_0_2_T_1 | ~canFOpPostReq_0_0; // @[Issue.scala 392:64]
  wire  maskCondSelFRS2_0_2 = _maskCondSelIRS1_0_2_T_1 | ~canFOpPostReq_0_1; // @[Issue.scala 393:64]
  wire  maskCondSelFRS3_0_2 = _maskCondSelIRS1_0_2_T_1 | ~canFOpPostReq_0_2; // @[Issue.scala 394:64]
  wire  _matrixOut_0_2_T_6 = ~maskCondSelFRS1_0_2; // @[Issue.scala 200:46]
  wire  _matrixOut_0_2_T_9 = ~maskCondSelFRS2_0_2; // @[Issue.scala 200:46]
  wire  _matrixOut_0_2_T_12 = ~maskCondSelFRS3_0_2; // @[Issue.scala 200:46]
  wire  _T_141 = _matrixOut_0_2_T_6 & _matrixOut_0_2_T_6 & _matrixOut_0_2_T_6; // @[Issue.scala 414:66]
  wire [1:0] _T_142 = {{1'd0}, _T_141}; // @[Bitwise.scala 51:90]
  wire [2:0] _T_144 = {{1'd0}, _T_142}; // @[Bitwise.scala 51:90]
  wire  _T_146 = _T_144[1:0] == 2'h1; // @[Issue.scala 414:101]
  wire  _T_147 = maskCondSelFRS1_0_2 | _T_146; // @[Issue.scala 413:92]
  wire  _T_189 = _matrixOut_0_2_T_9 & _matrixOut_0_2_T_9 & _matrixOut_0_2_T_9; // @[Issue.scala 419:66]
  wire [1:0] _T_190 = {{1'd0}, _T_189}; // @[Bitwise.scala 51:90]
  wire [2:0] _T_192 = {{1'd0}, _T_190}; // @[Bitwise.scala 51:90]
  wire  _T_194 = _T_192[1:0] == 2'h1; // @[Issue.scala 419:101]
  wire  _T_195 = maskCondSelFRS2_0_2 | _T_194; // @[Issue.scala 418:93]
  wire  _T_237 = _matrixOut_0_2_T_12 & _matrixOut_0_2_T_12 & _matrixOut_0_2_T_12; // @[Issue.scala 424:66]
  wire [1:0] _T_238 = {{1'd0}, _T_237}; // @[Bitwise.scala 51:90]
  wire [2:0] _T_240 = {{1'd0}, _T_238}; // @[Bitwise.scala 51:90]
  wire  _T_242 = _T_240[1:0] == 2'h1; // @[Issue.scala 424:101]
  wire  _T_243 = maskCondSelFRS3_0_2 | _T_242; // @[Issue.scala 423:93]
  wire  _GEN_1764 = bufValid_0 & bufReqNum_0_0 == io_irgRsp_0_bits_phy | _GEN_1230; // @[Issue.scala 489:98 491:32]
  wire  _GEN_1766 = bufValid_0 & bufReqNum_0_1 == io_irgRsp_0_bits_phy | _GEN_1234; // @[Issue.scala 489:98 491:32]
  wire  _GEN_1768 = bufValid_1 & bufReqNum_1_0 == io_irgRsp_0_bits_phy | _GEN_1231; // @[Issue.scala 489:98 491:32]
  wire  _GEN_1770 = bufValid_1 & bufReqNum_1_1 == io_irgRsp_0_bits_phy | _GEN_1235; // @[Issue.scala 489:98 491:32]
  wire  postIsOpReady_0_0 = _canIOpReq_0_0_T_6 | isOpReady_0_0; // @[Mux.scala 101:16]
  wire  postIsOpReady_0_1 = _canIOpReq_0_1_T_6 | isOpReady_0_1; // @[Mux.scala 101:16]
  wire  postIsOpReady_1_0 = _canIOpReq_1_0_T_6 | isOpReady_1_0; // @[Mux.scala 101:16]
  wire  postIsOpReady_1_1 = _canIOpReq_1_1_T_6 | isOpReady_1_1; // @[Mux.scala 101:16]
  wire  _maskCondAluIss_0_0_T_30 = bufInfo_0_alu_isa_lui | bufInfo_0_alu_isa_auipc | bufInfo_0_alu_isa_addi |
    bufInfo_0_alu_isa_addiw | bufInfo_0_alu_isa_slti | bufInfo_0_alu_isa_sltiu | bufInfo_0_alu_isa_xori |
    bufInfo_0_alu_isa_ori | bufInfo_0_alu_isa_andi | bufInfo_0_alu_isa_slli | bufInfo_0_alu_isa_slliw |
    bufInfo_0_alu_isa_srli | bufInfo_0_alu_isa_srliw | bufInfo_0_alu_isa_srai | bufInfo_0_alu_isa_sraiw |
    bufInfo_0_alu_isa_add | bufInfo_0_alu_isa_addw | bufInfo_0_alu_isa_sub | bufInfo_0_alu_isa_subw |
    bufInfo_0_alu_isa_sll | bufInfo_0_alu_isa_sllw | bufInfo_0_alu_isa_slt | bufInfo_0_alu_isa_sltu |
    bufInfo_0_alu_isa_xor | bufInfo_0_alu_isa_srl | bufInfo_0_alu_isa_srlw | bufInfo_0_alu_isa_sra |
    bufInfo_0_alu_isa_sraw | bufInfo_0_alu_isa_or | bufInfo_0_alu_isa_and | bufInfo_0_alu_isa_wfi; // @[riscv_isa.scala 78:217]
  wire  _maskCondAluIss_0_0_T_31 = ~_maskCondAluIss_0_0_T_30; // @[Issue.scala 617:11]
  wire  _maskCondAluIss_0_0_T_32 = _entrySel_T | _maskCondAluIss_0_0_T_31; // @[Issue.scala 616:24]
  wire  _maskCondAluIss_0_0_T_33 = postIsOpReady_0_0 & postIsOpReady_0_1; // @[Issue.scala 618:33]
  wire  _maskCondAluIss_0_0_T_34 = ~(postIsOpReady_0_0 & postIsOpReady_0_1); // @[Issue.scala 618:11]
  wire  maskCondAluIss_0_0 = _maskCondAluIss_0_0_T_32 | _maskCondAluIss_0_0_T_34; // @[Issue.scala 617:38]
  wire  _maskCondAluIss_0_1_T_30 = bufInfo_1_alu_isa_lui | bufInfo_1_alu_isa_auipc | bufInfo_1_alu_isa_addi |
    bufInfo_1_alu_isa_addiw | bufInfo_1_alu_isa_slti | bufInfo_1_alu_isa_sltiu | bufInfo_1_alu_isa_xori |
    bufInfo_1_alu_isa_ori | bufInfo_1_alu_isa_andi | bufInfo_1_alu_isa_slli | bufInfo_1_alu_isa_slliw |
    bufInfo_1_alu_isa_srli | bufInfo_1_alu_isa_srliw | bufInfo_1_alu_isa_srai | bufInfo_1_alu_isa_sraiw |
    bufInfo_1_alu_isa_add | bufInfo_1_alu_isa_addw | bufInfo_1_alu_isa_sub | bufInfo_1_alu_isa_subw |
    bufInfo_1_alu_isa_sll | bufInfo_1_alu_isa_sllw | bufInfo_1_alu_isa_slt | bufInfo_1_alu_isa_sltu |
    bufInfo_1_alu_isa_xor | bufInfo_1_alu_isa_srl | bufInfo_1_alu_isa_srlw | bufInfo_1_alu_isa_sra |
    bufInfo_1_alu_isa_sraw | bufInfo_1_alu_isa_or | bufInfo_1_alu_isa_and | bufInfo_1_alu_isa_wfi; // @[riscv_isa.scala 78:217]
  wire  _maskCondAluIss_0_1_T_31 = ~_maskCondAluIss_0_1_T_30; // @[Issue.scala 617:11]
  wire  _maskCondAluIss_0_1_T_32 = _io_dptReq_0_ready_T_1 | _maskCondAluIss_0_1_T_31; // @[Issue.scala 616:24]
  wire  _maskCondAluIss_0_1_T_33 = postIsOpReady_1_0 & postIsOpReady_1_1; // @[Issue.scala 618:33]
  wire  _maskCondAluIss_0_1_T_34 = ~(postIsOpReady_1_0 & postIsOpReady_1_1); // @[Issue.scala 618:11]
  wire  maskCondAluIss_0_1 = _maskCondAluIss_0_1_T_32 | _maskCondAluIss_0_1_T_34; // @[Issue.scala 617:38]
  wire  matrixOut_5_0_0 = ageMatrixW_0_0 & ~maskCondAluIss_0_0 | maskCondAluIss_0_0; // @[Issue.scala 200:60]
  wire  matrixOut_5_0_1 = ageMatrixW_0_1 & ~maskCondAluIss_0_1 | maskCondAluIss_0_0; // @[Issue.scala 200:60]
  wire  matrixOut_5_1_0 = ageMatrixR_1_0 & ~maskCondAluIss_0_0 | maskCondAluIss_0_1; // @[Issue.scala 200:60]
  wire  matrixOut_5_1_1 = ageMatrixW_1_1 & ~maskCondAluIss_0_1 | maskCondAluIss_0_1; // @[Issue.scala 200:60]
  wire  _T_300 = matrixOut_5_0_0 & matrixOut_5_0_1 & (matrixOut_5_1_0 & matrixOut_5_1_1); // @[Issue.scala 628:31]
  wire  _T_304 = ~matrixOut_5_0_0 & ~matrixOut_5_0_1; // @[Issue.scala 629:65]
  wire  _T_308 = ~matrixOut_5_1_0 & ~matrixOut_5_1_1; // @[Issue.scala 629:65]
  wire [1:0] _T_309 = _T_304 + _T_308; // @[Bitwise.scala 51:90]
  wire  _T_311 = _T_309 == 2'h1; // @[Issue.scala 629:100]
  wire  _T_312 = matrixOut_5_0_0 & matrixOut_5_0_1 & (matrixOut_5_1_0 & matrixOut_5_1_1) | _T_311; // @[Issue.scala 628:92]
  wire  aluIssIdx_0 = _T_304 ? 1'h0 : 1'h1; // @[Issue.scala 635:51]
  wire  _T_316 = aluIssFifo_0_io_enq_ready & aluIssFifo_0_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_318 = _T_316 & ~aluIssIdx_0; // @[Issue.scala 640:41]
  wire  _GEN_1804 = _T_316 & ~aluIssIdx_0 ? 1'h0 : bufValidDnxt_0_0; // @[Issue.scala 640:68 641:21 75:12]
  wire  _T_361 = _T_316 & aluIssIdx_0; // @[Issue.scala 640:41]
  wire  _GEN_1805 = _T_316 & aluIssIdx_0 ? 1'h0 : bufValidDnxt_0_1; // @[Issue.scala 640:68 641:21 75:12]
  wire  _maskCondMulIss_0_0_T_4 = bufInfo_0_mul_isa_mul | bufInfo_0_mul_isa_mulh | bufInfo_0_mul_isa_mulhsu |
    bufInfo_0_mul_isa_mulhu | bufInfo_0_mul_isa_mulw; // @[riscv_isa.scala 203:43]
  wire  _maskCondMulIss_0_0_T_11 = bufInfo_0_mul_isa_div | bufInfo_0_mul_isa_divu | bufInfo_0_mul_isa_divw |
    bufInfo_0_mul_isa_divuw | bufInfo_0_mul_isa_rem | bufInfo_0_mul_isa_remu | bufInfo_0_mul_isa_remw |
    bufInfo_0_mul_isa_remuw; // @[riscv_isa.scala 204:61]
  wire  _maskCondMulIss_0_0_T_12 = _maskCondMulIss_0_0_T_4 | _maskCondMulIss_0_0_T_11; // @[riscv_isa.scala 206:25]
  wire  _maskCondMulIss_0_0_T_13 = ~_maskCondMulIss_0_0_T_12; // @[Issue.scala 682:13]
  wire  _maskCondMulIss_0_0_T_14 = _entrySel_T | _maskCondMulIss_0_0_T_13; // @[Issue.scala 681:26]
  wire  maskCondMulIss_0_0 = _maskCondMulIss_0_0_T_14 | _maskCondAluIss_0_0_T_34; // @[Issue.scala 682:43]
  wire  _maskCondMulIss_0_1_T_4 = bufInfo_1_mul_isa_mul | bufInfo_1_mul_isa_mulh | bufInfo_1_mul_isa_mulhsu |
    bufInfo_1_mul_isa_mulhu | bufInfo_1_mul_isa_mulw; // @[riscv_isa.scala 203:43]
  wire  _maskCondMulIss_0_1_T_11 = bufInfo_1_mul_isa_div | bufInfo_1_mul_isa_divu | bufInfo_1_mul_isa_divw |
    bufInfo_1_mul_isa_divuw | bufInfo_1_mul_isa_rem | bufInfo_1_mul_isa_remu | bufInfo_1_mul_isa_remw |
    bufInfo_1_mul_isa_remuw; // @[riscv_isa.scala 204:61]
  wire  _maskCondMulIss_0_1_T_12 = _maskCondMulIss_0_1_T_4 | _maskCondMulIss_0_1_T_11; // @[riscv_isa.scala 206:25]
  wire  _maskCondMulIss_0_1_T_13 = ~_maskCondMulIss_0_1_T_12; // @[Issue.scala 682:13]
  wire  _maskCondMulIss_0_1_T_14 = _io_dptReq_0_ready_T_1 | _maskCondMulIss_0_1_T_13; // @[Issue.scala 681:26]
  wire  maskCondMulIss_0_1 = _maskCondMulIss_0_1_T_14 | _maskCondAluIss_0_1_T_34; // @[Issue.scala 682:43]
  wire  matrixOut_6_0_0 = ageMatrixW_0_0 & ~maskCondMulIss_0_0 | maskCondMulIss_0_0; // @[Issue.scala 200:60]
  wire  matrixOut_6_0_1 = ageMatrixW_0_1 & ~maskCondMulIss_0_1 | maskCondMulIss_0_0; // @[Issue.scala 200:60]
  wire  matrixOut_6_1_0 = ageMatrixR_1_0 & ~maskCondMulIss_0_0 | maskCondMulIss_0_1; // @[Issue.scala 200:60]
  wire  matrixOut_6_1_1 = ageMatrixW_1_1 & ~maskCondMulIss_0_1 | maskCondMulIss_0_1; // @[Issue.scala 200:60]
  wire  _T_411 = matrixOut_6_0_0 & matrixOut_6_0_1 & (matrixOut_6_1_0 & matrixOut_6_1_1); // @[Issue.scala 693:33]
  wire  _T_415 = ~matrixOut_6_0_0 & ~matrixOut_6_0_1; // @[Issue.scala 694:67]
  wire  _T_419 = ~matrixOut_6_1_0 & ~matrixOut_6_1_1; // @[Issue.scala 694:67]
  wire [1:0] _T_420 = _T_415 + _T_419; // @[Bitwise.scala 51:90]
  wire  _T_422 = _T_420 == 2'h1; // @[Issue.scala 694:102]
  wire  _T_423 = matrixOut_6_0_0 & matrixOut_6_0_1 & (matrixOut_6_1_0 & matrixOut_6_1_1) | _T_422; // @[Issue.scala 693:95]
  wire  mulIssIdx_0 = _T_415 ? 1'h0 : 1'h1; // @[Issue.scala 700:53]
  wire  _T_427 = mulIssFifo_0_io_enq_ready & mulIssFifo_0_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_429 = _T_427 & ~mulIssIdx_0; // @[Issue.scala 705:43]
  wire  _GEN_1806 = _T_427 & ~mulIssIdx_0 ? 1'h0 : _GEN_1804; // @[Issue.scala 705:70 706:23]
  wire  _T_454 = _T_427 & mulIssIdx_0; // @[Issue.scala 705:43]
  wire  _GEN_1807 = _T_427 & mulIssIdx_0 ? 1'h0 : _GEN_1805; // @[Issue.scala 705:70 706:23]
  wire  _maskCondBruIss_0_T_7 = bufInfo_0_bru_isa_jal | bufInfo_0_bru_isa_jalr | bufInfo_0_bru_isa_beq |
    bufInfo_0_bru_isa_bne | bufInfo_0_bru_isa_blt | bufInfo_0_bru_isa_bge | bufInfo_0_bru_isa_bltu |
    bufInfo_0_bru_isa_bgeu; // @[riscv_isa.scala 92:58]
  wire  _maskCondBruIss_0_T_8 = ~_maskCondBruIss_0_T_7; // @[Issue.scala 752:7]
  wire  maskCondBruIss_0 = _entrySel_T | _maskCondBruIss_0_T_8; // @[Issue.scala 751:20]
  wire  _maskCondBruIss_1_T_7 = bufInfo_1_bru_isa_jal | bufInfo_1_bru_isa_jalr | bufInfo_1_bru_isa_beq |
    bufInfo_1_bru_isa_bne | bufInfo_1_bru_isa_blt | bufInfo_1_bru_isa_bge | bufInfo_1_bru_isa_bltu |
    bufInfo_1_bru_isa_bgeu; // @[riscv_isa.scala 92:58]
  wire  _maskCondBruIss_1_T_8 = ~_maskCondBruIss_1_T_7; // @[Issue.scala 752:7]
  wire  maskCondBruIss_1 = _io_dptReq_0_ready_T_1 | _maskCondBruIss_1_T_8; // @[Issue.scala 751:20]
  wire  matrixOut_7_0_0 = ageMatrixW_0_0 & ~maskCondBruIss_0 | maskCondBruIss_0; // @[Issue.scala 200:60]
  wire  matrixOut_7_0_1 = ageMatrixW_0_1 & ~maskCondBruIss_1 | maskCondBruIss_0; // @[Issue.scala 200:60]
  wire  matrixOut_7_1_0 = ageMatrixR_1_0 & ~maskCondBruIss_0 | maskCondBruIss_1; // @[Issue.scala 200:60]
  wire  matrixOut_7_1_1 = ageMatrixW_1_1 & ~maskCondBruIss_1 | maskCondBruIss_1; // @[Issue.scala 200:60]
  wire  _T_490 = ~matrixOut_7_0_0 & ~matrixOut_7_0_1; // @[Issue.scala 759:58]
  wire  _T_494 = ~matrixOut_7_1_0 & ~matrixOut_7_1_1; // @[Issue.scala 759:58]
  wire [1:0] _T_495 = _T_490 + _T_494; // @[Bitwise.scala 51:90]
  wire  _T_497 = _T_495 == 2'h1; // @[Issue.scala 759:92]
  wire  _T_498 = matrixOut_7_0_0 & matrixOut_7_0_1 & (matrixOut_7_1_0 & matrixOut_7_1_1) | _T_497; // @[Issue.scala 758:86]
  wire  bruIssIdx = _T_490 ? 1'h0 : 1'h1; // @[Issue.scala 762:39]
  wire  _T_502 = bruIssFifo_io_enq_ready & bruIssFifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_504 = _T_502 & ~bruIssIdx; // @[Issue.scala 771:34]
  wire  _T_524 = _T_502 & bruIssIdx; // @[Issue.scala 771:34]
  wire  _maskCondCsrIss_0_T_5 = bufInfo_0_csr_isa_rw | bufInfo_0_csr_isa_rs | bufInfo_0_csr_isa_rc |
    bufInfo_0_csr_isa_rwi | bufInfo_0_csr_isa_rsi | bufInfo_0_csr_isa_rci; // @[riscv_isa.scala 179:41]
  wire  _maskCondCsrIss_0_T_6 = ~_maskCondCsrIss_0_T_5; // @[Issue.scala 818:7]
  wire  maskCondCsrIss_0 = _entrySel_T | _maskCondCsrIss_0_T_6; // @[Issue.scala 817:20]
  wire  _maskCondCsrIss_1_T_5 = bufInfo_1_csr_isa_rw | bufInfo_1_csr_isa_rs | bufInfo_1_csr_isa_rc |
    bufInfo_1_csr_isa_rwi | bufInfo_1_csr_isa_rsi | bufInfo_1_csr_isa_rci; // @[riscv_isa.scala 179:41]
  wire  _maskCondCsrIss_1_T_6 = ~_maskCondCsrIss_1_T_5; // @[Issue.scala 818:7]
  wire  maskCondCsrIss_1 = _io_dptReq_0_ready_T_1 | _maskCondCsrIss_1_T_6; // @[Issue.scala 817:20]
  wire  matrixOut_8_0_0 = ageMatrixW_0_0 & ~maskCondCsrIss_0 | maskCondCsrIss_0; // @[Issue.scala 200:60]
  wire  matrixOut_8_0_1 = ageMatrixW_0_1 & ~maskCondCsrIss_1 | maskCondCsrIss_0; // @[Issue.scala 200:60]
  wire  matrixOut_8_1_0 = ageMatrixR_1_0 & ~maskCondCsrIss_0 | maskCondCsrIss_1; // @[Issue.scala 200:60]
  wire  matrixOut_8_1_1 = ageMatrixW_1_1 & ~maskCondCsrIss_1 | maskCondCsrIss_1; // @[Issue.scala 200:60]
  wire  _T_555 = ~matrixOut_8_0_0 & ~matrixOut_8_0_1; // @[Issue.scala 825:58]
  wire  _T_559 = ~matrixOut_8_1_0 & ~matrixOut_8_1_1; // @[Issue.scala 825:58]
  wire [1:0] _T_560 = _T_555 + _T_559; // @[Bitwise.scala 51:90]
  wire  _T_562 = _T_560 == 2'h1; // @[Issue.scala 825:92]
  wire  _T_563 = matrixOut_8_0_0 & matrixOut_8_0_1 & (matrixOut_8_1_0 & matrixOut_8_1_1) | _T_562; // @[Issue.scala 824:86]
  wire  csrIssIdx = _T_555 ? 1'h0 : 1'h1; // @[Issue.scala 828:39]
  wire  _T_567 = csrIssFifo_io_enq_ready & csrIssFifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_569 = _T_567 & ~csrIssIdx; // @[Issue.scala 837:34]
  wire  _T_587 = _T_567 & csrIssIdx; // @[Issue.scala 837:34]
  wire  _maskCondLsuIss_0_T_10 = bufInfo_0_lsu_isa_lb | bufInfo_0_lsu_isa_lh | bufInfo_0_lsu_isa_lw |
    bufInfo_0_lsu_isa_ld | bufInfo_0_lsu_isa_lbu | bufInfo_0_lsu_isa_lhu | bufInfo_0_lsu_isa_lwu | bufInfo_0_lsu_isa_sb
     | bufInfo_0_lsu_isa_sh | bufInfo_0_lsu_isa_sw | bufInfo_0_lsu_isa_sd; // @[riscv_isa.scala 145:67]
  wire  _maskCondLsuIss_0_T_11 = bufInfo_0_lsu_isa_sc_d | bufInfo_0_lsu_isa_sc_w; // @[riscv_isa.scala 140:20]
  wire  _maskCondLsuIss_0_T_12 = bufInfo_0_lsu_isa_lr_d | bufInfo_0_lsu_isa_lr_w; // @[riscv_isa.scala 141:20]
  wire  _maskCondLsuIss_0_T_13 = _maskCondLsuIss_0_T_11 | _maskCondLsuIss_0_T_12; // @[riscv_isa.scala 146:23]
  wire  _maskCondLsuIss_0_T_33 = bufInfo_0_lsu_isa_amoswap_w | bufInfo_0_lsu_isa_amoadd_w | bufInfo_0_lsu_isa_amoxor_w
     | bufInfo_0_lsu_isa_amoand_w | bufInfo_0_lsu_isa_amoor_w | bufInfo_0_lsu_isa_amomin_w | bufInfo_0_lsu_isa_amomax_w
     | bufInfo_0_lsu_isa_amominu_w | bufInfo_0_lsu_isa_amomaxu_w | bufInfo_0_lsu_isa_amoswap_d |
    bufInfo_0_lsu_isa_amoadd_d | bufInfo_0_lsu_isa_amoxor_d | bufInfo_0_lsu_isa_amoand_d | bufInfo_0_lsu_isa_amoor_d |
    bufInfo_0_lsu_isa_amomin_d | bufInfo_0_lsu_isa_amomax_d | bufInfo_0_lsu_isa_amominu_d | bufInfo_0_lsu_isa_amomaxu_d
     | _maskCondLsuIss_0_T_11; // @[riscv_isa.scala 148:205]
  wire  _maskCondLsuIss_0_T_37 = bufInfo_0_lsu_isa_flw | bufInfo_0_lsu_isa_fsw | bufInfo_0_lsu_isa_fld |
    bufInfo_0_lsu_isa_fsd; // @[riscv_isa.scala 149:32]
  wire  _maskCondLsuIss_0_T_40 = bufInfo_0_lsu_isa_fence | bufInfo_0_lsu_isa_fence_i | bufInfo_0_lsu_isa_sfence_vma; // @[riscv_isa.scala 150:34]
  wire  _maskCondLsuIss_0_T_41 = _maskCondLsuIss_0_T_10 | _maskCondLsuIss_0_T_13 | _maskCondLsuIss_0_T_33 |
    _maskCondLsuIss_0_T_37 | _maskCondLsuIss_0_T_40; // @[riscv_isa.scala 151:51]
  wire  _maskCondLsuIss_0_T_42 = ~_maskCondLsuIss_0_T_41; // @[Issue.scala 881:7]
  wire  maskCondLsuIss_0 = _entrySel_T | _maskCondLsuIss_0_T_42; // @[Issue.scala 880:20]
  wire  _maskCondLsuIss_1_T_10 = bufInfo_1_lsu_isa_lb | bufInfo_1_lsu_isa_lh | bufInfo_1_lsu_isa_lw |
    bufInfo_1_lsu_isa_ld | bufInfo_1_lsu_isa_lbu | bufInfo_1_lsu_isa_lhu | bufInfo_1_lsu_isa_lwu | bufInfo_1_lsu_isa_sb
     | bufInfo_1_lsu_isa_sh | bufInfo_1_lsu_isa_sw | bufInfo_1_lsu_isa_sd; // @[riscv_isa.scala 145:67]
  wire  _maskCondLsuIss_1_T_11 = bufInfo_1_lsu_isa_sc_d | bufInfo_1_lsu_isa_sc_w; // @[riscv_isa.scala 140:20]
  wire  _maskCondLsuIss_1_T_12 = bufInfo_1_lsu_isa_lr_d | bufInfo_1_lsu_isa_lr_w; // @[riscv_isa.scala 141:20]
  wire  _maskCondLsuIss_1_T_13 = _maskCondLsuIss_1_T_11 | _maskCondLsuIss_1_T_12; // @[riscv_isa.scala 146:23]
  wire  _maskCondLsuIss_1_T_33 = bufInfo_1_lsu_isa_amoswap_w | bufInfo_1_lsu_isa_amoadd_w | bufInfo_1_lsu_isa_amoxor_w
     | bufInfo_1_lsu_isa_amoand_w | bufInfo_1_lsu_isa_amoor_w | bufInfo_1_lsu_isa_amomin_w | bufInfo_1_lsu_isa_amomax_w
     | bufInfo_1_lsu_isa_amominu_w | bufInfo_1_lsu_isa_amomaxu_w | bufInfo_1_lsu_isa_amoswap_d |
    bufInfo_1_lsu_isa_amoadd_d | bufInfo_1_lsu_isa_amoxor_d | bufInfo_1_lsu_isa_amoand_d | bufInfo_1_lsu_isa_amoor_d |
    bufInfo_1_lsu_isa_amomin_d | bufInfo_1_lsu_isa_amomax_d | bufInfo_1_lsu_isa_amominu_d | bufInfo_1_lsu_isa_amomaxu_d
     | _maskCondLsuIss_1_T_11; // @[riscv_isa.scala 148:205]
  wire  _maskCondLsuIss_1_T_37 = bufInfo_1_lsu_isa_flw | bufInfo_1_lsu_isa_fsw | bufInfo_1_lsu_isa_fld |
    bufInfo_1_lsu_isa_fsd; // @[riscv_isa.scala 149:32]
  wire  _maskCondLsuIss_1_T_40 = bufInfo_1_lsu_isa_fence | bufInfo_1_lsu_isa_fence_i | bufInfo_1_lsu_isa_sfence_vma; // @[riscv_isa.scala 150:34]
  wire  _maskCondLsuIss_1_T_41 = _maskCondLsuIss_1_T_10 | _maskCondLsuIss_1_T_13 | _maskCondLsuIss_1_T_33 |
    _maskCondLsuIss_1_T_37 | _maskCondLsuIss_1_T_40; // @[riscv_isa.scala 151:51]
  wire  _maskCondLsuIss_1_T_42 = ~_maskCondLsuIss_1_T_41; // @[Issue.scala 881:7]
  wire  maskCondLsuIss_1 = _io_dptReq_0_ready_T_1 | _maskCondLsuIss_1_T_42; // @[Issue.scala 880:20]
  wire  matrixOut_9_0_0 = ageMatrixW_0_0 & ~maskCondLsuIss_0 | maskCondLsuIss_0; // @[Issue.scala 200:60]
  wire  matrixOut_9_0_1 = ageMatrixW_0_1 & ~maskCondLsuIss_1 | maskCondLsuIss_0; // @[Issue.scala 200:60]
  wire  matrixOut_9_1_0 = ageMatrixR_1_0 & ~maskCondLsuIss_0 | maskCondLsuIss_1; // @[Issue.scala 200:60]
  wire  matrixOut_9_1_1 = ageMatrixW_1_1 & ~maskCondLsuIss_1 | maskCondLsuIss_1; // @[Issue.scala 200:60]
  wire  _T_616 = ~matrixOut_9_0_0 & ~matrixOut_9_0_1; // @[Issue.scala 888:58]
  wire  _T_620 = ~matrixOut_9_1_0 & ~matrixOut_9_1_1; // @[Issue.scala 888:58]
  wire [1:0] _T_621 = _T_616 + _T_620; // @[Bitwise.scala 51:90]
  wire  _T_623 = _T_621 == 2'h1; // @[Issue.scala 888:92]
  wire  _T_624 = matrixOut_9_0_0 & matrixOut_9_0_1 & (matrixOut_9_1_0 & matrixOut_9_1_1) | _T_623; // @[Issue.scala 887:86]
  wire  lsuIssIdx = _T_616 ? 1'h0 : 1'h1; // @[Issue.scala 891:39]
  wire  _T_628 = lsuIssFifo_io_enq_ready & lsuIssFifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_630 = _T_628 & ~lsuIssIdx; // @[Issue.scala 900:34]
  wire  _T_684 = _T_628 & lsuIssIdx; // @[Issue.scala 900:34]
  wire  _GEN_206 = _T_318 & _T_53; // @[Issue.scala 642:15]
  wire  _GEN_209 = _T_361 & _T_53; // @[Issue.scala 642:15]
  wire  _GEN_212 = _T_429 & _T_53; // @[Issue.scala 707:17]
  wire  _GEN_215 = _T_454 & _T_53; // @[Issue.scala 707:17]
  wire  _GEN_218 = _T_504 & _T_53; // @[Issue.scala 773:13]
  wire  _GEN_221 = _T_524 & _T_53; // @[Issue.scala 773:13]
  wire  _GEN_224 = _T_569 & _T_53; // @[Issue.scala 839:13]
  wire  _GEN_227 = _T_587 & _T_53; // @[Issue.scala 839:13]
  wire  _GEN_230 = _T_630 & _T_53; // @[Issue.scala 902:13]
  wire  _GEN_233 = _T_684 & _T_53; // @[Issue.scala 902:13]
  Queue_2 aluIssFifo_0 ( // @[Issue.scala 605:11]
    .clock(aluIssFifo_0_clock),
    .reset(aluIssFifo_0_reset),
    .io_enq_ready(aluIssFifo_0_io_enq_ready),
    .io_enq_valid(aluIssFifo_0_io_enq_valid),
    .io_deq_ready(aluIssFifo_0_io_deq_ready),
    .io_deq_valid(aluIssFifo_0_io_deq_valid)
  );
  Queue_3 mulIssFifo_0 ( // @[Issue.scala 671:13]
    .clock(mulIssFifo_0_clock),
    .reset(mulIssFifo_0_reset),
    .io_enq_ready(mulIssFifo_0_io_enq_ready),
    .io_enq_valid(mulIssFifo_0_io_enq_valid),
    .io_deq_ready(mulIssFifo_0_io_deq_ready),
    .io_deq_valid(mulIssFifo_0_io_deq_valid)
  );
  Queue_4 bruIssFifo ( // @[Issue.scala 743:26]
    .clock(bruIssFifo_clock),
    .reset(bruIssFifo_reset),
    .io_enq_ready(bruIssFifo_io_enq_ready),
    .io_enq_valid(bruIssFifo_io_enq_valid),
    .io_deq_ready(bruIssFifo_io_deq_ready),
    .io_deq_valid(bruIssFifo_io_deq_valid)
  );
  Queue_5 csrIssFifo ( // @[Issue.scala 809:26]
    .clock(csrIssFifo_clock),
    .reset(csrIssFifo_reset),
    .io_enq_ready(csrIssFifo_io_enq_ready),
    .io_enq_valid(csrIssFifo_io_enq_valid),
    .io_deq_ready(csrIssFifo_io_deq_ready),
    .io_deq_valid(csrIssFifo_io_deq_valid)
  );
  Queue_6 lsuIssFifo ( // @[Issue.scala 872:26]
    .clock(lsuIssFifo_clock),
    .reset(lsuIssFifo_reset),
    .io_enq_ready(lsuIssFifo_io_enq_ready),
    .io_enq_valid(lsuIssFifo_io_enq_valid),
    .io_deq_ready(lsuIssFifo_io_deq_ready),
    .io_deq_valid(lsuIssFifo_io_deq_valid)
  );
  assign io_dptReq_0_ready = 1'h1; // @[Issue.scala 78:76]
  assign aluIssFifo_0_clock = clock;
  assign aluIssFifo_0_reset = io_flush | reset; // @[Issue.scala 648:39]
  assign aluIssFifo_0_io_enq_valid = ~_T_300; // @[Issue.scala 634:37]
  assign aluIssFifo_0_io_deq_ready = io_alu_iss_exe_0_ready; // @[Issue.scala 647:28]
  assign mulIssFifo_0_clock = clock;
  assign mulIssFifo_0_reset = io_flush | reset; // @[Issue.scala 713:41]
  assign mulIssFifo_0_io_enq_valid = ~_T_411; // @[Issue.scala 699:39]
  assign mulIssFifo_0_io_deq_ready = io_mul_iss_exe_0_ready; // @[Issue.scala 712:30]
  assign bruIssFifo_clock = clock;
  assign bruIssFifo_reset = io_flush | reset; // @[Issue.scala 780:32]
  assign bruIssFifo_io_enq_valid = _T_490 & postIsOpReady_0_0 & postIsOpReady_0_1 | _T_494 & postIsOpReady_1_0 &
    postIsOpReady_1_1; // @[Issue.scala 765:149]
  assign bruIssFifo_io_deq_ready = io_bru_iss_exe_ready; // @[Issue.scala 779:21]
  assign csrIssFifo_clock = clock;
  assign csrIssFifo_reset = io_flush | reset; // @[Issue.scala 846:32]
  assign csrIssFifo_io_enq_valid = _T_555 & postIsOpReady_0_0 & postIsOpReady_0_1 | _T_559 & postIsOpReady_1_0 &
    postIsOpReady_1_1; // @[Issue.scala 831:149]
  assign csrIssFifo_io_deq_ready = io_csr_iss_exe_ready; // @[Issue.scala 845:21]
  assign lsuIssFifo_clock = clock;
  assign lsuIssFifo_reset = io_flush | reset; // @[Issue.scala 909:32]
  assign lsuIssFifo_io_enq_valid = _T_616 & postIsOpReady_0_0 & postIsOpReady_0_1 | _T_620 & postIsOpReady_1_0 &
    postIsOpReady_1_1; // @[Issue.scala 894:149]
  assign lsuIssFifo_io_deq_ready = io_lsu_iss_exe_ready; // @[Issue.scala 908:21]
  always @(posedge clock) begin
    if (reset) begin // @[Issue.scala 61:29]
      bufValid_0 <= 1'h0; // @[Issue.scala 61:29]
    end else if (_T_628 & ~lsuIssIdx) begin // @[Issue.scala 900:56]
      bufValid_0 <= 1'h0; // @[Issue.scala 901:19]
    end else if (_T_567 & ~csrIssIdx) begin // @[Issue.scala 837:56]
      bufValid_0 <= 1'h0; // @[Issue.scala 838:19]
    end else if (_T_502 & ~bruIssIdx) begin // @[Issue.scala 771:56]
      bufValid_0 <= 1'h0; // @[Issue.scala 772:19]
    end else begin
      bufValid_0 <= _GEN_1806;
    end
    if (reset) begin // @[Issue.scala 61:29]
      bufValid_1 <= 1'h0; // @[Issue.scala 61:29]
    end else if (_T_628 & lsuIssIdx) begin // @[Issue.scala 900:56]
      bufValid_1 <= 1'h0; // @[Issue.scala 901:19]
    end else if (_T_567 & csrIssIdx) begin // @[Issue.scala 837:56]
      bufValid_1 <= 1'h0; // @[Issue.scala 838:19]
    end else if (_T_502 & bruIssIdx) begin // @[Issue.scala 771:56]
      bufValid_1 <= 1'h0; // @[Issue.scala 772:19]
    end else begin
      bufValid_1 <= _GEN_1807;
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_lui <= io_dptReq_0_bits_alu_isa_lui; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_auipc <= io_dptReq_0_bits_alu_isa_auipc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_addi <= io_dptReq_0_bits_alu_isa_addi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_addiw <= io_dptReq_0_bits_alu_isa_addiw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_slti <= io_dptReq_0_bits_alu_isa_slti; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_sltiu <= io_dptReq_0_bits_alu_isa_sltiu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_xori <= io_dptReq_0_bits_alu_isa_xori; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_ori <= io_dptReq_0_bits_alu_isa_ori; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_andi <= io_dptReq_0_bits_alu_isa_andi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_slli <= io_dptReq_0_bits_alu_isa_slli; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_slliw <= io_dptReq_0_bits_alu_isa_slliw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_srli <= io_dptReq_0_bits_alu_isa_srli; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_srliw <= io_dptReq_0_bits_alu_isa_srliw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_srai <= io_dptReq_0_bits_alu_isa_srai; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_sraiw <= io_dptReq_0_bits_alu_isa_sraiw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_add <= io_dptReq_0_bits_alu_isa_add; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_addw <= io_dptReq_0_bits_alu_isa_addw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_sub <= io_dptReq_0_bits_alu_isa_sub; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_subw <= io_dptReq_0_bits_alu_isa_subw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_sll <= io_dptReq_0_bits_alu_isa_sll; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_sllw <= io_dptReq_0_bits_alu_isa_sllw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_slt <= io_dptReq_0_bits_alu_isa_slt; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_sltu <= io_dptReq_0_bits_alu_isa_sltu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_xor <= io_dptReq_0_bits_alu_isa_xor; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_srl <= io_dptReq_0_bits_alu_isa_srl; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_srlw <= io_dptReq_0_bits_alu_isa_srlw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_sra <= io_dptReq_0_bits_alu_isa_sra; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_sraw <= io_dptReq_0_bits_alu_isa_sraw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_or <= io_dptReq_0_bits_alu_isa_or; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_and <= io_dptReq_0_bits_alu_isa_and; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_alu_isa_wfi <= io_dptReq_0_bits_alu_isa_wfi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_bru_isa_jal <= io_dptReq_0_bits_bru_isa_jal; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_bru_isa_jalr <= io_dptReq_0_bits_bru_isa_jalr; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_bru_isa_beq <= io_dptReq_0_bits_bru_isa_beq; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_bru_isa_bne <= io_dptReq_0_bits_bru_isa_bne; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_bru_isa_blt <= io_dptReq_0_bits_bru_isa_blt; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_bru_isa_bge <= io_dptReq_0_bits_bru_isa_bge; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_bru_isa_bltu <= io_dptReq_0_bits_bru_isa_bltu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_bru_isa_bgeu <= io_dptReq_0_bits_bru_isa_bgeu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_lb <= io_dptReq_0_bits_lsu_isa_lb; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_lh <= io_dptReq_0_bits_lsu_isa_lh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_lw <= io_dptReq_0_bits_lsu_isa_lw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_ld <= io_dptReq_0_bits_lsu_isa_ld; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_lbu <= io_dptReq_0_bits_lsu_isa_lbu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_lhu <= io_dptReq_0_bits_lsu_isa_lhu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_lwu <= io_dptReq_0_bits_lsu_isa_lwu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_sb <= io_dptReq_0_bits_lsu_isa_sb; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_sh <= io_dptReq_0_bits_lsu_isa_sh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_sw <= io_dptReq_0_bits_lsu_isa_sw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_sd <= io_dptReq_0_bits_lsu_isa_sd; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_fence <= io_dptReq_0_bits_lsu_isa_fence; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_fence_i <= io_dptReq_0_bits_lsu_isa_fence_i; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_sfence_vma <= io_dptReq_0_bits_lsu_isa_sfence_vma; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_lr_w <= io_dptReq_0_bits_lsu_isa_lr_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_sc_w <= io_dptReq_0_bits_lsu_isa_sc_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoswap_w <= io_dptReq_0_bits_lsu_isa_amoswap_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoadd_w <= io_dptReq_0_bits_lsu_isa_amoadd_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoxor_w <= io_dptReq_0_bits_lsu_isa_amoxor_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoand_w <= io_dptReq_0_bits_lsu_isa_amoand_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoor_w <= io_dptReq_0_bits_lsu_isa_amoor_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amomin_w <= io_dptReq_0_bits_lsu_isa_amomin_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amomax_w <= io_dptReq_0_bits_lsu_isa_amomax_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amominu_w <= io_dptReq_0_bits_lsu_isa_amominu_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amomaxu_w <= io_dptReq_0_bits_lsu_isa_amomaxu_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_lr_d <= io_dptReq_0_bits_lsu_isa_lr_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_sc_d <= io_dptReq_0_bits_lsu_isa_sc_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoswap_d <= io_dptReq_0_bits_lsu_isa_amoswap_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoadd_d <= io_dptReq_0_bits_lsu_isa_amoadd_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoxor_d <= io_dptReq_0_bits_lsu_isa_amoxor_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoand_d <= io_dptReq_0_bits_lsu_isa_amoand_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amoor_d <= io_dptReq_0_bits_lsu_isa_amoor_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amomin_d <= io_dptReq_0_bits_lsu_isa_amomin_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amomax_d <= io_dptReq_0_bits_lsu_isa_amomax_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amominu_d <= io_dptReq_0_bits_lsu_isa_amominu_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_amomaxu_d <= io_dptReq_0_bits_lsu_isa_amomaxu_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_flw <= io_dptReq_0_bits_lsu_isa_flw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_fsw <= io_dptReq_0_bits_lsu_isa_fsw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_fld <= io_dptReq_0_bits_lsu_isa_fld; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_lsu_isa_fsd <= io_dptReq_0_bits_lsu_isa_fsd; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_csr_isa_rw <= io_dptReq_0_bits_csr_isa_rw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_csr_isa_rs <= io_dptReq_0_bits_csr_isa_rs; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_csr_isa_rc <= io_dptReq_0_bits_csr_isa_rc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_csr_isa_rwi <= io_dptReq_0_bits_csr_isa_rwi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_csr_isa_rsi <= io_dptReq_0_bits_csr_isa_rsi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_csr_isa_rci <= io_dptReq_0_bits_csr_isa_rci; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_mul <= io_dptReq_0_bits_mul_isa_mul; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_mulh <= io_dptReq_0_bits_mul_isa_mulh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_mulhsu <= io_dptReq_0_bits_mul_isa_mulhsu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_mulhu <= io_dptReq_0_bits_mul_isa_mulhu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_div <= io_dptReq_0_bits_mul_isa_div; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_divu <= io_dptReq_0_bits_mul_isa_divu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_rem <= io_dptReq_0_bits_mul_isa_rem; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_remu <= io_dptReq_0_bits_mul_isa_remu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_mulw <= io_dptReq_0_bits_mul_isa_mulw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_divw <= io_dptReq_0_bits_mul_isa_divw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_divuw <= io_dptReq_0_bits_mul_isa_divuw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_remw <= io_dptReq_0_bits_mul_isa_remw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_mul_isa_remuw <= io_dptReq_0_bits_mul_isa_remuw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_phy_rs1 <= io_dptReq_0_bits_phy_rs1; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_phy_rs2 <= io_dptReq_0_bits_phy_rs2; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (~entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_0_phy_rs3 <= io_dptReq_0_bits_phy_rs3; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_lui <= io_dptReq_0_bits_alu_isa_lui; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_auipc <= io_dptReq_0_bits_alu_isa_auipc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_addi <= io_dptReq_0_bits_alu_isa_addi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_addiw <= io_dptReq_0_bits_alu_isa_addiw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_slti <= io_dptReq_0_bits_alu_isa_slti; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_sltiu <= io_dptReq_0_bits_alu_isa_sltiu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_xori <= io_dptReq_0_bits_alu_isa_xori; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_ori <= io_dptReq_0_bits_alu_isa_ori; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_andi <= io_dptReq_0_bits_alu_isa_andi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_slli <= io_dptReq_0_bits_alu_isa_slli; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_slliw <= io_dptReq_0_bits_alu_isa_slliw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_srli <= io_dptReq_0_bits_alu_isa_srli; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_srliw <= io_dptReq_0_bits_alu_isa_srliw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_srai <= io_dptReq_0_bits_alu_isa_srai; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_sraiw <= io_dptReq_0_bits_alu_isa_sraiw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_add <= io_dptReq_0_bits_alu_isa_add; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_addw <= io_dptReq_0_bits_alu_isa_addw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_sub <= io_dptReq_0_bits_alu_isa_sub; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_subw <= io_dptReq_0_bits_alu_isa_subw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_sll <= io_dptReq_0_bits_alu_isa_sll; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_sllw <= io_dptReq_0_bits_alu_isa_sllw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_slt <= io_dptReq_0_bits_alu_isa_slt; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_sltu <= io_dptReq_0_bits_alu_isa_sltu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_xor <= io_dptReq_0_bits_alu_isa_xor; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_srl <= io_dptReq_0_bits_alu_isa_srl; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_srlw <= io_dptReq_0_bits_alu_isa_srlw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_sra <= io_dptReq_0_bits_alu_isa_sra; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_sraw <= io_dptReq_0_bits_alu_isa_sraw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_or <= io_dptReq_0_bits_alu_isa_or; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_and <= io_dptReq_0_bits_alu_isa_and; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_alu_isa_wfi <= io_dptReq_0_bits_alu_isa_wfi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_bru_isa_jal <= io_dptReq_0_bits_bru_isa_jal; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_bru_isa_jalr <= io_dptReq_0_bits_bru_isa_jalr; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_bru_isa_beq <= io_dptReq_0_bits_bru_isa_beq; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_bru_isa_bne <= io_dptReq_0_bits_bru_isa_bne; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_bru_isa_blt <= io_dptReq_0_bits_bru_isa_blt; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_bru_isa_bge <= io_dptReq_0_bits_bru_isa_bge; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_bru_isa_bltu <= io_dptReq_0_bits_bru_isa_bltu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_bru_isa_bgeu <= io_dptReq_0_bits_bru_isa_bgeu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_lb <= io_dptReq_0_bits_lsu_isa_lb; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_lh <= io_dptReq_0_bits_lsu_isa_lh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_lw <= io_dptReq_0_bits_lsu_isa_lw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_ld <= io_dptReq_0_bits_lsu_isa_ld; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_lbu <= io_dptReq_0_bits_lsu_isa_lbu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_lhu <= io_dptReq_0_bits_lsu_isa_lhu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_lwu <= io_dptReq_0_bits_lsu_isa_lwu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_sb <= io_dptReq_0_bits_lsu_isa_sb; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_sh <= io_dptReq_0_bits_lsu_isa_sh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_sw <= io_dptReq_0_bits_lsu_isa_sw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_sd <= io_dptReq_0_bits_lsu_isa_sd; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_fence <= io_dptReq_0_bits_lsu_isa_fence; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_fence_i <= io_dptReq_0_bits_lsu_isa_fence_i; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_sfence_vma <= io_dptReq_0_bits_lsu_isa_sfence_vma; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_lr_w <= io_dptReq_0_bits_lsu_isa_lr_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_sc_w <= io_dptReq_0_bits_lsu_isa_sc_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoswap_w <= io_dptReq_0_bits_lsu_isa_amoswap_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoadd_w <= io_dptReq_0_bits_lsu_isa_amoadd_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoxor_w <= io_dptReq_0_bits_lsu_isa_amoxor_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoand_w <= io_dptReq_0_bits_lsu_isa_amoand_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoor_w <= io_dptReq_0_bits_lsu_isa_amoor_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amomin_w <= io_dptReq_0_bits_lsu_isa_amomin_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amomax_w <= io_dptReq_0_bits_lsu_isa_amomax_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amominu_w <= io_dptReq_0_bits_lsu_isa_amominu_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amomaxu_w <= io_dptReq_0_bits_lsu_isa_amomaxu_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_lr_d <= io_dptReq_0_bits_lsu_isa_lr_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_sc_d <= io_dptReq_0_bits_lsu_isa_sc_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoswap_d <= io_dptReq_0_bits_lsu_isa_amoswap_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoadd_d <= io_dptReq_0_bits_lsu_isa_amoadd_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoxor_d <= io_dptReq_0_bits_lsu_isa_amoxor_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoand_d <= io_dptReq_0_bits_lsu_isa_amoand_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amoor_d <= io_dptReq_0_bits_lsu_isa_amoor_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amomin_d <= io_dptReq_0_bits_lsu_isa_amomin_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amomax_d <= io_dptReq_0_bits_lsu_isa_amomax_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amominu_d <= io_dptReq_0_bits_lsu_isa_amominu_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_amomaxu_d <= io_dptReq_0_bits_lsu_isa_amomaxu_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_flw <= io_dptReq_0_bits_lsu_isa_flw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_fsw <= io_dptReq_0_bits_lsu_isa_fsw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_fld <= io_dptReq_0_bits_lsu_isa_fld; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_lsu_isa_fsd <= io_dptReq_0_bits_lsu_isa_fsd; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_csr_isa_rw <= io_dptReq_0_bits_csr_isa_rw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_csr_isa_rs <= io_dptReq_0_bits_csr_isa_rs; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_csr_isa_rc <= io_dptReq_0_bits_csr_isa_rc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_csr_isa_rwi <= io_dptReq_0_bits_csr_isa_rwi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_csr_isa_rsi <= io_dptReq_0_bits_csr_isa_rsi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_csr_isa_rci <= io_dptReq_0_bits_csr_isa_rci; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_mul <= io_dptReq_0_bits_mul_isa_mul; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_mulh <= io_dptReq_0_bits_mul_isa_mulh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_mulhsu <= io_dptReq_0_bits_mul_isa_mulhsu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_mulhu <= io_dptReq_0_bits_mul_isa_mulhu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_div <= io_dptReq_0_bits_mul_isa_div; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_divu <= io_dptReq_0_bits_mul_isa_divu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_rem <= io_dptReq_0_bits_mul_isa_rem; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_remu <= io_dptReq_0_bits_mul_isa_remu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_mulw <= io_dptReq_0_bits_mul_isa_mulw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_divw <= io_dptReq_0_bits_mul_isa_divw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_divuw <= io_dptReq_0_bits_mul_isa_divuw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_remw <= io_dptReq_0_bits_mul_isa_remw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_mul_isa_remuw <= io_dptReq_0_bits_mul_isa_remuw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_phy_rs1 <= io_dptReq_0_bits_phy_rs1; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_phy_rs2 <= io_dptReq_0_bits_phy_rs2; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(io_flush)) begin // @[Issue.scala 86:22]
      if (_T) begin // @[Issue.scala 88:38]
        if (entrySel_0) begin // @[Issue.scala 90:28]
          bufInfo_1_phy_rs3 <= io_dptReq_0_bits_phy_rs3; // @[Issue.scala 90:28]
        end
      end
    end
    if (io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      isOpReady_0_0 <= _GEN_1764;
    end else if (_T) begin // @[Issue.scala 120:31]
      if (io_dptReq_0_bits_phy_rs1 == 6'h21) begin // @[Issue.scala 121:58]
        isOpReady_0_0 <= _GEN_1200;
      end else if (~entrySel_0) begin // @[Issue.scala 125:36]
        isOpReady_0_0 <= 1'h0; // @[Issue.scala 125:36]
      end
    end
    if (io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      isOpReady_0_1 <= _GEN_1766;
    end else if (_T) begin // @[Issue.scala 120:31]
      if (io_dptReq_0_bits_phy_rs2 == 6'h21) begin // @[Issue.scala 127:58]
        isOpReady_0_1 <= _GEN_1210;
      end else if (~entrySel_0) begin // @[Issue.scala 131:36]
        isOpReady_0_1 <= 1'h0; // @[Issue.scala 131:36]
      end
    end
    if (io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      isOpReady_1_0 <= _GEN_1768;
    end else if (_T) begin // @[Issue.scala 120:31]
      if (io_dptReq_0_bits_phy_rs1 == 6'h21) begin // @[Issue.scala 121:58]
        isOpReady_1_0 <= _GEN_1201;
      end else if (entrySel_0) begin // @[Issue.scala 125:36]
        isOpReady_1_0 <= 1'h0; // @[Issue.scala 125:36]
      end
    end
    if (io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      isOpReady_1_1 <= _GEN_1770;
    end else if (_T) begin // @[Issue.scala 120:31]
      if (io_dptReq_0_bits_phy_rs2 == 6'h21) begin // @[Issue.scala 127:58]
        isOpReady_1_1 <= _GEN_1211;
      end else if (entrySel_0) begin // @[Issue.scala 131:36]
        isOpReady_1_1 <= 1'h0; // @[Issue.scala 131:36]
      end
    end
    if (_T) begin // @[Issue.scala 170:31]
      if (~entrySel_0) begin // @[Issue.scala 172:44]
        ageMatrixW_0_0 <= 1'h0; // @[Issue.scala 172:44]
      end else begin
        ageMatrixW_0_0 <= _GEN_1242;
      end
    end
    if (_T) begin // @[Issue.scala 170:31]
      if (entrySel_0) begin // @[Issue.scala 172:44]
        ageMatrixW_0_1 <= 1'h0; // @[Issue.scala 172:44]
      end else begin
        ageMatrixW_0_1 <= _GEN_1244;
      end
    end
    if (_T) begin // @[Issue.scala 170:31]
      if (entrySel_0) begin // @[Issue.scala 172:44]
        ageMatrixW_1_1 <= 1'h0; // @[Issue.scala 172:44]
      end else begin
        ageMatrixW_1_1 <= _GEN_1245;
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_51) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:276 assert(\n"); // @[Issue.scala 276:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_51 & ~reset) begin
          $fatal; // @[Issue.scala 276:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_99) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:281 assert(\n"); // @[Issue.scala 281:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & _T_53) begin
          $fatal; // @[Issue.scala 281:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_147) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:412 assert(\n"); // @[Issue.scala 412:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_147 & _T_53) begin
          $fatal; // @[Issue.scala 412:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_195) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:417 assert(\n"); // @[Issue.scala 417:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & _T_53) begin
          $fatal; // @[Issue.scala 417:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_243) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:422 assert(\n"); // @[Issue.scala 422:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_243 & _T_53) begin
          $fatal; // @[Issue.scala 422:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_312) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:627 assert(\n"); // @[Issue.scala 627:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_312 & _T_53) begin
          $fatal; // @[Issue.scala 627:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_318 & _T_53 & _maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:642 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 642:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_0_T_33 & (_T_318 & _T_53)) begin
          $fatal; // @[Issue.scala 642:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_206 & _entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:643 assert( bufValid(i) )\n"); // @[Issue.scala 643:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_0 & (_T_318 & _T_53)) begin
          $fatal; // @[Issue.scala 643:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_206 & _maskCondAluIss_0_0_T_31) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:644 assert( bufInfo(i).alu_isa.is_alu )\n"); // @[Issue.scala 644:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_0_T_30 & (_T_318 & _T_53)) begin
          $fatal; // @[Issue.scala 644:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_361 & _T_53 & _maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:642 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 642:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_1_T_33 & (_T_361 & _T_53)) begin
          $fatal; // @[Issue.scala 642:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_209 & _io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:643 assert( bufValid(i) )\n"); // @[Issue.scala 643:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_1 & (_T_361 & _T_53)) begin
          $fatal; // @[Issue.scala 643:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_209 & _maskCondAluIss_0_1_T_31) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:644 assert( bufInfo(i).alu_isa.is_alu )\n"); // @[Issue.scala 644:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_1_T_30 & (_T_361 & _T_53)) begin
          $fatal; // @[Issue.scala 644:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_423) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:692 assert(\n"); // @[Issue.scala 692:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_423 & _T_53) begin
          $fatal; // @[Issue.scala 692:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_429 & _T_53 & _maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:707 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 707:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_0_T_33 & (_T_429 & _T_53)) begin
          $fatal; // @[Issue.scala 707:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_212 & _entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:708 assert( bufValid(i) )\n"); // @[Issue.scala 708:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_0 & (_T_429 & _T_53)) begin
          $fatal; // @[Issue.scala 708:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_212 & _maskCondMulIss_0_0_T_13) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:709 assert( bufInfo(i).mul_isa.is_mulDiv )\n"); // @[Issue.scala 709:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondMulIss_0_0_T_12 & (_T_429 & _T_53)) begin
          $fatal; // @[Issue.scala 709:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_454 & _T_53 & _maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:707 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 707:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_1_T_33 & (_T_454 & _T_53)) begin
          $fatal; // @[Issue.scala 707:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_215 & _io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:708 assert( bufValid(i) )\n"); // @[Issue.scala 708:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_1 & (_T_454 & _T_53)) begin
          $fatal; // @[Issue.scala 708:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_215 & _maskCondMulIss_0_1_T_13) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:709 assert( bufInfo(i).mul_isa.is_mulDiv )\n"); // @[Issue.scala 709:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondMulIss_0_1_T_12 & (_T_454 & _T_53)) begin
          $fatal; // @[Issue.scala 709:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_498) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:757 assert(\n"); // @[Issue.scala 757:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_498 & _T_53) begin
          $fatal; // @[Issue.scala 757:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_504 & _T_53 & _maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:773 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 773:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_0_T_33 & (_T_504 & _T_53)) begin
          $fatal; // @[Issue.scala 773:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_218 & _entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:774 assert( bufValid(i) )\n"); // @[Issue.scala 774:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_0 & (_T_504 & _T_53)) begin
          $fatal; // @[Issue.scala 774:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_218 & _maskCondBruIss_0_T_8) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:775 assert( bufInfo(i).bru_isa.is_bru )\n"); // @[Issue.scala 775:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondBruIss_0_T_7 & (_T_504 & _T_53)) begin
          $fatal; // @[Issue.scala 775:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_524 & _T_53 & _maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:773 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 773:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_1_T_33 & (_T_524 & _T_53)) begin
          $fatal; // @[Issue.scala 773:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_221 & _io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:774 assert( bufValid(i) )\n"); // @[Issue.scala 774:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_1 & (_T_524 & _T_53)) begin
          $fatal; // @[Issue.scala 774:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_221 & _maskCondBruIss_1_T_8) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:775 assert( bufInfo(i).bru_isa.is_bru )\n"); // @[Issue.scala 775:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondBruIss_1_T_7 & (_T_524 & _T_53)) begin
          $fatal; // @[Issue.scala 775:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_563) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:823 assert(\n"); // @[Issue.scala 823:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_563 & _T_53) begin
          $fatal; // @[Issue.scala 823:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_569 & _T_53 & _maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:839 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 839:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_0_T_33 & (_T_569 & _T_53)) begin
          $fatal; // @[Issue.scala 839:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_224 & _entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:840 assert( bufValid(i) )\n"); // @[Issue.scala 840:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_0 & (_T_569 & _T_53)) begin
          $fatal; // @[Issue.scala 840:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_224 & _maskCondCsrIss_0_T_6) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:841 assert( bufInfo(i).csr_isa.is_csr )\n"); // @[Issue.scala 841:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondCsrIss_0_T_5 & (_T_569 & _T_53)) begin
          $fatal; // @[Issue.scala 841:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_587 & _T_53 & _maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:839 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 839:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_1_T_33 & (_T_587 & _T_53)) begin
          $fatal; // @[Issue.scala 839:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_227 & _io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:840 assert( bufValid(i) )\n"); // @[Issue.scala 840:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_1 & (_T_587 & _T_53)) begin
          $fatal; // @[Issue.scala 840:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_227 & _maskCondCsrIss_1_T_6) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:841 assert( bufInfo(i).csr_isa.is_csr )\n"); // @[Issue.scala 841:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondCsrIss_1_T_5 & (_T_587 & _T_53)) begin
          $fatal; // @[Issue.scala 841:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_53 & ~_T_624) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:886 assert(\n"); // @[Issue.scala 886:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & _T_53) begin
          $fatal; // @[Issue.scala 886:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_630 & _T_53 & _maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:902 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 902:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_0_T_33 & (_T_630 & _T_53)) begin
          $fatal; // @[Issue.scala 902:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_230 & _entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:903 assert( bufValid(i) )\n"); // @[Issue.scala 903:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_0 & (_T_630 & _T_53)) begin
          $fatal; // @[Issue.scala 903:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_230 & _maskCondLsuIss_0_T_42) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:904 assert( bufInfo(i).lsu_isa.is_lsu )\n"); // @[Issue.scala 904:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondLsuIss_0_T_41 & (_T_630 & _T_53)) begin
          $fatal; // @[Issue.scala 904:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_684 & _T_53 & _maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:902 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 902:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondAluIss_0_1_T_33 & (_T_684 & _T_53)) begin
          $fatal; // @[Issue.scala 902:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_233 & _io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:903 assert( bufValid(i) )\n"); // @[Issue.scala 903:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~bufValid_1 & (_T_684 & _T_53)) begin
          $fatal; // @[Issue.scala 903:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_233 & _maskCondLsuIss_1_T_42) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:904 assert( bufInfo(i).lsu_isa.is_lsu )\n"); // @[Issue.scala 904:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_maskCondLsuIss_1_T_41 & (_T_684 & _T_53)) begin
          $fatal; // @[Issue.scala 904:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  bufValid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  bufValid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  bufInfo_0_alu_isa_lui = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  bufInfo_0_alu_isa_auipc = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  bufInfo_0_alu_isa_addi = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  bufInfo_0_alu_isa_addiw = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  bufInfo_0_alu_isa_slti = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  bufInfo_0_alu_isa_sltiu = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  bufInfo_0_alu_isa_xori = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  bufInfo_0_alu_isa_ori = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  bufInfo_0_alu_isa_andi = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  bufInfo_0_alu_isa_slli = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  bufInfo_0_alu_isa_slliw = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  bufInfo_0_alu_isa_srli = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  bufInfo_0_alu_isa_srliw = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  bufInfo_0_alu_isa_srai = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  bufInfo_0_alu_isa_sraiw = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  bufInfo_0_alu_isa_add = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  bufInfo_0_alu_isa_addw = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  bufInfo_0_alu_isa_sub = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  bufInfo_0_alu_isa_subw = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  bufInfo_0_alu_isa_sll = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  bufInfo_0_alu_isa_sllw = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  bufInfo_0_alu_isa_slt = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  bufInfo_0_alu_isa_sltu = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  bufInfo_0_alu_isa_xor = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  bufInfo_0_alu_isa_srl = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  bufInfo_0_alu_isa_srlw = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  bufInfo_0_alu_isa_sra = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  bufInfo_0_alu_isa_sraw = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  bufInfo_0_alu_isa_or = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  bufInfo_0_alu_isa_and = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  bufInfo_0_alu_isa_wfi = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  bufInfo_0_bru_isa_jal = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  bufInfo_0_bru_isa_jalr = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  bufInfo_0_bru_isa_beq = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  bufInfo_0_bru_isa_bne = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  bufInfo_0_bru_isa_blt = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  bufInfo_0_bru_isa_bge = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  bufInfo_0_bru_isa_bltu = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  bufInfo_0_bru_isa_bgeu = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_lb = _RAND_41[0:0];
  _RAND_42 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_lh = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_lw = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_ld = _RAND_44[0:0];
  _RAND_45 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_lbu = _RAND_45[0:0];
  _RAND_46 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_lhu = _RAND_46[0:0];
  _RAND_47 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_lwu = _RAND_47[0:0];
  _RAND_48 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_sb = _RAND_48[0:0];
  _RAND_49 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_sh = _RAND_49[0:0];
  _RAND_50 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_sw = _RAND_50[0:0];
  _RAND_51 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_sd = _RAND_51[0:0];
  _RAND_52 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_fence = _RAND_52[0:0];
  _RAND_53 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_fence_i = _RAND_53[0:0];
  _RAND_54 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_sfence_vma = _RAND_54[0:0];
  _RAND_55 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_lr_w = _RAND_55[0:0];
  _RAND_56 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_sc_w = _RAND_56[0:0];
  _RAND_57 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoswap_w = _RAND_57[0:0];
  _RAND_58 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoadd_w = _RAND_58[0:0];
  _RAND_59 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoxor_w = _RAND_59[0:0];
  _RAND_60 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoand_w = _RAND_60[0:0];
  _RAND_61 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoor_w = _RAND_61[0:0];
  _RAND_62 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amomin_w = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amomax_w = _RAND_63[0:0];
  _RAND_64 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amominu_w = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amomaxu_w = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_lr_d = _RAND_66[0:0];
  _RAND_67 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_sc_d = _RAND_67[0:0];
  _RAND_68 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoswap_d = _RAND_68[0:0];
  _RAND_69 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoadd_d = _RAND_69[0:0];
  _RAND_70 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoxor_d = _RAND_70[0:0];
  _RAND_71 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoand_d = _RAND_71[0:0];
  _RAND_72 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amoor_d = _RAND_72[0:0];
  _RAND_73 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amomin_d = _RAND_73[0:0];
  _RAND_74 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amomax_d = _RAND_74[0:0];
  _RAND_75 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amominu_d = _RAND_75[0:0];
  _RAND_76 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_amomaxu_d = _RAND_76[0:0];
  _RAND_77 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_flw = _RAND_77[0:0];
  _RAND_78 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_fsw = _RAND_78[0:0];
  _RAND_79 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_fld = _RAND_79[0:0];
  _RAND_80 = {1{`RANDOM}};
  bufInfo_0_lsu_isa_fsd = _RAND_80[0:0];
  _RAND_81 = {1{`RANDOM}};
  bufInfo_0_csr_isa_rw = _RAND_81[0:0];
  _RAND_82 = {1{`RANDOM}};
  bufInfo_0_csr_isa_rs = _RAND_82[0:0];
  _RAND_83 = {1{`RANDOM}};
  bufInfo_0_csr_isa_rc = _RAND_83[0:0];
  _RAND_84 = {1{`RANDOM}};
  bufInfo_0_csr_isa_rwi = _RAND_84[0:0];
  _RAND_85 = {1{`RANDOM}};
  bufInfo_0_csr_isa_rsi = _RAND_85[0:0];
  _RAND_86 = {1{`RANDOM}};
  bufInfo_0_csr_isa_rci = _RAND_86[0:0];
  _RAND_87 = {1{`RANDOM}};
  bufInfo_0_mul_isa_mul = _RAND_87[0:0];
  _RAND_88 = {1{`RANDOM}};
  bufInfo_0_mul_isa_mulh = _RAND_88[0:0];
  _RAND_89 = {1{`RANDOM}};
  bufInfo_0_mul_isa_mulhsu = _RAND_89[0:0];
  _RAND_90 = {1{`RANDOM}};
  bufInfo_0_mul_isa_mulhu = _RAND_90[0:0];
  _RAND_91 = {1{`RANDOM}};
  bufInfo_0_mul_isa_div = _RAND_91[0:0];
  _RAND_92 = {1{`RANDOM}};
  bufInfo_0_mul_isa_divu = _RAND_92[0:0];
  _RAND_93 = {1{`RANDOM}};
  bufInfo_0_mul_isa_rem = _RAND_93[0:0];
  _RAND_94 = {1{`RANDOM}};
  bufInfo_0_mul_isa_remu = _RAND_94[0:0];
  _RAND_95 = {1{`RANDOM}};
  bufInfo_0_mul_isa_mulw = _RAND_95[0:0];
  _RAND_96 = {1{`RANDOM}};
  bufInfo_0_mul_isa_divw = _RAND_96[0:0];
  _RAND_97 = {1{`RANDOM}};
  bufInfo_0_mul_isa_divuw = _RAND_97[0:0];
  _RAND_98 = {1{`RANDOM}};
  bufInfo_0_mul_isa_remw = _RAND_98[0:0];
  _RAND_99 = {1{`RANDOM}};
  bufInfo_0_mul_isa_remuw = _RAND_99[0:0];
  _RAND_100 = {1{`RANDOM}};
  bufInfo_0_phy_rs1 = _RAND_100[5:0];
  _RAND_101 = {1{`RANDOM}};
  bufInfo_0_phy_rs2 = _RAND_101[5:0];
  _RAND_102 = {1{`RANDOM}};
  bufInfo_0_phy_rs3 = _RAND_102[5:0];
  _RAND_103 = {1{`RANDOM}};
  bufInfo_1_alu_isa_lui = _RAND_103[0:0];
  _RAND_104 = {1{`RANDOM}};
  bufInfo_1_alu_isa_auipc = _RAND_104[0:0];
  _RAND_105 = {1{`RANDOM}};
  bufInfo_1_alu_isa_addi = _RAND_105[0:0];
  _RAND_106 = {1{`RANDOM}};
  bufInfo_1_alu_isa_addiw = _RAND_106[0:0];
  _RAND_107 = {1{`RANDOM}};
  bufInfo_1_alu_isa_slti = _RAND_107[0:0];
  _RAND_108 = {1{`RANDOM}};
  bufInfo_1_alu_isa_sltiu = _RAND_108[0:0];
  _RAND_109 = {1{`RANDOM}};
  bufInfo_1_alu_isa_xori = _RAND_109[0:0];
  _RAND_110 = {1{`RANDOM}};
  bufInfo_1_alu_isa_ori = _RAND_110[0:0];
  _RAND_111 = {1{`RANDOM}};
  bufInfo_1_alu_isa_andi = _RAND_111[0:0];
  _RAND_112 = {1{`RANDOM}};
  bufInfo_1_alu_isa_slli = _RAND_112[0:0];
  _RAND_113 = {1{`RANDOM}};
  bufInfo_1_alu_isa_slliw = _RAND_113[0:0];
  _RAND_114 = {1{`RANDOM}};
  bufInfo_1_alu_isa_srli = _RAND_114[0:0];
  _RAND_115 = {1{`RANDOM}};
  bufInfo_1_alu_isa_srliw = _RAND_115[0:0];
  _RAND_116 = {1{`RANDOM}};
  bufInfo_1_alu_isa_srai = _RAND_116[0:0];
  _RAND_117 = {1{`RANDOM}};
  bufInfo_1_alu_isa_sraiw = _RAND_117[0:0];
  _RAND_118 = {1{`RANDOM}};
  bufInfo_1_alu_isa_add = _RAND_118[0:0];
  _RAND_119 = {1{`RANDOM}};
  bufInfo_1_alu_isa_addw = _RAND_119[0:0];
  _RAND_120 = {1{`RANDOM}};
  bufInfo_1_alu_isa_sub = _RAND_120[0:0];
  _RAND_121 = {1{`RANDOM}};
  bufInfo_1_alu_isa_subw = _RAND_121[0:0];
  _RAND_122 = {1{`RANDOM}};
  bufInfo_1_alu_isa_sll = _RAND_122[0:0];
  _RAND_123 = {1{`RANDOM}};
  bufInfo_1_alu_isa_sllw = _RAND_123[0:0];
  _RAND_124 = {1{`RANDOM}};
  bufInfo_1_alu_isa_slt = _RAND_124[0:0];
  _RAND_125 = {1{`RANDOM}};
  bufInfo_1_alu_isa_sltu = _RAND_125[0:0];
  _RAND_126 = {1{`RANDOM}};
  bufInfo_1_alu_isa_xor = _RAND_126[0:0];
  _RAND_127 = {1{`RANDOM}};
  bufInfo_1_alu_isa_srl = _RAND_127[0:0];
  _RAND_128 = {1{`RANDOM}};
  bufInfo_1_alu_isa_srlw = _RAND_128[0:0];
  _RAND_129 = {1{`RANDOM}};
  bufInfo_1_alu_isa_sra = _RAND_129[0:0];
  _RAND_130 = {1{`RANDOM}};
  bufInfo_1_alu_isa_sraw = _RAND_130[0:0];
  _RAND_131 = {1{`RANDOM}};
  bufInfo_1_alu_isa_or = _RAND_131[0:0];
  _RAND_132 = {1{`RANDOM}};
  bufInfo_1_alu_isa_and = _RAND_132[0:0];
  _RAND_133 = {1{`RANDOM}};
  bufInfo_1_alu_isa_wfi = _RAND_133[0:0];
  _RAND_134 = {1{`RANDOM}};
  bufInfo_1_bru_isa_jal = _RAND_134[0:0];
  _RAND_135 = {1{`RANDOM}};
  bufInfo_1_bru_isa_jalr = _RAND_135[0:0];
  _RAND_136 = {1{`RANDOM}};
  bufInfo_1_bru_isa_beq = _RAND_136[0:0];
  _RAND_137 = {1{`RANDOM}};
  bufInfo_1_bru_isa_bne = _RAND_137[0:0];
  _RAND_138 = {1{`RANDOM}};
  bufInfo_1_bru_isa_blt = _RAND_138[0:0];
  _RAND_139 = {1{`RANDOM}};
  bufInfo_1_bru_isa_bge = _RAND_139[0:0];
  _RAND_140 = {1{`RANDOM}};
  bufInfo_1_bru_isa_bltu = _RAND_140[0:0];
  _RAND_141 = {1{`RANDOM}};
  bufInfo_1_bru_isa_bgeu = _RAND_141[0:0];
  _RAND_142 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_lb = _RAND_142[0:0];
  _RAND_143 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_lh = _RAND_143[0:0];
  _RAND_144 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_lw = _RAND_144[0:0];
  _RAND_145 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_ld = _RAND_145[0:0];
  _RAND_146 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_lbu = _RAND_146[0:0];
  _RAND_147 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_lhu = _RAND_147[0:0];
  _RAND_148 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_lwu = _RAND_148[0:0];
  _RAND_149 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_sb = _RAND_149[0:0];
  _RAND_150 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_sh = _RAND_150[0:0];
  _RAND_151 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_sw = _RAND_151[0:0];
  _RAND_152 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_sd = _RAND_152[0:0];
  _RAND_153 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_fence = _RAND_153[0:0];
  _RAND_154 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_fence_i = _RAND_154[0:0];
  _RAND_155 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_sfence_vma = _RAND_155[0:0];
  _RAND_156 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_lr_w = _RAND_156[0:0];
  _RAND_157 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_sc_w = _RAND_157[0:0];
  _RAND_158 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoswap_w = _RAND_158[0:0];
  _RAND_159 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoadd_w = _RAND_159[0:0];
  _RAND_160 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoxor_w = _RAND_160[0:0];
  _RAND_161 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoand_w = _RAND_161[0:0];
  _RAND_162 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoor_w = _RAND_162[0:0];
  _RAND_163 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amomin_w = _RAND_163[0:0];
  _RAND_164 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amomax_w = _RAND_164[0:0];
  _RAND_165 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amominu_w = _RAND_165[0:0];
  _RAND_166 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amomaxu_w = _RAND_166[0:0];
  _RAND_167 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_lr_d = _RAND_167[0:0];
  _RAND_168 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_sc_d = _RAND_168[0:0];
  _RAND_169 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoswap_d = _RAND_169[0:0];
  _RAND_170 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoadd_d = _RAND_170[0:0];
  _RAND_171 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoxor_d = _RAND_171[0:0];
  _RAND_172 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoand_d = _RAND_172[0:0];
  _RAND_173 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amoor_d = _RAND_173[0:0];
  _RAND_174 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amomin_d = _RAND_174[0:0];
  _RAND_175 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amomax_d = _RAND_175[0:0];
  _RAND_176 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amominu_d = _RAND_176[0:0];
  _RAND_177 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_amomaxu_d = _RAND_177[0:0];
  _RAND_178 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_flw = _RAND_178[0:0];
  _RAND_179 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_fsw = _RAND_179[0:0];
  _RAND_180 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_fld = _RAND_180[0:0];
  _RAND_181 = {1{`RANDOM}};
  bufInfo_1_lsu_isa_fsd = _RAND_181[0:0];
  _RAND_182 = {1{`RANDOM}};
  bufInfo_1_csr_isa_rw = _RAND_182[0:0];
  _RAND_183 = {1{`RANDOM}};
  bufInfo_1_csr_isa_rs = _RAND_183[0:0];
  _RAND_184 = {1{`RANDOM}};
  bufInfo_1_csr_isa_rc = _RAND_184[0:0];
  _RAND_185 = {1{`RANDOM}};
  bufInfo_1_csr_isa_rwi = _RAND_185[0:0];
  _RAND_186 = {1{`RANDOM}};
  bufInfo_1_csr_isa_rsi = _RAND_186[0:0];
  _RAND_187 = {1{`RANDOM}};
  bufInfo_1_csr_isa_rci = _RAND_187[0:0];
  _RAND_188 = {1{`RANDOM}};
  bufInfo_1_mul_isa_mul = _RAND_188[0:0];
  _RAND_189 = {1{`RANDOM}};
  bufInfo_1_mul_isa_mulh = _RAND_189[0:0];
  _RAND_190 = {1{`RANDOM}};
  bufInfo_1_mul_isa_mulhsu = _RAND_190[0:0];
  _RAND_191 = {1{`RANDOM}};
  bufInfo_1_mul_isa_mulhu = _RAND_191[0:0];
  _RAND_192 = {1{`RANDOM}};
  bufInfo_1_mul_isa_div = _RAND_192[0:0];
  _RAND_193 = {1{`RANDOM}};
  bufInfo_1_mul_isa_divu = _RAND_193[0:0];
  _RAND_194 = {1{`RANDOM}};
  bufInfo_1_mul_isa_rem = _RAND_194[0:0];
  _RAND_195 = {1{`RANDOM}};
  bufInfo_1_mul_isa_remu = _RAND_195[0:0];
  _RAND_196 = {1{`RANDOM}};
  bufInfo_1_mul_isa_mulw = _RAND_196[0:0];
  _RAND_197 = {1{`RANDOM}};
  bufInfo_1_mul_isa_divw = _RAND_197[0:0];
  _RAND_198 = {1{`RANDOM}};
  bufInfo_1_mul_isa_divuw = _RAND_198[0:0];
  _RAND_199 = {1{`RANDOM}};
  bufInfo_1_mul_isa_remw = _RAND_199[0:0];
  _RAND_200 = {1{`RANDOM}};
  bufInfo_1_mul_isa_remuw = _RAND_200[0:0];
  _RAND_201 = {1{`RANDOM}};
  bufInfo_1_phy_rs1 = _RAND_201[5:0];
  _RAND_202 = {1{`RANDOM}};
  bufInfo_1_phy_rs2 = _RAND_202[5:0];
  _RAND_203 = {1{`RANDOM}};
  bufInfo_1_phy_rs3 = _RAND_203[5:0];
  _RAND_204 = {1{`RANDOM}};
  isOpReady_0_0 = _RAND_204[0:0];
  _RAND_205 = {1{`RANDOM}};
  isOpReady_0_1 = _RAND_205[0:0];
  _RAND_206 = {1{`RANDOM}};
  isOpReady_1_0 = _RAND_206[0:0];
  _RAND_207 = {1{`RANDOM}};
  isOpReady_1_1 = _RAND_207[0:0];
  _RAND_208 = {1{`RANDOM}};
  ageMatrixW_0_0 = _RAND_208[0:0];
  _RAND_209 = {1{`RANDOM}};
  ageMatrixW_0_1 = _RAND_209[0:0];
  _RAND_210 = {1{`RANDOM}};
  ageMatrixW_1_1 = _RAND_210[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_7(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign io_enq_ready = io_deq_ready | empty; // @[Decoupled.scala 305:16 325:{24,39}]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Alu(
  input   clock,
  input   reset,
  input   io_alu_iss_exe_valid,
  input   io_alu_exe_iwb_ready,
  input   io_flush
);
  wire  alu_exe_iwb_fifo_clock; // @[Alu.scala 38:32]
  wire  alu_exe_iwb_fifo_reset; // @[Alu.scala 38:32]
  wire  alu_exe_iwb_fifo_io_enq_ready; // @[Alu.scala 38:32]
  wire  alu_exe_iwb_fifo_io_enq_valid; // @[Alu.scala 38:32]
  wire  alu_exe_iwb_fifo_io_deq_ready; // @[Alu.scala 38:32]
  wire  alu_exe_iwb_fifo_io_deq_valid; // @[Alu.scala 38:32]
  Queue_7 alu_exe_iwb_fifo ( // @[Alu.scala 38:32]
    .clock(alu_exe_iwb_fifo_clock),
    .reset(alu_exe_iwb_fifo_reset),
    .io_enq_ready(alu_exe_iwb_fifo_io_enq_ready),
    .io_enq_valid(alu_exe_iwb_fifo_io_enq_valid),
    .io_deq_ready(alu_exe_iwb_fifo_io_deq_ready),
    .io_deq_valid(alu_exe_iwb_fifo_io_deq_valid)
  );
  assign alu_exe_iwb_fifo_clock = clock;
  assign alu_exe_iwb_fifo_reset = reset | io_flush; // @[Alu.scala 40:42]
  assign alu_exe_iwb_fifo_io_enq_valid = io_alu_iss_exe_valid; // @[Alu.scala 90:33]
  assign alu_exe_iwb_fifo_io_deq_ready = io_alu_exe_iwb_ready; // @[Alu.scala 39:18]
endmodule
module Queue_9(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_enq_bits_isPredictTaken,
  input   io_enq_bits_isFinalTaken,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_10(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [38:0] io_enq_bits_btbResp_target,
  input  [38:0] io_enq_bits_rasResp_target,
  input         io_enq_bits_isRas,
  input  [63:0] io_enq_bits_finalTarget,
  input         io_deq_ready,
  output        io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Bru(
  input         clock,
  input         reset,
  output        io_bru_iss_exe_ready,
  input         io_bru_iss_exe_valid,
  input         io_bru_iss_exe_bits_fun_jalr,
  input         io_bru_iss_exe_bits_fun_beq,
  input         io_bru_iss_exe_bits_fun_bne,
  input         io_bru_iss_exe_bits_fun_blt,
  input         io_bru_iss_exe_bits_fun_bge,
  input         io_bru_iss_exe_bits_fun_bltu,
  input         io_bru_iss_exe_bits_fun_bgeu,
  input  [63:0] io_bru_iss_exe_bits_param_imm,
  input  [63:0] io_bru_iss_exe_bits_param_dat_op1,
  input  [63:0] io_bru_iss_exe_bits_param_dat_op2,
  input         io_bru_exe_iwb_ready,
  output        io_bftq_ready,
  input         io_bftq_valid,
  input         io_bftq_bits_isPredictTaken,
  output        io_jftq_ready,
  input         io_jftq_valid,
  input  [38:0] io_jftq_bits_btbResp_target,
  input  [38:0] io_jftq_bits_rasResp_target,
  input         io_jftq_bits_isRas,
  input         io_bctq_ready,
  input         io_jctq_ready,
  input         io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  wire  bru_exe_iwb_fifo_clock; // @[Bru.scala 46:32]
  wire  bru_exe_iwb_fifo_reset; // @[Bru.scala 46:32]
  wire  bru_exe_iwb_fifo_io_enq_ready; // @[Bru.scala 46:32]
  wire  bru_exe_iwb_fifo_io_enq_valid; // @[Bru.scala 46:32]
  wire  bru_exe_iwb_fifo_io_deq_ready; // @[Bru.scala 46:32]
  wire  bru_exe_iwb_fifo_io_deq_valid; // @[Bru.scala 46:32]
  wire  bctq_clock; // @[Bru.scala 47:20]
  wire  bctq_reset; // @[Bru.scala 47:20]
  wire  bctq_io_enq_ready; // @[Bru.scala 47:20]
  wire  bctq_io_enq_valid; // @[Bru.scala 47:20]
  wire  bctq_io_enq_bits_isPredictTaken; // @[Bru.scala 47:20]
  wire  bctq_io_enq_bits_isFinalTaken; // @[Bru.scala 47:20]
  wire  bctq_io_deq_ready; // @[Bru.scala 47:20]
  wire  bctq_io_deq_valid; // @[Bru.scala 47:20]
  wire  jctq_clock; // @[Bru.scala 48:20]
  wire  jctq_reset; // @[Bru.scala 48:20]
  wire  jctq_io_enq_ready; // @[Bru.scala 48:20]
  wire  jctq_io_enq_valid; // @[Bru.scala 48:20]
  wire [38:0] jctq_io_enq_bits_btbResp_target; // @[Bru.scala 48:20]
  wire [38:0] jctq_io_enq_bits_rasResp_target; // @[Bru.scala 48:20]
  wire  jctq_io_enq_bits_isRas; // @[Bru.scala 48:20]
  wire [63:0] jctq_io_enq_bits_finalTarget; // @[Bru.scala 48:20]
  wire  jctq_io_deq_ready; // @[Bru.scala 48:20]
  wire  jctq_io_deq_valid; // @[Bru.scala 48:20]
  reg  misPredict_locker; // @[Bru.scala 50:34]
  wire  _is_branchTaken_T = io_bru_iss_exe_bits_param_dat_op1 == io_bru_iss_exe_bits_param_dat_op2; // @[Bru.scala 62:42]
  wire  _is_branchTaken_T_1 = io_bru_iss_exe_bits_param_dat_op1 != io_bru_iss_exe_bits_param_dat_op2; // @[Bru.scala 63:42]
  wire  _is_branchTaken_T_4 = $signed(io_bru_iss_exe_bits_param_dat_op1) < $signed(io_bru_iss_exe_bits_param_dat_op2); // @[Bru.scala 64:49]
  wire  _is_branchTaken_T_7 = $signed(io_bru_iss_exe_bits_param_dat_op1) >= $signed(io_bru_iss_exe_bits_param_dat_op2); // @[Bru.scala 65:49]
  wire  _is_branchTaken_T_8 = io_bru_iss_exe_bits_param_dat_op1 < io_bru_iss_exe_bits_param_dat_op2; // @[Bru.scala 66:42]
  wire  _is_branchTaken_T_9 = io_bru_iss_exe_bits_param_dat_op1 >= io_bru_iss_exe_bits_param_dat_op2; // @[Bru.scala 67:42]
  wire [63:0] _jctq_io_enq_bits_finalTarget_T_1 = io_bru_iss_exe_bits_param_dat_op1 + io_bru_iss_exe_bits_param_imm; // @[Bru.scala 79:40]
  wire  _T = bctq_io_enq_ready & bctq_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = bctq_io_enq_bits_isPredictTaken != bctq_io_enq_bits_isFinalTaken; // @[frontend.scala 245:37]
  wire  _T_3 = jctq_io_enq_ready & jctq_io_enq_valid; // @[Decoupled.scala 52:35]
  wire [63:0] _GEN_2 = {{25'd0}, jctq_io_enq_bits_rasResp_target}; // @[frontend.scala 250:48]
  wire [63:0] _GEN_3 = {{25'd0}, jctq_io_enq_bits_btbResp_target}; // @[frontend.scala 250:80]
  wire  _T_6 = jctq_io_enq_bits_isRas ? _GEN_2 != jctq_io_enq_bits_finalTarget : _GEN_3 != jctq_io_enq_bits_finalTarget; // @[frontend.scala 250:25]
  wire  _GEN_0 = _T & _T_1 | _T_3 & _T_6 | misPredict_locker; // @[Bru.scala 97:122 98:23 50:34]
  wire  _io_bftq_ready_T = io_bru_iss_exe_ready & io_bru_iss_exe_valid; // @[Decoupled.scala 52:35]
  wire  _io_bftq_ready_T_5 = io_bru_iss_exe_bits_fun_beq | io_bru_iss_exe_bits_fun_bne | io_bru_iss_exe_bits_fun_blt |
    io_bru_iss_exe_bits_fun_bge | io_bru_iss_exe_bits_fun_bltu | io_bru_iss_exe_bits_fun_bgeu; // @[riscv_isa.scala 93:48]
  wire  _io_bftq_ready_T_6 = _io_bftq_ready_T & _io_bftq_ready_T_5; // @[Bru.scala 112:40]
  wire  _io_jftq_ready_T_1 = _io_bftq_ready_T & io_bru_iss_exe_bits_fun_jalr; // @[Bru.scala 113:40]
  wire  _T_14 = ~reset; // @[Bru.scala 124:9]
  wire  _T_16 = io_jftq_ready & io_jftq_valid; // @[Decoupled.scala 52:35]
  wire  _T_34 = io_bftq_ready & io_bftq_valid; // @[Decoupled.scala 52:35]
  wire  _T_41 = bru_exe_iwb_fifo_io_enq_ready & bru_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  Queue_7 bru_exe_iwb_fifo ( // @[Bru.scala 46:32]
    .clock(bru_exe_iwb_fifo_clock),
    .reset(bru_exe_iwb_fifo_reset),
    .io_enq_ready(bru_exe_iwb_fifo_io_enq_ready),
    .io_enq_valid(bru_exe_iwb_fifo_io_enq_valid),
    .io_deq_ready(bru_exe_iwb_fifo_io_deq_ready),
    .io_deq_valid(bru_exe_iwb_fifo_io_deq_valid)
  );
  Queue_9 bctq ( // @[Bru.scala 47:20]
    .clock(bctq_clock),
    .reset(bctq_reset),
    .io_enq_ready(bctq_io_enq_ready),
    .io_enq_valid(bctq_io_enq_valid),
    .io_enq_bits_isPredictTaken(bctq_io_enq_bits_isPredictTaken),
    .io_enq_bits_isFinalTaken(bctq_io_enq_bits_isFinalTaken),
    .io_deq_ready(bctq_io_deq_ready),
    .io_deq_valid(bctq_io_deq_valid)
  );
  Queue_10 jctq ( // @[Bru.scala 48:20]
    .clock(jctq_clock),
    .reset(jctq_reset),
    .io_enq_ready(jctq_io_enq_ready),
    .io_enq_valid(jctq_io_enq_valid),
    .io_enq_bits_btbResp_target(jctq_io_enq_bits_btbResp_target),
    .io_enq_bits_rasResp_target(jctq_io_enq_bits_rasResp_target),
    .io_enq_bits_isRas(jctq_io_enq_bits_isRas),
    .io_enq_bits_finalTarget(jctq_io_enq_bits_finalTarget),
    .io_deq_ready(jctq_io_deq_ready),
    .io_deq_valid(jctq_io_deq_valid)
  );
  assign io_bru_iss_exe_ready = bru_exe_iwb_fifo_io_enq_ready & bctq_io_enq_ready & jctq_io_enq_ready & ~
    misPredict_locker; // @[Bru.scala 110:97]
  assign io_bftq_ready = _io_bftq_ready_T & _io_bftq_ready_T_5; // @[Bru.scala 112:40]
  assign io_jftq_ready = _io_bftq_ready_T & io_bru_iss_exe_bits_fun_jalr; // @[Bru.scala 113:40]
  assign bru_exe_iwb_fifo_clock = clock;
  assign bru_exe_iwb_fifo_reset = reset | io_flush; // @[Bru.scala 105:42]
  assign bru_exe_iwb_fifo_io_enq_valid = io_bru_iss_exe_ready & io_bru_iss_exe_valid; // @[Decoupled.scala 52:35]
  assign bru_exe_iwb_fifo_io_deq_ready = io_bru_exe_iwb_ready; // @[Bru.scala 101:18]
  assign bctq_clock = clock;
  assign bctq_reset = reset | io_flush; // @[Bru.scala 106:30]
  assign bctq_io_enq_valid = _io_bftq_ready_T & _io_bftq_ready_T_5; // @[Bru.scala 116:44]
  assign bctq_io_enq_bits_isPredictTaken = io_bftq_bits_isPredictTaken; // @[Bru.scala 70:63]
  assign bctq_io_enq_bits_isFinalTaken = io_bru_iss_exe_bits_fun_beq & _is_branchTaken_T | io_bru_iss_exe_bits_fun_bne
     & _is_branchTaken_T_1 | io_bru_iss_exe_bits_fun_blt & _is_branchTaken_T_4 | io_bru_iss_exe_bits_fun_bge &
    _is_branchTaken_T_7 | io_bru_iss_exe_bits_fun_bltu & _is_branchTaken_T_8 | io_bru_iss_exe_bits_fun_bgeu &
    _is_branchTaken_T_9; // @[Mux.scala 27:73]
  assign bctq_io_deq_ready = io_bctq_ready; // @[Bru.scala 102:11]
  assign jctq_clock = clock;
  assign jctq_reset = reset | io_flush; // @[Bru.scala 107:30]
  assign jctq_io_enq_valid = _io_bftq_ready_T & io_bru_iss_exe_bits_fun_jalr; // @[Bru.scala 117:44]
  assign jctq_io_enq_bits_btbResp_target = io_jftq_bits_btbResp_target; // @[Bru.scala 78:61]
  assign jctq_io_enq_bits_rasResp_target = io_jftq_bits_rasResp_target; // @[Bru.scala 78:61]
  assign jctq_io_enq_bits_isRas = io_jftq_bits_isRas; // @[Bru.scala 78:61]
  assign jctq_io_enq_bits_finalTarget = {_jctq_io_enq_bits_finalTarget_T_1[63:1], 1'h0}; // @[Bru.scala 79:52]
  assign jctq_io_deq_ready = io_jctq_ready; // @[Bru.scala 103:11]
  always @(posedge clock) begin
    if (reset) begin // @[Bru.scala 50:34]
      misPredict_locker <= 1'h0; // @[Bru.scala 50:34]
    end else if (io_flush) begin // @[Bru.scala 95:20]
      misPredict_locker <= 1'h0; // @[Bru.scala 96:23]
    end else begin
      misPredict_locker <= _GEN_0;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_3 == _io_jftq_ready_T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Bru.scala:124 assert( jctq.io.enq.fire === (io.bru_iss_exe.fire & io.bru_iss_exe.bits.fun.jalr) )\n"
            ); // @[Bru.scala 124:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_3 == _io_jftq_ready_T_1) & ~reset) begin
          $fatal; // @[Bru.scala 124:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_14 & ~(_T_16 == _T_3)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Bru.scala:125 assert( io.jftq.fire === jctq.io.enq.fire )\n"); // @[Bru.scala 125:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_16 == _T_3) & _T_14) begin
          $fatal; // @[Bru.scala 125:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_14 & ~(_T == _io_bftq_ready_T_6)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Bru.scala:126 assert( bctq.io.enq.fire === (io.bru_iss_exe.fire & io.bru_iss_exe.bits.fun.is_branch)  )\n"
            ); // @[Bru.scala 126:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T == _io_bftq_ready_T_6) & _T_14) begin
          $fatal; // @[Bru.scala 126:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_14 & ~(_T_34 == _T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Bru.scala:127 assert( io.bftq.fire === bctq.io.enq.fire )\n"); // @[Bru.scala 127:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_34 == _T) & _T_14) begin
          $fatal; // @[Bru.scala 127:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_14 & ~(_io_bftq_ready_T == _T_41)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Bru.scala:128 assert( io.bru_iss_exe.fire === bru_exe_iwb_fifo.io.enq.fire )\n"); // @[Bru.scala 128:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_io_bftq_ready_T == _T_41) & _T_14) begin
          $fatal; // @[Bru.scala 128:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  misPredict_locker = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Store_queue(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_fun_lb,
  input         io_enq_bits_fun_lh,
  input         io_enq_bits_fun_lw,
  input         io_enq_bits_fun_ld,
  input         io_enq_bits_fun_lbu,
  input         io_enq_bits_fun_lhu,
  input         io_enq_bits_fun_lwu,
  input         io_enq_bits_fun_sb,
  input         io_enq_bits_fun_sh,
  input         io_enq_bits_fun_sw,
  input         io_enq_bits_fun_sd,
  input         io_enq_bits_fun_lr_w,
  input         io_enq_bits_fun_sc_w,
  input         io_enq_bits_fun_amoswap_w,
  input         io_enq_bits_fun_amoadd_w,
  input         io_enq_bits_fun_amoxor_w,
  input         io_enq_bits_fun_amoand_w,
  input         io_enq_bits_fun_amoor_w,
  input         io_enq_bits_fun_amomin_w,
  input         io_enq_bits_fun_amomax_w,
  input         io_enq_bits_fun_amominu_w,
  input         io_enq_bits_fun_amomaxu_w,
  input         io_enq_bits_fun_lr_d,
  input         io_enq_bits_fun_sc_d,
  input         io_enq_bits_fun_amoswap_d,
  input         io_enq_bits_fun_amoadd_d,
  input         io_enq_bits_fun_amoxor_d,
  input         io_enq_bits_fun_amoand_d,
  input         io_enq_bits_fun_amoor_d,
  input         io_enq_bits_fun_amomin_d,
  input         io_enq_bits_fun_amomax_d,
  input         io_enq_bits_fun_amominu_d,
  input         io_enq_bits_fun_amomaxu_d,
  input         io_enq_bits_fun_flw,
  input         io_enq_bits_fun_fsw,
  input         io_enq_bits_fun_fld,
  input         io_enq_bits_fun_fsd,
  input  [63:0] io_enq_bits_param_dat_op1,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_fun_lb,
  output        io_deq_bits_fun_lh,
  output        io_deq_bits_fun_lw,
  output        io_deq_bits_fun_ld,
  output        io_deq_bits_fun_lbu,
  output        io_deq_bits_fun_lhu,
  output        io_deq_bits_fun_lwu,
  output        io_deq_bits_fun_sb,
  output        io_deq_bits_fun_sh,
  output        io_deq_bits_fun_sw,
  output        io_deq_bits_fun_sd,
  output        io_deq_bits_fun_lr_w,
  output        io_deq_bits_fun_sc_w,
  output        io_deq_bits_fun_amoswap_w,
  output        io_deq_bits_fun_amoadd_w,
  output        io_deq_bits_fun_amoxor_w,
  output        io_deq_bits_fun_amoand_w,
  output        io_deq_bits_fun_amoor_w,
  output        io_deq_bits_fun_amomin_w,
  output        io_deq_bits_fun_amomax_w,
  output        io_deq_bits_fun_amominu_w,
  output        io_deq_bits_fun_amomaxu_w,
  output        io_deq_bits_fun_lr_d,
  output        io_deq_bits_fun_sc_d,
  output        io_deq_bits_fun_amoswap_d,
  output        io_deq_bits_fun_amoadd_d,
  output        io_deq_bits_fun_amoxor_d,
  output        io_deq_bits_fun_amoand_d,
  output        io_deq_bits_fun_amoor_d,
  output        io_deq_bits_fun_amomin_d,
  output        io_deq_bits_fun_amomax_d,
  output        io_deq_bits_fun_amominu_d,
  output        io_deq_bits_fun_amomaxu_d,
  output        io_deq_bits_fun_flw,
  output        io_deq_bits_fun_fsw,
  output        io_deq_bits_fun_fld,
  output        io_deq_bits_fun_fsd,
  output [63:0] io_deq_bits_param_dat_op1,
  input         io_cmm_lsu_is_amo_pending,
  input         io_cmm_lsu_is_store_commit_0,
  output        io_is_empty,
  input         io_overlapReq_valid,
  input  [31:0] io_overlapReq_bits_paddr,
  output        io_overlapResp_valid,
  input         io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [63:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [63:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
`endif // RANDOMIZE_REG_INIT
  reg  buff_0_fun_lb; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_lh; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_lw; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_ld; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_lbu; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_lhu; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_lwu; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_sb; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_sh; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_sw; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_sd; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_lr_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_sc_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoswap_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoadd_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoxor_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoand_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoor_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amomin_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amomax_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amominu_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amomaxu_w; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_lr_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_sc_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoswap_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoadd_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoxor_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoand_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amoor_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amomin_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amomax_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amominu_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_amomaxu_d; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_flw; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_fsw; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_fld; // @[Store_queue.scala 54:21]
  reg  buff_0_fun_fsd; // @[Store_queue.scala 54:21]
  reg [63:0] buff_0_param_dat_op1; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_lb; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_lh; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_lw; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_ld; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_lbu; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_lhu; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_lwu; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_sb; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_sh; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_sw; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_sd; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_lr_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_sc_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoswap_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoadd_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoxor_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoand_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoor_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amomin_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amomax_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amominu_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amomaxu_w; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_lr_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_sc_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoswap_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoadd_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoxor_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoand_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amoor_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amomin_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amomax_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amominu_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_amomaxu_d; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_flw; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_fsw; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_fld; // @[Store_queue.scala 54:21]
  reg  buff_1_fun_fsd; // @[Store_queue.scala 54:21]
  reg [63:0] buff_1_param_dat_op1; // @[Store_queue.scala 54:21]
  reg [1:0] cm_ptr_reg; // @[Store_queue.scala 56:27]
  reg [1:0] wr_ptr_reg; // @[Store_queue.scala 57:27]
  reg [1:0] rd_ptr_reg; // @[Store_queue.scala 58:27]
  wire  wr_ptr = wr_ptr_reg[0]; // @[Store_queue.scala 61:26]
  wire  rd_ptr = rd_ptr_reg[0]; // @[Store_queue.scala 62:26]
  wire  full = wr_ptr_reg[1] != rd_ptr_reg[1] & wr_ptr == rd_ptr; // @[Store_queue.scala 64:54]
  wire  emty = cm_ptr_reg == rd_ptr_reg; // @[Store_queue.scala 65:25]
  reg  is_amo; // @[Store_queue.scala 69:23]
  reg  is_amo_pre; // @[Store_queue.scala 76:29]
  wire  is_amo_pos = io_cmm_lsu_is_amo_pending & ~is_amo_pre; // @[Store_queue.scala 77:48]
  wire  _T_1 = is_amo & ~io_is_empty; // @[Store_queue.scala 82:24]
  wire  _GEN_0 = is_amo & ~io_is_empty ? 1'h0 : is_amo; // @[Store_queue.scala 82:40 83:14 69:23]
  wire  _GEN_1 = is_amo_pos | _GEN_0; // @[Store_queue.scala 80:31 81:14]
  wire  _GEN_47 = rd_ptr ? buff_1_fun_lb : buff_0_fun_lb; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_48 = rd_ptr ? buff_1_fun_lh : buff_0_fun_lh; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_49 = rd_ptr ? buff_1_fun_lw : buff_0_fun_lw; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_50 = rd_ptr ? buff_1_fun_ld : buff_0_fun_ld; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_51 = rd_ptr ? buff_1_fun_lbu : buff_0_fun_lbu; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_52 = rd_ptr ? buff_1_fun_lhu : buff_0_fun_lhu; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_53 = rd_ptr ? buff_1_fun_lwu : buff_0_fun_lwu; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_54 = rd_ptr ? buff_1_fun_sb : buff_0_fun_sb; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_55 = rd_ptr ? buff_1_fun_sh : buff_0_fun_sh; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_56 = rd_ptr ? buff_1_fun_sw : buff_0_fun_sw; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_57 = rd_ptr ? buff_1_fun_sd : buff_0_fun_sd; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_61 = rd_ptr ? buff_1_fun_lr_w : buff_0_fun_lr_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_62 = rd_ptr ? buff_1_fun_sc_w : buff_0_fun_sc_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_63 = rd_ptr ? buff_1_fun_amoswap_w : buff_0_fun_amoswap_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_64 = rd_ptr ? buff_1_fun_amoadd_w : buff_0_fun_amoadd_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_65 = rd_ptr ? buff_1_fun_amoxor_w : buff_0_fun_amoxor_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_66 = rd_ptr ? buff_1_fun_amoand_w : buff_0_fun_amoand_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_67 = rd_ptr ? buff_1_fun_amoor_w : buff_0_fun_amoor_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_68 = rd_ptr ? buff_1_fun_amomin_w : buff_0_fun_amomin_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_69 = rd_ptr ? buff_1_fun_amomax_w : buff_0_fun_amomax_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_70 = rd_ptr ? buff_1_fun_amominu_w : buff_0_fun_amominu_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_71 = rd_ptr ? buff_1_fun_amomaxu_w : buff_0_fun_amomaxu_w; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_72 = rd_ptr ? buff_1_fun_lr_d : buff_0_fun_lr_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_73 = rd_ptr ? buff_1_fun_sc_d : buff_0_fun_sc_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_74 = rd_ptr ? buff_1_fun_amoswap_d : buff_0_fun_amoswap_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_75 = rd_ptr ? buff_1_fun_amoadd_d : buff_0_fun_amoadd_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_76 = rd_ptr ? buff_1_fun_amoxor_d : buff_0_fun_amoxor_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_77 = rd_ptr ? buff_1_fun_amoand_d : buff_0_fun_amoand_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_78 = rd_ptr ? buff_1_fun_amoor_d : buff_0_fun_amoor_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_79 = rd_ptr ? buff_1_fun_amomin_d : buff_0_fun_amomin_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_80 = rd_ptr ? buff_1_fun_amomax_d : buff_0_fun_amomax_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_81 = rd_ptr ? buff_1_fun_amominu_d : buff_0_fun_amominu_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_82 = rd_ptr ? buff_1_fun_amomaxu_d : buff_0_fun_amomaxu_d; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_83 = rd_ptr ? buff_1_fun_flw : buff_0_fun_flw; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_84 = rd_ptr ? buff_1_fun_fsw : buff_0_fun_fsw; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_85 = rd_ptr ? buff_1_fun_fld : buff_0_fun_fld; // @[Store_queue.scala 92:{21,21}]
  wire  _GEN_86 = rd_ptr ? buff_1_fun_fsd : buff_0_fun_fsd; // @[Store_queue.scala 92:{21,21}]
  wire [63:0] _GEN_88 = rd_ptr ? buff_1_param_dat_op1 : buff_0_param_dat_op1; // @[Store_queue.scala 92:{21,21}]
  wire [1:0] _wr_ptr_reg_T_1 = cm_ptr_reg + 2'h1; // @[Store_queue.scala 100:86]
  wire  _T_5 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_92 = ~wr_ptr ? io_enq_bits_fun_lb : buff_0_fun_lb; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_93 = wr_ptr ? io_enq_bits_fun_lb : buff_1_fun_lb; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_94 = ~wr_ptr ? io_enq_bits_fun_lh : buff_0_fun_lh; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_95 = wr_ptr ? io_enq_bits_fun_lh : buff_1_fun_lh; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_96 = ~wr_ptr ? io_enq_bits_fun_lw : buff_0_fun_lw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_97 = wr_ptr ? io_enq_bits_fun_lw : buff_1_fun_lw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_98 = ~wr_ptr ? io_enq_bits_fun_ld : buff_0_fun_ld; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_99 = wr_ptr ? io_enq_bits_fun_ld : buff_1_fun_ld; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_100 = ~wr_ptr ? io_enq_bits_fun_lbu : buff_0_fun_lbu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_101 = wr_ptr ? io_enq_bits_fun_lbu : buff_1_fun_lbu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_102 = ~wr_ptr ? io_enq_bits_fun_lhu : buff_0_fun_lhu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_103 = wr_ptr ? io_enq_bits_fun_lhu : buff_1_fun_lhu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_104 = ~wr_ptr ? io_enq_bits_fun_lwu : buff_0_fun_lwu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_105 = wr_ptr ? io_enq_bits_fun_lwu : buff_1_fun_lwu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_106 = ~wr_ptr ? io_enq_bits_fun_sb : buff_0_fun_sb; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_107 = wr_ptr ? io_enq_bits_fun_sb : buff_1_fun_sb; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_108 = ~wr_ptr ? io_enq_bits_fun_sh : buff_0_fun_sh; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_109 = wr_ptr ? io_enq_bits_fun_sh : buff_1_fun_sh; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_110 = ~wr_ptr ? io_enq_bits_fun_sw : buff_0_fun_sw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_111 = wr_ptr ? io_enq_bits_fun_sw : buff_1_fun_sw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_112 = ~wr_ptr ? io_enq_bits_fun_sd : buff_0_fun_sd; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_113 = wr_ptr ? io_enq_bits_fun_sd : buff_1_fun_sd; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_120 = ~wr_ptr ? io_enq_bits_fun_lr_w : buff_0_fun_lr_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_121 = wr_ptr ? io_enq_bits_fun_lr_w : buff_1_fun_lr_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_122 = ~wr_ptr ? io_enq_bits_fun_sc_w : buff_0_fun_sc_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_123 = wr_ptr ? io_enq_bits_fun_sc_w : buff_1_fun_sc_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_124 = ~wr_ptr ? io_enq_bits_fun_amoswap_w : buff_0_fun_amoswap_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_125 = wr_ptr ? io_enq_bits_fun_amoswap_w : buff_1_fun_amoswap_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_126 = ~wr_ptr ? io_enq_bits_fun_amoadd_w : buff_0_fun_amoadd_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_127 = wr_ptr ? io_enq_bits_fun_amoadd_w : buff_1_fun_amoadd_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_128 = ~wr_ptr ? io_enq_bits_fun_amoxor_w : buff_0_fun_amoxor_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_129 = wr_ptr ? io_enq_bits_fun_amoxor_w : buff_1_fun_amoxor_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_130 = ~wr_ptr ? io_enq_bits_fun_amoand_w : buff_0_fun_amoand_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_131 = wr_ptr ? io_enq_bits_fun_amoand_w : buff_1_fun_amoand_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_132 = ~wr_ptr ? io_enq_bits_fun_amoor_w : buff_0_fun_amoor_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_133 = wr_ptr ? io_enq_bits_fun_amoor_w : buff_1_fun_amoor_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_134 = ~wr_ptr ? io_enq_bits_fun_amomin_w : buff_0_fun_amomin_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_135 = wr_ptr ? io_enq_bits_fun_amomin_w : buff_1_fun_amomin_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_136 = ~wr_ptr ? io_enq_bits_fun_amomax_w : buff_0_fun_amomax_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_137 = wr_ptr ? io_enq_bits_fun_amomax_w : buff_1_fun_amomax_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_138 = ~wr_ptr ? io_enq_bits_fun_amominu_w : buff_0_fun_amominu_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_139 = wr_ptr ? io_enq_bits_fun_amominu_w : buff_1_fun_amominu_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_140 = ~wr_ptr ? io_enq_bits_fun_amomaxu_w : buff_0_fun_amomaxu_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_141 = wr_ptr ? io_enq_bits_fun_amomaxu_w : buff_1_fun_amomaxu_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_142 = ~wr_ptr ? io_enq_bits_fun_lr_d : buff_0_fun_lr_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_143 = wr_ptr ? io_enq_bits_fun_lr_d : buff_1_fun_lr_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_144 = ~wr_ptr ? io_enq_bits_fun_sc_d : buff_0_fun_sc_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_145 = wr_ptr ? io_enq_bits_fun_sc_d : buff_1_fun_sc_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_146 = ~wr_ptr ? io_enq_bits_fun_amoswap_d : buff_0_fun_amoswap_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_147 = wr_ptr ? io_enq_bits_fun_amoswap_d : buff_1_fun_amoswap_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_148 = ~wr_ptr ? io_enq_bits_fun_amoadd_d : buff_0_fun_amoadd_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_149 = wr_ptr ? io_enq_bits_fun_amoadd_d : buff_1_fun_amoadd_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_150 = ~wr_ptr ? io_enq_bits_fun_amoxor_d : buff_0_fun_amoxor_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_151 = wr_ptr ? io_enq_bits_fun_amoxor_d : buff_1_fun_amoxor_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_152 = ~wr_ptr ? io_enq_bits_fun_amoand_d : buff_0_fun_amoand_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_153 = wr_ptr ? io_enq_bits_fun_amoand_d : buff_1_fun_amoand_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_154 = ~wr_ptr ? io_enq_bits_fun_amoor_d : buff_0_fun_amoor_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_155 = wr_ptr ? io_enq_bits_fun_amoor_d : buff_1_fun_amoor_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_156 = ~wr_ptr ? io_enq_bits_fun_amomin_d : buff_0_fun_amomin_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_157 = wr_ptr ? io_enq_bits_fun_amomin_d : buff_1_fun_amomin_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_158 = ~wr_ptr ? io_enq_bits_fun_amomax_d : buff_0_fun_amomax_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_159 = wr_ptr ? io_enq_bits_fun_amomax_d : buff_1_fun_amomax_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_160 = ~wr_ptr ? io_enq_bits_fun_amominu_d : buff_0_fun_amominu_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_161 = wr_ptr ? io_enq_bits_fun_amominu_d : buff_1_fun_amominu_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_162 = ~wr_ptr ? io_enq_bits_fun_amomaxu_d : buff_0_fun_amomaxu_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_163 = wr_ptr ? io_enq_bits_fun_amomaxu_d : buff_1_fun_amomaxu_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_164 = ~wr_ptr ? io_enq_bits_fun_flw : buff_0_fun_flw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_165 = wr_ptr ? io_enq_bits_fun_flw : buff_1_fun_flw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_166 = ~wr_ptr ? io_enq_bits_fun_fsw : buff_0_fun_fsw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_167 = wr_ptr ? io_enq_bits_fun_fsw : buff_1_fun_fsw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_168 = ~wr_ptr ? io_enq_bits_fun_fld : buff_0_fun_fld; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_169 = wr_ptr ? io_enq_bits_fun_fld : buff_1_fun_fld; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_170 = ~wr_ptr ? io_enq_bits_fun_fsd : buff_0_fun_fsd; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  _GEN_171 = wr_ptr ? io_enq_bits_fun_fsd : buff_1_fun_fsd; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [63:0] _GEN_174 = ~wr_ptr ? io_enq_bits_param_dat_op1 : buff_0_param_dat_op1; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [63:0] _GEN_175 = wr_ptr ? io_enq_bits_param_dat_op1 : buff_1_param_dat_op1; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [1:0] _wr_ptr_reg_T_3 = wr_ptr_reg + 2'h1; // @[Store_queue.scala 108:30]
  wire  _GEN_180 = _T_5 ? _GEN_92 : buff_0_fun_lb; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_181 = _T_5 ? _GEN_93 : buff_1_fun_lb; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_182 = _T_5 ? _GEN_94 : buff_0_fun_lh; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_183 = _T_5 ? _GEN_95 : buff_1_fun_lh; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_184 = _T_5 ? _GEN_96 : buff_0_fun_lw; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_185 = _T_5 ? _GEN_97 : buff_1_fun_lw; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_186 = _T_5 ? _GEN_98 : buff_0_fun_ld; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_187 = _T_5 ? _GEN_99 : buff_1_fun_ld; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_188 = _T_5 ? _GEN_100 : buff_0_fun_lbu; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_189 = _T_5 ? _GEN_101 : buff_1_fun_lbu; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_190 = _T_5 ? _GEN_102 : buff_0_fun_lhu; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_191 = _T_5 ? _GEN_103 : buff_1_fun_lhu; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_192 = _T_5 ? _GEN_104 : buff_0_fun_lwu; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_193 = _T_5 ? _GEN_105 : buff_1_fun_lwu; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_194 = _T_5 ? _GEN_106 : buff_0_fun_sb; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_195 = _T_5 ? _GEN_107 : buff_1_fun_sb; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_196 = _T_5 ? _GEN_108 : buff_0_fun_sh; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_197 = _T_5 ? _GEN_109 : buff_1_fun_sh; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_198 = _T_5 ? _GEN_110 : buff_0_fun_sw; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_199 = _T_5 ? _GEN_111 : buff_1_fun_sw; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_200 = _T_5 ? _GEN_112 : buff_0_fun_sd; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_201 = _T_5 ? _GEN_113 : buff_1_fun_sd; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_208 = _T_5 ? _GEN_120 : buff_0_fun_lr_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_209 = _T_5 ? _GEN_121 : buff_1_fun_lr_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_210 = _T_5 ? _GEN_122 : buff_0_fun_sc_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_211 = _T_5 ? _GEN_123 : buff_1_fun_sc_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_212 = _T_5 ? _GEN_124 : buff_0_fun_amoswap_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_213 = _T_5 ? _GEN_125 : buff_1_fun_amoswap_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_214 = _T_5 ? _GEN_126 : buff_0_fun_amoadd_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_215 = _T_5 ? _GEN_127 : buff_1_fun_amoadd_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_216 = _T_5 ? _GEN_128 : buff_0_fun_amoxor_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_217 = _T_5 ? _GEN_129 : buff_1_fun_amoxor_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_218 = _T_5 ? _GEN_130 : buff_0_fun_amoand_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_219 = _T_5 ? _GEN_131 : buff_1_fun_amoand_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_220 = _T_5 ? _GEN_132 : buff_0_fun_amoor_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_221 = _T_5 ? _GEN_133 : buff_1_fun_amoor_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_222 = _T_5 ? _GEN_134 : buff_0_fun_amomin_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_223 = _T_5 ? _GEN_135 : buff_1_fun_amomin_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_224 = _T_5 ? _GEN_136 : buff_0_fun_amomax_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_225 = _T_5 ? _GEN_137 : buff_1_fun_amomax_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_226 = _T_5 ? _GEN_138 : buff_0_fun_amominu_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_227 = _T_5 ? _GEN_139 : buff_1_fun_amominu_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_228 = _T_5 ? _GEN_140 : buff_0_fun_amomaxu_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_229 = _T_5 ? _GEN_141 : buff_1_fun_amomaxu_w; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_230 = _T_5 ? _GEN_142 : buff_0_fun_lr_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_231 = _T_5 ? _GEN_143 : buff_1_fun_lr_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_232 = _T_5 ? _GEN_144 : buff_0_fun_sc_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_233 = _T_5 ? _GEN_145 : buff_1_fun_sc_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_234 = _T_5 ? _GEN_146 : buff_0_fun_amoswap_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_235 = _T_5 ? _GEN_147 : buff_1_fun_amoswap_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_236 = _T_5 ? _GEN_148 : buff_0_fun_amoadd_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_237 = _T_5 ? _GEN_149 : buff_1_fun_amoadd_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_238 = _T_5 ? _GEN_150 : buff_0_fun_amoxor_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_239 = _T_5 ? _GEN_151 : buff_1_fun_amoxor_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_240 = _T_5 ? _GEN_152 : buff_0_fun_amoand_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_241 = _T_5 ? _GEN_153 : buff_1_fun_amoand_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_242 = _T_5 ? _GEN_154 : buff_0_fun_amoor_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_243 = _T_5 ? _GEN_155 : buff_1_fun_amoor_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_244 = _T_5 ? _GEN_156 : buff_0_fun_amomin_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_245 = _T_5 ? _GEN_157 : buff_1_fun_amomin_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_246 = _T_5 ? _GEN_158 : buff_0_fun_amomax_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_247 = _T_5 ? _GEN_159 : buff_1_fun_amomax_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_248 = _T_5 ? _GEN_160 : buff_0_fun_amominu_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_249 = _T_5 ? _GEN_161 : buff_1_fun_amominu_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_250 = _T_5 ? _GEN_162 : buff_0_fun_amomaxu_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_251 = _T_5 ? _GEN_163 : buff_1_fun_amomaxu_d; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_252 = _T_5 ? _GEN_164 : buff_0_fun_flw; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_253 = _T_5 ? _GEN_165 : buff_1_fun_flw; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_254 = _T_5 ? _GEN_166 : buff_0_fun_fsw; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_255 = _T_5 ? _GEN_167 : buff_1_fun_fsw; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_256 = _T_5 ? _GEN_168 : buff_0_fun_fld; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_257 = _T_5 ? _GEN_169 : buff_1_fun_fld; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_258 = _T_5 ? _GEN_170 : buff_0_fun_fsd; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_259 = _T_5 ? _GEN_171 : buff_1_fun_fsd; // @[Store_queue.scala 106:30 54:21]
  wire [63:0] _GEN_262 = _T_5 ? _GEN_174 : buff_0_param_dat_op1; // @[Store_queue.scala 106:30 54:21]
  wire [63:0] _GEN_263 = _T_5 ? _GEN_175 : buff_1_param_dat_op1; // @[Store_queue.scala 106:30 54:21]
  wire  _GEN_270 = io_flush ? buff_0_fun_lb : _GEN_180; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_271 = io_flush ? buff_1_fun_lb : _GEN_181; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_272 = io_flush ? buff_0_fun_lh : _GEN_182; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_273 = io_flush ? buff_1_fun_lh : _GEN_183; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_274 = io_flush ? buff_0_fun_lw : _GEN_184; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_275 = io_flush ? buff_1_fun_lw : _GEN_185; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_276 = io_flush ? buff_0_fun_ld : _GEN_186; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_277 = io_flush ? buff_1_fun_ld : _GEN_187; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_278 = io_flush ? buff_0_fun_lbu : _GEN_188; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_279 = io_flush ? buff_1_fun_lbu : _GEN_189; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_280 = io_flush ? buff_0_fun_lhu : _GEN_190; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_281 = io_flush ? buff_1_fun_lhu : _GEN_191; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_282 = io_flush ? buff_0_fun_lwu : _GEN_192; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_283 = io_flush ? buff_1_fun_lwu : _GEN_193; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_284 = io_flush ? buff_0_fun_sb : _GEN_194; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_285 = io_flush ? buff_1_fun_sb : _GEN_195; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_286 = io_flush ? buff_0_fun_sh : _GEN_196; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_287 = io_flush ? buff_1_fun_sh : _GEN_197; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_288 = io_flush ? buff_0_fun_sw : _GEN_198; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_289 = io_flush ? buff_1_fun_sw : _GEN_199; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_290 = io_flush ? buff_0_fun_sd : _GEN_200; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_291 = io_flush ? buff_1_fun_sd : _GEN_201; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_298 = io_flush ? buff_0_fun_lr_w : _GEN_208; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_299 = io_flush ? buff_1_fun_lr_w : _GEN_209; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_300 = io_flush ? buff_0_fun_sc_w : _GEN_210; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_301 = io_flush ? buff_1_fun_sc_w : _GEN_211; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_302 = io_flush ? buff_0_fun_amoswap_w : _GEN_212; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_303 = io_flush ? buff_1_fun_amoswap_w : _GEN_213; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_304 = io_flush ? buff_0_fun_amoadd_w : _GEN_214; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_305 = io_flush ? buff_1_fun_amoadd_w : _GEN_215; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_306 = io_flush ? buff_0_fun_amoxor_w : _GEN_216; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_307 = io_flush ? buff_1_fun_amoxor_w : _GEN_217; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_308 = io_flush ? buff_0_fun_amoand_w : _GEN_218; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_309 = io_flush ? buff_1_fun_amoand_w : _GEN_219; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_310 = io_flush ? buff_0_fun_amoor_w : _GEN_220; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_311 = io_flush ? buff_1_fun_amoor_w : _GEN_221; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_312 = io_flush ? buff_0_fun_amomin_w : _GEN_222; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_313 = io_flush ? buff_1_fun_amomin_w : _GEN_223; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_314 = io_flush ? buff_0_fun_amomax_w : _GEN_224; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_315 = io_flush ? buff_1_fun_amomax_w : _GEN_225; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_316 = io_flush ? buff_0_fun_amominu_w : _GEN_226; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_317 = io_flush ? buff_1_fun_amominu_w : _GEN_227; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_318 = io_flush ? buff_0_fun_amomaxu_w : _GEN_228; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_319 = io_flush ? buff_1_fun_amomaxu_w : _GEN_229; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_320 = io_flush ? buff_0_fun_lr_d : _GEN_230; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_321 = io_flush ? buff_1_fun_lr_d : _GEN_231; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_322 = io_flush ? buff_0_fun_sc_d : _GEN_232; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_323 = io_flush ? buff_1_fun_sc_d : _GEN_233; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_324 = io_flush ? buff_0_fun_amoswap_d : _GEN_234; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_325 = io_flush ? buff_1_fun_amoswap_d : _GEN_235; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_326 = io_flush ? buff_0_fun_amoadd_d : _GEN_236; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_327 = io_flush ? buff_1_fun_amoadd_d : _GEN_237; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_328 = io_flush ? buff_0_fun_amoxor_d : _GEN_238; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_329 = io_flush ? buff_1_fun_amoxor_d : _GEN_239; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_330 = io_flush ? buff_0_fun_amoand_d : _GEN_240; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_331 = io_flush ? buff_1_fun_amoand_d : _GEN_241; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_332 = io_flush ? buff_0_fun_amoor_d : _GEN_242; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_333 = io_flush ? buff_1_fun_amoor_d : _GEN_243; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_334 = io_flush ? buff_0_fun_amomin_d : _GEN_244; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_335 = io_flush ? buff_1_fun_amomin_d : _GEN_245; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_336 = io_flush ? buff_0_fun_amomax_d : _GEN_246; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_337 = io_flush ? buff_1_fun_amomax_d : _GEN_247; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_338 = io_flush ? buff_0_fun_amominu_d : _GEN_248; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_339 = io_flush ? buff_1_fun_amominu_d : _GEN_249; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_340 = io_flush ? buff_0_fun_amomaxu_d : _GEN_250; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_341 = io_flush ? buff_1_fun_amomaxu_d : _GEN_251; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_342 = io_flush ? buff_0_fun_flw : _GEN_252; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_343 = io_flush ? buff_1_fun_flw : _GEN_253; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_344 = io_flush ? buff_0_fun_fsw : _GEN_254; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_345 = io_flush ? buff_1_fun_fsw : _GEN_255; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_346 = io_flush ? buff_0_fun_fld : _GEN_256; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_347 = io_flush ? buff_1_fun_fld : _GEN_257; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_348 = io_flush ? buff_0_fun_fsd : _GEN_258; // @[Store_queue.scala 94:20 54:21]
  wire  _GEN_349 = io_flush ? buff_1_fun_fsd : _GEN_259; // @[Store_queue.scala 94:20 54:21]
  wire [63:0] _GEN_352 = io_flush ? buff_0_param_dat_op1 : _GEN_262; // @[Store_queue.scala 94:20 54:21]
  wire [63:0] _GEN_353 = io_flush ? buff_1_param_dat_op1 : _GEN_263; // @[Store_queue.scala 94:20 54:21]
  wire  _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _rd_ptr_reg_T_1 = rd_ptr_reg + 2'h1; // @[Store_queue.scala 112:30]
  wire  _T_9 = ~reset; // @[Store_queue.scala 129:13]
  wire  _T_11 = cm_ptr_reg != wr_ptr_reg; // @[Store_queue.scala 130:26]
  wire  _T_14 = ~(cm_ptr_reg != wr_ptr_reg); // @[Store_queue.scala 130:13]
  wire  _T_30 = rd_ptr_reg[1] != wr_ptr_reg[1]; // @[Store_queue.scala 148:28]
  wire [2:0] _ro_ptr_T = {{1'd0}, rd_ptr_reg}; // @[Store_queue.scala 151:34]
  wire  ro_ptr = _ro_ptr_T[0]; // @[Store_queue.scala 151:40]
  wire  _T_35 = ro_ptr >= rd_ptr; // @[Store_queue.scala 152:23]
  wire  _T_36 = ro_ptr < wr_ptr; // @[Store_queue.scala 152:43]
  wire [63:0] _GEN_538 = ro_ptr ? buff_1_param_dat_op1 : buff_0_param_dat_op1; // @[Store_queue.scala 152:{83,83}]
  wire  _T_40 = _GEN_538[31:3] == io_overlapReq_bits_paddr[31:3]; // @[Store_queue.scala 152:94]
  wire  _GEN_570 = ro_ptr ? buff_1_fun_sc_w : buff_0_fun_sc_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_572 = ro_ptr ? buff_1_fun_amoswap_w : buff_0_fun_amoswap_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_574 = ro_ptr ? buff_1_fun_amoadd_w : buff_0_fun_amoadd_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_576 = ro_ptr ? buff_1_fun_amoxor_w : buff_0_fun_amoxor_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_578 = ro_ptr ? buff_1_fun_amoand_w : buff_0_fun_amoand_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_580 = ro_ptr ? buff_1_fun_amoor_w : buff_0_fun_amoor_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_582 = ro_ptr ? buff_1_fun_amomin_w : buff_0_fun_amomin_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_584 = ro_ptr ? buff_1_fun_amomax_w : buff_0_fun_amomax_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_586 = ro_ptr ? buff_1_fun_amominu_w : buff_0_fun_amominu_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_588 = ro_ptr ? buff_1_fun_amomaxu_w : buff_0_fun_amomaxu_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_592 = ro_ptr ? buff_1_fun_sc_d : buff_0_fun_sc_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_594 = ro_ptr ? buff_1_fun_amoswap_d : buff_0_fun_amoswap_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_596 = ro_ptr ? buff_1_fun_amoadd_d : buff_0_fun_amoadd_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_598 = ro_ptr ? buff_1_fun_amoxor_d : buff_0_fun_amoxor_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_600 = ro_ptr ? buff_1_fun_amoand_d : buff_0_fun_amoand_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_602 = ro_ptr ? buff_1_fun_amoor_d : buff_0_fun_amoor_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_604 = ro_ptr ? buff_1_fun_amomin_d : buff_0_fun_amomin_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_606 = ro_ptr ? buff_1_fun_amomax_d : buff_0_fun_amomax_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_608 = ro_ptr ? buff_1_fun_amominu_d : buff_0_fun_amominu_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_610 = ro_ptr ? buff_1_fun_amomaxu_d : buff_0_fun_amomaxu_d; // @[Store_queue.scala 153:{27,27}]
  wire  _T_59 = _GEN_592 | _GEN_570; // @[riscv_isa.scala 140:20]
  wire  _T_60 = _GEN_572 | _GEN_574 | _GEN_576 | _GEN_578 | _GEN_580 | _GEN_582 | _GEN_584 | _GEN_586 | _GEN_588 |
    _GEN_594 | _GEN_596 | _GEN_598 | _GEN_600 | _GEN_602 | _GEN_604 | _GEN_606 | _GEN_608 | _GEN_610 | _T_59; // @[riscv_isa.scala 148:205]
  wire  _GEN_625 = _T_60 ? 1'h0 : io_overlapReq_valid; // @[Store_queue.scala 146:26 155:{43,66}]
  wire  _GEN_670 = (ro_ptr >= rd_ptr | ro_ptr < wr_ptr) & _GEN_538[31:3] == io_overlapReq_bits_paddr[31:3] ? _GEN_625 :
    io_overlapReq_valid; // @[Store_queue.scala 152:136 146:26]
  wire  ro_ptr_1 = _rd_ptr_reg_T_1[0]; // @[Store_queue.scala 151:40]
  wire  _T_61 = ro_ptr_1 >= rd_ptr; // @[Store_queue.scala 152:23]
  wire  _T_62 = ro_ptr_1 < wr_ptr; // @[Store_queue.scala 152:43]
  wire [63:0] _GEN_672 = ro_ptr_1 ? buff_1_param_dat_op1 : buff_0_param_dat_op1; // @[Store_queue.scala 152:{83,83}]
  wire  _T_66 = _GEN_672[31:3] == io_overlapReq_bits_paddr[31:3]; // @[Store_queue.scala 152:94]
  wire  _GEN_704 = ro_ptr_1 ? buff_1_fun_sc_w : buff_0_fun_sc_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_706 = ro_ptr_1 ? buff_1_fun_amoswap_w : buff_0_fun_amoswap_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_708 = ro_ptr_1 ? buff_1_fun_amoadd_w : buff_0_fun_amoadd_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_710 = ro_ptr_1 ? buff_1_fun_amoxor_w : buff_0_fun_amoxor_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_712 = ro_ptr_1 ? buff_1_fun_amoand_w : buff_0_fun_amoand_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_714 = ro_ptr_1 ? buff_1_fun_amoor_w : buff_0_fun_amoor_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_716 = ro_ptr_1 ? buff_1_fun_amomin_w : buff_0_fun_amomin_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_718 = ro_ptr_1 ? buff_1_fun_amomax_w : buff_0_fun_amomax_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_720 = ro_ptr_1 ? buff_1_fun_amominu_w : buff_0_fun_amominu_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_722 = ro_ptr_1 ? buff_1_fun_amomaxu_w : buff_0_fun_amomaxu_w; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_726 = ro_ptr_1 ? buff_1_fun_sc_d : buff_0_fun_sc_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_728 = ro_ptr_1 ? buff_1_fun_amoswap_d : buff_0_fun_amoswap_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_730 = ro_ptr_1 ? buff_1_fun_amoadd_d : buff_0_fun_amoadd_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_732 = ro_ptr_1 ? buff_1_fun_amoxor_d : buff_0_fun_amoxor_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_734 = ro_ptr_1 ? buff_1_fun_amoand_d : buff_0_fun_amoand_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_736 = ro_ptr_1 ? buff_1_fun_amoor_d : buff_0_fun_amoor_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_738 = ro_ptr_1 ? buff_1_fun_amomin_d : buff_0_fun_amomin_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_740 = ro_ptr_1 ? buff_1_fun_amomax_d : buff_0_fun_amomax_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_742 = ro_ptr_1 ? buff_1_fun_amominu_d : buff_0_fun_amominu_d; // @[Store_queue.scala 153:{27,27}]
  wire  _GEN_744 = ro_ptr_1 ? buff_1_fun_amomaxu_d : buff_0_fun_amomaxu_d; // @[Store_queue.scala 153:{27,27}]
  wire  _T_85 = _GEN_726 | _GEN_704; // @[riscv_isa.scala 140:20]
  wire  _T_86 = _GEN_706 | _GEN_708 | _GEN_710 | _GEN_712 | _GEN_714 | _GEN_716 | _GEN_718 | _GEN_720 | _GEN_722 |
    _GEN_728 | _GEN_730 | _GEN_732 | _GEN_734 | _GEN_736 | _GEN_738 | _GEN_740 | _GEN_742 | _GEN_744 | _T_85; // @[riscv_isa.scala 148:205]
  wire  _GEN_759 = _T_86 ? 1'h0 : _GEN_670; // @[Store_queue.scala 155:{43,66}]
  wire  _GEN_804 = (ro_ptr_1 >= rd_ptr | ro_ptr_1 < wr_ptr) & _GEN_672[31:3] == io_overlapReq_bits_paddr[31:3] ?
    _GEN_759 : _GEN_670; // @[Store_queue.scala 152:136]
  wire  _GEN_938 = _T_35 & _T_36 & _T_40 ? _GEN_625 : io_overlapReq_valid; // @[Store_queue.scala 165:134 146:26]
  wire  _GEN_1027 = _T_86 ? 1'h0 : _GEN_938; // @[Store_queue.scala 168:{43,66}]
  wire  _GEN_1072 = _T_61 & _T_62 & _T_66 ? _GEN_1027 : _GEN_938; // @[Store_queue.scala 165:134]
  wire  _GEN_14 = io_cmm_lsu_is_store_commit_0 & ~reset; // @[Store_queue.scala 129:13]
  wire  _GEN_43 = ~io_cmm_lsu_is_store_commit_0 & _T_1; // @[Store_queue.scala 133:13]
  wire  _GEN_45 = ~io_cmm_lsu_is_store_commit_0 & _T_1 & _T_9; // @[Store_queue.scala 133:13]
  assign io_enq_ready = ~full; // @[Store_queue.scala 89:19]
  assign io_deq_valid = ~emty; // @[Store_queue.scala 90:19]
  assign io_deq_bits_fun_lb = io_deq_valid & _GEN_47; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_lh = io_deq_valid & _GEN_48; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_lw = io_deq_valid & _GEN_49; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_ld = io_deq_valid & _GEN_50; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_lbu = io_deq_valid & _GEN_51; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_lhu = io_deq_valid & _GEN_52; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_lwu = io_deq_valid & _GEN_53; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_sb = io_deq_valid & _GEN_54; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_sh = io_deq_valid & _GEN_55; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_sw = io_deq_valid & _GEN_56; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_sd = io_deq_valid & _GEN_57; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_lr_w = io_deq_valid & _GEN_61; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_sc_w = io_deq_valid & _GEN_62; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoswap_w = io_deq_valid & _GEN_63; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoadd_w = io_deq_valid & _GEN_64; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoxor_w = io_deq_valid & _GEN_65; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoand_w = io_deq_valid & _GEN_66; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoor_w = io_deq_valid & _GEN_67; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amomin_w = io_deq_valid & _GEN_68; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amomax_w = io_deq_valid & _GEN_69; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amominu_w = io_deq_valid & _GEN_70; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amomaxu_w = io_deq_valid & _GEN_71; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_lr_d = io_deq_valid & _GEN_72; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_sc_d = io_deq_valid & _GEN_73; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoswap_d = io_deq_valid & _GEN_74; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoadd_d = io_deq_valid & _GEN_75; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoxor_d = io_deq_valid & _GEN_76; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoand_d = io_deq_valid & _GEN_77; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amoor_d = io_deq_valid & _GEN_78; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amomin_d = io_deq_valid & _GEN_79; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amomax_d = io_deq_valid & _GEN_80; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amominu_d = io_deq_valid & _GEN_81; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_amomaxu_d = io_deq_valid & _GEN_82; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_flw = io_deq_valid & _GEN_83; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_fsw = io_deq_valid & _GEN_84; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_fld = io_deq_valid & _GEN_85; // @[Store_queue.scala 92:21]
  assign io_deq_bits_fun_fsd = io_deq_valid & _GEN_86; // @[Store_queue.scala 92:21]
  assign io_deq_bits_param_dat_op1 = io_deq_valid ? _GEN_88 : 64'h0; // @[Store_queue.scala 92:21]
  assign io_is_empty = cm_ptr_reg == wr_ptr_reg & emty; // @[Store_queue.scala 141:48]
  assign io_overlapResp_valid = rd_ptr_reg[1] != wr_ptr_reg[1] ? _GEN_804 : _GEN_1072; // @[Store_queue.scala 148:51]
  always @(posedge clock) begin
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_lb <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_lb <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_lb <= _GEN_270;
      end
    end else begin
      buff_0_fun_lb <= _GEN_270;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_lh <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_lh <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_lh <= _GEN_272;
      end
    end else begin
      buff_0_fun_lh <= _GEN_272;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_lw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_lw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_lw <= _GEN_274;
      end
    end else begin
      buff_0_fun_lw <= _GEN_274;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_ld <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_ld <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_ld <= _GEN_276;
      end
    end else begin
      buff_0_fun_ld <= _GEN_276;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_lbu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_lbu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_lbu <= _GEN_278;
      end
    end else begin
      buff_0_fun_lbu <= _GEN_278;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_lhu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_lhu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_lhu <= _GEN_280;
      end
    end else begin
      buff_0_fun_lhu <= _GEN_280;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_lwu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_lwu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_lwu <= _GEN_282;
      end
    end else begin
      buff_0_fun_lwu <= _GEN_282;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_sb <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_sb <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_sb <= _GEN_284;
      end
    end else begin
      buff_0_fun_sb <= _GEN_284;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_sh <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_sh <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_sh <= _GEN_286;
      end
    end else begin
      buff_0_fun_sh <= _GEN_286;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_sw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_sw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_sw <= _GEN_288;
      end
    end else begin
      buff_0_fun_sw <= _GEN_288;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_sd <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_sd <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_sd <= _GEN_290;
      end
    end else begin
      buff_0_fun_sd <= _GEN_290;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_lr_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_lr_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_lr_w <= _GEN_298;
      end
    end else begin
      buff_0_fun_lr_w <= _GEN_298;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_sc_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_sc_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_sc_w <= _GEN_300;
      end
    end else begin
      buff_0_fun_sc_w <= _GEN_300;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoswap_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoswap_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoswap_w <= _GEN_302;
      end
    end else begin
      buff_0_fun_amoswap_w <= _GEN_302;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoadd_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoadd_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoadd_w <= _GEN_304;
      end
    end else begin
      buff_0_fun_amoadd_w <= _GEN_304;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoxor_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoxor_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoxor_w <= _GEN_306;
      end
    end else begin
      buff_0_fun_amoxor_w <= _GEN_306;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoand_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoand_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoand_w <= _GEN_308;
      end
    end else begin
      buff_0_fun_amoand_w <= _GEN_308;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoor_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoor_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoor_w <= _GEN_310;
      end
    end else begin
      buff_0_fun_amoor_w <= _GEN_310;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amomin_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amomin_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amomin_w <= _GEN_312;
      end
    end else begin
      buff_0_fun_amomin_w <= _GEN_312;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amomax_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amomax_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amomax_w <= _GEN_314;
      end
    end else begin
      buff_0_fun_amomax_w <= _GEN_314;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amominu_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amominu_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amominu_w <= _GEN_316;
      end
    end else begin
      buff_0_fun_amominu_w <= _GEN_316;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amomaxu_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amomaxu_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amomaxu_w <= _GEN_318;
      end
    end else begin
      buff_0_fun_amomaxu_w <= _GEN_318;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_lr_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_lr_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_lr_d <= _GEN_320;
      end
    end else begin
      buff_0_fun_lr_d <= _GEN_320;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_sc_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_sc_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_sc_d <= _GEN_322;
      end
    end else begin
      buff_0_fun_sc_d <= _GEN_322;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoswap_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoswap_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoswap_d <= _GEN_324;
      end
    end else begin
      buff_0_fun_amoswap_d <= _GEN_324;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoadd_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoadd_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoadd_d <= _GEN_326;
      end
    end else begin
      buff_0_fun_amoadd_d <= _GEN_326;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoxor_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoxor_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoxor_d <= _GEN_328;
      end
    end else begin
      buff_0_fun_amoxor_d <= _GEN_328;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoand_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoand_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoand_d <= _GEN_330;
      end
    end else begin
      buff_0_fun_amoand_d <= _GEN_330;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amoor_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amoor_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amoor_d <= _GEN_332;
      end
    end else begin
      buff_0_fun_amoor_d <= _GEN_332;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amomin_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amomin_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amomin_d <= _GEN_334;
      end
    end else begin
      buff_0_fun_amomin_d <= _GEN_334;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amomax_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amomax_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amomax_d <= _GEN_336;
      end
    end else begin
      buff_0_fun_amomax_d <= _GEN_336;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amominu_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amominu_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amominu_d <= _GEN_338;
      end
    end else begin
      buff_0_fun_amominu_d <= _GEN_338;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_amomaxu_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_amomaxu_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_amomaxu_d <= _GEN_340;
      end
    end else begin
      buff_0_fun_amomaxu_d <= _GEN_340;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_flw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_flw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_flw <= _GEN_342;
      end
    end else begin
      buff_0_fun_flw <= _GEN_342;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_fsw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_fsw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_fsw <= _GEN_344;
      end
    end else begin
      buff_0_fun_fsw <= _GEN_344;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_fld <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_fld <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_fld <= _GEN_346;
      end
    end else begin
      buff_0_fun_fld <= _GEN_346;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_fun_fsd <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_fun_fsd <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_fun_fsd <= _GEN_348;
      end
    end else begin
      buff_0_fun_fsd <= _GEN_348;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_0_param_dat_op1 <= 64'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (~rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_0_param_dat_op1 <= 64'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_0_param_dat_op1 <= _GEN_352;
      end
    end else begin
      buff_0_param_dat_op1 <= _GEN_352;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_lb <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_lb <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_lb <= _GEN_271;
      end
    end else begin
      buff_1_fun_lb <= _GEN_271;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_lh <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_lh <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_lh <= _GEN_273;
      end
    end else begin
      buff_1_fun_lh <= _GEN_273;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_lw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_lw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_lw <= _GEN_275;
      end
    end else begin
      buff_1_fun_lw <= _GEN_275;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_ld <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_ld <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_ld <= _GEN_277;
      end
    end else begin
      buff_1_fun_ld <= _GEN_277;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_lbu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_lbu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_lbu <= _GEN_279;
      end
    end else begin
      buff_1_fun_lbu <= _GEN_279;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_lhu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_lhu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_lhu <= _GEN_281;
      end
    end else begin
      buff_1_fun_lhu <= _GEN_281;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_lwu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_lwu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_lwu <= _GEN_283;
      end
    end else begin
      buff_1_fun_lwu <= _GEN_283;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_sb <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_sb <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_sb <= _GEN_285;
      end
    end else begin
      buff_1_fun_sb <= _GEN_285;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_sh <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_sh <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_sh <= _GEN_287;
      end
    end else begin
      buff_1_fun_sh <= _GEN_287;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_sw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_sw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_sw <= _GEN_289;
      end
    end else begin
      buff_1_fun_sw <= _GEN_289;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_sd <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_sd <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_sd <= _GEN_291;
      end
    end else begin
      buff_1_fun_sd <= _GEN_291;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_lr_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_lr_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_lr_w <= _GEN_299;
      end
    end else begin
      buff_1_fun_lr_w <= _GEN_299;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_sc_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_sc_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_sc_w <= _GEN_301;
      end
    end else begin
      buff_1_fun_sc_w <= _GEN_301;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoswap_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoswap_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoswap_w <= _GEN_303;
      end
    end else begin
      buff_1_fun_amoswap_w <= _GEN_303;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoadd_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoadd_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoadd_w <= _GEN_305;
      end
    end else begin
      buff_1_fun_amoadd_w <= _GEN_305;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoxor_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoxor_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoxor_w <= _GEN_307;
      end
    end else begin
      buff_1_fun_amoxor_w <= _GEN_307;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoand_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoand_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoand_w <= _GEN_309;
      end
    end else begin
      buff_1_fun_amoand_w <= _GEN_309;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoor_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoor_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoor_w <= _GEN_311;
      end
    end else begin
      buff_1_fun_amoor_w <= _GEN_311;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amomin_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amomin_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amomin_w <= _GEN_313;
      end
    end else begin
      buff_1_fun_amomin_w <= _GEN_313;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amomax_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amomax_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amomax_w <= _GEN_315;
      end
    end else begin
      buff_1_fun_amomax_w <= _GEN_315;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amominu_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amominu_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amominu_w <= _GEN_317;
      end
    end else begin
      buff_1_fun_amominu_w <= _GEN_317;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amomaxu_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amomaxu_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amomaxu_w <= _GEN_319;
      end
    end else begin
      buff_1_fun_amomaxu_w <= _GEN_319;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_lr_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_lr_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_lr_d <= _GEN_321;
      end
    end else begin
      buff_1_fun_lr_d <= _GEN_321;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_sc_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_sc_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_sc_d <= _GEN_323;
      end
    end else begin
      buff_1_fun_sc_d <= _GEN_323;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoswap_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoswap_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoswap_d <= _GEN_325;
      end
    end else begin
      buff_1_fun_amoswap_d <= _GEN_325;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoadd_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoadd_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoadd_d <= _GEN_327;
      end
    end else begin
      buff_1_fun_amoadd_d <= _GEN_327;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoxor_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoxor_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoxor_d <= _GEN_329;
      end
    end else begin
      buff_1_fun_amoxor_d <= _GEN_329;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoand_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoand_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoand_d <= _GEN_331;
      end
    end else begin
      buff_1_fun_amoand_d <= _GEN_331;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amoor_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amoor_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amoor_d <= _GEN_333;
      end
    end else begin
      buff_1_fun_amoor_d <= _GEN_333;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amomin_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amomin_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amomin_d <= _GEN_335;
      end
    end else begin
      buff_1_fun_amomin_d <= _GEN_335;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amomax_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amomax_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amomax_d <= _GEN_337;
      end
    end else begin
      buff_1_fun_amomax_d <= _GEN_337;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amominu_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amominu_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amominu_d <= _GEN_339;
      end
    end else begin
      buff_1_fun_amominu_d <= _GEN_339;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_amomaxu_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_amomaxu_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_amomaxu_d <= _GEN_341;
      end
    end else begin
      buff_1_fun_amomaxu_d <= _GEN_341;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_flw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_flw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_flw <= _GEN_343;
      end
    end else begin
      buff_1_fun_flw <= _GEN_343;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_fsw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_fsw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_fsw <= _GEN_345;
      end
    end else begin
      buff_1_fun_fsw <= _GEN_345;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_fld <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_fld <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_fld <= _GEN_347;
      end
    end else begin
      buff_1_fun_fld <= _GEN_347;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_fun_fsd <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_fun_fsd <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_fun_fsd <= _GEN_349;
      end
    end else begin
      buff_1_fun_fsd <= _GEN_349;
    end
    if (reset) begin // @[Store_queue.scala 54:21]
      buff_1_param_dat_op1 <= 64'h0; // @[Store_queue.scala 54:21]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      if (rd_ptr) begin // @[Store_queue.scala 113:18]
        buff_1_param_dat_op1 <= 64'h0; // @[Store_queue.scala 113:18]
      end else begin
        buff_1_param_dat_op1 <= _GEN_353;
      end
    end else begin
      buff_1_param_dat_op1 <= _GEN_353;
    end
    if (reset) begin // @[Store_queue.scala 56:27]
      cm_ptr_reg <= 2'h0; // @[Store_queue.scala 56:27]
    end else if (io_cmm_lsu_is_store_commit_0) begin // @[Store_queue.scala 127:31]
      cm_ptr_reg <= _wr_ptr_reg_T_1; // @[Store_queue.scala 128:18]
    end else if (_T_1) begin // @[Store_queue.scala 131:44]
      cm_ptr_reg <= _wr_ptr_reg_T_1; // @[Store_queue.scala 132:18]
    end
    if (reset) begin // @[Store_queue.scala 57:27]
      wr_ptr_reg <= 2'h0; // @[Store_queue.scala 57:27]
    end else if (io_flush) begin // @[Store_queue.scala 94:20]
      if (io_cmm_lsu_is_store_commit_0 | _T_1) begin // @[Store_queue.scala 100:59]
        wr_ptr_reg <= _wr_ptr_reg_T_1; // @[Store_queue.scala 100:72]
      end else begin
        wr_ptr_reg <= cm_ptr_reg; // @[Store_queue.scala 101:30]
      end
    end else if (_T_5) begin // @[Store_queue.scala 106:30]
      wr_ptr_reg <= _wr_ptr_reg_T_3; // @[Store_queue.scala 108:16]
    end
    if (reset) begin // @[Store_queue.scala 58:27]
      rd_ptr_reg <= 2'h0; // @[Store_queue.scala 58:27]
    end else if (_T_6) begin // @[Store_queue.scala 111:23]
      rd_ptr_reg <= _rd_ptr_reg_T_1; // @[Store_queue.scala 112:16]
    end
    if (reset) begin // @[Store_queue.scala 69:23]
      is_amo <= 1'h0; // @[Store_queue.scala 69:23]
    end else if (io_flush) begin // @[Store_queue.scala 78:22]
      is_amo <= 1'h0; // @[Store_queue.scala 79:14]
    end else begin
      is_amo <= _GEN_1;
    end
    if (reset) begin // @[Store_queue.scala 76:29]
      is_amo_pre <= 1'h0; // @[Store_queue.scala 76:29]
    end else begin
      is_amo_pre <= io_cmm_lsu_is_amo_pending; // @[Store_queue.scala 76:29]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_cmm_lsu_is_store_commit_0 & ~reset & ~(~is_amo)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:129 assert( ~is_amo )\n"); // @[Store_queue.scala 129:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~is_amo) & (io_cmm_lsu_is_store_commit_0 & ~reset)) begin
          $fatal; // @[Store_queue.scala 129:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_14 & ~(cm_ptr_reg != wr_ptr_reg)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:130 assert( cm_ptr_reg =/= wr_ptr_reg )\n"); // @[Store_queue.scala 130:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(cm_ptr_reg != wr_ptr_reg) & (io_cmm_lsu_is_store_commit_0 & _T_9)) begin
          $fatal; // @[Store_queue.scala 130:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~io_cmm_lsu_is_store_commit_0 & _T_1 & _T_9 & ~(~(io_cmm_lsu_is_store_commit_0 & _T_1))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, is_amo only launch at chn 0!\n\n    at Store_queue.scala:133 assert( ~((is_st_commited(0)) & (is_amo & ~io.is_empty)), \"Assert Failed, is_amo only launch at chn 0!\\n\" )\n"
            ); // @[Store_queue.scala 133:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_cmm_lsu_is_store_commit_0 & _T_1)) & (~io_cmm_lsu_is_store_commit_0 & _T_1 & _T_9)) begin
          $fatal; // @[Store_queue.scala 133:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_45 & _T_14) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:134 assert( cm_ptr_reg =/= wr_ptr_reg )\n"); // @[Store_queue.scala 134:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_11 & (_GEN_43 & _T_9)) begin
          $fatal; // @[Store_queue.scala 134:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_30 & _T_9 & ~(rd_ptr >= wr_ptr)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:149 assert( rd_ptr >= wr_ptr )\n"); // @[Store_queue.scala 149:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(rd_ptr >= wr_ptr) & (_T_30 & _T_9)) begin
          $fatal; // @[Store_queue.scala 149:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_30 & _T_9 & ~(rd_ptr <= wr_ptr)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:162 assert( rd_ptr <= wr_ptr )\n"); // @[Store_queue.scala 162:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(rd_ptr <= wr_ptr) & (~_T_30 & _T_9)) begin
          $fatal; // @[Store_queue.scala 162:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  buff_0_fun_lb = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buff_0_fun_lh = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  buff_0_fun_lw = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  buff_0_fun_ld = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  buff_0_fun_lbu = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  buff_0_fun_lhu = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  buff_0_fun_lwu = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  buff_0_fun_sb = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  buff_0_fun_sh = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  buff_0_fun_sw = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  buff_0_fun_sd = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  buff_0_fun_lr_w = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  buff_0_fun_sc_w = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  buff_0_fun_amoswap_w = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  buff_0_fun_amoadd_w = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  buff_0_fun_amoxor_w = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  buff_0_fun_amoand_w = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  buff_0_fun_amoor_w = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  buff_0_fun_amomin_w = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  buff_0_fun_amomax_w = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  buff_0_fun_amominu_w = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  buff_0_fun_amomaxu_w = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  buff_0_fun_lr_d = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  buff_0_fun_sc_d = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  buff_0_fun_amoswap_d = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  buff_0_fun_amoadd_d = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  buff_0_fun_amoxor_d = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  buff_0_fun_amoand_d = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  buff_0_fun_amoor_d = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  buff_0_fun_amomin_d = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  buff_0_fun_amomax_d = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  buff_0_fun_amominu_d = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  buff_0_fun_amomaxu_d = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  buff_0_fun_flw = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  buff_0_fun_fsw = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  buff_0_fun_fld = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  buff_0_fun_fsd = _RAND_36[0:0];
  _RAND_37 = {2{`RANDOM}};
  buff_0_param_dat_op1 = _RAND_37[63:0];
  _RAND_38 = {1{`RANDOM}};
  buff_1_fun_lb = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  buff_1_fun_lh = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  buff_1_fun_lw = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  buff_1_fun_ld = _RAND_41[0:0];
  _RAND_42 = {1{`RANDOM}};
  buff_1_fun_lbu = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  buff_1_fun_lhu = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  buff_1_fun_lwu = _RAND_44[0:0];
  _RAND_45 = {1{`RANDOM}};
  buff_1_fun_sb = _RAND_45[0:0];
  _RAND_46 = {1{`RANDOM}};
  buff_1_fun_sh = _RAND_46[0:0];
  _RAND_47 = {1{`RANDOM}};
  buff_1_fun_sw = _RAND_47[0:0];
  _RAND_48 = {1{`RANDOM}};
  buff_1_fun_sd = _RAND_48[0:0];
  _RAND_49 = {1{`RANDOM}};
  buff_1_fun_lr_w = _RAND_49[0:0];
  _RAND_50 = {1{`RANDOM}};
  buff_1_fun_sc_w = _RAND_50[0:0];
  _RAND_51 = {1{`RANDOM}};
  buff_1_fun_amoswap_w = _RAND_51[0:0];
  _RAND_52 = {1{`RANDOM}};
  buff_1_fun_amoadd_w = _RAND_52[0:0];
  _RAND_53 = {1{`RANDOM}};
  buff_1_fun_amoxor_w = _RAND_53[0:0];
  _RAND_54 = {1{`RANDOM}};
  buff_1_fun_amoand_w = _RAND_54[0:0];
  _RAND_55 = {1{`RANDOM}};
  buff_1_fun_amoor_w = _RAND_55[0:0];
  _RAND_56 = {1{`RANDOM}};
  buff_1_fun_amomin_w = _RAND_56[0:0];
  _RAND_57 = {1{`RANDOM}};
  buff_1_fun_amomax_w = _RAND_57[0:0];
  _RAND_58 = {1{`RANDOM}};
  buff_1_fun_amominu_w = _RAND_58[0:0];
  _RAND_59 = {1{`RANDOM}};
  buff_1_fun_amomaxu_w = _RAND_59[0:0];
  _RAND_60 = {1{`RANDOM}};
  buff_1_fun_lr_d = _RAND_60[0:0];
  _RAND_61 = {1{`RANDOM}};
  buff_1_fun_sc_d = _RAND_61[0:0];
  _RAND_62 = {1{`RANDOM}};
  buff_1_fun_amoswap_d = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  buff_1_fun_amoadd_d = _RAND_63[0:0];
  _RAND_64 = {1{`RANDOM}};
  buff_1_fun_amoxor_d = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  buff_1_fun_amoand_d = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  buff_1_fun_amoor_d = _RAND_66[0:0];
  _RAND_67 = {1{`RANDOM}};
  buff_1_fun_amomin_d = _RAND_67[0:0];
  _RAND_68 = {1{`RANDOM}};
  buff_1_fun_amomax_d = _RAND_68[0:0];
  _RAND_69 = {1{`RANDOM}};
  buff_1_fun_amominu_d = _RAND_69[0:0];
  _RAND_70 = {1{`RANDOM}};
  buff_1_fun_amomaxu_d = _RAND_70[0:0];
  _RAND_71 = {1{`RANDOM}};
  buff_1_fun_flw = _RAND_71[0:0];
  _RAND_72 = {1{`RANDOM}};
  buff_1_fun_fsw = _RAND_72[0:0];
  _RAND_73 = {1{`RANDOM}};
  buff_1_fun_fld = _RAND_73[0:0];
  _RAND_74 = {1{`RANDOM}};
  buff_1_fun_fsd = _RAND_74[0:0];
  _RAND_75 = {2{`RANDOM}};
  buff_1_param_dat_op1 = _RAND_75[63:0];
  _RAND_76 = {1{`RANDOM}};
  cm_ptr_reg = _RAND_76[1:0];
  _RAND_77 = {1{`RANDOM}};
  wr_ptr_reg = _RAND_77[1:0];
  _RAND_78 = {1{`RANDOM}};
  rd_ptr_reg = _RAND_78[1:0];
  _RAND_79 = {1{`RANDOM}};
  is_amo = _RAND_79[0:0];
  _RAND_80 = {1{`RANDOM}};
  is_amo_pre = _RAND_80[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Arbiter(
  input         io_in_0_valid,
  input         io_in_0_bits_fun_lb,
  input         io_in_0_bits_fun_lh,
  input         io_in_0_bits_fun_lw,
  input         io_in_0_bits_fun_ld,
  input         io_in_0_bits_fun_lbu,
  input         io_in_0_bits_fun_lhu,
  input         io_in_0_bits_fun_lwu,
  input         io_in_0_bits_fun_sb,
  input         io_in_0_bits_fun_sh,
  input         io_in_0_bits_fun_sw,
  input         io_in_0_bits_fun_sd,
  input         io_in_0_bits_fun_lr_w,
  input         io_in_0_bits_fun_sc_w,
  input         io_in_0_bits_fun_amoswap_w,
  input         io_in_0_bits_fun_amoadd_w,
  input         io_in_0_bits_fun_amoxor_w,
  input         io_in_0_bits_fun_amoand_w,
  input         io_in_0_bits_fun_amoor_w,
  input         io_in_0_bits_fun_amomin_w,
  input         io_in_0_bits_fun_amomax_w,
  input         io_in_0_bits_fun_amominu_w,
  input         io_in_0_bits_fun_amomaxu_w,
  input         io_in_0_bits_fun_lr_d,
  input         io_in_0_bits_fun_sc_d,
  input         io_in_0_bits_fun_amoswap_d,
  input         io_in_0_bits_fun_amoadd_d,
  input         io_in_0_bits_fun_amoxor_d,
  input         io_in_0_bits_fun_amoand_d,
  input         io_in_0_bits_fun_amoor_d,
  input         io_in_0_bits_fun_amomin_d,
  input         io_in_0_bits_fun_amomax_d,
  input         io_in_0_bits_fun_amominu_d,
  input         io_in_0_bits_fun_amomaxu_d,
  input         io_in_0_bits_fun_flw,
  input         io_in_0_bits_fun_fsw,
  input         io_in_0_bits_fun_fld,
  input         io_in_0_bits_fun_fsd,
  input  [63:0] io_in_0_bits_param_dat_op1,
  output        io_in_1_ready,
  input         io_in_1_valid,
  input         io_in_1_bits_fun_lb,
  input         io_in_1_bits_fun_lh,
  input         io_in_1_bits_fun_lw,
  input         io_in_1_bits_fun_ld,
  input         io_in_1_bits_fun_lbu,
  input         io_in_1_bits_fun_lhu,
  input         io_in_1_bits_fun_lwu,
  input         io_in_1_bits_fun_sb,
  input         io_in_1_bits_fun_sh,
  input         io_in_1_bits_fun_sw,
  input         io_in_1_bits_fun_sd,
  input         io_in_1_bits_fun_lr_w,
  input         io_in_1_bits_fun_sc_w,
  input         io_in_1_bits_fun_amoswap_w,
  input         io_in_1_bits_fun_amoadd_w,
  input         io_in_1_bits_fun_amoxor_w,
  input         io_in_1_bits_fun_amoand_w,
  input         io_in_1_bits_fun_amoor_w,
  input         io_in_1_bits_fun_amomin_w,
  input         io_in_1_bits_fun_amomax_w,
  input         io_in_1_bits_fun_amominu_w,
  input         io_in_1_bits_fun_amomaxu_w,
  input         io_in_1_bits_fun_lr_d,
  input         io_in_1_bits_fun_sc_d,
  input         io_in_1_bits_fun_amoswap_d,
  input         io_in_1_bits_fun_amoadd_d,
  input         io_in_1_bits_fun_amoxor_d,
  input         io_in_1_bits_fun_amoand_d,
  input         io_in_1_bits_fun_amoor_d,
  input         io_in_1_bits_fun_amomin_d,
  input         io_in_1_bits_fun_amomax_d,
  input         io_in_1_bits_fun_amominu_d,
  input         io_in_1_bits_fun_amomaxu_d,
  input         io_in_1_bits_fun_flw,
  input         io_in_1_bits_fun_fsw,
  input         io_in_1_bits_fun_fld,
  input         io_in_1_bits_fun_fsd,
  input  [63:0] io_in_1_bits_param_dat_op1,
  input         io_out_ready,
  output        io_out_valid,
  output        io_out_bits_fun_lb,
  output        io_out_bits_fun_lh,
  output        io_out_bits_fun_lw,
  output        io_out_bits_fun_ld,
  output        io_out_bits_fun_lbu,
  output        io_out_bits_fun_lhu,
  output        io_out_bits_fun_lwu,
  output        io_out_bits_fun_sb,
  output        io_out_bits_fun_sh,
  output        io_out_bits_fun_sw,
  output        io_out_bits_fun_sd,
  output        io_out_bits_fun_lr_w,
  output        io_out_bits_fun_sc_w,
  output        io_out_bits_fun_amoswap_w,
  output        io_out_bits_fun_amoadd_w,
  output        io_out_bits_fun_amoxor_w,
  output        io_out_bits_fun_amoand_w,
  output        io_out_bits_fun_amoor_w,
  output        io_out_bits_fun_amomin_w,
  output        io_out_bits_fun_amomax_w,
  output        io_out_bits_fun_amominu_w,
  output        io_out_bits_fun_amomaxu_w,
  output        io_out_bits_fun_lr_d,
  output        io_out_bits_fun_sc_d,
  output        io_out_bits_fun_amoswap_d,
  output        io_out_bits_fun_amoadd_d,
  output        io_out_bits_fun_amoxor_d,
  output        io_out_bits_fun_amoand_d,
  output        io_out_bits_fun_amoor_d,
  output        io_out_bits_fun_amomin_d,
  output        io_out_bits_fun_amomax_d,
  output        io_out_bits_fun_amominu_d,
  output        io_out_bits_fun_amomaxu_d,
  output        io_out_bits_fun_flw,
  output        io_out_bits_fun_fsw,
  output        io_out_bits_fun_fld,
  output        io_out_bits_fun_fsd,
  output [63:0] io_out_bits_param_dat_op1
);
  wire  grant_1 = ~io_in_0_valid; // @[Arbiter.scala 45:78]
  assign io_in_1_ready = grant_1 & io_out_ready; // @[Arbiter.scala 146:19]
  assign io_out_valid = ~grant_1 | io_in_1_valid; // @[Arbiter.scala 147:31]
  assign io_out_bits_fun_lb = io_in_0_valid ? io_in_0_bits_fun_lb : io_in_1_bits_fun_lb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lh = io_in_0_valid ? io_in_0_bits_fun_lh : io_in_1_bits_fun_lh; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lw = io_in_0_valid ? io_in_0_bits_fun_lw : io_in_1_bits_fun_lw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_ld = io_in_0_valid ? io_in_0_bits_fun_ld : io_in_1_bits_fun_ld; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lbu = io_in_0_valid ? io_in_0_bits_fun_lbu : io_in_1_bits_fun_lbu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lhu = io_in_0_valid ? io_in_0_bits_fun_lhu : io_in_1_bits_fun_lhu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lwu = io_in_0_valid ? io_in_0_bits_fun_lwu : io_in_1_bits_fun_lwu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sb = io_in_0_valid ? io_in_0_bits_fun_sb : io_in_1_bits_fun_sb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sh = io_in_0_valid ? io_in_0_bits_fun_sh : io_in_1_bits_fun_sh; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sw = io_in_0_valid ? io_in_0_bits_fun_sw : io_in_1_bits_fun_sw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sd = io_in_0_valid ? io_in_0_bits_fun_sd : io_in_1_bits_fun_sd; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lr_w = io_in_0_valid ? io_in_0_bits_fun_lr_w : io_in_1_bits_fun_lr_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sc_w = io_in_0_valid ? io_in_0_bits_fun_sc_w : io_in_1_bits_fun_sc_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoswap_w = io_in_0_valid ? io_in_0_bits_fun_amoswap_w : io_in_1_bits_fun_amoswap_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoadd_w = io_in_0_valid ? io_in_0_bits_fun_amoadd_w : io_in_1_bits_fun_amoadd_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoxor_w = io_in_0_valid ? io_in_0_bits_fun_amoxor_w : io_in_1_bits_fun_amoxor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoand_w = io_in_0_valid ? io_in_0_bits_fun_amoand_w : io_in_1_bits_fun_amoand_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoor_w = io_in_0_valid ? io_in_0_bits_fun_amoor_w : io_in_1_bits_fun_amoor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomin_w = io_in_0_valid ? io_in_0_bits_fun_amomin_w : io_in_1_bits_fun_amomin_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomax_w = io_in_0_valid ? io_in_0_bits_fun_amomax_w : io_in_1_bits_fun_amomax_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amominu_w = io_in_0_valid ? io_in_0_bits_fun_amominu_w : io_in_1_bits_fun_amominu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomaxu_w = io_in_0_valid ? io_in_0_bits_fun_amomaxu_w : io_in_1_bits_fun_amomaxu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lr_d = io_in_0_valid ? io_in_0_bits_fun_lr_d : io_in_1_bits_fun_lr_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sc_d = io_in_0_valid ? io_in_0_bits_fun_sc_d : io_in_1_bits_fun_sc_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoswap_d = io_in_0_valid ? io_in_0_bits_fun_amoswap_d : io_in_1_bits_fun_amoswap_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoadd_d = io_in_0_valid ? io_in_0_bits_fun_amoadd_d : io_in_1_bits_fun_amoadd_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoxor_d = io_in_0_valid ? io_in_0_bits_fun_amoxor_d : io_in_1_bits_fun_amoxor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoand_d = io_in_0_valid ? io_in_0_bits_fun_amoand_d : io_in_1_bits_fun_amoand_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoor_d = io_in_0_valid ? io_in_0_bits_fun_amoor_d : io_in_1_bits_fun_amoor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomin_d = io_in_0_valid ? io_in_0_bits_fun_amomin_d : io_in_1_bits_fun_amomin_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomax_d = io_in_0_valid ? io_in_0_bits_fun_amomax_d : io_in_1_bits_fun_amomax_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amominu_d = io_in_0_valid ? io_in_0_bits_fun_amominu_d : io_in_1_bits_fun_amominu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomaxu_d = io_in_0_valid ? io_in_0_bits_fun_amomaxu_d : io_in_1_bits_fun_amomaxu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_flw = io_in_0_valid ? io_in_0_bits_fun_flw : io_in_1_bits_fun_flw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_fsw = io_in_0_valid ? io_in_0_bits_fun_fsw : io_in_1_bits_fun_fsw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_fld = io_in_0_valid ? io_in_0_bits_fun_fld : io_in_1_bits_fun_fld; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_fsd = io_in_0_valid ? io_in_0_bits_fun_fsd : io_in_1_bits_fun_fsd; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_param_dat_op1 = io_in_0_valid ? io_in_0_bits_param_dat_op1 : io_in_1_bits_param_dat_op1; // @[Arbiter.scala 136:15 138:26 140:19]
endmodule
module IO_Lsu(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input        io_enq_bits_fun_lb,
  input        io_enq_bits_fun_lh,
  input        io_enq_bits_fun_lw,
  input        io_enq_bits_fun_ld,
  input        io_enq_bits_fun_lbu,
  input        io_enq_bits_fun_lhu,
  input        io_enq_bits_fun_lwu,
  input        io_enq_bits_fun_sb,
  input        io_enq_bits_fun_sh,
  input        io_enq_bits_fun_sw,
  input        io_enq_bits_fun_sd,
  input        io_enq_bits_fun_lr_w,
  input        io_enq_bits_fun_sc_w,
  input        io_enq_bits_fun_lr_d,
  input        io_enq_bits_fun_sc_d,
  input        io_enq_bits_fun_flw,
  input        io_enq_bits_fun_fsw,
  input        io_enq_bits_fun_fld,
  input        io_enq_bits_fun_fsd,
  input        io_deq_ready,
  output       io_deq_valid,
  output       io_deq_bits_is_load_amo,
  output       io_deq_bits_is_flw,
  output       io_deq_bits_is_fld,
  output       io_is_empty,
  input        io_getPut_ready,
  output       io_getPut_valid,
  output       io_access_ready,
  input        io_access_valid,
  input  [2:0] io_access_bits_opcode
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
`endif // RANDOMIZE_REG_INIT
  reg  is_busy; // @[IO_Lsu.scala 45:27]
  reg  isTransing; // @[IO_Lsu.scala 46:27]
  reg  pending_fun_lb; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_lh; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_lw; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_ld; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_lbu; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_lhu; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_lwu; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_sb; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_sh; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_sw; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_sd; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_lr_w; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_sc_w; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_lr_d; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_sc_d; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_flw; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_fsw; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_fld; // @[IO_Lsu.scala 47:20]
  reg  pending_fun_fsd; // @[IO_Lsu.scala 47:20]
  wire  _io_is_empty_T = ~is_busy; // @[IO_Lsu.scala 49:18]
  wire  _io_getPut_valid_T = ~isTransing; // @[IO_Lsu.scala 51:32]
  wire  _T_8 = pending_fun_lr_d | pending_fun_lr_w; // @[riscv_isa.scala 141:20]
  wire  _T_9 = pending_fun_lb | pending_fun_lh | pending_fun_lw | pending_fun_ld | pending_fun_lbu | pending_fun_lhu |
    pending_fun_lwu | pending_fun_flw | pending_fun_fld | _T_8; // @[riscv_isa.scala 143:65]
  wire  _T_12 = _T_9 & ~_T_8; // @[IO_Lsu.scala 55:29]
  wire  _T_17 = pending_fun_sb | pending_fun_sh | pending_fun_sw | pending_fun_sd | pending_fun_fsw | pending_fun_fsd; // @[riscv_isa.scala 144:40]
  wire  _T_18 = pending_fun_sc_d | pending_fun_sc_w; // @[riscv_isa.scala 140:20]
  wire  _T_20 = _T_17 & ~_T_18; // @[IO_Lsu.scala 62:38]
  wire  _T_22 = ~reset; // @[IO_Lsu.scala 73:15]
  wire  _T_24 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_33 = io_getPut_ready & io_getPut_valid; // @[Decoupled.scala 52:35]
  wire  _T_34 = io_access_ready & io_access_valid; // @[Decoupled.scala 52:35]
  wire  _T_35 = _T_33 & _T_34; // @[IO_Lsu.scala 89:31]
  wire  _GEN_24 = _T_34 ? 1'h0 : is_busy; // @[IO_Lsu.scala 96:32 98:13 45:27]
  wire  _GEN_25 = _T_34 ? 1'h0 : isTransing; // @[IO_Lsu.scala 96:32 99:16 46:27]
  wire  _GEN_26 = _T_33 | _GEN_25; // @[IO_Lsu.scala 93:33 95:16]
  wire  _GEN_27 = _T_33 ? is_busy : _GEN_24; // @[IO_Lsu.scala 45:27 93:33]
  wire  _GEN_28 = _T_33 & _T_34 ? 1'h0 : _GEN_27; // @[IO_Lsu.scala 89:50 90:13]
  wire  _GEN_74 = _T_24 | _GEN_28; // @[IO_Lsu.scala 84:23 88:13]
  wire  _GEN_8 = _T_24 & _T_22; // @[IO_Lsu.scala 85:11]
  wire  _GEN_10 = ~_T_24; // @[IO_Lsu.scala 92:11]
  wire  _GEN_14 = _GEN_10 & ~_T_35; // @[IO_Lsu.scala 94:11]
  assign io_enq_ready = ~is_busy; // @[IO_Lsu.scala 53:19]
  assign io_deq_valid = io_access_valid; // @[IO_Lsu.scala 102:19]
  assign io_deq_bits_is_load_amo = io_access_bits_opcode == 3'h1; // @[IO_Lsu.scala 121:53]
  assign io_deq_bits_is_flw = io_deq_valid & pending_fun_flw; // @[IO_Lsu.scala 125:28]
  assign io_deq_bits_is_fld = io_deq_valid & pending_fun_fld; // @[IO_Lsu.scala 126:28]
  assign io_is_empty = ~is_busy; // @[IO_Lsu.scala 49:18]
  assign io_getPut_valid = is_busy & ~isTransing; // @[IO_Lsu.scala 51:30]
  assign io_access_ready = io_deq_ready; // @[IO_Lsu.scala 129:19]
  always @(posedge clock) begin
    if (reset) begin // @[IO_Lsu.scala 45:27]
      is_busy <= 1'h0; // @[IO_Lsu.scala 45:27]
    end else begin
      is_busy <= _GEN_74;
    end
    if (reset) begin // @[IO_Lsu.scala 46:27]
      isTransing <= 1'h0; // @[IO_Lsu.scala 46:27]
    end else if (!(_T_24)) begin // @[IO_Lsu.scala 84:23]
      if (_T_33 & _T_34) begin // @[IO_Lsu.scala 89:50]
        isTransing <= 1'h0; // @[IO_Lsu.scala 91:16]
      end else begin
        isTransing <= _GEN_26;
      end
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_lb <= io_enq_bits_fun_lb; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_lh <= io_enq_bits_fun_lh; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_lw <= io_enq_bits_fun_lw; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_ld <= io_enq_bits_fun_ld; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_lbu <= io_enq_bits_fun_lbu; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_lhu <= io_enq_bits_fun_lhu; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_lwu <= io_enq_bits_fun_lwu; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_sb <= io_enq_bits_fun_sb; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_sh <= io_enq_bits_fun_sh; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_sw <= io_enq_bits_fun_sw; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_sd <= io_enq_bits_fun_sd; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_lr_w <= io_enq_bits_fun_lr_w; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_sc_w <= io_enq_bits_fun_sc_w; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_lr_d <= io_enq_bits_fun_lr_d; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_sc_d <= io_enq_bits_fun_sc_d; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_flw <= io_enq_bits_fun_flw; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_fsw <= io_enq_bits_fun_fsw; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_fld <= io_enq_bits_fun_fld; // @[IO_Lsu.scala 87:13]
    end
    if (_T_24) begin // @[IO_Lsu.scala 84:23]
      pending_fun_fsd <= io_enq_bits_fun_fsd; // @[IO_Lsu.scala 87:13]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (is_busy & ~_T_12 & ~_T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IO_Lsu, RISCV-A is not support at IO region\n    at IO_Lsu.scala:73 assert(false.B, \"Assert Failed at IO_Lsu, RISCV-A is not support at IO region\")\n"
            ); // @[IO_Lsu.scala 73:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (is_busy & ~_T_12 & ~_T_20 & ~reset)) begin
          $fatal; // @[IO_Lsu.scala 73:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_24 & _T_22 & ~_io_is_empty_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:85 assert( is_busy === false.B  )\n"); // @[IO_Lsu.scala 85:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_io_is_empty_T & (_T_24 & _T_22)) begin
          $fatal; // @[IO_Lsu.scala 85:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_8 & ~_io_getPut_valid_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:86 assert( isTransing === false.B  )\n"); // @[IO_Lsu.scala 86:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_io_getPut_valid_T & (_T_24 & _T_22)) begin
          $fatal; // @[IO_Lsu.scala 86:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_24 & _T_35 & _T_22) begin
          $fwrite(32'h80000002,"Warning! Accessing a Non-define Region."); // @[IO_Lsu.scala 92:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_10 & ~_T_35 & _T_33 & _T_22 & _io_is_empty_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:94 assert( is_busy === true.B )\n"); // @[IO_Lsu.scala 94:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_busy & (_GEN_10 & ~_T_35 & _T_33 & _T_22)) begin
          $fatal; // @[IO_Lsu.scala 94:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_14 & ~_T_33 & _T_34 & _T_22 & _io_is_empty_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:97 assert( is_busy === true.B  )\n"); // @[IO_Lsu.scala 97:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_busy & (_GEN_14 & ~_T_33 & _T_34 & _T_22)) begin
          $fatal; // @[IO_Lsu.scala 97:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  is_busy = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  isTransing = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  pending_fun_lb = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  pending_fun_lh = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  pending_fun_lw = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  pending_fun_ld = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  pending_fun_lbu = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  pending_fun_lhu = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  pending_fun_lwu = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  pending_fun_sb = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  pending_fun_sh = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  pending_fun_sw = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  pending_fun_sd = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  pending_fun_lr_w = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  pending_fun_sc_w = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  pending_fun_lr_d = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  pending_fun_sc_d = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  pending_fun_flw = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  pending_fun_fsw = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  pending_fun_fld = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  pending_fun_fsd = _RAND_20[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MissUnit(
  input         clock,
  input         reset,
  input         io_req_valid,
  input  [31:0] io_req_bits_paddr,
  output        io_rsp_valid,
  output [31:0] io_rsp_bits_paddr,
  input         io_cache_acquire_ready,
  output        io_cache_acquire_valid,
  output        io_cache_grant_ready,
  input         io_cache_grant_valid,
  input  [2:0]  io_cache_grant_bits_opcode,
  input  [2:0]  io_cache_grant_bits_size,
  input         io_cache_grant_bits_source,
  input         io_cache_grantAck_ready,
  output        io_cache_grantAck_valid,
  input         io_miss_ban,
  output        io_release_ban
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] miss_queue_0_paddr; // @[MissUnit.scala 56:27]
  reg [31:0] miss_queue_1_paddr; // @[MissUnit.scala 56:27]
  reg  miss_valid_0; // @[MissUnit.scala 59:27]
  reg  miss_valid_1; // @[MissUnit.scala 59:27]
  reg [2:0] mshr_state_qout; // @[MissUnit.scala 65:32]
  wire  _T = io_cache_grant_ready & io_cache_grant_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _beats1_decode_T_1 = 11'hf << io_cache_grant_bits_size; // @[package.scala 234:77]
  wire [3:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  beats1_decode = _beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  beats1_opdata = io_cache_grant_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  beats1 = beats1_opdata & beats1_decode; // @[Edges.scala 220:14]
  reg  counter; // @[Edges.scala 228:27]
  wire  counter1 = counter - 1'h1; // @[Edges.scala 229:28]
  wire  first = ~counter; // @[Edges.scala 230:25]
  wire  last = counter | ~beats1; // @[Edges.scala 231:37]
  wire  is_trans_done = last & _T; // @[Edges.scala 232:22]
  wire  acquire_sel_sel = miss_valid_0 ? 1'h0 : 1'h1; // @[MissUnit.scala 75:36]
  wire  _acquire_sel_T = mshr_state_qout == 3'h0; // @[MissUnit.scala 76:26]
  wire  _mshr_state_dnxt_T_6 = (miss_valid_0 | miss_valid_1) & ~io_miss_ban; // @[MissUnit.scala 103:68]
  wire  _mshr_state_dnxt_T_16 = _acquire_sel_T & _mshr_state_dnxt_T_6; // @[Mux.scala 27:73]
  wire  _mshr_state_dnxt_T_8 = mshr_state_qout == 3'h1; // @[MissUnit.scala 104:24]
  wire  _mshr_state_dnxt_T_9 = io_cache_acquire_ready & io_cache_acquire_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _mshr_state_dnxt_T_10 = _mshr_state_dnxt_T_9 ? 2'h2 : 2'h1; // @[MissUnit.scala 104:39]
  wire [1:0] _mshr_state_dnxt_T_17 = _mshr_state_dnxt_T_8 ? _mshr_state_dnxt_T_10 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_2 = {{1'd0}, _mshr_state_dnxt_T_16}; // @[Mux.scala 27:73]
  wire [1:0] _mshr_state_dnxt_T_20 = _GEN_2 | _mshr_state_dnxt_T_17; // @[Mux.scala 27:73]
  wire  _mshr_state_dnxt_T_11 = mshr_state_qout == 3'h2; // @[MissUnit.scala 105:24]
  wire [1:0] _mshr_state_dnxt_T_12 = is_trans_done ? 2'h3 : 2'h2; // @[MissUnit.scala 105:39]
  wire [1:0] _mshr_state_dnxt_T_18 = _mshr_state_dnxt_T_11 ? _mshr_state_dnxt_T_12 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _mshr_state_dnxt_T_21 = _mshr_state_dnxt_T_20 | _mshr_state_dnxt_T_18; // @[Mux.scala 27:73]
  wire  _mshr_state_dnxt_T_13 = mshr_state_qout == 3'h3; // @[MissUnit.scala 106:24]
  wire  _mshr_state_dnxt_T_14 = io_cache_grantAck_ready & io_cache_grantAck_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _mshr_state_dnxt_T_15 = _mshr_state_dnxt_T_14 ? 2'h0 : 2'h3; // @[MissUnit.scala 106:39]
  wire [1:0] _mshr_state_dnxt_T_19 = _mshr_state_dnxt_T_13 ? _mshr_state_dnxt_T_15 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _mshr_state_dnxt_T_22 = _mshr_state_dnxt_T_21 | _mshr_state_dnxt_T_19; // @[Mux.scala 27:73]
  wire [2:0] mshr_state_dnxt = {{1'd0}, _mshr_state_dnxt_T_22}; // @[MissUnit.scala 101:19 64:29]
  wire  _acquire_sel_T_3 = mshr_state_qout == 3'h0 & mshr_state_dnxt == 3'h1; // @[MissUnit.scala 76:79]
  reg  acquire_sel_r; // @[Reg.scala 19:16]
  wire  acquire_sel = mshr_state_qout == 3'h0 ? acquire_sel_sel : acquire_sel_r; // @[MissUnit.scala 76:8]
  reg  cache_acquire_vaild; // @[MissUnit.scala 81:37]
  reg  cache_grantAck_valid; // @[MissUnit.scala 87:37]
  reg  rsp_valid; // @[MissUnit.scala 90:26]
  wire  _T_6 = ~reset; // @[MissUnit.scala 93:9]
  wire  _GEN_10 = _mshr_state_dnxt_T_9 ? 1'h0 : cache_acquire_vaild; // @[MissUnit.scala 111:40 112:25 81:37]
  wire  _GEN_11 = _acquire_sel_T_3 | _GEN_10; // @[MissUnit.scala 109:61 110:25]
  wire  _T_23 = mshr_state_dnxt == 3'h3 & _mshr_state_dnxt_T_11; // @[MissUnit.scala 145:33]
  wire  _T_28 = ~_mshr_state_dnxt_T_13; // @[MissUnit.scala 150:11]
  wire  _GEN_18 = ~acquire_sel ? 1'h0 : miss_valid_0; // @[MissUnit.scala 153:{31,31} 59:27]
  wire  _GEN_19 = acquire_sel ? 1'h0 : miss_valid_1; // @[MissUnit.scala 153:{31,31} 59:27]
  wire  _GEN_20 = _mshr_state_dnxt_T_14 ? 1'h0 : cache_grantAck_valid; // @[MissUnit.scala 151:41 152:26 87:37]
  wire  _GEN_21 = _mshr_state_dnxt_T_14 ? _GEN_18 : miss_valid_0; // @[MissUnit.scala 151:41 59:27]
  wire  _GEN_22 = _mshr_state_dnxt_T_14 ? _GEN_19 : miss_valid_1; // @[MissUnit.scala 151:41 59:27]
  wire  _GEN_23 = io_rsp_valid ? 1'h0 : rsp_valid; // @[MissUnit.scala 147:28 148:15 90:26]
  wire  _GEN_24 = io_rsp_valid | _GEN_20; // @[MissUnit.scala 147:28 149:26]
  wire  _GEN_25 = io_rsp_valid ? miss_valid_0 : _GEN_21; // @[MissUnit.scala 147:28 59:27]
  wire  _GEN_26 = io_rsp_valid ? miss_valid_1 : _GEN_22; // @[MissUnit.scala 147:28 59:27]
  wire  _GEN_27 = mshr_state_dnxt == 3'h3 & _mshr_state_dnxt_T_11 | _GEN_23; // @[MissUnit.scala 145:61 146:15]
  wire  _GEN_29 = mshr_state_dnxt == 3'h3 & _mshr_state_dnxt_T_11 ? miss_valid_0 : _GEN_25; // @[MissUnit.scala 145:61 59:27]
  wire  _GEN_30 = mshr_state_dnxt == 3'h3 & _mshr_state_dnxt_T_11 ? miss_valid_1 : _GEN_26; // @[MissUnit.scala 145:61 59:27]
  wire  is_missQueue_full = miss_valid_0 & miss_valid_1; // @[MissUnit.scala 167:44]
  wire  _load_sel_T = ~miss_valid_0; // @[MissUnit.scala 170:56]
  wire  load_sel = ~miss_valid_0 ? 1'h0 : 1'h1; // @[MissUnit.scala 170:39]
  wire  _is_merge_T_2 = miss_queue_0_paddr == io_req_bits_paddr & miss_valid_0; // @[MissUnit.scala 178:51]
  wire  _is_merge_T_5 = miss_queue_1_paddr == io_req_bits_paddr & miss_valid_1; // @[MissUnit.scala 178:51]
  wire  is_merge = _is_merge_T_2 | _is_merge_T_5; // @[MissUnit.scala 180:13]
  wire  _GEN_33 = ~load_sel | _GEN_29; // @[MissUnit.scala 186:{28,28}]
  wire  _GEN_34 = load_sel | _GEN_30; // @[MissUnit.scala 186:{28,28}]
  wire  _T_48 = _load_sel_T | ~miss_valid_1 | is_merge; // @[MissUnit.scala 194:54]
  wire  _GEN_14 = ~_T_23; // @[MissUnit.scala 150:11]
  assign io_rsp_valid = rsp_valid; // @[MissUnit.scala 99:16]
  assign io_rsp_bits_paddr = acquire_sel ? miss_queue_1_paddr : miss_queue_0_paddr; // @[MissUnit.scala 130:{49,49}]
  assign io_cache_acquire_valid = cache_acquire_vaild; // @[MissUnit.scala 95:26]
  assign io_cache_grant_ready = mshr_state_qout == 3'h2; // @[MissUnit.scala 139:41]
  assign io_cache_grantAck_valid = cache_grantAck_valid; // @[MissUnit.scala 97:27]
  assign io_release_ban = mshr_state_dnxt == 3'h2 | _mshr_state_dnxt_T_11; // @[MissUnit.scala 161:45]
  always @(posedge clock) begin
    if (reset) begin // @[MissUnit.scala 56:27]
      miss_queue_0_paddr <= 32'h0; // @[MissUnit.scala 56:27]
    end else if (io_req_valid) begin // @[MissUnit.scala 183:21]
      if (~is_merge & ~is_missQueue_full) begin // @[MissUnit.scala 184:44]
        if (~load_sel) begin // @[MissUnit.scala 185:28]
          miss_queue_0_paddr <= io_req_bits_paddr; // @[MissUnit.scala 185:28]
        end
      end
    end
    if (reset) begin // @[MissUnit.scala 56:27]
      miss_queue_1_paddr <= 32'h0; // @[MissUnit.scala 56:27]
    end else if (io_req_valid) begin // @[MissUnit.scala 183:21]
      if (~is_merge & ~is_missQueue_full) begin // @[MissUnit.scala 184:44]
        if (load_sel) begin // @[MissUnit.scala 185:28]
          miss_queue_1_paddr <= io_req_bits_paddr; // @[MissUnit.scala 185:28]
        end
      end
    end
    if (reset) begin // @[MissUnit.scala 59:27]
      miss_valid_0 <= 1'h0; // @[MissUnit.scala 59:27]
    end else if (io_req_valid) begin // @[MissUnit.scala 183:21]
      if (~is_merge & ~is_missQueue_full) begin // @[MissUnit.scala 184:44]
        miss_valid_0 <= _GEN_33;
      end else begin
        miss_valid_0 <= _GEN_29;
      end
    end else begin
      miss_valid_0 <= _GEN_29;
    end
    if (reset) begin // @[MissUnit.scala 59:27]
      miss_valid_1 <= 1'h0; // @[MissUnit.scala 59:27]
    end else if (io_req_valid) begin // @[MissUnit.scala 183:21]
      if (~is_merge & ~is_missQueue_full) begin // @[MissUnit.scala 184:44]
        miss_valid_1 <= _GEN_34;
      end else begin
        miss_valid_1 <= _GEN_30;
      end
    end else begin
      miss_valid_1 <= _GEN_30;
    end
    if (reset) begin // @[MissUnit.scala 65:32]
      mshr_state_qout <= 3'h0; // @[MissUnit.scala 65:32]
    end else begin
      mshr_state_qout <= mshr_state_dnxt; // @[MissUnit.scala 65:32]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        counter <= beats1;
      end else begin
        counter <= counter1;
      end
    end
    if (_acquire_sel_T_3) begin // @[Reg.scala 20:18]
      if (miss_valid_0) begin // @[MissUnit.scala 75:36]
        acquire_sel_r <= 1'h0;
      end else begin
        acquire_sel_r <= 1'h1;
      end
    end
    if (reset) begin // @[MissUnit.scala 81:37]
      cache_acquire_vaild <= 1'h0; // @[MissUnit.scala 81:37]
    end else begin
      cache_acquire_vaild <= _GEN_11;
    end
    if (reset) begin // @[MissUnit.scala 87:37]
      cache_grantAck_valid <= 1'h0; // @[MissUnit.scala 87:37]
    end else if (!(mshr_state_dnxt == 3'h3 & _mshr_state_dnxt_T_11)) begin // @[MissUnit.scala 145:61]
      cache_grantAck_valid <= _GEN_24;
    end
    if (reset) begin // @[MissUnit.scala 90:26]
      rsp_valid <= 1'h0; // @[MissUnit.scala 90:26]
    end else begin
      rsp_valid <= _GEN_27;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(_T & io_cache_grant_bits_source))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at missUnit, source-id of grant mis-match\n    at MissUnit.scala:93 assert( ~(io.cache_grant.fire & io.cache_grant.bits.source =/= id.U), \"Assert Failed at missUnit, source-id of grant mis-match\"  )\n"
            ); // @[MissUnit.scala 93:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T & io_cache_grant_bits_source)) & ~reset) begin
          $fatal; // @[MissUnit.scala 93:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_acquire_sel_T_3 & _mshr_state_dnxt_T_9 & _T_6 & ~_mshr_state_dnxt_T_8) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MissUnit.scala:113 assert(mshr_state_qout === 1.U)\n"); // @[MissUnit.scala 113:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mshr_state_dnxt_T_8 & (~_acquire_sel_T_3 & _mshr_state_dnxt_T_9 & _T_6)) begin
          $fatal; // @[MissUnit.scala 113:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T & _T_6 & ~_mshr_state_dnxt_T_11) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MissUnit.scala:142 assert( mshr_state_qout === 2.U )\n"); // @[MissUnit.scala 142:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mshr_state_dnxt_T_11 & (_T & _T_6)) begin
          $fatal; // @[MissUnit.scala 142:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_23 & io_rsp_valid & _T_6 & ~_mshr_state_dnxt_T_13) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MissUnit.scala:150 assert(mshr_state_qout === 3.U)\n"); // @[MissUnit.scala 150:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mshr_state_dnxt_T_13 & (~_T_23 & io_rsp_valid & _T_6)) begin
          $fatal; // @[MissUnit.scala 150:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_14 & ~io_rsp_valid & _mshr_state_dnxt_T_14 & _T_6 & _T_28) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MissUnit.scala:154 assert(mshr_state_qout === 3.U)\n"); // @[MissUnit.scala 154:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mshr_state_dnxt_T_13 & (_GEN_14 & ~io_rsp_valid & _mshr_state_dnxt_T_14 & _T_6)) begin
          $fatal; // @[MissUnit.scala 154:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_req_valid & _T_6 & ~_T_48) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at MissUnit, the Miss-Entry is equal to SB-Entry, which hints that missUnit never full!\n    at MissUnit.scala:193 assert(\n"
            ); // @[MissUnit.scala 193:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_48 & (io_req_valid & _T_6)) begin
          $fatal; // @[MissUnit.scala 193:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  miss_queue_0_paddr = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  miss_queue_1_paddr = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  miss_valid_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  miss_valid_1 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  mshr_state_qout = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  counter = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  acquire_sel_r = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  cache_acquire_vaild = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  cache_grantAck_valid = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  rsp_valid = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_11(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [31:0] io_enq_bits,
  input         io_deq_ready,
  output        io_deq_valid,
  output [31:0] io_deq_bits
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] ram [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_io_deq_bits_MPORT_en = 1'h1;
  assign ram_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_io_deq_bits_MPORT_data = ram[ram_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_MPORT_data = io_enq_bits;
  assign ram_MPORT_addr = 1'h0;
  assign ram_MPORT_mask = 1'h1;
  assign ram_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits = ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_MPORT_en & ram_MPORT_mask) begin
      ram[ram_MPORT_addr] <= ram_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram[initvar] = _RAND_0[31:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  maybe_full = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ProbeUnit(
  input         clock,
  input         reset,
  input         io_cache_probe_valid,
  input  [31:0] io_cache_probe_bits_address,
  input         io_req_ready,
  output        io_req_valid,
  output [31:0] io_req_bits_paddr,
  input         io_probeBan
);
  wire  probe_fifo_clock; // @[ProbeUnit.scala 47:26]
  wire  probe_fifo_reset; // @[ProbeUnit.scala 47:26]
  wire  probe_fifo_io_enq_ready; // @[ProbeUnit.scala 47:26]
  wire  probe_fifo_io_enq_valid; // @[ProbeUnit.scala 47:26]
  wire [31:0] probe_fifo_io_enq_bits; // @[ProbeUnit.scala 47:26]
  wire  probe_fifo_io_deq_ready; // @[ProbeUnit.scala 47:26]
  wire  probe_fifo_io_deq_valid; // @[ProbeUnit.scala 47:26]
  wire [31:0] probe_fifo_io_deq_bits; // @[ProbeUnit.scala 47:26]
  wire  _io_req_valid_T = ~io_probeBan; // @[ProbeUnit.scala 54:45]
  Queue_11 probe_fifo ( // @[ProbeUnit.scala 47:26]
    .clock(probe_fifo_clock),
    .reset(probe_fifo_reset),
    .io_enq_ready(probe_fifo_io_enq_ready),
    .io_enq_valid(probe_fifo_io_enq_valid),
    .io_enq_bits(probe_fifo_io_enq_bits),
    .io_deq_ready(probe_fifo_io_deq_ready),
    .io_deq_valid(probe_fifo_io_deq_valid),
    .io_deq_bits(probe_fifo_io_deq_bits)
  );
  assign io_req_valid = probe_fifo_io_deq_valid & ~io_probeBan; // @[ProbeUnit.scala 54:43]
  assign io_req_bits_paddr = probe_fifo_io_deq_bits; // @[ProbeUnit.scala 56:21]
  assign probe_fifo_clock = clock;
  assign probe_fifo_reset = reset;
  assign probe_fifo_io_enq_valid = io_cache_probe_valid; // @[ProbeUnit.scala 50:27]
  assign probe_fifo_io_enq_bits = io_cache_probe_bits_address; // @[ProbeUnit.scala 51:26]
  assign probe_fifo_io_deq_ready = io_req_ready & _io_req_valid_T; // @[ProbeUnit.scala 55:43]
endmodule
module Queue_12(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_enq_bits_is_releaseData,
  input   io_enq_bits_is_release,
  input   io_enq_bits_is_probe,
  input   io_enq_bits_is_probeData,
  input   io_deq_ready,
  output  io_deq_valid,
  output  io_deq_bits_is_releaseData,
  output  io_deq_bits_is_release,
  output  io_deq_bits_is_probe,
  output  io_deq_bits_is_probeData
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  reg  ram_is_releaseData [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_is_releaseData_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_is_releaseData_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_releaseData_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_releaseData_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_releaseData_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_releaseData_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_is_releaseData_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_is_release [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_is_release_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_is_release_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_release_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_release_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_release_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_release_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_is_release_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_is_probe [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_is_probe_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_is_probe_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_probe_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_probe_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_probe_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_is_probe_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_is_probeData [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_is_probeData_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_is_probeData_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_probeData_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_probeData_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_probeData_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_probeData_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_is_probeData_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_17 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_17 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_is_releaseData_io_deq_bits_MPORT_en = 1'h1;
  assign ram_is_releaseData_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_is_releaseData_io_deq_bits_MPORT_data = ram_is_releaseData[ram_is_releaseData_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_is_releaseData_MPORT_data = io_enq_bits_is_releaseData;
  assign ram_is_releaseData_MPORT_addr = enq_ptr_value;
  assign ram_is_releaseData_MPORT_mask = 1'h1;
  assign ram_is_releaseData_MPORT_en = empty ? _GEN_17 : _do_enq_T;
  assign ram_is_release_io_deq_bits_MPORT_en = 1'h1;
  assign ram_is_release_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_is_release_io_deq_bits_MPORT_data = ram_is_release[ram_is_release_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_is_release_MPORT_data = io_enq_bits_is_release;
  assign ram_is_release_MPORT_addr = enq_ptr_value;
  assign ram_is_release_MPORT_mask = 1'h1;
  assign ram_is_release_MPORT_en = empty ? _GEN_17 : _do_enq_T;
  assign ram_is_probe_io_deq_bits_MPORT_en = 1'h1;
  assign ram_is_probe_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_is_probe_io_deq_bits_MPORT_data = ram_is_probe[ram_is_probe_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_is_probe_MPORT_data = io_enq_bits_is_probe;
  assign ram_is_probe_MPORT_addr = enq_ptr_value;
  assign ram_is_probe_MPORT_mask = 1'h1;
  assign ram_is_probe_MPORT_en = empty ? _GEN_17 : _do_enq_T;
  assign ram_is_probeData_io_deq_bits_MPORT_en = 1'h1;
  assign ram_is_probeData_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_is_probeData_io_deq_bits_MPORT_data = ram_is_probeData[ram_is_probeData_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_is_probeData_MPORT_data = io_enq_bits_is_probeData;
  assign ram_is_probeData_MPORT_addr = enq_ptr_value;
  assign ram_is_probeData_MPORT_mask = 1'h1;
  assign ram_is_probeData_MPORT_en = empty ? _GEN_17 : _do_enq_T;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_is_releaseData = empty ? io_enq_bits_is_releaseData : ram_is_releaseData_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_is_release = empty ? io_enq_bits_is_release : ram_is_release_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_is_probe = empty ? io_enq_bits_is_probe : ram_is_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_is_probeData = empty ? io_enq_bits_is_probeData : ram_is_probeData_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_is_releaseData_MPORT_en & ram_is_releaseData_MPORT_mask) begin
      ram_is_releaseData[ram_is_releaseData_MPORT_addr] <= ram_is_releaseData_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_is_release_MPORT_en & ram_is_release_MPORT_mask) begin
      ram_is_release[ram_is_release_MPORT_addr] <= ram_is_release_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_is_probe_MPORT_en & ram_is_probe_MPORT_mask) begin
      ram_is_probe[ram_is_probe_MPORT_addr] <= ram_is_probe_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_is_probeData_MPORT_en & ram_is_probeData_MPORT_mask) begin
      ram_is_probeData[ram_is_probeData_MPORT_addr] <= ram_is_probeData_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_is_releaseData[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_is_release[initvar] = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_is_probe[initvar] = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_is_probeData[initvar] = _RAND_3[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_4 = {1{`RANDOM}};
  enq_ptr_value = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  deq_ptr_value = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  maybe_full = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module WriteBackUnit(
  input        clock,
  input        reset,
  input        io_wb_req_valid,
  input        io_wb_req_bits_is_releaseData,
  input        io_wb_req_bits_is_release,
  input        io_wb_req_bits_is_probe,
  input        io_wb_req_bits_is_probeData,
  input        io_cache_release_ready,
  output       io_cache_release_valid,
  output [2:0] io_cache_release_bits_opcode,
  output [2:0] io_cache_release_bits_size,
  output       io_cache_grant_ready,
  input        io_cache_grant_valid,
  input        io_cache_grant_bits_source,
  input        io_release_ban,
  output       io_miss_ban
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  wire  wb_fifo_clock; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_reset; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_enq_ready; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_enq_valid; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_enq_bits_is_releaseData; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_enq_bits_is_release; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_enq_bits_is_probe; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_enq_bits_is_probeData; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_deq_ready; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_deq_valid; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_deq_bits_is_releaseData; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_deq_bits_is_release; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_deq_bits_is_probe; // @[wrtieBackUnit.scala 61:23]
  wire  wb_fifo_io_deq_bits_is_probeData; // @[wrtieBackUnit.scala 61:23]
  reg [1:0] wb_state_qout; // @[wrtieBackUnit.scala 70:30]
  wire  _is_release_done_T = io_cache_release_ready & io_cache_release_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _is_release_done_beats1_decode_T_1 = 11'hf << io_cache_release_bits_size; // @[package.scala 234:77]
  wire [3:0] _is_release_done_beats1_decode_T_3 = ~_is_release_done_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  is_release_done_beats1_decode = _is_release_done_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  is_release_done_beats1_opdata = io_cache_release_bits_opcode[0]; // @[Edges.scala 101:36]
  wire  is_release_done_beats1 = is_release_done_beats1_opdata & is_release_done_beats1_decode; // @[Edges.scala 220:14]
  reg  is_release_done_counter; // @[Edges.scala 228:27]
  wire  is_release_done_counter1 = is_release_done_counter - 1'h1; // @[Edges.scala 229:28]
  wire  is_release_done_first = ~is_release_done_counter; // @[Edges.scala 230:25]
  wire  is_release_done_last = is_release_done_counter | ~is_release_done_beats1; // @[Edges.scala 231:37]
  wire  is_release_done = is_release_done_last & _is_release_done_T; // @[Edges.scala 232:22]
  reg  cache_release_valid; // @[wrtieBackUnit.scala 76:36]
  reg  cache_grant_ready; // @[wrtieBackUnit.scala 79:36]
  wire  _wb_state_dnxt_T = wb_state_qout == 2'h0; // @[wrtieBackUnit.scala 87:22]
  wire  _wb_state_dnxt_T_4 = wb_fifo_io_deq_bits_is_probe | wb_fifo_io_deq_bits_is_probeData; // @[wrtieBackUnit.scala 90:42]
  wire  _wb_state_dnxt_T_5 = ~io_release_ban & (wb_fifo_io_deq_bits_is_release | wb_fifo_io_deq_bits_is_releaseData) |
    _wb_state_dnxt_T_4; // @[wrtieBackUnit.scala 89:103]
  wire  _wb_state_dnxt_T_6 = wb_fifo_io_deq_valid & _wb_state_dnxt_T_5; // @[wrtieBackUnit.scala 88:30]
  wire  _wb_state_dnxt_T_8 = wb_state_qout == 2'h1; // @[wrtieBackUnit.scala 93:22]
  wire [1:0] _wb_state_dnxt_T_11 = wb_fifo_io_deq_bits_is_probeData | wb_fifo_io_deq_bits_is_probe ? 2'h0 : 2'h2; // @[wrtieBackUnit.scala 95:14]
  wire [1:0] _wb_state_dnxt_T_12 = ~is_release_done ? 2'h1 : _wb_state_dnxt_T_11; // @[wrtieBackUnit.scala 94:12]
  wire  _wb_state_dnxt_T_13 = wb_state_qout == 2'h2; // @[wrtieBackUnit.scala 96:22]
  wire  _wb_state_dnxt_T_14 = io_cache_grant_ready & io_cache_grant_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _wb_state_dnxt_T_15 = _wb_state_dnxt_T_14 ? 2'h0 : 2'h2; // @[wrtieBackUnit.scala 96:37]
  wire  _wb_state_dnxt_T_16 = _wb_state_dnxt_T & _wb_state_dnxt_T_6; // @[Mux.scala 27:73]
  wire [1:0] _wb_state_dnxt_T_17 = _wb_state_dnxt_T_8 ? _wb_state_dnxt_T_12 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _wb_state_dnxt_T_18 = _wb_state_dnxt_T_13 ? _wb_state_dnxt_T_15 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_1 = {{1'd0}, _wb_state_dnxt_T_16}; // @[Mux.scala 27:73]
  wire [1:0] _wb_state_dnxt_T_19 = _GEN_1 | _wb_state_dnxt_T_17; // @[Mux.scala 27:73]
  wire [1:0] wb_state_dnxt = _wb_state_dnxt_T_19 | _wb_state_dnxt_T_18; // @[Mux.scala 27:73]
  wire  _GEN_3 = ~io_cache_release_valid | cache_release_valid; // @[wrtieBackUnit.scala 106:{42,64} 76:36]
  wire [2:0] _io_cache_release_bits_T_28 = wb_fifo_io_deq_bits_is_probe ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_29 = wb_fifo_io_deq_bits_is_probeData ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_30 = wb_fifo_io_deq_bits_is_release ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_31 = wb_fifo_io_deq_bits_is_releaseData ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_32 = _io_cache_release_bits_T_28 | _io_cache_release_bits_T_29; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_33 = _io_cache_release_bits_T_32 | _io_cache_release_bits_T_30; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_43 = wb_fifo_io_deq_bits_is_probeData ? 3'h5 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_44 = wb_fifo_io_deq_bits_is_release ? 3'h6 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_45 = wb_fifo_io_deq_bits_is_releaseData ? 3'h7 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_46 = _io_cache_release_bits_T_28 | _io_cache_release_bits_T_43; // @[Mux.scala 27:73]
  wire [2:0] _io_cache_release_bits_T_47 = _io_cache_release_bits_T_46 | _io_cache_release_bits_T_44; // @[Mux.scala 27:73]
  wire  _T_8 = io_cache_grant_valid & ~io_cache_grant_ready; // @[wrtieBackUnit.scala 160:30]
  wire  _T_11 = ~reset; // @[wrtieBackUnit.scala 162:11]
  wire  _T_12 = ~_wb_state_dnxt_T_13; // @[wrtieBackUnit.scala 162:11]
  wire  _GEN_6 = io_cache_grant_ready ? 1'h0 : cache_grant_ready; // @[wrtieBackUnit.scala 163:39 164:23 79:36]
  wire  _GEN_7 = io_cache_grant_valid & ~io_cache_grant_ready | _GEN_6; // @[wrtieBackUnit.scala 160:56 161:23]
  wire  _T_24 = ~wb_fifo_io_enq_ready; // @[wrtieBackUnit.scala 175:9]
  Queue_12 wb_fifo ( // @[wrtieBackUnit.scala 61:23]
    .clock(wb_fifo_clock),
    .reset(wb_fifo_reset),
    .io_enq_ready(wb_fifo_io_enq_ready),
    .io_enq_valid(wb_fifo_io_enq_valid),
    .io_enq_bits_is_releaseData(wb_fifo_io_enq_bits_is_releaseData),
    .io_enq_bits_is_release(wb_fifo_io_enq_bits_is_release),
    .io_enq_bits_is_probe(wb_fifo_io_enq_bits_is_probe),
    .io_enq_bits_is_probeData(wb_fifo_io_enq_bits_is_probeData),
    .io_deq_ready(wb_fifo_io_deq_ready),
    .io_deq_valid(wb_fifo_io_deq_valid),
    .io_deq_bits_is_releaseData(wb_fifo_io_deq_bits_is_releaseData),
    .io_deq_bits_is_release(wb_fifo_io_deq_bits_is_release),
    .io_deq_bits_is_probe(wb_fifo_io_deq_bits_is_probe),
    .io_deq_bits_is_probeData(wb_fifo_io_deq_bits_is_probeData)
  );
  assign io_cache_release_valid = cache_release_valid; // @[wrtieBackUnit.scala 81:26]
  assign io_cache_release_bits_opcode = _io_cache_release_bits_T_47 | _io_cache_release_bits_T_45; // @[Mux.scala 27:73]
  assign io_cache_release_bits_size = _io_cache_release_bits_T_33 | _io_cache_release_bits_T_31; // @[Mux.scala 27:73]
  assign io_cache_grant_ready = cache_grant_ready; // @[wrtieBackUnit.scala 82:26]
  assign io_miss_ban = _wb_state_dnxt_T_8 | _wb_state_dnxt_T_13 | wb_fifo_io_deq_valid; // @[wrtieBackUnit.scala 171:64]
  assign wb_fifo_clock = clock;
  assign wb_fifo_reset = reset;
  assign wb_fifo_io_enq_valid = io_wb_req_valid; // @[wrtieBackUnit.scala 63:24]
  assign wb_fifo_io_enq_bits_is_releaseData = io_wb_req_bits_is_releaseData; // @[wrtieBackUnit.scala 64:24]
  assign wb_fifo_io_enq_bits_is_release = io_wb_req_bits_is_release; // @[wrtieBackUnit.scala 64:24]
  assign wb_fifo_io_enq_bits_is_probe = io_wb_req_bits_is_probe; // @[wrtieBackUnit.scala 64:24]
  assign wb_fifo_io_enq_bits_is_probeData = io_wb_req_bits_is_probeData; // @[wrtieBackUnit.scala 64:24]
  assign wb_fifo_io_deq_ready = wb_state_qout != 2'h0 & wb_state_dnxt == 2'h0; // @[wrtieBackUnit.scala 169:27]
  always @(posedge clock) begin
    if (reset) begin // @[wrtieBackUnit.scala 70:30]
      wb_state_qout <= 2'h0; // @[wrtieBackUnit.scala 70:30]
    end else begin
      wb_state_qout <= wb_state_dnxt; // @[wrtieBackUnit.scala 70:30]
    end
    if (reset) begin // @[Edges.scala 228:27]
      is_release_done_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_is_release_done_T) begin // @[Edges.scala 234:17]
      if (is_release_done_first) begin // @[Edges.scala 235:21]
        is_release_done_counter <= is_release_done_beats1;
      end else begin
        is_release_done_counter <= is_release_done_counter1;
      end
    end
    if (reset) begin // @[wrtieBackUnit.scala 76:36]
      cache_release_valid <= 1'h0; // @[wrtieBackUnit.scala 76:36]
    end else if (_wb_state_dnxt_T_8) begin // @[wrtieBackUnit.scala 104:33]
      if (_is_release_done_T) begin // @[wrtieBackUnit.scala 105:35]
        cache_release_valid <= 1'h0; // @[wrtieBackUnit.scala 105:57]
      end else begin
        cache_release_valid <= _GEN_3;
      end
    end
    if (reset) begin // @[wrtieBackUnit.scala 79:36]
      cache_grant_ready <= 1'h0; // @[wrtieBackUnit.scala 79:36]
    end else begin
      cache_grant_ready <= _GEN_7;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & ~reset & ~_wb_state_dnxt_T_13) begin
          $fwrite(32'h80000002,"Assertion failed\n    at wrtieBackUnit.scala:162 assert( wb_state_qout === 2.U )\n"); // @[wrtieBackUnit.scala 162:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_wb_state_dnxt_T_13 & (_T_8 & ~reset)) begin
          $fatal; // @[wrtieBackUnit.scala 162:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_8 & io_cache_grant_ready & _T_11 & _T_12) begin
          $fwrite(32'h80000002,"Assertion failed\n    at wrtieBackUnit.scala:165 assert( wb_state_qout === 2.U )\n"); // @[wrtieBackUnit.scala 165:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_wb_state_dnxt_T_13 & (~_T_8 & io_cache_grant_ready & _T_11)) begin
          $fatal; // @[wrtieBackUnit.scala 165:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_11 & ~(~(_wb_state_dnxt_T_14 & io_cache_grant_bits_source))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at writeBack-Unit, grant-id mis-match\n    at wrtieBackUnit.scala:167 assert( ~(io.cache_grant.fire & io.cache_grant.bits.source =/= id.U), \"Assert Failed at writeBack-Unit, grant-id mis-match\" )\n"
            ); // @[wrtieBackUnit.scala 167:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_wb_state_dnxt_T_14 & io_cache_grant_bits_source)) & _T_11) begin
          $fatal; // @[wrtieBackUnit.scala 167:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_24 & _T_11 & ~(~io_wb_req_valid)) begin
          $fwrite(32'h80000002,
            "Assertion failed: When WriteBack Unit is busy, no new acquire will be emitted, and there is no wb request!\n    at wrtieBackUnit.scala:176 assert(~io.wb_req.valid, \"When WriteBack Unit is busy, no new acquire will be emitted, and there is no wb request!\")\n"
            ); // @[wrtieBackUnit.scala 176:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_wb_req_valid) & (_T_24 & _T_11)) begin
          $fatal; // @[wrtieBackUnit.scala 176:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  wb_state_qout = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  is_release_done_counter = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  cache_release_valid = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  cache_grant_ready = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_13(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_chkIdx,
  input  [31:0] io_enq_bits_paddr,
  input         io_enq_bits_fun_lb,
  input         io_enq_bits_fun_lh,
  input         io_enq_bits_fun_lw,
  input         io_enq_bits_fun_ld,
  input         io_enq_bits_fun_lbu,
  input         io_enq_bits_fun_lhu,
  input         io_enq_bits_fun_lwu,
  input         io_enq_bits_fun_sb,
  input         io_enq_bits_fun_sh,
  input         io_enq_bits_fun_sw,
  input         io_enq_bits_fun_sd,
  input         io_enq_bits_fun_lr_w,
  input         io_enq_bits_fun_sc_w,
  input         io_enq_bits_fun_amoswap_w,
  input         io_enq_bits_fun_amoadd_w,
  input         io_enq_bits_fun_amoxor_w,
  input         io_enq_bits_fun_amoand_w,
  input         io_enq_bits_fun_amoor_w,
  input         io_enq_bits_fun_amomin_w,
  input         io_enq_bits_fun_amomax_w,
  input         io_enq_bits_fun_amominu_w,
  input         io_enq_bits_fun_amomaxu_w,
  input         io_enq_bits_fun_lr_d,
  input         io_enq_bits_fun_sc_d,
  input         io_enq_bits_fun_amoswap_d,
  input         io_enq_bits_fun_amoadd_d,
  input         io_enq_bits_fun_amoxor_d,
  input         io_enq_bits_fun_amoand_d,
  input         io_enq_bits_fun_amoor_d,
  input         io_enq_bits_fun_amomin_d,
  input         io_enq_bits_fun_amomax_d,
  input         io_enq_bits_fun_amominu_d,
  input         io_enq_bits_fun_amomaxu_d,
  input         io_enq_bits_fun_flw,
  input         io_enq_bits_fun_fsw,
  input         io_enq_bits_fun_fld,
  input         io_enq_bits_fun_fsd,
  input         io_enq_bits_fun_probe,
  input         io_enq_bits_fun_grant,
  input         io_enq_bits_fun_preft,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_chkIdx,
  output [31:0] io_deq_bits_paddr,
  output        io_deq_bits_fun_lb,
  output        io_deq_bits_fun_lh,
  output        io_deq_bits_fun_lw,
  output        io_deq_bits_fun_ld,
  output        io_deq_bits_fun_lbu,
  output        io_deq_bits_fun_lhu,
  output        io_deq_bits_fun_lwu,
  output        io_deq_bits_fun_sb,
  output        io_deq_bits_fun_sh,
  output        io_deq_bits_fun_sw,
  output        io_deq_bits_fun_sd,
  output        io_deq_bits_fun_lr_w,
  output        io_deq_bits_fun_sc_w,
  output        io_deq_bits_fun_amoswap_w,
  output        io_deq_bits_fun_amoadd_w,
  output        io_deq_bits_fun_amoxor_w,
  output        io_deq_bits_fun_amoand_w,
  output        io_deq_bits_fun_amoor_w,
  output        io_deq_bits_fun_amomin_w,
  output        io_deq_bits_fun_amomax_w,
  output        io_deq_bits_fun_amominu_w,
  output        io_deq_bits_fun_amomaxu_w,
  output        io_deq_bits_fun_lr_d,
  output        io_deq_bits_fun_sc_d,
  output        io_deq_bits_fun_amoswap_d,
  output        io_deq_bits_fun_amoadd_d,
  output        io_deq_bits_fun_amoxor_d,
  output        io_deq_bits_fun_amoand_d,
  output        io_deq_bits_fun_amoor_d,
  output        io_deq_bits_fun_amomin_d,
  output        io_deq_bits_fun_amomax_d,
  output        io_deq_bits_fun_amominu_d,
  output        io_deq_bits_fun_amomaxu_d,
  output        io_deq_bits_fun_flw,
  output        io_deq_bits_fun_fsw,
  output        io_deq_bits_fun_fld,
  output        io_deq_bits_fun_fsd,
  output        io_deq_bits_fun_probe,
  output        io_deq_bits_fun_grant,
  output        io_deq_bits_fun_preft
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
`endif // RANDOMIZE_REG_INIT
  reg  ram_chkIdx [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_paddr [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_paddr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_paddr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_paddr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_paddr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_paddr_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lb [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lh [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lw [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_ld [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lbu [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lhu [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lwu [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sb [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sh [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sw [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sd [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lr_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sc_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoswap_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoadd_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoxor_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoand_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoor_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomin_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomax_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amominu_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomaxu_w [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lr_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sc_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoswap_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoadd_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoxor_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoand_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoor_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomin_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomax_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amominu_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomaxu_d [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_flw [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_fsw [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_fld [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_fsd [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_probe [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_grant [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_preft [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_59 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_59 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_chkIdx_io_deq_bits_MPORT_en = 1'h1;
  assign ram_chkIdx_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_chkIdx_io_deq_bits_MPORT_data = ram_chkIdx[ram_chkIdx_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_chkIdx_MPORT_data = io_enq_bits_chkIdx;
  assign ram_chkIdx_MPORT_addr = enq_ptr_value;
  assign ram_chkIdx_MPORT_mask = 1'h1;
  assign ram_chkIdx_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_paddr_io_deq_bits_MPORT_en = 1'h1;
  assign ram_paddr_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_paddr_io_deq_bits_MPORT_data = ram_paddr[ram_paddr_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_paddr_MPORT_data = io_enq_bits_paddr;
  assign ram_paddr_MPORT_addr = enq_ptr_value;
  assign ram_paddr_MPORT_mask = 1'h1;
  assign ram_paddr_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_lb_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lb_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_lb_io_deq_bits_MPORT_data = ram_fun_lb[ram_fun_lb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lb_MPORT_data = io_enq_bits_fun_lb;
  assign ram_fun_lb_MPORT_addr = enq_ptr_value;
  assign ram_fun_lb_MPORT_mask = 1'h1;
  assign ram_fun_lb_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_lh_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lh_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_lh_io_deq_bits_MPORT_data = ram_fun_lh[ram_fun_lh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lh_MPORT_data = io_enq_bits_fun_lh;
  assign ram_fun_lh_MPORT_addr = enq_ptr_value;
  assign ram_fun_lh_MPORT_mask = 1'h1;
  assign ram_fun_lh_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_lw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lw_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_lw_io_deq_bits_MPORT_data = ram_fun_lw[ram_fun_lw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lw_MPORT_data = io_enq_bits_fun_lw;
  assign ram_fun_lw_MPORT_addr = enq_ptr_value;
  assign ram_fun_lw_MPORT_mask = 1'h1;
  assign ram_fun_lw_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_ld_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_ld_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_ld_io_deq_bits_MPORT_data = ram_fun_ld[ram_fun_ld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_ld_MPORT_data = io_enq_bits_fun_ld;
  assign ram_fun_ld_MPORT_addr = enq_ptr_value;
  assign ram_fun_ld_MPORT_mask = 1'h1;
  assign ram_fun_ld_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_lbu_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lbu_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_lbu_io_deq_bits_MPORT_data = ram_fun_lbu[ram_fun_lbu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lbu_MPORT_data = io_enq_bits_fun_lbu;
  assign ram_fun_lbu_MPORT_addr = enq_ptr_value;
  assign ram_fun_lbu_MPORT_mask = 1'h1;
  assign ram_fun_lbu_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_lhu_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lhu_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_lhu_io_deq_bits_MPORT_data = ram_fun_lhu[ram_fun_lhu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lhu_MPORT_data = io_enq_bits_fun_lhu;
  assign ram_fun_lhu_MPORT_addr = enq_ptr_value;
  assign ram_fun_lhu_MPORT_mask = 1'h1;
  assign ram_fun_lhu_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_lwu_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lwu_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_lwu_io_deq_bits_MPORT_data = ram_fun_lwu[ram_fun_lwu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lwu_MPORT_data = io_enq_bits_fun_lwu;
  assign ram_fun_lwu_MPORT_addr = enq_ptr_value;
  assign ram_fun_lwu_MPORT_mask = 1'h1;
  assign ram_fun_lwu_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_sb_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sb_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_sb_io_deq_bits_MPORT_data = ram_fun_sb[ram_fun_sb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sb_MPORT_data = io_enq_bits_fun_sb;
  assign ram_fun_sb_MPORT_addr = enq_ptr_value;
  assign ram_fun_sb_MPORT_mask = 1'h1;
  assign ram_fun_sb_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_sh_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sh_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_sh_io_deq_bits_MPORT_data = ram_fun_sh[ram_fun_sh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sh_MPORT_data = io_enq_bits_fun_sh;
  assign ram_fun_sh_MPORT_addr = enq_ptr_value;
  assign ram_fun_sh_MPORT_mask = 1'h1;
  assign ram_fun_sh_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_sw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sw_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_sw_io_deq_bits_MPORT_data = ram_fun_sw[ram_fun_sw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sw_MPORT_data = io_enq_bits_fun_sw;
  assign ram_fun_sw_MPORT_addr = enq_ptr_value;
  assign ram_fun_sw_MPORT_mask = 1'h1;
  assign ram_fun_sw_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_sd_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sd_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_sd_io_deq_bits_MPORT_data = ram_fun_sd[ram_fun_sd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sd_MPORT_data = io_enq_bits_fun_sd;
  assign ram_fun_sd_MPORT_addr = enq_ptr_value;
  assign ram_fun_sd_MPORT_mask = 1'h1;
  assign ram_fun_sd_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_lr_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lr_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_lr_w_io_deq_bits_MPORT_data = ram_fun_lr_w[ram_fun_lr_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lr_w_MPORT_data = io_enq_bits_fun_lr_w;
  assign ram_fun_lr_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_lr_w_MPORT_mask = 1'h1;
  assign ram_fun_lr_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_sc_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sc_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_sc_w_io_deq_bits_MPORT_data = ram_fun_sc_w[ram_fun_sc_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sc_w_MPORT_data = io_enq_bits_fun_sc_w;
  assign ram_fun_sc_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_sc_w_MPORT_mask = 1'h1;
  assign ram_fun_sc_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoswap_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoswap_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoswap_w_io_deq_bits_MPORT_data = ram_fun_amoswap_w[ram_fun_amoswap_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoswap_w_MPORT_data = io_enq_bits_fun_amoswap_w;
  assign ram_fun_amoswap_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoswap_w_MPORT_mask = 1'h1;
  assign ram_fun_amoswap_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoadd_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoadd_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoadd_w_io_deq_bits_MPORT_data = ram_fun_amoadd_w[ram_fun_amoadd_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoadd_w_MPORT_data = io_enq_bits_fun_amoadd_w;
  assign ram_fun_amoadd_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoadd_w_MPORT_mask = 1'h1;
  assign ram_fun_amoadd_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoxor_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoxor_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoxor_w_io_deq_bits_MPORT_data = ram_fun_amoxor_w[ram_fun_amoxor_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoxor_w_MPORT_data = io_enq_bits_fun_amoxor_w;
  assign ram_fun_amoxor_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoxor_w_MPORT_mask = 1'h1;
  assign ram_fun_amoxor_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoand_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoand_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoand_w_io_deq_bits_MPORT_data = ram_fun_amoand_w[ram_fun_amoand_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoand_w_MPORT_data = io_enq_bits_fun_amoand_w;
  assign ram_fun_amoand_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoand_w_MPORT_mask = 1'h1;
  assign ram_fun_amoand_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoor_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoor_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoor_w_io_deq_bits_MPORT_data = ram_fun_amoor_w[ram_fun_amoor_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoor_w_MPORT_data = io_enq_bits_fun_amoor_w;
  assign ram_fun_amoor_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoor_w_MPORT_mask = 1'h1;
  assign ram_fun_amoor_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amomin_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomin_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amomin_w_io_deq_bits_MPORT_data = ram_fun_amomin_w[ram_fun_amomin_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomin_w_MPORT_data = io_enq_bits_fun_amomin_w;
  assign ram_fun_amomin_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amomin_w_MPORT_mask = 1'h1;
  assign ram_fun_amomin_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amomax_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomax_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amomax_w_io_deq_bits_MPORT_data = ram_fun_amomax_w[ram_fun_amomax_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomax_w_MPORT_data = io_enq_bits_fun_amomax_w;
  assign ram_fun_amomax_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amomax_w_MPORT_mask = 1'h1;
  assign ram_fun_amomax_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amominu_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amominu_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amominu_w_io_deq_bits_MPORT_data = ram_fun_amominu_w[ram_fun_amominu_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amominu_w_MPORT_data = io_enq_bits_fun_amominu_w;
  assign ram_fun_amominu_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amominu_w_MPORT_mask = 1'h1;
  assign ram_fun_amominu_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amomaxu_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomaxu_w_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amomaxu_w_io_deq_bits_MPORT_data = ram_fun_amomaxu_w[ram_fun_amomaxu_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomaxu_w_MPORT_data = io_enq_bits_fun_amomaxu_w;
  assign ram_fun_amomaxu_w_MPORT_addr = enq_ptr_value;
  assign ram_fun_amomaxu_w_MPORT_mask = 1'h1;
  assign ram_fun_amomaxu_w_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_lr_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lr_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_lr_d_io_deq_bits_MPORT_data = ram_fun_lr_d[ram_fun_lr_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lr_d_MPORT_data = io_enq_bits_fun_lr_d;
  assign ram_fun_lr_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_lr_d_MPORT_mask = 1'h1;
  assign ram_fun_lr_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_sc_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sc_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_sc_d_io_deq_bits_MPORT_data = ram_fun_sc_d[ram_fun_sc_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sc_d_MPORT_data = io_enq_bits_fun_sc_d;
  assign ram_fun_sc_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_sc_d_MPORT_mask = 1'h1;
  assign ram_fun_sc_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoswap_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoswap_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoswap_d_io_deq_bits_MPORT_data = ram_fun_amoswap_d[ram_fun_amoswap_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoswap_d_MPORT_data = io_enq_bits_fun_amoswap_d;
  assign ram_fun_amoswap_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoswap_d_MPORT_mask = 1'h1;
  assign ram_fun_amoswap_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoadd_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoadd_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoadd_d_io_deq_bits_MPORT_data = ram_fun_amoadd_d[ram_fun_amoadd_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoadd_d_MPORT_data = io_enq_bits_fun_amoadd_d;
  assign ram_fun_amoadd_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoadd_d_MPORT_mask = 1'h1;
  assign ram_fun_amoadd_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoxor_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoxor_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoxor_d_io_deq_bits_MPORT_data = ram_fun_amoxor_d[ram_fun_amoxor_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoxor_d_MPORT_data = io_enq_bits_fun_amoxor_d;
  assign ram_fun_amoxor_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoxor_d_MPORT_mask = 1'h1;
  assign ram_fun_amoxor_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoand_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoand_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoand_d_io_deq_bits_MPORT_data = ram_fun_amoand_d[ram_fun_amoand_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoand_d_MPORT_data = io_enq_bits_fun_amoand_d;
  assign ram_fun_amoand_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoand_d_MPORT_mask = 1'h1;
  assign ram_fun_amoand_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amoor_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoor_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amoor_d_io_deq_bits_MPORT_data = ram_fun_amoor_d[ram_fun_amoor_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoor_d_MPORT_data = io_enq_bits_fun_amoor_d;
  assign ram_fun_amoor_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amoor_d_MPORT_mask = 1'h1;
  assign ram_fun_amoor_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amomin_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomin_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amomin_d_io_deq_bits_MPORT_data = ram_fun_amomin_d[ram_fun_amomin_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomin_d_MPORT_data = io_enq_bits_fun_amomin_d;
  assign ram_fun_amomin_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amomin_d_MPORT_mask = 1'h1;
  assign ram_fun_amomin_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amomax_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomax_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amomax_d_io_deq_bits_MPORT_data = ram_fun_amomax_d[ram_fun_amomax_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomax_d_MPORT_data = io_enq_bits_fun_amomax_d;
  assign ram_fun_amomax_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amomax_d_MPORT_mask = 1'h1;
  assign ram_fun_amomax_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amominu_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amominu_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amominu_d_io_deq_bits_MPORT_data = ram_fun_amominu_d[ram_fun_amominu_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amominu_d_MPORT_data = io_enq_bits_fun_amominu_d;
  assign ram_fun_amominu_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amominu_d_MPORT_mask = 1'h1;
  assign ram_fun_amominu_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_amomaxu_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomaxu_d_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_amomaxu_d_io_deq_bits_MPORT_data = ram_fun_amomaxu_d[ram_fun_amomaxu_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomaxu_d_MPORT_data = io_enq_bits_fun_amomaxu_d;
  assign ram_fun_amomaxu_d_MPORT_addr = enq_ptr_value;
  assign ram_fun_amomaxu_d_MPORT_mask = 1'h1;
  assign ram_fun_amomaxu_d_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_flw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_flw_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_flw_io_deq_bits_MPORT_data = ram_fun_flw[ram_fun_flw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_flw_MPORT_data = io_enq_bits_fun_flw;
  assign ram_fun_flw_MPORT_addr = enq_ptr_value;
  assign ram_fun_flw_MPORT_mask = 1'h1;
  assign ram_fun_flw_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_fsw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_fsw_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_fsw_io_deq_bits_MPORT_data = ram_fun_fsw[ram_fun_fsw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_fsw_MPORT_data = io_enq_bits_fun_fsw;
  assign ram_fun_fsw_MPORT_addr = enq_ptr_value;
  assign ram_fun_fsw_MPORT_mask = 1'h1;
  assign ram_fun_fsw_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_fld_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_fld_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_fld_io_deq_bits_MPORT_data = ram_fun_fld[ram_fun_fld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_fld_MPORT_data = io_enq_bits_fun_fld;
  assign ram_fun_fld_MPORT_addr = enq_ptr_value;
  assign ram_fun_fld_MPORT_mask = 1'h1;
  assign ram_fun_fld_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_fsd_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_fsd_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_fsd_io_deq_bits_MPORT_data = ram_fun_fsd[ram_fun_fsd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_fsd_MPORT_data = io_enq_bits_fun_fsd;
  assign ram_fun_fsd_MPORT_addr = enq_ptr_value;
  assign ram_fun_fsd_MPORT_mask = 1'h1;
  assign ram_fun_fsd_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_probe_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_probe_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_probe_io_deq_bits_MPORT_data = ram_fun_probe[ram_fun_probe_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_probe_MPORT_data = io_enq_bits_fun_probe;
  assign ram_fun_probe_MPORT_addr = enq_ptr_value;
  assign ram_fun_probe_MPORT_mask = 1'h1;
  assign ram_fun_probe_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_grant_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_grant_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_grant_io_deq_bits_MPORT_data = ram_fun_grant[ram_fun_grant_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_grant_MPORT_data = io_enq_bits_fun_grant;
  assign ram_fun_grant_MPORT_addr = enq_ptr_value;
  assign ram_fun_grant_MPORT_mask = 1'h1;
  assign ram_fun_grant_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign ram_fun_preft_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_preft_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_fun_preft_io_deq_bits_MPORT_data = ram_fun_preft[ram_fun_preft_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_preft_MPORT_data = io_enq_bits_fun_preft;
  assign ram_fun_preft_MPORT_addr = enq_ptr_value;
  assign ram_fun_preft_MPORT_mask = 1'h1;
  assign ram_fun_preft_MPORT_en = empty ? _GEN_59 : _do_enq_T;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_chkIdx = empty ? io_enq_bits_chkIdx : ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_paddr = empty ? io_enq_bits_paddr : ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_lb = empty ? io_enq_bits_fun_lb : ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_lh = empty ? io_enq_bits_fun_lh : ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_lw = empty ? io_enq_bits_fun_lw : ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_ld = empty ? io_enq_bits_fun_ld : ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_lbu = empty ? io_enq_bits_fun_lbu : ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_lhu = empty ? io_enq_bits_fun_lhu : ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_lwu = empty ? io_enq_bits_fun_lwu : ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_sb = empty ? io_enq_bits_fun_sb : ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_sh = empty ? io_enq_bits_fun_sh : ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_sw = empty ? io_enq_bits_fun_sw : ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_sd = empty ? io_enq_bits_fun_sd : ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_lr_w = empty ? io_enq_bits_fun_lr_w : ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_sc_w = empty ? io_enq_bits_fun_sc_w : ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoswap_w = empty ? io_enq_bits_fun_amoswap_w : ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoadd_w = empty ? io_enq_bits_fun_amoadd_w : ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoxor_w = empty ? io_enq_bits_fun_amoxor_w : ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoand_w = empty ? io_enq_bits_fun_amoand_w : ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoor_w = empty ? io_enq_bits_fun_amoor_w : ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amomin_w = empty ? io_enq_bits_fun_amomin_w : ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amomax_w = empty ? io_enq_bits_fun_amomax_w : ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amominu_w = empty ? io_enq_bits_fun_amominu_w : ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amomaxu_w = empty ? io_enq_bits_fun_amomaxu_w : ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_lr_d = empty ? io_enq_bits_fun_lr_d : ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_sc_d = empty ? io_enq_bits_fun_sc_d : ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoswap_d = empty ? io_enq_bits_fun_amoswap_d : ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoadd_d = empty ? io_enq_bits_fun_amoadd_d : ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoxor_d = empty ? io_enq_bits_fun_amoxor_d : ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoand_d = empty ? io_enq_bits_fun_amoand_d : ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amoor_d = empty ? io_enq_bits_fun_amoor_d : ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amomin_d = empty ? io_enq_bits_fun_amomin_d : ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amomax_d = empty ? io_enq_bits_fun_amomax_d : ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amominu_d = empty ? io_enq_bits_fun_amominu_d : ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_amomaxu_d = empty ? io_enq_bits_fun_amomaxu_d : ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_flw = empty ? io_enq_bits_fun_flw : ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_fsw = empty ? io_enq_bits_fun_fsw : ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_fld = empty ? io_enq_bits_fun_fld : ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_fsd = empty ? io_enq_bits_fun_fsd : ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_probe = empty ? io_enq_bits_fun_probe : ram_fun_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_grant = empty ? io_enq_bits_fun_grant : ram_fun_grant_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_fun_preft = empty ? io_enq_bits_fun_preft : ram_fun_preft_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_chkIdx_MPORT_en & ram_chkIdx_MPORT_mask) begin
      ram_chkIdx[ram_chkIdx_MPORT_addr] <= ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_paddr_MPORT_en & ram_paddr_MPORT_mask) begin
      ram_paddr[ram_paddr_MPORT_addr] <= ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lb_MPORT_en & ram_fun_lb_MPORT_mask) begin
      ram_fun_lb[ram_fun_lb_MPORT_addr] <= ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lh_MPORT_en & ram_fun_lh_MPORT_mask) begin
      ram_fun_lh[ram_fun_lh_MPORT_addr] <= ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lw_MPORT_en & ram_fun_lw_MPORT_mask) begin
      ram_fun_lw[ram_fun_lw_MPORT_addr] <= ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_ld_MPORT_en & ram_fun_ld_MPORT_mask) begin
      ram_fun_ld[ram_fun_ld_MPORT_addr] <= ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lbu_MPORT_en & ram_fun_lbu_MPORT_mask) begin
      ram_fun_lbu[ram_fun_lbu_MPORT_addr] <= ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lhu_MPORT_en & ram_fun_lhu_MPORT_mask) begin
      ram_fun_lhu[ram_fun_lhu_MPORT_addr] <= ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lwu_MPORT_en & ram_fun_lwu_MPORT_mask) begin
      ram_fun_lwu[ram_fun_lwu_MPORT_addr] <= ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sb_MPORT_en & ram_fun_sb_MPORT_mask) begin
      ram_fun_sb[ram_fun_sb_MPORT_addr] <= ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sh_MPORT_en & ram_fun_sh_MPORT_mask) begin
      ram_fun_sh[ram_fun_sh_MPORT_addr] <= ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sw_MPORT_en & ram_fun_sw_MPORT_mask) begin
      ram_fun_sw[ram_fun_sw_MPORT_addr] <= ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sd_MPORT_en & ram_fun_sd_MPORT_mask) begin
      ram_fun_sd[ram_fun_sd_MPORT_addr] <= ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lr_w_MPORT_en & ram_fun_lr_w_MPORT_mask) begin
      ram_fun_lr_w[ram_fun_lr_w_MPORT_addr] <= ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sc_w_MPORT_en & ram_fun_sc_w_MPORT_mask) begin
      ram_fun_sc_w[ram_fun_sc_w_MPORT_addr] <= ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoswap_w_MPORT_en & ram_fun_amoswap_w_MPORT_mask) begin
      ram_fun_amoswap_w[ram_fun_amoswap_w_MPORT_addr] <= ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoadd_w_MPORT_en & ram_fun_amoadd_w_MPORT_mask) begin
      ram_fun_amoadd_w[ram_fun_amoadd_w_MPORT_addr] <= ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoxor_w_MPORT_en & ram_fun_amoxor_w_MPORT_mask) begin
      ram_fun_amoxor_w[ram_fun_amoxor_w_MPORT_addr] <= ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoand_w_MPORT_en & ram_fun_amoand_w_MPORT_mask) begin
      ram_fun_amoand_w[ram_fun_amoand_w_MPORT_addr] <= ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoor_w_MPORT_en & ram_fun_amoor_w_MPORT_mask) begin
      ram_fun_amoor_w[ram_fun_amoor_w_MPORT_addr] <= ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomin_w_MPORT_en & ram_fun_amomin_w_MPORT_mask) begin
      ram_fun_amomin_w[ram_fun_amomin_w_MPORT_addr] <= ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomax_w_MPORT_en & ram_fun_amomax_w_MPORT_mask) begin
      ram_fun_amomax_w[ram_fun_amomax_w_MPORT_addr] <= ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amominu_w_MPORT_en & ram_fun_amominu_w_MPORT_mask) begin
      ram_fun_amominu_w[ram_fun_amominu_w_MPORT_addr] <= ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomaxu_w_MPORT_en & ram_fun_amomaxu_w_MPORT_mask) begin
      ram_fun_amomaxu_w[ram_fun_amomaxu_w_MPORT_addr] <= ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lr_d_MPORT_en & ram_fun_lr_d_MPORT_mask) begin
      ram_fun_lr_d[ram_fun_lr_d_MPORT_addr] <= ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sc_d_MPORT_en & ram_fun_sc_d_MPORT_mask) begin
      ram_fun_sc_d[ram_fun_sc_d_MPORT_addr] <= ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoswap_d_MPORT_en & ram_fun_amoswap_d_MPORT_mask) begin
      ram_fun_amoswap_d[ram_fun_amoswap_d_MPORT_addr] <= ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoadd_d_MPORT_en & ram_fun_amoadd_d_MPORT_mask) begin
      ram_fun_amoadd_d[ram_fun_amoadd_d_MPORT_addr] <= ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoxor_d_MPORT_en & ram_fun_amoxor_d_MPORT_mask) begin
      ram_fun_amoxor_d[ram_fun_amoxor_d_MPORT_addr] <= ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoand_d_MPORT_en & ram_fun_amoand_d_MPORT_mask) begin
      ram_fun_amoand_d[ram_fun_amoand_d_MPORT_addr] <= ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoor_d_MPORT_en & ram_fun_amoor_d_MPORT_mask) begin
      ram_fun_amoor_d[ram_fun_amoor_d_MPORT_addr] <= ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomin_d_MPORT_en & ram_fun_amomin_d_MPORT_mask) begin
      ram_fun_amomin_d[ram_fun_amomin_d_MPORT_addr] <= ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomax_d_MPORT_en & ram_fun_amomax_d_MPORT_mask) begin
      ram_fun_amomax_d[ram_fun_amomax_d_MPORT_addr] <= ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amominu_d_MPORT_en & ram_fun_amominu_d_MPORT_mask) begin
      ram_fun_amominu_d[ram_fun_amominu_d_MPORT_addr] <= ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomaxu_d_MPORT_en & ram_fun_amomaxu_d_MPORT_mask) begin
      ram_fun_amomaxu_d[ram_fun_amomaxu_d_MPORT_addr] <= ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_flw_MPORT_en & ram_fun_flw_MPORT_mask) begin
      ram_fun_flw[ram_fun_flw_MPORT_addr] <= ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_fsw_MPORT_en & ram_fun_fsw_MPORT_mask) begin
      ram_fun_fsw[ram_fun_fsw_MPORT_addr] <= ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_fld_MPORT_en & ram_fun_fld_MPORT_mask) begin
      ram_fun_fld[ram_fun_fld_MPORT_addr] <= ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_fsd_MPORT_en & ram_fun_fsd_MPORT_mask) begin
      ram_fun_fsd[ram_fun_fsd_MPORT_addr] <= ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_probe_MPORT_en & ram_fun_probe_MPORT_mask) begin
      ram_fun_probe[ram_fun_probe_MPORT_addr] <= ram_fun_probe_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_grant_MPORT_en & ram_fun_grant_MPORT_mask) begin
      ram_fun_grant[ram_fun_grant_MPORT_addr] <= ram_fun_grant_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_preft_MPORT_en & ram_fun_preft_MPORT_mask) begin
      ram_fun_preft[ram_fun_preft_MPORT_addr] <= ram_fun_preft_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_chkIdx[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_paddr[initvar] = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_lb[initvar] = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_lh[initvar] = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_lw[initvar] = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_ld[initvar] = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_lbu[initvar] = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_lhu[initvar] = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_lwu[initvar] = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_sb[initvar] = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_sh[initvar] = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_sw[initvar] = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_sd[initvar] = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_lr_w[initvar] = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_sc_w[initvar] = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoswap_w[initvar] = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoadd_w[initvar] = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoxor_w[initvar] = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoand_w[initvar] = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoor_w[initvar] = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amomin_w[initvar] = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amomax_w[initvar] = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amominu_w[initvar] = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amomaxu_w[initvar] = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_lr_d[initvar] = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_sc_d[initvar] = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoswap_d[initvar] = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoadd_d[initvar] = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoxor_d[initvar] = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoand_d[initvar] = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amoor_d[initvar] = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amomin_d[initvar] = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amomax_d[initvar] = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amominu_d[initvar] = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_amomaxu_d[initvar] = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_flw[initvar] = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_fsw[initvar] = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_fld[initvar] = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_fsd[initvar] = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_probe[initvar] = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_grant[initvar] = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_fun_preft[initvar] = _RAND_41[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_42 = {1{`RANDOM}};
  enq_ptr_value = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  deq_ptr_value = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  maybe_full = _RAND_44[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_14(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_enq_bits_chkIdx,
  input   io_enq_bits_is_load_amo,
  input   io_enq_bits_is_flw,
  input   io_enq_bits_is_fld,
  input   io_deq_ready,
  output  io_deq_valid,
  output  io_deq_bits_chkIdx,
  output  io_deq_bits_is_load_amo,
  output  io_deq_bits_is_flw,
  output  io_deq_bits_is_fld
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  reg  ram_chkIdx [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_is_load_amo [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_is_load_amo_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_is_load_amo_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_load_amo_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_load_amo_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_load_amo_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_load_amo_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_is_load_amo_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_is_flw [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_is_flw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_is_flw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_flw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_flw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_flw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_is_flw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_is_fld [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_is_fld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_is_fld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_fld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_is_fld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_is_fld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_is_fld_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_17 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_17 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_chkIdx_io_deq_bits_MPORT_en = 1'h1;
  assign ram_chkIdx_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_chkIdx_io_deq_bits_MPORT_data = ram_chkIdx[ram_chkIdx_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_chkIdx_MPORT_data = io_enq_bits_chkIdx;
  assign ram_chkIdx_MPORT_addr = enq_ptr_value;
  assign ram_chkIdx_MPORT_mask = 1'h1;
  assign ram_chkIdx_MPORT_en = empty ? _GEN_17 : _do_enq_T;
  assign ram_is_load_amo_io_deq_bits_MPORT_en = 1'h1;
  assign ram_is_load_amo_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_is_load_amo_io_deq_bits_MPORT_data = ram_is_load_amo[ram_is_load_amo_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_is_load_amo_MPORT_data = io_enq_bits_is_load_amo;
  assign ram_is_load_amo_MPORT_addr = enq_ptr_value;
  assign ram_is_load_amo_MPORT_mask = 1'h1;
  assign ram_is_load_amo_MPORT_en = empty ? _GEN_17 : _do_enq_T;
  assign ram_is_flw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_is_flw_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_is_flw_io_deq_bits_MPORT_data = ram_is_flw[ram_is_flw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_is_flw_MPORT_data = io_enq_bits_is_flw;
  assign ram_is_flw_MPORT_addr = enq_ptr_value;
  assign ram_is_flw_MPORT_mask = 1'h1;
  assign ram_is_flw_MPORT_en = empty ? _GEN_17 : _do_enq_T;
  assign ram_is_fld_io_deq_bits_MPORT_en = 1'h1;
  assign ram_is_fld_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_is_fld_io_deq_bits_MPORT_data = ram_is_fld[ram_is_fld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_is_fld_MPORT_data = io_enq_bits_is_fld;
  assign ram_is_fld_MPORT_addr = enq_ptr_value;
  assign ram_is_fld_MPORT_mask = 1'h1;
  assign ram_is_fld_MPORT_en = empty ? _GEN_17 : _do_enq_T;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_chkIdx = empty ? io_enq_bits_chkIdx : ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_is_load_amo = empty ? io_enq_bits_is_load_amo : ram_is_load_amo_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_is_flw = empty ? io_enq_bits_is_flw : ram_is_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_is_fld = empty ? io_enq_bits_is_fld : ram_is_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_chkIdx_MPORT_en & ram_chkIdx_MPORT_mask) begin
      ram_chkIdx[ram_chkIdx_MPORT_addr] <= ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_is_load_amo_MPORT_en & ram_is_load_amo_MPORT_mask) begin
      ram_is_load_amo[ram_is_load_amo_MPORT_addr] <= ram_is_load_amo_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_is_flw_MPORT_en & ram_is_flw_MPORT_mask) begin
      ram_is_flw[ram_is_flw_MPORT_addr] <= ram_is_flw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_is_fld_MPORT_en & ram_is_fld_MPORT_mask) begin
      ram_is_fld[ram_is_fld_MPORT_addr] <= ram_is_fld_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_chkIdx[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_is_load_amo[initvar] = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_is_flw[initvar] = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_is_fld[initvar] = _RAND_3[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_4 = {1{`RANDOM}};
  enq_ptr_value = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  deq_ptr_value = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  maybe_full = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Arbiter_1(
  output        io_in_0_ready,
  input         io_in_0_valid,
  input         io_in_0_bits_chkIdx,
  input  [31:0] io_in_0_bits_paddr,
  input         io_in_0_bits_fun_lb,
  input         io_in_0_bits_fun_lh,
  input         io_in_0_bits_fun_lw,
  input         io_in_0_bits_fun_ld,
  input         io_in_0_bits_fun_lbu,
  input         io_in_0_bits_fun_lhu,
  input         io_in_0_bits_fun_lwu,
  input         io_in_0_bits_fun_sb,
  input         io_in_0_bits_fun_sh,
  input         io_in_0_bits_fun_sw,
  input         io_in_0_bits_fun_sd,
  input         io_in_0_bits_fun_lr_w,
  input         io_in_0_bits_fun_sc_w,
  input         io_in_0_bits_fun_amoswap_w,
  input         io_in_0_bits_fun_amoadd_w,
  input         io_in_0_bits_fun_amoxor_w,
  input         io_in_0_bits_fun_amoand_w,
  input         io_in_0_bits_fun_amoor_w,
  input         io_in_0_bits_fun_amomin_w,
  input         io_in_0_bits_fun_amomax_w,
  input         io_in_0_bits_fun_amominu_w,
  input         io_in_0_bits_fun_amomaxu_w,
  input         io_in_0_bits_fun_lr_d,
  input         io_in_0_bits_fun_sc_d,
  input         io_in_0_bits_fun_amoswap_d,
  input         io_in_0_bits_fun_amoadd_d,
  input         io_in_0_bits_fun_amoxor_d,
  input         io_in_0_bits_fun_amoand_d,
  input         io_in_0_bits_fun_amoor_d,
  input         io_in_0_bits_fun_amomin_d,
  input         io_in_0_bits_fun_amomax_d,
  input         io_in_0_bits_fun_amominu_d,
  input         io_in_0_bits_fun_amomaxu_d,
  input         io_in_0_bits_fun_flw,
  input         io_in_0_bits_fun_fsw,
  input         io_in_0_bits_fun_fld,
  input         io_in_0_bits_fun_fsd,
  input         io_in_0_bits_fun_probe,
  input         io_in_0_bits_fun_grant,
  input         io_in_0_bits_fun_preft,
  output        io_in_1_ready,
  input         io_in_1_valid,
  input         io_in_1_bits_chkIdx,
  input  [31:0] io_in_1_bits_paddr,
  input         io_in_1_bits_fun_lb,
  input         io_in_1_bits_fun_lh,
  input         io_in_1_bits_fun_lw,
  input         io_in_1_bits_fun_ld,
  input         io_in_1_bits_fun_lbu,
  input         io_in_1_bits_fun_lhu,
  input         io_in_1_bits_fun_lwu,
  input         io_in_1_bits_fun_sb,
  input         io_in_1_bits_fun_sh,
  input         io_in_1_bits_fun_sw,
  input         io_in_1_bits_fun_sd,
  input         io_in_1_bits_fun_lr_w,
  input         io_in_1_bits_fun_sc_w,
  input         io_in_1_bits_fun_amoswap_w,
  input         io_in_1_bits_fun_amoadd_w,
  input         io_in_1_bits_fun_amoxor_w,
  input         io_in_1_bits_fun_amoand_w,
  input         io_in_1_bits_fun_amoor_w,
  input         io_in_1_bits_fun_amomin_w,
  input         io_in_1_bits_fun_amomax_w,
  input         io_in_1_bits_fun_amominu_w,
  input         io_in_1_bits_fun_amomaxu_w,
  input         io_in_1_bits_fun_lr_d,
  input         io_in_1_bits_fun_sc_d,
  input         io_in_1_bits_fun_amoswap_d,
  input         io_in_1_bits_fun_amoadd_d,
  input         io_in_1_bits_fun_amoxor_d,
  input         io_in_1_bits_fun_amoand_d,
  input         io_in_1_bits_fun_amoor_d,
  input         io_in_1_bits_fun_amomin_d,
  input         io_in_1_bits_fun_amomax_d,
  input         io_in_1_bits_fun_amominu_d,
  input         io_in_1_bits_fun_amomaxu_d,
  input         io_in_1_bits_fun_flw,
  input         io_in_1_bits_fun_fsw,
  input         io_in_1_bits_fun_fld,
  input         io_in_1_bits_fun_fsd,
  input         io_out_ready,
  output        io_out_valid,
  output        io_out_bits_chkIdx,
  output [31:0] io_out_bits_paddr,
  output        io_out_bits_fun_lb,
  output        io_out_bits_fun_lh,
  output        io_out_bits_fun_lw,
  output        io_out_bits_fun_ld,
  output        io_out_bits_fun_lbu,
  output        io_out_bits_fun_lhu,
  output        io_out_bits_fun_lwu,
  output        io_out_bits_fun_sb,
  output        io_out_bits_fun_sh,
  output        io_out_bits_fun_sw,
  output        io_out_bits_fun_sd,
  output        io_out_bits_fun_lr_w,
  output        io_out_bits_fun_sc_w,
  output        io_out_bits_fun_amoswap_w,
  output        io_out_bits_fun_amoadd_w,
  output        io_out_bits_fun_amoxor_w,
  output        io_out_bits_fun_amoand_w,
  output        io_out_bits_fun_amoor_w,
  output        io_out_bits_fun_amomin_w,
  output        io_out_bits_fun_amomax_w,
  output        io_out_bits_fun_amominu_w,
  output        io_out_bits_fun_amomaxu_w,
  output        io_out_bits_fun_lr_d,
  output        io_out_bits_fun_sc_d,
  output        io_out_bits_fun_amoswap_d,
  output        io_out_bits_fun_amoadd_d,
  output        io_out_bits_fun_amoxor_d,
  output        io_out_bits_fun_amoand_d,
  output        io_out_bits_fun_amoor_d,
  output        io_out_bits_fun_amomin_d,
  output        io_out_bits_fun_amomax_d,
  output        io_out_bits_fun_amominu_d,
  output        io_out_bits_fun_amomaxu_d,
  output        io_out_bits_fun_flw,
  output        io_out_bits_fun_fsw,
  output        io_out_bits_fun_fld,
  output        io_out_bits_fun_fsd,
  output        io_out_bits_fun_probe,
  output        io_out_bits_fun_grant,
  output        io_out_bits_fun_preft
);
  wire  grant_1 = ~io_in_0_valid; // @[Arbiter.scala 45:78]
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
  assign io_in_1_ready = grant_1 & io_out_ready; // @[Arbiter.scala 146:19]
  assign io_out_valid = ~grant_1 | io_in_1_valid; // @[Arbiter.scala 147:31]
  assign io_out_bits_chkIdx = io_in_0_valid ? io_in_0_bits_chkIdx : io_in_1_bits_chkIdx; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_paddr = io_in_0_valid ? io_in_0_bits_paddr : io_in_1_bits_paddr; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lb = io_in_0_valid ? io_in_0_bits_fun_lb : io_in_1_bits_fun_lb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lh = io_in_0_valid ? io_in_0_bits_fun_lh : io_in_1_bits_fun_lh; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lw = io_in_0_valid ? io_in_0_bits_fun_lw : io_in_1_bits_fun_lw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_ld = io_in_0_valid ? io_in_0_bits_fun_ld : io_in_1_bits_fun_ld; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lbu = io_in_0_valid ? io_in_0_bits_fun_lbu : io_in_1_bits_fun_lbu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lhu = io_in_0_valid ? io_in_0_bits_fun_lhu : io_in_1_bits_fun_lhu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lwu = io_in_0_valid ? io_in_0_bits_fun_lwu : io_in_1_bits_fun_lwu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sb = io_in_0_valid ? io_in_0_bits_fun_sb : io_in_1_bits_fun_sb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sh = io_in_0_valid ? io_in_0_bits_fun_sh : io_in_1_bits_fun_sh; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sw = io_in_0_valid ? io_in_0_bits_fun_sw : io_in_1_bits_fun_sw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sd = io_in_0_valid ? io_in_0_bits_fun_sd : io_in_1_bits_fun_sd; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lr_w = io_in_0_valid ? io_in_0_bits_fun_lr_w : io_in_1_bits_fun_lr_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sc_w = io_in_0_valid ? io_in_0_bits_fun_sc_w : io_in_1_bits_fun_sc_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoswap_w = io_in_0_valid ? io_in_0_bits_fun_amoswap_w : io_in_1_bits_fun_amoswap_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoadd_w = io_in_0_valid ? io_in_0_bits_fun_amoadd_w : io_in_1_bits_fun_amoadd_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoxor_w = io_in_0_valid ? io_in_0_bits_fun_amoxor_w : io_in_1_bits_fun_amoxor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoand_w = io_in_0_valid ? io_in_0_bits_fun_amoand_w : io_in_1_bits_fun_amoand_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoor_w = io_in_0_valid ? io_in_0_bits_fun_amoor_w : io_in_1_bits_fun_amoor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomin_w = io_in_0_valid ? io_in_0_bits_fun_amomin_w : io_in_1_bits_fun_amomin_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomax_w = io_in_0_valid ? io_in_0_bits_fun_amomax_w : io_in_1_bits_fun_amomax_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amominu_w = io_in_0_valid ? io_in_0_bits_fun_amominu_w : io_in_1_bits_fun_amominu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomaxu_w = io_in_0_valid ? io_in_0_bits_fun_amomaxu_w : io_in_1_bits_fun_amomaxu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_lr_d = io_in_0_valid ? io_in_0_bits_fun_lr_d : io_in_1_bits_fun_lr_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_sc_d = io_in_0_valid ? io_in_0_bits_fun_sc_d : io_in_1_bits_fun_sc_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoswap_d = io_in_0_valid ? io_in_0_bits_fun_amoswap_d : io_in_1_bits_fun_amoswap_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoadd_d = io_in_0_valid ? io_in_0_bits_fun_amoadd_d : io_in_1_bits_fun_amoadd_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoxor_d = io_in_0_valid ? io_in_0_bits_fun_amoxor_d : io_in_1_bits_fun_amoxor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoand_d = io_in_0_valid ? io_in_0_bits_fun_amoand_d : io_in_1_bits_fun_amoand_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amoor_d = io_in_0_valid ? io_in_0_bits_fun_amoor_d : io_in_1_bits_fun_amoor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomin_d = io_in_0_valid ? io_in_0_bits_fun_amomin_d : io_in_1_bits_fun_amomin_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomax_d = io_in_0_valid ? io_in_0_bits_fun_amomax_d : io_in_1_bits_fun_amomax_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amominu_d = io_in_0_valid ? io_in_0_bits_fun_amominu_d : io_in_1_bits_fun_amominu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_amomaxu_d = io_in_0_valid ? io_in_0_bits_fun_amomaxu_d : io_in_1_bits_fun_amomaxu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_flw = io_in_0_valid ? io_in_0_bits_fun_flw : io_in_1_bits_fun_flw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_fsw = io_in_0_valid ? io_in_0_bits_fun_fsw : io_in_1_bits_fun_fsw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_fld = io_in_0_valid ? io_in_0_bits_fun_fld : io_in_1_bits_fun_fld; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_fsd = io_in_0_valid ? io_in_0_bits_fun_fsd : io_in_1_bits_fun_fsd; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_probe = io_in_0_valid & io_in_0_bits_fun_probe; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_grant = io_in_0_valid & io_in_0_bits_fun_grant; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_fun_preft = io_in_0_valid & io_in_0_bits_fun_preft; // @[Arbiter.scala 136:15 138:26 140:19]
endmodule
module Arbiter_2(
  input         io_in_0_valid,
  input  [31:0] io_in_0_bits_paddr,
  output        io_in_1_ready,
  input         io_in_1_valid,
  input  [31:0] io_in_1_bits_paddr,
  output        io_in_2_ready,
  input         io_in_2_valid,
  input         io_in_2_bits_chkIdx,
  input  [31:0] io_in_2_bits_paddr,
  input         io_in_2_bits_fun_lb,
  input         io_in_2_bits_fun_lh,
  input         io_in_2_bits_fun_lw,
  input         io_in_2_bits_fun_ld,
  input         io_in_2_bits_fun_lbu,
  input         io_in_2_bits_fun_lhu,
  input         io_in_2_bits_fun_lwu,
  input         io_in_2_bits_fun_sb,
  input         io_in_2_bits_fun_sh,
  input         io_in_2_bits_fun_sw,
  input         io_in_2_bits_fun_sd,
  input         io_in_2_bits_fun_lr_w,
  input         io_in_2_bits_fun_sc_w,
  input         io_in_2_bits_fun_amoswap_w,
  input         io_in_2_bits_fun_amoadd_w,
  input         io_in_2_bits_fun_amoxor_w,
  input         io_in_2_bits_fun_amoand_w,
  input         io_in_2_bits_fun_amoor_w,
  input         io_in_2_bits_fun_amomin_w,
  input         io_in_2_bits_fun_amomax_w,
  input         io_in_2_bits_fun_amominu_w,
  input         io_in_2_bits_fun_amomaxu_w,
  input         io_in_2_bits_fun_lr_d,
  input         io_in_2_bits_fun_sc_d,
  input         io_in_2_bits_fun_amoswap_d,
  input         io_in_2_bits_fun_amoadd_d,
  input         io_in_2_bits_fun_amoxor_d,
  input         io_in_2_bits_fun_amoand_d,
  input         io_in_2_bits_fun_amoor_d,
  input         io_in_2_bits_fun_amomin_d,
  input         io_in_2_bits_fun_amomax_d,
  input         io_in_2_bits_fun_amominu_d,
  input         io_in_2_bits_fun_amomaxu_d,
  input         io_in_2_bits_fun_flw,
  input         io_in_2_bits_fun_fsw,
  input         io_in_2_bits_fun_fld,
  input         io_in_2_bits_fun_fsd,
  input         io_in_2_bits_fun_probe,
  input         io_in_2_bits_fun_grant,
  input         io_in_2_bits_fun_preft,
  output        io_out_valid,
  output        io_out_bits_chkIdx,
  output [31:0] io_out_bits_paddr,
  output        io_out_bits_fun_lb,
  output        io_out_bits_fun_lh,
  output        io_out_bits_fun_lw,
  output        io_out_bits_fun_ld,
  output        io_out_bits_fun_lbu,
  output        io_out_bits_fun_lhu,
  output        io_out_bits_fun_lwu,
  output        io_out_bits_fun_sb,
  output        io_out_bits_fun_sh,
  output        io_out_bits_fun_sw,
  output        io_out_bits_fun_sd,
  output        io_out_bits_fun_lr_w,
  output        io_out_bits_fun_sc_w,
  output        io_out_bits_fun_amoswap_w,
  output        io_out_bits_fun_amoadd_w,
  output        io_out_bits_fun_amoxor_w,
  output        io_out_bits_fun_amoand_w,
  output        io_out_bits_fun_amoor_w,
  output        io_out_bits_fun_amomin_w,
  output        io_out_bits_fun_amomax_w,
  output        io_out_bits_fun_amominu_w,
  output        io_out_bits_fun_amomaxu_w,
  output        io_out_bits_fun_lr_d,
  output        io_out_bits_fun_sc_d,
  output        io_out_bits_fun_amoswap_d,
  output        io_out_bits_fun_amoadd_d,
  output        io_out_bits_fun_amoxor_d,
  output        io_out_bits_fun_amoand_d,
  output        io_out_bits_fun_amoor_d,
  output        io_out_bits_fun_amomin_d,
  output        io_out_bits_fun_amomax_d,
  output        io_out_bits_fun_amominu_d,
  output        io_out_bits_fun_amomaxu_d,
  output        io_out_bits_fun_flw,
  output        io_out_bits_fun_fsw,
  output        io_out_bits_fun_fld,
  output        io_out_bits_fun_fsd,
  output        io_out_bits_fun_probe,
  output        io_out_bits_fun_grant,
  output        io_out_bits_fun_preft
);
  wire  _GEN_1 = io_in_1_valid ? 1'h0 : io_in_2_bits_chkIdx; // @[Arbiter.scala 136:15 138:26 140:19]
  wire [31:0] _GEN_2 = io_in_1_valid ? io_in_1_bits_paddr : io_in_2_bits_paddr; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_5 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_lb; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_6 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_lh; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_7 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_lw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_8 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_ld; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_9 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_lbu; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_10 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_lhu; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_11 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_lwu; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_12 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_sb; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_13 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_sh; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_14 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_sw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_15 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_sd; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_19 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_lr_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_20 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_sc_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_21 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoswap_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_22 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoadd_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_23 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoxor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_24 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoand_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_25 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_26 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amomin_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_27 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amomax_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_28 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amominu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_29 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amomaxu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_30 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_lr_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_31 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_sc_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_32 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoswap_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_33 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoadd_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_34 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoxor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_35 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoand_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_36 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amoor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_37 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amomin_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_38 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amomax_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_39 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amominu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_40 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_amomaxu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_41 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_flw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_42 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_fsw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_43 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_fld; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_44 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_fsd; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_45 = io_in_1_valid | io_in_2_bits_fun_probe; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_46 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_grant; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_47 = io_in_1_valid ? 1'h0 : io_in_2_bits_fun_preft; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  grant_2 = ~(io_in_0_valid | io_in_1_valid); // @[Arbiter.scala 45:78]
  assign io_in_1_ready = ~io_in_0_valid; // @[Arbiter.scala 45:78]
  assign io_in_2_ready = ~(io_in_0_valid | io_in_1_valid); // @[Arbiter.scala 45:78]
  assign io_out_valid = ~grant_2 | io_in_2_valid; // @[Arbiter.scala 147:31]
  assign io_out_bits_chkIdx = io_in_0_valid ? 1'h0 : _GEN_1; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_paddr = io_in_0_valid ? io_in_0_bits_paddr : _GEN_2; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_lb = io_in_0_valid ? 1'h0 : _GEN_5; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_lh = io_in_0_valid ? 1'h0 : _GEN_6; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_lw = io_in_0_valid ? 1'h0 : _GEN_7; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_ld = io_in_0_valid ? 1'h0 : _GEN_8; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_lbu = io_in_0_valid ? 1'h0 : _GEN_9; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_lhu = io_in_0_valid ? 1'h0 : _GEN_10; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_lwu = io_in_0_valid ? 1'h0 : _GEN_11; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_sb = io_in_0_valid ? 1'h0 : _GEN_12; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_sh = io_in_0_valid ? 1'h0 : _GEN_13; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_sw = io_in_0_valid ? 1'h0 : _GEN_14; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_sd = io_in_0_valid ? 1'h0 : _GEN_15; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_lr_w = io_in_0_valid ? 1'h0 : _GEN_19; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_sc_w = io_in_0_valid ? 1'h0 : _GEN_20; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoswap_w = io_in_0_valid ? 1'h0 : _GEN_21; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoadd_w = io_in_0_valid ? 1'h0 : _GEN_22; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoxor_w = io_in_0_valid ? 1'h0 : _GEN_23; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoand_w = io_in_0_valid ? 1'h0 : _GEN_24; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoor_w = io_in_0_valid ? 1'h0 : _GEN_25; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amomin_w = io_in_0_valid ? 1'h0 : _GEN_26; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amomax_w = io_in_0_valid ? 1'h0 : _GEN_27; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amominu_w = io_in_0_valid ? 1'h0 : _GEN_28; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amomaxu_w = io_in_0_valid ? 1'h0 : _GEN_29; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_lr_d = io_in_0_valid ? 1'h0 : _GEN_30; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_sc_d = io_in_0_valid ? 1'h0 : _GEN_31; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoswap_d = io_in_0_valid ? 1'h0 : _GEN_32; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoadd_d = io_in_0_valid ? 1'h0 : _GEN_33; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoxor_d = io_in_0_valid ? 1'h0 : _GEN_34; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoand_d = io_in_0_valid ? 1'h0 : _GEN_35; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amoor_d = io_in_0_valid ? 1'h0 : _GEN_36; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amomin_d = io_in_0_valid ? 1'h0 : _GEN_37; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amomax_d = io_in_0_valid ? 1'h0 : _GEN_38; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amominu_d = io_in_0_valid ? 1'h0 : _GEN_39; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_amomaxu_d = io_in_0_valid ? 1'h0 : _GEN_40; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_flw = io_in_0_valid ? 1'h0 : _GEN_41; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_fsw = io_in_0_valid ? 1'h0 : _GEN_42; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_fld = io_in_0_valid ? 1'h0 : _GEN_43; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_fsd = io_in_0_valid ? 1'h0 : _GEN_44; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_probe = io_in_0_valid ? 1'h0 : _GEN_45; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_grant = io_in_0_valid | _GEN_46; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_fun_preft = io_in_0_valid ? 1'h0 : _GEN_47; // @[Arbiter.scala 138:26 140:19]
endmodule
module Queue_15(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_chkIdx,
  input  [31:0] io_enq_bits_paddr,
  input         io_enq_bits_fun_lb,
  input         io_enq_bits_fun_lh,
  input         io_enq_bits_fun_lw,
  input         io_enq_bits_fun_ld,
  input         io_enq_bits_fun_lbu,
  input         io_enq_bits_fun_lhu,
  input         io_enq_bits_fun_lwu,
  input         io_enq_bits_fun_sb,
  input         io_enq_bits_fun_sh,
  input         io_enq_bits_fun_sw,
  input         io_enq_bits_fun_sd,
  input         io_enq_bits_fun_lr_w,
  input         io_enq_bits_fun_sc_w,
  input         io_enq_bits_fun_amoswap_w,
  input         io_enq_bits_fun_amoadd_w,
  input         io_enq_bits_fun_amoxor_w,
  input         io_enq_bits_fun_amoand_w,
  input         io_enq_bits_fun_amoor_w,
  input         io_enq_bits_fun_amomin_w,
  input         io_enq_bits_fun_amomax_w,
  input         io_enq_bits_fun_amominu_w,
  input         io_enq_bits_fun_amomaxu_w,
  input         io_enq_bits_fun_lr_d,
  input         io_enq_bits_fun_sc_d,
  input         io_enq_bits_fun_amoswap_d,
  input         io_enq_bits_fun_amoadd_d,
  input         io_enq_bits_fun_amoxor_d,
  input         io_enq_bits_fun_amoand_d,
  input         io_enq_bits_fun_amoor_d,
  input         io_enq_bits_fun_amomin_d,
  input         io_enq_bits_fun_amomax_d,
  input         io_enq_bits_fun_amominu_d,
  input         io_enq_bits_fun_amomaxu_d,
  input         io_enq_bits_fun_flw,
  input         io_enq_bits_fun_fsw,
  input         io_enq_bits_fun_fld,
  input         io_enq_bits_fun_fsd,
  input         io_enq_bits_fun_probe,
  input         io_enq_bits_fun_grant,
  input         io_enq_bits_fun_preft,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_chkIdx,
  output [31:0] io_deq_bits_paddr,
  output        io_deq_bits_fun_lb,
  output        io_deq_bits_fun_lh,
  output        io_deq_bits_fun_lw,
  output        io_deq_bits_fun_ld,
  output        io_deq_bits_fun_lbu,
  output        io_deq_bits_fun_lhu,
  output        io_deq_bits_fun_lwu,
  output        io_deq_bits_fun_sb,
  output        io_deq_bits_fun_sh,
  output        io_deq_bits_fun_sw,
  output        io_deq_bits_fun_sd,
  output        io_deq_bits_fun_lr_w,
  output        io_deq_bits_fun_sc_w,
  output        io_deq_bits_fun_amoswap_w,
  output        io_deq_bits_fun_amoadd_w,
  output        io_deq_bits_fun_amoxor_w,
  output        io_deq_bits_fun_amoand_w,
  output        io_deq_bits_fun_amoor_w,
  output        io_deq_bits_fun_amomin_w,
  output        io_deq_bits_fun_amomax_w,
  output        io_deq_bits_fun_amominu_w,
  output        io_deq_bits_fun_amomaxu_w,
  output        io_deq_bits_fun_lr_d,
  output        io_deq_bits_fun_sc_d,
  output        io_deq_bits_fun_amoswap_d,
  output        io_deq_bits_fun_amoadd_d,
  output        io_deq_bits_fun_amoxor_d,
  output        io_deq_bits_fun_amoand_d,
  output        io_deq_bits_fun_amoor_d,
  output        io_deq_bits_fun_amomin_d,
  output        io_deq_bits_fun_amomax_d,
  output        io_deq_bits_fun_amominu_d,
  output        io_deq_bits_fun_amomaxu_d,
  output        io_deq_bits_fun_flw,
  output        io_deq_bits_fun_fsw,
  output        io_deq_bits_fun_fld,
  output        io_deq_bits_fun_fsd,
  output        io_deq_bits_fun_probe,
  output        io_deq_bits_fun_grant,
  output        io_deq_bits_fun_preft
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_42;
`endif // RANDOMIZE_REG_INIT
  reg  ram_chkIdx [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_chkIdx_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_paddr [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_paddr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_paddr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_paddr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_paddr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_paddr_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lb [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lb_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lh [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lh_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lw [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_ld [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_ld_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lbu [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lbu_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lhu [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lhu_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lwu [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lwu_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sb [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sb_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sh [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sh_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sw [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sd [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sd_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lr_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sc_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoswap_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoadd_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoxor_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoand_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoor_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomin_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomax_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amominu_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomaxu_w [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_w_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_lr_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_lr_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_sc_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_sc_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoswap_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoswap_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoadd_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoadd_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoxor_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoxor_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoand_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoand_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amoor_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amoor_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomin_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomin_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomax_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomax_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amominu_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amominu_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_amomaxu_d [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_amomaxu_d_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_flw [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_flw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_fsw [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsw_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_fld [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_fld_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_fsd [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_fsd_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_probe [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_probe_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_grant [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_grant_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_fun_preft [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_fun_preft_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_chkIdx_io_deq_bits_MPORT_en = 1'h1;
  assign ram_chkIdx_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_chkIdx_io_deq_bits_MPORT_data = ram_chkIdx[ram_chkIdx_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_chkIdx_MPORT_data = io_enq_bits_chkIdx;
  assign ram_chkIdx_MPORT_addr = 1'h0;
  assign ram_chkIdx_MPORT_mask = 1'h1;
  assign ram_chkIdx_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_paddr_io_deq_bits_MPORT_en = 1'h1;
  assign ram_paddr_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_paddr_io_deq_bits_MPORT_data = ram_paddr[ram_paddr_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_paddr_MPORT_data = io_enq_bits_paddr;
  assign ram_paddr_MPORT_addr = 1'h0;
  assign ram_paddr_MPORT_mask = 1'h1;
  assign ram_paddr_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_lb_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lb_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_lb_io_deq_bits_MPORT_data = ram_fun_lb[ram_fun_lb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lb_MPORT_data = io_enq_bits_fun_lb;
  assign ram_fun_lb_MPORT_addr = 1'h0;
  assign ram_fun_lb_MPORT_mask = 1'h1;
  assign ram_fun_lb_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_lh_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lh_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_lh_io_deq_bits_MPORT_data = ram_fun_lh[ram_fun_lh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lh_MPORT_data = io_enq_bits_fun_lh;
  assign ram_fun_lh_MPORT_addr = 1'h0;
  assign ram_fun_lh_MPORT_mask = 1'h1;
  assign ram_fun_lh_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_lw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lw_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_lw_io_deq_bits_MPORT_data = ram_fun_lw[ram_fun_lw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lw_MPORT_data = io_enq_bits_fun_lw;
  assign ram_fun_lw_MPORT_addr = 1'h0;
  assign ram_fun_lw_MPORT_mask = 1'h1;
  assign ram_fun_lw_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_ld_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_ld_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_ld_io_deq_bits_MPORT_data = ram_fun_ld[ram_fun_ld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_ld_MPORT_data = io_enq_bits_fun_ld;
  assign ram_fun_ld_MPORT_addr = 1'h0;
  assign ram_fun_ld_MPORT_mask = 1'h1;
  assign ram_fun_ld_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_lbu_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lbu_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_lbu_io_deq_bits_MPORT_data = ram_fun_lbu[ram_fun_lbu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lbu_MPORT_data = io_enq_bits_fun_lbu;
  assign ram_fun_lbu_MPORT_addr = 1'h0;
  assign ram_fun_lbu_MPORT_mask = 1'h1;
  assign ram_fun_lbu_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_lhu_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lhu_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_lhu_io_deq_bits_MPORT_data = ram_fun_lhu[ram_fun_lhu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lhu_MPORT_data = io_enq_bits_fun_lhu;
  assign ram_fun_lhu_MPORT_addr = 1'h0;
  assign ram_fun_lhu_MPORT_mask = 1'h1;
  assign ram_fun_lhu_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_lwu_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lwu_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_lwu_io_deq_bits_MPORT_data = ram_fun_lwu[ram_fun_lwu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lwu_MPORT_data = io_enq_bits_fun_lwu;
  assign ram_fun_lwu_MPORT_addr = 1'h0;
  assign ram_fun_lwu_MPORT_mask = 1'h1;
  assign ram_fun_lwu_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_sb_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sb_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_sb_io_deq_bits_MPORT_data = ram_fun_sb[ram_fun_sb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sb_MPORT_data = io_enq_bits_fun_sb;
  assign ram_fun_sb_MPORT_addr = 1'h0;
  assign ram_fun_sb_MPORT_mask = 1'h1;
  assign ram_fun_sb_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_sh_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sh_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_sh_io_deq_bits_MPORT_data = ram_fun_sh[ram_fun_sh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sh_MPORT_data = io_enq_bits_fun_sh;
  assign ram_fun_sh_MPORT_addr = 1'h0;
  assign ram_fun_sh_MPORT_mask = 1'h1;
  assign ram_fun_sh_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_sw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sw_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_sw_io_deq_bits_MPORT_data = ram_fun_sw[ram_fun_sw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sw_MPORT_data = io_enq_bits_fun_sw;
  assign ram_fun_sw_MPORT_addr = 1'h0;
  assign ram_fun_sw_MPORT_mask = 1'h1;
  assign ram_fun_sw_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_sd_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sd_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_sd_io_deq_bits_MPORT_data = ram_fun_sd[ram_fun_sd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sd_MPORT_data = io_enq_bits_fun_sd;
  assign ram_fun_sd_MPORT_addr = 1'h0;
  assign ram_fun_sd_MPORT_mask = 1'h1;
  assign ram_fun_sd_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_lr_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lr_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_lr_w_io_deq_bits_MPORT_data = ram_fun_lr_w[ram_fun_lr_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lr_w_MPORT_data = io_enq_bits_fun_lr_w;
  assign ram_fun_lr_w_MPORT_addr = 1'h0;
  assign ram_fun_lr_w_MPORT_mask = 1'h1;
  assign ram_fun_lr_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_sc_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sc_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_sc_w_io_deq_bits_MPORT_data = ram_fun_sc_w[ram_fun_sc_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sc_w_MPORT_data = io_enq_bits_fun_sc_w;
  assign ram_fun_sc_w_MPORT_addr = 1'h0;
  assign ram_fun_sc_w_MPORT_mask = 1'h1;
  assign ram_fun_sc_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoswap_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoswap_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoswap_w_io_deq_bits_MPORT_data = ram_fun_amoswap_w[ram_fun_amoswap_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoswap_w_MPORT_data = io_enq_bits_fun_amoswap_w;
  assign ram_fun_amoswap_w_MPORT_addr = 1'h0;
  assign ram_fun_amoswap_w_MPORT_mask = 1'h1;
  assign ram_fun_amoswap_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoadd_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoadd_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoadd_w_io_deq_bits_MPORT_data = ram_fun_amoadd_w[ram_fun_amoadd_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoadd_w_MPORT_data = io_enq_bits_fun_amoadd_w;
  assign ram_fun_amoadd_w_MPORT_addr = 1'h0;
  assign ram_fun_amoadd_w_MPORT_mask = 1'h1;
  assign ram_fun_amoadd_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoxor_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoxor_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoxor_w_io_deq_bits_MPORT_data = ram_fun_amoxor_w[ram_fun_amoxor_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoxor_w_MPORT_data = io_enq_bits_fun_amoxor_w;
  assign ram_fun_amoxor_w_MPORT_addr = 1'h0;
  assign ram_fun_amoxor_w_MPORT_mask = 1'h1;
  assign ram_fun_amoxor_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoand_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoand_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoand_w_io_deq_bits_MPORT_data = ram_fun_amoand_w[ram_fun_amoand_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoand_w_MPORT_data = io_enq_bits_fun_amoand_w;
  assign ram_fun_amoand_w_MPORT_addr = 1'h0;
  assign ram_fun_amoand_w_MPORT_mask = 1'h1;
  assign ram_fun_amoand_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoor_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoor_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoor_w_io_deq_bits_MPORT_data = ram_fun_amoor_w[ram_fun_amoor_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoor_w_MPORT_data = io_enq_bits_fun_amoor_w;
  assign ram_fun_amoor_w_MPORT_addr = 1'h0;
  assign ram_fun_amoor_w_MPORT_mask = 1'h1;
  assign ram_fun_amoor_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amomin_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomin_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amomin_w_io_deq_bits_MPORT_data = ram_fun_amomin_w[ram_fun_amomin_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomin_w_MPORT_data = io_enq_bits_fun_amomin_w;
  assign ram_fun_amomin_w_MPORT_addr = 1'h0;
  assign ram_fun_amomin_w_MPORT_mask = 1'h1;
  assign ram_fun_amomin_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amomax_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomax_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amomax_w_io_deq_bits_MPORT_data = ram_fun_amomax_w[ram_fun_amomax_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomax_w_MPORT_data = io_enq_bits_fun_amomax_w;
  assign ram_fun_amomax_w_MPORT_addr = 1'h0;
  assign ram_fun_amomax_w_MPORT_mask = 1'h1;
  assign ram_fun_amomax_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amominu_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amominu_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amominu_w_io_deq_bits_MPORT_data = ram_fun_amominu_w[ram_fun_amominu_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amominu_w_MPORT_data = io_enq_bits_fun_amominu_w;
  assign ram_fun_amominu_w_MPORT_addr = 1'h0;
  assign ram_fun_amominu_w_MPORT_mask = 1'h1;
  assign ram_fun_amominu_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amomaxu_w_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomaxu_w_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amomaxu_w_io_deq_bits_MPORT_data = ram_fun_amomaxu_w[ram_fun_amomaxu_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomaxu_w_MPORT_data = io_enq_bits_fun_amomaxu_w;
  assign ram_fun_amomaxu_w_MPORT_addr = 1'h0;
  assign ram_fun_amomaxu_w_MPORT_mask = 1'h1;
  assign ram_fun_amomaxu_w_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_lr_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_lr_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_lr_d_io_deq_bits_MPORT_data = ram_fun_lr_d[ram_fun_lr_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_lr_d_MPORT_data = io_enq_bits_fun_lr_d;
  assign ram_fun_lr_d_MPORT_addr = 1'h0;
  assign ram_fun_lr_d_MPORT_mask = 1'h1;
  assign ram_fun_lr_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_sc_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_sc_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_sc_d_io_deq_bits_MPORT_data = ram_fun_sc_d[ram_fun_sc_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_sc_d_MPORT_data = io_enq_bits_fun_sc_d;
  assign ram_fun_sc_d_MPORT_addr = 1'h0;
  assign ram_fun_sc_d_MPORT_mask = 1'h1;
  assign ram_fun_sc_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoswap_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoswap_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoswap_d_io_deq_bits_MPORT_data = ram_fun_amoswap_d[ram_fun_amoswap_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoswap_d_MPORT_data = io_enq_bits_fun_amoswap_d;
  assign ram_fun_amoswap_d_MPORT_addr = 1'h0;
  assign ram_fun_amoswap_d_MPORT_mask = 1'h1;
  assign ram_fun_amoswap_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoadd_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoadd_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoadd_d_io_deq_bits_MPORT_data = ram_fun_amoadd_d[ram_fun_amoadd_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoadd_d_MPORT_data = io_enq_bits_fun_amoadd_d;
  assign ram_fun_amoadd_d_MPORT_addr = 1'h0;
  assign ram_fun_amoadd_d_MPORT_mask = 1'h1;
  assign ram_fun_amoadd_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoxor_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoxor_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoxor_d_io_deq_bits_MPORT_data = ram_fun_amoxor_d[ram_fun_amoxor_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoxor_d_MPORT_data = io_enq_bits_fun_amoxor_d;
  assign ram_fun_amoxor_d_MPORT_addr = 1'h0;
  assign ram_fun_amoxor_d_MPORT_mask = 1'h1;
  assign ram_fun_amoxor_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoand_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoand_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoand_d_io_deq_bits_MPORT_data = ram_fun_amoand_d[ram_fun_amoand_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoand_d_MPORT_data = io_enq_bits_fun_amoand_d;
  assign ram_fun_amoand_d_MPORT_addr = 1'h0;
  assign ram_fun_amoand_d_MPORT_mask = 1'h1;
  assign ram_fun_amoand_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amoor_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amoor_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amoor_d_io_deq_bits_MPORT_data = ram_fun_amoor_d[ram_fun_amoor_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amoor_d_MPORT_data = io_enq_bits_fun_amoor_d;
  assign ram_fun_amoor_d_MPORT_addr = 1'h0;
  assign ram_fun_amoor_d_MPORT_mask = 1'h1;
  assign ram_fun_amoor_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amomin_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomin_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amomin_d_io_deq_bits_MPORT_data = ram_fun_amomin_d[ram_fun_amomin_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomin_d_MPORT_data = io_enq_bits_fun_amomin_d;
  assign ram_fun_amomin_d_MPORT_addr = 1'h0;
  assign ram_fun_amomin_d_MPORT_mask = 1'h1;
  assign ram_fun_amomin_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amomax_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomax_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amomax_d_io_deq_bits_MPORT_data = ram_fun_amomax_d[ram_fun_amomax_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomax_d_MPORT_data = io_enq_bits_fun_amomax_d;
  assign ram_fun_amomax_d_MPORT_addr = 1'h0;
  assign ram_fun_amomax_d_MPORT_mask = 1'h1;
  assign ram_fun_amomax_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amominu_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amominu_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amominu_d_io_deq_bits_MPORT_data = ram_fun_amominu_d[ram_fun_amominu_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amominu_d_MPORT_data = io_enq_bits_fun_amominu_d;
  assign ram_fun_amominu_d_MPORT_addr = 1'h0;
  assign ram_fun_amominu_d_MPORT_mask = 1'h1;
  assign ram_fun_amominu_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_amomaxu_d_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_amomaxu_d_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_amomaxu_d_io_deq_bits_MPORT_data = ram_fun_amomaxu_d[ram_fun_amomaxu_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_amomaxu_d_MPORT_data = io_enq_bits_fun_amomaxu_d;
  assign ram_fun_amomaxu_d_MPORT_addr = 1'h0;
  assign ram_fun_amomaxu_d_MPORT_mask = 1'h1;
  assign ram_fun_amomaxu_d_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_flw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_flw_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_flw_io_deq_bits_MPORT_data = ram_fun_flw[ram_fun_flw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_flw_MPORT_data = io_enq_bits_fun_flw;
  assign ram_fun_flw_MPORT_addr = 1'h0;
  assign ram_fun_flw_MPORT_mask = 1'h1;
  assign ram_fun_flw_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_fsw_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_fsw_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_fsw_io_deq_bits_MPORT_data = ram_fun_fsw[ram_fun_fsw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_fsw_MPORT_data = io_enq_bits_fun_fsw;
  assign ram_fun_fsw_MPORT_addr = 1'h0;
  assign ram_fun_fsw_MPORT_mask = 1'h1;
  assign ram_fun_fsw_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_fld_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_fld_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_fld_io_deq_bits_MPORT_data = ram_fun_fld[ram_fun_fld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_fld_MPORT_data = io_enq_bits_fun_fld;
  assign ram_fun_fld_MPORT_addr = 1'h0;
  assign ram_fun_fld_MPORT_mask = 1'h1;
  assign ram_fun_fld_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_fsd_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_fsd_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_fsd_io_deq_bits_MPORT_data = ram_fun_fsd[ram_fun_fsd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_fsd_MPORT_data = io_enq_bits_fun_fsd;
  assign ram_fun_fsd_MPORT_addr = 1'h0;
  assign ram_fun_fsd_MPORT_mask = 1'h1;
  assign ram_fun_fsd_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_probe_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_probe_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_probe_io_deq_bits_MPORT_data = ram_fun_probe[ram_fun_probe_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_probe_MPORT_data = io_enq_bits_fun_probe;
  assign ram_fun_probe_MPORT_addr = 1'h0;
  assign ram_fun_probe_MPORT_mask = 1'h1;
  assign ram_fun_probe_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_grant_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_grant_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_grant_io_deq_bits_MPORT_data = ram_fun_grant[ram_fun_grant_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_grant_MPORT_data = io_enq_bits_fun_grant;
  assign ram_fun_grant_MPORT_addr = 1'h0;
  assign ram_fun_grant_MPORT_mask = 1'h1;
  assign ram_fun_grant_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_fun_preft_io_deq_bits_MPORT_en = 1'h1;
  assign ram_fun_preft_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_fun_preft_io_deq_bits_MPORT_data = ram_fun_preft[ram_fun_preft_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_fun_preft_MPORT_data = io_enq_bits_fun_preft;
  assign ram_fun_preft_MPORT_addr = 1'h0;
  assign ram_fun_preft_MPORT_mask = 1'h1;
  assign ram_fun_preft_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = io_deq_ready | empty; // @[Decoupled.scala 305:16 325:{24,39}]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_chkIdx = ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_paddr = ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_lb = ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_lh = ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_lw = ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_ld = ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_lbu = ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_lhu = ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_lwu = ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_sb = ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_sh = ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_sw = ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_sd = ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_lr_w = ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_sc_w = ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoswap_w = ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoadd_w = ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoxor_w = ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoand_w = ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoor_w = ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amomin_w = ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amomax_w = ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amominu_w = ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amomaxu_w = ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_lr_d = ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_sc_d = ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoswap_d = ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoadd_d = ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoxor_d = ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoand_d = ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amoor_d = ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amomin_d = ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amomax_d = ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amominu_d = ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_amomaxu_d = ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_flw = ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_fsw = ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_fld = ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_fsd = ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_probe = ram_fun_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_grant = ram_fun_grant_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_fun_preft = ram_fun_preft_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_chkIdx_MPORT_en & ram_chkIdx_MPORT_mask) begin
      ram_chkIdx[ram_chkIdx_MPORT_addr] <= ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_paddr_MPORT_en & ram_paddr_MPORT_mask) begin
      ram_paddr[ram_paddr_MPORT_addr] <= ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lb_MPORT_en & ram_fun_lb_MPORT_mask) begin
      ram_fun_lb[ram_fun_lb_MPORT_addr] <= ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lh_MPORT_en & ram_fun_lh_MPORT_mask) begin
      ram_fun_lh[ram_fun_lh_MPORT_addr] <= ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lw_MPORT_en & ram_fun_lw_MPORT_mask) begin
      ram_fun_lw[ram_fun_lw_MPORT_addr] <= ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_ld_MPORT_en & ram_fun_ld_MPORT_mask) begin
      ram_fun_ld[ram_fun_ld_MPORT_addr] <= ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lbu_MPORT_en & ram_fun_lbu_MPORT_mask) begin
      ram_fun_lbu[ram_fun_lbu_MPORT_addr] <= ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lhu_MPORT_en & ram_fun_lhu_MPORT_mask) begin
      ram_fun_lhu[ram_fun_lhu_MPORT_addr] <= ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lwu_MPORT_en & ram_fun_lwu_MPORT_mask) begin
      ram_fun_lwu[ram_fun_lwu_MPORT_addr] <= ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sb_MPORT_en & ram_fun_sb_MPORT_mask) begin
      ram_fun_sb[ram_fun_sb_MPORT_addr] <= ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sh_MPORT_en & ram_fun_sh_MPORT_mask) begin
      ram_fun_sh[ram_fun_sh_MPORT_addr] <= ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sw_MPORT_en & ram_fun_sw_MPORT_mask) begin
      ram_fun_sw[ram_fun_sw_MPORT_addr] <= ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sd_MPORT_en & ram_fun_sd_MPORT_mask) begin
      ram_fun_sd[ram_fun_sd_MPORT_addr] <= ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lr_w_MPORT_en & ram_fun_lr_w_MPORT_mask) begin
      ram_fun_lr_w[ram_fun_lr_w_MPORT_addr] <= ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sc_w_MPORT_en & ram_fun_sc_w_MPORT_mask) begin
      ram_fun_sc_w[ram_fun_sc_w_MPORT_addr] <= ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoswap_w_MPORT_en & ram_fun_amoswap_w_MPORT_mask) begin
      ram_fun_amoswap_w[ram_fun_amoswap_w_MPORT_addr] <= ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoadd_w_MPORT_en & ram_fun_amoadd_w_MPORT_mask) begin
      ram_fun_amoadd_w[ram_fun_amoadd_w_MPORT_addr] <= ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoxor_w_MPORT_en & ram_fun_amoxor_w_MPORT_mask) begin
      ram_fun_amoxor_w[ram_fun_amoxor_w_MPORT_addr] <= ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoand_w_MPORT_en & ram_fun_amoand_w_MPORT_mask) begin
      ram_fun_amoand_w[ram_fun_amoand_w_MPORT_addr] <= ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoor_w_MPORT_en & ram_fun_amoor_w_MPORT_mask) begin
      ram_fun_amoor_w[ram_fun_amoor_w_MPORT_addr] <= ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomin_w_MPORT_en & ram_fun_amomin_w_MPORT_mask) begin
      ram_fun_amomin_w[ram_fun_amomin_w_MPORT_addr] <= ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomax_w_MPORT_en & ram_fun_amomax_w_MPORT_mask) begin
      ram_fun_amomax_w[ram_fun_amomax_w_MPORT_addr] <= ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amominu_w_MPORT_en & ram_fun_amominu_w_MPORT_mask) begin
      ram_fun_amominu_w[ram_fun_amominu_w_MPORT_addr] <= ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomaxu_w_MPORT_en & ram_fun_amomaxu_w_MPORT_mask) begin
      ram_fun_amomaxu_w[ram_fun_amomaxu_w_MPORT_addr] <= ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_lr_d_MPORT_en & ram_fun_lr_d_MPORT_mask) begin
      ram_fun_lr_d[ram_fun_lr_d_MPORT_addr] <= ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_sc_d_MPORT_en & ram_fun_sc_d_MPORT_mask) begin
      ram_fun_sc_d[ram_fun_sc_d_MPORT_addr] <= ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoswap_d_MPORT_en & ram_fun_amoswap_d_MPORT_mask) begin
      ram_fun_amoswap_d[ram_fun_amoswap_d_MPORT_addr] <= ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoadd_d_MPORT_en & ram_fun_amoadd_d_MPORT_mask) begin
      ram_fun_amoadd_d[ram_fun_amoadd_d_MPORT_addr] <= ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoxor_d_MPORT_en & ram_fun_amoxor_d_MPORT_mask) begin
      ram_fun_amoxor_d[ram_fun_amoxor_d_MPORT_addr] <= ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoand_d_MPORT_en & ram_fun_amoand_d_MPORT_mask) begin
      ram_fun_amoand_d[ram_fun_amoand_d_MPORT_addr] <= ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amoor_d_MPORT_en & ram_fun_amoor_d_MPORT_mask) begin
      ram_fun_amoor_d[ram_fun_amoor_d_MPORT_addr] <= ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomin_d_MPORT_en & ram_fun_amomin_d_MPORT_mask) begin
      ram_fun_amomin_d[ram_fun_amomin_d_MPORT_addr] <= ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomax_d_MPORT_en & ram_fun_amomax_d_MPORT_mask) begin
      ram_fun_amomax_d[ram_fun_amomax_d_MPORT_addr] <= ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amominu_d_MPORT_en & ram_fun_amominu_d_MPORT_mask) begin
      ram_fun_amominu_d[ram_fun_amominu_d_MPORT_addr] <= ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_amomaxu_d_MPORT_en & ram_fun_amomaxu_d_MPORT_mask) begin
      ram_fun_amomaxu_d[ram_fun_amomaxu_d_MPORT_addr] <= ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_flw_MPORT_en & ram_fun_flw_MPORT_mask) begin
      ram_fun_flw[ram_fun_flw_MPORT_addr] <= ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_fsw_MPORT_en & ram_fun_fsw_MPORT_mask) begin
      ram_fun_fsw[ram_fun_fsw_MPORT_addr] <= ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_fld_MPORT_en & ram_fun_fld_MPORT_mask) begin
      ram_fun_fld[ram_fun_fld_MPORT_addr] <= ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_fsd_MPORT_en & ram_fun_fsd_MPORT_mask) begin
      ram_fun_fsd[ram_fun_fsd_MPORT_addr] <= ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_probe_MPORT_en & ram_fun_probe_MPORT_mask) begin
      ram_fun_probe[ram_fun_probe_MPORT_addr] <= ram_fun_probe_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_grant_MPORT_en & ram_fun_grant_MPORT_mask) begin
      ram_fun_grant[ram_fun_grant_MPORT_addr] <= ram_fun_grant_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_fun_preft_MPORT_en & ram_fun_preft_MPORT_mask) begin
      ram_fun_preft[ram_fun_preft_MPORT_addr] <= ram_fun_preft_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_chkIdx[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_paddr[initvar] = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_lb[initvar] = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_lh[initvar] = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_lw[initvar] = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_ld[initvar] = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_lbu[initvar] = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_lhu[initvar] = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_lwu[initvar] = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_sb[initvar] = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_sh[initvar] = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_sw[initvar] = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_sd[initvar] = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_lr_w[initvar] = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_sc_w[initvar] = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoswap_w[initvar] = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoadd_w[initvar] = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoxor_w[initvar] = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoand_w[initvar] = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoor_w[initvar] = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amomin_w[initvar] = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amomax_w[initvar] = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amominu_w[initvar] = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amomaxu_w[initvar] = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_lr_d[initvar] = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_sc_d[initvar] = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoswap_d[initvar] = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoadd_d[initvar] = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoxor_d[initvar] = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoand_d[initvar] = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amoor_d[initvar] = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amomin_d[initvar] = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amomax_d[initvar] = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amominu_d[initvar] = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_amomaxu_d[initvar] = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_flw[initvar] = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_fsw[initvar] = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_fld[initvar] = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_fsd[initvar] = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_probe[initvar] = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_grant[initvar] = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_fun_preft[initvar] = _RAND_41[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_42 = {1{`RANDOM}};
  maybe_full = _RAND_42[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module DcacheStage(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_chkIdx,
  input  [31:0] io_enq_bits_paddr,
  input         io_enq_bits_fun_lb,
  input         io_enq_bits_fun_lh,
  input         io_enq_bits_fun_lw,
  input         io_enq_bits_fun_ld,
  input         io_enq_bits_fun_lbu,
  input         io_enq_bits_fun_lhu,
  input         io_enq_bits_fun_lwu,
  input         io_enq_bits_fun_sb,
  input         io_enq_bits_fun_sh,
  input         io_enq_bits_fun_sw,
  input         io_enq_bits_fun_sd,
  input         io_enq_bits_fun_lr_w,
  input         io_enq_bits_fun_sc_w,
  input         io_enq_bits_fun_amoswap_w,
  input         io_enq_bits_fun_amoadd_w,
  input         io_enq_bits_fun_amoxor_w,
  input         io_enq_bits_fun_amoand_w,
  input         io_enq_bits_fun_amoor_w,
  input         io_enq_bits_fun_amomin_w,
  input         io_enq_bits_fun_amomax_w,
  input         io_enq_bits_fun_amominu_w,
  input         io_enq_bits_fun_amomaxu_w,
  input         io_enq_bits_fun_lr_d,
  input         io_enq_bits_fun_sc_d,
  input         io_enq_bits_fun_amoswap_d,
  input         io_enq_bits_fun_amoadd_d,
  input         io_enq_bits_fun_amoxor_d,
  input         io_enq_bits_fun_amoand_d,
  input         io_enq_bits_fun_amoor_d,
  input         io_enq_bits_fun_amomin_d,
  input         io_enq_bits_fun_amomax_d,
  input         io_enq_bits_fun_amominu_d,
  input         io_enq_bits_fun_amomaxu_d,
  input         io_enq_bits_fun_flw,
  input         io_enq_bits_fun_fsw,
  input         io_enq_bits_fun_fld,
  input         io_enq_bits_fun_fsd,
  input         io_enq_bits_fun_probe,
  input         io_enq_bits_fun_grant,
  input         io_enq_bits_fun_preft,
  output        io_reload_valid,
  output        io_reload_bits_chkIdx,
  output [31:0] io_reload_bits_paddr,
  output        io_reload_bits_fun_lb,
  output        io_reload_bits_fun_lh,
  output        io_reload_bits_fun_lw,
  output        io_reload_bits_fun_ld,
  output        io_reload_bits_fun_lbu,
  output        io_reload_bits_fun_lhu,
  output        io_reload_bits_fun_lwu,
  output        io_reload_bits_fun_sb,
  output        io_reload_bits_fun_sh,
  output        io_reload_bits_fun_sw,
  output        io_reload_bits_fun_sd,
  output        io_reload_bits_fun_lr_w,
  output        io_reload_bits_fun_sc_w,
  output        io_reload_bits_fun_amoswap_w,
  output        io_reload_bits_fun_amoadd_w,
  output        io_reload_bits_fun_amoxor_w,
  output        io_reload_bits_fun_amoand_w,
  output        io_reload_bits_fun_amoor_w,
  output        io_reload_bits_fun_amomin_w,
  output        io_reload_bits_fun_amomax_w,
  output        io_reload_bits_fun_amominu_w,
  output        io_reload_bits_fun_amomaxu_w,
  output        io_reload_bits_fun_lr_d,
  output        io_reload_bits_fun_sc_d,
  output        io_reload_bits_fun_amoswap_d,
  output        io_reload_bits_fun_amoadd_d,
  output        io_reload_bits_fun_amoxor_d,
  output        io_reload_bits_fun_amoand_d,
  output        io_reload_bits_fun_amoor_d,
  output        io_reload_bits_fun_amomin_d,
  output        io_reload_bits_fun_amomax_d,
  output        io_reload_bits_fun_amominu_d,
  output        io_reload_bits_fun_amomaxu_d,
  output        io_reload_bits_fun_flw,
  output        io_reload_bits_fun_fsw,
  output        io_reload_bits_fun_fld,
  output        io_reload_bits_fun_fsd,
  output        io_reload_bits_fun_probe,
  output        io_reload_bits_fun_grant,
  output        io_reload_bits_fun_preft,
  output        io_deq_valid,
  output        io_deq_bits_chkIdx,
  output        io_deq_bits_is_load_amo,
  output        io_deq_bits_is_flw,
  output        io_deq_bits_is_fld,
  output        io_missUnit_req_valid,
  output [31:0] io_missUnit_req_bits_paddr,
  output        io_wb_req_valid,
  output        io_wb_req_bits_is_releaseData,
  output        io_wb_req_bits_is_release,
  output        io_wb_req_bits_is_probe,
  output        io_wb_req_bits_is_probeData,
  input         io_isCacheEmpty,
  input         io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_91;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
  reg [31:0] _RAND_94;
  reg [31:0] _RAND_95;
  reg [31:0] _RAND_96;
  reg [31:0] _RAND_97;
  reg [31:0] _RAND_98;
  reg [31:0] _RAND_99;
  reg [31:0] _RAND_100;
  reg [31:0] _RAND_101;
  reg [31:0] _RAND_102;
`endif // RANDOMIZE_REG_INIT
  wire  tagRAM_0_clock; // @[DcacheStage.scala 63:54]
  wire  tagRAM_0_io_addrr; // @[DcacheStage.scala 63:54]
  wire  tagRAM_0_io_addrw; // @[DcacheStage.scala 63:54]
  wire [26:0] tagRAM_0_io_dataw; // @[DcacheStage.scala 63:54]
  wire [26:0] tagRAM_0_io_datar; // @[DcacheStage.scala 63:54]
  wire  tagRAM_0_io_enw; // @[DcacheStage.scala 63:54]
  wire  tagRAM_0_io_enr; // @[DcacheStage.scala 63:54]
  wire  _pipeStage1Valid_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  reg  pipeStage1Valid; // @[DcacheStage.scala 71:32]
  reg  pipeStage1Bits_chkIdx; // @[DcacheStage.scala 72:32]
  reg [31:0] pipeStage1Bits_paddr; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_lb; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_lh; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_lw; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_ld; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_lbu; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_lhu; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_lwu; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_sb; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_sh; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_sw; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_sd; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_lr_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_sc_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoswap_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoadd_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoxor_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoand_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoor_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amomin_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amomax_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amominu_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amomaxu_w; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_lr_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_sc_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoswap_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoadd_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoxor_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoand_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amoor_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amomin_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amomax_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amominu_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_amomaxu_d; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_flw; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_fsw; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_fld; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_fsd; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_probe; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_grant; // @[DcacheStage.scala 72:32]
  reg  pipeStage1Bits_fun_preft; // @[DcacheStage.scala 72:32]
  reg  isTagBypass; // @[Reg.scala 19:16]
  reg [26:0] tagBypassData; // @[Reg.scala 19:16]
  wire [26:0] tagInfoR_0 = isTagBypass ? tagBypassData : tagRAM_0_io_datar; // @[DcacheStage.scala 127:31]
  wire [26:0] tagInfoW = pipeStage1Bits_paddr[31:5]; // @[Dcache.scala 73:21]
  wire  addrSelW = pipeStage1Bits_paddr[4]; // @[Dcache.scala 74:21]
  reg  isCBValid_1_0; // @[DcacheStage.scala 84:26]
  reg  isCBValid_0_0; // @[DcacheStage.scala 84:26]
  wire  _GEN_72 = addrSelW ? isCBValid_1_0 : isCBValid_0_0; // @[DcacheStage.scala 241:{73,73}]
  wire  res_0 = tagInfoR_0 == tagInfoW & _GEN_72; // @[DcacheStage.scala 241:73]
  wire  isHit = |res_0; // @[DcacheStage.scala 77:30]
  reg  isCBDirty_0_0; // @[DcacheStage.scala 86:26]
  reg  isCBDirty_1_0; // @[DcacheStage.scala 86:26]
  wire  addrSelR = io_enq_bits_paddr[4]; // @[Dcache.scala 74:21]
  wire  tagEnW_0 = pipeStage1Valid & pipeStage1Bits_fun_grant; // @[DcacheStage.scala 106:52]
  wire  _isTagBypass_T = addrSelR == addrSelW; // @[DcacheStage.scala 117:58]
  wire  _isTagBypass_T_1 = tagEnW_0 & addrSelR == addrSelW; // @[DcacheStage.scala 117:46]
  wire  _tagBypassData_T_3 = _pipeStage1Valid_T & tagEnW_0 & _isTagBypass_T; // @[DcacheStage.scala 118:70]
  reg  killTrans; // @[DcacheStage.scala 146:26]
  wire  _T_92 = io_flush | killTrans; // @[DcacheStage.scala 157:18]
  wire  _T_110 = pipeStage1Bits_fun_sc_d | pipeStage1Bits_fun_sc_w; // @[riscv_isa.scala 140:20]
  wire  _T_111 = pipeStage1Bits_fun_amoswap_w | pipeStage1Bits_fun_amoadd_w | pipeStage1Bits_fun_amoxor_w |
    pipeStage1Bits_fun_amoand_w | pipeStage1Bits_fun_amoor_w | pipeStage1Bits_fun_amomin_w | pipeStage1Bits_fun_amomax_w
     | pipeStage1Bits_fun_amominu_w | pipeStage1Bits_fun_amomaxu_w | pipeStage1Bits_fun_amoswap_d |
    pipeStage1Bits_fun_amoadd_d | pipeStage1Bits_fun_amoxor_d | pipeStage1Bits_fun_amoand_d | pipeStage1Bits_fun_amoor_d
     | pipeStage1Bits_fun_amomin_d | pipeStage1Bits_fun_amomax_d | pipeStage1Bits_fun_amominu_d |
    pipeStage1Bits_fun_amomaxu_d | _T_110; // @[riscv_isa.scala 148:205]
  wire  _T_120 = pipeStage1Bits_fun_lr_d | pipeStage1Bits_fun_lr_w; // @[riscv_isa.scala 141:20]
  wire  _T_121 = pipeStage1Bits_fun_lb | pipeStage1Bits_fun_lh | pipeStage1Bits_fun_lw | pipeStage1Bits_fun_ld |
    pipeStage1Bits_fun_lbu | pipeStage1Bits_fun_lhu | pipeStage1Bits_fun_lwu | pipeStage1Bits_fun_flw |
    pipeStage1Bits_fun_fld | _T_120; // @[riscv_isa.scala 143:65]
  wire  _T_122 = _T_111 | _T_121; // @[Dcache.scala 50:27]
  wire  _T_127 = pipeStage1Bits_fun_sb | pipeStage1Bits_fun_sh | pipeStage1Bits_fun_sw | pipeStage1Bits_fun_sd |
    pipeStage1Bits_fun_fsw | pipeStage1Bits_fun_fsd; // @[riscv_isa.scala 144:40]
  wire  _T_132 = _T_111 | _T_121 | _T_127 | _T_120 | _T_110; // @[Dcache.scala 50:51]
  wire  _T_133 = pipeStage1Valid & _T_132; // @[DcacheStage.scala 159:32]
  wire  _T_134 = pipeStage1Valid & _T_132 & isHit; // @[DcacheStage.scala 159:63]
  wire  _T_149 = pipeStage1Bits_fun_ld | pipeStage1Bits_fun_lr_d | pipeStage1Bits_fun_fld | pipeStage1Bits_fun_sd |
    pipeStage1Bits_fun_sc_d | pipeStage1Bits_fun_fsd | pipeStage1Bits_fun_amoswap_d | pipeStage1Bits_fun_amoadd_d |
    pipeStage1Bits_fun_amoxor_d | pipeStage1Bits_fun_amoand_d | pipeStage1Bits_fun_amoor_d | pipeStage1Bits_fun_amomin_d
     | pipeStage1Bits_fun_amomax_d | pipeStage1Bits_fun_amominu_d | pipeStage1Bits_fun_amomaxu_d; // @[riscv_isa.scala 156:140]
  wire  _T_164 = pipeStage1Bits_fun_lw | pipeStage1Bits_fun_lwu | pipeStage1Bits_fun_sw | pipeStage1Bits_fun_amoswap_w
     | pipeStage1Bits_fun_amoadd_w | pipeStage1Bits_fun_amoxor_w | pipeStage1Bits_fun_amoand_w |
    pipeStage1Bits_fun_amoor_w | pipeStage1Bits_fun_amomin_w | pipeStage1Bits_fun_amomax_w |
    pipeStage1Bits_fun_amominu_w | pipeStage1Bits_fun_amomaxu_w | pipeStage1Bits_fun_flw | pipeStage1Bits_fun_fsw |
    pipeStage1Bits_fun_lr_w | pipeStage1Bits_fun_sc_w; // @[riscv_isa.scala 155:151]
  wire  _T_167 = ~reset; // @[DcacheStage.scala 164:13]
  wire  _GEN_49 = io_isCacheEmpty ? 1'h0 : killTrans; // @[DcacheStage.scala 180:34 181:15 146:26]
  wire  _GEN_50 = io_flush | _GEN_49; // @[DcacheStage.scala 178:20 179:15]
  wire  _GEN_2 = ~addrSelW; // @[DcacheStage.scala 228:{34,34} 84:26]
  wire  _GEN_51 = ~addrSelW | isCBValid_0_0; // @[DcacheStage.scala 228:{34,34} 84:26]
  wire  _GEN_52 = addrSelW | isCBValid_1_0; // @[DcacheStage.scala 228:{34,34} 84:26]
  wire  _GEN_53 = ~addrSelW ? 1'h0 : isCBDirty_0_0; // @[DcacheStage.scala 229:{34,34} 86:26]
  wire  _GEN_54 = addrSelW ? 1'h0 : isCBDirty_1_0; // @[DcacheStage.scala 229:{34,34} 86:26]
  wire  _GEN_55 = pipeStage1Bits_fun_grant ? _GEN_51 : isCBValid_0_0; // @[DcacheStage.scala 227:38 84:26]
  wire  _GEN_56 = pipeStage1Bits_fun_grant ? _GEN_52 : isCBValid_1_0; // @[DcacheStage.scala 227:38 84:26]
  wire  _GEN_57 = pipeStage1Bits_fun_grant ? _GEN_53 : isCBDirty_0_0; // @[DcacheStage.scala 227:38 86:26]
  wire  _GEN_58 = pipeStage1Bits_fun_grant ? _GEN_54 : isCBDirty_1_0; // @[DcacheStage.scala 227:38 86:26]
  wire  _T_247 = _T_111 | _T_127 | _T_110; // @[Dcache.scala 55:35]
  wire  _GEN_59 = _GEN_2 | _GEN_57; // @[DcacheStage.scala 232:{34,34}]
  wire  _GEN_60 = addrSelW | _GEN_58; // @[DcacheStage.scala 232:{34,34}]
  wire  _T_253 = ~isHit; // @[DcacheStage.scala 283:46]
  reg  missUnitReqValid; // @[DcacheStage.scala 291:33]
  reg [31:0] missUnitReqPaddr; // @[DcacheStage.scala 292:29]
  wire  _T_299 = pipeStage1Valid & (_T_132 | pipeStage1Bits_fun_preft) & _T_253; // @[DcacheStage.scala 297:87]
  wire [31:0] _missUnitReqPaddr_T = {{4'd0}, pipeStage1Bits_paddr[31:4]}; // @[DcacheStage.scala 299:46]
  wire [35:0] _GEN_5 = {_missUnitReqPaddr_T, 4'h0}; // @[DcacheStage.scala 299:60]
  wire [38:0] _missUnitReqPaddr_T_1 = {{3'd0}, _GEN_5}; // @[DcacheStage.scala 299:60]
  wire [38:0] _GEN_74 = pipeStage1Valid & (_T_132 | pipeStage1Bits_fun_preft) & _T_253 ? _missUnitReqPaddr_T_1 : {{7
    'd0}, missUnitReqPaddr}; // @[DcacheStage.scala 297:102 299:22 292:29]
  reg  wbReqValid; // @[DcacheStage.scala 307:27]
  reg  wbReqisData; // @[DcacheStage.scala 310:24]
  reg  isPb; // @[DcacheStage.scala 311:24]
  wire  _io_wb_req_bits_is_releaseData_T = ~isPb; // @[DcacheStage.scala 317:51]
  wire  _io_wb_req_bits_is_release_T = ~wbReqisData; // @[DcacheStage.scala 318:36]
  wire  _GEN_76 = addrSelW ? isCBDirty_1_0 : isCBDirty_0_0; // @[DcacheStage.scala 326:{17,17}]
  wire  _T_305 = pipeStage1Valid & pipeStage1Bits_fun_probe; // @[DcacheStage.scala 328:32]
  wire  _GEN_81 = pipeStage1Valid & pipeStage1Bits_fun_probe | isPb; // @[DcacheStage.scala 328:60 333:17 311:24]
  wire  _GEN_82 = pipeStage1Valid & (pipeStage1Bits_fun_grant & ~(~_GEN_72)) | _T_305; // @[DcacheStage.scala 322:99 323:17]
  reg  reloadValid; // @[DcacheStage.scala 347:28]
  reg  reloadBits_chkIdx; // @[DcacheStage.scala 348:24]
  reg [31:0] reloadBits_paddr; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_lb; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_lh; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_lw; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_ld; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_lbu; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_lhu; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_lwu; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_sb; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_sh; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_sw; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_sd; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_lr_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_sc_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoswap_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoadd_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoxor_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoand_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoor_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amomin_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amomax_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amominu_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amomaxu_w; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_lr_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_sc_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoswap_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoadd_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoxor_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoand_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amoor_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amomin_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amomax_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amominu_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_amomaxu_d; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_flw; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_fsw; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_fld; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_fsd; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_probe; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_grant; // @[DcacheStage.scala 348:24]
  reg  reloadBits_fun_preft; // @[DcacheStage.scala 348:24]
  wire  _T_348 = _T_133 & _T_253; // @[DcacheStage.scala 350:56]
  reg  deqValid; // @[DcacheStage.scala 362:25]
  reg  deqBits_chkIdx; // @[DcacheStage.scala 363:21]
  reg  deqBits_is_load_amo; // @[DcacheStage.scala 363:21]
  reg  deqBits_is_flw; // @[DcacheStage.scala 363:21]
  reg  deqBits_is_fld; // @[DcacheStage.scala 363:21]
  wire  _deqBits_is_load_amo_T_31 = _T_122 | _T_120; // @[Dcache.scala 56:31]
  TagRAM tagRAM_0 ( // @[DcacheStage.scala 63:54]
    .clock(tagRAM_0_clock),
    .io_addrr(tagRAM_0_io_addrr),
    .io_addrw(tagRAM_0_io_addrw),
    .io_dataw(tagRAM_0_io_dataw),
    .io_datar(tagRAM_0_io_datar),
    .io_enw(tagRAM_0_io_enw),
    .io_enr(tagRAM_0_io_enr)
  );
  assign io_enq_ready = 1'h1; // @[DcacheStage.scala 70:16]
  assign io_reload_valid = reloadValid; // @[DcacheStage.scala 359:19]
  assign io_reload_bits_chkIdx = reloadBits_chkIdx; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_paddr = reloadBits_paddr; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_lb = reloadBits_fun_lb; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_lh = reloadBits_fun_lh; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_lw = reloadBits_fun_lw; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_ld = reloadBits_fun_ld; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_lbu = reloadBits_fun_lbu; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_lhu = reloadBits_fun_lhu; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_lwu = reloadBits_fun_lwu; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_sb = reloadBits_fun_sb; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_sh = reloadBits_fun_sh; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_sw = reloadBits_fun_sw; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_sd = reloadBits_fun_sd; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_lr_w = reloadBits_fun_lr_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_sc_w = reloadBits_fun_sc_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoswap_w = reloadBits_fun_amoswap_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoadd_w = reloadBits_fun_amoadd_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoxor_w = reloadBits_fun_amoxor_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoand_w = reloadBits_fun_amoand_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoor_w = reloadBits_fun_amoor_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amomin_w = reloadBits_fun_amomin_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amomax_w = reloadBits_fun_amomax_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amominu_w = reloadBits_fun_amominu_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amomaxu_w = reloadBits_fun_amomaxu_w; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_lr_d = reloadBits_fun_lr_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_sc_d = reloadBits_fun_sc_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoswap_d = reloadBits_fun_amoswap_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoadd_d = reloadBits_fun_amoadd_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoxor_d = reloadBits_fun_amoxor_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoand_d = reloadBits_fun_amoand_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amoor_d = reloadBits_fun_amoor_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amomin_d = reloadBits_fun_amomin_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amomax_d = reloadBits_fun_amomax_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amominu_d = reloadBits_fun_amominu_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_amomaxu_d = reloadBits_fun_amomaxu_d; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_flw = reloadBits_fun_flw; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_fsw = reloadBits_fun_fsw; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_fld = reloadBits_fun_fld; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_fsd = reloadBits_fun_fsd; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_probe = reloadBits_fun_probe; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_grant = reloadBits_fun_grant; // @[DcacheStage.scala 360:19]
  assign io_reload_bits_fun_preft = reloadBits_fun_preft; // @[DcacheStage.scala 360:19]
  assign io_deq_valid = deqValid; // @[DcacheStage.scala 365:16]
  assign io_deq_bits_chkIdx = deqBits_chkIdx; // @[DcacheStage.scala 366:16]
  assign io_deq_bits_is_load_amo = deqBits_is_load_amo; // @[DcacheStage.scala 366:16]
  assign io_deq_bits_is_flw = deqBits_is_flw; // @[DcacheStage.scala 366:16]
  assign io_deq_bits_is_fld = deqBits_is_fld; // @[DcacheStage.scala 366:16]
  assign io_missUnit_req_valid = missUnitReqValid; // @[DcacheStage.scala 294:25]
  assign io_missUnit_req_bits_paddr = missUnitReqPaddr; // @[DcacheStage.scala 295:30]
  assign io_wb_req_valid = wbReqValid; // @[DcacheStage.scala 313:19]
  assign io_wb_req_bits_is_releaseData = wbReqisData & ~isPb; // @[DcacheStage.scala 317:49]
  assign io_wb_req_bits_is_release = ~wbReqisData & _io_wb_req_bits_is_releaseData_T; // @[DcacheStage.scala 318:49]
  assign io_wb_req_bits_is_probe = _io_wb_req_bits_is_release_T & isPb; // @[DcacheStage.scala 320:49]
  assign io_wb_req_bits_is_probeData = wbReqisData & isPb; // @[DcacheStage.scala 319:49]
  assign tagRAM_0_clock = clock;
  assign tagRAM_0_io_addrr = io_enq_bits_paddr[4]; // @[Dcache.scala 74:21]
  assign tagRAM_0_io_addrw = pipeStage1Bits_paddr[4]; // @[Dcache.scala 74:21]
  assign tagRAM_0_io_dataw = pipeStage1Bits_paddr[31:5]; // @[Dcache.scala 73:21]
  assign tagRAM_0_io_enw = pipeStage1Valid & pipeStage1Bits_fun_grant; // @[DcacheStage.scala 106:52]
  assign tagRAM_0_io_enr = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  always @(posedge clock) begin
    if (reset) begin // @[DcacheStage.scala 71:32]
      pipeStage1Valid <= 1'h0; // @[DcacheStage.scala 71:32]
    end else begin
      pipeStage1Valid <= _pipeStage1Valid_T; // @[DcacheStage.scala 71:32]
    end
    pipeStage1Bits_chkIdx <= io_enq_bits_chkIdx; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_paddr <= io_enq_bits_paddr; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_lb <= io_enq_bits_fun_lb; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_lh <= io_enq_bits_fun_lh; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_lw <= io_enq_bits_fun_lw; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_ld <= io_enq_bits_fun_ld; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_lbu <= io_enq_bits_fun_lbu; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_lhu <= io_enq_bits_fun_lhu; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_lwu <= io_enq_bits_fun_lwu; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_sb <= io_enq_bits_fun_sb; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_sh <= io_enq_bits_fun_sh; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_sw <= io_enq_bits_fun_sw; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_sd <= io_enq_bits_fun_sd; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_lr_w <= io_enq_bits_fun_lr_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_sc_w <= io_enq_bits_fun_sc_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoswap_w <= io_enq_bits_fun_amoswap_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoadd_w <= io_enq_bits_fun_amoadd_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoxor_w <= io_enq_bits_fun_amoxor_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoand_w <= io_enq_bits_fun_amoand_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoor_w <= io_enq_bits_fun_amoor_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amomin_w <= io_enq_bits_fun_amomin_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amomax_w <= io_enq_bits_fun_amomax_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amominu_w <= io_enq_bits_fun_amominu_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amomaxu_w <= io_enq_bits_fun_amomaxu_w; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_lr_d <= io_enq_bits_fun_lr_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_sc_d <= io_enq_bits_fun_sc_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoswap_d <= io_enq_bits_fun_amoswap_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoadd_d <= io_enq_bits_fun_amoadd_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoxor_d <= io_enq_bits_fun_amoxor_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoand_d <= io_enq_bits_fun_amoand_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amoor_d <= io_enq_bits_fun_amoor_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amomin_d <= io_enq_bits_fun_amomin_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amomax_d <= io_enq_bits_fun_amomax_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amominu_d <= io_enq_bits_fun_amominu_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_amomaxu_d <= io_enq_bits_fun_amomaxu_d; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_flw <= io_enq_bits_fun_flw; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_fsw <= io_enq_bits_fun_fsw; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_fld <= io_enq_bits_fun_fld; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_fsd <= io_enq_bits_fun_fsd; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_probe <= io_enq_bits_fun_probe; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_grant <= io_enq_bits_fun_grant; // @[DcacheStage.scala 72:32]
    pipeStage1Bits_fun_preft <= io_enq_bits_fun_preft; // @[DcacheStage.scala 72:32]
    if (_pipeStage1Valid_T) begin // @[Reg.scala 20:18]
      isTagBypass <= _isTagBypass_T_1; // @[Reg.scala 20:22]
    end
    if (_tagBypassData_T_3) begin // @[Reg.scala 20:18]
      tagBypassData <= tagInfoW; // @[Reg.scala 20:22]
    end
    if (reset) begin // @[DcacheStage.scala 84:26]
      isCBValid_1_0 <= 1'h0; // @[DcacheStage.scala 84:26]
    end else if (pipeStage1Valid) begin // @[DcacheStage.scala 226:27]
      if (pipeStage1Bits_fun_probe & isHit) begin // @[DcacheStage.scala 235:46]
        if (addrSelW) begin // @[DcacheStage.scala 236:34]
          isCBValid_1_0 <= 1'h0; // @[DcacheStage.scala 236:34]
        end else begin
          isCBValid_1_0 <= _GEN_56;
        end
      end else begin
        isCBValid_1_0 <= _GEN_56;
      end
    end
    if (reset) begin // @[DcacheStage.scala 84:26]
      isCBValid_0_0 <= 1'h0; // @[DcacheStage.scala 84:26]
    end else if (pipeStage1Valid) begin // @[DcacheStage.scala 226:27]
      if (pipeStage1Bits_fun_probe & isHit) begin // @[DcacheStage.scala 235:46]
        if (~addrSelW) begin // @[DcacheStage.scala 236:34]
          isCBValid_0_0 <= 1'h0; // @[DcacheStage.scala 236:34]
        end else begin
          isCBValid_0_0 <= _GEN_55;
        end
      end else begin
        isCBValid_0_0 <= _GEN_55;
      end
    end
    if (reset) begin // @[DcacheStage.scala 86:26]
      isCBDirty_0_0 <= 1'h0; // @[DcacheStage.scala 86:26]
    end else if (pipeStage1Valid) begin // @[DcacheStage.scala 226:27]
      if (_T_247) begin // @[DcacheStage.scala 231:42]
        isCBDirty_0_0 <= _GEN_59;
      end else if (pipeStage1Bits_fun_grant) begin // @[DcacheStage.scala 227:38]
        isCBDirty_0_0 <= _GEN_53;
      end
    end
    if (reset) begin // @[DcacheStage.scala 86:26]
      isCBDirty_1_0 <= 1'h0; // @[DcacheStage.scala 86:26]
    end else if (pipeStage1Valid) begin // @[DcacheStage.scala 226:27]
      if (_T_247) begin // @[DcacheStage.scala 231:42]
        isCBDirty_1_0 <= _GEN_60;
      end else if (pipeStage1Bits_fun_grant) begin // @[DcacheStage.scala 227:38]
        isCBDirty_1_0 <= _GEN_54;
      end
    end
    if (reset) begin // @[DcacheStage.scala 146:26]
      killTrans <= 1'h0; // @[DcacheStage.scala 146:26]
    end else begin
      killTrans <= _GEN_50;
    end
    if (reset) begin // @[DcacheStage.scala 291:33]
      missUnitReqValid <= 1'h0; // @[DcacheStage.scala 291:33]
    end else begin
      missUnitReqValid <= _T_299;
    end
    missUnitReqPaddr <= _GEN_74[31:0];
    if (reset) begin // @[DcacheStage.scala 307:27]
      wbReqValid <= 1'h0; // @[DcacheStage.scala 307:27]
    end else begin
      wbReqValid <= _GEN_82;
    end
    if (pipeStage1Valid & (pipeStage1Bits_fun_grant & ~(~_GEN_72))) begin // @[DcacheStage.scala 322:99]
      if (addrSelW) begin // @[DcacheStage.scala 326:17]
        wbReqisData <= isCBDirty_1_0; // @[DcacheStage.scala 326:17]
      end else begin
        wbReqisData <= isCBDirty_0_0;
      end
    end else if (pipeStage1Valid & pipeStage1Bits_fun_probe) begin // @[DcacheStage.scala 328:60]
      wbReqisData <= _GEN_76 & isHit; // @[DcacheStage.scala 332:17]
    end
    if (pipeStage1Valid & (pipeStage1Bits_fun_grant & ~(~_GEN_72))) begin // @[DcacheStage.scala 322:99]
      isPb <= 1'h0; // @[DcacheStage.scala 327:17]
    end else begin
      isPb <= _GEN_81;
    end
    if (reset) begin // @[DcacheStage.scala 347:28]
      reloadValid <= 1'h0; // @[DcacheStage.scala 347:28]
    end else begin
      reloadValid <= _T_348;
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_chkIdx <= pipeStage1Bits_chkIdx; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_paddr <= pipeStage1Bits_paddr; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_lb <= pipeStage1Bits_fun_lb; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_lh <= pipeStage1Bits_fun_lh; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_lw <= pipeStage1Bits_fun_lw; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_ld <= pipeStage1Bits_fun_ld; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_lbu <= pipeStage1Bits_fun_lbu; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_lhu <= pipeStage1Bits_fun_lhu; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_lwu <= pipeStage1Bits_fun_lwu; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_sb <= pipeStage1Bits_fun_sb; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_sh <= pipeStage1Bits_fun_sh; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_sw <= pipeStage1Bits_fun_sw; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_sd <= pipeStage1Bits_fun_sd; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_lr_w <= pipeStage1Bits_fun_lr_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_sc_w <= pipeStage1Bits_fun_sc_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoswap_w <= pipeStage1Bits_fun_amoswap_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoadd_w <= pipeStage1Bits_fun_amoadd_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoxor_w <= pipeStage1Bits_fun_amoxor_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoand_w <= pipeStage1Bits_fun_amoand_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoor_w <= pipeStage1Bits_fun_amoor_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amomin_w <= pipeStage1Bits_fun_amomin_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amomax_w <= pipeStage1Bits_fun_amomax_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amominu_w <= pipeStage1Bits_fun_amominu_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amomaxu_w <= pipeStage1Bits_fun_amomaxu_w; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_lr_d <= pipeStage1Bits_fun_lr_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_sc_d <= pipeStage1Bits_fun_sc_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoswap_d <= pipeStage1Bits_fun_amoswap_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoadd_d <= pipeStage1Bits_fun_amoadd_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoxor_d <= pipeStage1Bits_fun_amoxor_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoand_d <= pipeStage1Bits_fun_amoand_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amoor_d <= pipeStage1Bits_fun_amoor_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amomin_d <= pipeStage1Bits_fun_amomin_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amomax_d <= pipeStage1Bits_fun_amomax_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amominu_d <= pipeStage1Bits_fun_amominu_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_amomaxu_d <= pipeStage1Bits_fun_amomaxu_d; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_flw <= pipeStage1Bits_fun_flw; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_fsw <= pipeStage1Bits_fun_fsw; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_fld <= pipeStage1Bits_fun_fld; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_fsd <= pipeStage1Bits_fun_fsd; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_probe <= pipeStage1Bits_fun_probe; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_grant <= pipeStage1Bits_fun_grant; // @[DcacheStage.scala 352:17]
    end
    if (_T_133 & _T_253) begin // @[DcacheStage.scala 350:67]
      reloadBits_fun_preft <= pipeStage1Bits_fun_preft; // @[DcacheStage.scala 352:17]
    end
    if (reset) begin // @[DcacheStage.scala 362:25]
      deqValid <= 1'h0; // @[DcacheStage.scala 362:25]
    end else begin
      deqValid <= _T_134;
    end
    if (_T_134) begin // @[DcacheStage.scala 368:66]
      deqBits_chkIdx <= pipeStage1Bits_chkIdx; // @[DcacheStage.scala 395:24]
    end
    if (_T_134) begin // @[DcacheStage.scala 368:66]
      deqBits_is_load_amo <= _deqBits_is_load_amo_T_31; // @[DcacheStage.scala 396:25]
    end
    if (_T_134) begin // @[DcacheStage.scala 368:66]
      deqBits_is_flw <= pipeStage1Bits_fun_flw; // @[DcacheStage.scala 397:25]
    end
    if (_T_134) begin // @[DcacheStage.scala 368:66]
      deqBits_is_fld <= pipeStage1Bits_fun_fld; // @[DcacheStage.scala 398:25]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_92 & _T_134 & _T_120 & ~reset & ~(_T_149 | _T_164)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at DcacheStage.scala:164 assert( pipeStage1Bits.fun.is_dubl | pipeStage1Bits.fun.is_word )\n"
            ); // @[DcacheStage.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_149 | _T_164) & (~_T_92 & _T_134 & _T_120 & ~reset)) begin
          $fatal; // @[DcacheStage.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (pipeStage1Valid & _T_167)) begin
          $fatal; // @[DcacheStage.scala 242:36]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_305 & ~isHit & _T_167) begin
          $fwrite(32'h80000002,"Warning, l2 will never request a empty probe, is it in writeback unit?\n"); // @[DcacheStage.scala 283:63]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pipeStage1Valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  pipeStage1Bits_chkIdx = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  pipeStage1Bits_paddr = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  pipeStage1Bits_fun_lb = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  pipeStage1Bits_fun_lh = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  pipeStage1Bits_fun_lw = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  pipeStage1Bits_fun_ld = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  pipeStage1Bits_fun_lbu = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  pipeStage1Bits_fun_lhu = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  pipeStage1Bits_fun_lwu = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  pipeStage1Bits_fun_sb = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  pipeStage1Bits_fun_sh = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  pipeStage1Bits_fun_sw = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  pipeStage1Bits_fun_sd = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  pipeStage1Bits_fun_lr_w = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  pipeStage1Bits_fun_sc_w = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoswap_w = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoadd_w = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoxor_w = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoand_w = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoor_w = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  pipeStage1Bits_fun_amomin_w = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  pipeStage1Bits_fun_amomax_w = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  pipeStage1Bits_fun_amominu_w = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  pipeStage1Bits_fun_amomaxu_w = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  pipeStage1Bits_fun_lr_d = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  pipeStage1Bits_fun_sc_d = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoswap_d = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoadd_d = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoxor_d = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoand_d = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  pipeStage1Bits_fun_amoor_d = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  pipeStage1Bits_fun_amomin_d = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  pipeStage1Bits_fun_amomax_d = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  pipeStage1Bits_fun_amominu_d = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  pipeStage1Bits_fun_amomaxu_d = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  pipeStage1Bits_fun_flw = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  pipeStage1Bits_fun_fsw = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  pipeStage1Bits_fun_fld = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  pipeStage1Bits_fun_fsd = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  pipeStage1Bits_fun_probe = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  pipeStage1Bits_fun_grant = _RAND_41[0:0];
  _RAND_42 = {1{`RANDOM}};
  pipeStage1Bits_fun_preft = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  isTagBypass = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  tagBypassData = _RAND_44[26:0];
  _RAND_45 = {1{`RANDOM}};
  isCBValid_1_0 = _RAND_45[0:0];
  _RAND_46 = {1{`RANDOM}};
  isCBValid_0_0 = _RAND_46[0:0];
  _RAND_47 = {1{`RANDOM}};
  isCBDirty_0_0 = _RAND_47[0:0];
  _RAND_48 = {1{`RANDOM}};
  isCBDirty_1_0 = _RAND_48[0:0];
  _RAND_49 = {1{`RANDOM}};
  killTrans = _RAND_49[0:0];
  _RAND_50 = {1{`RANDOM}};
  missUnitReqValid = _RAND_50[0:0];
  _RAND_51 = {1{`RANDOM}};
  missUnitReqPaddr = _RAND_51[31:0];
  _RAND_52 = {1{`RANDOM}};
  wbReqValid = _RAND_52[0:0];
  _RAND_53 = {1{`RANDOM}};
  wbReqisData = _RAND_53[0:0];
  _RAND_54 = {1{`RANDOM}};
  isPb = _RAND_54[0:0];
  _RAND_55 = {1{`RANDOM}};
  reloadValid = _RAND_55[0:0];
  _RAND_56 = {1{`RANDOM}};
  reloadBits_chkIdx = _RAND_56[0:0];
  _RAND_57 = {1{`RANDOM}};
  reloadBits_paddr = _RAND_57[31:0];
  _RAND_58 = {1{`RANDOM}};
  reloadBits_fun_lb = _RAND_58[0:0];
  _RAND_59 = {1{`RANDOM}};
  reloadBits_fun_lh = _RAND_59[0:0];
  _RAND_60 = {1{`RANDOM}};
  reloadBits_fun_lw = _RAND_60[0:0];
  _RAND_61 = {1{`RANDOM}};
  reloadBits_fun_ld = _RAND_61[0:0];
  _RAND_62 = {1{`RANDOM}};
  reloadBits_fun_lbu = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  reloadBits_fun_lhu = _RAND_63[0:0];
  _RAND_64 = {1{`RANDOM}};
  reloadBits_fun_lwu = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  reloadBits_fun_sb = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  reloadBits_fun_sh = _RAND_66[0:0];
  _RAND_67 = {1{`RANDOM}};
  reloadBits_fun_sw = _RAND_67[0:0];
  _RAND_68 = {1{`RANDOM}};
  reloadBits_fun_sd = _RAND_68[0:0];
  _RAND_69 = {1{`RANDOM}};
  reloadBits_fun_lr_w = _RAND_69[0:0];
  _RAND_70 = {1{`RANDOM}};
  reloadBits_fun_sc_w = _RAND_70[0:0];
  _RAND_71 = {1{`RANDOM}};
  reloadBits_fun_amoswap_w = _RAND_71[0:0];
  _RAND_72 = {1{`RANDOM}};
  reloadBits_fun_amoadd_w = _RAND_72[0:0];
  _RAND_73 = {1{`RANDOM}};
  reloadBits_fun_amoxor_w = _RAND_73[0:0];
  _RAND_74 = {1{`RANDOM}};
  reloadBits_fun_amoand_w = _RAND_74[0:0];
  _RAND_75 = {1{`RANDOM}};
  reloadBits_fun_amoor_w = _RAND_75[0:0];
  _RAND_76 = {1{`RANDOM}};
  reloadBits_fun_amomin_w = _RAND_76[0:0];
  _RAND_77 = {1{`RANDOM}};
  reloadBits_fun_amomax_w = _RAND_77[0:0];
  _RAND_78 = {1{`RANDOM}};
  reloadBits_fun_amominu_w = _RAND_78[0:0];
  _RAND_79 = {1{`RANDOM}};
  reloadBits_fun_amomaxu_w = _RAND_79[0:0];
  _RAND_80 = {1{`RANDOM}};
  reloadBits_fun_lr_d = _RAND_80[0:0];
  _RAND_81 = {1{`RANDOM}};
  reloadBits_fun_sc_d = _RAND_81[0:0];
  _RAND_82 = {1{`RANDOM}};
  reloadBits_fun_amoswap_d = _RAND_82[0:0];
  _RAND_83 = {1{`RANDOM}};
  reloadBits_fun_amoadd_d = _RAND_83[0:0];
  _RAND_84 = {1{`RANDOM}};
  reloadBits_fun_amoxor_d = _RAND_84[0:0];
  _RAND_85 = {1{`RANDOM}};
  reloadBits_fun_amoand_d = _RAND_85[0:0];
  _RAND_86 = {1{`RANDOM}};
  reloadBits_fun_amoor_d = _RAND_86[0:0];
  _RAND_87 = {1{`RANDOM}};
  reloadBits_fun_amomin_d = _RAND_87[0:0];
  _RAND_88 = {1{`RANDOM}};
  reloadBits_fun_amomax_d = _RAND_88[0:0];
  _RAND_89 = {1{`RANDOM}};
  reloadBits_fun_amominu_d = _RAND_89[0:0];
  _RAND_90 = {1{`RANDOM}};
  reloadBits_fun_amomaxu_d = _RAND_90[0:0];
  _RAND_91 = {1{`RANDOM}};
  reloadBits_fun_flw = _RAND_91[0:0];
  _RAND_92 = {1{`RANDOM}};
  reloadBits_fun_fsw = _RAND_92[0:0];
  _RAND_93 = {1{`RANDOM}};
  reloadBits_fun_fld = _RAND_93[0:0];
  _RAND_94 = {1{`RANDOM}};
  reloadBits_fun_fsd = _RAND_94[0:0];
  _RAND_95 = {1{`RANDOM}};
  reloadBits_fun_probe = _RAND_95[0:0];
  _RAND_96 = {1{`RANDOM}};
  reloadBits_fun_grant = _RAND_96[0:0];
  _RAND_97 = {1{`RANDOM}};
  reloadBits_fun_preft = _RAND_97[0:0];
  _RAND_98 = {1{`RANDOM}};
  deqValid = _RAND_98[0:0];
  _RAND_99 = {1{`RANDOM}};
  deqBits_chkIdx = _RAND_99[0:0];
  _RAND_100 = {1{`RANDOM}};
  deqBits_is_load_amo = _RAND_100[0:0];
  _RAND_101 = {1{`RANDOM}};
  deqBits_is_flw = _RAND_101[0:0];
  _RAND_102 = {1{`RANDOM}};
  deqBits_is_fld = _RAND_102[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Dcache(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [31:0] io_enq_bits_paddr,
  input         io_enq_bits_fun_lb,
  input         io_enq_bits_fun_lh,
  input         io_enq_bits_fun_lw,
  input         io_enq_bits_fun_ld,
  input         io_enq_bits_fun_lbu,
  input         io_enq_bits_fun_lhu,
  input         io_enq_bits_fun_lwu,
  input         io_enq_bits_fun_sb,
  input         io_enq_bits_fun_sh,
  input         io_enq_bits_fun_sw,
  input         io_enq_bits_fun_sd,
  input         io_enq_bits_fun_lr_w,
  input         io_enq_bits_fun_sc_w,
  input         io_enq_bits_fun_amoswap_w,
  input         io_enq_bits_fun_amoadd_w,
  input         io_enq_bits_fun_amoxor_w,
  input         io_enq_bits_fun_amoand_w,
  input         io_enq_bits_fun_amoor_w,
  input         io_enq_bits_fun_amomin_w,
  input         io_enq_bits_fun_amomax_w,
  input         io_enq_bits_fun_amominu_w,
  input         io_enq_bits_fun_amomaxu_w,
  input         io_enq_bits_fun_lr_d,
  input         io_enq_bits_fun_sc_d,
  input         io_enq_bits_fun_amoswap_d,
  input         io_enq_bits_fun_amoadd_d,
  input         io_enq_bits_fun_amoxor_d,
  input         io_enq_bits_fun_amoand_d,
  input         io_enq_bits_fun_amoor_d,
  input         io_enq_bits_fun_amomin_d,
  input         io_enq_bits_fun_amomax_d,
  input         io_enq_bits_fun_amominu_d,
  input         io_enq_bits_fun_amomaxu_d,
  input         io_enq_bits_fun_flw,
  input         io_enq_bits_fun_fsw,
  input         io_enq_bits_fun_fld,
  input         io_enq_bits_fun_fsd,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_chkIdx,
  output        io_deq_bits_is_load_amo,
  output        io_deq_bits_is_flw,
  output        io_deq_bits_is_fld,
  output        io_is_empty,
  input         io_flush,
  input         io_missUnit_dcache_acquire_ready,
  input         io_missUnit_dcache_grant_valid,
  input  [2:0]  io_missUnit_dcache_grant_bits_opcode,
  input  [2:0]  io_missUnit_dcache_grant_bits_size,
  input         io_missUnit_dcache_grant_bits_source,
  input         io_missUnit_dcache_grantAck_ready,
  input         io_probeUnit_dcache_probe_valid,
  input  [31:0] io_probeUnit_dcache_probe_bits_address,
  input         io_writeBackUnit_dcache_release_ready,
  output        io_writeBackUnit_dcache_release_valid,
  output [2:0]  io_writeBackUnit_dcache_release_bits_opcode,
  output [2:0]  io_writeBackUnit_dcache_release_bits_size,
  input         io_writeBackUnit_dcache_grant_valid,
  input         io_writeBackUnit_dcache_grant_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  wire  missUnit_clock; // @[Dcache.scala 116:46]
  wire  missUnit_reset; // @[Dcache.scala 116:46]
  wire  missUnit_io_req_valid; // @[Dcache.scala 116:46]
  wire [31:0] missUnit_io_req_bits_paddr; // @[Dcache.scala 116:46]
  wire  missUnit_io_rsp_valid; // @[Dcache.scala 116:46]
  wire [31:0] missUnit_io_rsp_bits_paddr; // @[Dcache.scala 116:46]
  wire  missUnit_io_cache_acquire_ready; // @[Dcache.scala 116:46]
  wire  missUnit_io_cache_acquire_valid; // @[Dcache.scala 116:46]
  wire  missUnit_io_cache_grant_ready; // @[Dcache.scala 116:46]
  wire  missUnit_io_cache_grant_valid; // @[Dcache.scala 116:46]
  wire [2:0] missUnit_io_cache_grant_bits_opcode; // @[Dcache.scala 116:46]
  wire [2:0] missUnit_io_cache_grant_bits_size; // @[Dcache.scala 116:46]
  wire  missUnit_io_cache_grant_bits_source; // @[Dcache.scala 116:46]
  wire  missUnit_io_cache_grantAck_ready; // @[Dcache.scala 116:46]
  wire  missUnit_io_cache_grantAck_valid; // @[Dcache.scala 116:46]
  wire  missUnit_io_miss_ban; // @[Dcache.scala 116:46]
  wire  missUnit_io_release_ban; // @[Dcache.scala 116:46]
  wire  probeUnit_clock; // @[Dcache.scala 117:46]
  wire  probeUnit_reset; // @[Dcache.scala 117:46]
  wire  probeUnit_io_cache_probe_valid; // @[Dcache.scala 117:46]
  wire [31:0] probeUnit_io_cache_probe_bits_address; // @[Dcache.scala 117:46]
  wire  probeUnit_io_req_ready; // @[Dcache.scala 117:46]
  wire  probeUnit_io_req_valid; // @[Dcache.scala 117:46]
  wire [31:0] probeUnit_io_req_bits_paddr; // @[Dcache.scala 117:46]
  wire  probeUnit_io_probeBan; // @[Dcache.scala 117:46]
  wire  writeBackUnit_clock; // @[Dcache.scala 118:46]
  wire  writeBackUnit_reset; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_wb_req_valid; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_wb_req_bits_is_releaseData; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_wb_req_bits_is_release; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_wb_req_bits_is_probe; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_wb_req_bits_is_probeData; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_cache_release_ready; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_cache_release_valid; // @[Dcache.scala 118:46]
  wire [2:0] writeBackUnit_io_cache_release_bits_opcode; // @[Dcache.scala 118:46]
  wire [2:0] writeBackUnit_io_cache_release_bits_size; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_cache_grant_ready; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_cache_grant_valid; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_cache_grant_bits_source; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_release_ban; // @[Dcache.scala 118:46]
  wire  writeBackUnit_io_miss_ban; // @[Dcache.scala 118:46]
  wire  lsEntry_clock; // @[Dcache.scala 123:23]
  wire  lsEntry_reset; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_ready; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_valid; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_chkIdx; // @[Dcache.scala 123:23]
  wire [31:0] lsEntry_io_enq_bits_paddr; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_lb; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_lh; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_lw; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_ld; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_lbu; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_lhu; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_lwu; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_sb; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_sh; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_sw; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_sd; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_lr_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_sc_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoswap_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoadd_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoxor_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoand_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoor_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amomin_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amomax_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amominu_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amomaxu_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_lr_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_sc_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoswap_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoadd_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoxor_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoand_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amoor_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amomin_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amomax_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amominu_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_amomaxu_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_flw; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_fsw; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_fld; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_fsd; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_probe; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_grant; // @[Dcache.scala 123:23]
  wire  lsEntry_io_enq_bits_fun_preft; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_ready; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_valid; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_chkIdx; // @[Dcache.scala 123:23]
  wire [31:0] lsEntry_io_deq_bits_paddr; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_lb; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_lh; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_lw; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_ld; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_lbu; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_lhu; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_lwu; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_sb; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_sh; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_sw; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_sd; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_lr_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_sc_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoswap_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoadd_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoxor_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoand_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoor_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amomin_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amomax_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amominu_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amomaxu_w; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_lr_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_sc_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoswap_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoadd_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoxor_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoand_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amoor_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amomin_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amomax_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amominu_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_amomaxu_d; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_flw; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_fsw; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_fld; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_fsd; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_probe; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_grant; // @[Dcache.scala 123:23]
  wire  lsEntry_io_deq_bits_fun_preft; // @[Dcache.scala 123:23]
  wire  rtn_fifo_clock; // @[Dcache.scala 126:24]
  wire  rtn_fifo_reset; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_enq_ready; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_enq_valid; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_enq_bits_chkIdx; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_enq_bits_is_load_amo; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_enq_bits_is_flw; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_enq_bits_is_fld; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_deq_ready; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_deq_valid; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_deq_bits_chkIdx; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_deq_bits_is_load_amo; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_deq_bits_is_flw; // @[Dcache.scala 126:24]
  wire  rtn_fifo_io_deq_bits_is_fld; // @[Dcache.scala 126:24]
  wire  op_arb_io_in_0_ready; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_valid; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_chkIdx; // @[Dcache.scala 127:22]
  wire [31:0] op_arb_io_in_0_bits_paddr; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_lb; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_lh; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_lw; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_ld; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_lbu; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_lhu; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_lwu; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_sb; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_sh; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_sw; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_sd; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_lr_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_sc_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoswap_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoadd_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoxor_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoand_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoor_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amomin_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amomax_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amominu_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amomaxu_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_lr_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_sc_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoswap_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoadd_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoxor_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoand_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amoor_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amomin_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amomax_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amominu_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_amomaxu_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_flw; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_fsw; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_fld; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_fsd; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_probe; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_grant; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_0_bits_fun_preft; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_ready; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_valid; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_chkIdx; // @[Dcache.scala 127:22]
  wire [31:0] op_arb_io_in_1_bits_paddr; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_lb; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_lh; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_lw; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_ld; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_lbu; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_lhu; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_lwu; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_sb; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_sh; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_sw; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_sd; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_lr_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_sc_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoswap_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoadd_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoxor_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoand_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoor_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amomin_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amomax_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amominu_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amomaxu_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_lr_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_sc_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoswap_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoadd_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoxor_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoand_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amoor_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amomin_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amomax_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amominu_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_amomaxu_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_flw; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_fsw; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_fld; // @[Dcache.scala 127:22]
  wire  op_arb_io_in_1_bits_fun_fsd; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_ready; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_valid; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_chkIdx; // @[Dcache.scala 127:22]
  wire [31:0] op_arb_io_out_bits_paddr; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_lb; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_lh; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_lw; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_ld; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_lbu; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_lhu; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_lwu; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_sb; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_sh; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_sw; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_sd; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_lr_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_sc_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoswap_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoadd_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoxor_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoand_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoor_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amomin_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amomax_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amominu_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amomaxu_w; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_lr_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_sc_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoswap_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoadd_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoxor_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoand_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amoor_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amomin_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amomax_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amominu_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_amomaxu_d; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_flw; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_fsw; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_fld; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_fsd; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_probe; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_grant; // @[Dcache.scala 127:22]
  wire  op_arb_io_out_bits_fun_preft; // @[Dcache.scala 127:22]
  wire  rd_arb_io_in_0_valid; // @[Dcache.scala 128:22]
  wire [31:0] rd_arb_io_in_0_bits_paddr; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_1_ready; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_1_valid; // @[Dcache.scala 128:22]
  wire [31:0] rd_arb_io_in_1_bits_paddr; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_ready; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_valid; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_chkIdx; // @[Dcache.scala 128:22]
  wire [31:0] rd_arb_io_in_2_bits_paddr; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_lb; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_lh; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_lw; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_ld; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_lbu; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_lhu; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_lwu; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_sb; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_sh; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_sw; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_sd; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_lr_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_sc_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoswap_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoadd_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoxor_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoand_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoor_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amomin_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amomax_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amominu_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amomaxu_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_lr_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_sc_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoswap_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoadd_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoxor_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoand_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amoor_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amomin_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amomax_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amominu_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_amomaxu_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_flw; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_fsw; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_fld; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_fsd; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_probe; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_grant; // @[Dcache.scala 128:22]
  wire  rd_arb_io_in_2_bits_fun_preft; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_valid; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_chkIdx; // @[Dcache.scala 128:22]
  wire [31:0] rd_arb_io_out_bits_paddr; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_lb; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_lh; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_lw; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_ld; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_lbu; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_lhu; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_lwu; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_sb; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_sh; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_sw; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_sd; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_lr_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_sc_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoswap_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoadd_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoxor_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoand_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoor_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amomin_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amomax_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amominu_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amomaxu_w; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_lr_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_sc_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoswap_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoadd_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoxor_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoand_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amoor_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amomin_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amomax_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amominu_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_amomaxu_d; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_flw; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_fsw; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_fld; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_fsd; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_probe; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_grant; // @[Dcache.scala 128:22]
  wire  rd_arb_io_out_bits_fun_preft; // @[Dcache.scala 128:22]
  wire  reload_fifo_clock; // @[Dcache.scala 130:27]
  wire  reload_fifo_reset; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_ready; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_valid; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_chkIdx; // @[Dcache.scala 130:27]
  wire [31:0] reload_fifo_io_enq_bits_paddr; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_lb; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_lh; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_lw; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_ld; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_lbu; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_lhu; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_lwu; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_sb; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_sh; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_sw; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_sd; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_lr_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_sc_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoswap_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoadd_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoxor_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoand_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoor_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amomin_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amomax_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amominu_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amomaxu_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_lr_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_sc_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoswap_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoadd_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoxor_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoand_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amoor_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amomin_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amomax_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amominu_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_amomaxu_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_flw; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_fsw; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_fld; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_fsd; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_probe; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_grant; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_enq_bits_fun_preft; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_ready; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_valid; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_chkIdx; // @[Dcache.scala 130:27]
  wire [31:0] reload_fifo_io_deq_bits_paddr; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_lb; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_lh; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_lw; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_ld; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_lbu; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_lhu; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_lwu; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_sb; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_sh; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_sw; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_sd; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_lr_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_sc_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoswap_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoadd_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoxor_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoand_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoor_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amomin_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amomax_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amominu_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amomaxu_w; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_lr_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_sc_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoswap_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoadd_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoxor_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoand_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amoor_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amomin_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amomax_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amominu_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_amomaxu_d; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_flw; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_fsw; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_fld; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_fsd; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_probe; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_grant; // @[Dcache.scala 130:27]
  wire  reload_fifo_io_deq_bits_fun_preft; // @[Dcache.scala 130:27]
  wire  stage_clock; // @[Dcache.scala 132:21]
  wire  stage_reset; // @[Dcache.scala 132:21]
  wire  stage_io_enq_ready; // @[Dcache.scala 132:21]
  wire  stage_io_enq_valid; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_chkIdx; // @[Dcache.scala 132:21]
  wire [31:0] stage_io_enq_bits_paddr; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_lb; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_lh; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_lw; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_ld; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_lbu; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_lhu; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_lwu; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_sb; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_sh; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_sw; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_sd; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_lr_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_sc_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoswap_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoadd_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoxor_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoand_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoor_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amomin_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amomax_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amominu_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amomaxu_w; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_lr_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_sc_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoswap_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoadd_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoxor_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoand_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amoor_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amomin_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amomax_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amominu_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_amomaxu_d; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_flw; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_fsw; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_fld; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_fsd; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_probe; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_grant; // @[Dcache.scala 132:21]
  wire  stage_io_enq_bits_fun_preft; // @[Dcache.scala 132:21]
  wire  stage_io_reload_valid; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_chkIdx; // @[Dcache.scala 132:21]
  wire [31:0] stage_io_reload_bits_paddr; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_lb; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_lh; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_lw; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_ld; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_lbu; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_lhu; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_lwu; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_sb; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_sh; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_sw; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_sd; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_lr_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_sc_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoswap_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoadd_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoxor_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoand_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoor_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amomin_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amomax_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amominu_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amomaxu_w; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_lr_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_sc_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoswap_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoadd_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoxor_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoand_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amoor_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amomin_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amomax_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amominu_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_amomaxu_d; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_flw; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_fsw; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_fld; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_fsd; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_probe; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_grant; // @[Dcache.scala 132:21]
  wire  stage_io_reload_bits_fun_preft; // @[Dcache.scala 132:21]
  wire  stage_io_deq_valid; // @[Dcache.scala 132:21]
  wire  stage_io_deq_bits_chkIdx; // @[Dcache.scala 132:21]
  wire  stage_io_deq_bits_is_load_amo; // @[Dcache.scala 132:21]
  wire  stage_io_deq_bits_is_flw; // @[Dcache.scala 132:21]
  wire  stage_io_deq_bits_is_fld; // @[Dcache.scala 132:21]
  wire  stage_io_missUnit_req_valid; // @[Dcache.scala 132:21]
  wire [31:0] stage_io_missUnit_req_bits_paddr; // @[Dcache.scala 132:21]
  wire  stage_io_wb_req_valid; // @[Dcache.scala 132:21]
  wire  stage_io_wb_req_bits_is_releaseData; // @[Dcache.scala 132:21]
  wire  stage_io_wb_req_bits_is_release; // @[Dcache.scala 132:21]
  wire  stage_io_wb_req_bits_is_probe; // @[Dcache.scala 132:21]
  wire  stage_io_wb_req_bits_is_probeData; // @[Dcache.scala 132:21]
  wire  stage_io_isCacheEmpty; // @[Dcache.scala 132:21]
  wire  stage_io_flush; // @[Dcache.scala 132:21]
  reg [31:0] sbBuff_0_paddr; // @[Dcache.scala 138:23]
  reg [31:0] sbBuff_1_paddr; // @[Dcache.scala 138:23]
  reg  sbValid_0; // @[Dcache.scala 139:24]
  reg  sbValid_1; // @[Dcache.scala 139:24]
  wire  isHazard = sbBuff_0_paddr[31:3] == io_enq_bits_paddr[31:3] | sbBuff_1_paddr[31:3] == io_enq_bits_paddr[31:3]; // @[Dcache.scala 142:106]
  wire  _sbIdx_T = ~sbValid_0; // @[Dcache.scala 143:50]
  wire  sbIdx = ~sbValid_0 ? 1'h0 : 1'h1; // @[Dcache.scala 143:33]
  wire  _sbEnqReady_T_1 = ~sbValid_1; // @[Dcache.scala 147:36]
  wire  _sbEnqReady_T_4 = ~isHazard; // @[Dcache.scala 148:5]
  wire  sbEnqReady = (_sbIdx_T | ~sbValid_1) & _sbEnqReady_T_4; // @[Dcache.scala 147:51]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire [31:0] _GEN_2 = ~sbIdx ? io_enq_bits_paddr : sbBuff_0_paddr; // @[Dcache.scala 151:{20,20} 138:23]
  wire [31:0] _GEN_3 = sbIdx ? io_enq_bits_paddr : sbBuff_1_paddr; // @[Dcache.scala 151:{20,20} 138:23]
  wire  _GEN_96 = ~sbIdx | sbValid_0; // @[Dcache.scala 152:{20,20} 139:24]
  wire  _GEN_97 = sbIdx | sbValid_1; // @[Dcache.scala 152:{20,20} 139:24]
  wire [31:0] _GEN_100 = _T ? _GEN_2 : sbBuff_0_paddr; // @[Dcache.scala 138:23 150:23]
  wire [31:0] _GEN_101 = _T ? _GEN_3 : sbBuff_1_paddr; // @[Dcache.scala 138:23 150:23]
  wire  _GEN_194 = _T ? _GEN_96 : sbValid_0; // @[Dcache.scala 150:23 139:24]
  wire  _GEN_195 = _T ? _GEN_97 : sbValid_1; // @[Dcache.scala 150:23 139:24]
  wire  _T_1 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  isSBEmpty = _sbIdx_T & _sbEnqReady_T_1; // @[Dcache.scala 160:33]
  wire  _T_5 = ~reset; // @[Dcache.scala 161:31]
  wire [1:0] _T_10 = 1'h1 + (sbBuff_1_paddr == sbBuff_0_paddr); // @[Dcache.scala 168:27]
  wire [1:0] _T_19 = (sbBuff_0_paddr == sbBuff_1_paddr) + 1'h1; // @[Dcache.scala 168:27]
  MissUnit missUnit ( // @[Dcache.scala 116:46]
    .clock(missUnit_clock),
    .reset(missUnit_reset),
    .io_req_valid(missUnit_io_req_valid),
    .io_req_bits_paddr(missUnit_io_req_bits_paddr),
    .io_rsp_valid(missUnit_io_rsp_valid),
    .io_rsp_bits_paddr(missUnit_io_rsp_bits_paddr),
    .io_cache_acquire_ready(missUnit_io_cache_acquire_ready),
    .io_cache_acquire_valid(missUnit_io_cache_acquire_valid),
    .io_cache_grant_ready(missUnit_io_cache_grant_ready),
    .io_cache_grant_valid(missUnit_io_cache_grant_valid),
    .io_cache_grant_bits_opcode(missUnit_io_cache_grant_bits_opcode),
    .io_cache_grant_bits_size(missUnit_io_cache_grant_bits_size),
    .io_cache_grant_bits_source(missUnit_io_cache_grant_bits_source),
    .io_cache_grantAck_ready(missUnit_io_cache_grantAck_ready),
    .io_cache_grantAck_valid(missUnit_io_cache_grantAck_valid),
    .io_miss_ban(missUnit_io_miss_ban),
    .io_release_ban(missUnit_io_release_ban)
  );
  ProbeUnit probeUnit ( // @[Dcache.scala 117:46]
    .clock(probeUnit_clock),
    .reset(probeUnit_reset),
    .io_cache_probe_valid(probeUnit_io_cache_probe_valid),
    .io_cache_probe_bits_address(probeUnit_io_cache_probe_bits_address),
    .io_req_ready(probeUnit_io_req_ready),
    .io_req_valid(probeUnit_io_req_valid),
    .io_req_bits_paddr(probeUnit_io_req_bits_paddr),
    .io_probeBan(probeUnit_io_probeBan)
  );
  WriteBackUnit writeBackUnit ( // @[Dcache.scala 118:46]
    .clock(writeBackUnit_clock),
    .reset(writeBackUnit_reset),
    .io_wb_req_valid(writeBackUnit_io_wb_req_valid),
    .io_wb_req_bits_is_releaseData(writeBackUnit_io_wb_req_bits_is_releaseData),
    .io_wb_req_bits_is_release(writeBackUnit_io_wb_req_bits_is_release),
    .io_wb_req_bits_is_probe(writeBackUnit_io_wb_req_bits_is_probe),
    .io_wb_req_bits_is_probeData(writeBackUnit_io_wb_req_bits_is_probeData),
    .io_cache_release_ready(writeBackUnit_io_cache_release_ready),
    .io_cache_release_valid(writeBackUnit_io_cache_release_valid),
    .io_cache_release_bits_opcode(writeBackUnit_io_cache_release_bits_opcode),
    .io_cache_release_bits_size(writeBackUnit_io_cache_release_bits_size),
    .io_cache_grant_ready(writeBackUnit_io_cache_grant_ready),
    .io_cache_grant_valid(writeBackUnit_io_cache_grant_valid),
    .io_cache_grant_bits_source(writeBackUnit_io_cache_grant_bits_source),
    .io_release_ban(writeBackUnit_io_release_ban),
    .io_miss_ban(writeBackUnit_io_miss_ban)
  );
  Queue_13 lsEntry ( // @[Dcache.scala 123:23]
    .clock(lsEntry_clock),
    .reset(lsEntry_reset),
    .io_enq_ready(lsEntry_io_enq_ready),
    .io_enq_valid(lsEntry_io_enq_valid),
    .io_enq_bits_chkIdx(lsEntry_io_enq_bits_chkIdx),
    .io_enq_bits_paddr(lsEntry_io_enq_bits_paddr),
    .io_enq_bits_fun_lb(lsEntry_io_enq_bits_fun_lb),
    .io_enq_bits_fun_lh(lsEntry_io_enq_bits_fun_lh),
    .io_enq_bits_fun_lw(lsEntry_io_enq_bits_fun_lw),
    .io_enq_bits_fun_ld(lsEntry_io_enq_bits_fun_ld),
    .io_enq_bits_fun_lbu(lsEntry_io_enq_bits_fun_lbu),
    .io_enq_bits_fun_lhu(lsEntry_io_enq_bits_fun_lhu),
    .io_enq_bits_fun_lwu(lsEntry_io_enq_bits_fun_lwu),
    .io_enq_bits_fun_sb(lsEntry_io_enq_bits_fun_sb),
    .io_enq_bits_fun_sh(lsEntry_io_enq_bits_fun_sh),
    .io_enq_bits_fun_sw(lsEntry_io_enq_bits_fun_sw),
    .io_enq_bits_fun_sd(lsEntry_io_enq_bits_fun_sd),
    .io_enq_bits_fun_lr_w(lsEntry_io_enq_bits_fun_lr_w),
    .io_enq_bits_fun_sc_w(lsEntry_io_enq_bits_fun_sc_w),
    .io_enq_bits_fun_amoswap_w(lsEntry_io_enq_bits_fun_amoswap_w),
    .io_enq_bits_fun_amoadd_w(lsEntry_io_enq_bits_fun_amoadd_w),
    .io_enq_bits_fun_amoxor_w(lsEntry_io_enq_bits_fun_amoxor_w),
    .io_enq_bits_fun_amoand_w(lsEntry_io_enq_bits_fun_amoand_w),
    .io_enq_bits_fun_amoor_w(lsEntry_io_enq_bits_fun_amoor_w),
    .io_enq_bits_fun_amomin_w(lsEntry_io_enq_bits_fun_amomin_w),
    .io_enq_bits_fun_amomax_w(lsEntry_io_enq_bits_fun_amomax_w),
    .io_enq_bits_fun_amominu_w(lsEntry_io_enq_bits_fun_amominu_w),
    .io_enq_bits_fun_amomaxu_w(lsEntry_io_enq_bits_fun_amomaxu_w),
    .io_enq_bits_fun_lr_d(lsEntry_io_enq_bits_fun_lr_d),
    .io_enq_bits_fun_sc_d(lsEntry_io_enq_bits_fun_sc_d),
    .io_enq_bits_fun_amoswap_d(lsEntry_io_enq_bits_fun_amoswap_d),
    .io_enq_bits_fun_amoadd_d(lsEntry_io_enq_bits_fun_amoadd_d),
    .io_enq_bits_fun_amoxor_d(lsEntry_io_enq_bits_fun_amoxor_d),
    .io_enq_bits_fun_amoand_d(lsEntry_io_enq_bits_fun_amoand_d),
    .io_enq_bits_fun_amoor_d(lsEntry_io_enq_bits_fun_amoor_d),
    .io_enq_bits_fun_amomin_d(lsEntry_io_enq_bits_fun_amomin_d),
    .io_enq_bits_fun_amomax_d(lsEntry_io_enq_bits_fun_amomax_d),
    .io_enq_bits_fun_amominu_d(lsEntry_io_enq_bits_fun_amominu_d),
    .io_enq_bits_fun_amomaxu_d(lsEntry_io_enq_bits_fun_amomaxu_d),
    .io_enq_bits_fun_flw(lsEntry_io_enq_bits_fun_flw),
    .io_enq_bits_fun_fsw(lsEntry_io_enq_bits_fun_fsw),
    .io_enq_bits_fun_fld(lsEntry_io_enq_bits_fun_fld),
    .io_enq_bits_fun_fsd(lsEntry_io_enq_bits_fun_fsd),
    .io_enq_bits_fun_probe(lsEntry_io_enq_bits_fun_probe),
    .io_enq_bits_fun_grant(lsEntry_io_enq_bits_fun_grant),
    .io_enq_bits_fun_preft(lsEntry_io_enq_bits_fun_preft),
    .io_deq_ready(lsEntry_io_deq_ready),
    .io_deq_valid(lsEntry_io_deq_valid),
    .io_deq_bits_chkIdx(lsEntry_io_deq_bits_chkIdx),
    .io_deq_bits_paddr(lsEntry_io_deq_bits_paddr),
    .io_deq_bits_fun_lb(lsEntry_io_deq_bits_fun_lb),
    .io_deq_bits_fun_lh(lsEntry_io_deq_bits_fun_lh),
    .io_deq_bits_fun_lw(lsEntry_io_deq_bits_fun_lw),
    .io_deq_bits_fun_ld(lsEntry_io_deq_bits_fun_ld),
    .io_deq_bits_fun_lbu(lsEntry_io_deq_bits_fun_lbu),
    .io_deq_bits_fun_lhu(lsEntry_io_deq_bits_fun_lhu),
    .io_deq_bits_fun_lwu(lsEntry_io_deq_bits_fun_lwu),
    .io_deq_bits_fun_sb(lsEntry_io_deq_bits_fun_sb),
    .io_deq_bits_fun_sh(lsEntry_io_deq_bits_fun_sh),
    .io_deq_bits_fun_sw(lsEntry_io_deq_bits_fun_sw),
    .io_deq_bits_fun_sd(lsEntry_io_deq_bits_fun_sd),
    .io_deq_bits_fun_lr_w(lsEntry_io_deq_bits_fun_lr_w),
    .io_deq_bits_fun_sc_w(lsEntry_io_deq_bits_fun_sc_w),
    .io_deq_bits_fun_amoswap_w(lsEntry_io_deq_bits_fun_amoswap_w),
    .io_deq_bits_fun_amoadd_w(lsEntry_io_deq_bits_fun_amoadd_w),
    .io_deq_bits_fun_amoxor_w(lsEntry_io_deq_bits_fun_amoxor_w),
    .io_deq_bits_fun_amoand_w(lsEntry_io_deq_bits_fun_amoand_w),
    .io_deq_bits_fun_amoor_w(lsEntry_io_deq_bits_fun_amoor_w),
    .io_deq_bits_fun_amomin_w(lsEntry_io_deq_bits_fun_amomin_w),
    .io_deq_bits_fun_amomax_w(lsEntry_io_deq_bits_fun_amomax_w),
    .io_deq_bits_fun_amominu_w(lsEntry_io_deq_bits_fun_amominu_w),
    .io_deq_bits_fun_amomaxu_w(lsEntry_io_deq_bits_fun_amomaxu_w),
    .io_deq_bits_fun_lr_d(lsEntry_io_deq_bits_fun_lr_d),
    .io_deq_bits_fun_sc_d(lsEntry_io_deq_bits_fun_sc_d),
    .io_deq_bits_fun_amoswap_d(lsEntry_io_deq_bits_fun_amoswap_d),
    .io_deq_bits_fun_amoadd_d(lsEntry_io_deq_bits_fun_amoadd_d),
    .io_deq_bits_fun_amoxor_d(lsEntry_io_deq_bits_fun_amoxor_d),
    .io_deq_bits_fun_amoand_d(lsEntry_io_deq_bits_fun_amoand_d),
    .io_deq_bits_fun_amoor_d(lsEntry_io_deq_bits_fun_amoor_d),
    .io_deq_bits_fun_amomin_d(lsEntry_io_deq_bits_fun_amomin_d),
    .io_deq_bits_fun_amomax_d(lsEntry_io_deq_bits_fun_amomax_d),
    .io_deq_bits_fun_amominu_d(lsEntry_io_deq_bits_fun_amominu_d),
    .io_deq_bits_fun_amomaxu_d(lsEntry_io_deq_bits_fun_amomaxu_d),
    .io_deq_bits_fun_flw(lsEntry_io_deq_bits_fun_flw),
    .io_deq_bits_fun_fsw(lsEntry_io_deq_bits_fun_fsw),
    .io_deq_bits_fun_fld(lsEntry_io_deq_bits_fun_fld),
    .io_deq_bits_fun_fsd(lsEntry_io_deq_bits_fun_fsd),
    .io_deq_bits_fun_probe(lsEntry_io_deq_bits_fun_probe),
    .io_deq_bits_fun_grant(lsEntry_io_deq_bits_fun_grant),
    .io_deq_bits_fun_preft(lsEntry_io_deq_bits_fun_preft)
  );
  Queue_14 rtn_fifo ( // @[Dcache.scala 126:24]
    .clock(rtn_fifo_clock),
    .reset(rtn_fifo_reset),
    .io_enq_ready(rtn_fifo_io_enq_ready),
    .io_enq_valid(rtn_fifo_io_enq_valid),
    .io_enq_bits_chkIdx(rtn_fifo_io_enq_bits_chkIdx),
    .io_enq_bits_is_load_amo(rtn_fifo_io_enq_bits_is_load_amo),
    .io_enq_bits_is_flw(rtn_fifo_io_enq_bits_is_flw),
    .io_enq_bits_is_fld(rtn_fifo_io_enq_bits_is_fld),
    .io_deq_ready(rtn_fifo_io_deq_ready),
    .io_deq_valid(rtn_fifo_io_deq_valid),
    .io_deq_bits_chkIdx(rtn_fifo_io_deq_bits_chkIdx),
    .io_deq_bits_is_load_amo(rtn_fifo_io_deq_bits_is_load_amo),
    .io_deq_bits_is_flw(rtn_fifo_io_deq_bits_is_flw),
    .io_deq_bits_is_fld(rtn_fifo_io_deq_bits_is_fld)
  );
  Arbiter_1 op_arb ( // @[Dcache.scala 127:22]
    .io_in_0_ready(op_arb_io_in_0_ready),
    .io_in_0_valid(op_arb_io_in_0_valid),
    .io_in_0_bits_chkIdx(op_arb_io_in_0_bits_chkIdx),
    .io_in_0_bits_paddr(op_arb_io_in_0_bits_paddr),
    .io_in_0_bits_fun_lb(op_arb_io_in_0_bits_fun_lb),
    .io_in_0_bits_fun_lh(op_arb_io_in_0_bits_fun_lh),
    .io_in_0_bits_fun_lw(op_arb_io_in_0_bits_fun_lw),
    .io_in_0_bits_fun_ld(op_arb_io_in_0_bits_fun_ld),
    .io_in_0_bits_fun_lbu(op_arb_io_in_0_bits_fun_lbu),
    .io_in_0_bits_fun_lhu(op_arb_io_in_0_bits_fun_lhu),
    .io_in_0_bits_fun_lwu(op_arb_io_in_0_bits_fun_lwu),
    .io_in_0_bits_fun_sb(op_arb_io_in_0_bits_fun_sb),
    .io_in_0_bits_fun_sh(op_arb_io_in_0_bits_fun_sh),
    .io_in_0_bits_fun_sw(op_arb_io_in_0_bits_fun_sw),
    .io_in_0_bits_fun_sd(op_arb_io_in_0_bits_fun_sd),
    .io_in_0_bits_fun_lr_w(op_arb_io_in_0_bits_fun_lr_w),
    .io_in_0_bits_fun_sc_w(op_arb_io_in_0_bits_fun_sc_w),
    .io_in_0_bits_fun_amoswap_w(op_arb_io_in_0_bits_fun_amoswap_w),
    .io_in_0_bits_fun_amoadd_w(op_arb_io_in_0_bits_fun_amoadd_w),
    .io_in_0_bits_fun_amoxor_w(op_arb_io_in_0_bits_fun_amoxor_w),
    .io_in_0_bits_fun_amoand_w(op_arb_io_in_0_bits_fun_amoand_w),
    .io_in_0_bits_fun_amoor_w(op_arb_io_in_0_bits_fun_amoor_w),
    .io_in_0_bits_fun_amomin_w(op_arb_io_in_0_bits_fun_amomin_w),
    .io_in_0_bits_fun_amomax_w(op_arb_io_in_0_bits_fun_amomax_w),
    .io_in_0_bits_fun_amominu_w(op_arb_io_in_0_bits_fun_amominu_w),
    .io_in_0_bits_fun_amomaxu_w(op_arb_io_in_0_bits_fun_amomaxu_w),
    .io_in_0_bits_fun_lr_d(op_arb_io_in_0_bits_fun_lr_d),
    .io_in_0_bits_fun_sc_d(op_arb_io_in_0_bits_fun_sc_d),
    .io_in_0_bits_fun_amoswap_d(op_arb_io_in_0_bits_fun_amoswap_d),
    .io_in_0_bits_fun_amoadd_d(op_arb_io_in_0_bits_fun_amoadd_d),
    .io_in_0_bits_fun_amoxor_d(op_arb_io_in_0_bits_fun_amoxor_d),
    .io_in_0_bits_fun_amoand_d(op_arb_io_in_0_bits_fun_amoand_d),
    .io_in_0_bits_fun_amoor_d(op_arb_io_in_0_bits_fun_amoor_d),
    .io_in_0_bits_fun_amomin_d(op_arb_io_in_0_bits_fun_amomin_d),
    .io_in_0_bits_fun_amomax_d(op_arb_io_in_0_bits_fun_amomax_d),
    .io_in_0_bits_fun_amominu_d(op_arb_io_in_0_bits_fun_amominu_d),
    .io_in_0_bits_fun_amomaxu_d(op_arb_io_in_0_bits_fun_amomaxu_d),
    .io_in_0_bits_fun_flw(op_arb_io_in_0_bits_fun_flw),
    .io_in_0_bits_fun_fsw(op_arb_io_in_0_bits_fun_fsw),
    .io_in_0_bits_fun_fld(op_arb_io_in_0_bits_fun_fld),
    .io_in_0_bits_fun_fsd(op_arb_io_in_0_bits_fun_fsd),
    .io_in_0_bits_fun_probe(op_arb_io_in_0_bits_fun_probe),
    .io_in_0_bits_fun_grant(op_arb_io_in_0_bits_fun_grant),
    .io_in_0_bits_fun_preft(op_arb_io_in_0_bits_fun_preft),
    .io_in_1_ready(op_arb_io_in_1_ready),
    .io_in_1_valid(op_arb_io_in_1_valid),
    .io_in_1_bits_chkIdx(op_arb_io_in_1_bits_chkIdx),
    .io_in_1_bits_paddr(op_arb_io_in_1_bits_paddr),
    .io_in_1_bits_fun_lb(op_arb_io_in_1_bits_fun_lb),
    .io_in_1_bits_fun_lh(op_arb_io_in_1_bits_fun_lh),
    .io_in_1_bits_fun_lw(op_arb_io_in_1_bits_fun_lw),
    .io_in_1_bits_fun_ld(op_arb_io_in_1_bits_fun_ld),
    .io_in_1_bits_fun_lbu(op_arb_io_in_1_bits_fun_lbu),
    .io_in_1_bits_fun_lhu(op_arb_io_in_1_bits_fun_lhu),
    .io_in_1_bits_fun_lwu(op_arb_io_in_1_bits_fun_lwu),
    .io_in_1_bits_fun_sb(op_arb_io_in_1_bits_fun_sb),
    .io_in_1_bits_fun_sh(op_arb_io_in_1_bits_fun_sh),
    .io_in_1_bits_fun_sw(op_arb_io_in_1_bits_fun_sw),
    .io_in_1_bits_fun_sd(op_arb_io_in_1_bits_fun_sd),
    .io_in_1_bits_fun_lr_w(op_arb_io_in_1_bits_fun_lr_w),
    .io_in_1_bits_fun_sc_w(op_arb_io_in_1_bits_fun_sc_w),
    .io_in_1_bits_fun_amoswap_w(op_arb_io_in_1_bits_fun_amoswap_w),
    .io_in_1_bits_fun_amoadd_w(op_arb_io_in_1_bits_fun_amoadd_w),
    .io_in_1_bits_fun_amoxor_w(op_arb_io_in_1_bits_fun_amoxor_w),
    .io_in_1_bits_fun_amoand_w(op_arb_io_in_1_bits_fun_amoand_w),
    .io_in_1_bits_fun_amoor_w(op_arb_io_in_1_bits_fun_amoor_w),
    .io_in_1_bits_fun_amomin_w(op_arb_io_in_1_bits_fun_amomin_w),
    .io_in_1_bits_fun_amomax_w(op_arb_io_in_1_bits_fun_amomax_w),
    .io_in_1_bits_fun_amominu_w(op_arb_io_in_1_bits_fun_amominu_w),
    .io_in_1_bits_fun_amomaxu_w(op_arb_io_in_1_bits_fun_amomaxu_w),
    .io_in_1_bits_fun_lr_d(op_arb_io_in_1_bits_fun_lr_d),
    .io_in_1_bits_fun_sc_d(op_arb_io_in_1_bits_fun_sc_d),
    .io_in_1_bits_fun_amoswap_d(op_arb_io_in_1_bits_fun_amoswap_d),
    .io_in_1_bits_fun_amoadd_d(op_arb_io_in_1_bits_fun_amoadd_d),
    .io_in_1_bits_fun_amoxor_d(op_arb_io_in_1_bits_fun_amoxor_d),
    .io_in_1_bits_fun_amoand_d(op_arb_io_in_1_bits_fun_amoand_d),
    .io_in_1_bits_fun_amoor_d(op_arb_io_in_1_bits_fun_amoor_d),
    .io_in_1_bits_fun_amomin_d(op_arb_io_in_1_bits_fun_amomin_d),
    .io_in_1_bits_fun_amomax_d(op_arb_io_in_1_bits_fun_amomax_d),
    .io_in_1_bits_fun_amominu_d(op_arb_io_in_1_bits_fun_amominu_d),
    .io_in_1_bits_fun_amomaxu_d(op_arb_io_in_1_bits_fun_amomaxu_d),
    .io_in_1_bits_fun_flw(op_arb_io_in_1_bits_fun_flw),
    .io_in_1_bits_fun_fsw(op_arb_io_in_1_bits_fun_fsw),
    .io_in_1_bits_fun_fld(op_arb_io_in_1_bits_fun_fld),
    .io_in_1_bits_fun_fsd(op_arb_io_in_1_bits_fun_fsd),
    .io_out_ready(op_arb_io_out_ready),
    .io_out_valid(op_arb_io_out_valid),
    .io_out_bits_chkIdx(op_arb_io_out_bits_chkIdx),
    .io_out_bits_paddr(op_arb_io_out_bits_paddr),
    .io_out_bits_fun_lb(op_arb_io_out_bits_fun_lb),
    .io_out_bits_fun_lh(op_arb_io_out_bits_fun_lh),
    .io_out_bits_fun_lw(op_arb_io_out_bits_fun_lw),
    .io_out_bits_fun_ld(op_arb_io_out_bits_fun_ld),
    .io_out_bits_fun_lbu(op_arb_io_out_bits_fun_lbu),
    .io_out_bits_fun_lhu(op_arb_io_out_bits_fun_lhu),
    .io_out_bits_fun_lwu(op_arb_io_out_bits_fun_lwu),
    .io_out_bits_fun_sb(op_arb_io_out_bits_fun_sb),
    .io_out_bits_fun_sh(op_arb_io_out_bits_fun_sh),
    .io_out_bits_fun_sw(op_arb_io_out_bits_fun_sw),
    .io_out_bits_fun_sd(op_arb_io_out_bits_fun_sd),
    .io_out_bits_fun_lr_w(op_arb_io_out_bits_fun_lr_w),
    .io_out_bits_fun_sc_w(op_arb_io_out_bits_fun_sc_w),
    .io_out_bits_fun_amoswap_w(op_arb_io_out_bits_fun_amoswap_w),
    .io_out_bits_fun_amoadd_w(op_arb_io_out_bits_fun_amoadd_w),
    .io_out_bits_fun_amoxor_w(op_arb_io_out_bits_fun_amoxor_w),
    .io_out_bits_fun_amoand_w(op_arb_io_out_bits_fun_amoand_w),
    .io_out_bits_fun_amoor_w(op_arb_io_out_bits_fun_amoor_w),
    .io_out_bits_fun_amomin_w(op_arb_io_out_bits_fun_amomin_w),
    .io_out_bits_fun_amomax_w(op_arb_io_out_bits_fun_amomax_w),
    .io_out_bits_fun_amominu_w(op_arb_io_out_bits_fun_amominu_w),
    .io_out_bits_fun_amomaxu_w(op_arb_io_out_bits_fun_amomaxu_w),
    .io_out_bits_fun_lr_d(op_arb_io_out_bits_fun_lr_d),
    .io_out_bits_fun_sc_d(op_arb_io_out_bits_fun_sc_d),
    .io_out_bits_fun_amoswap_d(op_arb_io_out_bits_fun_amoswap_d),
    .io_out_bits_fun_amoadd_d(op_arb_io_out_bits_fun_amoadd_d),
    .io_out_bits_fun_amoxor_d(op_arb_io_out_bits_fun_amoxor_d),
    .io_out_bits_fun_amoand_d(op_arb_io_out_bits_fun_amoand_d),
    .io_out_bits_fun_amoor_d(op_arb_io_out_bits_fun_amoor_d),
    .io_out_bits_fun_amomin_d(op_arb_io_out_bits_fun_amomin_d),
    .io_out_bits_fun_amomax_d(op_arb_io_out_bits_fun_amomax_d),
    .io_out_bits_fun_amominu_d(op_arb_io_out_bits_fun_amominu_d),
    .io_out_bits_fun_amomaxu_d(op_arb_io_out_bits_fun_amomaxu_d),
    .io_out_bits_fun_flw(op_arb_io_out_bits_fun_flw),
    .io_out_bits_fun_fsw(op_arb_io_out_bits_fun_fsw),
    .io_out_bits_fun_fld(op_arb_io_out_bits_fun_fld),
    .io_out_bits_fun_fsd(op_arb_io_out_bits_fun_fsd),
    .io_out_bits_fun_probe(op_arb_io_out_bits_fun_probe),
    .io_out_bits_fun_grant(op_arb_io_out_bits_fun_grant),
    .io_out_bits_fun_preft(op_arb_io_out_bits_fun_preft)
  );
  Arbiter_2 rd_arb ( // @[Dcache.scala 128:22]
    .io_in_0_valid(rd_arb_io_in_0_valid),
    .io_in_0_bits_paddr(rd_arb_io_in_0_bits_paddr),
    .io_in_1_ready(rd_arb_io_in_1_ready),
    .io_in_1_valid(rd_arb_io_in_1_valid),
    .io_in_1_bits_paddr(rd_arb_io_in_1_bits_paddr),
    .io_in_2_ready(rd_arb_io_in_2_ready),
    .io_in_2_valid(rd_arb_io_in_2_valid),
    .io_in_2_bits_chkIdx(rd_arb_io_in_2_bits_chkIdx),
    .io_in_2_bits_paddr(rd_arb_io_in_2_bits_paddr),
    .io_in_2_bits_fun_lb(rd_arb_io_in_2_bits_fun_lb),
    .io_in_2_bits_fun_lh(rd_arb_io_in_2_bits_fun_lh),
    .io_in_2_bits_fun_lw(rd_arb_io_in_2_bits_fun_lw),
    .io_in_2_bits_fun_ld(rd_arb_io_in_2_bits_fun_ld),
    .io_in_2_bits_fun_lbu(rd_arb_io_in_2_bits_fun_lbu),
    .io_in_2_bits_fun_lhu(rd_arb_io_in_2_bits_fun_lhu),
    .io_in_2_bits_fun_lwu(rd_arb_io_in_2_bits_fun_lwu),
    .io_in_2_bits_fun_sb(rd_arb_io_in_2_bits_fun_sb),
    .io_in_2_bits_fun_sh(rd_arb_io_in_2_bits_fun_sh),
    .io_in_2_bits_fun_sw(rd_arb_io_in_2_bits_fun_sw),
    .io_in_2_bits_fun_sd(rd_arb_io_in_2_bits_fun_sd),
    .io_in_2_bits_fun_lr_w(rd_arb_io_in_2_bits_fun_lr_w),
    .io_in_2_bits_fun_sc_w(rd_arb_io_in_2_bits_fun_sc_w),
    .io_in_2_bits_fun_amoswap_w(rd_arb_io_in_2_bits_fun_amoswap_w),
    .io_in_2_bits_fun_amoadd_w(rd_arb_io_in_2_bits_fun_amoadd_w),
    .io_in_2_bits_fun_amoxor_w(rd_arb_io_in_2_bits_fun_amoxor_w),
    .io_in_2_bits_fun_amoand_w(rd_arb_io_in_2_bits_fun_amoand_w),
    .io_in_2_bits_fun_amoor_w(rd_arb_io_in_2_bits_fun_amoor_w),
    .io_in_2_bits_fun_amomin_w(rd_arb_io_in_2_bits_fun_amomin_w),
    .io_in_2_bits_fun_amomax_w(rd_arb_io_in_2_bits_fun_amomax_w),
    .io_in_2_bits_fun_amominu_w(rd_arb_io_in_2_bits_fun_amominu_w),
    .io_in_2_bits_fun_amomaxu_w(rd_arb_io_in_2_bits_fun_amomaxu_w),
    .io_in_2_bits_fun_lr_d(rd_arb_io_in_2_bits_fun_lr_d),
    .io_in_2_bits_fun_sc_d(rd_arb_io_in_2_bits_fun_sc_d),
    .io_in_2_bits_fun_amoswap_d(rd_arb_io_in_2_bits_fun_amoswap_d),
    .io_in_2_bits_fun_amoadd_d(rd_arb_io_in_2_bits_fun_amoadd_d),
    .io_in_2_bits_fun_amoxor_d(rd_arb_io_in_2_bits_fun_amoxor_d),
    .io_in_2_bits_fun_amoand_d(rd_arb_io_in_2_bits_fun_amoand_d),
    .io_in_2_bits_fun_amoor_d(rd_arb_io_in_2_bits_fun_amoor_d),
    .io_in_2_bits_fun_amomin_d(rd_arb_io_in_2_bits_fun_amomin_d),
    .io_in_2_bits_fun_amomax_d(rd_arb_io_in_2_bits_fun_amomax_d),
    .io_in_2_bits_fun_amominu_d(rd_arb_io_in_2_bits_fun_amominu_d),
    .io_in_2_bits_fun_amomaxu_d(rd_arb_io_in_2_bits_fun_amomaxu_d),
    .io_in_2_bits_fun_flw(rd_arb_io_in_2_bits_fun_flw),
    .io_in_2_bits_fun_fsw(rd_arb_io_in_2_bits_fun_fsw),
    .io_in_2_bits_fun_fld(rd_arb_io_in_2_bits_fun_fld),
    .io_in_2_bits_fun_fsd(rd_arb_io_in_2_bits_fun_fsd),
    .io_in_2_bits_fun_probe(rd_arb_io_in_2_bits_fun_probe),
    .io_in_2_bits_fun_grant(rd_arb_io_in_2_bits_fun_grant),
    .io_in_2_bits_fun_preft(rd_arb_io_in_2_bits_fun_preft),
    .io_out_valid(rd_arb_io_out_valid),
    .io_out_bits_chkIdx(rd_arb_io_out_bits_chkIdx),
    .io_out_bits_paddr(rd_arb_io_out_bits_paddr),
    .io_out_bits_fun_lb(rd_arb_io_out_bits_fun_lb),
    .io_out_bits_fun_lh(rd_arb_io_out_bits_fun_lh),
    .io_out_bits_fun_lw(rd_arb_io_out_bits_fun_lw),
    .io_out_bits_fun_ld(rd_arb_io_out_bits_fun_ld),
    .io_out_bits_fun_lbu(rd_arb_io_out_bits_fun_lbu),
    .io_out_bits_fun_lhu(rd_arb_io_out_bits_fun_lhu),
    .io_out_bits_fun_lwu(rd_arb_io_out_bits_fun_lwu),
    .io_out_bits_fun_sb(rd_arb_io_out_bits_fun_sb),
    .io_out_bits_fun_sh(rd_arb_io_out_bits_fun_sh),
    .io_out_bits_fun_sw(rd_arb_io_out_bits_fun_sw),
    .io_out_bits_fun_sd(rd_arb_io_out_bits_fun_sd),
    .io_out_bits_fun_lr_w(rd_arb_io_out_bits_fun_lr_w),
    .io_out_bits_fun_sc_w(rd_arb_io_out_bits_fun_sc_w),
    .io_out_bits_fun_amoswap_w(rd_arb_io_out_bits_fun_amoswap_w),
    .io_out_bits_fun_amoadd_w(rd_arb_io_out_bits_fun_amoadd_w),
    .io_out_bits_fun_amoxor_w(rd_arb_io_out_bits_fun_amoxor_w),
    .io_out_bits_fun_amoand_w(rd_arb_io_out_bits_fun_amoand_w),
    .io_out_bits_fun_amoor_w(rd_arb_io_out_bits_fun_amoor_w),
    .io_out_bits_fun_amomin_w(rd_arb_io_out_bits_fun_amomin_w),
    .io_out_bits_fun_amomax_w(rd_arb_io_out_bits_fun_amomax_w),
    .io_out_bits_fun_amominu_w(rd_arb_io_out_bits_fun_amominu_w),
    .io_out_bits_fun_amomaxu_w(rd_arb_io_out_bits_fun_amomaxu_w),
    .io_out_bits_fun_lr_d(rd_arb_io_out_bits_fun_lr_d),
    .io_out_bits_fun_sc_d(rd_arb_io_out_bits_fun_sc_d),
    .io_out_bits_fun_amoswap_d(rd_arb_io_out_bits_fun_amoswap_d),
    .io_out_bits_fun_amoadd_d(rd_arb_io_out_bits_fun_amoadd_d),
    .io_out_bits_fun_amoxor_d(rd_arb_io_out_bits_fun_amoxor_d),
    .io_out_bits_fun_amoand_d(rd_arb_io_out_bits_fun_amoand_d),
    .io_out_bits_fun_amoor_d(rd_arb_io_out_bits_fun_amoor_d),
    .io_out_bits_fun_amomin_d(rd_arb_io_out_bits_fun_amomin_d),
    .io_out_bits_fun_amomax_d(rd_arb_io_out_bits_fun_amomax_d),
    .io_out_bits_fun_amominu_d(rd_arb_io_out_bits_fun_amominu_d),
    .io_out_bits_fun_amomaxu_d(rd_arb_io_out_bits_fun_amomaxu_d),
    .io_out_bits_fun_flw(rd_arb_io_out_bits_fun_flw),
    .io_out_bits_fun_fsw(rd_arb_io_out_bits_fun_fsw),
    .io_out_bits_fun_fld(rd_arb_io_out_bits_fun_fld),
    .io_out_bits_fun_fsd(rd_arb_io_out_bits_fun_fsd),
    .io_out_bits_fun_probe(rd_arb_io_out_bits_fun_probe),
    .io_out_bits_fun_grant(rd_arb_io_out_bits_fun_grant),
    .io_out_bits_fun_preft(rd_arb_io_out_bits_fun_preft)
  );
  Queue_15 reload_fifo ( // @[Dcache.scala 130:27]
    .clock(reload_fifo_clock),
    .reset(reload_fifo_reset),
    .io_enq_ready(reload_fifo_io_enq_ready),
    .io_enq_valid(reload_fifo_io_enq_valid),
    .io_enq_bits_chkIdx(reload_fifo_io_enq_bits_chkIdx),
    .io_enq_bits_paddr(reload_fifo_io_enq_bits_paddr),
    .io_enq_bits_fun_lb(reload_fifo_io_enq_bits_fun_lb),
    .io_enq_bits_fun_lh(reload_fifo_io_enq_bits_fun_lh),
    .io_enq_bits_fun_lw(reload_fifo_io_enq_bits_fun_lw),
    .io_enq_bits_fun_ld(reload_fifo_io_enq_bits_fun_ld),
    .io_enq_bits_fun_lbu(reload_fifo_io_enq_bits_fun_lbu),
    .io_enq_bits_fun_lhu(reload_fifo_io_enq_bits_fun_lhu),
    .io_enq_bits_fun_lwu(reload_fifo_io_enq_bits_fun_lwu),
    .io_enq_bits_fun_sb(reload_fifo_io_enq_bits_fun_sb),
    .io_enq_bits_fun_sh(reload_fifo_io_enq_bits_fun_sh),
    .io_enq_bits_fun_sw(reload_fifo_io_enq_bits_fun_sw),
    .io_enq_bits_fun_sd(reload_fifo_io_enq_bits_fun_sd),
    .io_enq_bits_fun_lr_w(reload_fifo_io_enq_bits_fun_lr_w),
    .io_enq_bits_fun_sc_w(reload_fifo_io_enq_bits_fun_sc_w),
    .io_enq_bits_fun_amoswap_w(reload_fifo_io_enq_bits_fun_amoswap_w),
    .io_enq_bits_fun_amoadd_w(reload_fifo_io_enq_bits_fun_amoadd_w),
    .io_enq_bits_fun_amoxor_w(reload_fifo_io_enq_bits_fun_amoxor_w),
    .io_enq_bits_fun_amoand_w(reload_fifo_io_enq_bits_fun_amoand_w),
    .io_enq_bits_fun_amoor_w(reload_fifo_io_enq_bits_fun_amoor_w),
    .io_enq_bits_fun_amomin_w(reload_fifo_io_enq_bits_fun_amomin_w),
    .io_enq_bits_fun_amomax_w(reload_fifo_io_enq_bits_fun_amomax_w),
    .io_enq_bits_fun_amominu_w(reload_fifo_io_enq_bits_fun_amominu_w),
    .io_enq_bits_fun_amomaxu_w(reload_fifo_io_enq_bits_fun_amomaxu_w),
    .io_enq_bits_fun_lr_d(reload_fifo_io_enq_bits_fun_lr_d),
    .io_enq_bits_fun_sc_d(reload_fifo_io_enq_bits_fun_sc_d),
    .io_enq_bits_fun_amoswap_d(reload_fifo_io_enq_bits_fun_amoswap_d),
    .io_enq_bits_fun_amoadd_d(reload_fifo_io_enq_bits_fun_amoadd_d),
    .io_enq_bits_fun_amoxor_d(reload_fifo_io_enq_bits_fun_amoxor_d),
    .io_enq_bits_fun_amoand_d(reload_fifo_io_enq_bits_fun_amoand_d),
    .io_enq_bits_fun_amoor_d(reload_fifo_io_enq_bits_fun_amoor_d),
    .io_enq_bits_fun_amomin_d(reload_fifo_io_enq_bits_fun_amomin_d),
    .io_enq_bits_fun_amomax_d(reload_fifo_io_enq_bits_fun_amomax_d),
    .io_enq_bits_fun_amominu_d(reload_fifo_io_enq_bits_fun_amominu_d),
    .io_enq_bits_fun_amomaxu_d(reload_fifo_io_enq_bits_fun_amomaxu_d),
    .io_enq_bits_fun_flw(reload_fifo_io_enq_bits_fun_flw),
    .io_enq_bits_fun_fsw(reload_fifo_io_enq_bits_fun_fsw),
    .io_enq_bits_fun_fld(reload_fifo_io_enq_bits_fun_fld),
    .io_enq_bits_fun_fsd(reload_fifo_io_enq_bits_fun_fsd),
    .io_enq_bits_fun_probe(reload_fifo_io_enq_bits_fun_probe),
    .io_enq_bits_fun_grant(reload_fifo_io_enq_bits_fun_grant),
    .io_enq_bits_fun_preft(reload_fifo_io_enq_bits_fun_preft),
    .io_deq_ready(reload_fifo_io_deq_ready),
    .io_deq_valid(reload_fifo_io_deq_valid),
    .io_deq_bits_chkIdx(reload_fifo_io_deq_bits_chkIdx),
    .io_deq_bits_paddr(reload_fifo_io_deq_bits_paddr),
    .io_deq_bits_fun_lb(reload_fifo_io_deq_bits_fun_lb),
    .io_deq_bits_fun_lh(reload_fifo_io_deq_bits_fun_lh),
    .io_deq_bits_fun_lw(reload_fifo_io_deq_bits_fun_lw),
    .io_deq_bits_fun_ld(reload_fifo_io_deq_bits_fun_ld),
    .io_deq_bits_fun_lbu(reload_fifo_io_deq_bits_fun_lbu),
    .io_deq_bits_fun_lhu(reload_fifo_io_deq_bits_fun_lhu),
    .io_deq_bits_fun_lwu(reload_fifo_io_deq_bits_fun_lwu),
    .io_deq_bits_fun_sb(reload_fifo_io_deq_bits_fun_sb),
    .io_deq_bits_fun_sh(reload_fifo_io_deq_bits_fun_sh),
    .io_deq_bits_fun_sw(reload_fifo_io_deq_bits_fun_sw),
    .io_deq_bits_fun_sd(reload_fifo_io_deq_bits_fun_sd),
    .io_deq_bits_fun_lr_w(reload_fifo_io_deq_bits_fun_lr_w),
    .io_deq_bits_fun_sc_w(reload_fifo_io_deq_bits_fun_sc_w),
    .io_deq_bits_fun_amoswap_w(reload_fifo_io_deq_bits_fun_amoswap_w),
    .io_deq_bits_fun_amoadd_w(reload_fifo_io_deq_bits_fun_amoadd_w),
    .io_deq_bits_fun_amoxor_w(reload_fifo_io_deq_bits_fun_amoxor_w),
    .io_deq_bits_fun_amoand_w(reload_fifo_io_deq_bits_fun_amoand_w),
    .io_deq_bits_fun_amoor_w(reload_fifo_io_deq_bits_fun_amoor_w),
    .io_deq_bits_fun_amomin_w(reload_fifo_io_deq_bits_fun_amomin_w),
    .io_deq_bits_fun_amomax_w(reload_fifo_io_deq_bits_fun_amomax_w),
    .io_deq_bits_fun_amominu_w(reload_fifo_io_deq_bits_fun_amominu_w),
    .io_deq_bits_fun_amomaxu_w(reload_fifo_io_deq_bits_fun_amomaxu_w),
    .io_deq_bits_fun_lr_d(reload_fifo_io_deq_bits_fun_lr_d),
    .io_deq_bits_fun_sc_d(reload_fifo_io_deq_bits_fun_sc_d),
    .io_deq_bits_fun_amoswap_d(reload_fifo_io_deq_bits_fun_amoswap_d),
    .io_deq_bits_fun_amoadd_d(reload_fifo_io_deq_bits_fun_amoadd_d),
    .io_deq_bits_fun_amoxor_d(reload_fifo_io_deq_bits_fun_amoxor_d),
    .io_deq_bits_fun_amoand_d(reload_fifo_io_deq_bits_fun_amoand_d),
    .io_deq_bits_fun_amoor_d(reload_fifo_io_deq_bits_fun_amoor_d),
    .io_deq_bits_fun_amomin_d(reload_fifo_io_deq_bits_fun_amomin_d),
    .io_deq_bits_fun_amomax_d(reload_fifo_io_deq_bits_fun_amomax_d),
    .io_deq_bits_fun_amominu_d(reload_fifo_io_deq_bits_fun_amominu_d),
    .io_deq_bits_fun_amomaxu_d(reload_fifo_io_deq_bits_fun_amomaxu_d),
    .io_deq_bits_fun_flw(reload_fifo_io_deq_bits_fun_flw),
    .io_deq_bits_fun_fsw(reload_fifo_io_deq_bits_fun_fsw),
    .io_deq_bits_fun_fld(reload_fifo_io_deq_bits_fun_fld),
    .io_deq_bits_fun_fsd(reload_fifo_io_deq_bits_fun_fsd),
    .io_deq_bits_fun_probe(reload_fifo_io_deq_bits_fun_probe),
    .io_deq_bits_fun_grant(reload_fifo_io_deq_bits_fun_grant),
    .io_deq_bits_fun_preft(reload_fifo_io_deq_bits_fun_preft)
  );
  DcacheStage stage ( // @[Dcache.scala 132:21]
    .clock(stage_clock),
    .reset(stage_reset),
    .io_enq_ready(stage_io_enq_ready),
    .io_enq_valid(stage_io_enq_valid),
    .io_enq_bits_chkIdx(stage_io_enq_bits_chkIdx),
    .io_enq_bits_paddr(stage_io_enq_bits_paddr),
    .io_enq_bits_fun_lb(stage_io_enq_bits_fun_lb),
    .io_enq_bits_fun_lh(stage_io_enq_bits_fun_lh),
    .io_enq_bits_fun_lw(stage_io_enq_bits_fun_lw),
    .io_enq_bits_fun_ld(stage_io_enq_bits_fun_ld),
    .io_enq_bits_fun_lbu(stage_io_enq_bits_fun_lbu),
    .io_enq_bits_fun_lhu(stage_io_enq_bits_fun_lhu),
    .io_enq_bits_fun_lwu(stage_io_enq_bits_fun_lwu),
    .io_enq_bits_fun_sb(stage_io_enq_bits_fun_sb),
    .io_enq_bits_fun_sh(stage_io_enq_bits_fun_sh),
    .io_enq_bits_fun_sw(stage_io_enq_bits_fun_sw),
    .io_enq_bits_fun_sd(stage_io_enq_bits_fun_sd),
    .io_enq_bits_fun_lr_w(stage_io_enq_bits_fun_lr_w),
    .io_enq_bits_fun_sc_w(stage_io_enq_bits_fun_sc_w),
    .io_enq_bits_fun_amoswap_w(stage_io_enq_bits_fun_amoswap_w),
    .io_enq_bits_fun_amoadd_w(stage_io_enq_bits_fun_amoadd_w),
    .io_enq_bits_fun_amoxor_w(stage_io_enq_bits_fun_amoxor_w),
    .io_enq_bits_fun_amoand_w(stage_io_enq_bits_fun_amoand_w),
    .io_enq_bits_fun_amoor_w(stage_io_enq_bits_fun_amoor_w),
    .io_enq_bits_fun_amomin_w(stage_io_enq_bits_fun_amomin_w),
    .io_enq_bits_fun_amomax_w(stage_io_enq_bits_fun_amomax_w),
    .io_enq_bits_fun_amominu_w(stage_io_enq_bits_fun_amominu_w),
    .io_enq_bits_fun_amomaxu_w(stage_io_enq_bits_fun_amomaxu_w),
    .io_enq_bits_fun_lr_d(stage_io_enq_bits_fun_lr_d),
    .io_enq_bits_fun_sc_d(stage_io_enq_bits_fun_sc_d),
    .io_enq_bits_fun_amoswap_d(stage_io_enq_bits_fun_amoswap_d),
    .io_enq_bits_fun_amoadd_d(stage_io_enq_bits_fun_amoadd_d),
    .io_enq_bits_fun_amoxor_d(stage_io_enq_bits_fun_amoxor_d),
    .io_enq_bits_fun_amoand_d(stage_io_enq_bits_fun_amoand_d),
    .io_enq_bits_fun_amoor_d(stage_io_enq_bits_fun_amoor_d),
    .io_enq_bits_fun_amomin_d(stage_io_enq_bits_fun_amomin_d),
    .io_enq_bits_fun_amomax_d(stage_io_enq_bits_fun_amomax_d),
    .io_enq_bits_fun_amominu_d(stage_io_enq_bits_fun_amominu_d),
    .io_enq_bits_fun_amomaxu_d(stage_io_enq_bits_fun_amomaxu_d),
    .io_enq_bits_fun_flw(stage_io_enq_bits_fun_flw),
    .io_enq_bits_fun_fsw(stage_io_enq_bits_fun_fsw),
    .io_enq_bits_fun_fld(stage_io_enq_bits_fun_fld),
    .io_enq_bits_fun_fsd(stage_io_enq_bits_fun_fsd),
    .io_enq_bits_fun_probe(stage_io_enq_bits_fun_probe),
    .io_enq_bits_fun_grant(stage_io_enq_bits_fun_grant),
    .io_enq_bits_fun_preft(stage_io_enq_bits_fun_preft),
    .io_reload_valid(stage_io_reload_valid),
    .io_reload_bits_chkIdx(stage_io_reload_bits_chkIdx),
    .io_reload_bits_paddr(stage_io_reload_bits_paddr),
    .io_reload_bits_fun_lb(stage_io_reload_bits_fun_lb),
    .io_reload_bits_fun_lh(stage_io_reload_bits_fun_lh),
    .io_reload_bits_fun_lw(stage_io_reload_bits_fun_lw),
    .io_reload_bits_fun_ld(stage_io_reload_bits_fun_ld),
    .io_reload_bits_fun_lbu(stage_io_reload_bits_fun_lbu),
    .io_reload_bits_fun_lhu(stage_io_reload_bits_fun_lhu),
    .io_reload_bits_fun_lwu(stage_io_reload_bits_fun_lwu),
    .io_reload_bits_fun_sb(stage_io_reload_bits_fun_sb),
    .io_reload_bits_fun_sh(stage_io_reload_bits_fun_sh),
    .io_reload_bits_fun_sw(stage_io_reload_bits_fun_sw),
    .io_reload_bits_fun_sd(stage_io_reload_bits_fun_sd),
    .io_reload_bits_fun_lr_w(stage_io_reload_bits_fun_lr_w),
    .io_reload_bits_fun_sc_w(stage_io_reload_bits_fun_sc_w),
    .io_reload_bits_fun_amoswap_w(stage_io_reload_bits_fun_amoswap_w),
    .io_reload_bits_fun_amoadd_w(stage_io_reload_bits_fun_amoadd_w),
    .io_reload_bits_fun_amoxor_w(stage_io_reload_bits_fun_amoxor_w),
    .io_reload_bits_fun_amoand_w(stage_io_reload_bits_fun_amoand_w),
    .io_reload_bits_fun_amoor_w(stage_io_reload_bits_fun_amoor_w),
    .io_reload_bits_fun_amomin_w(stage_io_reload_bits_fun_amomin_w),
    .io_reload_bits_fun_amomax_w(stage_io_reload_bits_fun_amomax_w),
    .io_reload_bits_fun_amominu_w(stage_io_reload_bits_fun_amominu_w),
    .io_reload_bits_fun_amomaxu_w(stage_io_reload_bits_fun_amomaxu_w),
    .io_reload_bits_fun_lr_d(stage_io_reload_bits_fun_lr_d),
    .io_reload_bits_fun_sc_d(stage_io_reload_bits_fun_sc_d),
    .io_reload_bits_fun_amoswap_d(stage_io_reload_bits_fun_amoswap_d),
    .io_reload_bits_fun_amoadd_d(stage_io_reload_bits_fun_amoadd_d),
    .io_reload_bits_fun_amoxor_d(stage_io_reload_bits_fun_amoxor_d),
    .io_reload_bits_fun_amoand_d(stage_io_reload_bits_fun_amoand_d),
    .io_reload_bits_fun_amoor_d(stage_io_reload_bits_fun_amoor_d),
    .io_reload_bits_fun_amomin_d(stage_io_reload_bits_fun_amomin_d),
    .io_reload_bits_fun_amomax_d(stage_io_reload_bits_fun_amomax_d),
    .io_reload_bits_fun_amominu_d(stage_io_reload_bits_fun_amominu_d),
    .io_reload_bits_fun_amomaxu_d(stage_io_reload_bits_fun_amomaxu_d),
    .io_reload_bits_fun_flw(stage_io_reload_bits_fun_flw),
    .io_reload_bits_fun_fsw(stage_io_reload_bits_fun_fsw),
    .io_reload_bits_fun_fld(stage_io_reload_bits_fun_fld),
    .io_reload_bits_fun_fsd(stage_io_reload_bits_fun_fsd),
    .io_reload_bits_fun_probe(stage_io_reload_bits_fun_probe),
    .io_reload_bits_fun_grant(stage_io_reload_bits_fun_grant),
    .io_reload_bits_fun_preft(stage_io_reload_bits_fun_preft),
    .io_deq_valid(stage_io_deq_valid),
    .io_deq_bits_chkIdx(stage_io_deq_bits_chkIdx),
    .io_deq_bits_is_load_amo(stage_io_deq_bits_is_load_amo),
    .io_deq_bits_is_flw(stage_io_deq_bits_is_flw),
    .io_deq_bits_is_fld(stage_io_deq_bits_is_fld),
    .io_missUnit_req_valid(stage_io_missUnit_req_valid),
    .io_missUnit_req_bits_paddr(stage_io_missUnit_req_bits_paddr),
    .io_wb_req_valid(stage_io_wb_req_valid),
    .io_wb_req_bits_is_releaseData(stage_io_wb_req_bits_is_releaseData),
    .io_wb_req_bits_is_release(stage_io_wb_req_bits_is_release),
    .io_wb_req_bits_is_probe(stage_io_wb_req_bits_is_probe),
    .io_wb_req_bits_is_probeData(stage_io_wb_req_bits_is_probeData),
    .io_isCacheEmpty(stage_io_isCacheEmpty),
    .io_flush(stage_io_flush)
  );
  assign io_enq_ready = op_arb_io_in_1_ready & sbEnqReady; // @[Dcache.scala 253:41]
  assign io_deq_valid = rtn_fifo_io_deq_valid; // @[Dcache.scala 273:19]
  assign io_deq_bits_chkIdx = rtn_fifo_io_deq_bits_chkIdx; // @[Dcache.scala 273:19]
  assign io_deq_bits_is_load_amo = rtn_fifo_io_deq_bits_is_load_amo; // @[Dcache.scala 273:19]
  assign io_deq_bits_is_flw = rtn_fifo_io_deq_bits_is_flw; // @[Dcache.scala 273:19]
  assign io_deq_bits_is_fld = rtn_fifo_io_deq_bits_is_fld; // @[Dcache.scala 273:19]
  assign io_is_empty = _sbIdx_T & _sbEnqReady_T_1; // @[Dcache.scala 160:33]
  assign io_writeBackUnit_dcache_release_valid = writeBackUnit_io_cache_release_valid; // @[Dcache.scala 188:41]
  assign io_writeBackUnit_dcache_release_bits_opcode = writeBackUnit_io_cache_release_bits_opcode; // @[Dcache.scala 188:41]
  assign io_writeBackUnit_dcache_release_bits_size = writeBackUnit_io_cache_release_bits_size; // @[Dcache.scala 188:41]
  assign missUnit_clock = clock;
  assign missUnit_reset = reset;
  assign missUnit_io_req_valid = stage_io_missUnit_req_valid; // @[Dcache.scala 216:32]
  assign missUnit_io_req_bits_paddr = stage_io_missUnit_req_bits_paddr; // @[Dcache.scala 216:32]
  assign missUnit_io_cache_acquire_ready = io_missUnit_dcache_acquire_ready; // @[Dcache.scala 184:37]
  assign missUnit_io_cache_grant_valid = io_missUnit_dcache_grant_valid; // @[Dcache.scala 185:33]
  assign missUnit_io_cache_grant_bits_opcode = io_missUnit_dcache_grant_bits_opcode; // @[Dcache.scala 185:33]
  assign missUnit_io_cache_grant_bits_size = io_missUnit_dcache_grant_bits_size; // @[Dcache.scala 185:33]
  assign missUnit_io_cache_grant_bits_source = io_missUnit_dcache_grant_bits_source; // @[Dcache.scala 185:33]
  assign missUnit_io_cache_grantAck_ready = io_missUnit_dcache_grantAck_ready; // @[Dcache.scala 186:37]
  assign missUnit_io_miss_ban = writeBackUnit_io_miss_ban; // @[Dcache.scala 220:30]
  assign probeUnit_clock = clock;
  assign probeUnit_reset = reset;
  assign probeUnit_io_cache_probe_valid = io_probeUnit_dcache_probe_valid; // @[Dcache.scala 187:34]
  assign probeUnit_io_cache_probe_bits_address = io_probeUnit_dcache_probe_bits_address; // @[Dcache.scala 187:34]
  assign probeUnit_io_req_ready = rd_arb_io_in_1_ready; // @[Dcache.scala 229:32]
  assign probeUnit_io_probeBan = writeBackUnit_io_miss_ban; // @[Dcache.scala 219:31]
  assign writeBackUnit_clock = clock;
  assign writeBackUnit_reset = reset;
  assign writeBackUnit_io_wb_req_valid = stage_io_wb_req_valid; // @[Dcache.scala 217:21]
  assign writeBackUnit_io_wb_req_bits_is_releaseData = stage_io_wb_req_bits_is_releaseData; // @[Dcache.scala 217:21]
  assign writeBackUnit_io_wb_req_bits_is_release = stage_io_wb_req_bits_is_release; // @[Dcache.scala 217:21]
  assign writeBackUnit_io_wb_req_bits_is_probe = stage_io_wb_req_bits_is_probe; // @[Dcache.scala 217:21]
  assign writeBackUnit_io_wb_req_bits_is_probeData = stage_io_wb_req_bits_is_probeData; // @[Dcache.scala 217:21]
  assign writeBackUnit_io_cache_release_ready = io_writeBackUnit_dcache_release_ready; // @[Dcache.scala 188:41]
  assign writeBackUnit_io_cache_grant_valid = io_writeBackUnit_dcache_grant_valid; // @[Dcache.scala 189:38]
  assign writeBackUnit_io_cache_grant_bits_source = io_writeBackUnit_dcache_grant_bits_source; // @[Dcache.scala 189:38]
  assign writeBackUnit_io_release_ban = missUnit_io_release_ban; // @[Dcache.scala 221:38]
  assign lsEntry_clock = clock;
  assign lsEntry_reset = reset;
  assign lsEntry_io_enq_valid = op_arb_io_out_valid; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_chkIdx = op_arb_io_out_bits_chkIdx; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_paddr = op_arb_io_out_bits_paddr; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_lb = op_arb_io_out_bits_fun_lb; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_lh = op_arb_io_out_bits_fun_lh; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_lw = op_arb_io_out_bits_fun_lw; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_ld = op_arb_io_out_bits_fun_ld; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_lbu = op_arb_io_out_bits_fun_lbu; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_lhu = op_arb_io_out_bits_fun_lhu; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_lwu = op_arb_io_out_bits_fun_lwu; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_sb = op_arb_io_out_bits_fun_sb; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_sh = op_arb_io_out_bits_fun_sh; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_sw = op_arb_io_out_bits_fun_sw; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_sd = op_arb_io_out_bits_fun_sd; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_lr_w = op_arb_io_out_bits_fun_lr_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_sc_w = op_arb_io_out_bits_fun_sc_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoswap_w = op_arb_io_out_bits_fun_amoswap_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoadd_w = op_arb_io_out_bits_fun_amoadd_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoxor_w = op_arb_io_out_bits_fun_amoxor_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoand_w = op_arb_io_out_bits_fun_amoand_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoor_w = op_arb_io_out_bits_fun_amoor_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amomin_w = op_arb_io_out_bits_fun_amomin_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amomax_w = op_arb_io_out_bits_fun_amomax_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amominu_w = op_arb_io_out_bits_fun_amominu_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amomaxu_w = op_arb_io_out_bits_fun_amomaxu_w; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_lr_d = op_arb_io_out_bits_fun_lr_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_sc_d = op_arb_io_out_bits_fun_sc_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoswap_d = op_arb_io_out_bits_fun_amoswap_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoadd_d = op_arb_io_out_bits_fun_amoadd_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoxor_d = op_arb_io_out_bits_fun_amoxor_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoand_d = op_arb_io_out_bits_fun_amoand_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amoor_d = op_arb_io_out_bits_fun_amoor_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amomin_d = op_arb_io_out_bits_fun_amomin_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amomax_d = op_arb_io_out_bits_fun_amomax_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amominu_d = op_arb_io_out_bits_fun_amominu_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_amomaxu_d = op_arb_io_out_bits_fun_amomaxu_d; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_flw = op_arb_io_out_bits_fun_flw; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_fsw = op_arb_io_out_bits_fun_fsw; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_fld = op_arb_io_out_bits_fun_fld; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_fsd = op_arb_io_out_bits_fun_fsd; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_probe = op_arb_io_out_bits_fun_probe; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_grant = op_arb_io_out_bits_fun_grant; // @[Dcache.scala 257:17]
  assign lsEntry_io_enq_bits_fun_preft = op_arb_io_out_bits_fun_preft; // @[Dcache.scala 257:17]
  assign lsEntry_io_deq_ready = rd_arb_io_in_2_ready; // @[Dcache.scala 264:18]
  assign rtn_fifo_clock = clock;
  assign rtn_fifo_reset = reset;
  assign rtn_fifo_io_enq_valid = stage_io_deq_valid; // @[Dcache.scala 270:25]
  assign rtn_fifo_io_enq_bits_chkIdx = stage_io_deq_bits_chkIdx; // @[Dcache.scala 271:25]
  assign rtn_fifo_io_enq_bits_is_load_amo = stage_io_deq_bits_is_load_amo; // @[Dcache.scala 271:25]
  assign rtn_fifo_io_enq_bits_is_flw = stage_io_deq_bits_is_flw; // @[Dcache.scala 271:25]
  assign rtn_fifo_io_enq_bits_is_fld = stage_io_deq_bits_is_fld; // @[Dcache.scala 271:25]
  assign rtn_fifo_io_deq_ready = io_deq_ready; // @[Dcache.scala 273:19]
  assign op_arb_io_in_0_valid = reload_fifo_io_deq_valid; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_chkIdx = reload_fifo_io_deq_bits_chkIdx; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_paddr = reload_fifo_io_deq_bits_paddr; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_lb = reload_fifo_io_deq_bits_fun_lb; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_lh = reload_fifo_io_deq_bits_fun_lh; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_lw = reload_fifo_io_deq_bits_fun_lw; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_ld = reload_fifo_io_deq_bits_fun_ld; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_lbu = reload_fifo_io_deq_bits_fun_lbu; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_lhu = reload_fifo_io_deq_bits_fun_lhu; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_lwu = reload_fifo_io_deq_bits_fun_lwu; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_sb = reload_fifo_io_deq_bits_fun_sb; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_sh = reload_fifo_io_deq_bits_fun_sh; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_sw = reload_fifo_io_deq_bits_fun_sw; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_sd = reload_fifo_io_deq_bits_fun_sd; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_lr_w = reload_fifo_io_deq_bits_fun_lr_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_sc_w = reload_fifo_io_deq_bits_fun_sc_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoswap_w = reload_fifo_io_deq_bits_fun_amoswap_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoadd_w = reload_fifo_io_deq_bits_fun_amoadd_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoxor_w = reload_fifo_io_deq_bits_fun_amoxor_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoand_w = reload_fifo_io_deq_bits_fun_amoand_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoor_w = reload_fifo_io_deq_bits_fun_amoor_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amomin_w = reload_fifo_io_deq_bits_fun_amomin_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amomax_w = reload_fifo_io_deq_bits_fun_amomax_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amominu_w = reload_fifo_io_deq_bits_fun_amominu_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amomaxu_w = reload_fifo_io_deq_bits_fun_amomaxu_w; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_lr_d = reload_fifo_io_deq_bits_fun_lr_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_sc_d = reload_fifo_io_deq_bits_fun_sc_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoswap_d = reload_fifo_io_deq_bits_fun_amoswap_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoadd_d = reload_fifo_io_deq_bits_fun_amoadd_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoxor_d = reload_fifo_io_deq_bits_fun_amoxor_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoand_d = reload_fifo_io_deq_bits_fun_amoand_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amoor_d = reload_fifo_io_deq_bits_fun_amoor_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amomin_d = reload_fifo_io_deq_bits_fun_amomin_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amomax_d = reload_fifo_io_deq_bits_fun_amomax_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amominu_d = reload_fifo_io_deq_bits_fun_amominu_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_amomaxu_d = reload_fifo_io_deq_bits_fun_amomaxu_d; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_flw = reload_fifo_io_deq_bits_fun_flw; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_fsw = reload_fifo_io_deq_bits_fun_fsw; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_fld = reload_fifo_io_deq_bits_fun_fld; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_fsd = reload_fifo_io_deq_bits_fun_fsd; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_probe = reload_fifo_io_deq_bits_fun_probe; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_grant = reload_fifo_io_deq_bits_fun_grant; // @[Dcache.scala 252:22]
  assign op_arb_io_in_0_bits_fun_preft = reload_fifo_io_deq_bits_fun_preft; // @[Dcache.scala 252:22]
  assign op_arb_io_in_1_valid = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  assign op_arb_io_in_1_bits_chkIdx = ~sbValid_0 ? 1'h0 : 1'h1; // @[Dcache.scala 143:33]
  assign op_arb_io_in_1_bits_paddr = io_enq_bits_paddr; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_lb = io_enq_bits_fun_lb; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_lh = io_enq_bits_fun_lh; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_lw = io_enq_bits_fun_lw; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_ld = io_enq_bits_fun_ld; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_lbu = io_enq_bits_fun_lbu; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_lhu = io_enq_bits_fun_lhu; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_lwu = io_enq_bits_fun_lwu; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_sb = io_enq_bits_fun_sb; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_sh = io_enq_bits_fun_sh; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_sw = io_enq_bits_fun_sw; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_sd = io_enq_bits_fun_sd; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_lr_w = io_enq_bits_fun_lr_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_sc_w = io_enq_bits_fun_sc_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoswap_w = io_enq_bits_fun_amoswap_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoadd_w = io_enq_bits_fun_amoadd_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoxor_w = io_enq_bits_fun_amoxor_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoand_w = io_enq_bits_fun_amoand_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoor_w = io_enq_bits_fun_amoor_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amomin_w = io_enq_bits_fun_amomin_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amomax_w = io_enq_bits_fun_amomax_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amominu_w = io_enq_bits_fun_amominu_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amomaxu_w = io_enq_bits_fun_amomaxu_w; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_lr_d = io_enq_bits_fun_lr_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_sc_d = io_enq_bits_fun_sc_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoswap_d = io_enq_bits_fun_amoswap_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoadd_d = io_enq_bits_fun_amoadd_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoxor_d = io_enq_bits_fun_amoxor_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoand_d = io_enq_bits_fun_amoand_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amoor_d = io_enq_bits_fun_amoor_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amomin_d = io_enq_bits_fun_amomin_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amomax_d = io_enq_bits_fun_amomax_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amominu_d = io_enq_bits_fun_amominu_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_amomaxu_d = io_enq_bits_fun_amomaxu_d; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_flw = io_enq_bits_fun_flw; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_fsw = io_enq_bits_fun_fsw; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_fld = io_enq_bits_fun_fld; // @[Dcache.scala 255:25]
  assign op_arb_io_in_1_bits_fun_fsd = io_enq_bits_fun_fsd; // @[Dcache.scala 255:25]
  assign op_arb_io_out_ready = lsEntry_io_enq_ready; // @[Dcache.scala 257:17]
  assign rd_arb_io_in_0_valid = missUnit_io_rsp_valid; // @[Dcache.scala 224:27]
  assign rd_arb_io_in_0_bits_paddr = missUnit_io_rsp_bits_paddr; // @[Util.scala 48:19 50:15]
  assign rd_arb_io_in_1_valid = probeUnit_io_req_valid; // @[Dcache.scala 228:27]
  assign rd_arb_io_in_1_bits_paddr = probeUnit_io_req_bits_paddr; // @[Util.scala 64:19 65:15]
  assign rd_arb_io_in_2_valid = lsEntry_io_deq_valid; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_chkIdx = lsEntry_io_deq_bits_chkIdx; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_paddr = lsEntry_io_deq_bits_paddr; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_lb = lsEntry_io_deq_bits_fun_lb; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_lh = lsEntry_io_deq_bits_fun_lh; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_lw = lsEntry_io_deq_bits_fun_lw; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_ld = lsEntry_io_deq_bits_fun_ld; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_lbu = lsEntry_io_deq_bits_fun_lbu; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_lhu = lsEntry_io_deq_bits_fun_lhu; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_lwu = lsEntry_io_deq_bits_fun_lwu; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_sb = lsEntry_io_deq_bits_fun_sb; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_sh = lsEntry_io_deq_bits_fun_sh; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_sw = lsEntry_io_deq_bits_fun_sw; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_sd = lsEntry_io_deq_bits_fun_sd; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_lr_w = lsEntry_io_deq_bits_fun_lr_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_sc_w = lsEntry_io_deq_bits_fun_sc_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoswap_w = lsEntry_io_deq_bits_fun_amoswap_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoadd_w = lsEntry_io_deq_bits_fun_amoadd_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoxor_w = lsEntry_io_deq_bits_fun_amoxor_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoand_w = lsEntry_io_deq_bits_fun_amoand_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoor_w = lsEntry_io_deq_bits_fun_amoor_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amomin_w = lsEntry_io_deq_bits_fun_amomin_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amomax_w = lsEntry_io_deq_bits_fun_amomax_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amominu_w = lsEntry_io_deq_bits_fun_amominu_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amomaxu_w = lsEntry_io_deq_bits_fun_amomaxu_w; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_lr_d = lsEntry_io_deq_bits_fun_lr_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_sc_d = lsEntry_io_deq_bits_fun_sc_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoswap_d = lsEntry_io_deq_bits_fun_amoswap_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoadd_d = lsEntry_io_deq_bits_fun_amoadd_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoxor_d = lsEntry_io_deq_bits_fun_amoxor_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoand_d = lsEntry_io_deq_bits_fun_amoand_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amoor_d = lsEntry_io_deq_bits_fun_amoor_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amomin_d = lsEntry_io_deq_bits_fun_amomin_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amomax_d = lsEntry_io_deq_bits_fun_amomax_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amominu_d = lsEntry_io_deq_bits_fun_amominu_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_amomaxu_d = lsEntry_io_deq_bits_fun_amomaxu_d; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_flw = lsEntry_io_deq_bits_fun_flw; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_fsw = lsEntry_io_deq_bits_fun_fsw; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_fld = lsEntry_io_deq_bits_fun_fld; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_fsd = lsEntry_io_deq_bits_fun_fsd; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_probe = lsEntry_io_deq_bits_fun_probe; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_grant = lsEntry_io_deq_bits_fun_grant; // @[Dcache.scala 264:18]
  assign rd_arb_io_in_2_bits_fun_preft = lsEntry_io_deq_bits_fun_preft; // @[Dcache.scala 264:18]
  assign reload_fifo_clock = clock;
  assign reload_fifo_reset = reset;
  assign reload_fifo_io_enq_valid = stage_io_reload_valid; // @[Dcache.scala 248:28]
  assign reload_fifo_io_enq_bits_chkIdx = stage_io_reload_bits_chkIdx; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_paddr = stage_io_reload_bits_paddr; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_lb = stage_io_reload_bits_fun_lb; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_lh = stage_io_reload_bits_fun_lh; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_lw = stage_io_reload_bits_fun_lw; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_ld = stage_io_reload_bits_fun_ld; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_lbu = stage_io_reload_bits_fun_lbu; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_lhu = stage_io_reload_bits_fun_lhu; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_lwu = stage_io_reload_bits_fun_lwu; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_sb = stage_io_reload_bits_fun_sb; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_sh = stage_io_reload_bits_fun_sh; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_sw = stage_io_reload_bits_fun_sw; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_sd = stage_io_reload_bits_fun_sd; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_lr_w = stage_io_reload_bits_fun_lr_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_sc_w = stage_io_reload_bits_fun_sc_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoswap_w = stage_io_reload_bits_fun_amoswap_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoadd_w = stage_io_reload_bits_fun_amoadd_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoxor_w = stage_io_reload_bits_fun_amoxor_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoand_w = stage_io_reload_bits_fun_amoand_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoor_w = stage_io_reload_bits_fun_amoor_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amomin_w = stage_io_reload_bits_fun_amomin_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amomax_w = stage_io_reload_bits_fun_amomax_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amominu_w = stage_io_reload_bits_fun_amominu_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amomaxu_w = stage_io_reload_bits_fun_amomaxu_w; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_lr_d = stage_io_reload_bits_fun_lr_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_sc_d = stage_io_reload_bits_fun_sc_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoswap_d = stage_io_reload_bits_fun_amoswap_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoadd_d = stage_io_reload_bits_fun_amoadd_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoxor_d = stage_io_reload_bits_fun_amoxor_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoand_d = stage_io_reload_bits_fun_amoand_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amoor_d = stage_io_reload_bits_fun_amoor_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amomin_d = stage_io_reload_bits_fun_amomin_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amomax_d = stage_io_reload_bits_fun_amomax_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amominu_d = stage_io_reload_bits_fun_amominu_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_amomaxu_d = stage_io_reload_bits_fun_amomaxu_d; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_flw = stage_io_reload_bits_fun_flw; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_fsw = stage_io_reload_bits_fun_fsw; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_fld = stage_io_reload_bits_fun_fld; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_fsd = stage_io_reload_bits_fun_fsd; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_probe = stage_io_reload_bits_fun_probe; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_grant = stage_io_reload_bits_fun_grant; // @[Dcache.scala 249:28]
  assign reload_fifo_io_enq_bits_fun_preft = stage_io_reload_bits_fun_preft; // @[Dcache.scala 249:28]
  assign reload_fifo_io_deq_ready = op_arb_io_in_0_ready; // @[Dcache.scala 252:22]
  assign stage_clock = clock;
  assign stage_reset = reset;
  assign stage_io_enq_valid = rd_arb_io_out_valid; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_chkIdx = rd_arb_io_out_bits_chkIdx; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_paddr = rd_arb_io_out_bits_paddr; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_lb = rd_arb_io_out_bits_fun_lb; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_lh = rd_arb_io_out_bits_fun_lh; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_lw = rd_arb_io_out_bits_fun_lw; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_ld = rd_arb_io_out_bits_fun_ld; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_lbu = rd_arb_io_out_bits_fun_lbu; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_lhu = rd_arb_io_out_bits_fun_lhu; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_lwu = rd_arb_io_out_bits_fun_lwu; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_sb = rd_arb_io_out_bits_fun_sb; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_sh = rd_arb_io_out_bits_fun_sh; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_sw = rd_arb_io_out_bits_fun_sw; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_sd = rd_arb_io_out_bits_fun_sd; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_lr_w = rd_arb_io_out_bits_fun_lr_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_sc_w = rd_arb_io_out_bits_fun_sc_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoswap_w = rd_arb_io_out_bits_fun_amoswap_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoadd_w = rd_arb_io_out_bits_fun_amoadd_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoxor_w = rd_arb_io_out_bits_fun_amoxor_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoand_w = rd_arb_io_out_bits_fun_amoand_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoor_w = rd_arb_io_out_bits_fun_amoor_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amomin_w = rd_arb_io_out_bits_fun_amomin_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amomax_w = rd_arb_io_out_bits_fun_amomax_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amominu_w = rd_arb_io_out_bits_fun_amominu_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amomaxu_w = rd_arb_io_out_bits_fun_amomaxu_w; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_lr_d = rd_arb_io_out_bits_fun_lr_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_sc_d = rd_arb_io_out_bits_fun_sc_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoswap_d = rd_arb_io_out_bits_fun_amoswap_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoadd_d = rd_arb_io_out_bits_fun_amoadd_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoxor_d = rd_arb_io_out_bits_fun_amoxor_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoand_d = rd_arb_io_out_bits_fun_amoand_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amoor_d = rd_arb_io_out_bits_fun_amoor_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amomin_d = rd_arb_io_out_bits_fun_amomin_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amomax_d = rd_arb_io_out_bits_fun_amomax_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amominu_d = rd_arb_io_out_bits_fun_amominu_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_amomaxu_d = rd_arb_io_out_bits_fun_amomaxu_d; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_flw = rd_arb_io_out_bits_fun_flw; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_fsw = rd_arb_io_out_bits_fun_fsw; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_fld = rd_arb_io_out_bits_fun_fld; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_fsd = rd_arb_io_out_bits_fun_fsd; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_probe = rd_arb_io_out_bits_fun_probe; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_grant = rd_arb_io_out_bits_fun_grant; // @[Dcache.scala 265:16]
  assign stage_io_enq_bits_fun_preft = rd_arb_io_out_bits_fun_preft; // @[Dcache.scala 265:16]
  assign stage_io_isCacheEmpty = _sbIdx_T & _sbEnqReady_T_1; // @[Dcache.scala 160:33]
  assign stage_io_flush = io_flush; // @[Dcache.scala 259:18]
  always @(posedge clock) begin
    if (reset) begin // @[Dcache.scala 138:23]
      sbBuff_0_paddr <= 32'h0; // @[Dcache.scala 138:23]
    end else if (_T_1) begin // @[Dcache.scala 155:23]
      if (~io_deq_bits_chkIdx) begin // @[Dcache.scala 156:33]
        sbBuff_0_paddr <= 32'h0; // @[Dcache.scala 156:33]
      end else begin
        sbBuff_0_paddr <= _GEN_100;
      end
    end else begin
      sbBuff_0_paddr <= _GEN_100;
    end
    if (reset) begin // @[Dcache.scala 138:23]
      sbBuff_1_paddr <= 32'h0; // @[Dcache.scala 138:23]
    end else if (_T_1) begin // @[Dcache.scala 155:23]
      if (io_deq_bits_chkIdx) begin // @[Dcache.scala 156:33]
        sbBuff_1_paddr <= 32'h0; // @[Dcache.scala 156:33]
      end else begin
        sbBuff_1_paddr <= _GEN_101;
      end
    end else begin
      sbBuff_1_paddr <= _GEN_101;
    end
    if (reset) begin // @[Dcache.scala 139:24]
      sbValid_0 <= 1'h0; // @[Dcache.scala 139:24]
    end else if (_T_1) begin // @[Dcache.scala 155:23]
      if (~io_deq_bits_chkIdx) begin // @[Dcache.scala 157:33]
        sbValid_0 <= 1'h0; // @[Dcache.scala 157:33]
      end else begin
        sbValid_0 <= _GEN_194;
      end
    end else begin
      sbValid_0 <= _GEN_194;
    end
    if (reset) begin // @[Dcache.scala 139:24]
      sbValid_1 <= 1'h0; // @[Dcache.scala 139:24]
    end else if (_T_1) begin // @[Dcache.scala 155:23]
      if (io_deq_bits_chkIdx) begin // @[Dcache.scala 157:33]
        sbValid_1 <= 1'h0; // @[Dcache.scala 157:33]
      end else begin
        sbValid_1 <= _GEN_195;
      end
    end else begin
      sbValid_1 <= _GEN_195;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1 & ~reset & ~(~isSBEmpty)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Dcache.scala:161 when( io.deq.fire ) { assert(~isSBEmpty) }\n"
            ); // @[Dcache.scala 161:31]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~isSBEmpty) & (_T_1 & ~reset)) begin
          $fatal; // @[Dcache.scala 161:31]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (sbValid_0 & _T_5 & ~(_T_10 == 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Dcache.scala:168 assert( sbBuff.count( (x: Dcache_Enq_Bundle) => (x.paddr === sbBuff(i).paddr) ) === 1.U )\n"
            ); // @[Dcache.scala 168:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_10 == 2'h1) & (sbValid_0 & _T_5)) begin
          $fatal; // @[Dcache.scala 168:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (sbValid_1 & _T_5 & ~(_T_19 == 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Dcache.scala:168 assert( sbBuff.count( (x: Dcache_Enq_Bundle) => (x.paddr === sbBuff(i).paddr) ) === 1.U )\n"
            ); // @[Dcache.scala 168:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_19 == 2'h1) & (sbValid_1 & _T_5)) begin
          $fatal; // @[Dcache.scala 168:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (reload_fifo_io_enq_valid & _T_5 & ~reload_fifo_io_enq_ready) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at Dcache, Pipeline stuck!\n    at Dcache.scala:281 when(reload_fifo.io.enq.valid) {assert(reload_fifo.io.enq.ready, \"Assert Failed at Dcache, Pipeline stuck!\")}\n"
            ); // @[Dcache.scala 281:41]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~reload_fifo_io_enq_ready & (reload_fifo_io_enq_valid & _T_5)) begin
          $fatal; // @[Dcache.scala 281:41]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (rtn_fifo_io_enq_valid & _T_5 & ~rtn_fifo_io_enq_ready) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at Dcache, Pipeline stuck!\n    at Dcache.scala:282 when(rtn_fifo.io.enq.valid) {assert(rtn_fifo.io.enq.ready, \"Assert Failed at Dcache, Pipeline stuck!\")}\n"
            ); // @[Dcache.scala 282:38]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rtn_fifo_io_enq_ready & (rtn_fifo_io_enq_valid & _T_5)) begin
          $fatal; // @[Dcache.scala 282:38]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sbBuff_0_paddr = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  sbBuff_1_paddr = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  sbValid_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  sbValid_1 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Arbiter_3(
  output  io_in_0_ready,
  input   io_in_0_valid,
  input   io_in_0_bits_is_flw,
  input   io_in_0_bits_is_fld,
  output  io_in_1_ready,
  input   io_in_1_valid,
  input   io_in_1_bits_is_flw,
  input   io_in_1_bits_is_fld,
  output  io_in_2_ready,
  input   io_in_2_valid,
  input   io_in_2_bits_is_flw,
  input   io_in_2_bits_is_fld,
  input   io_out_ready,
  output  io_out_valid,
  output  io_out_bits_is_flw,
  output  io_out_bits_is_fld
);
  wire  _GEN_5 = io_in_1_valid ? io_in_1_bits_is_flw : io_in_2_bits_is_flw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  _GEN_6 = io_in_1_valid ? io_in_1_bits_is_fld : io_in_2_bits_is_fld; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  grant_1 = ~io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  grant_2 = ~(io_in_0_valid | io_in_1_valid); // @[Arbiter.scala 45:78]
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
  assign io_in_1_ready = grant_1 & io_out_ready; // @[Arbiter.scala 146:19]
  assign io_in_2_ready = grant_2 & io_out_ready; // @[Arbiter.scala 146:19]
  assign io_out_valid = ~grant_2 | io_in_2_valid; // @[Arbiter.scala 147:31]
  assign io_out_bits_is_flw = io_in_0_valid ? io_in_0_bits_is_flw : _GEN_5; // @[Arbiter.scala 138:26 140:19]
  assign io_out_bits_is_fld = io_in_0_valid ? io_in_0_bits_is_fld : _GEN_6; // @[Arbiter.scala 138:26 140:19]
endmodule
module Queue_16(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_10 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_10 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_17(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_10 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_10 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Arbiter_4(
  output  io_in_0_ready,
  input   io_in_0_valid,
  output  io_in_1_ready,
  input   io_in_1_valid,
  output  io_in_2_ready,
  input   io_out_ready
);
  wire  grant_1 = ~io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  grant_2 = ~(io_in_0_valid | io_in_1_valid); // @[Arbiter.scala 45:78]
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
  assign io_in_1_ready = grant_1 & io_out_ready; // @[Arbiter.scala 146:19]
  assign io_in_2_ready = grant_2 & io_out_ready; // @[Arbiter.scala 146:19]
endmodule
module Arbiter_5(
  output  io_in_0_ready,
  input   io_out_ready
);
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
endmodule
module Arbiter_6(
  output  io_in_0_ready,
  input   io_out_ready
);
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
endmodule
module Arbiter_7(
  output  io_in_0_ready,
  input   io_out_ready
);
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
endmodule
module Lsu(
  input         clock,
  input         reset,
  input         io_lsu_iss_exe_valid,
  input         io_lsu_iss_exe_bits_fun_lb,
  input         io_lsu_iss_exe_bits_fun_lh,
  input         io_lsu_iss_exe_bits_fun_lw,
  input         io_lsu_iss_exe_bits_fun_ld,
  input         io_lsu_iss_exe_bits_fun_lbu,
  input         io_lsu_iss_exe_bits_fun_lhu,
  input         io_lsu_iss_exe_bits_fun_lwu,
  input         io_lsu_iss_exe_bits_fun_sb,
  input         io_lsu_iss_exe_bits_fun_sh,
  input         io_lsu_iss_exe_bits_fun_sw,
  input         io_lsu_iss_exe_bits_fun_sd,
  input         io_lsu_iss_exe_bits_fun_fence,
  input         io_lsu_iss_exe_bits_fun_fence_i,
  input         io_lsu_iss_exe_bits_fun_sfence_vma,
  input         io_lsu_iss_exe_bits_fun_lr_w,
  input         io_lsu_iss_exe_bits_fun_sc_w,
  input         io_lsu_iss_exe_bits_fun_amoswap_w,
  input         io_lsu_iss_exe_bits_fun_amoadd_w,
  input         io_lsu_iss_exe_bits_fun_amoxor_w,
  input         io_lsu_iss_exe_bits_fun_amoand_w,
  input         io_lsu_iss_exe_bits_fun_amoor_w,
  input         io_lsu_iss_exe_bits_fun_amomin_w,
  input         io_lsu_iss_exe_bits_fun_amomax_w,
  input         io_lsu_iss_exe_bits_fun_amominu_w,
  input         io_lsu_iss_exe_bits_fun_amomaxu_w,
  input         io_lsu_iss_exe_bits_fun_lr_d,
  input         io_lsu_iss_exe_bits_fun_sc_d,
  input         io_lsu_iss_exe_bits_fun_amoswap_d,
  input         io_lsu_iss_exe_bits_fun_amoadd_d,
  input         io_lsu_iss_exe_bits_fun_amoxor_d,
  input         io_lsu_iss_exe_bits_fun_amoand_d,
  input         io_lsu_iss_exe_bits_fun_amoor_d,
  input         io_lsu_iss_exe_bits_fun_amomin_d,
  input         io_lsu_iss_exe_bits_fun_amomax_d,
  input         io_lsu_iss_exe_bits_fun_amominu_d,
  input         io_lsu_iss_exe_bits_fun_amomaxu_d,
  input         io_lsu_iss_exe_bits_fun_flw,
  input         io_lsu_iss_exe_bits_fun_fsw,
  input         io_lsu_iss_exe_bits_fun_fld,
  input         io_lsu_iss_exe_bits_fun_fsd,
  input  [63:0] io_lsu_iss_exe_bits_param_dat_op1,
  input         io_lsu_exe_iwb_ready,
  input         io_lsu_exe_fwb_ready,
  input         io_cmm_lsu_is_amo_pending,
  input         io_cmm_lsu_is_store_commit_0,
  input         io_mmu_lsu_valid,
  input  [63:0] io_mmu_lsu_bits_paddr,
  input         io_mmu_lsu_bits_is_paging_fault,
  input         io_mmu_lsu_bits_is_access_fault,
  input         io_missUnit_dcache_acquire_ready,
  input         io_missUnit_dcache_grant_valid,
  input  [2:0]  io_missUnit_dcache_grant_bits_opcode,
  input  [2:0]  io_missUnit_dcache_grant_bits_size,
  input         io_missUnit_dcache_grant_bits_source,
  input         io_missUnit_dcache_grantAck_ready,
  input         io_probeUnit_dcache_probe_valid,
  input  [31:0] io_probeUnit_dcache_probe_bits_address,
  input         io_writeBackUnit_dcache_release_ready,
  input         io_writeBackUnit_dcache_grant_valid,
  input         io_writeBackUnit_dcache_grant_bits_source,
  input         io_system_getPut_ready,
  input         io_system_access_valid,
  input  [2:0]  io_system_access_bits_opcode,
  input         io_periph_getPut_ready,
  input         io_periph_access_valid,
  input  [2:0]  io_periph_access_bits_opcode,
  input         io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  stQueue_clock; // @[Lsu.scala 84:23]
  wire  stQueue_reset; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_ready; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_valid; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_lb; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_lh; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_lw; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_ld; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_lbu; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_lhu; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_lwu; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_sb; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_sh; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_sw; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_sd; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_lr_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_sc_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoswap_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoadd_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoxor_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoand_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoor_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amomin_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amomax_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amominu_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amomaxu_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_lr_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_sc_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoswap_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoadd_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoxor_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoand_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amoor_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amomin_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amomax_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amominu_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_amomaxu_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_flw; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_fsw; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_fld; // @[Lsu.scala 84:23]
  wire  stQueue_io_enq_bits_fun_fsd; // @[Lsu.scala 84:23]
  wire [63:0] stQueue_io_enq_bits_param_dat_op1; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_ready; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_valid; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_lb; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_lh; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_lw; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_ld; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_lbu; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_lhu; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_lwu; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_sb; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_sh; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_sw; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_sd; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_lr_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_sc_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoswap_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoadd_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoxor_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoand_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoor_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amomin_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amomax_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amominu_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amomaxu_w; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_lr_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_sc_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoswap_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoadd_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoxor_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoand_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amoor_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amomin_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amomax_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amominu_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_amomaxu_d; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_flw; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_fsw; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_fld; // @[Lsu.scala 84:23]
  wire  stQueue_io_deq_bits_fun_fsd; // @[Lsu.scala 84:23]
  wire [63:0] stQueue_io_deq_bits_param_dat_op1; // @[Lsu.scala 84:23]
  wire  stQueue_io_cmm_lsu_is_amo_pending; // @[Lsu.scala 84:23]
  wire  stQueue_io_cmm_lsu_is_store_commit_0; // @[Lsu.scala 84:23]
  wire  stQueue_io_is_empty; // @[Lsu.scala 84:23]
  wire  stQueue_io_overlapReq_valid; // @[Lsu.scala 84:23]
  wire [31:0] stQueue_io_overlapReq_bits_paddr; // @[Lsu.scala 84:23]
  wire  stQueue_io_overlapResp_valid; // @[Lsu.scala 84:23]
  wire  stQueue_io_flush; // @[Lsu.scala 84:23]
  wire  ls_arb_io_in_0_valid; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_lb; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_lh; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_lw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_ld; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_lbu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_lhu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_lwu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_sb; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_sh; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_sw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_sd; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_lr_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_sc_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoswap_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoadd_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoxor_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoand_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoor_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amomin_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amomax_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amominu_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amomaxu_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_lr_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_sc_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoswap_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoadd_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoxor_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoand_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amoor_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amomin_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amomax_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amominu_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_amomaxu_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_flw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_fsw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_fld; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_0_bits_fun_fsd; // @[Lsu.scala 87:22]
  wire [63:0] ls_arb_io_in_0_bits_param_dat_op1; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_ready; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_valid; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_lb; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_lh; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_lw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_ld; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_lbu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_lhu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_lwu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_sb; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_sh; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_sw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_sd; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_lr_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_sc_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoswap_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoadd_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoxor_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoand_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoor_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amomin_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amomax_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amominu_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amomaxu_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_lr_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_sc_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoswap_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoadd_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoxor_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoand_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amoor_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amomin_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amomax_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amominu_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_amomaxu_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_flw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_fsw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_fld; // @[Lsu.scala 87:22]
  wire  ls_arb_io_in_1_bits_fun_fsd; // @[Lsu.scala 87:22]
  wire [63:0] ls_arb_io_in_1_bits_param_dat_op1; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_ready; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_valid; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_lb; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_lh; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_lw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_ld; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_lbu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_lhu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_lwu; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_sb; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_sh; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_sw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_sd; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_lr_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_sc_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoswap_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoadd_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoxor_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoand_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoor_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amomin_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amomax_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amominu_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amomaxu_w; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_lr_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_sc_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoswap_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoadd_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoxor_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoand_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amoor_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amomin_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amomax_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amominu_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_amomaxu_d; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_flw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_fsw; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_fld; // @[Lsu.scala 87:22]
  wire  ls_arb_io_out_bits_fun_fsd; // @[Lsu.scala 87:22]
  wire [63:0] ls_arb_io_out_bits_param_dat_op1; // @[Lsu.scala 87:22]
  wire  system_clock; // @[Lsu.scala 95:22]
  wire  system_reset; // @[Lsu.scala 95:22]
  wire  system_io_enq_ready; // @[Lsu.scala 95:22]
  wire  system_io_enq_valid; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_lb; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_lh; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_lw; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_ld; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_lbu; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_lhu; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_lwu; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_sb; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_sh; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_sw; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_sd; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_lr_w; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_sc_w; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_lr_d; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_sc_d; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_flw; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_fsw; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_fld; // @[Lsu.scala 95:22]
  wire  system_io_enq_bits_fun_fsd; // @[Lsu.scala 95:22]
  wire  system_io_deq_ready; // @[Lsu.scala 95:22]
  wire  system_io_deq_valid; // @[Lsu.scala 95:22]
  wire  system_io_deq_bits_is_load_amo; // @[Lsu.scala 95:22]
  wire  system_io_deq_bits_is_flw; // @[Lsu.scala 95:22]
  wire  system_io_deq_bits_is_fld; // @[Lsu.scala 95:22]
  wire  system_io_is_empty; // @[Lsu.scala 95:22]
  wire  system_io_getPut_ready; // @[Lsu.scala 95:22]
  wire  system_io_getPut_valid; // @[Lsu.scala 95:22]
  wire  system_io_access_ready; // @[Lsu.scala 95:22]
  wire  system_io_access_valid; // @[Lsu.scala 95:22]
  wire [2:0] system_io_access_bits_opcode; // @[Lsu.scala 95:22]
  wire  periph_clock; // @[Lsu.scala 96:22]
  wire  periph_reset; // @[Lsu.scala 96:22]
  wire  periph_io_enq_ready; // @[Lsu.scala 96:22]
  wire  periph_io_enq_valid; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_lb; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_lh; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_lw; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_ld; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_lbu; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_lhu; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_lwu; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_sb; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_sh; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_sw; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_sd; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_lr_w; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_sc_w; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_lr_d; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_sc_d; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_flw; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_fsw; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_fld; // @[Lsu.scala 96:22]
  wire  periph_io_enq_bits_fun_fsd; // @[Lsu.scala 96:22]
  wire  periph_io_deq_ready; // @[Lsu.scala 96:22]
  wire  periph_io_deq_valid; // @[Lsu.scala 96:22]
  wire  periph_io_deq_bits_is_load_amo; // @[Lsu.scala 96:22]
  wire  periph_io_deq_bits_is_flw; // @[Lsu.scala 96:22]
  wire  periph_io_deq_bits_is_fld; // @[Lsu.scala 96:22]
  wire  periph_io_is_empty; // @[Lsu.scala 96:22]
  wire  periph_io_getPut_ready; // @[Lsu.scala 96:22]
  wire  periph_io_getPut_valid; // @[Lsu.scala 96:22]
  wire  periph_io_access_ready; // @[Lsu.scala 96:22]
  wire  periph_io_access_valid; // @[Lsu.scala 96:22]
  wire [2:0] periph_io_access_bits_opcode; // @[Lsu.scala 96:22]
  wire  cache_0_clock; // @[Lsu.scala 97:63]
  wire  cache_0_reset; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_ready; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_valid; // @[Lsu.scala 97:63]
  wire [31:0] cache_0_io_enq_bits_paddr; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_lb; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_lh; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_lw; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_ld; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_lbu; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_lhu; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_lwu; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_sb; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_sh; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_sw; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_sd; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_lr_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_sc_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoswap_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoadd_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoxor_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoand_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoor_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amomin_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amomax_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amominu_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amomaxu_w; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_lr_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_sc_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoswap_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoadd_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoxor_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoand_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amoor_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amomin_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amomax_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amominu_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_amomaxu_d; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_flw; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_fsw; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_fld; // @[Lsu.scala 97:63]
  wire  cache_0_io_enq_bits_fun_fsd; // @[Lsu.scala 97:63]
  wire  cache_0_io_deq_ready; // @[Lsu.scala 97:63]
  wire  cache_0_io_deq_valid; // @[Lsu.scala 97:63]
  wire  cache_0_io_deq_bits_chkIdx; // @[Lsu.scala 97:63]
  wire  cache_0_io_deq_bits_is_load_amo; // @[Lsu.scala 97:63]
  wire  cache_0_io_deq_bits_is_flw; // @[Lsu.scala 97:63]
  wire  cache_0_io_deq_bits_is_fld; // @[Lsu.scala 97:63]
  wire  cache_0_io_is_empty; // @[Lsu.scala 97:63]
  wire  cache_0_io_flush; // @[Lsu.scala 97:63]
  wire  cache_0_io_missUnit_dcache_acquire_ready; // @[Lsu.scala 97:63]
  wire  cache_0_io_missUnit_dcache_grant_valid; // @[Lsu.scala 97:63]
  wire [2:0] cache_0_io_missUnit_dcache_grant_bits_opcode; // @[Lsu.scala 97:63]
  wire [2:0] cache_0_io_missUnit_dcache_grant_bits_size; // @[Lsu.scala 97:63]
  wire  cache_0_io_missUnit_dcache_grant_bits_source; // @[Lsu.scala 97:63]
  wire  cache_0_io_missUnit_dcache_grantAck_ready; // @[Lsu.scala 97:63]
  wire  cache_0_io_probeUnit_dcache_probe_valid; // @[Lsu.scala 97:63]
  wire [31:0] cache_0_io_probeUnit_dcache_probe_bits_address; // @[Lsu.scala 97:63]
  wire  cache_0_io_writeBackUnit_dcache_release_ready; // @[Lsu.scala 97:63]
  wire  cache_0_io_writeBackUnit_dcache_release_valid; // @[Lsu.scala 97:63]
  wire [2:0] cache_0_io_writeBackUnit_dcache_release_bits_opcode; // @[Lsu.scala 97:63]
  wire [2:0] cache_0_io_writeBackUnit_dcache_release_bits_size; // @[Lsu.scala 97:63]
  wire  cache_0_io_writeBackUnit_dcache_grant_valid; // @[Lsu.scala 97:63]
  wire  cache_0_io_writeBackUnit_dcache_grant_bits_source; // @[Lsu.scala 97:63]
  wire  lu_wb_arb_io_in_0_ready; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_0_valid; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_0_bits_is_flw; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_0_bits_is_fld; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_1_ready; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_1_valid; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_1_bits_is_flw; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_1_bits_is_fld; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_2_ready; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_2_valid; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_2_bits_is_flw; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_in_2_bits_is_fld; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_out_ready; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_out_valid; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_out_bits_is_flw; // @[Lsu.scala 103:25]
  wire  lu_wb_arb_io_out_bits_is_fld; // @[Lsu.scala 103:25]
  wire  lu_wb_fifo_clock; // @[Lsu.scala 110:26]
  wire  lu_wb_fifo_reset; // @[Lsu.scala 110:26]
  wire  lu_wb_fifo_io_enq_ready; // @[Lsu.scala 110:26]
  wire  lu_wb_fifo_io_enq_valid; // @[Lsu.scala 110:26]
  wire  lu_wb_fifo_io_deq_ready; // @[Lsu.scala 110:26]
  wire  lu_wb_fifo_io_deq_valid; // @[Lsu.scala 110:26]
  wire  flu_wb_fifo_clock; // @[Lsu.scala 112:27]
  wire  flu_wb_fifo_reset; // @[Lsu.scala 112:27]
  wire  flu_wb_fifo_io_enq_ready; // @[Lsu.scala 112:27]
  wire  flu_wb_fifo_io_enq_valid; // @[Lsu.scala 112:27]
  wire  flu_wb_fifo_io_deq_ready; // @[Lsu.scala 112:27]
  wire  flu_wb_fifo_io_deq_valid; // @[Lsu.scala 112:27]
  wire  su_wb_fifo_clock; // @[Lsu.scala 118:26]
  wire  su_wb_fifo_reset; // @[Lsu.scala 118:26]
  wire  su_wb_fifo_io_enq_ready; // @[Lsu.scala 118:26]
  wire  su_wb_fifo_io_enq_valid; // @[Lsu.scala 118:26]
  wire  su_wb_fifo_io_deq_ready; // @[Lsu.scala 118:26]
  wire  su_wb_fifo_io_deq_valid; // @[Lsu.scala 118:26]
  wire  fe_wb_fifo_clock; // @[Lsu.scala 119:26]
  wire  fe_wb_fifo_reset; // @[Lsu.scala 119:26]
  wire  fe_wb_fifo_io_enq_ready; // @[Lsu.scala 119:26]
  wire  fe_wb_fifo_io_enq_valid; // @[Lsu.scala 119:26]
  wire  fe_wb_fifo_io_deq_ready; // @[Lsu.scala 119:26]
  wire  fe_wb_fifo_io_deq_valid; // @[Lsu.scala 119:26]
  wire  rtn_arb_io_in_0_ready; // @[Lsu.scala 125:23]
  wire  rtn_arb_io_in_0_valid; // @[Lsu.scala 125:23]
  wire  rtn_arb_io_in_1_ready; // @[Lsu.scala 125:23]
  wire  rtn_arb_io_in_1_valid; // @[Lsu.scala 125:23]
  wire  rtn_arb_io_in_2_ready; // @[Lsu.scala 125:23]
  wire  rtn_arb_io_out_ready; // @[Lsu.scala 125:23]
  wire  acquireArb_io_in_0_ready; // @[Lsu.scala 277:29]
  wire  acquireArb_io_out_ready; // @[Lsu.scala 277:29]
  wire  grantAckArb_io_in_0_ready; // @[Lsu.scala 278:29]
  wire  grantAckArb_io_out_ready; // @[Lsu.scala 278:29]
  wire  releaseArb_io_in_0_ready; // @[Lsu.scala 279:29]
  wire  releaseArb_io_out_ready; // @[Lsu.scala 279:29]
  reg  trans_kill; // @[Lsu.scala 73:27]
  wire  _addrTransIO_valid_T = io_mmu_lsu_bits_is_access_fault | io_mmu_lsu_bits_is_paging_fault; // @[MMU.scala 77:34]
  wire  _addrTransIO_valid_T_4 = io_lsu_iss_exe_bits_fun_lh | io_lsu_iss_exe_bits_fun_lhu | io_lsu_iss_exe_bits_fun_sh; // @[riscv_isa.scala 154:26]
  wire  _addrTransIO_valid_T_21 = io_lsu_iss_exe_bits_fun_lw | io_lsu_iss_exe_bits_fun_lwu | io_lsu_iss_exe_bits_fun_sw
     | io_lsu_iss_exe_bits_fun_amoswap_w | io_lsu_iss_exe_bits_fun_amoadd_w | io_lsu_iss_exe_bits_fun_amoxor_w |
    io_lsu_iss_exe_bits_fun_amoand_w | io_lsu_iss_exe_bits_fun_amoor_w | io_lsu_iss_exe_bits_fun_amomin_w |
    io_lsu_iss_exe_bits_fun_amomax_w | io_lsu_iss_exe_bits_fun_amominu_w | io_lsu_iss_exe_bits_fun_amomaxu_w |
    io_lsu_iss_exe_bits_fun_flw | io_lsu_iss_exe_bits_fun_fsw | io_lsu_iss_exe_bits_fun_lr_w |
    io_lsu_iss_exe_bits_fun_sc_w; // @[riscv_isa.scala 155:151]
  wire  _addrTransIO_valid_T_23 = io_lsu_iss_exe_bits_param_dat_op1[1:0] != 2'h0; // @[riscv_isa.scala 899:42]
  wire  _addrTransIO_valid_T_37 = io_lsu_iss_exe_bits_fun_ld | io_lsu_iss_exe_bits_fun_lr_d |
    io_lsu_iss_exe_bits_fun_fld | io_lsu_iss_exe_bits_fun_sd | io_lsu_iss_exe_bits_fun_sc_d |
    io_lsu_iss_exe_bits_fun_fsd | io_lsu_iss_exe_bits_fun_amoswap_d | io_lsu_iss_exe_bits_fun_amoadd_d |
    io_lsu_iss_exe_bits_fun_amoxor_d | io_lsu_iss_exe_bits_fun_amoand_d | io_lsu_iss_exe_bits_fun_amoor_d |
    io_lsu_iss_exe_bits_fun_amomin_d | io_lsu_iss_exe_bits_fun_amomax_d | io_lsu_iss_exe_bits_fun_amominu_d |
    io_lsu_iss_exe_bits_fun_amomaxu_d; // @[riscv_isa.scala 156:140]
  wire  _addrTransIO_valid_T_39 = io_lsu_iss_exe_bits_param_dat_op1[2:0] != 3'h0; // @[riscv_isa.scala 900:42]
  wire  _addrTransIO_valid_T_44 = _addrTransIO_valid_T_4 & io_lsu_iss_exe_bits_param_dat_op1[0] |
    _addrTransIO_valid_T_21 & _addrTransIO_valid_T_23 | _addrTransIO_valid_T_37 & _addrTransIO_valid_T_39; // @[Mux.scala 27:73]
  wire  _addrTransIO_valid_T_48 = io_lsu_iss_exe_bits_fun_fence | io_lsu_iss_exe_bits_fun_fence_i |
    io_lsu_iss_exe_bits_fun_sfence_vma; // @[riscv_isa.scala 150:34]
  wire  addrTransIO_valid = io_mmu_lsu_valid & ~_addrTransIO_valid_T & ~_addrTransIO_valid_T_44 & ~(trans_kill |
    _addrTransIO_valid_T_48); // @[Lsu.scala 136:104]
  wire  _T_32 = io_lsu_iss_exe_bits_fun_sc_d | io_lsu_iss_exe_bits_fun_sc_w; // @[riscv_isa.scala 140:20]
  wire  _T_33 = io_lsu_iss_exe_bits_fun_amoswap_w | io_lsu_iss_exe_bits_fun_amoadd_w | io_lsu_iss_exe_bits_fun_amoxor_w
     | io_lsu_iss_exe_bits_fun_amoand_w | io_lsu_iss_exe_bits_fun_amoor_w | io_lsu_iss_exe_bits_fun_amomin_w |
    io_lsu_iss_exe_bits_fun_amomax_w | io_lsu_iss_exe_bits_fun_amominu_w | io_lsu_iss_exe_bits_fun_amomaxu_w |
    io_lsu_iss_exe_bits_fun_amoswap_d | io_lsu_iss_exe_bits_fun_amoadd_d | io_lsu_iss_exe_bits_fun_amoxor_d |
    io_lsu_iss_exe_bits_fun_amoand_d | io_lsu_iss_exe_bits_fun_amoor_d | io_lsu_iss_exe_bits_fun_amomin_d |
    io_lsu_iss_exe_bits_fun_amomax_d | io_lsu_iss_exe_bits_fun_amominu_d | io_lsu_iss_exe_bits_fun_amomaxu_d | _T_32; // @[riscv_isa.scala 148:205]
  wire  opAmIO_ready = stQueue_io_enq_ready; // @[Lsu.scala 463:16 81:20]
  wire  _T_14 = io_lsu_iss_exe_bits_fun_sb | io_lsu_iss_exe_bits_fun_sh | io_lsu_iss_exe_bits_fun_sw |
    io_lsu_iss_exe_bits_fun_sd | io_lsu_iss_exe_bits_fun_fsw | io_lsu_iss_exe_bits_fun_fsd; // @[riscv_isa.scala 144:40]
  wire  opStIO_ready = su_wb_fifo_io_enq_ready & stQueue_io_enq_ready; // @[Lsu.scala 462:43]
  wire  _T_8 = io_lsu_iss_exe_bits_fun_lr_d | io_lsu_iss_exe_bits_fun_lr_w; // @[riscv_isa.scala 141:20]
  wire  _T_9 = io_lsu_iss_exe_bits_fun_lb | io_lsu_iss_exe_bits_fun_lh | io_lsu_iss_exe_bits_fun_lw |
    io_lsu_iss_exe_bits_fun_ld | io_lsu_iss_exe_bits_fun_lbu | io_lsu_iss_exe_bits_fun_lhu | io_lsu_iss_exe_bits_fun_lwu
     | io_lsu_iss_exe_bits_fun_flw | io_lsu_iss_exe_bits_fun_fld | _T_8; // @[riscv_isa.scala 143:65]
  wire  opLdIO_valid = _T_9 & addrTransIO_valid; // @[Lsu.scala 162:38 163:23 167:18]
  wire [63:0] opLdIO_bits_param_dat_op1 = _T_9 ? io_mmu_lsu_bits_paddr : 64'h0; // @[Lsu.scala 162:38 164:23 168:18]
  wire  opStIO_valid = _T_14 & addrTransIO_valid; // @[Lsu.scala 171:38 172:23 176:18]
  wire  opStIO_bits_fun_lb = _T_14 & io_lsu_iss_exe_bits_fun_lb; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_lh = _T_14 & io_lsu_iss_exe_bits_fun_lh; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_lw = _T_14 & io_lsu_iss_exe_bits_fun_lw; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_ld = _T_14 & io_lsu_iss_exe_bits_fun_ld; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_lbu = _T_14 & io_lsu_iss_exe_bits_fun_lbu; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_lhu = _T_14 & io_lsu_iss_exe_bits_fun_lhu; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_lwu = _T_14 & io_lsu_iss_exe_bits_fun_lwu; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_sb = _T_14 & io_lsu_iss_exe_bits_fun_sb; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_sh = _T_14 & io_lsu_iss_exe_bits_fun_sh; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_sw = _T_14 & io_lsu_iss_exe_bits_fun_sw; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_sd = _T_14 & io_lsu_iss_exe_bits_fun_sd; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_lr_w = _T_14 & io_lsu_iss_exe_bits_fun_lr_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_sc_w = _T_14 & io_lsu_iss_exe_bits_fun_sc_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoswap_w = _T_14 & io_lsu_iss_exe_bits_fun_amoswap_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoadd_w = _T_14 & io_lsu_iss_exe_bits_fun_amoadd_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoxor_w = _T_14 & io_lsu_iss_exe_bits_fun_amoxor_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoand_w = _T_14 & io_lsu_iss_exe_bits_fun_amoand_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoor_w = _T_14 & io_lsu_iss_exe_bits_fun_amoor_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amomin_w = _T_14 & io_lsu_iss_exe_bits_fun_amomin_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amomax_w = _T_14 & io_lsu_iss_exe_bits_fun_amomax_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amominu_w = _T_14 & io_lsu_iss_exe_bits_fun_amominu_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amomaxu_w = _T_14 & io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_lr_d = _T_14 & io_lsu_iss_exe_bits_fun_lr_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_sc_d = _T_14 & io_lsu_iss_exe_bits_fun_sc_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoswap_d = _T_14 & io_lsu_iss_exe_bits_fun_amoswap_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoadd_d = _T_14 & io_lsu_iss_exe_bits_fun_amoadd_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoxor_d = _T_14 & io_lsu_iss_exe_bits_fun_amoxor_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoand_d = _T_14 & io_lsu_iss_exe_bits_fun_amoand_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amoor_d = _T_14 & io_lsu_iss_exe_bits_fun_amoor_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amomin_d = _T_14 & io_lsu_iss_exe_bits_fun_amomin_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amomax_d = _T_14 & io_lsu_iss_exe_bits_fun_amomax_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amominu_d = _T_14 & io_lsu_iss_exe_bits_fun_amominu_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_amomaxu_d = _T_14 & io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_flw = _T_14 & io_lsu_iss_exe_bits_fun_flw; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_fsw = _T_14 & io_lsu_iss_exe_bits_fun_fsw; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_fld = _T_14 & io_lsu_iss_exe_bits_fun_fld; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opStIO_bits_fun_fsd = _T_14 & io_lsu_iss_exe_bits_fun_fsd; // @[Lsu.scala 171:38 173:23 177:18]
  wire [63:0] opStIO_bits_param_dat_op1 = _T_14 ? io_mmu_lsu_bits_paddr : 64'h0; // @[Lsu.scala 171:38 173:23 177:18]
  wire  opAmIO_valid = _T_33 & addrTransIO_valid; // @[Lsu.scala 180:39 181:23 185:18]
  wire  opAmIO_bits_fun_lb = _T_33 & io_lsu_iss_exe_bits_fun_lb; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_lh = _T_33 & io_lsu_iss_exe_bits_fun_lh; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_lw = _T_33 & io_lsu_iss_exe_bits_fun_lw; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_ld = _T_33 & io_lsu_iss_exe_bits_fun_ld; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_lbu = _T_33 & io_lsu_iss_exe_bits_fun_lbu; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_lhu = _T_33 & io_lsu_iss_exe_bits_fun_lhu; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_lwu = _T_33 & io_lsu_iss_exe_bits_fun_lwu; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_sb = _T_33 & io_lsu_iss_exe_bits_fun_sb; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_sh = _T_33 & io_lsu_iss_exe_bits_fun_sh; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_sw = _T_33 & io_lsu_iss_exe_bits_fun_sw; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_sd = _T_33 & io_lsu_iss_exe_bits_fun_sd; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_lr_w = _T_33 & io_lsu_iss_exe_bits_fun_lr_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_sc_w = _T_33 & io_lsu_iss_exe_bits_fun_sc_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoswap_w = _T_33 & io_lsu_iss_exe_bits_fun_amoswap_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoadd_w = _T_33 & io_lsu_iss_exe_bits_fun_amoadd_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoxor_w = _T_33 & io_lsu_iss_exe_bits_fun_amoxor_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoand_w = _T_33 & io_lsu_iss_exe_bits_fun_amoand_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoor_w = _T_33 & io_lsu_iss_exe_bits_fun_amoor_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amomin_w = _T_33 & io_lsu_iss_exe_bits_fun_amomin_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amomax_w = _T_33 & io_lsu_iss_exe_bits_fun_amomax_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amominu_w = _T_33 & io_lsu_iss_exe_bits_fun_amominu_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amomaxu_w = _T_33 & io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_lr_d = _T_33 & io_lsu_iss_exe_bits_fun_lr_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_sc_d = _T_33 & io_lsu_iss_exe_bits_fun_sc_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoswap_d = _T_33 & io_lsu_iss_exe_bits_fun_amoswap_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoadd_d = _T_33 & io_lsu_iss_exe_bits_fun_amoadd_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoxor_d = _T_33 & io_lsu_iss_exe_bits_fun_amoxor_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoand_d = _T_33 & io_lsu_iss_exe_bits_fun_amoand_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amoor_d = _T_33 & io_lsu_iss_exe_bits_fun_amoor_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amomin_d = _T_33 & io_lsu_iss_exe_bits_fun_amomin_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amomax_d = _T_33 & io_lsu_iss_exe_bits_fun_amomax_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amominu_d = _T_33 & io_lsu_iss_exe_bits_fun_amominu_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_amomaxu_d = _T_33 & io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_flw = _T_33 & io_lsu_iss_exe_bits_fun_flw; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_fsw = _T_33 & io_lsu_iss_exe_bits_fun_fsw; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_fld = _T_33 & io_lsu_iss_exe_bits_fun_fld; // @[Lsu.scala 180:39 182:23 186:18]
  wire  opAmIO_bits_fun_fsd = _T_33 & io_lsu_iss_exe_bits_fun_fsd; // @[Lsu.scala 180:39 182:23 186:18]
  wire [63:0] opAmIO_bits_param_dat_op1 = _T_33 ? io_mmu_lsu_bits_paddr : 64'h0; // @[Lsu.scala 180:39 182:23 186:18]
  wire  _stQueue_io_enq_valid_T = opStIO_ready & opStIO_valid; // @[Decoupled.scala 52:35]
  wire  _stQueue_io_enq_valid_T_1 = opAmIO_ready & opAmIO_valid; // @[Decoupled.scala 52:35]
  wire [63:0] _stQueue_io_enq_bits_T_8 = _stQueue_io_enq_valid_T ? opStIO_bits_param_dat_op1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _stQueue_io_enq_bits_T_9 = _stQueue_io_enq_valid_T_1 ? opAmIO_bits_param_dat_op1 : 64'h0; // @[Mux.scala 27:73]
  wire [3:0] psel = ls_arb_io_out_bits_param_dat_op1[31:28]; // @[Lsu.scala 222:46]
  wire [1:0] _sel_T_2 = psel[2] ? 2'h1 : 2'h2; // @[Lsu.scala 223:35]
  wire [1:0] sel = psel[3] ? 2'h0 : _sel_T_2; // @[Lsu.scala 223:16]
  wire  regionPeriphIO_ready = periph_io_enq_ready; // @[Lsu.scala 398:24 91:28]
  wire  _GEN_183 = sel == 2'h2 & regionPeriphIO_ready; // @[Lsu.scala 226:23 228:23 231:26]
  wire  regionSystemIO_ready = system_io_enq_ready; // @[Lsu.scala 387:24 90:28]
  wire  _GEN_229 = sel == 2'h1 ? regionSystemIO_ready : _GEN_183; // @[Lsu.scala 237:23 240:26]
  wire [63:0] regionDCacheIO_bits_param_dat_op1 = sel == 2'h0 ? ls_arb_io_out_bits_param_dat_op1 : 64'h0; // @[Lsu.scala 246:23 248:26 252:26]
  wire  cacheBankIO_0_ready = cache_0_io_enq_ready; // @[Lsu.scala 93:25 381:27]
  reg  is_chnc_busy_0; // @[Lsu.scala 325:33]
  wire  _is_release_done_T = cache_0_io_writeBackUnit_dcache_release_ready &
    cache_0_io_writeBackUnit_dcache_release_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _is_release_done_beats1_decode_T_1 = 11'hf << cache_0_io_writeBackUnit_dcache_release_bits_size; // @[package.scala 234:77]
  wire [3:0] _is_release_done_beats1_decode_T_3 = ~_is_release_done_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  is_release_done_beats1_decode = _is_release_done_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  is_release_done_beats1_opdata = cache_0_io_writeBackUnit_dcache_release_bits_opcode[0]; // @[Edges.scala 101:36]
  wire  is_release_done_beats1 = is_release_done_beats1_opdata & is_release_done_beats1_decode; // @[Edges.scala 220:14]
  reg  is_release_done_counter; // @[Edges.scala 228:27]
  wire  is_release_done_counter1 = is_release_done_counter - 1'h1; // @[Edges.scala 229:28]
  wire  is_release_done_first = ~is_release_done_counter; // @[Edges.scala 230:25]
  wire  is_release_done_last = is_release_done_counter | ~is_release_done_beats1; // @[Edges.scala 231:37]
  wire  is_release_done_0 = is_release_done_last & _is_release_done_T; // @[Edges.scala 232:22]
  wire  _GEN_366 = is_chnc_busy_0 ? io_writeBackUnit_dcache_release_ready : releaseArb_io_in_0_ready; // @[Lsu.scala 332:29 339:{47,85}]
  wire  _T_47 = ~reset; // @[Lsu.scala 342:13]
  wire  _is_empty_WIRE_0 = cache_0_io_is_empty; // @[Lsu.scala 537:{12,12}]
  wire  _is_empty_T_2 = stQueue_io_is_empty & _is_empty_WIRE_0; // @[Lsu.scala 536:25]
  wire  _is_empty_T_3 = _is_empty_T_2 & system_io_is_empty; // @[Lsu.scala 537:79]
  wire  _is_empty_T_4 = _is_empty_T_3 & periph_io_is_empty; // @[Lsu.scala 538:24]
  wire  _is_empty_T_5 = ~su_wb_fifo_io_deq_valid; // @[Lsu.scala 540:5]
  wire  _is_empty_T_6 = _is_empty_T_4 & _is_empty_T_5; // @[Lsu.scala 539:24]
  wire  _is_empty_T_7 = ~lu_wb_fifo_io_deq_valid; // @[Lsu.scala 541:5]
  wire  is_empty = _is_empty_T_6 & _is_empty_T_7; // @[Lsu.scala 540:30]
  wire  _GEN_377 = is_empty ? 1'h0 : trans_kill; // @[Lsu.scala 412:{25,38} 73:27]
  wire  _GEN_378 = io_flush | _GEN_377; // @[Lsu.scala 411:{20,33}]
  wire  _T_49 = cache_0_io_deq_ready & cache_0_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _T_50 = lu_wb_arb_io_in_0_ready & lu_wb_arb_io_in_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_55 = system_io_deq_ready & system_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _T_56 = lu_wb_arb_io_in_1_ready & lu_wb_arb_io_in_1_valid; // @[Decoupled.scala 52:35]
  wire  _T_61 = periph_io_deq_ready & periph_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _T_62 = lu_wb_arb_io_in_2_ready & lu_wb_arb_io_in_2_valid; // @[Decoupled.scala 52:35]
  wire  _lu_wb_fifo_io_enq_valid_T = lu_wb_arb_io_out_bits_is_flw | lu_wb_arb_io_out_bits_is_fld; // @[Dcache.scala 88:23]
  wire  _lu_wb_fifo_io_enq_valid_T_1 = ~_lu_wb_fifo_io_enq_valid_T; // @[Dcache.scala 87:16]
  wire  _lu_wb_fifo_io_enq_valid_T_3 = ~trans_kill; // @[Lsu.scala 437:87]
  Store_queue stQueue ( // @[Lsu.scala 84:23]
    .clock(stQueue_clock),
    .reset(stQueue_reset),
    .io_enq_ready(stQueue_io_enq_ready),
    .io_enq_valid(stQueue_io_enq_valid),
    .io_enq_bits_fun_lb(stQueue_io_enq_bits_fun_lb),
    .io_enq_bits_fun_lh(stQueue_io_enq_bits_fun_lh),
    .io_enq_bits_fun_lw(stQueue_io_enq_bits_fun_lw),
    .io_enq_bits_fun_ld(stQueue_io_enq_bits_fun_ld),
    .io_enq_bits_fun_lbu(stQueue_io_enq_bits_fun_lbu),
    .io_enq_bits_fun_lhu(stQueue_io_enq_bits_fun_lhu),
    .io_enq_bits_fun_lwu(stQueue_io_enq_bits_fun_lwu),
    .io_enq_bits_fun_sb(stQueue_io_enq_bits_fun_sb),
    .io_enq_bits_fun_sh(stQueue_io_enq_bits_fun_sh),
    .io_enq_bits_fun_sw(stQueue_io_enq_bits_fun_sw),
    .io_enq_bits_fun_sd(stQueue_io_enq_bits_fun_sd),
    .io_enq_bits_fun_lr_w(stQueue_io_enq_bits_fun_lr_w),
    .io_enq_bits_fun_sc_w(stQueue_io_enq_bits_fun_sc_w),
    .io_enq_bits_fun_amoswap_w(stQueue_io_enq_bits_fun_amoswap_w),
    .io_enq_bits_fun_amoadd_w(stQueue_io_enq_bits_fun_amoadd_w),
    .io_enq_bits_fun_amoxor_w(stQueue_io_enq_bits_fun_amoxor_w),
    .io_enq_bits_fun_amoand_w(stQueue_io_enq_bits_fun_amoand_w),
    .io_enq_bits_fun_amoor_w(stQueue_io_enq_bits_fun_amoor_w),
    .io_enq_bits_fun_amomin_w(stQueue_io_enq_bits_fun_amomin_w),
    .io_enq_bits_fun_amomax_w(stQueue_io_enq_bits_fun_amomax_w),
    .io_enq_bits_fun_amominu_w(stQueue_io_enq_bits_fun_amominu_w),
    .io_enq_bits_fun_amomaxu_w(stQueue_io_enq_bits_fun_amomaxu_w),
    .io_enq_bits_fun_lr_d(stQueue_io_enq_bits_fun_lr_d),
    .io_enq_bits_fun_sc_d(stQueue_io_enq_bits_fun_sc_d),
    .io_enq_bits_fun_amoswap_d(stQueue_io_enq_bits_fun_amoswap_d),
    .io_enq_bits_fun_amoadd_d(stQueue_io_enq_bits_fun_amoadd_d),
    .io_enq_bits_fun_amoxor_d(stQueue_io_enq_bits_fun_amoxor_d),
    .io_enq_bits_fun_amoand_d(stQueue_io_enq_bits_fun_amoand_d),
    .io_enq_bits_fun_amoor_d(stQueue_io_enq_bits_fun_amoor_d),
    .io_enq_bits_fun_amomin_d(stQueue_io_enq_bits_fun_amomin_d),
    .io_enq_bits_fun_amomax_d(stQueue_io_enq_bits_fun_amomax_d),
    .io_enq_bits_fun_amominu_d(stQueue_io_enq_bits_fun_amominu_d),
    .io_enq_bits_fun_amomaxu_d(stQueue_io_enq_bits_fun_amomaxu_d),
    .io_enq_bits_fun_flw(stQueue_io_enq_bits_fun_flw),
    .io_enq_bits_fun_fsw(stQueue_io_enq_bits_fun_fsw),
    .io_enq_bits_fun_fld(stQueue_io_enq_bits_fun_fld),
    .io_enq_bits_fun_fsd(stQueue_io_enq_bits_fun_fsd),
    .io_enq_bits_param_dat_op1(stQueue_io_enq_bits_param_dat_op1),
    .io_deq_ready(stQueue_io_deq_ready),
    .io_deq_valid(stQueue_io_deq_valid),
    .io_deq_bits_fun_lb(stQueue_io_deq_bits_fun_lb),
    .io_deq_bits_fun_lh(stQueue_io_deq_bits_fun_lh),
    .io_deq_bits_fun_lw(stQueue_io_deq_bits_fun_lw),
    .io_deq_bits_fun_ld(stQueue_io_deq_bits_fun_ld),
    .io_deq_bits_fun_lbu(stQueue_io_deq_bits_fun_lbu),
    .io_deq_bits_fun_lhu(stQueue_io_deq_bits_fun_lhu),
    .io_deq_bits_fun_lwu(stQueue_io_deq_bits_fun_lwu),
    .io_deq_bits_fun_sb(stQueue_io_deq_bits_fun_sb),
    .io_deq_bits_fun_sh(stQueue_io_deq_bits_fun_sh),
    .io_deq_bits_fun_sw(stQueue_io_deq_bits_fun_sw),
    .io_deq_bits_fun_sd(stQueue_io_deq_bits_fun_sd),
    .io_deq_bits_fun_lr_w(stQueue_io_deq_bits_fun_lr_w),
    .io_deq_bits_fun_sc_w(stQueue_io_deq_bits_fun_sc_w),
    .io_deq_bits_fun_amoswap_w(stQueue_io_deq_bits_fun_amoswap_w),
    .io_deq_bits_fun_amoadd_w(stQueue_io_deq_bits_fun_amoadd_w),
    .io_deq_bits_fun_amoxor_w(stQueue_io_deq_bits_fun_amoxor_w),
    .io_deq_bits_fun_amoand_w(stQueue_io_deq_bits_fun_amoand_w),
    .io_deq_bits_fun_amoor_w(stQueue_io_deq_bits_fun_amoor_w),
    .io_deq_bits_fun_amomin_w(stQueue_io_deq_bits_fun_amomin_w),
    .io_deq_bits_fun_amomax_w(stQueue_io_deq_bits_fun_amomax_w),
    .io_deq_bits_fun_amominu_w(stQueue_io_deq_bits_fun_amominu_w),
    .io_deq_bits_fun_amomaxu_w(stQueue_io_deq_bits_fun_amomaxu_w),
    .io_deq_bits_fun_lr_d(stQueue_io_deq_bits_fun_lr_d),
    .io_deq_bits_fun_sc_d(stQueue_io_deq_bits_fun_sc_d),
    .io_deq_bits_fun_amoswap_d(stQueue_io_deq_bits_fun_amoswap_d),
    .io_deq_bits_fun_amoadd_d(stQueue_io_deq_bits_fun_amoadd_d),
    .io_deq_bits_fun_amoxor_d(stQueue_io_deq_bits_fun_amoxor_d),
    .io_deq_bits_fun_amoand_d(stQueue_io_deq_bits_fun_amoand_d),
    .io_deq_bits_fun_amoor_d(stQueue_io_deq_bits_fun_amoor_d),
    .io_deq_bits_fun_amomin_d(stQueue_io_deq_bits_fun_amomin_d),
    .io_deq_bits_fun_amomax_d(stQueue_io_deq_bits_fun_amomax_d),
    .io_deq_bits_fun_amominu_d(stQueue_io_deq_bits_fun_amominu_d),
    .io_deq_bits_fun_amomaxu_d(stQueue_io_deq_bits_fun_amomaxu_d),
    .io_deq_bits_fun_flw(stQueue_io_deq_bits_fun_flw),
    .io_deq_bits_fun_fsw(stQueue_io_deq_bits_fun_fsw),
    .io_deq_bits_fun_fld(stQueue_io_deq_bits_fun_fld),
    .io_deq_bits_fun_fsd(stQueue_io_deq_bits_fun_fsd),
    .io_deq_bits_param_dat_op1(stQueue_io_deq_bits_param_dat_op1),
    .io_cmm_lsu_is_amo_pending(stQueue_io_cmm_lsu_is_amo_pending),
    .io_cmm_lsu_is_store_commit_0(stQueue_io_cmm_lsu_is_store_commit_0),
    .io_is_empty(stQueue_io_is_empty),
    .io_overlapReq_valid(stQueue_io_overlapReq_valid),
    .io_overlapReq_bits_paddr(stQueue_io_overlapReq_bits_paddr),
    .io_overlapResp_valid(stQueue_io_overlapResp_valid),
    .io_flush(stQueue_io_flush)
  );
  Arbiter ls_arb ( // @[Lsu.scala 87:22]
    .io_in_0_valid(ls_arb_io_in_0_valid),
    .io_in_0_bits_fun_lb(ls_arb_io_in_0_bits_fun_lb),
    .io_in_0_bits_fun_lh(ls_arb_io_in_0_bits_fun_lh),
    .io_in_0_bits_fun_lw(ls_arb_io_in_0_bits_fun_lw),
    .io_in_0_bits_fun_ld(ls_arb_io_in_0_bits_fun_ld),
    .io_in_0_bits_fun_lbu(ls_arb_io_in_0_bits_fun_lbu),
    .io_in_0_bits_fun_lhu(ls_arb_io_in_0_bits_fun_lhu),
    .io_in_0_bits_fun_lwu(ls_arb_io_in_0_bits_fun_lwu),
    .io_in_0_bits_fun_sb(ls_arb_io_in_0_bits_fun_sb),
    .io_in_0_bits_fun_sh(ls_arb_io_in_0_bits_fun_sh),
    .io_in_0_bits_fun_sw(ls_arb_io_in_0_bits_fun_sw),
    .io_in_0_bits_fun_sd(ls_arb_io_in_0_bits_fun_sd),
    .io_in_0_bits_fun_lr_w(ls_arb_io_in_0_bits_fun_lr_w),
    .io_in_0_bits_fun_sc_w(ls_arb_io_in_0_bits_fun_sc_w),
    .io_in_0_bits_fun_amoswap_w(ls_arb_io_in_0_bits_fun_amoswap_w),
    .io_in_0_bits_fun_amoadd_w(ls_arb_io_in_0_bits_fun_amoadd_w),
    .io_in_0_bits_fun_amoxor_w(ls_arb_io_in_0_bits_fun_amoxor_w),
    .io_in_0_bits_fun_amoand_w(ls_arb_io_in_0_bits_fun_amoand_w),
    .io_in_0_bits_fun_amoor_w(ls_arb_io_in_0_bits_fun_amoor_w),
    .io_in_0_bits_fun_amomin_w(ls_arb_io_in_0_bits_fun_amomin_w),
    .io_in_0_bits_fun_amomax_w(ls_arb_io_in_0_bits_fun_amomax_w),
    .io_in_0_bits_fun_amominu_w(ls_arb_io_in_0_bits_fun_amominu_w),
    .io_in_0_bits_fun_amomaxu_w(ls_arb_io_in_0_bits_fun_amomaxu_w),
    .io_in_0_bits_fun_lr_d(ls_arb_io_in_0_bits_fun_lr_d),
    .io_in_0_bits_fun_sc_d(ls_arb_io_in_0_bits_fun_sc_d),
    .io_in_0_bits_fun_amoswap_d(ls_arb_io_in_0_bits_fun_amoswap_d),
    .io_in_0_bits_fun_amoadd_d(ls_arb_io_in_0_bits_fun_amoadd_d),
    .io_in_0_bits_fun_amoxor_d(ls_arb_io_in_0_bits_fun_amoxor_d),
    .io_in_0_bits_fun_amoand_d(ls_arb_io_in_0_bits_fun_amoand_d),
    .io_in_0_bits_fun_amoor_d(ls_arb_io_in_0_bits_fun_amoor_d),
    .io_in_0_bits_fun_amomin_d(ls_arb_io_in_0_bits_fun_amomin_d),
    .io_in_0_bits_fun_amomax_d(ls_arb_io_in_0_bits_fun_amomax_d),
    .io_in_0_bits_fun_amominu_d(ls_arb_io_in_0_bits_fun_amominu_d),
    .io_in_0_bits_fun_amomaxu_d(ls_arb_io_in_0_bits_fun_amomaxu_d),
    .io_in_0_bits_fun_flw(ls_arb_io_in_0_bits_fun_flw),
    .io_in_0_bits_fun_fsw(ls_arb_io_in_0_bits_fun_fsw),
    .io_in_0_bits_fun_fld(ls_arb_io_in_0_bits_fun_fld),
    .io_in_0_bits_fun_fsd(ls_arb_io_in_0_bits_fun_fsd),
    .io_in_0_bits_param_dat_op1(ls_arb_io_in_0_bits_param_dat_op1),
    .io_in_1_ready(ls_arb_io_in_1_ready),
    .io_in_1_valid(ls_arb_io_in_1_valid),
    .io_in_1_bits_fun_lb(ls_arb_io_in_1_bits_fun_lb),
    .io_in_1_bits_fun_lh(ls_arb_io_in_1_bits_fun_lh),
    .io_in_1_bits_fun_lw(ls_arb_io_in_1_bits_fun_lw),
    .io_in_1_bits_fun_ld(ls_arb_io_in_1_bits_fun_ld),
    .io_in_1_bits_fun_lbu(ls_arb_io_in_1_bits_fun_lbu),
    .io_in_1_bits_fun_lhu(ls_arb_io_in_1_bits_fun_lhu),
    .io_in_1_bits_fun_lwu(ls_arb_io_in_1_bits_fun_lwu),
    .io_in_1_bits_fun_sb(ls_arb_io_in_1_bits_fun_sb),
    .io_in_1_bits_fun_sh(ls_arb_io_in_1_bits_fun_sh),
    .io_in_1_bits_fun_sw(ls_arb_io_in_1_bits_fun_sw),
    .io_in_1_bits_fun_sd(ls_arb_io_in_1_bits_fun_sd),
    .io_in_1_bits_fun_lr_w(ls_arb_io_in_1_bits_fun_lr_w),
    .io_in_1_bits_fun_sc_w(ls_arb_io_in_1_bits_fun_sc_w),
    .io_in_1_bits_fun_amoswap_w(ls_arb_io_in_1_bits_fun_amoswap_w),
    .io_in_1_bits_fun_amoadd_w(ls_arb_io_in_1_bits_fun_amoadd_w),
    .io_in_1_bits_fun_amoxor_w(ls_arb_io_in_1_bits_fun_amoxor_w),
    .io_in_1_bits_fun_amoand_w(ls_arb_io_in_1_bits_fun_amoand_w),
    .io_in_1_bits_fun_amoor_w(ls_arb_io_in_1_bits_fun_amoor_w),
    .io_in_1_bits_fun_amomin_w(ls_arb_io_in_1_bits_fun_amomin_w),
    .io_in_1_bits_fun_amomax_w(ls_arb_io_in_1_bits_fun_amomax_w),
    .io_in_1_bits_fun_amominu_w(ls_arb_io_in_1_bits_fun_amominu_w),
    .io_in_1_bits_fun_amomaxu_w(ls_arb_io_in_1_bits_fun_amomaxu_w),
    .io_in_1_bits_fun_lr_d(ls_arb_io_in_1_bits_fun_lr_d),
    .io_in_1_bits_fun_sc_d(ls_arb_io_in_1_bits_fun_sc_d),
    .io_in_1_bits_fun_amoswap_d(ls_arb_io_in_1_bits_fun_amoswap_d),
    .io_in_1_bits_fun_amoadd_d(ls_arb_io_in_1_bits_fun_amoadd_d),
    .io_in_1_bits_fun_amoxor_d(ls_arb_io_in_1_bits_fun_amoxor_d),
    .io_in_1_bits_fun_amoand_d(ls_arb_io_in_1_bits_fun_amoand_d),
    .io_in_1_bits_fun_amoor_d(ls_arb_io_in_1_bits_fun_amoor_d),
    .io_in_1_bits_fun_amomin_d(ls_arb_io_in_1_bits_fun_amomin_d),
    .io_in_1_bits_fun_amomax_d(ls_arb_io_in_1_bits_fun_amomax_d),
    .io_in_1_bits_fun_amominu_d(ls_arb_io_in_1_bits_fun_amominu_d),
    .io_in_1_bits_fun_amomaxu_d(ls_arb_io_in_1_bits_fun_amomaxu_d),
    .io_in_1_bits_fun_flw(ls_arb_io_in_1_bits_fun_flw),
    .io_in_1_bits_fun_fsw(ls_arb_io_in_1_bits_fun_fsw),
    .io_in_1_bits_fun_fld(ls_arb_io_in_1_bits_fun_fld),
    .io_in_1_bits_fun_fsd(ls_arb_io_in_1_bits_fun_fsd),
    .io_in_1_bits_param_dat_op1(ls_arb_io_in_1_bits_param_dat_op1),
    .io_out_ready(ls_arb_io_out_ready),
    .io_out_valid(ls_arb_io_out_valid),
    .io_out_bits_fun_lb(ls_arb_io_out_bits_fun_lb),
    .io_out_bits_fun_lh(ls_arb_io_out_bits_fun_lh),
    .io_out_bits_fun_lw(ls_arb_io_out_bits_fun_lw),
    .io_out_bits_fun_ld(ls_arb_io_out_bits_fun_ld),
    .io_out_bits_fun_lbu(ls_arb_io_out_bits_fun_lbu),
    .io_out_bits_fun_lhu(ls_arb_io_out_bits_fun_lhu),
    .io_out_bits_fun_lwu(ls_arb_io_out_bits_fun_lwu),
    .io_out_bits_fun_sb(ls_arb_io_out_bits_fun_sb),
    .io_out_bits_fun_sh(ls_arb_io_out_bits_fun_sh),
    .io_out_bits_fun_sw(ls_arb_io_out_bits_fun_sw),
    .io_out_bits_fun_sd(ls_arb_io_out_bits_fun_sd),
    .io_out_bits_fun_lr_w(ls_arb_io_out_bits_fun_lr_w),
    .io_out_bits_fun_sc_w(ls_arb_io_out_bits_fun_sc_w),
    .io_out_bits_fun_amoswap_w(ls_arb_io_out_bits_fun_amoswap_w),
    .io_out_bits_fun_amoadd_w(ls_arb_io_out_bits_fun_amoadd_w),
    .io_out_bits_fun_amoxor_w(ls_arb_io_out_bits_fun_amoxor_w),
    .io_out_bits_fun_amoand_w(ls_arb_io_out_bits_fun_amoand_w),
    .io_out_bits_fun_amoor_w(ls_arb_io_out_bits_fun_amoor_w),
    .io_out_bits_fun_amomin_w(ls_arb_io_out_bits_fun_amomin_w),
    .io_out_bits_fun_amomax_w(ls_arb_io_out_bits_fun_amomax_w),
    .io_out_bits_fun_amominu_w(ls_arb_io_out_bits_fun_amominu_w),
    .io_out_bits_fun_amomaxu_w(ls_arb_io_out_bits_fun_amomaxu_w),
    .io_out_bits_fun_lr_d(ls_arb_io_out_bits_fun_lr_d),
    .io_out_bits_fun_sc_d(ls_arb_io_out_bits_fun_sc_d),
    .io_out_bits_fun_amoswap_d(ls_arb_io_out_bits_fun_amoswap_d),
    .io_out_bits_fun_amoadd_d(ls_arb_io_out_bits_fun_amoadd_d),
    .io_out_bits_fun_amoxor_d(ls_arb_io_out_bits_fun_amoxor_d),
    .io_out_bits_fun_amoand_d(ls_arb_io_out_bits_fun_amoand_d),
    .io_out_bits_fun_amoor_d(ls_arb_io_out_bits_fun_amoor_d),
    .io_out_bits_fun_amomin_d(ls_arb_io_out_bits_fun_amomin_d),
    .io_out_bits_fun_amomax_d(ls_arb_io_out_bits_fun_amomax_d),
    .io_out_bits_fun_amominu_d(ls_arb_io_out_bits_fun_amominu_d),
    .io_out_bits_fun_amomaxu_d(ls_arb_io_out_bits_fun_amomaxu_d),
    .io_out_bits_fun_flw(ls_arb_io_out_bits_fun_flw),
    .io_out_bits_fun_fsw(ls_arb_io_out_bits_fun_fsw),
    .io_out_bits_fun_fld(ls_arb_io_out_bits_fun_fld),
    .io_out_bits_fun_fsd(ls_arb_io_out_bits_fun_fsd),
    .io_out_bits_param_dat_op1(ls_arb_io_out_bits_param_dat_op1)
  );
  IO_Lsu system ( // @[Lsu.scala 95:22]
    .clock(system_clock),
    .reset(system_reset),
    .io_enq_ready(system_io_enq_ready),
    .io_enq_valid(system_io_enq_valid),
    .io_enq_bits_fun_lb(system_io_enq_bits_fun_lb),
    .io_enq_bits_fun_lh(system_io_enq_bits_fun_lh),
    .io_enq_bits_fun_lw(system_io_enq_bits_fun_lw),
    .io_enq_bits_fun_ld(system_io_enq_bits_fun_ld),
    .io_enq_bits_fun_lbu(system_io_enq_bits_fun_lbu),
    .io_enq_bits_fun_lhu(system_io_enq_bits_fun_lhu),
    .io_enq_bits_fun_lwu(system_io_enq_bits_fun_lwu),
    .io_enq_bits_fun_sb(system_io_enq_bits_fun_sb),
    .io_enq_bits_fun_sh(system_io_enq_bits_fun_sh),
    .io_enq_bits_fun_sw(system_io_enq_bits_fun_sw),
    .io_enq_bits_fun_sd(system_io_enq_bits_fun_sd),
    .io_enq_bits_fun_lr_w(system_io_enq_bits_fun_lr_w),
    .io_enq_bits_fun_sc_w(system_io_enq_bits_fun_sc_w),
    .io_enq_bits_fun_lr_d(system_io_enq_bits_fun_lr_d),
    .io_enq_bits_fun_sc_d(system_io_enq_bits_fun_sc_d),
    .io_enq_bits_fun_flw(system_io_enq_bits_fun_flw),
    .io_enq_bits_fun_fsw(system_io_enq_bits_fun_fsw),
    .io_enq_bits_fun_fld(system_io_enq_bits_fun_fld),
    .io_enq_bits_fun_fsd(system_io_enq_bits_fun_fsd),
    .io_deq_ready(system_io_deq_ready),
    .io_deq_valid(system_io_deq_valid),
    .io_deq_bits_is_load_amo(system_io_deq_bits_is_load_amo),
    .io_deq_bits_is_flw(system_io_deq_bits_is_flw),
    .io_deq_bits_is_fld(system_io_deq_bits_is_fld),
    .io_is_empty(system_io_is_empty),
    .io_getPut_ready(system_io_getPut_ready),
    .io_getPut_valid(system_io_getPut_valid),
    .io_access_ready(system_io_access_ready),
    .io_access_valid(system_io_access_valid),
    .io_access_bits_opcode(system_io_access_bits_opcode)
  );
  IO_Lsu periph ( // @[Lsu.scala 96:22]
    .clock(periph_clock),
    .reset(periph_reset),
    .io_enq_ready(periph_io_enq_ready),
    .io_enq_valid(periph_io_enq_valid),
    .io_enq_bits_fun_lb(periph_io_enq_bits_fun_lb),
    .io_enq_bits_fun_lh(periph_io_enq_bits_fun_lh),
    .io_enq_bits_fun_lw(periph_io_enq_bits_fun_lw),
    .io_enq_bits_fun_ld(periph_io_enq_bits_fun_ld),
    .io_enq_bits_fun_lbu(periph_io_enq_bits_fun_lbu),
    .io_enq_bits_fun_lhu(periph_io_enq_bits_fun_lhu),
    .io_enq_bits_fun_lwu(periph_io_enq_bits_fun_lwu),
    .io_enq_bits_fun_sb(periph_io_enq_bits_fun_sb),
    .io_enq_bits_fun_sh(periph_io_enq_bits_fun_sh),
    .io_enq_bits_fun_sw(periph_io_enq_bits_fun_sw),
    .io_enq_bits_fun_sd(periph_io_enq_bits_fun_sd),
    .io_enq_bits_fun_lr_w(periph_io_enq_bits_fun_lr_w),
    .io_enq_bits_fun_sc_w(periph_io_enq_bits_fun_sc_w),
    .io_enq_bits_fun_lr_d(periph_io_enq_bits_fun_lr_d),
    .io_enq_bits_fun_sc_d(periph_io_enq_bits_fun_sc_d),
    .io_enq_bits_fun_flw(periph_io_enq_bits_fun_flw),
    .io_enq_bits_fun_fsw(periph_io_enq_bits_fun_fsw),
    .io_enq_bits_fun_fld(periph_io_enq_bits_fun_fld),
    .io_enq_bits_fun_fsd(periph_io_enq_bits_fun_fsd),
    .io_deq_ready(periph_io_deq_ready),
    .io_deq_valid(periph_io_deq_valid),
    .io_deq_bits_is_load_amo(periph_io_deq_bits_is_load_amo),
    .io_deq_bits_is_flw(periph_io_deq_bits_is_flw),
    .io_deq_bits_is_fld(periph_io_deq_bits_is_fld),
    .io_is_empty(periph_io_is_empty),
    .io_getPut_ready(periph_io_getPut_ready),
    .io_getPut_valid(periph_io_getPut_valid),
    .io_access_ready(periph_io_access_ready),
    .io_access_valid(periph_io_access_valid),
    .io_access_bits_opcode(periph_io_access_bits_opcode)
  );
  Dcache cache_0 ( // @[Lsu.scala 97:63]
    .clock(cache_0_clock),
    .reset(cache_0_reset),
    .io_enq_ready(cache_0_io_enq_ready),
    .io_enq_valid(cache_0_io_enq_valid),
    .io_enq_bits_paddr(cache_0_io_enq_bits_paddr),
    .io_enq_bits_fun_lb(cache_0_io_enq_bits_fun_lb),
    .io_enq_bits_fun_lh(cache_0_io_enq_bits_fun_lh),
    .io_enq_bits_fun_lw(cache_0_io_enq_bits_fun_lw),
    .io_enq_bits_fun_ld(cache_0_io_enq_bits_fun_ld),
    .io_enq_bits_fun_lbu(cache_0_io_enq_bits_fun_lbu),
    .io_enq_bits_fun_lhu(cache_0_io_enq_bits_fun_lhu),
    .io_enq_bits_fun_lwu(cache_0_io_enq_bits_fun_lwu),
    .io_enq_bits_fun_sb(cache_0_io_enq_bits_fun_sb),
    .io_enq_bits_fun_sh(cache_0_io_enq_bits_fun_sh),
    .io_enq_bits_fun_sw(cache_0_io_enq_bits_fun_sw),
    .io_enq_bits_fun_sd(cache_0_io_enq_bits_fun_sd),
    .io_enq_bits_fun_lr_w(cache_0_io_enq_bits_fun_lr_w),
    .io_enq_bits_fun_sc_w(cache_0_io_enq_bits_fun_sc_w),
    .io_enq_bits_fun_amoswap_w(cache_0_io_enq_bits_fun_amoswap_w),
    .io_enq_bits_fun_amoadd_w(cache_0_io_enq_bits_fun_amoadd_w),
    .io_enq_bits_fun_amoxor_w(cache_0_io_enq_bits_fun_amoxor_w),
    .io_enq_bits_fun_amoand_w(cache_0_io_enq_bits_fun_amoand_w),
    .io_enq_bits_fun_amoor_w(cache_0_io_enq_bits_fun_amoor_w),
    .io_enq_bits_fun_amomin_w(cache_0_io_enq_bits_fun_amomin_w),
    .io_enq_bits_fun_amomax_w(cache_0_io_enq_bits_fun_amomax_w),
    .io_enq_bits_fun_amominu_w(cache_0_io_enq_bits_fun_amominu_w),
    .io_enq_bits_fun_amomaxu_w(cache_0_io_enq_bits_fun_amomaxu_w),
    .io_enq_bits_fun_lr_d(cache_0_io_enq_bits_fun_lr_d),
    .io_enq_bits_fun_sc_d(cache_0_io_enq_bits_fun_sc_d),
    .io_enq_bits_fun_amoswap_d(cache_0_io_enq_bits_fun_amoswap_d),
    .io_enq_bits_fun_amoadd_d(cache_0_io_enq_bits_fun_amoadd_d),
    .io_enq_bits_fun_amoxor_d(cache_0_io_enq_bits_fun_amoxor_d),
    .io_enq_bits_fun_amoand_d(cache_0_io_enq_bits_fun_amoand_d),
    .io_enq_bits_fun_amoor_d(cache_0_io_enq_bits_fun_amoor_d),
    .io_enq_bits_fun_amomin_d(cache_0_io_enq_bits_fun_amomin_d),
    .io_enq_bits_fun_amomax_d(cache_0_io_enq_bits_fun_amomax_d),
    .io_enq_bits_fun_amominu_d(cache_0_io_enq_bits_fun_amominu_d),
    .io_enq_bits_fun_amomaxu_d(cache_0_io_enq_bits_fun_amomaxu_d),
    .io_enq_bits_fun_flw(cache_0_io_enq_bits_fun_flw),
    .io_enq_bits_fun_fsw(cache_0_io_enq_bits_fun_fsw),
    .io_enq_bits_fun_fld(cache_0_io_enq_bits_fun_fld),
    .io_enq_bits_fun_fsd(cache_0_io_enq_bits_fun_fsd),
    .io_deq_ready(cache_0_io_deq_ready),
    .io_deq_valid(cache_0_io_deq_valid),
    .io_deq_bits_chkIdx(cache_0_io_deq_bits_chkIdx),
    .io_deq_bits_is_load_amo(cache_0_io_deq_bits_is_load_amo),
    .io_deq_bits_is_flw(cache_0_io_deq_bits_is_flw),
    .io_deq_bits_is_fld(cache_0_io_deq_bits_is_fld),
    .io_is_empty(cache_0_io_is_empty),
    .io_flush(cache_0_io_flush),
    .io_missUnit_dcache_acquire_ready(cache_0_io_missUnit_dcache_acquire_ready),
    .io_missUnit_dcache_grant_valid(cache_0_io_missUnit_dcache_grant_valid),
    .io_missUnit_dcache_grant_bits_opcode(cache_0_io_missUnit_dcache_grant_bits_opcode),
    .io_missUnit_dcache_grant_bits_size(cache_0_io_missUnit_dcache_grant_bits_size),
    .io_missUnit_dcache_grant_bits_source(cache_0_io_missUnit_dcache_grant_bits_source),
    .io_missUnit_dcache_grantAck_ready(cache_0_io_missUnit_dcache_grantAck_ready),
    .io_probeUnit_dcache_probe_valid(cache_0_io_probeUnit_dcache_probe_valid),
    .io_probeUnit_dcache_probe_bits_address(cache_0_io_probeUnit_dcache_probe_bits_address),
    .io_writeBackUnit_dcache_release_ready(cache_0_io_writeBackUnit_dcache_release_ready),
    .io_writeBackUnit_dcache_release_valid(cache_0_io_writeBackUnit_dcache_release_valid),
    .io_writeBackUnit_dcache_release_bits_opcode(cache_0_io_writeBackUnit_dcache_release_bits_opcode),
    .io_writeBackUnit_dcache_release_bits_size(cache_0_io_writeBackUnit_dcache_release_bits_size),
    .io_writeBackUnit_dcache_grant_valid(cache_0_io_writeBackUnit_dcache_grant_valid),
    .io_writeBackUnit_dcache_grant_bits_source(cache_0_io_writeBackUnit_dcache_grant_bits_source)
  );
  Arbiter_3 lu_wb_arb ( // @[Lsu.scala 103:25]
    .io_in_0_ready(lu_wb_arb_io_in_0_ready),
    .io_in_0_valid(lu_wb_arb_io_in_0_valid),
    .io_in_0_bits_is_flw(lu_wb_arb_io_in_0_bits_is_flw),
    .io_in_0_bits_is_fld(lu_wb_arb_io_in_0_bits_is_fld),
    .io_in_1_ready(lu_wb_arb_io_in_1_ready),
    .io_in_1_valid(lu_wb_arb_io_in_1_valid),
    .io_in_1_bits_is_flw(lu_wb_arb_io_in_1_bits_is_flw),
    .io_in_1_bits_is_fld(lu_wb_arb_io_in_1_bits_is_fld),
    .io_in_2_ready(lu_wb_arb_io_in_2_ready),
    .io_in_2_valid(lu_wb_arb_io_in_2_valid),
    .io_in_2_bits_is_flw(lu_wb_arb_io_in_2_bits_is_flw),
    .io_in_2_bits_is_fld(lu_wb_arb_io_in_2_bits_is_fld),
    .io_out_ready(lu_wb_arb_io_out_ready),
    .io_out_valid(lu_wb_arb_io_out_valid),
    .io_out_bits_is_flw(lu_wb_arb_io_out_bits_is_flw),
    .io_out_bits_is_fld(lu_wb_arb_io_out_bits_is_fld)
  );
  Queue_16 lu_wb_fifo ( // @[Lsu.scala 110:26]
    .clock(lu_wb_fifo_clock),
    .reset(lu_wb_fifo_reset),
    .io_enq_ready(lu_wb_fifo_io_enq_ready),
    .io_enq_valid(lu_wb_fifo_io_enq_valid),
    .io_deq_ready(lu_wb_fifo_io_deq_ready),
    .io_deq_valid(lu_wb_fifo_io_deq_valid)
  );
  Queue_17 flu_wb_fifo ( // @[Lsu.scala 112:27]
    .clock(flu_wb_fifo_clock),
    .reset(flu_wb_fifo_reset),
    .io_enq_ready(flu_wb_fifo_io_enq_ready),
    .io_enq_valid(flu_wb_fifo_io_enq_valid),
    .io_deq_ready(flu_wb_fifo_io_deq_ready),
    .io_deq_valid(flu_wb_fifo_io_deq_valid)
  );
  Queue_16 su_wb_fifo ( // @[Lsu.scala 118:26]
    .clock(su_wb_fifo_clock),
    .reset(su_wb_fifo_reset),
    .io_enq_ready(su_wb_fifo_io_enq_ready),
    .io_enq_valid(su_wb_fifo_io_enq_valid),
    .io_deq_ready(su_wb_fifo_io_deq_ready),
    .io_deq_valid(su_wb_fifo_io_deq_valid)
  );
  Queue_16 fe_wb_fifo ( // @[Lsu.scala 119:26]
    .clock(fe_wb_fifo_clock),
    .reset(fe_wb_fifo_reset),
    .io_enq_ready(fe_wb_fifo_io_enq_ready),
    .io_enq_valid(fe_wb_fifo_io_enq_valid),
    .io_deq_ready(fe_wb_fifo_io_deq_ready),
    .io_deq_valid(fe_wb_fifo_io_deq_valid)
  );
  Arbiter_4 rtn_arb ( // @[Lsu.scala 125:23]
    .io_in_0_ready(rtn_arb_io_in_0_ready),
    .io_in_0_valid(rtn_arb_io_in_0_valid),
    .io_in_1_ready(rtn_arb_io_in_1_ready),
    .io_in_1_valid(rtn_arb_io_in_1_valid),
    .io_in_2_ready(rtn_arb_io_in_2_ready),
    .io_out_ready(rtn_arb_io_out_ready)
  );
  Arbiter_5 acquireArb ( // @[Lsu.scala 277:29]
    .io_in_0_ready(acquireArb_io_in_0_ready),
    .io_out_ready(acquireArb_io_out_ready)
  );
  Arbiter_6 grantAckArb ( // @[Lsu.scala 278:29]
    .io_in_0_ready(grantAckArb_io_in_0_ready),
    .io_out_ready(grantAckArb_io_out_ready)
  );
  Arbiter_7 releaseArb ( // @[Lsu.scala 279:29]
    .io_in_0_ready(releaseArb_io_in_0_ready),
    .io_out_ready(releaseArb_io_out_ready)
  );
  assign stQueue_clock = clock;
  assign stQueue_reset = reset;
  assign stQueue_io_enq_valid = _stQueue_io_enq_valid_T | _stQueue_io_enq_valid_T_1; // @[Lsu.scala 194:39]
  assign stQueue_io_enq_bits_fun_lb = _stQueue_io_enq_valid_T & opStIO_bits_fun_lb | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_lb; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_lh = _stQueue_io_enq_valid_T & opStIO_bits_fun_lh | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_lh; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_lw = _stQueue_io_enq_valid_T & opStIO_bits_fun_lw | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_lw; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_ld = _stQueue_io_enq_valid_T & opStIO_bits_fun_ld | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_ld; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_lbu = _stQueue_io_enq_valid_T & opStIO_bits_fun_lbu | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_lbu; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_lhu = _stQueue_io_enq_valid_T & opStIO_bits_fun_lhu | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_lhu; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_lwu = _stQueue_io_enq_valid_T & opStIO_bits_fun_lwu | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_lwu; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_sb = _stQueue_io_enq_valid_T & opStIO_bits_fun_sb | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_sb; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_sh = _stQueue_io_enq_valid_T & opStIO_bits_fun_sh | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_sh; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_sw = _stQueue_io_enq_valid_T & opStIO_bits_fun_sw | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_sw; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_sd = _stQueue_io_enq_valid_T & opStIO_bits_fun_sd | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_sd; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_lr_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_lr_w | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_lr_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_sc_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_sc_w | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_sc_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoswap_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoswap_w |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amoswap_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoadd_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoadd_w |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amoadd_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoxor_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoxor_w |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amoxor_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoand_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoand_w |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amoand_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoor_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoor_w | _stQueue_io_enq_valid_T_1
     & opAmIO_bits_fun_amoor_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amomin_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amomin_w |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amomin_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amomax_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amomax_w |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amomax_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amominu_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amominu_w |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amominu_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amomaxu_w = _stQueue_io_enq_valid_T & opStIO_bits_fun_amomaxu_w |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amomaxu_w; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_lr_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_lr_d | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_lr_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_sc_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_sc_d | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_sc_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoswap_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoswap_d |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amoswap_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoadd_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoadd_d |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amoadd_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoxor_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoxor_d |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amoxor_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoand_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoand_d |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amoand_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amoor_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amoor_d | _stQueue_io_enq_valid_T_1
     & opAmIO_bits_fun_amoor_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amomin_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amomin_d |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amomin_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amomax_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amomax_d |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amomax_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amominu_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amominu_d |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amominu_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_amomaxu_d = _stQueue_io_enq_valid_T & opStIO_bits_fun_amomaxu_d |
    _stQueue_io_enq_valid_T_1 & opAmIO_bits_fun_amomaxu_d; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_flw = _stQueue_io_enq_valid_T & opStIO_bits_fun_flw | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_flw; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_fsw = _stQueue_io_enq_valid_T & opStIO_bits_fun_fsw | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_fsw; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_fld = _stQueue_io_enq_valid_T & opStIO_bits_fun_fld | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_fld; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_fun_fsd = _stQueue_io_enq_valid_T & opStIO_bits_fun_fsd | _stQueue_io_enq_valid_T_1 &
    opAmIO_bits_fun_fsd; // @[Mux.scala 27:73]
  assign stQueue_io_enq_bits_param_dat_op1 = _stQueue_io_enq_bits_T_8 | _stQueue_io_enq_bits_T_9; // @[Mux.scala 27:73]
  assign stQueue_io_deq_ready = ls_arb_io_in_1_ready; // @[Lsu.scala 215:19]
  assign stQueue_io_cmm_lsu_is_amo_pending = io_cmm_lsu_is_amo_pending; // @[Lsu.scala 200:22]
  assign stQueue_io_cmm_lsu_is_store_commit_0 = io_cmm_lsu_is_store_commit_0; // @[Lsu.scala 200:22]
  assign stQueue_io_overlapReq_valid = _T_9 & addrTransIO_valid; // @[Lsu.scala 162:38 163:23 167:18]
  assign stQueue_io_overlapReq_bits_paddr = opLdIO_bits_param_dat_op1[31:0]; // @[Lsu.scala 208:36]
  assign stQueue_io_flush = io_flush; // @[Lsu.scala 202:20]
  assign ls_arb_io_in_0_valid = opLdIO_valid & stQueue_io_overlapResp_valid; // @[Lsu.scala 211:41]
  assign ls_arb_io_in_0_bits_fun_lb = _T_9 & io_lsu_iss_exe_bits_fun_lb; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_lh = _T_9 & io_lsu_iss_exe_bits_fun_lh; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_lw = _T_9 & io_lsu_iss_exe_bits_fun_lw; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_ld = _T_9 & io_lsu_iss_exe_bits_fun_ld; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_lbu = _T_9 & io_lsu_iss_exe_bits_fun_lbu; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_lhu = _T_9 & io_lsu_iss_exe_bits_fun_lhu; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_lwu = _T_9 & io_lsu_iss_exe_bits_fun_lwu; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_sb = _T_9 & io_lsu_iss_exe_bits_fun_sb; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_sh = _T_9 & io_lsu_iss_exe_bits_fun_sh; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_sw = _T_9 & io_lsu_iss_exe_bits_fun_sw; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_sd = _T_9 & io_lsu_iss_exe_bits_fun_sd; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_lr_w = _T_9 & io_lsu_iss_exe_bits_fun_lr_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_sc_w = _T_9 & io_lsu_iss_exe_bits_fun_sc_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoswap_w = _T_9 & io_lsu_iss_exe_bits_fun_amoswap_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoadd_w = _T_9 & io_lsu_iss_exe_bits_fun_amoadd_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoxor_w = _T_9 & io_lsu_iss_exe_bits_fun_amoxor_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoand_w = _T_9 & io_lsu_iss_exe_bits_fun_amoand_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoor_w = _T_9 & io_lsu_iss_exe_bits_fun_amoor_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amomin_w = _T_9 & io_lsu_iss_exe_bits_fun_amomin_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amomax_w = _T_9 & io_lsu_iss_exe_bits_fun_amomax_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amominu_w = _T_9 & io_lsu_iss_exe_bits_fun_amominu_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amomaxu_w = _T_9 & io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_lr_d = _T_9 & io_lsu_iss_exe_bits_fun_lr_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_sc_d = _T_9 & io_lsu_iss_exe_bits_fun_sc_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoswap_d = _T_9 & io_lsu_iss_exe_bits_fun_amoswap_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoadd_d = _T_9 & io_lsu_iss_exe_bits_fun_amoadd_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoxor_d = _T_9 & io_lsu_iss_exe_bits_fun_amoxor_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoand_d = _T_9 & io_lsu_iss_exe_bits_fun_amoand_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amoor_d = _T_9 & io_lsu_iss_exe_bits_fun_amoor_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amomin_d = _T_9 & io_lsu_iss_exe_bits_fun_amomin_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amomax_d = _T_9 & io_lsu_iss_exe_bits_fun_amomax_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amominu_d = _T_9 & io_lsu_iss_exe_bits_fun_amominu_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_amomaxu_d = _T_9 & io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_flw = _T_9 & io_lsu_iss_exe_bits_fun_flw; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_fsw = _T_9 & io_lsu_iss_exe_bits_fun_fsw; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_fld = _T_9 & io_lsu_iss_exe_bits_fun_fld; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_fun_fsd = _T_9 & io_lsu_iss_exe_bits_fun_fsd; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_0_bits_param_dat_op1 = _T_9 ? io_mmu_lsu_bits_paddr : 64'h0; // @[Lsu.scala 162:38 164:23 168:18]
  assign ls_arb_io_in_1_valid = stQueue_io_deq_valid; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_lb = stQueue_io_deq_bits_fun_lb; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_lh = stQueue_io_deq_bits_fun_lh; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_lw = stQueue_io_deq_bits_fun_lw; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_ld = stQueue_io_deq_bits_fun_ld; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_lbu = stQueue_io_deq_bits_fun_lbu; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_lhu = stQueue_io_deq_bits_fun_lhu; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_lwu = stQueue_io_deq_bits_fun_lwu; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_sb = stQueue_io_deq_bits_fun_sb; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_sh = stQueue_io_deq_bits_fun_sh; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_sw = stQueue_io_deq_bits_fun_sw; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_sd = stQueue_io_deq_bits_fun_sd; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_lr_w = stQueue_io_deq_bits_fun_lr_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_sc_w = stQueue_io_deq_bits_fun_sc_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoswap_w = stQueue_io_deq_bits_fun_amoswap_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoadd_w = stQueue_io_deq_bits_fun_amoadd_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoxor_w = stQueue_io_deq_bits_fun_amoxor_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoand_w = stQueue_io_deq_bits_fun_amoand_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoor_w = stQueue_io_deq_bits_fun_amoor_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amomin_w = stQueue_io_deq_bits_fun_amomin_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amomax_w = stQueue_io_deq_bits_fun_amomax_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amominu_w = stQueue_io_deq_bits_fun_amominu_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amomaxu_w = stQueue_io_deq_bits_fun_amomaxu_w; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_lr_d = stQueue_io_deq_bits_fun_lr_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_sc_d = stQueue_io_deq_bits_fun_sc_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoswap_d = stQueue_io_deq_bits_fun_amoswap_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoadd_d = stQueue_io_deq_bits_fun_amoadd_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoxor_d = stQueue_io_deq_bits_fun_amoxor_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoand_d = stQueue_io_deq_bits_fun_amoand_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amoor_d = stQueue_io_deq_bits_fun_amoor_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amomin_d = stQueue_io_deq_bits_fun_amomin_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amomax_d = stQueue_io_deq_bits_fun_amomax_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amominu_d = stQueue_io_deq_bits_fun_amominu_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_amomaxu_d = stQueue_io_deq_bits_fun_amomaxu_d; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_flw = stQueue_io_deq_bits_fun_flw; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_fsw = stQueue_io_deq_bits_fun_fsw; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_fld = stQueue_io_deq_bits_fun_fld; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_fun_fsd = stQueue_io_deq_bits_fun_fsd; // @[Lsu.scala 215:19]
  assign ls_arb_io_in_1_bits_param_dat_op1 = stQueue_io_deq_bits_param_dat_op1; // @[Lsu.scala 215:19]
  assign ls_arb_io_out_ready = sel == 2'h0 ? cacheBankIO_0_ready : _GEN_229; // @[Lsu.scala 246:23 249:26]
  assign system_clock = clock;
  assign system_reset = reset;
  assign system_io_enq_valid = sel == 2'h1 & ls_arb_io_out_valid; // @[Lsu.scala 237:23 238:26 242:26]
  assign system_io_enq_bits_fun_lb = sel == 2'h1 & ls_arb_io_out_bits_fun_lb; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_lh = sel == 2'h1 & ls_arb_io_out_bits_fun_lh; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_lw = sel == 2'h1 & ls_arb_io_out_bits_fun_lw; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_ld = sel == 2'h1 & ls_arb_io_out_bits_fun_ld; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_lbu = sel == 2'h1 & ls_arb_io_out_bits_fun_lbu; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_lhu = sel == 2'h1 & ls_arb_io_out_bits_fun_lhu; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_lwu = sel == 2'h1 & ls_arb_io_out_bits_fun_lwu; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_sb = sel == 2'h1 & ls_arb_io_out_bits_fun_sb; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_sh = sel == 2'h1 & ls_arb_io_out_bits_fun_sh; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_sw = sel == 2'h1 & ls_arb_io_out_bits_fun_sw; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_sd = sel == 2'h1 & ls_arb_io_out_bits_fun_sd; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_lr_w = sel == 2'h1 & ls_arb_io_out_bits_fun_lr_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_sc_w = sel == 2'h1 & ls_arb_io_out_bits_fun_sc_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_lr_d = sel == 2'h1 & ls_arb_io_out_bits_fun_lr_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_sc_d = sel == 2'h1 & ls_arb_io_out_bits_fun_sc_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_flw = sel == 2'h1 & ls_arb_io_out_bits_fun_flw; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_fsw = sel == 2'h1 & ls_arb_io_out_bits_fun_fsw; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_fld = sel == 2'h1 & ls_arb_io_out_bits_fun_fld; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_enq_bits_fun_fsd = sel == 2'h1 & ls_arb_io_out_bits_fun_fsd; // @[Lsu.scala 237:23 239:26 243:26]
  assign system_io_deq_ready = lu_wb_arb_io_in_1_ready | ~system_io_deq_bits_is_load_amo; // @[Lsu.scala 427:52]
  assign system_io_getPut_ready = io_system_getPut_ready; // @[Lsu.scala 391:26]
  assign system_io_access_valid = io_system_access_valid; // @[Lsu.scala 392:26]
  assign system_io_access_bits_opcode = io_system_access_bits_opcode; // @[Lsu.scala 393:26]
  assign periph_clock = clock;
  assign periph_reset = reset;
  assign periph_io_enq_valid = sel == 2'h2 & ls_arb_io_out_valid; // @[Lsu.scala 228:23 229:26 233:26]
  assign periph_io_enq_bits_fun_lb = sel == 2'h2 & ls_arb_io_out_bits_fun_lb; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_lh = sel == 2'h2 & ls_arb_io_out_bits_fun_lh; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_lw = sel == 2'h2 & ls_arb_io_out_bits_fun_lw; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_ld = sel == 2'h2 & ls_arb_io_out_bits_fun_ld; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_lbu = sel == 2'h2 & ls_arb_io_out_bits_fun_lbu; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_lhu = sel == 2'h2 & ls_arb_io_out_bits_fun_lhu; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_lwu = sel == 2'h2 & ls_arb_io_out_bits_fun_lwu; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_sb = sel == 2'h2 & ls_arb_io_out_bits_fun_sb; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_sh = sel == 2'h2 & ls_arb_io_out_bits_fun_sh; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_sw = sel == 2'h2 & ls_arb_io_out_bits_fun_sw; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_sd = sel == 2'h2 & ls_arb_io_out_bits_fun_sd; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_lr_w = sel == 2'h2 & ls_arb_io_out_bits_fun_lr_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_sc_w = sel == 2'h2 & ls_arb_io_out_bits_fun_sc_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_lr_d = sel == 2'h2 & ls_arb_io_out_bits_fun_lr_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_sc_d = sel == 2'h2 & ls_arb_io_out_bits_fun_sc_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_flw = sel == 2'h2 & ls_arb_io_out_bits_fun_flw; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_fsw = sel == 2'h2 & ls_arb_io_out_bits_fun_fsw; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_fld = sel == 2'h2 & ls_arb_io_out_bits_fun_fld; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_enq_bits_fun_fsd = sel == 2'h2 & ls_arb_io_out_bits_fun_fsd; // @[Lsu.scala 228:23 230:26 234:26]
  assign periph_io_deq_ready = lu_wb_arb_io_in_2_ready | ~periph_io_deq_bits_is_load_amo; // @[Lsu.scala 432:54]
  assign periph_io_getPut_ready = io_periph_getPut_ready; // @[Lsu.scala 402:26]
  assign periph_io_access_valid = io_periph_access_valid; // @[Lsu.scala 403:26]
  assign periph_io_access_bits_opcode = io_periph_access_bits_opcode; // @[Lsu.scala 404:26]
  assign cache_0_clock = clock;
  assign cache_0_reset = reset;
  assign cache_0_io_enq_valid = sel == 2'h0 & ls_arb_io_out_valid; // @[Lsu.scala 246:23 247:26 251:26]
  assign cache_0_io_enq_bits_paddr = regionDCacheIO_bits_param_dat_op1[31:0]; // @[Util.scala 81:19 84:15]
  assign cache_0_io_enq_bits_fun_lb = sel == 2'h0 & ls_arb_io_out_bits_fun_lb; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_lh = sel == 2'h0 & ls_arb_io_out_bits_fun_lh; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_lw = sel == 2'h0 & ls_arb_io_out_bits_fun_lw; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_ld = sel == 2'h0 & ls_arb_io_out_bits_fun_ld; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_lbu = sel == 2'h0 & ls_arb_io_out_bits_fun_lbu; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_lhu = sel == 2'h0 & ls_arb_io_out_bits_fun_lhu; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_lwu = sel == 2'h0 & ls_arb_io_out_bits_fun_lwu; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_sb = sel == 2'h0 & ls_arb_io_out_bits_fun_sb; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_sh = sel == 2'h0 & ls_arb_io_out_bits_fun_sh; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_sw = sel == 2'h0 & ls_arb_io_out_bits_fun_sw; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_sd = sel == 2'h0 & ls_arb_io_out_bits_fun_sd; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_lr_w = sel == 2'h0 & ls_arb_io_out_bits_fun_lr_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_sc_w = sel == 2'h0 & ls_arb_io_out_bits_fun_sc_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoswap_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amoswap_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoadd_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amoadd_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoxor_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amoxor_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoand_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amoand_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoor_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amoor_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amomin_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amomin_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amomax_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amomax_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amominu_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amominu_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amomaxu_w = sel == 2'h0 & ls_arb_io_out_bits_fun_amomaxu_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_lr_d = sel == 2'h0 & ls_arb_io_out_bits_fun_lr_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_sc_d = sel == 2'h0 & ls_arb_io_out_bits_fun_sc_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoswap_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amoswap_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoadd_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amoadd_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoxor_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amoxor_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoand_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amoand_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amoor_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amoor_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amomin_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amomin_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amomax_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amomax_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amominu_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amominu_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_amomaxu_d = sel == 2'h0 & ls_arb_io_out_bits_fun_amomaxu_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_flw = sel == 2'h0 & ls_arb_io_out_bits_fun_flw; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_fsw = sel == 2'h0 & ls_arb_io_out_bits_fun_fsw; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_fld = sel == 2'h0 & ls_arb_io_out_bits_fun_fld; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_enq_bits_fun_fsd = sel == 2'h0 & ls_arb_io_out_bits_fun_fsd; // @[Lsu.scala 246:23 248:26 252:26]
  assign cache_0_io_deq_ready = lu_wb_arb_io_in_0_ready | ~cache_0_io_deq_bits_is_load_amo; // @[Lsu.scala 421:55]
  assign cache_0_io_flush = io_flush; // @[Lsu.scala 382:23]
  assign cache_0_io_missUnit_dcache_acquire_ready = acquireArb_io_in_0_ready; // @[Lsu.scala 305:27]
  assign cache_0_io_missUnit_dcache_grant_valid = ~io_missUnit_dcache_grant_bits_source & io_missUnit_dcache_grant_valid
    ; // @[Lsu.scala 307:64 308:47 292:54]
  assign cache_0_io_missUnit_dcache_grant_bits_opcode = ~io_missUnit_dcache_grant_bits_source ?
    io_missUnit_dcache_grant_bits_opcode : 3'h0; // @[Lsu.scala 307:64 308:47 293:54]
  assign cache_0_io_missUnit_dcache_grant_bits_size = ~io_missUnit_dcache_grant_bits_source ?
    io_missUnit_dcache_grant_bits_size : 3'h0; // @[Lsu.scala 307:64 308:47 293:54]
  assign cache_0_io_missUnit_dcache_grant_bits_source = ~io_missUnit_dcache_grant_bits_source &
    io_missUnit_dcache_grant_bits_source; // @[Lsu.scala 307:64 308:47 293:54]
  assign cache_0_io_missUnit_dcache_grantAck_ready = grantAckArb_io_in_0_ready; // @[Lsu.scala 311:28]
  assign cache_0_io_probeUnit_dcache_probe_valid = io_probeUnit_dcache_probe_valid; // @[Lsu.scala 313:120 314:48 295:54]
  assign cache_0_io_probeUnit_dcache_probe_bits_address = io_probeUnit_dcache_probe_bits_address; // @[Lsu.scala 313:120 314:48 296:54]
  assign cache_0_io_writeBackUnit_dcache_release_ready = ~is_chnc_busy_0 ? releaseArb_io_in_0_ready : _GEN_366; // @[Lsu.scala 332:29 334:64]
  assign cache_0_io_writeBackUnit_dcache_grant_valid = ~io_writeBackUnit_dcache_grant_bits_source &
    io_writeBackUnit_dcache_grant_valid; // @[Lsu.scala 317:69 318:52 298:58]
  assign cache_0_io_writeBackUnit_dcache_grant_bits_source = ~io_writeBackUnit_dcache_grant_bits_source &
    io_writeBackUnit_dcache_grant_bits_source; // @[Lsu.scala 317:69 318:52 299:58]
  assign lu_wb_arb_io_in_0_valid = cache_0_io_deq_valid & cache_0_io_deq_bits_is_load_amo; // @[Lsu.scala 419:55]
  assign lu_wb_arb_io_in_0_bits_is_flw = lu_wb_arb_io_in_0_valid & cache_0_io_deq_bits_is_flw; // @[Lsu.scala 420:35]
  assign lu_wb_arb_io_in_0_bits_is_fld = lu_wb_arb_io_in_0_valid & cache_0_io_deq_bits_is_fld; // @[Lsu.scala 420:35]
  assign lu_wb_arb_io_in_1_valid = system_io_deq_valid & system_io_deq_bits_is_load_amo; // @[Lsu.scala 425:52]
  assign lu_wb_arb_io_in_1_bits_is_flw = lu_wb_arb_io_in_1_valid & system_io_deq_bits_is_flw; // @[Lsu.scala 426:34]
  assign lu_wb_arb_io_in_1_bits_is_fld = lu_wb_arb_io_in_1_valid & system_io_deq_bits_is_fld; // @[Lsu.scala 426:34]
  assign lu_wb_arb_io_in_2_valid = periph_io_deq_valid & periph_io_deq_bits_is_load_amo; // @[Lsu.scala 430:54]
  assign lu_wb_arb_io_in_2_bits_is_flw = lu_wb_arb_io_in_2_valid & periph_io_deq_bits_is_flw; // @[Lsu.scala 431:36]
  assign lu_wb_arb_io_in_2_bits_is_fld = lu_wb_arb_io_in_2_valid & periph_io_deq_bits_is_fld; // @[Lsu.scala 431:36]
  assign lu_wb_arb_io_out_ready = lu_wb_fifo_io_enq_ready & flu_wb_fifo_io_enq_ready | trans_kill; // @[Lsu.scala 454:82]
  assign lu_wb_fifo_clock = clock;
  assign lu_wb_fifo_reset = reset | io_flush; // @[Lsu.scala 440:36]
  assign lu_wb_fifo_io_enq_valid = lu_wb_arb_io_out_valid & _lu_wb_fifo_io_enq_valid_T_1 & ~trans_kill; // @[Lsu.scala 437:84]
  assign lu_wb_fifo_io_deq_ready = rtn_arb_io_in_1_ready; // @[Lsu.scala 475:20]
  assign flu_wb_fifo_clock = clock;
  assign flu_wb_fifo_reset = reset | io_flush; // @[Lsu.scala 451:37]
  assign flu_wb_fifo_io_enq_valid = lu_wb_arb_io_out_valid & _lu_wb_fifo_io_enq_valid_T & _lu_wb_fifo_io_enq_valid_T_3; // @[Lsu.scala 443:85]
  assign flu_wb_fifo_io_deq_ready = io_lsu_exe_fwb_ready; // @[Lsu.scala 450:22]
  assign su_wb_fifo_clock = clock;
  assign su_wb_fifo_reset = reset | io_flush; // @[Lsu.scala 460:36]
  assign su_wb_fifo_io_enq_valid = opStIO_ready & opStIO_valid; // @[Decoupled.scala 52:35]
  assign su_wb_fifo_io_deq_ready = rtn_arb_io_in_0_ready; // @[Lsu.scala 474:20]
  assign fe_wb_fifo_clock = clock;
  assign fe_wb_fifo_reset = reset | io_flush; // @[Lsu.scala 470:36]
  assign fe_wb_fifo_io_enq_valid = is_empty & _addrTransIO_valid_T_48 & io_lsu_iss_exe_valid; // @[Lsu.scala 467:74]
  assign fe_wb_fifo_io_deq_ready = rtn_arb_io_in_2_ready; // @[Lsu.scala 476:20]
  assign rtn_arb_io_in_0_valid = su_wb_fifo_io_deq_valid; // @[Lsu.scala 474:20]
  assign rtn_arb_io_in_1_valid = lu_wb_fifo_io_deq_valid; // @[Lsu.scala 475:20]
  assign rtn_arb_io_out_ready = io_lsu_exe_iwb_ready; // @[Lsu.scala 477:18]
  assign acquireArb_io_out_ready = io_missUnit_dcache_acquire_ready; // @[Lsu.scala 302:37]
  assign grantAckArb_io_out_ready = io_missUnit_dcache_grantAck_ready; // @[Lsu.scala 303:37]
  assign releaseArb_io_out_ready = ~is_chnc_busy_0 & io_writeBackUnit_dcache_release_ready; // @[Lsu.scala 334:64 335:45 337:33]
  always @(posedge clock) begin
    if (reset) begin // @[Lsu.scala 73:27]
      trans_kill <= 1'h0; // @[Lsu.scala 73:27]
    end else begin
      trans_kill <= _GEN_378;
    end
    if (reset) begin // @[Lsu.scala 325:33]
      is_chnc_busy_0 <= 1'h0; // @[Lsu.scala 325:33]
    end else if (_is_release_done_T) begin // @[Lsu.scala 328:67]
      if (is_release_done_0) begin // @[Lsu.scala 328:91]
        is_chnc_busy_0 <= 1'h0;
      end else begin
        is_chnc_busy_0 <= 1'h1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      is_release_done_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_is_release_done_T) begin // @[Edges.scala 234:17]
      if (is_release_done_first) begin // @[Edges.scala 235:21]
        is_release_done_counter <= is_release_done_beats1;
      end else begin
        is_release_done_counter <= is_release_done_counter1;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Lsu.scala 342:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cache_0_io_deq_bits_is_load_amo & _T_47 & ~(_T_49 == _T_50)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Lsu.scala:422 when( cache(i).io.deq.bits.is_load_amo ) { assert(cache(i).io.deq.fire === lu_wb_arb.io.in(i).fire) }\n"
            ); // @[Lsu.scala 422:54]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_49 == _T_50) & (cache_0_io_deq_bits_is_load_amo & _T_47)) begin
          $fatal; // @[Lsu.scala 422:54]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (system_io_deq_bits_is_load_amo & _T_47 & ~(_T_55 == _T_56)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Lsu.scala:428 when( system.io.deq.bits.is_load_amo ) { assert(system.io.deq.fire === lu_wb_arb.io.in(bk).fire) }\n"
            ); // @[Lsu.scala 428:50]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_55 == _T_56) & (system_io_deq_bits_is_load_amo & _T_47)) begin
          $fatal; // @[Lsu.scala 428:50]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (periph_io_deq_bits_is_load_amo & _T_47 & ~(_T_61 == _T_62)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Lsu.scala:433 when( periph.io.deq.bits.is_load_amo ) { assert(periph.io.deq.fire === lu_wb_arb.io.in(bk+1).fire) }\n"
            ); // @[Lsu.scala 433:50]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_61 == _T_62) & (periph_io_deq_bits_is_load_amo & _T_47)) begin
          $fatal; // @[Lsu.scala 433:50]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  trans_kill = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  is_chnc_busy_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  is_release_done_counter = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_21(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  always @(posedge clock) begin
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  maybe_full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Csr(
  input   clock,
  input   reset,
  input   io_csr_iss_exe_valid,
  input   io_csr_exe_iwb_ready,
  input   io_csr_data_valid,
  input   io_csr_cmm_op_ready,
  input   io_flush
);
  wire  csr_exe_iwb_fifo_clock; // @[Csr.scala 43:32]
  wire  csr_exe_iwb_fifo_reset; // @[Csr.scala 43:32]
  wire  csr_exe_iwb_fifo_io_enq_ready; // @[Csr.scala 43:32]
  wire  csr_exe_iwb_fifo_io_enq_valid; // @[Csr.scala 43:32]
  wire  csr_exe_iwb_fifo_io_deq_ready; // @[Csr.scala 43:32]
  wire  csr_exe_iwb_fifo_io_deq_valid; // @[Csr.scala 43:32]
  wire  csr_op_fifo_clock; // @[Csr.scala 47:27]
  wire  csr_op_fifo_reset; // @[Csr.scala 47:27]
  wire  csr_op_fifo_io_enq_ready; // @[Csr.scala 47:27]
  wire  csr_op_fifo_io_enq_valid; // @[Csr.scala 47:27]
  wire  csr_op_fifo_io_deq_ready; // @[Csr.scala 47:27]
  wire  csr_op_fifo_io_deq_valid; // @[Csr.scala 47:27]
  Queue_7 csr_exe_iwb_fifo ( // @[Csr.scala 43:32]
    .clock(csr_exe_iwb_fifo_clock),
    .reset(csr_exe_iwb_fifo_reset),
    .io_enq_ready(csr_exe_iwb_fifo_io_enq_ready),
    .io_enq_valid(csr_exe_iwb_fifo_io_enq_valid),
    .io_deq_ready(csr_exe_iwb_fifo_io_deq_ready),
    .io_deq_valid(csr_exe_iwb_fifo_io_deq_valid)
  );
  Queue_21 csr_op_fifo ( // @[Csr.scala 47:27]
    .clock(csr_op_fifo_clock),
    .reset(csr_op_fifo_reset),
    .io_enq_ready(csr_op_fifo_io_enq_ready),
    .io_enq_valid(csr_op_fifo_io_enq_valid),
    .io_deq_ready(csr_op_fifo_io_deq_ready),
    .io_deq_valid(csr_op_fifo_io_deq_valid)
  );
  assign csr_exe_iwb_fifo_clock = clock;
  assign csr_exe_iwb_fifo_reset = reset | io_flush; // @[Csr.scala 45:42]
  assign csr_exe_iwb_fifo_io_enq_valid = io_csr_iss_exe_valid & csr_op_fifo_io_enq_ready & io_csr_data_valid; // @[Csr.scala 74:84]
  assign csr_exe_iwb_fifo_io_deq_ready = io_csr_exe_iwb_ready; // @[Csr.scala 44:18]
  assign csr_op_fifo_clock = clock;
  assign csr_op_fifo_reset = reset | io_flush; // @[Csr.scala 49:37]
  assign csr_op_fifo_io_enq_valid = csr_exe_iwb_fifo_io_enq_ready & csr_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  assign csr_op_fifo_io_deq_ready = io_csr_cmm_op_ready; // @[Csr.scala 48:17]
endmodule
module NorMultiplier(
  input   io_enq_valid,
  output  io_deq_valid
);
  assign io_deq_valid = io_enq_valid; // @[Mul.scala 418:10]
endmodule
module NorDivider(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_deq_ready,
  output  io_deq_valid,
  input   io_flush
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg  isDivBusy; // @[Mul.scala 582:26]
  reg [6:0] cnt; // @[Mul.scala 584:20]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire [6:0] _cnt_T_1 = cnt + 7'h1; // @[Mul.scala 588:16]
  wire  _T_4 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_2 = _T | isDivBusy; // @[Mul.scala 598:30 599:15 582:26]
  assign io_enq_ready = ~isDivBusy; // @[Mul.scala 594:19]
  assign io_deq_valid = isDivBusy & cnt == 7'h40; // @[Mul.scala 626:29]
  always @(posedge clock) begin
    if (reset) begin // @[Mul.scala 582:26]
      isDivBusy <= 1'h0; // @[Mul.scala 582:26]
    end else if (_T_4 | io_flush) begin // @[Mul.scala 596:34]
      isDivBusy <= 1'h0; // @[Mul.scala 597:15]
    end else begin
      isDivBusy <= _GEN_2;
    end
    if (reset) begin // @[Mul.scala 584:20]
      cnt <= 7'h0; // @[Mul.scala 584:20]
    end else if (_T | io_flush) begin // @[Mul.scala 585:34]
      cnt <= 7'h0; // @[Mul.scala 586:9]
    end else if (isDivBusy & cnt != 7'h40) begin // @[Mul.scala 587:43]
      cnt <= _cnt_T_1; // @[Mul.scala 588:9]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  isDivBusy = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  cnt = _RAND_1[6:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Arbiter_8(
  output  io_in_0_ready,
  input   io_in_0_valid,
  output  io_in_1_ready,
  input   io_in_1_valid,
  input   io_out_ready,
  output  io_out_valid
);
  wire  grant_1 = ~io_in_0_valid; // @[Arbiter.scala 45:78]
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
  assign io_in_1_ready = grant_1 & io_out_ready; // @[Arbiter.scala 146:19]
  assign io_out_valid = ~grant_1 | io_in_1_valid; // @[Arbiter.scala 147:31]
endmodule
module Dividor(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_fun_div,
  input         io_enq_bits_fun_divu,
  input         io_enq_bits_fun_rem,
  input         io_enq_bits_fun_remu,
  input         io_enq_bits_fun_divw,
  input         io_enq_bits_fun_divuw,
  input         io_enq_bits_fun_remw,
  input         io_enq_bits_fun_remuw,
  input  [63:0] io_enq_bits_param_dat_op1,
  input  [63:0] io_enq_bits_param_dat_op2,
  input         io_deq_ready,
  output        io_deq_valid,
  input         io_flush
);
  wire  algDivider_clock; // @[Mul.scala 507:26]
  wire  algDivider_reset; // @[Mul.scala 507:26]
  wire  algDivider_io_enq_ready; // @[Mul.scala 507:26]
  wire  algDivider_io_enq_valid; // @[Mul.scala 507:26]
  wire  algDivider_io_deq_ready; // @[Mul.scala 507:26]
  wire  algDivider_io_deq_valid; // @[Mul.scala 507:26]
  wire  algDivider_io_flush; // @[Mul.scala 507:26]
  wire  divRtnArb_io_in_0_ready; // @[Mul.scala 548:25]
  wire  divRtnArb_io_in_0_valid; // @[Mul.scala 548:25]
  wire  divRtnArb_io_in_1_ready; // @[Mul.scala 548:25]
  wire  divRtnArb_io_in_1_valid; // @[Mul.scala 548:25]
  wire  divRtnArb_io_out_ready; // @[Mul.scala 548:25]
  wire  divRtnArb_io_out_valid; // @[Mul.scala 548:25]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_7 = io_enq_bits_fun_div | io_enq_bits_fun_divu | io_enq_bits_fun_divw | io_enq_bits_fun_divuw |
    io_enq_bits_fun_rem | io_enq_bits_fun_remu | io_enq_bits_fun_remw | io_enq_bits_fun_remuw; // @[riscv_isa.scala 204:61]
  wire  is32wPre = io_enq_bits_fun_divw | io_enq_bits_fun_divuw | io_enq_bits_fun_remw | io_enq_bits_fun_remuw; // @[riscv_isa.scala 199:39]
  wire  isUsiPre = io_enq_bits_fun_divu | io_enq_bits_fun_remu | io_enq_bits_fun_divuw | io_enq_bits_fun_remuw; // @[riscv_isa.scala 200:39]
  wire  isDivByZero = io_enq_bits_param_dat_op2 == 64'h0; // @[Mul.scala 480:29]
  wire  _isDivOverflow_T_10 = is32wPre & (io_enq_bits_param_dat_op1[31] & io_enq_bits_param_dat_op1[30:0] == 31'h0) & &
    io_enq_bits_param_dat_op2[31:0]; // @[Mul.scala 483:76]
  wire  _isDivOverflow_T_21 = ~is32wPre & (io_enq_bits_param_dat_op1[63] & io_enq_bits_param_dat_op1[62:0] == 63'h0) & &
    io_enq_bits_param_dat_op2; // @[Mul.scala 485:76]
  wire  _isDivOverflow_T_22 = _isDivOverflow_T_10 | _isDivOverflow_T_21; // @[Mul.scala 484:17]
  wire  isDivOverflow = ~isUsiPre & _isDivOverflow_T_22; // @[Mul.scala 481:33]
  wire  divBypass = isDivByZero | isDivOverflow; // @[Mul.scala 487:31]
  NorDivider algDivider ( // @[Mul.scala 507:26]
    .clock(algDivider_clock),
    .reset(algDivider_reset),
    .io_enq_ready(algDivider_io_enq_ready),
    .io_enq_valid(algDivider_io_enq_valid),
    .io_deq_ready(algDivider_io_deq_ready),
    .io_deq_valid(algDivider_io_deq_valid),
    .io_flush(algDivider_io_flush)
  );
  Arbiter_8 divRtnArb ( // @[Mul.scala 548:25]
    .io_in_0_ready(divRtnArb_io_in_0_ready),
    .io_in_0_valid(divRtnArb_io_in_0_valid),
    .io_in_1_ready(divRtnArb_io_in_1_ready),
    .io_in_1_valid(divRtnArb_io_in_1_valid),
    .io_out_ready(divRtnArb_io_out_ready),
    .io_out_valid(divRtnArb_io_out_valid)
  );
  assign io_enq_ready = divBypass ? divRtnArb_io_in_1_ready : algDivider_io_enq_ready; // @[Mul.scala 559:22]
  assign io_deq_valid = divRtnArb_io_out_valid; // @[Mul.scala 560:10]
  assign algDivider_clock = clock;
  assign algDivider_reset = reset;
  assign algDivider_io_enq_valid = io_enq_valid & ~divBypass; // @[Mul.scala 509:45]
  assign algDivider_io_deq_ready = divRtnArb_io_in_0_ready; // @[Mul.scala 557:28]
  assign algDivider_io_flush = io_flush; // @[Mul.scala 515:25]
  assign divRtnArb_io_in_0_valid = algDivider_io_deq_valid; // @[Mul.scala 554:28]
  assign divRtnArb_io_in_1_valid = io_enq_valid & divBypass; // @[Mul.scala 549:44]
  assign divRtnArb_io_out_ready = io_deq_ready; // @[Mul.scala 560:10]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T & ~reset & ~_T_7) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Mul.scala:430 when( io.enq.fire ) { assert( io.enq.bits.fun.isDiv ) }\n"); // @[Mul.scala 430:31]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_7 & (_T & ~reset)) begin
          $fatal; // @[Mul.scala 430:31]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module MulDiv(
  input         clock,
  input         reset,
  input         io_mul_iss_exe_valid,
  input         io_mul_iss_exe_bits_fun_mul,
  input         io_mul_iss_exe_bits_fun_mulh,
  input         io_mul_iss_exe_bits_fun_mulhsu,
  input         io_mul_iss_exe_bits_fun_mulhu,
  input         io_mul_iss_exe_bits_fun_div,
  input         io_mul_iss_exe_bits_fun_divu,
  input         io_mul_iss_exe_bits_fun_rem,
  input         io_mul_iss_exe_bits_fun_remu,
  input         io_mul_iss_exe_bits_fun_mulw,
  input         io_mul_iss_exe_bits_fun_divw,
  input         io_mul_iss_exe_bits_fun_divuw,
  input         io_mul_iss_exe_bits_fun_remw,
  input         io_mul_iss_exe_bits_fun_remuw,
  input  [63:0] io_mul_iss_exe_bits_param_dat_op1,
  input  [63:0] io_mul_iss_exe_bits_param_dat_op2,
  input         io_mul_exe_iwb_ready,
  input         io_flush
);
  wire  mul_exe_iwb_fifo_clock; // @[Mul.scala 40:32]
  wire  mul_exe_iwb_fifo_reset; // @[Mul.scala 40:32]
  wire  mul_exe_iwb_fifo_io_enq_ready; // @[Mul.scala 40:32]
  wire  mul_exe_iwb_fifo_io_enq_valid; // @[Mul.scala 40:32]
  wire  mul_exe_iwb_fifo_io_deq_ready; // @[Mul.scala 40:32]
  wire  mul_exe_iwb_fifo_io_deq_valid; // @[Mul.scala 40:32]
  wire  multiplier_io_enq_valid; // @[Mul.scala 80:26]
  wire  multiplier_io_deq_valid; // @[Mul.scala 80:26]
  wire  dividor_clock; // @[Mul.scala 104:23]
  wire  dividor_reset; // @[Mul.scala 104:23]
  wire  dividor_io_enq_ready; // @[Mul.scala 104:23]
  wire  dividor_io_enq_valid; // @[Mul.scala 104:23]
  wire  dividor_io_enq_bits_fun_div; // @[Mul.scala 104:23]
  wire  dividor_io_enq_bits_fun_divu; // @[Mul.scala 104:23]
  wire  dividor_io_enq_bits_fun_rem; // @[Mul.scala 104:23]
  wire  dividor_io_enq_bits_fun_remu; // @[Mul.scala 104:23]
  wire  dividor_io_enq_bits_fun_divw; // @[Mul.scala 104:23]
  wire  dividor_io_enq_bits_fun_divuw; // @[Mul.scala 104:23]
  wire  dividor_io_enq_bits_fun_remw; // @[Mul.scala 104:23]
  wire  dividor_io_enq_bits_fun_remuw; // @[Mul.scala 104:23]
  wire [63:0] dividor_io_enq_bits_param_dat_op1; // @[Mul.scala 104:23]
  wire [63:0] dividor_io_enq_bits_param_dat_op2; // @[Mul.scala 104:23]
  wire  dividor_io_deq_ready; // @[Mul.scala 104:23]
  wire  dividor_io_deq_valid; // @[Mul.scala 104:23]
  wire  dividor_io_flush; // @[Mul.scala 104:23]
  wire  iwbArb_io_in_0_ready; // @[Mul.scala 127:22]
  wire  iwbArb_io_in_0_valid; // @[Mul.scala 127:22]
  wire  iwbArb_io_in_1_ready; // @[Mul.scala 127:22]
  wire  iwbArb_io_in_1_valid; // @[Mul.scala 127:22]
  wire  iwbArb_io_out_ready; // @[Mul.scala 127:22]
  wire  iwbArb_io_out_valid; // @[Mul.scala 127:22]
  wire  _multiplier_io_enq_valid_T_3 = io_mul_iss_exe_bits_fun_mul | io_mul_iss_exe_bits_fun_mulh |
    io_mul_iss_exe_bits_fun_mulhsu | io_mul_iss_exe_bits_fun_mulhu | io_mul_iss_exe_bits_fun_mulw; // @[riscv_isa.scala 203:43]
  wire  _dividor_io_enq_valid_T_6 = io_mul_iss_exe_bits_fun_div | io_mul_iss_exe_bits_fun_divu |
    io_mul_iss_exe_bits_fun_divw | io_mul_iss_exe_bits_fun_divuw | io_mul_iss_exe_bits_fun_rem |
    io_mul_iss_exe_bits_fun_remu | io_mul_iss_exe_bits_fun_remw | io_mul_iss_exe_bits_fun_remuw; // @[riscv_isa.scala 204:61]
  Queue_7 mul_exe_iwb_fifo ( // @[Mul.scala 40:32]
    .clock(mul_exe_iwb_fifo_clock),
    .reset(mul_exe_iwb_fifo_reset),
    .io_enq_ready(mul_exe_iwb_fifo_io_enq_ready),
    .io_enq_valid(mul_exe_iwb_fifo_io_enq_valid),
    .io_deq_ready(mul_exe_iwb_fifo_io_deq_ready),
    .io_deq_valid(mul_exe_iwb_fifo_io_deq_valid)
  );
  NorMultiplier multiplier ( // @[Mul.scala 80:26]
    .io_enq_valid(multiplier_io_enq_valid),
    .io_deq_valid(multiplier_io_deq_valid)
  );
  Dividor dividor ( // @[Mul.scala 104:23]
    .clock(dividor_clock),
    .reset(dividor_reset),
    .io_enq_ready(dividor_io_enq_ready),
    .io_enq_valid(dividor_io_enq_valid),
    .io_enq_bits_fun_div(dividor_io_enq_bits_fun_div),
    .io_enq_bits_fun_divu(dividor_io_enq_bits_fun_divu),
    .io_enq_bits_fun_rem(dividor_io_enq_bits_fun_rem),
    .io_enq_bits_fun_remu(dividor_io_enq_bits_fun_remu),
    .io_enq_bits_fun_divw(dividor_io_enq_bits_fun_divw),
    .io_enq_bits_fun_divuw(dividor_io_enq_bits_fun_divuw),
    .io_enq_bits_fun_remw(dividor_io_enq_bits_fun_remw),
    .io_enq_bits_fun_remuw(dividor_io_enq_bits_fun_remuw),
    .io_enq_bits_param_dat_op1(dividor_io_enq_bits_param_dat_op1),
    .io_enq_bits_param_dat_op2(dividor_io_enq_bits_param_dat_op2),
    .io_deq_ready(dividor_io_deq_ready),
    .io_deq_valid(dividor_io_deq_valid),
    .io_flush(dividor_io_flush)
  );
  Arbiter_8 iwbArb ( // @[Mul.scala 127:22]
    .io_in_0_ready(iwbArb_io_in_0_ready),
    .io_in_0_valid(iwbArb_io_in_0_valid),
    .io_in_1_ready(iwbArb_io_in_1_ready),
    .io_in_1_valid(iwbArb_io_in_1_valid),
    .io_out_ready(iwbArb_io_out_ready),
    .io_out_valid(iwbArb_io_out_valid)
  );
  assign mul_exe_iwb_fifo_clock = clock;
  assign mul_exe_iwb_fifo_reset = reset | io_flush; // @[Mul.scala 41:42]
  assign mul_exe_iwb_fifo_io_enq_valid = iwbArb_io_out_valid; // @[Mul.scala 139:27]
  assign mul_exe_iwb_fifo_io_deq_ready = io_mul_exe_iwb_ready; // @[Mul.scala 42:18]
  assign multiplier_io_enq_valid = io_mul_iss_exe_valid & _multiplier_io_enq_valid_T_3; // @[Mul.scala 84:51]
  assign dividor_clock = clock;
  assign dividor_reset = reset;
  assign dividor_io_enq_valid = _dividor_io_enq_valid_T_6 & io_mul_iss_exe_valid; // @[Mul.scala 107:57]
  assign dividor_io_enq_bits_fun_div = io_mul_iss_exe_bits_fun_div; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_fun_divu = io_mul_iss_exe_bits_fun_divu; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_fun_rem = io_mul_iss_exe_bits_fun_rem; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_fun_remu = io_mul_iss_exe_bits_fun_remu; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_fun_divw = io_mul_iss_exe_bits_fun_divw; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_fun_divuw = io_mul_iss_exe_bits_fun_divuw; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_fun_remw = io_mul_iss_exe_bits_fun_remw; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_fun_remuw = io_mul_iss_exe_bits_fun_remuw; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_param_dat_op1 = io_mul_iss_exe_bits_param_dat_op1; // @[Mul.scala 106:24]
  assign dividor_io_enq_bits_param_dat_op2 = io_mul_iss_exe_bits_param_dat_op2; // @[Mul.scala 106:24]
  assign dividor_io_deq_ready = iwbArb_io_in_1_ready; // @[Mul.scala 135:19]
  assign dividor_io_flush = io_flush; // @[Mul.scala 109:20]
  assign iwbArb_io_in_0_valid = multiplier_io_deq_valid; // @[Mul.scala 131:25]
  assign iwbArb_io_in_1_valid = dividor_io_deq_valid; // @[Mul.scala 135:19]
  assign iwbArb_io_out_ready = mul_exe_iwb_fifo_io_enq_ready; // @[Mul.scala 139:27]
endmodule
module FakeFAlu(
  input   clock,
  input   reset,
  input   io_fpu_iss_exe_valid
);
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_fpu_iss_exe_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at FAlu.scala:282 assert( ~io.fpu_iss_exe.valid )\n"); // @[FAlu.scala 282:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_fpu_iss_exe_valid) & ~reset) begin
          $fatal; // @[FAlu.scala 282:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module Execute(
  input         clock,
  input         reset,
  input         io_alu_iss_exe_0_valid,
  input         io_alu_exe_iwb_0_ready,
  input         io_bru_iss_exe_valid,
  input         io_bru_iss_exe_bits_fun_jalr,
  input         io_bru_iss_exe_bits_fun_beq,
  input         io_bru_iss_exe_bits_fun_bne,
  input         io_bru_iss_exe_bits_fun_blt,
  input         io_bru_iss_exe_bits_fun_bge,
  input         io_bru_iss_exe_bits_fun_bltu,
  input         io_bru_iss_exe_bits_fun_bgeu,
  input  [63:0] io_bru_iss_exe_bits_param_imm,
  input  [63:0] io_bru_iss_exe_bits_param_dat_op1,
  input  [63:0] io_bru_iss_exe_bits_param_dat_op2,
  input         io_bru_exe_iwb_ready,
  input         io_csr_iss_exe_valid,
  input         io_csr_exe_iwb_ready,
  input         io_lsu_iss_exe_valid,
  input         io_lsu_iss_exe_bits_fun_lb,
  input         io_lsu_iss_exe_bits_fun_lh,
  input         io_lsu_iss_exe_bits_fun_lw,
  input         io_lsu_iss_exe_bits_fun_ld,
  input         io_lsu_iss_exe_bits_fun_lbu,
  input         io_lsu_iss_exe_bits_fun_lhu,
  input         io_lsu_iss_exe_bits_fun_lwu,
  input         io_lsu_iss_exe_bits_fun_sb,
  input         io_lsu_iss_exe_bits_fun_sh,
  input         io_lsu_iss_exe_bits_fun_sw,
  input         io_lsu_iss_exe_bits_fun_sd,
  input         io_lsu_iss_exe_bits_fun_fence,
  input         io_lsu_iss_exe_bits_fun_fence_i,
  input         io_lsu_iss_exe_bits_fun_sfence_vma,
  input         io_lsu_iss_exe_bits_fun_lr_w,
  input         io_lsu_iss_exe_bits_fun_sc_w,
  input         io_lsu_iss_exe_bits_fun_amoswap_w,
  input         io_lsu_iss_exe_bits_fun_amoadd_w,
  input         io_lsu_iss_exe_bits_fun_amoxor_w,
  input         io_lsu_iss_exe_bits_fun_amoand_w,
  input         io_lsu_iss_exe_bits_fun_amoor_w,
  input         io_lsu_iss_exe_bits_fun_amomin_w,
  input         io_lsu_iss_exe_bits_fun_amomax_w,
  input         io_lsu_iss_exe_bits_fun_amominu_w,
  input         io_lsu_iss_exe_bits_fun_amomaxu_w,
  input         io_lsu_iss_exe_bits_fun_lr_d,
  input         io_lsu_iss_exe_bits_fun_sc_d,
  input         io_lsu_iss_exe_bits_fun_amoswap_d,
  input         io_lsu_iss_exe_bits_fun_amoadd_d,
  input         io_lsu_iss_exe_bits_fun_amoxor_d,
  input         io_lsu_iss_exe_bits_fun_amoand_d,
  input         io_lsu_iss_exe_bits_fun_amoor_d,
  input         io_lsu_iss_exe_bits_fun_amomin_d,
  input         io_lsu_iss_exe_bits_fun_amomax_d,
  input         io_lsu_iss_exe_bits_fun_amominu_d,
  input         io_lsu_iss_exe_bits_fun_amomaxu_d,
  input         io_lsu_iss_exe_bits_fun_flw,
  input         io_lsu_iss_exe_bits_fun_fsw,
  input         io_lsu_iss_exe_bits_fun_fld,
  input         io_lsu_iss_exe_bits_fun_fsd,
  input  [63:0] io_lsu_iss_exe_bits_param_dat_op1,
  input         io_lsu_exe_iwb_ready,
  input         io_lsu_exe_fwb_ready,
  input         io_mul_iss_exe_0_valid,
  input         io_mul_iss_exe_0_bits_fun_mul,
  input         io_mul_iss_exe_0_bits_fun_mulh,
  input         io_mul_iss_exe_0_bits_fun_mulhsu,
  input         io_mul_iss_exe_0_bits_fun_mulhu,
  input         io_mul_iss_exe_0_bits_fun_div,
  input         io_mul_iss_exe_0_bits_fun_divu,
  input         io_mul_iss_exe_0_bits_fun_rem,
  input         io_mul_iss_exe_0_bits_fun_remu,
  input         io_mul_iss_exe_0_bits_fun_mulw,
  input         io_mul_iss_exe_0_bits_fun_divw,
  input         io_mul_iss_exe_0_bits_fun_divuw,
  input         io_mul_iss_exe_0_bits_fun_remw,
  input         io_mul_iss_exe_0_bits_fun_remuw,
  input  [63:0] io_mul_iss_exe_0_bits_param_dat_op1,
  input  [63:0] io_mul_iss_exe_0_bits_param_dat_op2,
  input         io_mul_exe_iwb_0_ready,
  input         io_fpu_iss_exe_0_valid,
  input         io_bftq_valid,
  input         io_bftq_bits_isPredictTaken,
  input         io_jftq_valid,
  input  [38:0] io_jftq_bits_btbResp_target,
  input  [38:0] io_jftq_bits_rasResp_target,
  input         io_jftq_bits_isRas,
  input         io_bctq_ready,
  input         io_jctq_ready,
  input         io_csr_data_valid,
  input         io_csr_cmm_op_ready,
  input         io_mmu_lsu_valid,
  input  [63:0] io_mmu_lsu_bits_paddr,
  input         io_mmu_lsu_bits_is_paging_fault,
  input         io_mmu_lsu_bits_is_access_fault,
  input         io_cmm_lsu_is_amo_pending,
  input         io_cmm_lsu_is_store_commit_0,
  input         io_missUnit_dcache_acquire_ready,
  input         io_missUnit_dcache_grant_valid,
  input  [2:0]  io_missUnit_dcache_grant_bits_opcode,
  input  [2:0]  io_missUnit_dcache_grant_bits_size,
  input         io_missUnit_dcache_grant_bits_source,
  input         io_missUnit_dcache_grantAck_ready,
  input         io_probeUnit_dcache_probe_valid,
  input  [31:0] io_probeUnit_dcache_probe_bits_address,
  input         io_writeBackUnit_dcache_release_ready,
  input         io_writeBackUnit_dcache_grant_valid,
  input         io_writeBackUnit_dcache_grant_bits_source,
  input         io_system_getPut_ready,
  input         io_system_access_valid,
  input  [2:0]  io_system_access_bits_opcode,
  input         io_periph_getPut_ready,
  input         io_periph_access_valid,
  input  [2:0]  io_periph_access_bits_opcode,
  input         io_flush
);
  wire  alu_0_clock; // @[Execute.scala 98:52]
  wire  alu_0_reset; // @[Execute.scala 98:52]
  wire  alu_0_io_alu_iss_exe_valid; // @[Execute.scala 98:52]
  wire  alu_0_io_alu_exe_iwb_ready; // @[Execute.scala 98:52]
  wire  alu_0_io_flush; // @[Execute.scala 98:52]
  wire  bru_clock; // @[Execute.scala 99:19]
  wire  bru_reset; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_ready; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_valid; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_bits_fun_jalr; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_bits_fun_beq; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_bits_fun_bne; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_bits_fun_blt; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_bits_fun_bge; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_bits_fun_bltu; // @[Execute.scala 99:19]
  wire  bru_io_bru_iss_exe_bits_fun_bgeu; // @[Execute.scala 99:19]
  wire [63:0] bru_io_bru_iss_exe_bits_param_imm; // @[Execute.scala 99:19]
  wire [63:0] bru_io_bru_iss_exe_bits_param_dat_op1; // @[Execute.scala 99:19]
  wire [63:0] bru_io_bru_iss_exe_bits_param_dat_op2; // @[Execute.scala 99:19]
  wire  bru_io_bru_exe_iwb_ready; // @[Execute.scala 99:19]
  wire  bru_io_bftq_ready; // @[Execute.scala 99:19]
  wire  bru_io_bftq_valid; // @[Execute.scala 99:19]
  wire  bru_io_bftq_bits_isPredictTaken; // @[Execute.scala 99:19]
  wire  bru_io_jftq_ready; // @[Execute.scala 99:19]
  wire  bru_io_jftq_valid; // @[Execute.scala 99:19]
  wire [38:0] bru_io_jftq_bits_btbResp_target; // @[Execute.scala 99:19]
  wire [38:0] bru_io_jftq_bits_rasResp_target; // @[Execute.scala 99:19]
  wire  bru_io_jftq_bits_isRas; // @[Execute.scala 99:19]
  wire  bru_io_bctq_ready; // @[Execute.scala 99:19]
  wire  bru_io_jctq_ready; // @[Execute.scala 99:19]
  wire  bru_io_flush; // @[Execute.scala 99:19]
  wire  lsu_clock; // @[Execute.scala 101:21]
  wire  lsu_reset; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_valid; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_lb; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_lh; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_lw; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_ld; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_lbu; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_lhu; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_lwu; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_sb; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_sh; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_sw; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_sd; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_fence; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_fence_i; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_sfence_vma; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_lr_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_sc_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoswap_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoadd_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoxor_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoand_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoor_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amomin_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amomax_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amominu_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_lr_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_sc_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoswap_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoadd_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoxor_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoand_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amoor_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amomin_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amomax_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amominu_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_flw; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_fsw; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_fld; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_iss_exe_bits_fun_fsd; // @[Execute.scala 101:21]
  wire [63:0] lsu_io_lsu_iss_exe_bits_param_dat_op1; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_exe_iwb_ready; // @[Execute.scala 101:21]
  wire  lsu_io_lsu_exe_fwb_ready; // @[Execute.scala 101:21]
  wire  lsu_io_cmm_lsu_is_amo_pending; // @[Execute.scala 101:21]
  wire  lsu_io_cmm_lsu_is_store_commit_0; // @[Execute.scala 101:21]
  wire  lsu_io_mmu_lsu_valid; // @[Execute.scala 101:21]
  wire [63:0] lsu_io_mmu_lsu_bits_paddr; // @[Execute.scala 101:21]
  wire  lsu_io_mmu_lsu_bits_is_paging_fault; // @[Execute.scala 101:21]
  wire  lsu_io_mmu_lsu_bits_is_access_fault; // @[Execute.scala 101:21]
  wire  lsu_io_missUnit_dcache_acquire_ready; // @[Execute.scala 101:21]
  wire  lsu_io_missUnit_dcache_grant_valid; // @[Execute.scala 101:21]
  wire [2:0] lsu_io_missUnit_dcache_grant_bits_opcode; // @[Execute.scala 101:21]
  wire [2:0] lsu_io_missUnit_dcache_grant_bits_size; // @[Execute.scala 101:21]
  wire  lsu_io_missUnit_dcache_grant_bits_source; // @[Execute.scala 101:21]
  wire  lsu_io_missUnit_dcache_grantAck_ready; // @[Execute.scala 101:21]
  wire  lsu_io_probeUnit_dcache_probe_valid; // @[Execute.scala 101:21]
  wire [31:0] lsu_io_probeUnit_dcache_probe_bits_address; // @[Execute.scala 101:21]
  wire  lsu_io_writeBackUnit_dcache_release_ready; // @[Execute.scala 101:21]
  wire  lsu_io_writeBackUnit_dcache_grant_valid; // @[Execute.scala 101:21]
  wire  lsu_io_writeBackUnit_dcache_grant_bits_source; // @[Execute.scala 101:21]
  wire  lsu_io_system_getPut_ready; // @[Execute.scala 101:21]
  wire  lsu_io_system_access_valid; // @[Execute.scala 101:21]
  wire [2:0] lsu_io_system_access_bits_opcode; // @[Execute.scala 101:21]
  wire  lsu_io_periph_getPut_ready; // @[Execute.scala 101:21]
  wire  lsu_io_periph_access_valid; // @[Execute.scala 101:21]
  wire [2:0] lsu_io_periph_access_bits_opcode; // @[Execute.scala 101:21]
  wire  lsu_io_flush; // @[Execute.scala 101:21]
  wire  csr_clock; // @[Execute.scala 169:19]
  wire  csr_reset; // @[Execute.scala 169:19]
  wire  csr_io_csr_iss_exe_valid; // @[Execute.scala 169:19]
  wire  csr_io_csr_exe_iwb_ready; // @[Execute.scala 169:19]
  wire  csr_io_csr_data_valid; // @[Execute.scala 169:19]
  wire  csr_io_csr_cmm_op_ready; // @[Execute.scala 169:19]
  wire  csr_io_flush; // @[Execute.scala 169:19]
  wire  mulDiv_0_clock; // @[Execute.scala 170:76]
  wire  mulDiv_0_reset; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_valid; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_mul; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_mulh; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_mulhsu; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_mulhu; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_div; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_divu; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_rem; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_remu; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_mulw; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_divw; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_divuw; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_remw; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_iss_exe_bits_fun_remuw; // @[Execute.scala 170:76]
  wire [63:0] mulDiv_0_io_mul_iss_exe_bits_param_dat_op1; // @[Execute.scala 170:76]
  wire [63:0] mulDiv_0_io_mul_iss_exe_bits_param_dat_op2; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_mul_exe_iwb_ready; // @[Execute.scala 170:76]
  wire  mulDiv_0_io_flush; // @[Execute.scala 170:76]
  wire  fpu_0_clock; // @[Execute.scala 172:103]
  wire  fpu_0_reset; // @[Execute.scala 172:103]
  wire  fpu_0_io_fpu_iss_exe_valid; // @[Execute.scala 172:103]
  Alu alu_0 ( // @[Execute.scala 98:52]
    .clock(alu_0_clock),
    .reset(alu_0_reset),
    .io_alu_iss_exe_valid(alu_0_io_alu_iss_exe_valid),
    .io_alu_exe_iwb_ready(alu_0_io_alu_exe_iwb_ready),
    .io_flush(alu_0_io_flush)
  );
  Bru bru ( // @[Execute.scala 99:19]
    .clock(bru_clock),
    .reset(bru_reset),
    .io_bru_iss_exe_ready(bru_io_bru_iss_exe_ready),
    .io_bru_iss_exe_valid(bru_io_bru_iss_exe_valid),
    .io_bru_iss_exe_bits_fun_jalr(bru_io_bru_iss_exe_bits_fun_jalr),
    .io_bru_iss_exe_bits_fun_beq(bru_io_bru_iss_exe_bits_fun_beq),
    .io_bru_iss_exe_bits_fun_bne(bru_io_bru_iss_exe_bits_fun_bne),
    .io_bru_iss_exe_bits_fun_blt(bru_io_bru_iss_exe_bits_fun_blt),
    .io_bru_iss_exe_bits_fun_bge(bru_io_bru_iss_exe_bits_fun_bge),
    .io_bru_iss_exe_bits_fun_bltu(bru_io_bru_iss_exe_bits_fun_bltu),
    .io_bru_iss_exe_bits_fun_bgeu(bru_io_bru_iss_exe_bits_fun_bgeu),
    .io_bru_iss_exe_bits_param_imm(bru_io_bru_iss_exe_bits_param_imm),
    .io_bru_iss_exe_bits_param_dat_op1(bru_io_bru_iss_exe_bits_param_dat_op1),
    .io_bru_iss_exe_bits_param_dat_op2(bru_io_bru_iss_exe_bits_param_dat_op2),
    .io_bru_exe_iwb_ready(bru_io_bru_exe_iwb_ready),
    .io_bftq_ready(bru_io_bftq_ready),
    .io_bftq_valid(bru_io_bftq_valid),
    .io_bftq_bits_isPredictTaken(bru_io_bftq_bits_isPredictTaken),
    .io_jftq_ready(bru_io_jftq_ready),
    .io_jftq_valid(bru_io_jftq_valid),
    .io_jftq_bits_btbResp_target(bru_io_jftq_bits_btbResp_target),
    .io_jftq_bits_rasResp_target(bru_io_jftq_bits_rasResp_target),
    .io_jftq_bits_isRas(bru_io_jftq_bits_isRas),
    .io_bctq_ready(bru_io_bctq_ready),
    .io_jctq_ready(bru_io_jctq_ready),
    .io_flush(bru_io_flush)
  );
  Lsu lsu ( // @[Execute.scala 101:21]
    .clock(lsu_clock),
    .reset(lsu_reset),
    .io_lsu_iss_exe_valid(lsu_io_lsu_iss_exe_valid),
    .io_lsu_iss_exe_bits_fun_lb(lsu_io_lsu_iss_exe_bits_fun_lb),
    .io_lsu_iss_exe_bits_fun_lh(lsu_io_lsu_iss_exe_bits_fun_lh),
    .io_lsu_iss_exe_bits_fun_lw(lsu_io_lsu_iss_exe_bits_fun_lw),
    .io_lsu_iss_exe_bits_fun_ld(lsu_io_lsu_iss_exe_bits_fun_ld),
    .io_lsu_iss_exe_bits_fun_lbu(lsu_io_lsu_iss_exe_bits_fun_lbu),
    .io_lsu_iss_exe_bits_fun_lhu(lsu_io_lsu_iss_exe_bits_fun_lhu),
    .io_lsu_iss_exe_bits_fun_lwu(lsu_io_lsu_iss_exe_bits_fun_lwu),
    .io_lsu_iss_exe_bits_fun_sb(lsu_io_lsu_iss_exe_bits_fun_sb),
    .io_lsu_iss_exe_bits_fun_sh(lsu_io_lsu_iss_exe_bits_fun_sh),
    .io_lsu_iss_exe_bits_fun_sw(lsu_io_lsu_iss_exe_bits_fun_sw),
    .io_lsu_iss_exe_bits_fun_sd(lsu_io_lsu_iss_exe_bits_fun_sd),
    .io_lsu_iss_exe_bits_fun_fence(lsu_io_lsu_iss_exe_bits_fun_fence),
    .io_lsu_iss_exe_bits_fun_fence_i(lsu_io_lsu_iss_exe_bits_fun_fence_i),
    .io_lsu_iss_exe_bits_fun_sfence_vma(lsu_io_lsu_iss_exe_bits_fun_sfence_vma),
    .io_lsu_iss_exe_bits_fun_lr_w(lsu_io_lsu_iss_exe_bits_fun_lr_w),
    .io_lsu_iss_exe_bits_fun_sc_w(lsu_io_lsu_iss_exe_bits_fun_sc_w),
    .io_lsu_iss_exe_bits_fun_amoswap_w(lsu_io_lsu_iss_exe_bits_fun_amoswap_w),
    .io_lsu_iss_exe_bits_fun_amoadd_w(lsu_io_lsu_iss_exe_bits_fun_amoadd_w),
    .io_lsu_iss_exe_bits_fun_amoxor_w(lsu_io_lsu_iss_exe_bits_fun_amoxor_w),
    .io_lsu_iss_exe_bits_fun_amoand_w(lsu_io_lsu_iss_exe_bits_fun_amoand_w),
    .io_lsu_iss_exe_bits_fun_amoor_w(lsu_io_lsu_iss_exe_bits_fun_amoor_w),
    .io_lsu_iss_exe_bits_fun_amomin_w(lsu_io_lsu_iss_exe_bits_fun_amomin_w),
    .io_lsu_iss_exe_bits_fun_amomax_w(lsu_io_lsu_iss_exe_bits_fun_amomax_w),
    .io_lsu_iss_exe_bits_fun_amominu_w(lsu_io_lsu_iss_exe_bits_fun_amominu_w),
    .io_lsu_iss_exe_bits_fun_amomaxu_w(lsu_io_lsu_iss_exe_bits_fun_amomaxu_w),
    .io_lsu_iss_exe_bits_fun_lr_d(lsu_io_lsu_iss_exe_bits_fun_lr_d),
    .io_lsu_iss_exe_bits_fun_sc_d(lsu_io_lsu_iss_exe_bits_fun_sc_d),
    .io_lsu_iss_exe_bits_fun_amoswap_d(lsu_io_lsu_iss_exe_bits_fun_amoswap_d),
    .io_lsu_iss_exe_bits_fun_amoadd_d(lsu_io_lsu_iss_exe_bits_fun_amoadd_d),
    .io_lsu_iss_exe_bits_fun_amoxor_d(lsu_io_lsu_iss_exe_bits_fun_amoxor_d),
    .io_lsu_iss_exe_bits_fun_amoand_d(lsu_io_lsu_iss_exe_bits_fun_amoand_d),
    .io_lsu_iss_exe_bits_fun_amoor_d(lsu_io_lsu_iss_exe_bits_fun_amoor_d),
    .io_lsu_iss_exe_bits_fun_amomin_d(lsu_io_lsu_iss_exe_bits_fun_amomin_d),
    .io_lsu_iss_exe_bits_fun_amomax_d(lsu_io_lsu_iss_exe_bits_fun_amomax_d),
    .io_lsu_iss_exe_bits_fun_amominu_d(lsu_io_lsu_iss_exe_bits_fun_amominu_d),
    .io_lsu_iss_exe_bits_fun_amomaxu_d(lsu_io_lsu_iss_exe_bits_fun_amomaxu_d),
    .io_lsu_iss_exe_bits_fun_flw(lsu_io_lsu_iss_exe_bits_fun_flw),
    .io_lsu_iss_exe_bits_fun_fsw(lsu_io_lsu_iss_exe_bits_fun_fsw),
    .io_lsu_iss_exe_bits_fun_fld(lsu_io_lsu_iss_exe_bits_fun_fld),
    .io_lsu_iss_exe_bits_fun_fsd(lsu_io_lsu_iss_exe_bits_fun_fsd),
    .io_lsu_iss_exe_bits_param_dat_op1(lsu_io_lsu_iss_exe_bits_param_dat_op1),
    .io_lsu_exe_iwb_ready(lsu_io_lsu_exe_iwb_ready),
    .io_lsu_exe_fwb_ready(lsu_io_lsu_exe_fwb_ready),
    .io_cmm_lsu_is_amo_pending(lsu_io_cmm_lsu_is_amo_pending),
    .io_cmm_lsu_is_store_commit_0(lsu_io_cmm_lsu_is_store_commit_0),
    .io_mmu_lsu_valid(lsu_io_mmu_lsu_valid),
    .io_mmu_lsu_bits_paddr(lsu_io_mmu_lsu_bits_paddr),
    .io_mmu_lsu_bits_is_paging_fault(lsu_io_mmu_lsu_bits_is_paging_fault),
    .io_mmu_lsu_bits_is_access_fault(lsu_io_mmu_lsu_bits_is_access_fault),
    .io_missUnit_dcache_acquire_ready(lsu_io_missUnit_dcache_acquire_ready),
    .io_missUnit_dcache_grant_valid(lsu_io_missUnit_dcache_grant_valid),
    .io_missUnit_dcache_grant_bits_opcode(lsu_io_missUnit_dcache_grant_bits_opcode),
    .io_missUnit_dcache_grant_bits_size(lsu_io_missUnit_dcache_grant_bits_size),
    .io_missUnit_dcache_grant_bits_source(lsu_io_missUnit_dcache_grant_bits_source),
    .io_missUnit_dcache_grantAck_ready(lsu_io_missUnit_dcache_grantAck_ready),
    .io_probeUnit_dcache_probe_valid(lsu_io_probeUnit_dcache_probe_valid),
    .io_probeUnit_dcache_probe_bits_address(lsu_io_probeUnit_dcache_probe_bits_address),
    .io_writeBackUnit_dcache_release_ready(lsu_io_writeBackUnit_dcache_release_ready),
    .io_writeBackUnit_dcache_grant_valid(lsu_io_writeBackUnit_dcache_grant_valid),
    .io_writeBackUnit_dcache_grant_bits_source(lsu_io_writeBackUnit_dcache_grant_bits_source),
    .io_system_getPut_ready(lsu_io_system_getPut_ready),
    .io_system_access_valid(lsu_io_system_access_valid),
    .io_system_access_bits_opcode(lsu_io_system_access_bits_opcode),
    .io_periph_getPut_ready(lsu_io_periph_getPut_ready),
    .io_periph_access_valid(lsu_io_periph_access_valid),
    .io_periph_access_bits_opcode(lsu_io_periph_access_bits_opcode),
    .io_flush(lsu_io_flush)
  );
  Csr csr ( // @[Execute.scala 169:19]
    .clock(csr_clock),
    .reset(csr_reset),
    .io_csr_iss_exe_valid(csr_io_csr_iss_exe_valid),
    .io_csr_exe_iwb_ready(csr_io_csr_exe_iwb_ready),
    .io_csr_data_valid(csr_io_csr_data_valid),
    .io_csr_cmm_op_ready(csr_io_csr_cmm_op_ready),
    .io_flush(csr_io_flush)
  );
  MulDiv mulDiv_0 ( // @[Execute.scala 170:76]
    .clock(mulDiv_0_clock),
    .reset(mulDiv_0_reset),
    .io_mul_iss_exe_valid(mulDiv_0_io_mul_iss_exe_valid),
    .io_mul_iss_exe_bits_fun_mul(mulDiv_0_io_mul_iss_exe_bits_fun_mul),
    .io_mul_iss_exe_bits_fun_mulh(mulDiv_0_io_mul_iss_exe_bits_fun_mulh),
    .io_mul_iss_exe_bits_fun_mulhsu(mulDiv_0_io_mul_iss_exe_bits_fun_mulhsu),
    .io_mul_iss_exe_bits_fun_mulhu(mulDiv_0_io_mul_iss_exe_bits_fun_mulhu),
    .io_mul_iss_exe_bits_fun_div(mulDiv_0_io_mul_iss_exe_bits_fun_div),
    .io_mul_iss_exe_bits_fun_divu(mulDiv_0_io_mul_iss_exe_bits_fun_divu),
    .io_mul_iss_exe_bits_fun_rem(mulDiv_0_io_mul_iss_exe_bits_fun_rem),
    .io_mul_iss_exe_bits_fun_remu(mulDiv_0_io_mul_iss_exe_bits_fun_remu),
    .io_mul_iss_exe_bits_fun_mulw(mulDiv_0_io_mul_iss_exe_bits_fun_mulw),
    .io_mul_iss_exe_bits_fun_divw(mulDiv_0_io_mul_iss_exe_bits_fun_divw),
    .io_mul_iss_exe_bits_fun_divuw(mulDiv_0_io_mul_iss_exe_bits_fun_divuw),
    .io_mul_iss_exe_bits_fun_remw(mulDiv_0_io_mul_iss_exe_bits_fun_remw),
    .io_mul_iss_exe_bits_fun_remuw(mulDiv_0_io_mul_iss_exe_bits_fun_remuw),
    .io_mul_iss_exe_bits_param_dat_op1(mulDiv_0_io_mul_iss_exe_bits_param_dat_op1),
    .io_mul_iss_exe_bits_param_dat_op2(mulDiv_0_io_mul_iss_exe_bits_param_dat_op2),
    .io_mul_exe_iwb_ready(mulDiv_0_io_mul_exe_iwb_ready),
    .io_flush(mulDiv_0_io_flush)
  );
  FakeFAlu fpu_0 ( // @[Execute.scala 172:103]
    .clock(fpu_0_clock),
    .reset(fpu_0_reset),
    .io_fpu_iss_exe_valid(fpu_0_io_fpu_iss_exe_valid)
  );
  assign alu_0_clock = clock;
  assign alu_0_reset = reset;
  assign alu_0_io_alu_iss_exe_valid = io_alu_iss_exe_0_valid; // @[Execute.scala 185:27]
  assign alu_0_io_alu_exe_iwb_ready = io_alu_exe_iwb_0_ready; // @[Execute.scala 186:27]
  assign alu_0_io_flush = io_flush; // @[Execute.scala 187:21]
  assign bru_clock = clock;
  assign bru_reset = reset;
  assign bru_io_bru_iss_exe_valid = io_bru_iss_exe_valid; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_fun_jalr = io_bru_iss_exe_bits_fun_jalr; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_fun_beq = io_bru_iss_exe_bits_fun_beq; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_fun_bne = io_bru_iss_exe_bits_fun_bne; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_fun_blt = io_bru_iss_exe_bits_fun_blt; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_fun_bge = io_bru_iss_exe_bits_fun_bge; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_fun_bltu = io_bru_iss_exe_bits_fun_bltu; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_fun_bgeu = io_bru_iss_exe_bits_fun_bgeu; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_param_imm = io_bru_iss_exe_bits_param_imm; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_param_dat_op1 = io_bru_iss_exe_bits_param_dat_op1; // @[Execute.scala 191:22]
  assign bru_io_bru_iss_exe_bits_param_dat_op2 = io_bru_iss_exe_bits_param_dat_op2; // @[Execute.scala 191:22]
  assign bru_io_bru_exe_iwb_ready = io_bru_exe_iwb_ready; // @[Execute.scala 192:22]
  assign bru_io_bftq_valid = io_bftq_valid; // @[Execute.scala 195:15]
  assign bru_io_bftq_bits_isPredictTaken = io_bftq_bits_isPredictTaken; // @[Execute.scala 195:15]
  assign bru_io_jftq_valid = io_jftq_valid; // @[Execute.scala 196:15]
  assign bru_io_jftq_bits_btbResp_target = io_jftq_bits_btbResp_target; // @[Execute.scala 196:15]
  assign bru_io_jftq_bits_rasResp_target = io_jftq_bits_rasResp_target; // @[Execute.scala 196:15]
  assign bru_io_jftq_bits_isRas = io_jftq_bits_isRas; // @[Execute.scala 196:15]
  assign bru_io_bctq_ready = io_bctq_ready; // @[Execute.scala 198:11]
  assign bru_io_jctq_ready = io_jctq_ready; // @[Execute.scala 199:11]
  assign bru_io_flush = io_flush; // @[Execute.scala 193:16]
  assign lsu_clock = clock;
  assign lsu_reset = reset;
  assign lsu_io_lsu_iss_exe_valid = io_lsu_iss_exe_valid; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_lb = io_lsu_iss_exe_bits_fun_lb; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_lh = io_lsu_iss_exe_bits_fun_lh; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_lw = io_lsu_iss_exe_bits_fun_lw; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_ld = io_lsu_iss_exe_bits_fun_ld; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_lbu = io_lsu_iss_exe_bits_fun_lbu; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_lhu = io_lsu_iss_exe_bits_fun_lhu; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_lwu = io_lsu_iss_exe_bits_fun_lwu; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_sb = io_lsu_iss_exe_bits_fun_sb; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_sh = io_lsu_iss_exe_bits_fun_sh; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_sw = io_lsu_iss_exe_bits_fun_sw; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_sd = io_lsu_iss_exe_bits_fun_sd; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_fence = io_lsu_iss_exe_bits_fun_fence; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_fence_i = io_lsu_iss_exe_bits_fun_fence_i; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_sfence_vma = io_lsu_iss_exe_bits_fun_sfence_vma; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_lr_w = io_lsu_iss_exe_bits_fun_lr_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_sc_w = io_lsu_iss_exe_bits_fun_sc_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoswap_w = io_lsu_iss_exe_bits_fun_amoswap_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoadd_w = io_lsu_iss_exe_bits_fun_amoadd_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoxor_w = io_lsu_iss_exe_bits_fun_amoxor_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoand_w = io_lsu_iss_exe_bits_fun_amoand_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoor_w = io_lsu_iss_exe_bits_fun_amoor_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amomin_w = io_lsu_iss_exe_bits_fun_amomin_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amomax_w = io_lsu_iss_exe_bits_fun_amomax_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amominu_w = io_lsu_iss_exe_bits_fun_amominu_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amomaxu_w = io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_lr_d = io_lsu_iss_exe_bits_fun_lr_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_sc_d = io_lsu_iss_exe_bits_fun_sc_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoswap_d = io_lsu_iss_exe_bits_fun_amoswap_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoadd_d = io_lsu_iss_exe_bits_fun_amoadd_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoxor_d = io_lsu_iss_exe_bits_fun_amoxor_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoand_d = io_lsu_iss_exe_bits_fun_amoand_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amoor_d = io_lsu_iss_exe_bits_fun_amoor_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amomin_d = io_lsu_iss_exe_bits_fun_amomin_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amomax_d = io_lsu_iss_exe_bits_fun_amomax_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amominu_d = io_lsu_iss_exe_bits_fun_amominu_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_amomaxu_d = io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_flw = io_lsu_iss_exe_bits_fun_flw; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_fsw = io_lsu_iss_exe_bits_fun_fsw; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_fld = io_lsu_iss_exe_bits_fun_fld; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_fun_fsd = io_lsu_iss_exe_bits_fun_fsd; // @[Execute.scala 103:24]
  assign lsu_io_lsu_iss_exe_bits_param_dat_op1 = io_lsu_iss_exe_bits_param_dat_op1; // @[Execute.scala 103:24]
  assign lsu_io_lsu_exe_iwb_ready = io_lsu_exe_iwb_ready; // @[Execute.scala 104:24]
  assign lsu_io_lsu_exe_fwb_ready = io_lsu_exe_fwb_ready; // @[Execute.scala 105:24]
  assign lsu_io_cmm_lsu_is_amo_pending = io_cmm_lsu_is_amo_pending; // @[Execute.scala 110:20]
  assign lsu_io_cmm_lsu_is_store_commit_0 = io_cmm_lsu_is_store_commit_0; // @[Execute.scala 110:20]
  assign lsu_io_mmu_lsu_valid = io_mmu_lsu_valid; // @[Execute.scala 108:20]
  assign lsu_io_mmu_lsu_bits_paddr = io_mmu_lsu_bits_paddr; // @[Execute.scala 108:20]
  assign lsu_io_mmu_lsu_bits_is_paging_fault = io_mmu_lsu_bits_is_paging_fault; // @[Execute.scala 108:20]
  assign lsu_io_mmu_lsu_bits_is_access_fault = io_mmu_lsu_bits_is_access_fault; // @[Execute.scala 108:20]
  assign lsu_io_missUnit_dcache_acquire_ready = io_missUnit_dcache_acquire_ready; // @[Execute.scala 116:46]
  assign lsu_io_missUnit_dcache_grant_valid = io_missUnit_dcache_grant_valid; // @[Execute.scala 118:44]
  assign lsu_io_missUnit_dcache_grant_bits_opcode = io_missUnit_dcache_grant_bits_opcode; // @[Execute.scala 119:44]
  assign lsu_io_missUnit_dcache_grant_bits_size = io_missUnit_dcache_grant_bits_size; // @[Execute.scala 119:44]
  assign lsu_io_missUnit_dcache_grant_bits_source = io_missUnit_dcache_grant_bits_source; // @[Execute.scala 119:44]
  assign lsu_io_missUnit_dcache_grantAck_ready = io_missUnit_dcache_grantAck_ready; // @[Execute.scala 124:47]
  assign lsu_io_probeUnit_dcache_probe_valid = io_probeUnit_dcache_probe_valid; // @[Execute.scala 126:45]
  assign lsu_io_probeUnit_dcache_probe_bits_address = io_probeUnit_dcache_probe_bits_address; // @[Execute.scala 127:44]
  assign lsu_io_writeBackUnit_dcache_release_ready = io_writeBackUnit_dcache_release_ready; // @[Execute.scala 132:51]
  assign lsu_io_writeBackUnit_dcache_grant_valid = io_writeBackUnit_dcache_grant_valid; // @[Execute.scala 134:49]
  assign lsu_io_writeBackUnit_dcache_grant_bits_source = io_writeBackUnit_dcache_grant_bits_source; // @[Execute.scala 135:48]
  assign lsu_io_system_getPut_ready = io_system_getPut_ready; // @[Execute.scala 151:32]
  assign lsu_io_system_access_valid = io_system_access_valid; // @[Execute.scala 152:32]
  assign lsu_io_system_access_bits_opcode = io_system_access_bits_opcode; // @[Execute.scala 153:31]
  assign lsu_io_periph_getPut_ready = io_periph_getPut_ready; // @[Execute.scala 158:32]
  assign lsu_io_periph_access_valid = io_periph_access_valid; // @[Execute.scala 159:32]
  assign lsu_io_periph_access_bits_opcode = io_periph_access_bits_opcode; // @[Execute.scala 160:31]
  assign lsu_io_flush = io_flush; // @[Execute.scala 165:18]
  assign csr_clock = clock;
  assign csr_reset = reset;
  assign csr_io_csr_iss_exe_valid = io_csr_iss_exe_valid; // @[Execute.scala 204:22]
  assign csr_io_csr_exe_iwb_ready = io_csr_exe_iwb_ready; // @[Execute.scala 205:22]
  assign csr_io_csr_data_valid = io_csr_data_valid; // @[Execute.scala 207:19]
  assign csr_io_csr_cmm_op_ready = io_csr_cmm_op_ready; // @[Execute.scala 208:21]
  assign csr_io_flush = io_flush; // @[Execute.scala 209:16]
  assign mulDiv_0_clock = clock;
  assign mulDiv_0_reset = reset;
  assign mulDiv_0_io_mul_iss_exe_valid = io_mul_iss_exe_0_valid; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_mul = io_mul_iss_exe_0_bits_fun_mul; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_mulh = io_mul_iss_exe_0_bits_fun_mulh; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_mulhsu = io_mul_iss_exe_0_bits_fun_mulhsu; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_mulhu = io_mul_iss_exe_0_bits_fun_mulhu; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_div = io_mul_iss_exe_0_bits_fun_div; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_divu = io_mul_iss_exe_0_bits_fun_divu; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_rem = io_mul_iss_exe_0_bits_fun_rem; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_remu = io_mul_iss_exe_0_bits_fun_remu; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_mulw = io_mul_iss_exe_0_bits_fun_mulw; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_divw = io_mul_iss_exe_0_bits_fun_divw; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_divuw = io_mul_iss_exe_0_bits_fun_divuw; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_remw = io_mul_iss_exe_0_bits_fun_remw; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_fun_remuw = io_mul_iss_exe_0_bits_fun_remuw; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_param_dat_op1 = io_mul_iss_exe_0_bits_param_dat_op1; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_iss_exe_bits_param_dat_op2 = io_mul_iss_exe_0_bits_param_dat_op2; // @[Execute.scala 212:30]
  assign mulDiv_0_io_mul_exe_iwb_ready = io_mul_exe_iwb_0_ready; // @[Execute.scala 213:30]
  assign mulDiv_0_io_flush = io_flush; // @[Execute.scala 214:24]
  assign fpu_0_clock = clock;
  assign fpu_0_reset = reset;
  assign fpu_0_io_fpu_iss_exe_valid = io_fpu_iss_exe_0_valid; // @[Execute.scala 176:27]
endmodule
module XRegFiles(
  input        clock,
  input        reset,
  output       io_rename_0_req_ready,
  input        io_rename_0_req_valid,
  input        io_rgReq_0_valid,
  input  [5:0] io_rgReq_0_bits,
  output       io_rgRsp_0_valid,
  output       io_exe_writeBack_0_ready,
  input        io_exe_writeBack_0_valid,
  input  [5:0] io_exe_writeBack_0_bits_rd0,
  input        io_commit_0_is_comfirm,
  input        io_commit_0_is_MisPredict,
  input        io_commit_0_is_abort,
  input  [4:0] io_commit_0_raw,
  input  [5:0] io_commit_0_phy,
  output       io_commit_0_is_writeback
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] log_reg_0; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_1; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_2; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_3; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_4; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_5; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_6; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_7; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_8; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_9; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_10; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_11; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_12; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_13; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_14; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_15; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_16; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_17; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_18; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_19; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_20; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_21; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_22; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_23; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_24; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_25; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_26; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_27; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_28; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_29; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_30; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_31; // @[Regfiles.scala 101:12]
  reg [1:0] log_reg_32; // @[Regfiles.scala 101:12]
  reg [5:0] archit_ptr_0; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_1; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_2; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_3; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_4; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_5; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_6; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_7; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_8; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_9; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_10; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_11; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_12; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_13; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_14; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_15; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_16; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_17; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_18; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_19; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_20; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_21; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_22; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_23; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_24; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_25; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_26; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_27; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_28; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_29; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_30; // @[Regfiles.scala 130:27]
  reg [5:0] archit_ptr_31; // @[Regfiles.scala 130:27]
  wire  _T_1 = log_reg_32 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1089 = log_reg_32 == 2'h0 ? 6'h20 : 6'h0; // @[Regfiles.scala 150:{46,62}]
  wire  _T_2 = log_reg_31 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1090 = log_reg_31 == 2'h0 ? 6'h1f : _GEN_1089; // @[Regfiles.scala 150:{46,62}]
  wire  _T_3 = log_reg_30 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1091 = log_reg_30 == 2'h0 ? 6'h1e : _GEN_1090; // @[Regfiles.scala 150:{46,62}]
  wire  _T_4 = log_reg_29 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1092 = log_reg_29 == 2'h0 ? 6'h1d : _GEN_1091; // @[Regfiles.scala 150:{46,62}]
  wire  _T_5 = log_reg_28 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1093 = log_reg_28 == 2'h0 ? 6'h1c : _GEN_1092; // @[Regfiles.scala 150:{46,62}]
  wire  _T_6 = log_reg_27 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1094 = log_reg_27 == 2'h0 ? 6'h1b : _GEN_1093; // @[Regfiles.scala 150:{46,62}]
  wire  _T_7 = log_reg_26 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1095 = log_reg_26 == 2'h0 ? 6'h1a : _GEN_1094; // @[Regfiles.scala 150:{46,62}]
  wire  _T_8 = log_reg_25 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1096 = log_reg_25 == 2'h0 ? 6'h19 : _GEN_1095; // @[Regfiles.scala 150:{46,62}]
  wire  _T_9 = log_reg_24 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1097 = log_reg_24 == 2'h0 ? 6'h18 : _GEN_1096; // @[Regfiles.scala 150:{46,62}]
  wire  _T_10 = log_reg_23 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1098 = log_reg_23 == 2'h0 ? 6'h17 : _GEN_1097; // @[Regfiles.scala 150:{46,62}]
  wire  _T_11 = log_reg_22 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1099 = log_reg_22 == 2'h0 ? 6'h16 : _GEN_1098; // @[Regfiles.scala 150:{46,62}]
  wire  _T_12 = log_reg_21 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1100 = log_reg_21 == 2'h0 ? 6'h15 : _GEN_1099; // @[Regfiles.scala 150:{46,62}]
  wire  _T_13 = log_reg_20 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1101 = log_reg_20 == 2'h0 ? 6'h14 : _GEN_1100; // @[Regfiles.scala 150:{46,62}]
  wire  _T_14 = log_reg_19 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1102 = log_reg_19 == 2'h0 ? 6'h13 : _GEN_1101; // @[Regfiles.scala 150:{46,62}]
  wire  _T_15 = log_reg_18 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1103 = log_reg_18 == 2'h0 ? 6'h12 : _GEN_1102; // @[Regfiles.scala 150:{46,62}]
  wire  _T_16 = log_reg_17 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1104 = log_reg_17 == 2'h0 ? 6'h11 : _GEN_1103; // @[Regfiles.scala 150:{46,62}]
  wire  _T_17 = log_reg_16 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1105 = log_reg_16 == 2'h0 ? 6'h10 : _GEN_1104; // @[Regfiles.scala 150:{46,62}]
  wire  _T_18 = log_reg_15 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1106 = log_reg_15 == 2'h0 ? 6'hf : _GEN_1105; // @[Regfiles.scala 150:{46,62}]
  wire  _T_19 = log_reg_14 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1107 = log_reg_14 == 2'h0 ? 6'he : _GEN_1106; // @[Regfiles.scala 150:{46,62}]
  wire  _T_20 = log_reg_13 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1108 = log_reg_13 == 2'h0 ? 6'hd : _GEN_1107; // @[Regfiles.scala 150:{46,62}]
  wire  _T_21 = log_reg_12 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1109 = log_reg_12 == 2'h0 ? 6'hc : _GEN_1108; // @[Regfiles.scala 150:{46,62}]
  wire  _T_22 = log_reg_11 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1110 = log_reg_11 == 2'h0 ? 6'hb : _GEN_1109; // @[Regfiles.scala 150:{46,62}]
  wire  _T_23 = log_reg_10 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1111 = log_reg_10 == 2'h0 ? 6'ha : _GEN_1110; // @[Regfiles.scala 150:{46,62}]
  wire  _T_24 = log_reg_9 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1112 = log_reg_9 == 2'h0 ? 6'h9 : _GEN_1111; // @[Regfiles.scala 150:{46,62}]
  wire  _T_25 = log_reg_8 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1113 = log_reg_8 == 2'h0 ? 6'h8 : _GEN_1112; // @[Regfiles.scala 150:{46,62}]
  wire  _T_26 = log_reg_7 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1114 = log_reg_7 == 2'h0 ? 6'h7 : _GEN_1113; // @[Regfiles.scala 150:{46,62}]
  wire  _T_27 = log_reg_6 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1115 = log_reg_6 == 2'h0 ? 6'h6 : _GEN_1114; // @[Regfiles.scala 150:{46,62}]
  wire  _T_28 = log_reg_5 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1116 = log_reg_5 == 2'h0 ? 6'h5 : _GEN_1115; // @[Regfiles.scala 150:{46,62}]
  wire  _T_29 = log_reg_4 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1117 = log_reg_4 == 2'h0 ? 6'h4 : _GEN_1116; // @[Regfiles.scala 150:{46,62}]
  wire  _T_30 = log_reg_3 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1118 = log_reg_3 == 2'h0 ? 6'h3 : _GEN_1117; // @[Regfiles.scala 150:{46,62}]
  wire  _T_31 = log_reg_2 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1119 = log_reg_2 == 2'h0 ? 6'h2 : _GEN_1118; // @[Regfiles.scala 150:{46,62}]
  wire  _T_32 = log_reg_1 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] _GEN_1120 = log_reg_1 == 2'h0 ? 6'h1 : _GEN_1119; // @[Regfiles.scala 150:{46,62}]
  wire  _T_33 = log_reg_0 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] molloc_idx_0 = log_reg_0 == 2'h0 ? 6'h0 : _GEN_1120; // @[Regfiles.scala 150:{46,62}]
  wire  _T_34 = io_rename_0_req_ready & io_rename_0_req_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _GEN_1123 = 6'h1 == molloc_idx_0 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1124 = 6'h2 == molloc_idx_0 ? log_reg_2 : _GEN_1123; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1125 = 6'h3 == molloc_idx_0 ? log_reg_3 : _GEN_1124; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1126 = 6'h4 == molloc_idx_0 ? log_reg_4 : _GEN_1125; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1127 = 6'h5 == molloc_idx_0 ? log_reg_5 : _GEN_1126; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1128 = 6'h6 == molloc_idx_0 ? log_reg_6 : _GEN_1127; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1129 = 6'h7 == molloc_idx_0 ? log_reg_7 : _GEN_1128; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1130 = 6'h8 == molloc_idx_0 ? log_reg_8 : _GEN_1129; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1131 = 6'h9 == molloc_idx_0 ? log_reg_9 : _GEN_1130; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1132 = 6'ha == molloc_idx_0 ? log_reg_10 : _GEN_1131; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1133 = 6'hb == molloc_idx_0 ? log_reg_11 : _GEN_1132; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1134 = 6'hc == molloc_idx_0 ? log_reg_12 : _GEN_1133; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1135 = 6'hd == molloc_idx_0 ? log_reg_13 : _GEN_1134; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1136 = 6'he == molloc_idx_0 ? log_reg_14 : _GEN_1135; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1137 = 6'hf == molloc_idx_0 ? log_reg_15 : _GEN_1136; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1138 = 6'h10 == molloc_idx_0 ? log_reg_16 : _GEN_1137; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1139 = 6'h11 == molloc_idx_0 ? log_reg_17 : _GEN_1138; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1140 = 6'h12 == molloc_idx_0 ? log_reg_18 : _GEN_1139; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1141 = 6'h13 == molloc_idx_0 ? log_reg_19 : _GEN_1140; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1142 = 6'h14 == molloc_idx_0 ? log_reg_20 : _GEN_1141; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1143 = 6'h15 == molloc_idx_0 ? log_reg_21 : _GEN_1142; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1144 = 6'h16 == molloc_idx_0 ? log_reg_22 : _GEN_1143; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1145 = 6'h17 == molloc_idx_0 ? log_reg_23 : _GEN_1144; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1146 = 6'h18 == molloc_idx_0 ? log_reg_24 : _GEN_1145; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1147 = 6'h19 == molloc_idx_0 ? log_reg_25 : _GEN_1146; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1148 = 6'h1a == molloc_idx_0 ? log_reg_26 : _GEN_1147; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1149 = 6'h1b == molloc_idx_0 ? log_reg_27 : _GEN_1148; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1150 = 6'h1c == molloc_idx_0 ? log_reg_28 : _GEN_1149; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1151 = 6'h1d == molloc_idx_0 ? log_reg_29 : _GEN_1150; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1152 = 6'h1e == molloc_idx_0 ? log_reg_30 : _GEN_1151; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1153 = 6'h1f == molloc_idx_0 ? log_reg_31 : _GEN_1152; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1154 = 6'h20 == molloc_idx_0 ? log_reg_32 : _GEN_1153; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] _GEN_1155 = 6'h21 == molloc_idx_0 ? 2'h3 : _GEN_1154; // @[Regfiles.scala 160:{34,34}]
  wire  _T_37 = ~reset; // @[Regfiles.scala 160:13]
  wire [1:0] _GEN_1156 = 6'h0 == molloc_idx_0 ? 2'h1 : log_reg_0; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1157 = 6'h1 == molloc_idx_0 ? 2'h1 : log_reg_1; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1158 = 6'h2 == molloc_idx_0 ? 2'h1 : log_reg_2; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1159 = 6'h3 == molloc_idx_0 ? 2'h1 : log_reg_3; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1160 = 6'h4 == molloc_idx_0 ? 2'h1 : log_reg_4; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1161 = 6'h5 == molloc_idx_0 ? 2'h1 : log_reg_5; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1162 = 6'h6 == molloc_idx_0 ? 2'h1 : log_reg_6; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1163 = 6'h7 == molloc_idx_0 ? 2'h1 : log_reg_7; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1164 = 6'h8 == molloc_idx_0 ? 2'h1 : log_reg_8; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1165 = 6'h9 == molloc_idx_0 ? 2'h1 : log_reg_9; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1166 = 6'ha == molloc_idx_0 ? 2'h1 : log_reg_10; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1167 = 6'hb == molloc_idx_0 ? 2'h1 : log_reg_11; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1168 = 6'hc == molloc_idx_0 ? 2'h1 : log_reg_12; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1169 = 6'hd == molloc_idx_0 ? 2'h1 : log_reg_13; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1170 = 6'he == molloc_idx_0 ? 2'h1 : log_reg_14; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1171 = 6'hf == molloc_idx_0 ? 2'h1 : log_reg_15; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1172 = 6'h10 == molloc_idx_0 ? 2'h1 : log_reg_16; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1173 = 6'h11 == molloc_idx_0 ? 2'h1 : log_reg_17; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1174 = 6'h12 == molloc_idx_0 ? 2'h1 : log_reg_18; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1175 = 6'h13 == molloc_idx_0 ? 2'h1 : log_reg_19; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1176 = 6'h14 == molloc_idx_0 ? 2'h1 : log_reg_20; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1177 = 6'h15 == molloc_idx_0 ? 2'h1 : log_reg_21; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1178 = 6'h16 == molloc_idx_0 ? 2'h1 : log_reg_22; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1179 = 6'h17 == molloc_idx_0 ? 2'h1 : log_reg_23; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1180 = 6'h18 == molloc_idx_0 ? 2'h1 : log_reg_24; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1181 = 6'h19 == molloc_idx_0 ? 2'h1 : log_reg_25; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1182 = 6'h1a == molloc_idx_0 ? 2'h1 : log_reg_26; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1183 = 6'h1b == molloc_idx_0 ? 2'h1 : log_reg_27; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1184 = 6'h1c == molloc_idx_0 ? 2'h1 : log_reg_28; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1185 = 6'h1d == molloc_idx_0 ? 2'h1 : log_reg_29; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1186 = 6'h1e == molloc_idx_0 ? 2'h1 : log_reg_30; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1187 = 6'h1f == molloc_idx_0 ? 2'h1 : log_reg_31; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1188 = 6'h20 == molloc_idx_0 ? 2'h1 : log_reg_32; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] _GEN_1221 = _T_34 ? _GEN_1156 : log_reg_0; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1222 = _T_34 ? _GEN_1157 : log_reg_1; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1223 = _T_34 ? _GEN_1158 : log_reg_2; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1224 = _T_34 ? _GEN_1159 : log_reg_3; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1225 = _T_34 ? _GEN_1160 : log_reg_4; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1226 = _T_34 ? _GEN_1161 : log_reg_5; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1227 = _T_34 ? _GEN_1162 : log_reg_6; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1228 = _T_34 ? _GEN_1163 : log_reg_7; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1229 = _T_34 ? _GEN_1164 : log_reg_8; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1230 = _T_34 ? _GEN_1165 : log_reg_9; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1231 = _T_34 ? _GEN_1166 : log_reg_10; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1232 = _T_34 ? _GEN_1167 : log_reg_11; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1233 = _T_34 ? _GEN_1168 : log_reg_12; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1234 = _T_34 ? _GEN_1169 : log_reg_13; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1235 = _T_34 ? _GEN_1170 : log_reg_14; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1236 = _T_34 ? _GEN_1171 : log_reg_15; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1237 = _T_34 ? _GEN_1172 : log_reg_16; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1238 = _T_34 ? _GEN_1173 : log_reg_17; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1239 = _T_34 ? _GEN_1174 : log_reg_18; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1240 = _T_34 ? _GEN_1175 : log_reg_19; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1241 = _T_34 ? _GEN_1176 : log_reg_20; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1242 = _T_34 ? _GEN_1177 : log_reg_21; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1243 = _T_34 ? _GEN_1178 : log_reg_22; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1244 = _T_34 ? _GEN_1179 : log_reg_23; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1245 = _T_34 ? _GEN_1180 : log_reg_24; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1246 = _T_34 ? _GEN_1181 : log_reg_25; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1247 = _T_34 ? _GEN_1182 : log_reg_26; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1248 = _T_34 ? _GEN_1183 : log_reg_27; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1249 = _T_34 ? _GEN_1184 : log_reg_28; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1250 = _T_34 ? _GEN_1185 : log_reg_29; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1251 = _T_34 ? _GEN_1186 : log_reg_30; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1252 = _T_34 ? _GEN_1187 : log_reg_31; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _GEN_1253 = _T_34 ? _GEN_1188 : log_reg_32; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] _io_rename_0_req_ready_T_34 = _T_33 + _T_32; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_36 = _T_31 + _T_30; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_38 = _io_rename_0_req_ready_T_34 + _io_rename_0_req_ready_T_36; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_40 = _T_29 + _T_28; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_42 = _T_27 + _T_26; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_44 = _io_rename_0_req_ready_T_40 + _io_rename_0_req_ready_T_42; // @[Regfiles.scala 165:40]
  wire [3:0] _io_rename_0_req_ready_T_46 = _io_rename_0_req_ready_T_38 + _io_rename_0_req_ready_T_44; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_48 = _T_25 + _T_24; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_50 = _T_23 + _T_22; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_52 = _io_rename_0_req_ready_T_48 + _io_rename_0_req_ready_T_50; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_54 = _T_21 + _T_20; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_56 = _T_18 + _T_17; // @[Regfiles.scala 165:40]
  wire [1:0] _GEN_0 = {{1'd0}, _T_19}; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_58 = _GEN_0 + _io_rename_0_req_ready_T_56; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_60 = _io_rename_0_req_ready_T_54 + _io_rename_0_req_ready_T_58[1:0]; // @[Regfiles.scala 165:40]
  wire [3:0] _io_rename_0_req_ready_T_62 = _io_rename_0_req_ready_T_52 + _io_rename_0_req_ready_T_60; // @[Regfiles.scala 165:40]
  wire [4:0] _io_rename_0_req_ready_T_64 = _io_rename_0_req_ready_T_46 + _io_rename_0_req_ready_T_62; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_66 = _T_16 + _T_15; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_68 = _T_14 + _T_13; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_70 = _io_rename_0_req_ready_T_66 + _io_rename_0_req_ready_T_68; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_72 = _T_12 + _T_11; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_74 = _T_10 + _T_9; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_76 = _io_rename_0_req_ready_T_72 + _io_rename_0_req_ready_T_74; // @[Regfiles.scala 165:40]
  wire [3:0] _io_rename_0_req_ready_T_78 = _io_rename_0_req_ready_T_70 + _io_rename_0_req_ready_T_76; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_80 = _T_8 + _T_7; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_82 = _T_6 + _T_5; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_84 = _io_rename_0_req_ready_T_80 + _io_rename_0_req_ready_T_82; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_86 = _T_4 + _T_3; // @[Regfiles.scala 165:40]
  wire [1:0] _io_rename_0_req_ready_T_88 = {{1'd0}, _T_1}; // @[Regfiles.scala 165:40]
  wire [1:0] _GEN_1 = {{1'd0}, _T_2}; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_90 = _GEN_1 + _io_rename_0_req_ready_T_88; // @[Regfiles.scala 165:40]
  wire [2:0] _io_rename_0_req_ready_T_92 = _io_rename_0_req_ready_T_86 + _io_rename_0_req_ready_T_90[1:0]; // @[Regfiles.scala 165:40]
  wire [3:0] _io_rename_0_req_ready_T_94 = _io_rename_0_req_ready_T_84 + _io_rename_0_req_ready_T_92; // @[Regfiles.scala 165:40]
  wire [4:0] _io_rename_0_req_ready_T_96 = _io_rename_0_req_ready_T_78 + _io_rename_0_req_ready_T_94; // @[Regfiles.scala 165:40]
  wire [5:0] _io_rename_0_req_ready_T_98 = _io_rename_0_req_ready_T_64 + _io_rename_0_req_ready_T_96; // @[Regfiles.scala 165:40]
  reg  io_rgRsp_0_valid_REG; // @[Regfiles.scala 191:36]
  wire [1:0] _GEN_1387 = 6'h1 == io_rgReq_0_bits ? log_reg_1 : log_reg_0; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1388 = 6'h2 == io_rgReq_0_bits ? log_reg_2 : _GEN_1387; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1389 = 6'h3 == io_rgReq_0_bits ? log_reg_3 : _GEN_1388; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1390 = 6'h4 == io_rgReq_0_bits ? log_reg_4 : _GEN_1389; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1391 = 6'h5 == io_rgReq_0_bits ? log_reg_5 : _GEN_1390; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1392 = 6'h6 == io_rgReq_0_bits ? log_reg_6 : _GEN_1391; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1393 = 6'h7 == io_rgReq_0_bits ? log_reg_7 : _GEN_1392; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1394 = 6'h8 == io_rgReq_0_bits ? log_reg_8 : _GEN_1393; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1395 = 6'h9 == io_rgReq_0_bits ? log_reg_9 : _GEN_1394; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1396 = 6'ha == io_rgReq_0_bits ? log_reg_10 : _GEN_1395; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1397 = 6'hb == io_rgReq_0_bits ? log_reg_11 : _GEN_1396; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1398 = 6'hc == io_rgReq_0_bits ? log_reg_12 : _GEN_1397; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1399 = 6'hd == io_rgReq_0_bits ? log_reg_13 : _GEN_1398; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1400 = 6'he == io_rgReq_0_bits ? log_reg_14 : _GEN_1399; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1401 = 6'hf == io_rgReq_0_bits ? log_reg_15 : _GEN_1400; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1402 = 6'h10 == io_rgReq_0_bits ? log_reg_16 : _GEN_1401; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1403 = 6'h11 == io_rgReq_0_bits ? log_reg_17 : _GEN_1402; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1404 = 6'h12 == io_rgReq_0_bits ? log_reg_18 : _GEN_1403; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1405 = 6'h13 == io_rgReq_0_bits ? log_reg_19 : _GEN_1404; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1406 = 6'h14 == io_rgReq_0_bits ? log_reg_20 : _GEN_1405; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1407 = 6'h15 == io_rgReq_0_bits ? log_reg_21 : _GEN_1406; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1408 = 6'h16 == io_rgReq_0_bits ? log_reg_22 : _GEN_1407; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1409 = 6'h17 == io_rgReq_0_bits ? log_reg_23 : _GEN_1408; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1410 = 6'h18 == io_rgReq_0_bits ? log_reg_24 : _GEN_1409; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1411 = 6'h19 == io_rgReq_0_bits ? log_reg_25 : _GEN_1410; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1412 = 6'h1a == io_rgReq_0_bits ? log_reg_26 : _GEN_1411; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1413 = 6'h1b == io_rgReq_0_bits ? log_reg_27 : _GEN_1412; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1414 = 6'h1c == io_rgReq_0_bits ? log_reg_28 : _GEN_1413; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1415 = 6'h1d == io_rgReq_0_bits ? log_reg_29 : _GEN_1414; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1416 = 6'h1e == io_rgReq_0_bits ? log_reg_30 : _GEN_1415; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1417 = 6'h1f == io_rgReq_0_bits ? log_reg_31 : _GEN_1416; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1418 = 6'h20 == io_rgReq_0_bits ? log_reg_32 : _GEN_1417; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] _GEN_1419 = 6'h21 == io_rgReq_0_bits ? 2'h3 : _GEN_1418; // @[Regfiles.scala 194:{64,64}]
  wire  _T_108 = io_exe_writeBack_0_ready & io_exe_writeBack_0_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _GEN_1421 = 6'h1 == io_exe_writeBack_0_bits_rd0 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1422 = 6'h2 == io_exe_writeBack_0_bits_rd0 ? log_reg_2 : _GEN_1421; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1423 = 6'h3 == io_exe_writeBack_0_bits_rd0 ? log_reg_3 : _GEN_1422; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1424 = 6'h4 == io_exe_writeBack_0_bits_rd0 ? log_reg_4 : _GEN_1423; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1425 = 6'h5 == io_exe_writeBack_0_bits_rd0 ? log_reg_5 : _GEN_1424; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1426 = 6'h6 == io_exe_writeBack_0_bits_rd0 ? log_reg_6 : _GEN_1425; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1427 = 6'h7 == io_exe_writeBack_0_bits_rd0 ? log_reg_7 : _GEN_1426; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1428 = 6'h8 == io_exe_writeBack_0_bits_rd0 ? log_reg_8 : _GEN_1427; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1429 = 6'h9 == io_exe_writeBack_0_bits_rd0 ? log_reg_9 : _GEN_1428; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1430 = 6'ha == io_exe_writeBack_0_bits_rd0 ? log_reg_10 : _GEN_1429; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1431 = 6'hb == io_exe_writeBack_0_bits_rd0 ? log_reg_11 : _GEN_1430; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1432 = 6'hc == io_exe_writeBack_0_bits_rd0 ? log_reg_12 : _GEN_1431; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1433 = 6'hd == io_exe_writeBack_0_bits_rd0 ? log_reg_13 : _GEN_1432; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1434 = 6'he == io_exe_writeBack_0_bits_rd0 ? log_reg_14 : _GEN_1433; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1435 = 6'hf == io_exe_writeBack_0_bits_rd0 ? log_reg_15 : _GEN_1434; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1436 = 6'h10 == io_exe_writeBack_0_bits_rd0 ? log_reg_16 : _GEN_1435; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1437 = 6'h11 == io_exe_writeBack_0_bits_rd0 ? log_reg_17 : _GEN_1436; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1438 = 6'h12 == io_exe_writeBack_0_bits_rd0 ? log_reg_18 : _GEN_1437; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1439 = 6'h13 == io_exe_writeBack_0_bits_rd0 ? log_reg_19 : _GEN_1438; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1440 = 6'h14 == io_exe_writeBack_0_bits_rd0 ? log_reg_20 : _GEN_1439; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1441 = 6'h15 == io_exe_writeBack_0_bits_rd0 ? log_reg_21 : _GEN_1440; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1442 = 6'h16 == io_exe_writeBack_0_bits_rd0 ? log_reg_22 : _GEN_1441; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1443 = 6'h17 == io_exe_writeBack_0_bits_rd0 ? log_reg_23 : _GEN_1442; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1444 = 6'h18 == io_exe_writeBack_0_bits_rd0 ? log_reg_24 : _GEN_1443; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1445 = 6'h19 == io_exe_writeBack_0_bits_rd0 ? log_reg_25 : _GEN_1444; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1446 = 6'h1a == io_exe_writeBack_0_bits_rd0 ? log_reg_26 : _GEN_1445; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1447 = 6'h1b == io_exe_writeBack_0_bits_rd0 ? log_reg_27 : _GEN_1446; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1448 = 6'h1c == io_exe_writeBack_0_bits_rd0 ? log_reg_28 : _GEN_1447; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1449 = 6'h1d == io_exe_writeBack_0_bits_rd0 ? log_reg_29 : _GEN_1448; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1450 = 6'h1e == io_exe_writeBack_0_bits_rd0 ? log_reg_30 : _GEN_1449; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1451 = 6'h1f == io_exe_writeBack_0_bits_rd0 ? log_reg_31 : _GEN_1450; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1452 = 6'h20 == io_exe_writeBack_0_bits_rd0 ? log_reg_32 : _GEN_1451; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1453 = 6'h21 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1452; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] _GEN_1454 = 6'h0 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1221; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1455 = 6'h1 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1222; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1456 = 6'h2 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1223; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1457 = 6'h3 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1224; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1458 = 6'h4 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1225; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1459 = 6'h5 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1226; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1460 = 6'h6 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1227; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1461 = 6'h7 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1228; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1462 = 6'h8 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1229; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1463 = 6'h9 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1230; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1464 = 6'ha == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1231; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1465 = 6'hb == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1232; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1466 = 6'hc == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1233; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1467 = 6'hd == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1234; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1468 = 6'he == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1235; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1469 = 6'hf == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1236; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1470 = 6'h10 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1237; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1471 = 6'h11 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1238; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1472 = 6'h12 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1239; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1473 = 6'h13 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1240; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1474 = 6'h14 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1241; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1475 = 6'h15 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1242; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1476 = 6'h16 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1243; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1477 = 6'h17 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1244; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1478 = 6'h18 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1245; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1479 = 6'h19 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1246; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1480 = 6'h1a == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1247; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1481 = 6'h1b == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1248; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1482 = 6'h1c == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1249; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1483 = 6'h1d == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1250; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1484 = 6'h1e == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1251; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1485 = 6'h1f == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1252; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1486 = 6'h20 == io_exe_writeBack_0_bits_rd0 ? 2'h3 : _GEN_1253; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] _GEN_1520 = _T_108 ? _GEN_1454 : _GEN_1221; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1521 = _T_108 ? _GEN_1455 : _GEN_1222; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1522 = _T_108 ? _GEN_1456 : _GEN_1223; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1523 = _T_108 ? _GEN_1457 : _GEN_1224; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1524 = _T_108 ? _GEN_1458 : _GEN_1225; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1525 = _T_108 ? _GEN_1459 : _GEN_1226; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1526 = _T_108 ? _GEN_1460 : _GEN_1227; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1527 = _T_108 ? _GEN_1461 : _GEN_1228; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1528 = _T_108 ? _GEN_1462 : _GEN_1229; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1529 = _T_108 ? _GEN_1463 : _GEN_1230; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1530 = _T_108 ? _GEN_1464 : _GEN_1231; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1531 = _T_108 ? _GEN_1465 : _GEN_1232; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1532 = _T_108 ? _GEN_1466 : _GEN_1233; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1533 = _T_108 ? _GEN_1467 : _GEN_1234; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1534 = _T_108 ? _GEN_1468 : _GEN_1235; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1535 = _T_108 ? _GEN_1469 : _GEN_1236; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1536 = _T_108 ? _GEN_1470 : _GEN_1237; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1537 = _T_108 ? _GEN_1471 : _GEN_1238; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1538 = _T_108 ? _GEN_1472 : _GEN_1239; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1539 = _T_108 ? _GEN_1473 : _GEN_1240; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1540 = _T_108 ? _GEN_1474 : _GEN_1241; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1541 = _T_108 ? _GEN_1475 : _GEN_1242; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1542 = _T_108 ? _GEN_1476 : _GEN_1243; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1543 = _T_108 ? _GEN_1477 : _GEN_1244; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1544 = _T_108 ? _GEN_1478 : _GEN_1245; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1545 = _T_108 ? _GEN_1479 : _GEN_1246; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1546 = _T_108 ? _GEN_1480 : _GEN_1247; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1547 = _T_108 ? _GEN_1481 : _GEN_1248; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1548 = _T_108 ? _GEN_1482 : _GEN_1249; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1549 = _T_108 ? _GEN_1483 : _GEN_1250; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1550 = _T_108 ? _GEN_1484 : _GEN_1251; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1551 = _T_108 ? _GEN_1485 : _GEN_1252; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1552 = _T_108 ? _GEN_1486 : _GEN_1253; // @[Regfiles.scala 201:38]
  wire [1:0] _GEN_1587 = 6'h1 == io_commit_0_phy ? log_reg_1 : log_reg_0; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1588 = 6'h2 == io_commit_0_phy ? log_reg_2 : _GEN_1587; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1589 = 6'h3 == io_commit_0_phy ? log_reg_3 : _GEN_1588; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1590 = 6'h4 == io_commit_0_phy ? log_reg_4 : _GEN_1589; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1591 = 6'h5 == io_commit_0_phy ? log_reg_5 : _GEN_1590; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1592 = 6'h6 == io_commit_0_phy ? log_reg_6 : _GEN_1591; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1593 = 6'h7 == io_commit_0_phy ? log_reg_7 : _GEN_1592; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1594 = 6'h8 == io_commit_0_phy ? log_reg_8 : _GEN_1593; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1595 = 6'h9 == io_commit_0_phy ? log_reg_9 : _GEN_1594; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1596 = 6'ha == io_commit_0_phy ? log_reg_10 : _GEN_1595; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1597 = 6'hb == io_commit_0_phy ? log_reg_11 : _GEN_1596; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1598 = 6'hc == io_commit_0_phy ? log_reg_12 : _GEN_1597; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1599 = 6'hd == io_commit_0_phy ? log_reg_13 : _GEN_1598; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1600 = 6'he == io_commit_0_phy ? log_reg_14 : _GEN_1599; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1601 = 6'hf == io_commit_0_phy ? log_reg_15 : _GEN_1600; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1602 = 6'h10 == io_commit_0_phy ? log_reg_16 : _GEN_1601; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1603 = 6'h11 == io_commit_0_phy ? log_reg_17 : _GEN_1602; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1604 = 6'h12 == io_commit_0_phy ? log_reg_18 : _GEN_1603; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1605 = 6'h13 == io_commit_0_phy ? log_reg_19 : _GEN_1604; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1606 = 6'h14 == io_commit_0_phy ? log_reg_20 : _GEN_1605; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1607 = 6'h15 == io_commit_0_phy ? log_reg_21 : _GEN_1606; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1608 = 6'h16 == io_commit_0_phy ? log_reg_22 : _GEN_1607; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1609 = 6'h17 == io_commit_0_phy ? log_reg_23 : _GEN_1608; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1610 = 6'h18 == io_commit_0_phy ? log_reg_24 : _GEN_1609; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1611 = 6'h19 == io_commit_0_phy ? log_reg_25 : _GEN_1610; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1612 = 6'h1a == io_commit_0_phy ? log_reg_26 : _GEN_1611; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1613 = 6'h1b == io_commit_0_phy ? log_reg_27 : _GEN_1612; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1614 = 6'h1c == io_commit_0_phy ? log_reg_28 : _GEN_1613; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1615 = 6'h1d == io_commit_0_phy ? log_reg_29 : _GEN_1614; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1616 = 6'h1e == io_commit_0_phy ? log_reg_30 : _GEN_1615; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1617 = 6'h1f == io_commit_0_phy ? log_reg_31 : _GEN_1616; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1618 = 6'h20 == io_commit_0_phy ? log_reg_32 : _GEN_1617; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] _GEN_1619 = 6'h21 == io_commit_0_phy ? 2'h3 : _GEN_1618; // @[Regfiles.scala 219:{46,46}]
  wire  _log_reg_0_T_15 = archit_ptr_15 == 6'h0; // @[Regfiles.scala 223:99]
  wire  _log_reg_0_T_47 = archit_ptr_0 == 6'h0 | archit_ptr_1 == 6'h0 | archit_ptr_2 == 6'h0 | archit_ptr_3 == 6'h0 |
    archit_ptr_4 == 6'h0 | archit_ptr_5 == 6'h0 | archit_ptr_6 == 6'h0 | archit_ptr_7 == 6'h0 | archit_ptr_8 == 6'h0 |
    archit_ptr_9 == 6'h0 | archit_ptr_10 == 6'h0 | archit_ptr_11 == 6'h0 | archit_ptr_12 == 6'h0 | archit_ptr_13 == 6'h0
     | archit_ptr_14 == 6'h0 | _log_reg_0_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_0_T_62 = _log_reg_0_T_47 | archit_ptr_16 == 6'h0 | archit_ptr_17 == 6'h0 | archit_ptr_18 == 6'h0 |
    archit_ptr_19 == 6'h0 | archit_ptr_20 == 6'h0 | archit_ptr_21 == 6'h0 | archit_ptr_22 == 6'h0 | archit_ptr_23 == 6'h0
     | archit_ptr_24 == 6'h0 | archit_ptr_25 == 6'h0 | archit_ptr_26 == 6'h0 | archit_ptr_27 == 6'h0 | archit_ptr_28 == 6'h0
     | archit_ptr_29 == 6'h0 | archit_ptr_30 == 6'h0; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_0_T_64 = _log_reg_0_T_62 | archit_ptr_31 == 6'h0 ? log_reg_0 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_1_T_15 = archit_ptr_15 == 6'h1; // @[Regfiles.scala 223:99]
  wire  _log_reg_1_T_47 = archit_ptr_0 == 6'h1 | archit_ptr_1 == 6'h1 | archit_ptr_2 == 6'h1 | archit_ptr_3 == 6'h1 |
    archit_ptr_4 == 6'h1 | archit_ptr_5 == 6'h1 | archit_ptr_6 == 6'h1 | archit_ptr_7 == 6'h1 | archit_ptr_8 == 6'h1 |
    archit_ptr_9 == 6'h1 | archit_ptr_10 == 6'h1 | archit_ptr_11 == 6'h1 | archit_ptr_12 == 6'h1 | archit_ptr_13 == 6'h1
     | archit_ptr_14 == 6'h1 | _log_reg_1_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_1_T_62 = _log_reg_1_T_47 | archit_ptr_16 == 6'h1 | archit_ptr_17 == 6'h1 | archit_ptr_18 == 6'h1 |
    archit_ptr_19 == 6'h1 | archit_ptr_20 == 6'h1 | archit_ptr_21 == 6'h1 | archit_ptr_22 == 6'h1 | archit_ptr_23 == 6'h1
     | archit_ptr_24 == 6'h1 | archit_ptr_25 == 6'h1 | archit_ptr_26 == 6'h1 | archit_ptr_27 == 6'h1 | archit_ptr_28 == 6'h1
     | archit_ptr_29 == 6'h1 | archit_ptr_30 == 6'h1; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_1_T_64 = _log_reg_1_T_62 | archit_ptr_31 == 6'h1 ? log_reg_1 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_2_T_15 = archit_ptr_15 == 6'h2; // @[Regfiles.scala 223:99]
  wire  _log_reg_2_T_47 = archit_ptr_0 == 6'h2 | archit_ptr_1 == 6'h2 | archit_ptr_2 == 6'h2 | archit_ptr_3 == 6'h2 |
    archit_ptr_4 == 6'h2 | archit_ptr_5 == 6'h2 | archit_ptr_6 == 6'h2 | archit_ptr_7 == 6'h2 | archit_ptr_8 == 6'h2 |
    archit_ptr_9 == 6'h2 | archit_ptr_10 == 6'h2 | archit_ptr_11 == 6'h2 | archit_ptr_12 == 6'h2 | archit_ptr_13 == 6'h2
     | archit_ptr_14 == 6'h2 | _log_reg_2_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_2_T_62 = _log_reg_2_T_47 | archit_ptr_16 == 6'h2 | archit_ptr_17 == 6'h2 | archit_ptr_18 == 6'h2 |
    archit_ptr_19 == 6'h2 | archit_ptr_20 == 6'h2 | archit_ptr_21 == 6'h2 | archit_ptr_22 == 6'h2 | archit_ptr_23 == 6'h2
     | archit_ptr_24 == 6'h2 | archit_ptr_25 == 6'h2 | archit_ptr_26 == 6'h2 | archit_ptr_27 == 6'h2 | archit_ptr_28 == 6'h2
     | archit_ptr_29 == 6'h2 | archit_ptr_30 == 6'h2; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_2_T_64 = _log_reg_2_T_62 | archit_ptr_31 == 6'h2 ? log_reg_2 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_3_T_15 = archit_ptr_15 == 6'h3; // @[Regfiles.scala 223:99]
  wire  _log_reg_3_T_47 = archit_ptr_0 == 6'h3 | archit_ptr_1 == 6'h3 | archit_ptr_2 == 6'h3 | archit_ptr_3 == 6'h3 |
    archit_ptr_4 == 6'h3 | archit_ptr_5 == 6'h3 | archit_ptr_6 == 6'h3 | archit_ptr_7 == 6'h3 | archit_ptr_8 == 6'h3 |
    archit_ptr_9 == 6'h3 | archit_ptr_10 == 6'h3 | archit_ptr_11 == 6'h3 | archit_ptr_12 == 6'h3 | archit_ptr_13 == 6'h3
     | archit_ptr_14 == 6'h3 | _log_reg_3_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_3_T_62 = _log_reg_3_T_47 | archit_ptr_16 == 6'h3 | archit_ptr_17 == 6'h3 | archit_ptr_18 == 6'h3 |
    archit_ptr_19 == 6'h3 | archit_ptr_20 == 6'h3 | archit_ptr_21 == 6'h3 | archit_ptr_22 == 6'h3 | archit_ptr_23 == 6'h3
     | archit_ptr_24 == 6'h3 | archit_ptr_25 == 6'h3 | archit_ptr_26 == 6'h3 | archit_ptr_27 == 6'h3 | archit_ptr_28 == 6'h3
     | archit_ptr_29 == 6'h3 | archit_ptr_30 == 6'h3; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_3_T_64 = _log_reg_3_T_62 | archit_ptr_31 == 6'h3 ? log_reg_3 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_4_T_15 = archit_ptr_15 == 6'h4; // @[Regfiles.scala 223:99]
  wire  _log_reg_4_T_47 = archit_ptr_0 == 6'h4 | archit_ptr_1 == 6'h4 | archit_ptr_2 == 6'h4 | archit_ptr_3 == 6'h4 |
    archit_ptr_4 == 6'h4 | archit_ptr_5 == 6'h4 | archit_ptr_6 == 6'h4 | archit_ptr_7 == 6'h4 | archit_ptr_8 == 6'h4 |
    archit_ptr_9 == 6'h4 | archit_ptr_10 == 6'h4 | archit_ptr_11 == 6'h4 | archit_ptr_12 == 6'h4 | archit_ptr_13 == 6'h4
     | archit_ptr_14 == 6'h4 | _log_reg_4_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_4_T_62 = _log_reg_4_T_47 | archit_ptr_16 == 6'h4 | archit_ptr_17 == 6'h4 | archit_ptr_18 == 6'h4 |
    archit_ptr_19 == 6'h4 | archit_ptr_20 == 6'h4 | archit_ptr_21 == 6'h4 | archit_ptr_22 == 6'h4 | archit_ptr_23 == 6'h4
     | archit_ptr_24 == 6'h4 | archit_ptr_25 == 6'h4 | archit_ptr_26 == 6'h4 | archit_ptr_27 == 6'h4 | archit_ptr_28 == 6'h4
     | archit_ptr_29 == 6'h4 | archit_ptr_30 == 6'h4; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_4_T_64 = _log_reg_4_T_62 | archit_ptr_31 == 6'h4 ? log_reg_4 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_5_T_15 = archit_ptr_15 == 6'h5; // @[Regfiles.scala 223:99]
  wire  _log_reg_5_T_47 = archit_ptr_0 == 6'h5 | archit_ptr_1 == 6'h5 | archit_ptr_2 == 6'h5 | archit_ptr_3 == 6'h5 |
    archit_ptr_4 == 6'h5 | archit_ptr_5 == 6'h5 | archit_ptr_6 == 6'h5 | archit_ptr_7 == 6'h5 | archit_ptr_8 == 6'h5 |
    archit_ptr_9 == 6'h5 | archit_ptr_10 == 6'h5 | archit_ptr_11 == 6'h5 | archit_ptr_12 == 6'h5 | archit_ptr_13 == 6'h5
     | archit_ptr_14 == 6'h5 | _log_reg_5_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_5_T_62 = _log_reg_5_T_47 | archit_ptr_16 == 6'h5 | archit_ptr_17 == 6'h5 | archit_ptr_18 == 6'h5 |
    archit_ptr_19 == 6'h5 | archit_ptr_20 == 6'h5 | archit_ptr_21 == 6'h5 | archit_ptr_22 == 6'h5 | archit_ptr_23 == 6'h5
     | archit_ptr_24 == 6'h5 | archit_ptr_25 == 6'h5 | archit_ptr_26 == 6'h5 | archit_ptr_27 == 6'h5 | archit_ptr_28 == 6'h5
     | archit_ptr_29 == 6'h5 | archit_ptr_30 == 6'h5; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_5_T_64 = _log_reg_5_T_62 | archit_ptr_31 == 6'h5 ? log_reg_5 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_6_T_15 = archit_ptr_15 == 6'h6; // @[Regfiles.scala 223:99]
  wire  _log_reg_6_T_47 = archit_ptr_0 == 6'h6 | archit_ptr_1 == 6'h6 | archit_ptr_2 == 6'h6 | archit_ptr_3 == 6'h6 |
    archit_ptr_4 == 6'h6 | archit_ptr_5 == 6'h6 | archit_ptr_6 == 6'h6 | archit_ptr_7 == 6'h6 | archit_ptr_8 == 6'h6 |
    archit_ptr_9 == 6'h6 | archit_ptr_10 == 6'h6 | archit_ptr_11 == 6'h6 | archit_ptr_12 == 6'h6 | archit_ptr_13 == 6'h6
     | archit_ptr_14 == 6'h6 | _log_reg_6_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_6_T_62 = _log_reg_6_T_47 | archit_ptr_16 == 6'h6 | archit_ptr_17 == 6'h6 | archit_ptr_18 == 6'h6 |
    archit_ptr_19 == 6'h6 | archit_ptr_20 == 6'h6 | archit_ptr_21 == 6'h6 | archit_ptr_22 == 6'h6 | archit_ptr_23 == 6'h6
     | archit_ptr_24 == 6'h6 | archit_ptr_25 == 6'h6 | archit_ptr_26 == 6'h6 | archit_ptr_27 == 6'h6 | archit_ptr_28 == 6'h6
     | archit_ptr_29 == 6'h6 | archit_ptr_30 == 6'h6; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_6_T_64 = _log_reg_6_T_62 | archit_ptr_31 == 6'h6 ? log_reg_6 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_7_T_15 = archit_ptr_15 == 6'h7; // @[Regfiles.scala 223:99]
  wire  _log_reg_7_T_47 = archit_ptr_0 == 6'h7 | archit_ptr_1 == 6'h7 | archit_ptr_2 == 6'h7 | archit_ptr_3 == 6'h7 |
    archit_ptr_4 == 6'h7 | archit_ptr_5 == 6'h7 | archit_ptr_6 == 6'h7 | archit_ptr_7 == 6'h7 | archit_ptr_8 == 6'h7 |
    archit_ptr_9 == 6'h7 | archit_ptr_10 == 6'h7 | archit_ptr_11 == 6'h7 | archit_ptr_12 == 6'h7 | archit_ptr_13 == 6'h7
     | archit_ptr_14 == 6'h7 | _log_reg_7_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_7_T_62 = _log_reg_7_T_47 | archit_ptr_16 == 6'h7 | archit_ptr_17 == 6'h7 | archit_ptr_18 == 6'h7 |
    archit_ptr_19 == 6'h7 | archit_ptr_20 == 6'h7 | archit_ptr_21 == 6'h7 | archit_ptr_22 == 6'h7 | archit_ptr_23 == 6'h7
     | archit_ptr_24 == 6'h7 | archit_ptr_25 == 6'h7 | archit_ptr_26 == 6'h7 | archit_ptr_27 == 6'h7 | archit_ptr_28 == 6'h7
     | archit_ptr_29 == 6'h7 | archit_ptr_30 == 6'h7; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_7_T_64 = _log_reg_7_T_62 | archit_ptr_31 == 6'h7 ? log_reg_7 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_8_T_15 = archit_ptr_15 == 6'h8; // @[Regfiles.scala 223:99]
  wire  _log_reg_8_T_47 = archit_ptr_0 == 6'h8 | archit_ptr_1 == 6'h8 | archit_ptr_2 == 6'h8 | archit_ptr_3 == 6'h8 |
    archit_ptr_4 == 6'h8 | archit_ptr_5 == 6'h8 | archit_ptr_6 == 6'h8 | archit_ptr_7 == 6'h8 | archit_ptr_8 == 6'h8 |
    archit_ptr_9 == 6'h8 | archit_ptr_10 == 6'h8 | archit_ptr_11 == 6'h8 | archit_ptr_12 == 6'h8 | archit_ptr_13 == 6'h8
     | archit_ptr_14 == 6'h8 | _log_reg_8_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_8_T_62 = _log_reg_8_T_47 | archit_ptr_16 == 6'h8 | archit_ptr_17 == 6'h8 | archit_ptr_18 == 6'h8 |
    archit_ptr_19 == 6'h8 | archit_ptr_20 == 6'h8 | archit_ptr_21 == 6'h8 | archit_ptr_22 == 6'h8 | archit_ptr_23 == 6'h8
     | archit_ptr_24 == 6'h8 | archit_ptr_25 == 6'h8 | archit_ptr_26 == 6'h8 | archit_ptr_27 == 6'h8 | archit_ptr_28 == 6'h8
     | archit_ptr_29 == 6'h8 | archit_ptr_30 == 6'h8; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_8_T_64 = _log_reg_8_T_62 | archit_ptr_31 == 6'h8 ? log_reg_8 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_9_T_15 = archit_ptr_15 == 6'h9; // @[Regfiles.scala 223:99]
  wire  _log_reg_9_T_47 = archit_ptr_0 == 6'h9 | archit_ptr_1 == 6'h9 | archit_ptr_2 == 6'h9 | archit_ptr_3 == 6'h9 |
    archit_ptr_4 == 6'h9 | archit_ptr_5 == 6'h9 | archit_ptr_6 == 6'h9 | archit_ptr_7 == 6'h9 | archit_ptr_8 == 6'h9 |
    archit_ptr_9 == 6'h9 | archit_ptr_10 == 6'h9 | archit_ptr_11 == 6'h9 | archit_ptr_12 == 6'h9 | archit_ptr_13 == 6'h9
     | archit_ptr_14 == 6'h9 | _log_reg_9_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_9_T_62 = _log_reg_9_T_47 | archit_ptr_16 == 6'h9 | archit_ptr_17 == 6'h9 | archit_ptr_18 == 6'h9 |
    archit_ptr_19 == 6'h9 | archit_ptr_20 == 6'h9 | archit_ptr_21 == 6'h9 | archit_ptr_22 == 6'h9 | archit_ptr_23 == 6'h9
     | archit_ptr_24 == 6'h9 | archit_ptr_25 == 6'h9 | archit_ptr_26 == 6'h9 | archit_ptr_27 == 6'h9 | archit_ptr_28 == 6'h9
     | archit_ptr_29 == 6'h9 | archit_ptr_30 == 6'h9; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_9_T_64 = _log_reg_9_T_62 | archit_ptr_31 == 6'h9 ? log_reg_9 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_10_T_15 = archit_ptr_15 == 6'ha; // @[Regfiles.scala 223:99]
  wire  _log_reg_10_T_47 = archit_ptr_0 == 6'ha | archit_ptr_1 == 6'ha | archit_ptr_2 == 6'ha | archit_ptr_3 == 6'ha |
    archit_ptr_4 == 6'ha | archit_ptr_5 == 6'ha | archit_ptr_6 == 6'ha | archit_ptr_7 == 6'ha | archit_ptr_8 == 6'ha |
    archit_ptr_9 == 6'ha | archit_ptr_10 == 6'ha | archit_ptr_11 == 6'ha | archit_ptr_12 == 6'ha | archit_ptr_13 == 6'ha
     | archit_ptr_14 == 6'ha | _log_reg_10_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_10_T_62 = _log_reg_10_T_47 | archit_ptr_16 == 6'ha | archit_ptr_17 == 6'ha | archit_ptr_18 == 6'ha |
    archit_ptr_19 == 6'ha | archit_ptr_20 == 6'ha | archit_ptr_21 == 6'ha | archit_ptr_22 == 6'ha | archit_ptr_23 == 6'ha
     | archit_ptr_24 == 6'ha | archit_ptr_25 == 6'ha | archit_ptr_26 == 6'ha | archit_ptr_27 == 6'ha | archit_ptr_28 == 6'ha
     | archit_ptr_29 == 6'ha | archit_ptr_30 == 6'ha; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_10_T_64 = _log_reg_10_T_62 | archit_ptr_31 == 6'ha ? log_reg_10 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_11_T_15 = archit_ptr_15 == 6'hb; // @[Regfiles.scala 223:99]
  wire  _log_reg_11_T_47 = archit_ptr_0 == 6'hb | archit_ptr_1 == 6'hb | archit_ptr_2 == 6'hb | archit_ptr_3 == 6'hb |
    archit_ptr_4 == 6'hb | archit_ptr_5 == 6'hb | archit_ptr_6 == 6'hb | archit_ptr_7 == 6'hb | archit_ptr_8 == 6'hb |
    archit_ptr_9 == 6'hb | archit_ptr_10 == 6'hb | archit_ptr_11 == 6'hb | archit_ptr_12 == 6'hb | archit_ptr_13 == 6'hb
     | archit_ptr_14 == 6'hb | _log_reg_11_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_11_T_62 = _log_reg_11_T_47 | archit_ptr_16 == 6'hb | archit_ptr_17 == 6'hb | archit_ptr_18 == 6'hb |
    archit_ptr_19 == 6'hb | archit_ptr_20 == 6'hb | archit_ptr_21 == 6'hb | archit_ptr_22 == 6'hb | archit_ptr_23 == 6'hb
     | archit_ptr_24 == 6'hb | archit_ptr_25 == 6'hb | archit_ptr_26 == 6'hb | archit_ptr_27 == 6'hb | archit_ptr_28 == 6'hb
     | archit_ptr_29 == 6'hb | archit_ptr_30 == 6'hb; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_11_T_64 = _log_reg_11_T_62 | archit_ptr_31 == 6'hb ? log_reg_11 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_12_T_15 = archit_ptr_15 == 6'hc; // @[Regfiles.scala 223:99]
  wire  _log_reg_12_T_47 = archit_ptr_0 == 6'hc | archit_ptr_1 == 6'hc | archit_ptr_2 == 6'hc | archit_ptr_3 == 6'hc |
    archit_ptr_4 == 6'hc | archit_ptr_5 == 6'hc | archit_ptr_6 == 6'hc | archit_ptr_7 == 6'hc | archit_ptr_8 == 6'hc |
    archit_ptr_9 == 6'hc | archit_ptr_10 == 6'hc | archit_ptr_11 == 6'hc | archit_ptr_12 == 6'hc | archit_ptr_13 == 6'hc
     | archit_ptr_14 == 6'hc | _log_reg_12_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_12_T_62 = _log_reg_12_T_47 | archit_ptr_16 == 6'hc | archit_ptr_17 == 6'hc | archit_ptr_18 == 6'hc |
    archit_ptr_19 == 6'hc | archit_ptr_20 == 6'hc | archit_ptr_21 == 6'hc | archit_ptr_22 == 6'hc | archit_ptr_23 == 6'hc
     | archit_ptr_24 == 6'hc | archit_ptr_25 == 6'hc | archit_ptr_26 == 6'hc | archit_ptr_27 == 6'hc | archit_ptr_28 == 6'hc
     | archit_ptr_29 == 6'hc | archit_ptr_30 == 6'hc; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_12_T_64 = _log_reg_12_T_62 | archit_ptr_31 == 6'hc ? log_reg_12 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_13_T_15 = archit_ptr_15 == 6'hd; // @[Regfiles.scala 223:99]
  wire  _log_reg_13_T_47 = archit_ptr_0 == 6'hd | archit_ptr_1 == 6'hd | archit_ptr_2 == 6'hd | archit_ptr_3 == 6'hd |
    archit_ptr_4 == 6'hd | archit_ptr_5 == 6'hd | archit_ptr_6 == 6'hd | archit_ptr_7 == 6'hd | archit_ptr_8 == 6'hd |
    archit_ptr_9 == 6'hd | archit_ptr_10 == 6'hd | archit_ptr_11 == 6'hd | archit_ptr_12 == 6'hd | archit_ptr_13 == 6'hd
     | archit_ptr_14 == 6'hd | _log_reg_13_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_13_T_62 = _log_reg_13_T_47 | archit_ptr_16 == 6'hd | archit_ptr_17 == 6'hd | archit_ptr_18 == 6'hd |
    archit_ptr_19 == 6'hd | archit_ptr_20 == 6'hd | archit_ptr_21 == 6'hd | archit_ptr_22 == 6'hd | archit_ptr_23 == 6'hd
     | archit_ptr_24 == 6'hd | archit_ptr_25 == 6'hd | archit_ptr_26 == 6'hd | archit_ptr_27 == 6'hd | archit_ptr_28 == 6'hd
     | archit_ptr_29 == 6'hd | archit_ptr_30 == 6'hd; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_13_T_64 = _log_reg_13_T_62 | archit_ptr_31 == 6'hd ? log_reg_13 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_14_T_15 = archit_ptr_15 == 6'he; // @[Regfiles.scala 223:99]
  wire  _log_reg_14_T_47 = archit_ptr_0 == 6'he | archit_ptr_1 == 6'he | archit_ptr_2 == 6'he | archit_ptr_3 == 6'he |
    archit_ptr_4 == 6'he | archit_ptr_5 == 6'he | archit_ptr_6 == 6'he | archit_ptr_7 == 6'he | archit_ptr_8 == 6'he |
    archit_ptr_9 == 6'he | archit_ptr_10 == 6'he | archit_ptr_11 == 6'he | archit_ptr_12 == 6'he | archit_ptr_13 == 6'he
     | archit_ptr_14 == 6'he | _log_reg_14_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_14_T_62 = _log_reg_14_T_47 | archit_ptr_16 == 6'he | archit_ptr_17 == 6'he | archit_ptr_18 == 6'he |
    archit_ptr_19 == 6'he | archit_ptr_20 == 6'he | archit_ptr_21 == 6'he | archit_ptr_22 == 6'he | archit_ptr_23 == 6'he
     | archit_ptr_24 == 6'he | archit_ptr_25 == 6'he | archit_ptr_26 == 6'he | archit_ptr_27 == 6'he | archit_ptr_28 == 6'he
     | archit_ptr_29 == 6'he | archit_ptr_30 == 6'he; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_14_T_64 = _log_reg_14_T_62 | archit_ptr_31 == 6'he ? log_reg_14 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_15_T_15 = archit_ptr_15 == 6'hf; // @[Regfiles.scala 223:99]
  wire  _log_reg_15_T_47 = archit_ptr_0 == 6'hf | archit_ptr_1 == 6'hf | archit_ptr_2 == 6'hf | archit_ptr_3 == 6'hf |
    archit_ptr_4 == 6'hf | archit_ptr_5 == 6'hf | archit_ptr_6 == 6'hf | archit_ptr_7 == 6'hf | archit_ptr_8 == 6'hf |
    archit_ptr_9 == 6'hf | archit_ptr_10 == 6'hf | archit_ptr_11 == 6'hf | archit_ptr_12 == 6'hf | archit_ptr_13 == 6'hf
     | archit_ptr_14 == 6'hf | _log_reg_15_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_15_T_62 = _log_reg_15_T_47 | archit_ptr_16 == 6'hf | archit_ptr_17 == 6'hf | archit_ptr_18 == 6'hf |
    archit_ptr_19 == 6'hf | archit_ptr_20 == 6'hf | archit_ptr_21 == 6'hf | archit_ptr_22 == 6'hf | archit_ptr_23 == 6'hf
     | archit_ptr_24 == 6'hf | archit_ptr_25 == 6'hf | archit_ptr_26 == 6'hf | archit_ptr_27 == 6'hf | archit_ptr_28 == 6'hf
     | archit_ptr_29 == 6'hf | archit_ptr_30 == 6'hf; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_15_T_64 = _log_reg_15_T_62 | archit_ptr_31 == 6'hf ? log_reg_15 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_16_T_15 = archit_ptr_15 == 6'h10; // @[Regfiles.scala 223:99]
  wire  _log_reg_16_T_47 = archit_ptr_0 == 6'h10 | archit_ptr_1 == 6'h10 | archit_ptr_2 == 6'h10 | archit_ptr_3 == 6'h10
     | archit_ptr_4 == 6'h10 | archit_ptr_5 == 6'h10 | archit_ptr_6 == 6'h10 | archit_ptr_7 == 6'h10 | archit_ptr_8 == 6'h10
     | archit_ptr_9 == 6'h10 | archit_ptr_10 == 6'h10 | archit_ptr_11 == 6'h10 | archit_ptr_12 == 6'h10 | archit_ptr_13
     == 6'h10 | archit_ptr_14 == 6'h10 | _log_reg_16_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_16_T_62 = _log_reg_16_T_47 | archit_ptr_16 == 6'h10 | archit_ptr_17 == 6'h10 | archit_ptr_18 == 6'h10
     | archit_ptr_19 == 6'h10 | archit_ptr_20 == 6'h10 | archit_ptr_21 == 6'h10 | archit_ptr_22 == 6'h10 | archit_ptr_23
     == 6'h10 | archit_ptr_24 == 6'h10 | archit_ptr_25 == 6'h10 | archit_ptr_26 == 6'h10 | archit_ptr_27 == 6'h10 |
    archit_ptr_28 == 6'h10 | archit_ptr_29 == 6'h10 | archit_ptr_30 == 6'h10; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_16_T_64 = _log_reg_16_T_62 | archit_ptr_31 == 6'h10 ? log_reg_16 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_17_T_15 = archit_ptr_15 == 6'h11; // @[Regfiles.scala 223:99]
  wire  _log_reg_17_T_47 = archit_ptr_0 == 6'h11 | archit_ptr_1 == 6'h11 | archit_ptr_2 == 6'h11 | archit_ptr_3 == 6'h11
     | archit_ptr_4 == 6'h11 | archit_ptr_5 == 6'h11 | archit_ptr_6 == 6'h11 | archit_ptr_7 == 6'h11 | archit_ptr_8 == 6'h11
     | archit_ptr_9 == 6'h11 | archit_ptr_10 == 6'h11 | archit_ptr_11 == 6'h11 | archit_ptr_12 == 6'h11 | archit_ptr_13
     == 6'h11 | archit_ptr_14 == 6'h11 | _log_reg_17_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_17_T_62 = _log_reg_17_T_47 | archit_ptr_16 == 6'h11 | archit_ptr_17 == 6'h11 | archit_ptr_18 == 6'h11
     | archit_ptr_19 == 6'h11 | archit_ptr_20 == 6'h11 | archit_ptr_21 == 6'h11 | archit_ptr_22 == 6'h11 | archit_ptr_23
     == 6'h11 | archit_ptr_24 == 6'h11 | archit_ptr_25 == 6'h11 | archit_ptr_26 == 6'h11 | archit_ptr_27 == 6'h11 |
    archit_ptr_28 == 6'h11 | archit_ptr_29 == 6'h11 | archit_ptr_30 == 6'h11; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_17_T_64 = _log_reg_17_T_62 | archit_ptr_31 == 6'h11 ? log_reg_17 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_18_T_15 = archit_ptr_15 == 6'h12; // @[Regfiles.scala 223:99]
  wire  _log_reg_18_T_47 = archit_ptr_0 == 6'h12 | archit_ptr_1 == 6'h12 | archit_ptr_2 == 6'h12 | archit_ptr_3 == 6'h12
     | archit_ptr_4 == 6'h12 | archit_ptr_5 == 6'h12 | archit_ptr_6 == 6'h12 | archit_ptr_7 == 6'h12 | archit_ptr_8 == 6'h12
     | archit_ptr_9 == 6'h12 | archit_ptr_10 == 6'h12 | archit_ptr_11 == 6'h12 | archit_ptr_12 == 6'h12 | archit_ptr_13
     == 6'h12 | archit_ptr_14 == 6'h12 | _log_reg_18_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_18_T_62 = _log_reg_18_T_47 | archit_ptr_16 == 6'h12 | archit_ptr_17 == 6'h12 | archit_ptr_18 == 6'h12
     | archit_ptr_19 == 6'h12 | archit_ptr_20 == 6'h12 | archit_ptr_21 == 6'h12 | archit_ptr_22 == 6'h12 | archit_ptr_23
     == 6'h12 | archit_ptr_24 == 6'h12 | archit_ptr_25 == 6'h12 | archit_ptr_26 == 6'h12 | archit_ptr_27 == 6'h12 |
    archit_ptr_28 == 6'h12 | archit_ptr_29 == 6'h12 | archit_ptr_30 == 6'h12; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_18_T_64 = _log_reg_18_T_62 | archit_ptr_31 == 6'h12 ? log_reg_18 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_19_T_15 = archit_ptr_15 == 6'h13; // @[Regfiles.scala 223:99]
  wire  _log_reg_19_T_47 = archit_ptr_0 == 6'h13 | archit_ptr_1 == 6'h13 | archit_ptr_2 == 6'h13 | archit_ptr_3 == 6'h13
     | archit_ptr_4 == 6'h13 | archit_ptr_5 == 6'h13 | archit_ptr_6 == 6'h13 | archit_ptr_7 == 6'h13 | archit_ptr_8 == 6'h13
     | archit_ptr_9 == 6'h13 | archit_ptr_10 == 6'h13 | archit_ptr_11 == 6'h13 | archit_ptr_12 == 6'h13 | archit_ptr_13
     == 6'h13 | archit_ptr_14 == 6'h13 | _log_reg_19_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_19_T_62 = _log_reg_19_T_47 | archit_ptr_16 == 6'h13 | archit_ptr_17 == 6'h13 | archit_ptr_18 == 6'h13
     | archit_ptr_19 == 6'h13 | archit_ptr_20 == 6'h13 | archit_ptr_21 == 6'h13 | archit_ptr_22 == 6'h13 | archit_ptr_23
     == 6'h13 | archit_ptr_24 == 6'h13 | archit_ptr_25 == 6'h13 | archit_ptr_26 == 6'h13 | archit_ptr_27 == 6'h13 |
    archit_ptr_28 == 6'h13 | archit_ptr_29 == 6'h13 | archit_ptr_30 == 6'h13; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_19_T_64 = _log_reg_19_T_62 | archit_ptr_31 == 6'h13 ? log_reg_19 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_20_T_15 = archit_ptr_15 == 6'h14; // @[Regfiles.scala 223:99]
  wire  _log_reg_20_T_47 = archit_ptr_0 == 6'h14 | archit_ptr_1 == 6'h14 | archit_ptr_2 == 6'h14 | archit_ptr_3 == 6'h14
     | archit_ptr_4 == 6'h14 | archit_ptr_5 == 6'h14 | archit_ptr_6 == 6'h14 | archit_ptr_7 == 6'h14 | archit_ptr_8 == 6'h14
     | archit_ptr_9 == 6'h14 | archit_ptr_10 == 6'h14 | archit_ptr_11 == 6'h14 | archit_ptr_12 == 6'h14 | archit_ptr_13
     == 6'h14 | archit_ptr_14 == 6'h14 | _log_reg_20_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_20_T_62 = _log_reg_20_T_47 | archit_ptr_16 == 6'h14 | archit_ptr_17 == 6'h14 | archit_ptr_18 == 6'h14
     | archit_ptr_19 == 6'h14 | archit_ptr_20 == 6'h14 | archit_ptr_21 == 6'h14 | archit_ptr_22 == 6'h14 | archit_ptr_23
     == 6'h14 | archit_ptr_24 == 6'h14 | archit_ptr_25 == 6'h14 | archit_ptr_26 == 6'h14 | archit_ptr_27 == 6'h14 |
    archit_ptr_28 == 6'h14 | archit_ptr_29 == 6'h14 | archit_ptr_30 == 6'h14; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_20_T_64 = _log_reg_20_T_62 | archit_ptr_31 == 6'h14 ? log_reg_20 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_21_T_15 = archit_ptr_15 == 6'h15; // @[Regfiles.scala 223:99]
  wire  _log_reg_21_T_47 = archit_ptr_0 == 6'h15 | archit_ptr_1 == 6'h15 | archit_ptr_2 == 6'h15 | archit_ptr_3 == 6'h15
     | archit_ptr_4 == 6'h15 | archit_ptr_5 == 6'h15 | archit_ptr_6 == 6'h15 | archit_ptr_7 == 6'h15 | archit_ptr_8 == 6'h15
     | archit_ptr_9 == 6'h15 | archit_ptr_10 == 6'h15 | archit_ptr_11 == 6'h15 | archit_ptr_12 == 6'h15 | archit_ptr_13
     == 6'h15 | archit_ptr_14 == 6'h15 | _log_reg_21_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_21_T_62 = _log_reg_21_T_47 | archit_ptr_16 == 6'h15 | archit_ptr_17 == 6'h15 | archit_ptr_18 == 6'h15
     | archit_ptr_19 == 6'h15 | archit_ptr_20 == 6'h15 | archit_ptr_21 == 6'h15 | archit_ptr_22 == 6'h15 | archit_ptr_23
     == 6'h15 | archit_ptr_24 == 6'h15 | archit_ptr_25 == 6'h15 | archit_ptr_26 == 6'h15 | archit_ptr_27 == 6'h15 |
    archit_ptr_28 == 6'h15 | archit_ptr_29 == 6'h15 | archit_ptr_30 == 6'h15; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_21_T_64 = _log_reg_21_T_62 | archit_ptr_31 == 6'h15 ? log_reg_21 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_22_T_15 = archit_ptr_15 == 6'h16; // @[Regfiles.scala 223:99]
  wire  _log_reg_22_T_47 = archit_ptr_0 == 6'h16 | archit_ptr_1 == 6'h16 | archit_ptr_2 == 6'h16 | archit_ptr_3 == 6'h16
     | archit_ptr_4 == 6'h16 | archit_ptr_5 == 6'h16 | archit_ptr_6 == 6'h16 | archit_ptr_7 == 6'h16 | archit_ptr_8 == 6'h16
     | archit_ptr_9 == 6'h16 | archit_ptr_10 == 6'h16 | archit_ptr_11 == 6'h16 | archit_ptr_12 == 6'h16 | archit_ptr_13
     == 6'h16 | archit_ptr_14 == 6'h16 | _log_reg_22_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_22_T_62 = _log_reg_22_T_47 | archit_ptr_16 == 6'h16 | archit_ptr_17 == 6'h16 | archit_ptr_18 == 6'h16
     | archit_ptr_19 == 6'h16 | archit_ptr_20 == 6'h16 | archit_ptr_21 == 6'h16 | archit_ptr_22 == 6'h16 | archit_ptr_23
     == 6'h16 | archit_ptr_24 == 6'h16 | archit_ptr_25 == 6'h16 | archit_ptr_26 == 6'h16 | archit_ptr_27 == 6'h16 |
    archit_ptr_28 == 6'h16 | archit_ptr_29 == 6'h16 | archit_ptr_30 == 6'h16; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_22_T_64 = _log_reg_22_T_62 | archit_ptr_31 == 6'h16 ? log_reg_22 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_23_T_15 = archit_ptr_15 == 6'h17; // @[Regfiles.scala 223:99]
  wire  _log_reg_23_T_47 = archit_ptr_0 == 6'h17 | archit_ptr_1 == 6'h17 | archit_ptr_2 == 6'h17 | archit_ptr_3 == 6'h17
     | archit_ptr_4 == 6'h17 | archit_ptr_5 == 6'h17 | archit_ptr_6 == 6'h17 | archit_ptr_7 == 6'h17 | archit_ptr_8 == 6'h17
     | archit_ptr_9 == 6'h17 | archit_ptr_10 == 6'h17 | archit_ptr_11 == 6'h17 | archit_ptr_12 == 6'h17 | archit_ptr_13
     == 6'h17 | archit_ptr_14 == 6'h17 | _log_reg_23_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_23_T_62 = _log_reg_23_T_47 | archit_ptr_16 == 6'h17 | archit_ptr_17 == 6'h17 | archit_ptr_18 == 6'h17
     | archit_ptr_19 == 6'h17 | archit_ptr_20 == 6'h17 | archit_ptr_21 == 6'h17 | archit_ptr_22 == 6'h17 | archit_ptr_23
     == 6'h17 | archit_ptr_24 == 6'h17 | archit_ptr_25 == 6'h17 | archit_ptr_26 == 6'h17 | archit_ptr_27 == 6'h17 |
    archit_ptr_28 == 6'h17 | archit_ptr_29 == 6'h17 | archit_ptr_30 == 6'h17; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_23_T_64 = _log_reg_23_T_62 | archit_ptr_31 == 6'h17 ? log_reg_23 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_24_T_15 = archit_ptr_15 == 6'h18; // @[Regfiles.scala 223:99]
  wire  _log_reg_24_T_47 = archit_ptr_0 == 6'h18 | archit_ptr_1 == 6'h18 | archit_ptr_2 == 6'h18 | archit_ptr_3 == 6'h18
     | archit_ptr_4 == 6'h18 | archit_ptr_5 == 6'h18 | archit_ptr_6 == 6'h18 | archit_ptr_7 == 6'h18 | archit_ptr_8 == 6'h18
     | archit_ptr_9 == 6'h18 | archit_ptr_10 == 6'h18 | archit_ptr_11 == 6'h18 | archit_ptr_12 == 6'h18 | archit_ptr_13
     == 6'h18 | archit_ptr_14 == 6'h18 | _log_reg_24_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_24_T_62 = _log_reg_24_T_47 | archit_ptr_16 == 6'h18 | archit_ptr_17 == 6'h18 | archit_ptr_18 == 6'h18
     | archit_ptr_19 == 6'h18 | archit_ptr_20 == 6'h18 | archit_ptr_21 == 6'h18 | archit_ptr_22 == 6'h18 | archit_ptr_23
     == 6'h18 | archit_ptr_24 == 6'h18 | archit_ptr_25 == 6'h18 | archit_ptr_26 == 6'h18 | archit_ptr_27 == 6'h18 |
    archit_ptr_28 == 6'h18 | archit_ptr_29 == 6'h18 | archit_ptr_30 == 6'h18; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_24_T_64 = _log_reg_24_T_62 | archit_ptr_31 == 6'h18 ? log_reg_24 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_25_T_15 = archit_ptr_15 == 6'h19; // @[Regfiles.scala 223:99]
  wire  _log_reg_25_T_47 = archit_ptr_0 == 6'h19 | archit_ptr_1 == 6'h19 | archit_ptr_2 == 6'h19 | archit_ptr_3 == 6'h19
     | archit_ptr_4 == 6'h19 | archit_ptr_5 == 6'h19 | archit_ptr_6 == 6'h19 | archit_ptr_7 == 6'h19 | archit_ptr_8 == 6'h19
     | archit_ptr_9 == 6'h19 | archit_ptr_10 == 6'h19 | archit_ptr_11 == 6'h19 | archit_ptr_12 == 6'h19 | archit_ptr_13
     == 6'h19 | archit_ptr_14 == 6'h19 | _log_reg_25_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_25_T_62 = _log_reg_25_T_47 | archit_ptr_16 == 6'h19 | archit_ptr_17 == 6'h19 | archit_ptr_18 == 6'h19
     | archit_ptr_19 == 6'h19 | archit_ptr_20 == 6'h19 | archit_ptr_21 == 6'h19 | archit_ptr_22 == 6'h19 | archit_ptr_23
     == 6'h19 | archit_ptr_24 == 6'h19 | archit_ptr_25 == 6'h19 | archit_ptr_26 == 6'h19 | archit_ptr_27 == 6'h19 |
    archit_ptr_28 == 6'h19 | archit_ptr_29 == 6'h19 | archit_ptr_30 == 6'h19; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_25_T_64 = _log_reg_25_T_62 | archit_ptr_31 == 6'h19 ? log_reg_25 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_26_T_15 = archit_ptr_15 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  _log_reg_26_T_47 = archit_ptr_0 == 6'h1a | archit_ptr_1 == 6'h1a | archit_ptr_2 == 6'h1a | archit_ptr_3 == 6'h1a
     | archit_ptr_4 == 6'h1a | archit_ptr_5 == 6'h1a | archit_ptr_6 == 6'h1a | archit_ptr_7 == 6'h1a | archit_ptr_8 == 6'h1a
     | archit_ptr_9 == 6'h1a | archit_ptr_10 == 6'h1a | archit_ptr_11 == 6'h1a | archit_ptr_12 == 6'h1a | archit_ptr_13
     == 6'h1a | archit_ptr_14 == 6'h1a | _log_reg_26_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_26_T_62 = _log_reg_26_T_47 | archit_ptr_16 == 6'h1a | archit_ptr_17 == 6'h1a | archit_ptr_18 == 6'h1a
     | archit_ptr_19 == 6'h1a | archit_ptr_20 == 6'h1a | archit_ptr_21 == 6'h1a | archit_ptr_22 == 6'h1a | archit_ptr_23
     == 6'h1a | archit_ptr_24 == 6'h1a | archit_ptr_25 == 6'h1a | archit_ptr_26 == 6'h1a | archit_ptr_27 == 6'h1a |
    archit_ptr_28 == 6'h1a | archit_ptr_29 == 6'h1a | archit_ptr_30 == 6'h1a; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_26_T_64 = _log_reg_26_T_62 | archit_ptr_31 == 6'h1a ? log_reg_26 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_27_T_15 = archit_ptr_15 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  _log_reg_27_T_47 = archit_ptr_0 == 6'h1b | archit_ptr_1 == 6'h1b | archit_ptr_2 == 6'h1b | archit_ptr_3 == 6'h1b
     | archit_ptr_4 == 6'h1b | archit_ptr_5 == 6'h1b | archit_ptr_6 == 6'h1b | archit_ptr_7 == 6'h1b | archit_ptr_8 == 6'h1b
     | archit_ptr_9 == 6'h1b | archit_ptr_10 == 6'h1b | archit_ptr_11 == 6'h1b | archit_ptr_12 == 6'h1b | archit_ptr_13
     == 6'h1b | archit_ptr_14 == 6'h1b | _log_reg_27_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_27_T_62 = _log_reg_27_T_47 | archit_ptr_16 == 6'h1b | archit_ptr_17 == 6'h1b | archit_ptr_18 == 6'h1b
     | archit_ptr_19 == 6'h1b | archit_ptr_20 == 6'h1b | archit_ptr_21 == 6'h1b | archit_ptr_22 == 6'h1b | archit_ptr_23
     == 6'h1b | archit_ptr_24 == 6'h1b | archit_ptr_25 == 6'h1b | archit_ptr_26 == 6'h1b | archit_ptr_27 == 6'h1b |
    archit_ptr_28 == 6'h1b | archit_ptr_29 == 6'h1b | archit_ptr_30 == 6'h1b; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_27_T_64 = _log_reg_27_T_62 | archit_ptr_31 == 6'h1b ? log_reg_27 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_28_T_15 = archit_ptr_15 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  _log_reg_28_T_47 = archit_ptr_0 == 6'h1c | archit_ptr_1 == 6'h1c | archit_ptr_2 == 6'h1c | archit_ptr_3 == 6'h1c
     | archit_ptr_4 == 6'h1c | archit_ptr_5 == 6'h1c | archit_ptr_6 == 6'h1c | archit_ptr_7 == 6'h1c | archit_ptr_8 == 6'h1c
     | archit_ptr_9 == 6'h1c | archit_ptr_10 == 6'h1c | archit_ptr_11 == 6'h1c | archit_ptr_12 == 6'h1c | archit_ptr_13
     == 6'h1c | archit_ptr_14 == 6'h1c | _log_reg_28_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_28_T_62 = _log_reg_28_T_47 | archit_ptr_16 == 6'h1c | archit_ptr_17 == 6'h1c | archit_ptr_18 == 6'h1c
     | archit_ptr_19 == 6'h1c | archit_ptr_20 == 6'h1c | archit_ptr_21 == 6'h1c | archit_ptr_22 == 6'h1c | archit_ptr_23
     == 6'h1c | archit_ptr_24 == 6'h1c | archit_ptr_25 == 6'h1c | archit_ptr_26 == 6'h1c | archit_ptr_27 == 6'h1c |
    archit_ptr_28 == 6'h1c | archit_ptr_29 == 6'h1c | archit_ptr_30 == 6'h1c; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_28_T_64 = _log_reg_28_T_62 | archit_ptr_31 == 6'h1c ? log_reg_28 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_29_T_15 = archit_ptr_15 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  _log_reg_29_T_47 = archit_ptr_0 == 6'h1d | archit_ptr_1 == 6'h1d | archit_ptr_2 == 6'h1d | archit_ptr_3 == 6'h1d
     | archit_ptr_4 == 6'h1d | archit_ptr_5 == 6'h1d | archit_ptr_6 == 6'h1d | archit_ptr_7 == 6'h1d | archit_ptr_8 == 6'h1d
     | archit_ptr_9 == 6'h1d | archit_ptr_10 == 6'h1d | archit_ptr_11 == 6'h1d | archit_ptr_12 == 6'h1d | archit_ptr_13
     == 6'h1d | archit_ptr_14 == 6'h1d | _log_reg_29_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_29_T_62 = _log_reg_29_T_47 | archit_ptr_16 == 6'h1d | archit_ptr_17 == 6'h1d | archit_ptr_18 == 6'h1d
     | archit_ptr_19 == 6'h1d | archit_ptr_20 == 6'h1d | archit_ptr_21 == 6'h1d | archit_ptr_22 == 6'h1d | archit_ptr_23
     == 6'h1d | archit_ptr_24 == 6'h1d | archit_ptr_25 == 6'h1d | archit_ptr_26 == 6'h1d | archit_ptr_27 == 6'h1d |
    archit_ptr_28 == 6'h1d | archit_ptr_29 == 6'h1d | archit_ptr_30 == 6'h1d; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_29_T_64 = _log_reg_29_T_62 | archit_ptr_31 == 6'h1d ? log_reg_29 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_30_T_15 = archit_ptr_15 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  _log_reg_30_T_47 = archit_ptr_0 == 6'h1e | archit_ptr_1 == 6'h1e | archit_ptr_2 == 6'h1e | archit_ptr_3 == 6'h1e
     | archit_ptr_4 == 6'h1e | archit_ptr_5 == 6'h1e | archit_ptr_6 == 6'h1e | archit_ptr_7 == 6'h1e | archit_ptr_8 == 6'h1e
     | archit_ptr_9 == 6'h1e | archit_ptr_10 == 6'h1e | archit_ptr_11 == 6'h1e | archit_ptr_12 == 6'h1e | archit_ptr_13
     == 6'h1e | archit_ptr_14 == 6'h1e | _log_reg_30_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_30_T_62 = _log_reg_30_T_47 | archit_ptr_16 == 6'h1e | archit_ptr_17 == 6'h1e | archit_ptr_18 == 6'h1e
     | archit_ptr_19 == 6'h1e | archit_ptr_20 == 6'h1e | archit_ptr_21 == 6'h1e | archit_ptr_22 == 6'h1e | archit_ptr_23
     == 6'h1e | archit_ptr_24 == 6'h1e | archit_ptr_25 == 6'h1e | archit_ptr_26 == 6'h1e | archit_ptr_27 == 6'h1e |
    archit_ptr_28 == 6'h1e | archit_ptr_29 == 6'h1e | archit_ptr_30 == 6'h1e; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_30_T_64 = _log_reg_30_T_62 | archit_ptr_31 == 6'h1e ? log_reg_30 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_31_T_15 = archit_ptr_15 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  _log_reg_31_T_47 = archit_ptr_0 == 6'h1f | archit_ptr_1 == 6'h1f | archit_ptr_2 == 6'h1f | archit_ptr_3 == 6'h1f
     | archit_ptr_4 == 6'h1f | archit_ptr_5 == 6'h1f | archit_ptr_6 == 6'h1f | archit_ptr_7 == 6'h1f | archit_ptr_8 == 6'h1f
     | archit_ptr_9 == 6'h1f | archit_ptr_10 == 6'h1f | archit_ptr_11 == 6'h1f | archit_ptr_12 == 6'h1f | archit_ptr_13
     == 6'h1f | archit_ptr_14 == 6'h1f | _log_reg_31_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_31_T_62 = _log_reg_31_T_47 | archit_ptr_16 == 6'h1f | archit_ptr_17 == 6'h1f | archit_ptr_18 == 6'h1f
     | archit_ptr_19 == 6'h1f | archit_ptr_20 == 6'h1f | archit_ptr_21 == 6'h1f | archit_ptr_22 == 6'h1f | archit_ptr_23
     == 6'h1f | archit_ptr_24 == 6'h1f | archit_ptr_25 == 6'h1f | archit_ptr_26 == 6'h1f | archit_ptr_27 == 6'h1f |
    archit_ptr_28 == 6'h1f | archit_ptr_29 == 6'h1f | archit_ptr_30 == 6'h1f; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_31_T_64 = _log_reg_31_T_62 | archit_ptr_31 == 6'h1f ? log_reg_31 : 2'h0; // @[Regfiles.scala 223:63]
  wire  _log_reg_32_T_15 = archit_ptr_15 == 6'h20; // @[Regfiles.scala 223:99]
  wire  _log_reg_32_T_47 = archit_ptr_0 == 6'h20 | archit_ptr_1 == 6'h20 | archit_ptr_2 == 6'h20 | archit_ptr_3 == 6'h20
     | archit_ptr_4 == 6'h20 | archit_ptr_5 == 6'h20 | archit_ptr_6 == 6'h20 | archit_ptr_7 == 6'h20 | archit_ptr_8 == 6'h20
     | archit_ptr_9 == 6'h20 | archit_ptr_10 == 6'h20 | archit_ptr_11 == 6'h20 | archit_ptr_12 == 6'h20 | archit_ptr_13
     == 6'h20 | archit_ptr_14 == 6'h20 | _log_reg_32_T_15; // @[Regfiles.scala 223:82]
  wire  _log_reg_32_T_62 = _log_reg_32_T_47 | archit_ptr_16 == 6'h20 | archit_ptr_17 == 6'h20 | archit_ptr_18 == 6'h20
     | archit_ptr_19 == 6'h20 | archit_ptr_20 == 6'h20 | archit_ptr_21 == 6'h20 | archit_ptr_22 == 6'h20 | archit_ptr_23
     == 6'h20 | archit_ptr_24 == 6'h20 | archit_ptr_25 == 6'h20 | archit_ptr_26 == 6'h20 | archit_ptr_27 == 6'h20 |
    archit_ptr_28 == 6'h20 | archit_ptr_29 == 6'h20 | archit_ptr_30 == 6'h20; // @[Regfiles.scala 223:82]
  wire [1:0] _log_reg_32_T_64 = _log_reg_32_T_62 | archit_ptr_31 == 6'h20 ? log_reg_32 : 2'h0; // @[Regfiles.scala 223:63]
  wire [1:0] _GEN_1620 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_0_T_64 : _GEN_1520; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1621 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_1_T_64 : _GEN_1521; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1622 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_2_T_64 : _GEN_1522; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1623 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_3_T_64 : _GEN_1523; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1624 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_4_T_64 : _GEN_1524; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1625 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_5_T_64 : _GEN_1525; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1626 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_6_T_64 : _GEN_1526; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1627 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_7_T_64 : _GEN_1527; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1628 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_8_T_64 : _GEN_1528; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1629 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_9_T_64 : _GEN_1529; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1630 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_10_T_64 : _GEN_1530; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1631 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_11_T_64 : _GEN_1531; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1632 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_12_T_64 : _GEN_1532; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1633 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_13_T_64 : _GEN_1533; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1634 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_14_T_64 : _GEN_1534; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1635 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_15_T_64 : _GEN_1535; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1636 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_16_T_64 : _GEN_1536; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1637 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_17_T_64 : _GEN_1537; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1638 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_18_T_64 : _GEN_1538; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1639 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_19_T_64 : _GEN_1539; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1640 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_20_T_64 : _GEN_1540; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1641 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_21_T_64 : _GEN_1541; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1642 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_22_T_64 : _GEN_1542; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1643 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_23_T_64 : _GEN_1543; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1644 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_24_T_64 : _GEN_1544; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1645 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_25_T_64 : _GEN_1545; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1646 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_26_T_64 : _GEN_1546; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1647 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_27_T_64 : _GEN_1547; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1648 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_28_T_64 : _GEN_1548; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1649 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_29_T_64 : _GEN_1549; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1650 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_30_T_64 : _GEN_1550; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1651 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_31_T_64 : _GEN_1551; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] _GEN_1652 = io_commit_0_is_MisPredict | io_commit_0_is_abort ? _log_reg_32_T_64 : _GEN_1552; // @[Regfiles.scala 221:64 223:57]
  wire  _T_114 = io_commit_0_is_MisPredict | io_commit_0_is_comfirm; // @[Regfiles.scala 225:38]
  wire [5:0] _GEN_1654 = 5'h1 == io_commit_0_raw ? archit_ptr_1 : archit_ptr_0; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1655 = 5'h2 == io_commit_0_raw ? archit_ptr_2 : _GEN_1654; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1656 = 5'h3 == io_commit_0_raw ? archit_ptr_3 : _GEN_1655; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1657 = 5'h4 == io_commit_0_raw ? archit_ptr_4 : _GEN_1656; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1658 = 5'h5 == io_commit_0_raw ? archit_ptr_5 : _GEN_1657; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1659 = 5'h6 == io_commit_0_raw ? archit_ptr_6 : _GEN_1658; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1660 = 5'h7 == io_commit_0_raw ? archit_ptr_7 : _GEN_1659; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1661 = 5'h8 == io_commit_0_raw ? archit_ptr_8 : _GEN_1660; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1662 = 5'h9 == io_commit_0_raw ? archit_ptr_9 : _GEN_1661; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1663 = 5'ha == io_commit_0_raw ? archit_ptr_10 : _GEN_1662; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1664 = 5'hb == io_commit_0_raw ? archit_ptr_11 : _GEN_1663; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1665 = 5'hc == io_commit_0_raw ? archit_ptr_12 : _GEN_1664; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1666 = 5'hd == io_commit_0_raw ? archit_ptr_13 : _GEN_1665; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1667 = 5'he == io_commit_0_raw ? archit_ptr_14 : _GEN_1666; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1668 = 5'hf == io_commit_0_raw ? archit_ptr_15 : _GEN_1667; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1669 = 5'h10 == io_commit_0_raw ? archit_ptr_16 : _GEN_1668; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1670 = 5'h11 == io_commit_0_raw ? archit_ptr_17 : _GEN_1669; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1671 = 5'h12 == io_commit_0_raw ? archit_ptr_18 : _GEN_1670; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1672 = 5'h13 == io_commit_0_raw ? archit_ptr_19 : _GEN_1671; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1673 = 5'h14 == io_commit_0_raw ? archit_ptr_20 : _GEN_1672; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1674 = 5'h15 == io_commit_0_raw ? archit_ptr_21 : _GEN_1673; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1675 = 5'h16 == io_commit_0_raw ? archit_ptr_22 : _GEN_1674; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1676 = 5'h17 == io_commit_0_raw ? archit_ptr_23 : _GEN_1675; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1677 = 5'h18 == io_commit_0_raw ? archit_ptr_24 : _GEN_1676; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1678 = 5'h19 == io_commit_0_raw ? archit_ptr_25 : _GEN_1677; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1679 = 5'h1a == io_commit_0_raw ? archit_ptr_26 : _GEN_1678; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1680 = 5'h1b == io_commit_0_raw ? archit_ptr_27 : _GEN_1679; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1681 = 5'h1c == io_commit_0_raw ? archit_ptr_28 : _GEN_1680; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1682 = 5'h1d == io_commit_0_raw ? archit_ptr_29 : _GEN_1681; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1683 = 5'h1e == io_commit_0_raw ? archit_ptr_30 : _GEN_1682; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] _GEN_1684 = 5'h1f == io_commit_0_raw ? archit_ptr_31 : _GEN_1683; // @[Regfiles.scala 229:{18,18}]
  wire [1:0] _GEN_1882 = 6'h1 == archit_ptr_0 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1883 = 6'h2 == archit_ptr_0 ? log_reg_2 : _GEN_1882; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1884 = 6'h3 == archit_ptr_0 ? log_reg_3 : _GEN_1883; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1885 = 6'h4 == archit_ptr_0 ? log_reg_4 : _GEN_1884; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1886 = 6'h5 == archit_ptr_0 ? log_reg_5 : _GEN_1885; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1887 = 6'h6 == archit_ptr_0 ? log_reg_6 : _GEN_1886; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1888 = 6'h7 == archit_ptr_0 ? log_reg_7 : _GEN_1887; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1889 = 6'h8 == archit_ptr_0 ? log_reg_8 : _GEN_1888; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1890 = 6'h9 == archit_ptr_0 ? log_reg_9 : _GEN_1889; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1891 = 6'ha == archit_ptr_0 ? log_reg_10 : _GEN_1890; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1892 = 6'hb == archit_ptr_0 ? log_reg_11 : _GEN_1891; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1893 = 6'hc == archit_ptr_0 ? log_reg_12 : _GEN_1892; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1894 = 6'hd == archit_ptr_0 ? log_reg_13 : _GEN_1893; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1895 = 6'he == archit_ptr_0 ? log_reg_14 : _GEN_1894; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1896 = 6'hf == archit_ptr_0 ? log_reg_15 : _GEN_1895; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1897 = 6'h10 == archit_ptr_0 ? log_reg_16 : _GEN_1896; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1898 = 6'h11 == archit_ptr_0 ? log_reg_17 : _GEN_1897; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1899 = 6'h12 == archit_ptr_0 ? log_reg_18 : _GEN_1898; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1900 = 6'h13 == archit_ptr_0 ? log_reg_19 : _GEN_1899; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1901 = 6'h14 == archit_ptr_0 ? log_reg_20 : _GEN_1900; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1902 = 6'h15 == archit_ptr_0 ? log_reg_21 : _GEN_1901; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1903 = 6'h16 == archit_ptr_0 ? log_reg_22 : _GEN_1902; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1904 = 6'h17 == archit_ptr_0 ? log_reg_23 : _GEN_1903; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1905 = 6'h18 == archit_ptr_0 ? log_reg_24 : _GEN_1904; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1906 = 6'h19 == archit_ptr_0 ? log_reg_25 : _GEN_1905; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1907 = 6'h1a == archit_ptr_0 ? log_reg_26 : _GEN_1906; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1908 = 6'h1b == archit_ptr_0 ? log_reg_27 : _GEN_1907; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1909 = 6'h1c == archit_ptr_0 ? log_reg_28 : _GEN_1908; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1910 = 6'h1d == archit_ptr_0 ? log_reg_29 : _GEN_1909; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1911 = 6'h1e == archit_ptr_0 ? log_reg_30 : _GEN_1910; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1912 = 6'h1f == archit_ptr_0 ? log_reg_31 : _GEN_1911; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1913 = 6'h20 == archit_ptr_0 ? log_reg_32 : _GEN_1912; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1914 = 6'h21 == archit_ptr_0 ? 2'h3 : _GEN_1913; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1916 = 6'h1 == archit_ptr_1 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1917 = 6'h2 == archit_ptr_1 ? log_reg_2 : _GEN_1916; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1918 = 6'h3 == archit_ptr_1 ? log_reg_3 : _GEN_1917; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1919 = 6'h4 == archit_ptr_1 ? log_reg_4 : _GEN_1918; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1920 = 6'h5 == archit_ptr_1 ? log_reg_5 : _GEN_1919; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1921 = 6'h6 == archit_ptr_1 ? log_reg_6 : _GEN_1920; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1922 = 6'h7 == archit_ptr_1 ? log_reg_7 : _GEN_1921; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1923 = 6'h8 == archit_ptr_1 ? log_reg_8 : _GEN_1922; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1924 = 6'h9 == archit_ptr_1 ? log_reg_9 : _GEN_1923; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1925 = 6'ha == archit_ptr_1 ? log_reg_10 : _GEN_1924; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1926 = 6'hb == archit_ptr_1 ? log_reg_11 : _GEN_1925; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1927 = 6'hc == archit_ptr_1 ? log_reg_12 : _GEN_1926; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1928 = 6'hd == archit_ptr_1 ? log_reg_13 : _GEN_1927; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1929 = 6'he == archit_ptr_1 ? log_reg_14 : _GEN_1928; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1930 = 6'hf == archit_ptr_1 ? log_reg_15 : _GEN_1929; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1931 = 6'h10 == archit_ptr_1 ? log_reg_16 : _GEN_1930; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1932 = 6'h11 == archit_ptr_1 ? log_reg_17 : _GEN_1931; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1933 = 6'h12 == archit_ptr_1 ? log_reg_18 : _GEN_1932; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1934 = 6'h13 == archit_ptr_1 ? log_reg_19 : _GEN_1933; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1935 = 6'h14 == archit_ptr_1 ? log_reg_20 : _GEN_1934; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1936 = 6'h15 == archit_ptr_1 ? log_reg_21 : _GEN_1935; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1937 = 6'h16 == archit_ptr_1 ? log_reg_22 : _GEN_1936; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1938 = 6'h17 == archit_ptr_1 ? log_reg_23 : _GEN_1937; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1939 = 6'h18 == archit_ptr_1 ? log_reg_24 : _GEN_1938; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1940 = 6'h19 == archit_ptr_1 ? log_reg_25 : _GEN_1939; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1941 = 6'h1a == archit_ptr_1 ? log_reg_26 : _GEN_1940; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1942 = 6'h1b == archit_ptr_1 ? log_reg_27 : _GEN_1941; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1943 = 6'h1c == archit_ptr_1 ? log_reg_28 : _GEN_1942; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1944 = 6'h1d == archit_ptr_1 ? log_reg_29 : _GEN_1943; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1945 = 6'h1e == archit_ptr_1 ? log_reg_30 : _GEN_1944; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1946 = 6'h1f == archit_ptr_1 ? log_reg_31 : _GEN_1945; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1947 = 6'h20 == archit_ptr_1 ? log_reg_32 : _GEN_1946; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1948 = 6'h21 == archit_ptr_1 ? 2'h3 : _GEN_1947; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1950 = 6'h1 == archit_ptr_2 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1951 = 6'h2 == archit_ptr_2 ? log_reg_2 : _GEN_1950; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1952 = 6'h3 == archit_ptr_2 ? log_reg_3 : _GEN_1951; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1953 = 6'h4 == archit_ptr_2 ? log_reg_4 : _GEN_1952; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1954 = 6'h5 == archit_ptr_2 ? log_reg_5 : _GEN_1953; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1955 = 6'h6 == archit_ptr_2 ? log_reg_6 : _GEN_1954; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1956 = 6'h7 == archit_ptr_2 ? log_reg_7 : _GEN_1955; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1957 = 6'h8 == archit_ptr_2 ? log_reg_8 : _GEN_1956; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1958 = 6'h9 == archit_ptr_2 ? log_reg_9 : _GEN_1957; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1959 = 6'ha == archit_ptr_2 ? log_reg_10 : _GEN_1958; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1960 = 6'hb == archit_ptr_2 ? log_reg_11 : _GEN_1959; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1961 = 6'hc == archit_ptr_2 ? log_reg_12 : _GEN_1960; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1962 = 6'hd == archit_ptr_2 ? log_reg_13 : _GEN_1961; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1963 = 6'he == archit_ptr_2 ? log_reg_14 : _GEN_1962; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1964 = 6'hf == archit_ptr_2 ? log_reg_15 : _GEN_1963; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1965 = 6'h10 == archit_ptr_2 ? log_reg_16 : _GEN_1964; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1966 = 6'h11 == archit_ptr_2 ? log_reg_17 : _GEN_1965; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1967 = 6'h12 == archit_ptr_2 ? log_reg_18 : _GEN_1966; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1968 = 6'h13 == archit_ptr_2 ? log_reg_19 : _GEN_1967; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1969 = 6'h14 == archit_ptr_2 ? log_reg_20 : _GEN_1968; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1970 = 6'h15 == archit_ptr_2 ? log_reg_21 : _GEN_1969; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1971 = 6'h16 == archit_ptr_2 ? log_reg_22 : _GEN_1970; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1972 = 6'h17 == archit_ptr_2 ? log_reg_23 : _GEN_1971; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1973 = 6'h18 == archit_ptr_2 ? log_reg_24 : _GEN_1972; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1974 = 6'h19 == archit_ptr_2 ? log_reg_25 : _GEN_1973; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1975 = 6'h1a == archit_ptr_2 ? log_reg_26 : _GEN_1974; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1976 = 6'h1b == archit_ptr_2 ? log_reg_27 : _GEN_1975; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1977 = 6'h1c == archit_ptr_2 ? log_reg_28 : _GEN_1976; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1978 = 6'h1d == archit_ptr_2 ? log_reg_29 : _GEN_1977; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1979 = 6'h1e == archit_ptr_2 ? log_reg_30 : _GEN_1978; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1980 = 6'h1f == archit_ptr_2 ? log_reg_31 : _GEN_1979; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1981 = 6'h20 == archit_ptr_2 ? log_reg_32 : _GEN_1980; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1982 = 6'h21 == archit_ptr_2 ? 2'h3 : _GEN_1981; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1984 = 6'h1 == archit_ptr_3 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1985 = 6'h2 == archit_ptr_3 ? log_reg_2 : _GEN_1984; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1986 = 6'h3 == archit_ptr_3 ? log_reg_3 : _GEN_1985; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1987 = 6'h4 == archit_ptr_3 ? log_reg_4 : _GEN_1986; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1988 = 6'h5 == archit_ptr_3 ? log_reg_5 : _GEN_1987; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1989 = 6'h6 == archit_ptr_3 ? log_reg_6 : _GEN_1988; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1990 = 6'h7 == archit_ptr_3 ? log_reg_7 : _GEN_1989; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1991 = 6'h8 == archit_ptr_3 ? log_reg_8 : _GEN_1990; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1992 = 6'h9 == archit_ptr_3 ? log_reg_9 : _GEN_1991; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1993 = 6'ha == archit_ptr_3 ? log_reg_10 : _GEN_1992; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1994 = 6'hb == archit_ptr_3 ? log_reg_11 : _GEN_1993; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1995 = 6'hc == archit_ptr_3 ? log_reg_12 : _GEN_1994; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1996 = 6'hd == archit_ptr_3 ? log_reg_13 : _GEN_1995; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1997 = 6'he == archit_ptr_3 ? log_reg_14 : _GEN_1996; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1998 = 6'hf == archit_ptr_3 ? log_reg_15 : _GEN_1997; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_1999 = 6'h10 == archit_ptr_3 ? log_reg_16 : _GEN_1998; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2000 = 6'h11 == archit_ptr_3 ? log_reg_17 : _GEN_1999; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2001 = 6'h12 == archit_ptr_3 ? log_reg_18 : _GEN_2000; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2002 = 6'h13 == archit_ptr_3 ? log_reg_19 : _GEN_2001; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2003 = 6'h14 == archit_ptr_3 ? log_reg_20 : _GEN_2002; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2004 = 6'h15 == archit_ptr_3 ? log_reg_21 : _GEN_2003; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2005 = 6'h16 == archit_ptr_3 ? log_reg_22 : _GEN_2004; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2006 = 6'h17 == archit_ptr_3 ? log_reg_23 : _GEN_2005; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2007 = 6'h18 == archit_ptr_3 ? log_reg_24 : _GEN_2006; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2008 = 6'h19 == archit_ptr_3 ? log_reg_25 : _GEN_2007; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2009 = 6'h1a == archit_ptr_3 ? log_reg_26 : _GEN_2008; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2010 = 6'h1b == archit_ptr_3 ? log_reg_27 : _GEN_2009; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2011 = 6'h1c == archit_ptr_3 ? log_reg_28 : _GEN_2010; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2012 = 6'h1d == archit_ptr_3 ? log_reg_29 : _GEN_2011; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2013 = 6'h1e == archit_ptr_3 ? log_reg_30 : _GEN_2012; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2014 = 6'h1f == archit_ptr_3 ? log_reg_31 : _GEN_2013; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2015 = 6'h20 == archit_ptr_3 ? log_reg_32 : _GEN_2014; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2016 = 6'h21 == archit_ptr_3 ? 2'h3 : _GEN_2015; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2018 = 6'h1 == archit_ptr_4 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2019 = 6'h2 == archit_ptr_4 ? log_reg_2 : _GEN_2018; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2020 = 6'h3 == archit_ptr_4 ? log_reg_3 : _GEN_2019; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2021 = 6'h4 == archit_ptr_4 ? log_reg_4 : _GEN_2020; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2022 = 6'h5 == archit_ptr_4 ? log_reg_5 : _GEN_2021; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2023 = 6'h6 == archit_ptr_4 ? log_reg_6 : _GEN_2022; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2024 = 6'h7 == archit_ptr_4 ? log_reg_7 : _GEN_2023; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2025 = 6'h8 == archit_ptr_4 ? log_reg_8 : _GEN_2024; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2026 = 6'h9 == archit_ptr_4 ? log_reg_9 : _GEN_2025; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2027 = 6'ha == archit_ptr_4 ? log_reg_10 : _GEN_2026; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2028 = 6'hb == archit_ptr_4 ? log_reg_11 : _GEN_2027; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2029 = 6'hc == archit_ptr_4 ? log_reg_12 : _GEN_2028; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2030 = 6'hd == archit_ptr_4 ? log_reg_13 : _GEN_2029; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2031 = 6'he == archit_ptr_4 ? log_reg_14 : _GEN_2030; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2032 = 6'hf == archit_ptr_4 ? log_reg_15 : _GEN_2031; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2033 = 6'h10 == archit_ptr_4 ? log_reg_16 : _GEN_2032; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2034 = 6'h11 == archit_ptr_4 ? log_reg_17 : _GEN_2033; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2035 = 6'h12 == archit_ptr_4 ? log_reg_18 : _GEN_2034; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2036 = 6'h13 == archit_ptr_4 ? log_reg_19 : _GEN_2035; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2037 = 6'h14 == archit_ptr_4 ? log_reg_20 : _GEN_2036; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2038 = 6'h15 == archit_ptr_4 ? log_reg_21 : _GEN_2037; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2039 = 6'h16 == archit_ptr_4 ? log_reg_22 : _GEN_2038; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2040 = 6'h17 == archit_ptr_4 ? log_reg_23 : _GEN_2039; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2041 = 6'h18 == archit_ptr_4 ? log_reg_24 : _GEN_2040; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2042 = 6'h19 == archit_ptr_4 ? log_reg_25 : _GEN_2041; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2043 = 6'h1a == archit_ptr_4 ? log_reg_26 : _GEN_2042; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2044 = 6'h1b == archit_ptr_4 ? log_reg_27 : _GEN_2043; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2045 = 6'h1c == archit_ptr_4 ? log_reg_28 : _GEN_2044; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2046 = 6'h1d == archit_ptr_4 ? log_reg_29 : _GEN_2045; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2047 = 6'h1e == archit_ptr_4 ? log_reg_30 : _GEN_2046; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2048 = 6'h1f == archit_ptr_4 ? log_reg_31 : _GEN_2047; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2049 = 6'h20 == archit_ptr_4 ? log_reg_32 : _GEN_2048; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2050 = 6'h21 == archit_ptr_4 ? 2'h3 : _GEN_2049; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2052 = 6'h1 == archit_ptr_5 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2053 = 6'h2 == archit_ptr_5 ? log_reg_2 : _GEN_2052; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2054 = 6'h3 == archit_ptr_5 ? log_reg_3 : _GEN_2053; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2055 = 6'h4 == archit_ptr_5 ? log_reg_4 : _GEN_2054; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2056 = 6'h5 == archit_ptr_5 ? log_reg_5 : _GEN_2055; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2057 = 6'h6 == archit_ptr_5 ? log_reg_6 : _GEN_2056; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2058 = 6'h7 == archit_ptr_5 ? log_reg_7 : _GEN_2057; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2059 = 6'h8 == archit_ptr_5 ? log_reg_8 : _GEN_2058; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2060 = 6'h9 == archit_ptr_5 ? log_reg_9 : _GEN_2059; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2061 = 6'ha == archit_ptr_5 ? log_reg_10 : _GEN_2060; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2062 = 6'hb == archit_ptr_5 ? log_reg_11 : _GEN_2061; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2063 = 6'hc == archit_ptr_5 ? log_reg_12 : _GEN_2062; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2064 = 6'hd == archit_ptr_5 ? log_reg_13 : _GEN_2063; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2065 = 6'he == archit_ptr_5 ? log_reg_14 : _GEN_2064; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2066 = 6'hf == archit_ptr_5 ? log_reg_15 : _GEN_2065; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2067 = 6'h10 == archit_ptr_5 ? log_reg_16 : _GEN_2066; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2068 = 6'h11 == archit_ptr_5 ? log_reg_17 : _GEN_2067; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2069 = 6'h12 == archit_ptr_5 ? log_reg_18 : _GEN_2068; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2070 = 6'h13 == archit_ptr_5 ? log_reg_19 : _GEN_2069; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2071 = 6'h14 == archit_ptr_5 ? log_reg_20 : _GEN_2070; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2072 = 6'h15 == archit_ptr_5 ? log_reg_21 : _GEN_2071; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2073 = 6'h16 == archit_ptr_5 ? log_reg_22 : _GEN_2072; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2074 = 6'h17 == archit_ptr_5 ? log_reg_23 : _GEN_2073; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2075 = 6'h18 == archit_ptr_5 ? log_reg_24 : _GEN_2074; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2076 = 6'h19 == archit_ptr_5 ? log_reg_25 : _GEN_2075; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2077 = 6'h1a == archit_ptr_5 ? log_reg_26 : _GEN_2076; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2078 = 6'h1b == archit_ptr_5 ? log_reg_27 : _GEN_2077; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2079 = 6'h1c == archit_ptr_5 ? log_reg_28 : _GEN_2078; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2080 = 6'h1d == archit_ptr_5 ? log_reg_29 : _GEN_2079; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2081 = 6'h1e == archit_ptr_5 ? log_reg_30 : _GEN_2080; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2082 = 6'h1f == archit_ptr_5 ? log_reg_31 : _GEN_2081; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2083 = 6'h20 == archit_ptr_5 ? log_reg_32 : _GEN_2082; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2084 = 6'h21 == archit_ptr_5 ? 2'h3 : _GEN_2083; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2086 = 6'h1 == archit_ptr_6 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2087 = 6'h2 == archit_ptr_6 ? log_reg_2 : _GEN_2086; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2088 = 6'h3 == archit_ptr_6 ? log_reg_3 : _GEN_2087; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2089 = 6'h4 == archit_ptr_6 ? log_reg_4 : _GEN_2088; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2090 = 6'h5 == archit_ptr_6 ? log_reg_5 : _GEN_2089; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2091 = 6'h6 == archit_ptr_6 ? log_reg_6 : _GEN_2090; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2092 = 6'h7 == archit_ptr_6 ? log_reg_7 : _GEN_2091; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2093 = 6'h8 == archit_ptr_6 ? log_reg_8 : _GEN_2092; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2094 = 6'h9 == archit_ptr_6 ? log_reg_9 : _GEN_2093; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2095 = 6'ha == archit_ptr_6 ? log_reg_10 : _GEN_2094; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2096 = 6'hb == archit_ptr_6 ? log_reg_11 : _GEN_2095; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2097 = 6'hc == archit_ptr_6 ? log_reg_12 : _GEN_2096; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2098 = 6'hd == archit_ptr_6 ? log_reg_13 : _GEN_2097; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2099 = 6'he == archit_ptr_6 ? log_reg_14 : _GEN_2098; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2100 = 6'hf == archit_ptr_6 ? log_reg_15 : _GEN_2099; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2101 = 6'h10 == archit_ptr_6 ? log_reg_16 : _GEN_2100; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2102 = 6'h11 == archit_ptr_6 ? log_reg_17 : _GEN_2101; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2103 = 6'h12 == archit_ptr_6 ? log_reg_18 : _GEN_2102; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2104 = 6'h13 == archit_ptr_6 ? log_reg_19 : _GEN_2103; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2105 = 6'h14 == archit_ptr_6 ? log_reg_20 : _GEN_2104; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2106 = 6'h15 == archit_ptr_6 ? log_reg_21 : _GEN_2105; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2107 = 6'h16 == archit_ptr_6 ? log_reg_22 : _GEN_2106; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2108 = 6'h17 == archit_ptr_6 ? log_reg_23 : _GEN_2107; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2109 = 6'h18 == archit_ptr_6 ? log_reg_24 : _GEN_2108; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2110 = 6'h19 == archit_ptr_6 ? log_reg_25 : _GEN_2109; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2111 = 6'h1a == archit_ptr_6 ? log_reg_26 : _GEN_2110; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2112 = 6'h1b == archit_ptr_6 ? log_reg_27 : _GEN_2111; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2113 = 6'h1c == archit_ptr_6 ? log_reg_28 : _GEN_2112; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2114 = 6'h1d == archit_ptr_6 ? log_reg_29 : _GEN_2113; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2115 = 6'h1e == archit_ptr_6 ? log_reg_30 : _GEN_2114; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2116 = 6'h1f == archit_ptr_6 ? log_reg_31 : _GEN_2115; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2117 = 6'h20 == archit_ptr_6 ? log_reg_32 : _GEN_2116; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2118 = 6'h21 == archit_ptr_6 ? 2'h3 : _GEN_2117; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2120 = 6'h1 == archit_ptr_7 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2121 = 6'h2 == archit_ptr_7 ? log_reg_2 : _GEN_2120; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2122 = 6'h3 == archit_ptr_7 ? log_reg_3 : _GEN_2121; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2123 = 6'h4 == archit_ptr_7 ? log_reg_4 : _GEN_2122; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2124 = 6'h5 == archit_ptr_7 ? log_reg_5 : _GEN_2123; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2125 = 6'h6 == archit_ptr_7 ? log_reg_6 : _GEN_2124; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2126 = 6'h7 == archit_ptr_7 ? log_reg_7 : _GEN_2125; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2127 = 6'h8 == archit_ptr_7 ? log_reg_8 : _GEN_2126; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2128 = 6'h9 == archit_ptr_7 ? log_reg_9 : _GEN_2127; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2129 = 6'ha == archit_ptr_7 ? log_reg_10 : _GEN_2128; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2130 = 6'hb == archit_ptr_7 ? log_reg_11 : _GEN_2129; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2131 = 6'hc == archit_ptr_7 ? log_reg_12 : _GEN_2130; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2132 = 6'hd == archit_ptr_7 ? log_reg_13 : _GEN_2131; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2133 = 6'he == archit_ptr_7 ? log_reg_14 : _GEN_2132; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2134 = 6'hf == archit_ptr_7 ? log_reg_15 : _GEN_2133; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2135 = 6'h10 == archit_ptr_7 ? log_reg_16 : _GEN_2134; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2136 = 6'h11 == archit_ptr_7 ? log_reg_17 : _GEN_2135; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2137 = 6'h12 == archit_ptr_7 ? log_reg_18 : _GEN_2136; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2138 = 6'h13 == archit_ptr_7 ? log_reg_19 : _GEN_2137; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2139 = 6'h14 == archit_ptr_7 ? log_reg_20 : _GEN_2138; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2140 = 6'h15 == archit_ptr_7 ? log_reg_21 : _GEN_2139; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2141 = 6'h16 == archit_ptr_7 ? log_reg_22 : _GEN_2140; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2142 = 6'h17 == archit_ptr_7 ? log_reg_23 : _GEN_2141; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2143 = 6'h18 == archit_ptr_7 ? log_reg_24 : _GEN_2142; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2144 = 6'h19 == archit_ptr_7 ? log_reg_25 : _GEN_2143; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2145 = 6'h1a == archit_ptr_7 ? log_reg_26 : _GEN_2144; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2146 = 6'h1b == archit_ptr_7 ? log_reg_27 : _GEN_2145; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2147 = 6'h1c == archit_ptr_7 ? log_reg_28 : _GEN_2146; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2148 = 6'h1d == archit_ptr_7 ? log_reg_29 : _GEN_2147; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2149 = 6'h1e == archit_ptr_7 ? log_reg_30 : _GEN_2148; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2150 = 6'h1f == archit_ptr_7 ? log_reg_31 : _GEN_2149; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2151 = 6'h20 == archit_ptr_7 ? log_reg_32 : _GEN_2150; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2152 = 6'h21 == archit_ptr_7 ? 2'h3 : _GEN_2151; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2154 = 6'h1 == archit_ptr_8 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2155 = 6'h2 == archit_ptr_8 ? log_reg_2 : _GEN_2154; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2156 = 6'h3 == archit_ptr_8 ? log_reg_3 : _GEN_2155; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2157 = 6'h4 == archit_ptr_8 ? log_reg_4 : _GEN_2156; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2158 = 6'h5 == archit_ptr_8 ? log_reg_5 : _GEN_2157; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2159 = 6'h6 == archit_ptr_8 ? log_reg_6 : _GEN_2158; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2160 = 6'h7 == archit_ptr_8 ? log_reg_7 : _GEN_2159; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2161 = 6'h8 == archit_ptr_8 ? log_reg_8 : _GEN_2160; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2162 = 6'h9 == archit_ptr_8 ? log_reg_9 : _GEN_2161; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2163 = 6'ha == archit_ptr_8 ? log_reg_10 : _GEN_2162; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2164 = 6'hb == archit_ptr_8 ? log_reg_11 : _GEN_2163; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2165 = 6'hc == archit_ptr_8 ? log_reg_12 : _GEN_2164; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2166 = 6'hd == archit_ptr_8 ? log_reg_13 : _GEN_2165; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2167 = 6'he == archit_ptr_8 ? log_reg_14 : _GEN_2166; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2168 = 6'hf == archit_ptr_8 ? log_reg_15 : _GEN_2167; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2169 = 6'h10 == archit_ptr_8 ? log_reg_16 : _GEN_2168; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2170 = 6'h11 == archit_ptr_8 ? log_reg_17 : _GEN_2169; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2171 = 6'h12 == archit_ptr_8 ? log_reg_18 : _GEN_2170; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2172 = 6'h13 == archit_ptr_8 ? log_reg_19 : _GEN_2171; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2173 = 6'h14 == archit_ptr_8 ? log_reg_20 : _GEN_2172; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2174 = 6'h15 == archit_ptr_8 ? log_reg_21 : _GEN_2173; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2175 = 6'h16 == archit_ptr_8 ? log_reg_22 : _GEN_2174; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2176 = 6'h17 == archit_ptr_8 ? log_reg_23 : _GEN_2175; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2177 = 6'h18 == archit_ptr_8 ? log_reg_24 : _GEN_2176; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2178 = 6'h19 == archit_ptr_8 ? log_reg_25 : _GEN_2177; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2179 = 6'h1a == archit_ptr_8 ? log_reg_26 : _GEN_2178; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2180 = 6'h1b == archit_ptr_8 ? log_reg_27 : _GEN_2179; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2181 = 6'h1c == archit_ptr_8 ? log_reg_28 : _GEN_2180; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2182 = 6'h1d == archit_ptr_8 ? log_reg_29 : _GEN_2181; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2183 = 6'h1e == archit_ptr_8 ? log_reg_30 : _GEN_2182; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2184 = 6'h1f == archit_ptr_8 ? log_reg_31 : _GEN_2183; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2185 = 6'h20 == archit_ptr_8 ? log_reg_32 : _GEN_2184; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2186 = 6'h21 == archit_ptr_8 ? 2'h3 : _GEN_2185; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2188 = 6'h1 == archit_ptr_9 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2189 = 6'h2 == archit_ptr_9 ? log_reg_2 : _GEN_2188; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2190 = 6'h3 == archit_ptr_9 ? log_reg_3 : _GEN_2189; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2191 = 6'h4 == archit_ptr_9 ? log_reg_4 : _GEN_2190; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2192 = 6'h5 == archit_ptr_9 ? log_reg_5 : _GEN_2191; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2193 = 6'h6 == archit_ptr_9 ? log_reg_6 : _GEN_2192; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2194 = 6'h7 == archit_ptr_9 ? log_reg_7 : _GEN_2193; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2195 = 6'h8 == archit_ptr_9 ? log_reg_8 : _GEN_2194; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2196 = 6'h9 == archit_ptr_9 ? log_reg_9 : _GEN_2195; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2197 = 6'ha == archit_ptr_9 ? log_reg_10 : _GEN_2196; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2198 = 6'hb == archit_ptr_9 ? log_reg_11 : _GEN_2197; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2199 = 6'hc == archit_ptr_9 ? log_reg_12 : _GEN_2198; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2200 = 6'hd == archit_ptr_9 ? log_reg_13 : _GEN_2199; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2201 = 6'he == archit_ptr_9 ? log_reg_14 : _GEN_2200; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2202 = 6'hf == archit_ptr_9 ? log_reg_15 : _GEN_2201; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2203 = 6'h10 == archit_ptr_9 ? log_reg_16 : _GEN_2202; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2204 = 6'h11 == archit_ptr_9 ? log_reg_17 : _GEN_2203; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2205 = 6'h12 == archit_ptr_9 ? log_reg_18 : _GEN_2204; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2206 = 6'h13 == archit_ptr_9 ? log_reg_19 : _GEN_2205; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2207 = 6'h14 == archit_ptr_9 ? log_reg_20 : _GEN_2206; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2208 = 6'h15 == archit_ptr_9 ? log_reg_21 : _GEN_2207; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2209 = 6'h16 == archit_ptr_9 ? log_reg_22 : _GEN_2208; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2210 = 6'h17 == archit_ptr_9 ? log_reg_23 : _GEN_2209; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2211 = 6'h18 == archit_ptr_9 ? log_reg_24 : _GEN_2210; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2212 = 6'h19 == archit_ptr_9 ? log_reg_25 : _GEN_2211; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2213 = 6'h1a == archit_ptr_9 ? log_reg_26 : _GEN_2212; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2214 = 6'h1b == archit_ptr_9 ? log_reg_27 : _GEN_2213; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2215 = 6'h1c == archit_ptr_9 ? log_reg_28 : _GEN_2214; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2216 = 6'h1d == archit_ptr_9 ? log_reg_29 : _GEN_2215; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2217 = 6'h1e == archit_ptr_9 ? log_reg_30 : _GEN_2216; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2218 = 6'h1f == archit_ptr_9 ? log_reg_31 : _GEN_2217; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2219 = 6'h20 == archit_ptr_9 ? log_reg_32 : _GEN_2218; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2220 = 6'h21 == archit_ptr_9 ? 2'h3 : _GEN_2219; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2222 = 6'h1 == archit_ptr_10 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2223 = 6'h2 == archit_ptr_10 ? log_reg_2 : _GEN_2222; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2224 = 6'h3 == archit_ptr_10 ? log_reg_3 : _GEN_2223; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2225 = 6'h4 == archit_ptr_10 ? log_reg_4 : _GEN_2224; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2226 = 6'h5 == archit_ptr_10 ? log_reg_5 : _GEN_2225; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2227 = 6'h6 == archit_ptr_10 ? log_reg_6 : _GEN_2226; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2228 = 6'h7 == archit_ptr_10 ? log_reg_7 : _GEN_2227; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2229 = 6'h8 == archit_ptr_10 ? log_reg_8 : _GEN_2228; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2230 = 6'h9 == archit_ptr_10 ? log_reg_9 : _GEN_2229; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2231 = 6'ha == archit_ptr_10 ? log_reg_10 : _GEN_2230; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2232 = 6'hb == archit_ptr_10 ? log_reg_11 : _GEN_2231; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2233 = 6'hc == archit_ptr_10 ? log_reg_12 : _GEN_2232; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2234 = 6'hd == archit_ptr_10 ? log_reg_13 : _GEN_2233; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2235 = 6'he == archit_ptr_10 ? log_reg_14 : _GEN_2234; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2236 = 6'hf == archit_ptr_10 ? log_reg_15 : _GEN_2235; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2237 = 6'h10 == archit_ptr_10 ? log_reg_16 : _GEN_2236; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2238 = 6'h11 == archit_ptr_10 ? log_reg_17 : _GEN_2237; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2239 = 6'h12 == archit_ptr_10 ? log_reg_18 : _GEN_2238; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2240 = 6'h13 == archit_ptr_10 ? log_reg_19 : _GEN_2239; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2241 = 6'h14 == archit_ptr_10 ? log_reg_20 : _GEN_2240; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2242 = 6'h15 == archit_ptr_10 ? log_reg_21 : _GEN_2241; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2243 = 6'h16 == archit_ptr_10 ? log_reg_22 : _GEN_2242; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2244 = 6'h17 == archit_ptr_10 ? log_reg_23 : _GEN_2243; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2245 = 6'h18 == archit_ptr_10 ? log_reg_24 : _GEN_2244; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2246 = 6'h19 == archit_ptr_10 ? log_reg_25 : _GEN_2245; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2247 = 6'h1a == archit_ptr_10 ? log_reg_26 : _GEN_2246; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2248 = 6'h1b == archit_ptr_10 ? log_reg_27 : _GEN_2247; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2249 = 6'h1c == archit_ptr_10 ? log_reg_28 : _GEN_2248; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2250 = 6'h1d == archit_ptr_10 ? log_reg_29 : _GEN_2249; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2251 = 6'h1e == archit_ptr_10 ? log_reg_30 : _GEN_2250; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2252 = 6'h1f == archit_ptr_10 ? log_reg_31 : _GEN_2251; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2253 = 6'h20 == archit_ptr_10 ? log_reg_32 : _GEN_2252; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2254 = 6'h21 == archit_ptr_10 ? 2'h3 : _GEN_2253; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2256 = 6'h1 == archit_ptr_11 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2257 = 6'h2 == archit_ptr_11 ? log_reg_2 : _GEN_2256; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2258 = 6'h3 == archit_ptr_11 ? log_reg_3 : _GEN_2257; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2259 = 6'h4 == archit_ptr_11 ? log_reg_4 : _GEN_2258; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2260 = 6'h5 == archit_ptr_11 ? log_reg_5 : _GEN_2259; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2261 = 6'h6 == archit_ptr_11 ? log_reg_6 : _GEN_2260; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2262 = 6'h7 == archit_ptr_11 ? log_reg_7 : _GEN_2261; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2263 = 6'h8 == archit_ptr_11 ? log_reg_8 : _GEN_2262; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2264 = 6'h9 == archit_ptr_11 ? log_reg_9 : _GEN_2263; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2265 = 6'ha == archit_ptr_11 ? log_reg_10 : _GEN_2264; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2266 = 6'hb == archit_ptr_11 ? log_reg_11 : _GEN_2265; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2267 = 6'hc == archit_ptr_11 ? log_reg_12 : _GEN_2266; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2268 = 6'hd == archit_ptr_11 ? log_reg_13 : _GEN_2267; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2269 = 6'he == archit_ptr_11 ? log_reg_14 : _GEN_2268; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2270 = 6'hf == archit_ptr_11 ? log_reg_15 : _GEN_2269; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2271 = 6'h10 == archit_ptr_11 ? log_reg_16 : _GEN_2270; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2272 = 6'h11 == archit_ptr_11 ? log_reg_17 : _GEN_2271; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2273 = 6'h12 == archit_ptr_11 ? log_reg_18 : _GEN_2272; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2274 = 6'h13 == archit_ptr_11 ? log_reg_19 : _GEN_2273; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2275 = 6'h14 == archit_ptr_11 ? log_reg_20 : _GEN_2274; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2276 = 6'h15 == archit_ptr_11 ? log_reg_21 : _GEN_2275; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2277 = 6'h16 == archit_ptr_11 ? log_reg_22 : _GEN_2276; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2278 = 6'h17 == archit_ptr_11 ? log_reg_23 : _GEN_2277; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2279 = 6'h18 == archit_ptr_11 ? log_reg_24 : _GEN_2278; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2280 = 6'h19 == archit_ptr_11 ? log_reg_25 : _GEN_2279; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2281 = 6'h1a == archit_ptr_11 ? log_reg_26 : _GEN_2280; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2282 = 6'h1b == archit_ptr_11 ? log_reg_27 : _GEN_2281; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2283 = 6'h1c == archit_ptr_11 ? log_reg_28 : _GEN_2282; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2284 = 6'h1d == archit_ptr_11 ? log_reg_29 : _GEN_2283; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2285 = 6'h1e == archit_ptr_11 ? log_reg_30 : _GEN_2284; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2286 = 6'h1f == archit_ptr_11 ? log_reg_31 : _GEN_2285; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2287 = 6'h20 == archit_ptr_11 ? log_reg_32 : _GEN_2286; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2288 = 6'h21 == archit_ptr_11 ? 2'h3 : _GEN_2287; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2290 = 6'h1 == archit_ptr_12 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2291 = 6'h2 == archit_ptr_12 ? log_reg_2 : _GEN_2290; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2292 = 6'h3 == archit_ptr_12 ? log_reg_3 : _GEN_2291; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2293 = 6'h4 == archit_ptr_12 ? log_reg_4 : _GEN_2292; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2294 = 6'h5 == archit_ptr_12 ? log_reg_5 : _GEN_2293; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2295 = 6'h6 == archit_ptr_12 ? log_reg_6 : _GEN_2294; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2296 = 6'h7 == archit_ptr_12 ? log_reg_7 : _GEN_2295; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2297 = 6'h8 == archit_ptr_12 ? log_reg_8 : _GEN_2296; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2298 = 6'h9 == archit_ptr_12 ? log_reg_9 : _GEN_2297; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2299 = 6'ha == archit_ptr_12 ? log_reg_10 : _GEN_2298; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2300 = 6'hb == archit_ptr_12 ? log_reg_11 : _GEN_2299; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2301 = 6'hc == archit_ptr_12 ? log_reg_12 : _GEN_2300; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2302 = 6'hd == archit_ptr_12 ? log_reg_13 : _GEN_2301; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2303 = 6'he == archit_ptr_12 ? log_reg_14 : _GEN_2302; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2304 = 6'hf == archit_ptr_12 ? log_reg_15 : _GEN_2303; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2305 = 6'h10 == archit_ptr_12 ? log_reg_16 : _GEN_2304; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2306 = 6'h11 == archit_ptr_12 ? log_reg_17 : _GEN_2305; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2307 = 6'h12 == archit_ptr_12 ? log_reg_18 : _GEN_2306; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2308 = 6'h13 == archit_ptr_12 ? log_reg_19 : _GEN_2307; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2309 = 6'h14 == archit_ptr_12 ? log_reg_20 : _GEN_2308; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2310 = 6'h15 == archit_ptr_12 ? log_reg_21 : _GEN_2309; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2311 = 6'h16 == archit_ptr_12 ? log_reg_22 : _GEN_2310; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2312 = 6'h17 == archit_ptr_12 ? log_reg_23 : _GEN_2311; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2313 = 6'h18 == archit_ptr_12 ? log_reg_24 : _GEN_2312; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2314 = 6'h19 == archit_ptr_12 ? log_reg_25 : _GEN_2313; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2315 = 6'h1a == archit_ptr_12 ? log_reg_26 : _GEN_2314; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2316 = 6'h1b == archit_ptr_12 ? log_reg_27 : _GEN_2315; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2317 = 6'h1c == archit_ptr_12 ? log_reg_28 : _GEN_2316; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2318 = 6'h1d == archit_ptr_12 ? log_reg_29 : _GEN_2317; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2319 = 6'h1e == archit_ptr_12 ? log_reg_30 : _GEN_2318; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2320 = 6'h1f == archit_ptr_12 ? log_reg_31 : _GEN_2319; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2321 = 6'h20 == archit_ptr_12 ? log_reg_32 : _GEN_2320; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2322 = 6'h21 == archit_ptr_12 ? 2'h3 : _GEN_2321; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2324 = 6'h1 == archit_ptr_13 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2325 = 6'h2 == archit_ptr_13 ? log_reg_2 : _GEN_2324; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2326 = 6'h3 == archit_ptr_13 ? log_reg_3 : _GEN_2325; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2327 = 6'h4 == archit_ptr_13 ? log_reg_4 : _GEN_2326; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2328 = 6'h5 == archit_ptr_13 ? log_reg_5 : _GEN_2327; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2329 = 6'h6 == archit_ptr_13 ? log_reg_6 : _GEN_2328; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2330 = 6'h7 == archit_ptr_13 ? log_reg_7 : _GEN_2329; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2331 = 6'h8 == archit_ptr_13 ? log_reg_8 : _GEN_2330; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2332 = 6'h9 == archit_ptr_13 ? log_reg_9 : _GEN_2331; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2333 = 6'ha == archit_ptr_13 ? log_reg_10 : _GEN_2332; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2334 = 6'hb == archit_ptr_13 ? log_reg_11 : _GEN_2333; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2335 = 6'hc == archit_ptr_13 ? log_reg_12 : _GEN_2334; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2336 = 6'hd == archit_ptr_13 ? log_reg_13 : _GEN_2335; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2337 = 6'he == archit_ptr_13 ? log_reg_14 : _GEN_2336; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2338 = 6'hf == archit_ptr_13 ? log_reg_15 : _GEN_2337; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2339 = 6'h10 == archit_ptr_13 ? log_reg_16 : _GEN_2338; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2340 = 6'h11 == archit_ptr_13 ? log_reg_17 : _GEN_2339; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2341 = 6'h12 == archit_ptr_13 ? log_reg_18 : _GEN_2340; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2342 = 6'h13 == archit_ptr_13 ? log_reg_19 : _GEN_2341; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2343 = 6'h14 == archit_ptr_13 ? log_reg_20 : _GEN_2342; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2344 = 6'h15 == archit_ptr_13 ? log_reg_21 : _GEN_2343; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2345 = 6'h16 == archit_ptr_13 ? log_reg_22 : _GEN_2344; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2346 = 6'h17 == archit_ptr_13 ? log_reg_23 : _GEN_2345; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2347 = 6'h18 == archit_ptr_13 ? log_reg_24 : _GEN_2346; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2348 = 6'h19 == archit_ptr_13 ? log_reg_25 : _GEN_2347; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2349 = 6'h1a == archit_ptr_13 ? log_reg_26 : _GEN_2348; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2350 = 6'h1b == archit_ptr_13 ? log_reg_27 : _GEN_2349; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2351 = 6'h1c == archit_ptr_13 ? log_reg_28 : _GEN_2350; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2352 = 6'h1d == archit_ptr_13 ? log_reg_29 : _GEN_2351; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2353 = 6'h1e == archit_ptr_13 ? log_reg_30 : _GEN_2352; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2354 = 6'h1f == archit_ptr_13 ? log_reg_31 : _GEN_2353; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2355 = 6'h20 == archit_ptr_13 ? log_reg_32 : _GEN_2354; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2356 = 6'h21 == archit_ptr_13 ? 2'h3 : _GEN_2355; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2358 = 6'h1 == archit_ptr_14 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2359 = 6'h2 == archit_ptr_14 ? log_reg_2 : _GEN_2358; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2360 = 6'h3 == archit_ptr_14 ? log_reg_3 : _GEN_2359; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2361 = 6'h4 == archit_ptr_14 ? log_reg_4 : _GEN_2360; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2362 = 6'h5 == archit_ptr_14 ? log_reg_5 : _GEN_2361; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2363 = 6'h6 == archit_ptr_14 ? log_reg_6 : _GEN_2362; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2364 = 6'h7 == archit_ptr_14 ? log_reg_7 : _GEN_2363; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2365 = 6'h8 == archit_ptr_14 ? log_reg_8 : _GEN_2364; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2366 = 6'h9 == archit_ptr_14 ? log_reg_9 : _GEN_2365; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2367 = 6'ha == archit_ptr_14 ? log_reg_10 : _GEN_2366; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2368 = 6'hb == archit_ptr_14 ? log_reg_11 : _GEN_2367; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2369 = 6'hc == archit_ptr_14 ? log_reg_12 : _GEN_2368; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2370 = 6'hd == archit_ptr_14 ? log_reg_13 : _GEN_2369; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2371 = 6'he == archit_ptr_14 ? log_reg_14 : _GEN_2370; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2372 = 6'hf == archit_ptr_14 ? log_reg_15 : _GEN_2371; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2373 = 6'h10 == archit_ptr_14 ? log_reg_16 : _GEN_2372; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2374 = 6'h11 == archit_ptr_14 ? log_reg_17 : _GEN_2373; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2375 = 6'h12 == archit_ptr_14 ? log_reg_18 : _GEN_2374; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2376 = 6'h13 == archit_ptr_14 ? log_reg_19 : _GEN_2375; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2377 = 6'h14 == archit_ptr_14 ? log_reg_20 : _GEN_2376; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2378 = 6'h15 == archit_ptr_14 ? log_reg_21 : _GEN_2377; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2379 = 6'h16 == archit_ptr_14 ? log_reg_22 : _GEN_2378; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2380 = 6'h17 == archit_ptr_14 ? log_reg_23 : _GEN_2379; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2381 = 6'h18 == archit_ptr_14 ? log_reg_24 : _GEN_2380; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2382 = 6'h19 == archit_ptr_14 ? log_reg_25 : _GEN_2381; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2383 = 6'h1a == archit_ptr_14 ? log_reg_26 : _GEN_2382; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2384 = 6'h1b == archit_ptr_14 ? log_reg_27 : _GEN_2383; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2385 = 6'h1c == archit_ptr_14 ? log_reg_28 : _GEN_2384; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2386 = 6'h1d == archit_ptr_14 ? log_reg_29 : _GEN_2385; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2387 = 6'h1e == archit_ptr_14 ? log_reg_30 : _GEN_2386; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2388 = 6'h1f == archit_ptr_14 ? log_reg_31 : _GEN_2387; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2389 = 6'h20 == archit_ptr_14 ? log_reg_32 : _GEN_2388; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2390 = 6'h21 == archit_ptr_14 ? 2'h3 : _GEN_2389; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2392 = 6'h1 == archit_ptr_15 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2393 = 6'h2 == archit_ptr_15 ? log_reg_2 : _GEN_2392; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2394 = 6'h3 == archit_ptr_15 ? log_reg_3 : _GEN_2393; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2395 = 6'h4 == archit_ptr_15 ? log_reg_4 : _GEN_2394; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2396 = 6'h5 == archit_ptr_15 ? log_reg_5 : _GEN_2395; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2397 = 6'h6 == archit_ptr_15 ? log_reg_6 : _GEN_2396; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2398 = 6'h7 == archit_ptr_15 ? log_reg_7 : _GEN_2397; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2399 = 6'h8 == archit_ptr_15 ? log_reg_8 : _GEN_2398; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2400 = 6'h9 == archit_ptr_15 ? log_reg_9 : _GEN_2399; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2401 = 6'ha == archit_ptr_15 ? log_reg_10 : _GEN_2400; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2402 = 6'hb == archit_ptr_15 ? log_reg_11 : _GEN_2401; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2403 = 6'hc == archit_ptr_15 ? log_reg_12 : _GEN_2402; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2404 = 6'hd == archit_ptr_15 ? log_reg_13 : _GEN_2403; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2405 = 6'he == archit_ptr_15 ? log_reg_14 : _GEN_2404; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2406 = 6'hf == archit_ptr_15 ? log_reg_15 : _GEN_2405; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2407 = 6'h10 == archit_ptr_15 ? log_reg_16 : _GEN_2406; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2408 = 6'h11 == archit_ptr_15 ? log_reg_17 : _GEN_2407; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2409 = 6'h12 == archit_ptr_15 ? log_reg_18 : _GEN_2408; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2410 = 6'h13 == archit_ptr_15 ? log_reg_19 : _GEN_2409; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2411 = 6'h14 == archit_ptr_15 ? log_reg_20 : _GEN_2410; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2412 = 6'h15 == archit_ptr_15 ? log_reg_21 : _GEN_2411; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2413 = 6'h16 == archit_ptr_15 ? log_reg_22 : _GEN_2412; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2414 = 6'h17 == archit_ptr_15 ? log_reg_23 : _GEN_2413; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2415 = 6'h18 == archit_ptr_15 ? log_reg_24 : _GEN_2414; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2416 = 6'h19 == archit_ptr_15 ? log_reg_25 : _GEN_2415; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2417 = 6'h1a == archit_ptr_15 ? log_reg_26 : _GEN_2416; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2418 = 6'h1b == archit_ptr_15 ? log_reg_27 : _GEN_2417; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2419 = 6'h1c == archit_ptr_15 ? log_reg_28 : _GEN_2418; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2420 = 6'h1d == archit_ptr_15 ? log_reg_29 : _GEN_2419; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2421 = 6'h1e == archit_ptr_15 ? log_reg_30 : _GEN_2420; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2422 = 6'h1f == archit_ptr_15 ? log_reg_31 : _GEN_2421; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2423 = 6'h20 == archit_ptr_15 ? log_reg_32 : _GEN_2422; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2424 = 6'h21 == archit_ptr_15 ? 2'h3 : _GEN_2423; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2426 = 6'h1 == archit_ptr_16 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2427 = 6'h2 == archit_ptr_16 ? log_reg_2 : _GEN_2426; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2428 = 6'h3 == archit_ptr_16 ? log_reg_3 : _GEN_2427; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2429 = 6'h4 == archit_ptr_16 ? log_reg_4 : _GEN_2428; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2430 = 6'h5 == archit_ptr_16 ? log_reg_5 : _GEN_2429; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2431 = 6'h6 == archit_ptr_16 ? log_reg_6 : _GEN_2430; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2432 = 6'h7 == archit_ptr_16 ? log_reg_7 : _GEN_2431; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2433 = 6'h8 == archit_ptr_16 ? log_reg_8 : _GEN_2432; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2434 = 6'h9 == archit_ptr_16 ? log_reg_9 : _GEN_2433; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2435 = 6'ha == archit_ptr_16 ? log_reg_10 : _GEN_2434; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2436 = 6'hb == archit_ptr_16 ? log_reg_11 : _GEN_2435; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2437 = 6'hc == archit_ptr_16 ? log_reg_12 : _GEN_2436; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2438 = 6'hd == archit_ptr_16 ? log_reg_13 : _GEN_2437; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2439 = 6'he == archit_ptr_16 ? log_reg_14 : _GEN_2438; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2440 = 6'hf == archit_ptr_16 ? log_reg_15 : _GEN_2439; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2441 = 6'h10 == archit_ptr_16 ? log_reg_16 : _GEN_2440; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2442 = 6'h11 == archit_ptr_16 ? log_reg_17 : _GEN_2441; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2443 = 6'h12 == archit_ptr_16 ? log_reg_18 : _GEN_2442; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2444 = 6'h13 == archit_ptr_16 ? log_reg_19 : _GEN_2443; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2445 = 6'h14 == archit_ptr_16 ? log_reg_20 : _GEN_2444; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2446 = 6'h15 == archit_ptr_16 ? log_reg_21 : _GEN_2445; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2447 = 6'h16 == archit_ptr_16 ? log_reg_22 : _GEN_2446; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2448 = 6'h17 == archit_ptr_16 ? log_reg_23 : _GEN_2447; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2449 = 6'h18 == archit_ptr_16 ? log_reg_24 : _GEN_2448; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2450 = 6'h19 == archit_ptr_16 ? log_reg_25 : _GEN_2449; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2451 = 6'h1a == archit_ptr_16 ? log_reg_26 : _GEN_2450; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2452 = 6'h1b == archit_ptr_16 ? log_reg_27 : _GEN_2451; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2453 = 6'h1c == archit_ptr_16 ? log_reg_28 : _GEN_2452; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2454 = 6'h1d == archit_ptr_16 ? log_reg_29 : _GEN_2453; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2455 = 6'h1e == archit_ptr_16 ? log_reg_30 : _GEN_2454; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2456 = 6'h1f == archit_ptr_16 ? log_reg_31 : _GEN_2455; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2457 = 6'h20 == archit_ptr_16 ? log_reg_32 : _GEN_2456; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2458 = 6'h21 == archit_ptr_16 ? 2'h3 : _GEN_2457; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2460 = 6'h1 == archit_ptr_17 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2461 = 6'h2 == archit_ptr_17 ? log_reg_2 : _GEN_2460; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2462 = 6'h3 == archit_ptr_17 ? log_reg_3 : _GEN_2461; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2463 = 6'h4 == archit_ptr_17 ? log_reg_4 : _GEN_2462; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2464 = 6'h5 == archit_ptr_17 ? log_reg_5 : _GEN_2463; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2465 = 6'h6 == archit_ptr_17 ? log_reg_6 : _GEN_2464; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2466 = 6'h7 == archit_ptr_17 ? log_reg_7 : _GEN_2465; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2467 = 6'h8 == archit_ptr_17 ? log_reg_8 : _GEN_2466; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2468 = 6'h9 == archit_ptr_17 ? log_reg_9 : _GEN_2467; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2469 = 6'ha == archit_ptr_17 ? log_reg_10 : _GEN_2468; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2470 = 6'hb == archit_ptr_17 ? log_reg_11 : _GEN_2469; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2471 = 6'hc == archit_ptr_17 ? log_reg_12 : _GEN_2470; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2472 = 6'hd == archit_ptr_17 ? log_reg_13 : _GEN_2471; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2473 = 6'he == archit_ptr_17 ? log_reg_14 : _GEN_2472; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2474 = 6'hf == archit_ptr_17 ? log_reg_15 : _GEN_2473; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2475 = 6'h10 == archit_ptr_17 ? log_reg_16 : _GEN_2474; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2476 = 6'h11 == archit_ptr_17 ? log_reg_17 : _GEN_2475; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2477 = 6'h12 == archit_ptr_17 ? log_reg_18 : _GEN_2476; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2478 = 6'h13 == archit_ptr_17 ? log_reg_19 : _GEN_2477; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2479 = 6'h14 == archit_ptr_17 ? log_reg_20 : _GEN_2478; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2480 = 6'h15 == archit_ptr_17 ? log_reg_21 : _GEN_2479; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2481 = 6'h16 == archit_ptr_17 ? log_reg_22 : _GEN_2480; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2482 = 6'h17 == archit_ptr_17 ? log_reg_23 : _GEN_2481; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2483 = 6'h18 == archit_ptr_17 ? log_reg_24 : _GEN_2482; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2484 = 6'h19 == archit_ptr_17 ? log_reg_25 : _GEN_2483; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2485 = 6'h1a == archit_ptr_17 ? log_reg_26 : _GEN_2484; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2486 = 6'h1b == archit_ptr_17 ? log_reg_27 : _GEN_2485; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2487 = 6'h1c == archit_ptr_17 ? log_reg_28 : _GEN_2486; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2488 = 6'h1d == archit_ptr_17 ? log_reg_29 : _GEN_2487; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2489 = 6'h1e == archit_ptr_17 ? log_reg_30 : _GEN_2488; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2490 = 6'h1f == archit_ptr_17 ? log_reg_31 : _GEN_2489; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2491 = 6'h20 == archit_ptr_17 ? log_reg_32 : _GEN_2490; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2492 = 6'h21 == archit_ptr_17 ? 2'h3 : _GEN_2491; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2494 = 6'h1 == archit_ptr_18 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2495 = 6'h2 == archit_ptr_18 ? log_reg_2 : _GEN_2494; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2496 = 6'h3 == archit_ptr_18 ? log_reg_3 : _GEN_2495; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2497 = 6'h4 == archit_ptr_18 ? log_reg_4 : _GEN_2496; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2498 = 6'h5 == archit_ptr_18 ? log_reg_5 : _GEN_2497; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2499 = 6'h6 == archit_ptr_18 ? log_reg_6 : _GEN_2498; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2500 = 6'h7 == archit_ptr_18 ? log_reg_7 : _GEN_2499; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2501 = 6'h8 == archit_ptr_18 ? log_reg_8 : _GEN_2500; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2502 = 6'h9 == archit_ptr_18 ? log_reg_9 : _GEN_2501; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2503 = 6'ha == archit_ptr_18 ? log_reg_10 : _GEN_2502; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2504 = 6'hb == archit_ptr_18 ? log_reg_11 : _GEN_2503; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2505 = 6'hc == archit_ptr_18 ? log_reg_12 : _GEN_2504; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2506 = 6'hd == archit_ptr_18 ? log_reg_13 : _GEN_2505; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2507 = 6'he == archit_ptr_18 ? log_reg_14 : _GEN_2506; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2508 = 6'hf == archit_ptr_18 ? log_reg_15 : _GEN_2507; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2509 = 6'h10 == archit_ptr_18 ? log_reg_16 : _GEN_2508; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2510 = 6'h11 == archit_ptr_18 ? log_reg_17 : _GEN_2509; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2511 = 6'h12 == archit_ptr_18 ? log_reg_18 : _GEN_2510; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2512 = 6'h13 == archit_ptr_18 ? log_reg_19 : _GEN_2511; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2513 = 6'h14 == archit_ptr_18 ? log_reg_20 : _GEN_2512; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2514 = 6'h15 == archit_ptr_18 ? log_reg_21 : _GEN_2513; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2515 = 6'h16 == archit_ptr_18 ? log_reg_22 : _GEN_2514; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2516 = 6'h17 == archit_ptr_18 ? log_reg_23 : _GEN_2515; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2517 = 6'h18 == archit_ptr_18 ? log_reg_24 : _GEN_2516; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2518 = 6'h19 == archit_ptr_18 ? log_reg_25 : _GEN_2517; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2519 = 6'h1a == archit_ptr_18 ? log_reg_26 : _GEN_2518; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2520 = 6'h1b == archit_ptr_18 ? log_reg_27 : _GEN_2519; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2521 = 6'h1c == archit_ptr_18 ? log_reg_28 : _GEN_2520; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2522 = 6'h1d == archit_ptr_18 ? log_reg_29 : _GEN_2521; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2523 = 6'h1e == archit_ptr_18 ? log_reg_30 : _GEN_2522; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2524 = 6'h1f == archit_ptr_18 ? log_reg_31 : _GEN_2523; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2525 = 6'h20 == archit_ptr_18 ? log_reg_32 : _GEN_2524; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2526 = 6'h21 == archit_ptr_18 ? 2'h3 : _GEN_2525; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2528 = 6'h1 == archit_ptr_19 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2529 = 6'h2 == archit_ptr_19 ? log_reg_2 : _GEN_2528; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2530 = 6'h3 == archit_ptr_19 ? log_reg_3 : _GEN_2529; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2531 = 6'h4 == archit_ptr_19 ? log_reg_4 : _GEN_2530; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2532 = 6'h5 == archit_ptr_19 ? log_reg_5 : _GEN_2531; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2533 = 6'h6 == archit_ptr_19 ? log_reg_6 : _GEN_2532; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2534 = 6'h7 == archit_ptr_19 ? log_reg_7 : _GEN_2533; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2535 = 6'h8 == archit_ptr_19 ? log_reg_8 : _GEN_2534; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2536 = 6'h9 == archit_ptr_19 ? log_reg_9 : _GEN_2535; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2537 = 6'ha == archit_ptr_19 ? log_reg_10 : _GEN_2536; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2538 = 6'hb == archit_ptr_19 ? log_reg_11 : _GEN_2537; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2539 = 6'hc == archit_ptr_19 ? log_reg_12 : _GEN_2538; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2540 = 6'hd == archit_ptr_19 ? log_reg_13 : _GEN_2539; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2541 = 6'he == archit_ptr_19 ? log_reg_14 : _GEN_2540; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2542 = 6'hf == archit_ptr_19 ? log_reg_15 : _GEN_2541; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2543 = 6'h10 == archit_ptr_19 ? log_reg_16 : _GEN_2542; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2544 = 6'h11 == archit_ptr_19 ? log_reg_17 : _GEN_2543; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2545 = 6'h12 == archit_ptr_19 ? log_reg_18 : _GEN_2544; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2546 = 6'h13 == archit_ptr_19 ? log_reg_19 : _GEN_2545; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2547 = 6'h14 == archit_ptr_19 ? log_reg_20 : _GEN_2546; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2548 = 6'h15 == archit_ptr_19 ? log_reg_21 : _GEN_2547; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2549 = 6'h16 == archit_ptr_19 ? log_reg_22 : _GEN_2548; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2550 = 6'h17 == archit_ptr_19 ? log_reg_23 : _GEN_2549; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2551 = 6'h18 == archit_ptr_19 ? log_reg_24 : _GEN_2550; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2552 = 6'h19 == archit_ptr_19 ? log_reg_25 : _GEN_2551; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2553 = 6'h1a == archit_ptr_19 ? log_reg_26 : _GEN_2552; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2554 = 6'h1b == archit_ptr_19 ? log_reg_27 : _GEN_2553; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2555 = 6'h1c == archit_ptr_19 ? log_reg_28 : _GEN_2554; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2556 = 6'h1d == archit_ptr_19 ? log_reg_29 : _GEN_2555; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2557 = 6'h1e == archit_ptr_19 ? log_reg_30 : _GEN_2556; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2558 = 6'h1f == archit_ptr_19 ? log_reg_31 : _GEN_2557; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2559 = 6'h20 == archit_ptr_19 ? log_reg_32 : _GEN_2558; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2560 = 6'h21 == archit_ptr_19 ? 2'h3 : _GEN_2559; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2562 = 6'h1 == archit_ptr_20 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2563 = 6'h2 == archit_ptr_20 ? log_reg_2 : _GEN_2562; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2564 = 6'h3 == archit_ptr_20 ? log_reg_3 : _GEN_2563; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2565 = 6'h4 == archit_ptr_20 ? log_reg_4 : _GEN_2564; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2566 = 6'h5 == archit_ptr_20 ? log_reg_5 : _GEN_2565; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2567 = 6'h6 == archit_ptr_20 ? log_reg_6 : _GEN_2566; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2568 = 6'h7 == archit_ptr_20 ? log_reg_7 : _GEN_2567; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2569 = 6'h8 == archit_ptr_20 ? log_reg_8 : _GEN_2568; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2570 = 6'h9 == archit_ptr_20 ? log_reg_9 : _GEN_2569; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2571 = 6'ha == archit_ptr_20 ? log_reg_10 : _GEN_2570; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2572 = 6'hb == archit_ptr_20 ? log_reg_11 : _GEN_2571; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2573 = 6'hc == archit_ptr_20 ? log_reg_12 : _GEN_2572; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2574 = 6'hd == archit_ptr_20 ? log_reg_13 : _GEN_2573; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2575 = 6'he == archit_ptr_20 ? log_reg_14 : _GEN_2574; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2576 = 6'hf == archit_ptr_20 ? log_reg_15 : _GEN_2575; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2577 = 6'h10 == archit_ptr_20 ? log_reg_16 : _GEN_2576; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2578 = 6'h11 == archit_ptr_20 ? log_reg_17 : _GEN_2577; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2579 = 6'h12 == archit_ptr_20 ? log_reg_18 : _GEN_2578; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2580 = 6'h13 == archit_ptr_20 ? log_reg_19 : _GEN_2579; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2581 = 6'h14 == archit_ptr_20 ? log_reg_20 : _GEN_2580; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2582 = 6'h15 == archit_ptr_20 ? log_reg_21 : _GEN_2581; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2583 = 6'h16 == archit_ptr_20 ? log_reg_22 : _GEN_2582; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2584 = 6'h17 == archit_ptr_20 ? log_reg_23 : _GEN_2583; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2585 = 6'h18 == archit_ptr_20 ? log_reg_24 : _GEN_2584; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2586 = 6'h19 == archit_ptr_20 ? log_reg_25 : _GEN_2585; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2587 = 6'h1a == archit_ptr_20 ? log_reg_26 : _GEN_2586; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2588 = 6'h1b == archit_ptr_20 ? log_reg_27 : _GEN_2587; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2589 = 6'h1c == archit_ptr_20 ? log_reg_28 : _GEN_2588; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2590 = 6'h1d == archit_ptr_20 ? log_reg_29 : _GEN_2589; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2591 = 6'h1e == archit_ptr_20 ? log_reg_30 : _GEN_2590; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2592 = 6'h1f == archit_ptr_20 ? log_reg_31 : _GEN_2591; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2593 = 6'h20 == archit_ptr_20 ? log_reg_32 : _GEN_2592; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2594 = 6'h21 == archit_ptr_20 ? 2'h3 : _GEN_2593; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2596 = 6'h1 == archit_ptr_21 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2597 = 6'h2 == archit_ptr_21 ? log_reg_2 : _GEN_2596; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2598 = 6'h3 == archit_ptr_21 ? log_reg_3 : _GEN_2597; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2599 = 6'h4 == archit_ptr_21 ? log_reg_4 : _GEN_2598; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2600 = 6'h5 == archit_ptr_21 ? log_reg_5 : _GEN_2599; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2601 = 6'h6 == archit_ptr_21 ? log_reg_6 : _GEN_2600; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2602 = 6'h7 == archit_ptr_21 ? log_reg_7 : _GEN_2601; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2603 = 6'h8 == archit_ptr_21 ? log_reg_8 : _GEN_2602; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2604 = 6'h9 == archit_ptr_21 ? log_reg_9 : _GEN_2603; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2605 = 6'ha == archit_ptr_21 ? log_reg_10 : _GEN_2604; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2606 = 6'hb == archit_ptr_21 ? log_reg_11 : _GEN_2605; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2607 = 6'hc == archit_ptr_21 ? log_reg_12 : _GEN_2606; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2608 = 6'hd == archit_ptr_21 ? log_reg_13 : _GEN_2607; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2609 = 6'he == archit_ptr_21 ? log_reg_14 : _GEN_2608; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2610 = 6'hf == archit_ptr_21 ? log_reg_15 : _GEN_2609; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2611 = 6'h10 == archit_ptr_21 ? log_reg_16 : _GEN_2610; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2612 = 6'h11 == archit_ptr_21 ? log_reg_17 : _GEN_2611; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2613 = 6'h12 == archit_ptr_21 ? log_reg_18 : _GEN_2612; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2614 = 6'h13 == archit_ptr_21 ? log_reg_19 : _GEN_2613; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2615 = 6'h14 == archit_ptr_21 ? log_reg_20 : _GEN_2614; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2616 = 6'h15 == archit_ptr_21 ? log_reg_21 : _GEN_2615; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2617 = 6'h16 == archit_ptr_21 ? log_reg_22 : _GEN_2616; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2618 = 6'h17 == archit_ptr_21 ? log_reg_23 : _GEN_2617; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2619 = 6'h18 == archit_ptr_21 ? log_reg_24 : _GEN_2618; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2620 = 6'h19 == archit_ptr_21 ? log_reg_25 : _GEN_2619; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2621 = 6'h1a == archit_ptr_21 ? log_reg_26 : _GEN_2620; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2622 = 6'h1b == archit_ptr_21 ? log_reg_27 : _GEN_2621; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2623 = 6'h1c == archit_ptr_21 ? log_reg_28 : _GEN_2622; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2624 = 6'h1d == archit_ptr_21 ? log_reg_29 : _GEN_2623; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2625 = 6'h1e == archit_ptr_21 ? log_reg_30 : _GEN_2624; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2626 = 6'h1f == archit_ptr_21 ? log_reg_31 : _GEN_2625; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2627 = 6'h20 == archit_ptr_21 ? log_reg_32 : _GEN_2626; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2628 = 6'h21 == archit_ptr_21 ? 2'h3 : _GEN_2627; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2630 = 6'h1 == archit_ptr_22 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2631 = 6'h2 == archit_ptr_22 ? log_reg_2 : _GEN_2630; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2632 = 6'h3 == archit_ptr_22 ? log_reg_3 : _GEN_2631; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2633 = 6'h4 == archit_ptr_22 ? log_reg_4 : _GEN_2632; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2634 = 6'h5 == archit_ptr_22 ? log_reg_5 : _GEN_2633; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2635 = 6'h6 == archit_ptr_22 ? log_reg_6 : _GEN_2634; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2636 = 6'h7 == archit_ptr_22 ? log_reg_7 : _GEN_2635; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2637 = 6'h8 == archit_ptr_22 ? log_reg_8 : _GEN_2636; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2638 = 6'h9 == archit_ptr_22 ? log_reg_9 : _GEN_2637; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2639 = 6'ha == archit_ptr_22 ? log_reg_10 : _GEN_2638; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2640 = 6'hb == archit_ptr_22 ? log_reg_11 : _GEN_2639; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2641 = 6'hc == archit_ptr_22 ? log_reg_12 : _GEN_2640; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2642 = 6'hd == archit_ptr_22 ? log_reg_13 : _GEN_2641; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2643 = 6'he == archit_ptr_22 ? log_reg_14 : _GEN_2642; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2644 = 6'hf == archit_ptr_22 ? log_reg_15 : _GEN_2643; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2645 = 6'h10 == archit_ptr_22 ? log_reg_16 : _GEN_2644; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2646 = 6'h11 == archit_ptr_22 ? log_reg_17 : _GEN_2645; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2647 = 6'h12 == archit_ptr_22 ? log_reg_18 : _GEN_2646; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2648 = 6'h13 == archit_ptr_22 ? log_reg_19 : _GEN_2647; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2649 = 6'h14 == archit_ptr_22 ? log_reg_20 : _GEN_2648; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2650 = 6'h15 == archit_ptr_22 ? log_reg_21 : _GEN_2649; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2651 = 6'h16 == archit_ptr_22 ? log_reg_22 : _GEN_2650; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2652 = 6'h17 == archit_ptr_22 ? log_reg_23 : _GEN_2651; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2653 = 6'h18 == archit_ptr_22 ? log_reg_24 : _GEN_2652; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2654 = 6'h19 == archit_ptr_22 ? log_reg_25 : _GEN_2653; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2655 = 6'h1a == archit_ptr_22 ? log_reg_26 : _GEN_2654; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2656 = 6'h1b == archit_ptr_22 ? log_reg_27 : _GEN_2655; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2657 = 6'h1c == archit_ptr_22 ? log_reg_28 : _GEN_2656; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2658 = 6'h1d == archit_ptr_22 ? log_reg_29 : _GEN_2657; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2659 = 6'h1e == archit_ptr_22 ? log_reg_30 : _GEN_2658; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2660 = 6'h1f == archit_ptr_22 ? log_reg_31 : _GEN_2659; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2661 = 6'h20 == archit_ptr_22 ? log_reg_32 : _GEN_2660; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2662 = 6'h21 == archit_ptr_22 ? 2'h3 : _GEN_2661; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2664 = 6'h1 == archit_ptr_23 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2665 = 6'h2 == archit_ptr_23 ? log_reg_2 : _GEN_2664; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2666 = 6'h3 == archit_ptr_23 ? log_reg_3 : _GEN_2665; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2667 = 6'h4 == archit_ptr_23 ? log_reg_4 : _GEN_2666; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2668 = 6'h5 == archit_ptr_23 ? log_reg_5 : _GEN_2667; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2669 = 6'h6 == archit_ptr_23 ? log_reg_6 : _GEN_2668; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2670 = 6'h7 == archit_ptr_23 ? log_reg_7 : _GEN_2669; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2671 = 6'h8 == archit_ptr_23 ? log_reg_8 : _GEN_2670; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2672 = 6'h9 == archit_ptr_23 ? log_reg_9 : _GEN_2671; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2673 = 6'ha == archit_ptr_23 ? log_reg_10 : _GEN_2672; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2674 = 6'hb == archit_ptr_23 ? log_reg_11 : _GEN_2673; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2675 = 6'hc == archit_ptr_23 ? log_reg_12 : _GEN_2674; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2676 = 6'hd == archit_ptr_23 ? log_reg_13 : _GEN_2675; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2677 = 6'he == archit_ptr_23 ? log_reg_14 : _GEN_2676; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2678 = 6'hf == archit_ptr_23 ? log_reg_15 : _GEN_2677; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2679 = 6'h10 == archit_ptr_23 ? log_reg_16 : _GEN_2678; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2680 = 6'h11 == archit_ptr_23 ? log_reg_17 : _GEN_2679; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2681 = 6'h12 == archit_ptr_23 ? log_reg_18 : _GEN_2680; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2682 = 6'h13 == archit_ptr_23 ? log_reg_19 : _GEN_2681; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2683 = 6'h14 == archit_ptr_23 ? log_reg_20 : _GEN_2682; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2684 = 6'h15 == archit_ptr_23 ? log_reg_21 : _GEN_2683; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2685 = 6'h16 == archit_ptr_23 ? log_reg_22 : _GEN_2684; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2686 = 6'h17 == archit_ptr_23 ? log_reg_23 : _GEN_2685; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2687 = 6'h18 == archit_ptr_23 ? log_reg_24 : _GEN_2686; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2688 = 6'h19 == archit_ptr_23 ? log_reg_25 : _GEN_2687; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2689 = 6'h1a == archit_ptr_23 ? log_reg_26 : _GEN_2688; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2690 = 6'h1b == archit_ptr_23 ? log_reg_27 : _GEN_2689; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2691 = 6'h1c == archit_ptr_23 ? log_reg_28 : _GEN_2690; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2692 = 6'h1d == archit_ptr_23 ? log_reg_29 : _GEN_2691; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2693 = 6'h1e == archit_ptr_23 ? log_reg_30 : _GEN_2692; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2694 = 6'h1f == archit_ptr_23 ? log_reg_31 : _GEN_2693; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2695 = 6'h20 == archit_ptr_23 ? log_reg_32 : _GEN_2694; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2696 = 6'h21 == archit_ptr_23 ? 2'h3 : _GEN_2695; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2698 = 6'h1 == archit_ptr_24 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2699 = 6'h2 == archit_ptr_24 ? log_reg_2 : _GEN_2698; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2700 = 6'h3 == archit_ptr_24 ? log_reg_3 : _GEN_2699; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2701 = 6'h4 == archit_ptr_24 ? log_reg_4 : _GEN_2700; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2702 = 6'h5 == archit_ptr_24 ? log_reg_5 : _GEN_2701; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2703 = 6'h6 == archit_ptr_24 ? log_reg_6 : _GEN_2702; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2704 = 6'h7 == archit_ptr_24 ? log_reg_7 : _GEN_2703; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2705 = 6'h8 == archit_ptr_24 ? log_reg_8 : _GEN_2704; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2706 = 6'h9 == archit_ptr_24 ? log_reg_9 : _GEN_2705; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2707 = 6'ha == archit_ptr_24 ? log_reg_10 : _GEN_2706; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2708 = 6'hb == archit_ptr_24 ? log_reg_11 : _GEN_2707; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2709 = 6'hc == archit_ptr_24 ? log_reg_12 : _GEN_2708; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2710 = 6'hd == archit_ptr_24 ? log_reg_13 : _GEN_2709; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2711 = 6'he == archit_ptr_24 ? log_reg_14 : _GEN_2710; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2712 = 6'hf == archit_ptr_24 ? log_reg_15 : _GEN_2711; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2713 = 6'h10 == archit_ptr_24 ? log_reg_16 : _GEN_2712; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2714 = 6'h11 == archit_ptr_24 ? log_reg_17 : _GEN_2713; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2715 = 6'h12 == archit_ptr_24 ? log_reg_18 : _GEN_2714; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2716 = 6'h13 == archit_ptr_24 ? log_reg_19 : _GEN_2715; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2717 = 6'h14 == archit_ptr_24 ? log_reg_20 : _GEN_2716; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2718 = 6'h15 == archit_ptr_24 ? log_reg_21 : _GEN_2717; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2719 = 6'h16 == archit_ptr_24 ? log_reg_22 : _GEN_2718; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2720 = 6'h17 == archit_ptr_24 ? log_reg_23 : _GEN_2719; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2721 = 6'h18 == archit_ptr_24 ? log_reg_24 : _GEN_2720; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2722 = 6'h19 == archit_ptr_24 ? log_reg_25 : _GEN_2721; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2723 = 6'h1a == archit_ptr_24 ? log_reg_26 : _GEN_2722; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2724 = 6'h1b == archit_ptr_24 ? log_reg_27 : _GEN_2723; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2725 = 6'h1c == archit_ptr_24 ? log_reg_28 : _GEN_2724; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2726 = 6'h1d == archit_ptr_24 ? log_reg_29 : _GEN_2725; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2727 = 6'h1e == archit_ptr_24 ? log_reg_30 : _GEN_2726; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2728 = 6'h1f == archit_ptr_24 ? log_reg_31 : _GEN_2727; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2729 = 6'h20 == archit_ptr_24 ? log_reg_32 : _GEN_2728; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2730 = 6'h21 == archit_ptr_24 ? 2'h3 : _GEN_2729; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2732 = 6'h1 == archit_ptr_25 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2733 = 6'h2 == archit_ptr_25 ? log_reg_2 : _GEN_2732; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2734 = 6'h3 == archit_ptr_25 ? log_reg_3 : _GEN_2733; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2735 = 6'h4 == archit_ptr_25 ? log_reg_4 : _GEN_2734; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2736 = 6'h5 == archit_ptr_25 ? log_reg_5 : _GEN_2735; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2737 = 6'h6 == archit_ptr_25 ? log_reg_6 : _GEN_2736; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2738 = 6'h7 == archit_ptr_25 ? log_reg_7 : _GEN_2737; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2739 = 6'h8 == archit_ptr_25 ? log_reg_8 : _GEN_2738; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2740 = 6'h9 == archit_ptr_25 ? log_reg_9 : _GEN_2739; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2741 = 6'ha == archit_ptr_25 ? log_reg_10 : _GEN_2740; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2742 = 6'hb == archit_ptr_25 ? log_reg_11 : _GEN_2741; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2743 = 6'hc == archit_ptr_25 ? log_reg_12 : _GEN_2742; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2744 = 6'hd == archit_ptr_25 ? log_reg_13 : _GEN_2743; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2745 = 6'he == archit_ptr_25 ? log_reg_14 : _GEN_2744; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2746 = 6'hf == archit_ptr_25 ? log_reg_15 : _GEN_2745; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2747 = 6'h10 == archit_ptr_25 ? log_reg_16 : _GEN_2746; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2748 = 6'h11 == archit_ptr_25 ? log_reg_17 : _GEN_2747; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2749 = 6'h12 == archit_ptr_25 ? log_reg_18 : _GEN_2748; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2750 = 6'h13 == archit_ptr_25 ? log_reg_19 : _GEN_2749; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2751 = 6'h14 == archit_ptr_25 ? log_reg_20 : _GEN_2750; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2752 = 6'h15 == archit_ptr_25 ? log_reg_21 : _GEN_2751; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2753 = 6'h16 == archit_ptr_25 ? log_reg_22 : _GEN_2752; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2754 = 6'h17 == archit_ptr_25 ? log_reg_23 : _GEN_2753; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2755 = 6'h18 == archit_ptr_25 ? log_reg_24 : _GEN_2754; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2756 = 6'h19 == archit_ptr_25 ? log_reg_25 : _GEN_2755; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2757 = 6'h1a == archit_ptr_25 ? log_reg_26 : _GEN_2756; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2758 = 6'h1b == archit_ptr_25 ? log_reg_27 : _GEN_2757; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2759 = 6'h1c == archit_ptr_25 ? log_reg_28 : _GEN_2758; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2760 = 6'h1d == archit_ptr_25 ? log_reg_29 : _GEN_2759; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2761 = 6'h1e == archit_ptr_25 ? log_reg_30 : _GEN_2760; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2762 = 6'h1f == archit_ptr_25 ? log_reg_31 : _GEN_2761; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2763 = 6'h20 == archit_ptr_25 ? log_reg_32 : _GEN_2762; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2764 = 6'h21 == archit_ptr_25 ? 2'h3 : _GEN_2763; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2766 = 6'h1 == archit_ptr_26 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2767 = 6'h2 == archit_ptr_26 ? log_reg_2 : _GEN_2766; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2768 = 6'h3 == archit_ptr_26 ? log_reg_3 : _GEN_2767; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2769 = 6'h4 == archit_ptr_26 ? log_reg_4 : _GEN_2768; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2770 = 6'h5 == archit_ptr_26 ? log_reg_5 : _GEN_2769; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2771 = 6'h6 == archit_ptr_26 ? log_reg_6 : _GEN_2770; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2772 = 6'h7 == archit_ptr_26 ? log_reg_7 : _GEN_2771; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2773 = 6'h8 == archit_ptr_26 ? log_reg_8 : _GEN_2772; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2774 = 6'h9 == archit_ptr_26 ? log_reg_9 : _GEN_2773; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2775 = 6'ha == archit_ptr_26 ? log_reg_10 : _GEN_2774; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2776 = 6'hb == archit_ptr_26 ? log_reg_11 : _GEN_2775; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2777 = 6'hc == archit_ptr_26 ? log_reg_12 : _GEN_2776; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2778 = 6'hd == archit_ptr_26 ? log_reg_13 : _GEN_2777; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2779 = 6'he == archit_ptr_26 ? log_reg_14 : _GEN_2778; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2780 = 6'hf == archit_ptr_26 ? log_reg_15 : _GEN_2779; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2781 = 6'h10 == archit_ptr_26 ? log_reg_16 : _GEN_2780; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2782 = 6'h11 == archit_ptr_26 ? log_reg_17 : _GEN_2781; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2783 = 6'h12 == archit_ptr_26 ? log_reg_18 : _GEN_2782; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2784 = 6'h13 == archit_ptr_26 ? log_reg_19 : _GEN_2783; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2785 = 6'h14 == archit_ptr_26 ? log_reg_20 : _GEN_2784; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2786 = 6'h15 == archit_ptr_26 ? log_reg_21 : _GEN_2785; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2787 = 6'h16 == archit_ptr_26 ? log_reg_22 : _GEN_2786; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2788 = 6'h17 == archit_ptr_26 ? log_reg_23 : _GEN_2787; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2789 = 6'h18 == archit_ptr_26 ? log_reg_24 : _GEN_2788; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2790 = 6'h19 == archit_ptr_26 ? log_reg_25 : _GEN_2789; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2791 = 6'h1a == archit_ptr_26 ? log_reg_26 : _GEN_2790; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2792 = 6'h1b == archit_ptr_26 ? log_reg_27 : _GEN_2791; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2793 = 6'h1c == archit_ptr_26 ? log_reg_28 : _GEN_2792; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2794 = 6'h1d == archit_ptr_26 ? log_reg_29 : _GEN_2793; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2795 = 6'h1e == archit_ptr_26 ? log_reg_30 : _GEN_2794; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2796 = 6'h1f == archit_ptr_26 ? log_reg_31 : _GEN_2795; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2797 = 6'h20 == archit_ptr_26 ? log_reg_32 : _GEN_2796; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2798 = 6'h21 == archit_ptr_26 ? 2'h3 : _GEN_2797; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2800 = 6'h1 == archit_ptr_27 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2801 = 6'h2 == archit_ptr_27 ? log_reg_2 : _GEN_2800; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2802 = 6'h3 == archit_ptr_27 ? log_reg_3 : _GEN_2801; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2803 = 6'h4 == archit_ptr_27 ? log_reg_4 : _GEN_2802; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2804 = 6'h5 == archit_ptr_27 ? log_reg_5 : _GEN_2803; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2805 = 6'h6 == archit_ptr_27 ? log_reg_6 : _GEN_2804; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2806 = 6'h7 == archit_ptr_27 ? log_reg_7 : _GEN_2805; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2807 = 6'h8 == archit_ptr_27 ? log_reg_8 : _GEN_2806; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2808 = 6'h9 == archit_ptr_27 ? log_reg_9 : _GEN_2807; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2809 = 6'ha == archit_ptr_27 ? log_reg_10 : _GEN_2808; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2810 = 6'hb == archit_ptr_27 ? log_reg_11 : _GEN_2809; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2811 = 6'hc == archit_ptr_27 ? log_reg_12 : _GEN_2810; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2812 = 6'hd == archit_ptr_27 ? log_reg_13 : _GEN_2811; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2813 = 6'he == archit_ptr_27 ? log_reg_14 : _GEN_2812; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2814 = 6'hf == archit_ptr_27 ? log_reg_15 : _GEN_2813; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2815 = 6'h10 == archit_ptr_27 ? log_reg_16 : _GEN_2814; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2816 = 6'h11 == archit_ptr_27 ? log_reg_17 : _GEN_2815; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2817 = 6'h12 == archit_ptr_27 ? log_reg_18 : _GEN_2816; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2818 = 6'h13 == archit_ptr_27 ? log_reg_19 : _GEN_2817; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2819 = 6'h14 == archit_ptr_27 ? log_reg_20 : _GEN_2818; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2820 = 6'h15 == archit_ptr_27 ? log_reg_21 : _GEN_2819; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2821 = 6'h16 == archit_ptr_27 ? log_reg_22 : _GEN_2820; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2822 = 6'h17 == archit_ptr_27 ? log_reg_23 : _GEN_2821; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2823 = 6'h18 == archit_ptr_27 ? log_reg_24 : _GEN_2822; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2824 = 6'h19 == archit_ptr_27 ? log_reg_25 : _GEN_2823; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2825 = 6'h1a == archit_ptr_27 ? log_reg_26 : _GEN_2824; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2826 = 6'h1b == archit_ptr_27 ? log_reg_27 : _GEN_2825; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2827 = 6'h1c == archit_ptr_27 ? log_reg_28 : _GEN_2826; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2828 = 6'h1d == archit_ptr_27 ? log_reg_29 : _GEN_2827; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2829 = 6'h1e == archit_ptr_27 ? log_reg_30 : _GEN_2828; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2830 = 6'h1f == archit_ptr_27 ? log_reg_31 : _GEN_2829; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2831 = 6'h20 == archit_ptr_27 ? log_reg_32 : _GEN_2830; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2832 = 6'h21 == archit_ptr_27 ? 2'h3 : _GEN_2831; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2834 = 6'h1 == archit_ptr_28 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2835 = 6'h2 == archit_ptr_28 ? log_reg_2 : _GEN_2834; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2836 = 6'h3 == archit_ptr_28 ? log_reg_3 : _GEN_2835; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2837 = 6'h4 == archit_ptr_28 ? log_reg_4 : _GEN_2836; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2838 = 6'h5 == archit_ptr_28 ? log_reg_5 : _GEN_2837; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2839 = 6'h6 == archit_ptr_28 ? log_reg_6 : _GEN_2838; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2840 = 6'h7 == archit_ptr_28 ? log_reg_7 : _GEN_2839; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2841 = 6'h8 == archit_ptr_28 ? log_reg_8 : _GEN_2840; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2842 = 6'h9 == archit_ptr_28 ? log_reg_9 : _GEN_2841; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2843 = 6'ha == archit_ptr_28 ? log_reg_10 : _GEN_2842; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2844 = 6'hb == archit_ptr_28 ? log_reg_11 : _GEN_2843; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2845 = 6'hc == archit_ptr_28 ? log_reg_12 : _GEN_2844; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2846 = 6'hd == archit_ptr_28 ? log_reg_13 : _GEN_2845; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2847 = 6'he == archit_ptr_28 ? log_reg_14 : _GEN_2846; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2848 = 6'hf == archit_ptr_28 ? log_reg_15 : _GEN_2847; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2849 = 6'h10 == archit_ptr_28 ? log_reg_16 : _GEN_2848; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2850 = 6'h11 == archit_ptr_28 ? log_reg_17 : _GEN_2849; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2851 = 6'h12 == archit_ptr_28 ? log_reg_18 : _GEN_2850; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2852 = 6'h13 == archit_ptr_28 ? log_reg_19 : _GEN_2851; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2853 = 6'h14 == archit_ptr_28 ? log_reg_20 : _GEN_2852; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2854 = 6'h15 == archit_ptr_28 ? log_reg_21 : _GEN_2853; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2855 = 6'h16 == archit_ptr_28 ? log_reg_22 : _GEN_2854; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2856 = 6'h17 == archit_ptr_28 ? log_reg_23 : _GEN_2855; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2857 = 6'h18 == archit_ptr_28 ? log_reg_24 : _GEN_2856; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2858 = 6'h19 == archit_ptr_28 ? log_reg_25 : _GEN_2857; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2859 = 6'h1a == archit_ptr_28 ? log_reg_26 : _GEN_2858; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2860 = 6'h1b == archit_ptr_28 ? log_reg_27 : _GEN_2859; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2861 = 6'h1c == archit_ptr_28 ? log_reg_28 : _GEN_2860; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2862 = 6'h1d == archit_ptr_28 ? log_reg_29 : _GEN_2861; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2863 = 6'h1e == archit_ptr_28 ? log_reg_30 : _GEN_2862; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2864 = 6'h1f == archit_ptr_28 ? log_reg_31 : _GEN_2863; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2865 = 6'h20 == archit_ptr_28 ? log_reg_32 : _GEN_2864; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2866 = 6'h21 == archit_ptr_28 ? 2'h3 : _GEN_2865; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2868 = 6'h1 == archit_ptr_29 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2869 = 6'h2 == archit_ptr_29 ? log_reg_2 : _GEN_2868; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2870 = 6'h3 == archit_ptr_29 ? log_reg_3 : _GEN_2869; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2871 = 6'h4 == archit_ptr_29 ? log_reg_4 : _GEN_2870; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2872 = 6'h5 == archit_ptr_29 ? log_reg_5 : _GEN_2871; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2873 = 6'h6 == archit_ptr_29 ? log_reg_6 : _GEN_2872; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2874 = 6'h7 == archit_ptr_29 ? log_reg_7 : _GEN_2873; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2875 = 6'h8 == archit_ptr_29 ? log_reg_8 : _GEN_2874; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2876 = 6'h9 == archit_ptr_29 ? log_reg_9 : _GEN_2875; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2877 = 6'ha == archit_ptr_29 ? log_reg_10 : _GEN_2876; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2878 = 6'hb == archit_ptr_29 ? log_reg_11 : _GEN_2877; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2879 = 6'hc == archit_ptr_29 ? log_reg_12 : _GEN_2878; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2880 = 6'hd == archit_ptr_29 ? log_reg_13 : _GEN_2879; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2881 = 6'he == archit_ptr_29 ? log_reg_14 : _GEN_2880; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2882 = 6'hf == archit_ptr_29 ? log_reg_15 : _GEN_2881; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2883 = 6'h10 == archit_ptr_29 ? log_reg_16 : _GEN_2882; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2884 = 6'h11 == archit_ptr_29 ? log_reg_17 : _GEN_2883; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2885 = 6'h12 == archit_ptr_29 ? log_reg_18 : _GEN_2884; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2886 = 6'h13 == archit_ptr_29 ? log_reg_19 : _GEN_2885; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2887 = 6'h14 == archit_ptr_29 ? log_reg_20 : _GEN_2886; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2888 = 6'h15 == archit_ptr_29 ? log_reg_21 : _GEN_2887; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2889 = 6'h16 == archit_ptr_29 ? log_reg_22 : _GEN_2888; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2890 = 6'h17 == archit_ptr_29 ? log_reg_23 : _GEN_2889; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2891 = 6'h18 == archit_ptr_29 ? log_reg_24 : _GEN_2890; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2892 = 6'h19 == archit_ptr_29 ? log_reg_25 : _GEN_2891; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2893 = 6'h1a == archit_ptr_29 ? log_reg_26 : _GEN_2892; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2894 = 6'h1b == archit_ptr_29 ? log_reg_27 : _GEN_2893; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2895 = 6'h1c == archit_ptr_29 ? log_reg_28 : _GEN_2894; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2896 = 6'h1d == archit_ptr_29 ? log_reg_29 : _GEN_2895; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2897 = 6'h1e == archit_ptr_29 ? log_reg_30 : _GEN_2896; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2898 = 6'h1f == archit_ptr_29 ? log_reg_31 : _GEN_2897; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2899 = 6'h20 == archit_ptr_29 ? log_reg_32 : _GEN_2898; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2900 = 6'h21 == archit_ptr_29 ? 2'h3 : _GEN_2899; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2902 = 6'h1 == archit_ptr_30 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2903 = 6'h2 == archit_ptr_30 ? log_reg_2 : _GEN_2902; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2904 = 6'h3 == archit_ptr_30 ? log_reg_3 : _GEN_2903; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2905 = 6'h4 == archit_ptr_30 ? log_reg_4 : _GEN_2904; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2906 = 6'h5 == archit_ptr_30 ? log_reg_5 : _GEN_2905; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2907 = 6'h6 == archit_ptr_30 ? log_reg_6 : _GEN_2906; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2908 = 6'h7 == archit_ptr_30 ? log_reg_7 : _GEN_2907; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2909 = 6'h8 == archit_ptr_30 ? log_reg_8 : _GEN_2908; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2910 = 6'h9 == archit_ptr_30 ? log_reg_9 : _GEN_2909; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2911 = 6'ha == archit_ptr_30 ? log_reg_10 : _GEN_2910; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2912 = 6'hb == archit_ptr_30 ? log_reg_11 : _GEN_2911; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2913 = 6'hc == archit_ptr_30 ? log_reg_12 : _GEN_2912; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2914 = 6'hd == archit_ptr_30 ? log_reg_13 : _GEN_2913; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2915 = 6'he == archit_ptr_30 ? log_reg_14 : _GEN_2914; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2916 = 6'hf == archit_ptr_30 ? log_reg_15 : _GEN_2915; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2917 = 6'h10 == archit_ptr_30 ? log_reg_16 : _GEN_2916; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2918 = 6'h11 == archit_ptr_30 ? log_reg_17 : _GEN_2917; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2919 = 6'h12 == archit_ptr_30 ? log_reg_18 : _GEN_2918; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2920 = 6'h13 == archit_ptr_30 ? log_reg_19 : _GEN_2919; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2921 = 6'h14 == archit_ptr_30 ? log_reg_20 : _GEN_2920; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2922 = 6'h15 == archit_ptr_30 ? log_reg_21 : _GEN_2921; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2923 = 6'h16 == archit_ptr_30 ? log_reg_22 : _GEN_2922; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2924 = 6'h17 == archit_ptr_30 ? log_reg_23 : _GEN_2923; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2925 = 6'h18 == archit_ptr_30 ? log_reg_24 : _GEN_2924; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2926 = 6'h19 == archit_ptr_30 ? log_reg_25 : _GEN_2925; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2927 = 6'h1a == archit_ptr_30 ? log_reg_26 : _GEN_2926; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2928 = 6'h1b == archit_ptr_30 ? log_reg_27 : _GEN_2927; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2929 = 6'h1c == archit_ptr_30 ? log_reg_28 : _GEN_2928; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2930 = 6'h1d == archit_ptr_30 ? log_reg_29 : _GEN_2929; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2931 = 6'h1e == archit_ptr_30 ? log_reg_30 : _GEN_2930; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2932 = 6'h1f == archit_ptr_30 ? log_reg_31 : _GEN_2931; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2933 = 6'h20 == archit_ptr_30 ? log_reg_32 : _GEN_2932; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2934 = 6'h21 == archit_ptr_30 ? 2'h3 : _GEN_2933; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2936 = 6'h1 == archit_ptr_31 ? log_reg_1 : log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2937 = 6'h2 == archit_ptr_31 ? log_reg_2 : _GEN_2936; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2938 = 6'h3 == archit_ptr_31 ? log_reg_3 : _GEN_2937; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2939 = 6'h4 == archit_ptr_31 ? log_reg_4 : _GEN_2938; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2940 = 6'h5 == archit_ptr_31 ? log_reg_5 : _GEN_2939; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2941 = 6'h6 == archit_ptr_31 ? log_reg_6 : _GEN_2940; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2942 = 6'h7 == archit_ptr_31 ? log_reg_7 : _GEN_2941; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2943 = 6'h8 == archit_ptr_31 ? log_reg_8 : _GEN_2942; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2944 = 6'h9 == archit_ptr_31 ? log_reg_9 : _GEN_2943; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2945 = 6'ha == archit_ptr_31 ? log_reg_10 : _GEN_2944; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2946 = 6'hb == archit_ptr_31 ? log_reg_11 : _GEN_2945; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2947 = 6'hc == archit_ptr_31 ? log_reg_12 : _GEN_2946; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2948 = 6'hd == archit_ptr_31 ? log_reg_13 : _GEN_2947; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2949 = 6'he == archit_ptr_31 ? log_reg_14 : _GEN_2948; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2950 = 6'hf == archit_ptr_31 ? log_reg_15 : _GEN_2949; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2951 = 6'h10 == archit_ptr_31 ? log_reg_16 : _GEN_2950; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2952 = 6'h11 == archit_ptr_31 ? log_reg_17 : _GEN_2951; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2953 = 6'h12 == archit_ptr_31 ? log_reg_18 : _GEN_2952; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2954 = 6'h13 == archit_ptr_31 ? log_reg_19 : _GEN_2953; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2955 = 6'h14 == archit_ptr_31 ? log_reg_20 : _GEN_2954; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2956 = 6'h15 == archit_ptr_31 ? log_reg_21 : _GEN_2955; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2957 = 6'h16 == archit_ptr_31 ? log_reg_22 : _GEN_2956; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2958 = 6'h17 == archit_ptr_31 ? log_reg_23 : _GEN_2957; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2959 = 6'h18 == archit_ptr_31 ? log_reg_24 : _GEN_2958; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2960 = 6'h19 == archit_ptr_31 ? log_reg_25 : _GEN_2959; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2961 = 6'h1a == archit_ptr_31 ? log_reg_26 : _GEN_2960; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2962 = 6'h1b == archit_ptr_31 ? log_reg_27 : _GEN_2961; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2963 = 6'h1c == archit_ptr_31 ? log_reg_28 : _GEN_2962; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2964 = 6'h1d == archit_ptr_31 ? log_reg_29 : _GEN_2963; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2965 = 6'h1e == archit_ptr_31 ? log_reg_30 : _GEN_2964; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2966 = 6'h1f == archit_ptr_31 ? log_reg_31 : _GEN_2965; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2967 = 6'h20 == archit_ptr_31 ? log_reg_32 : _GEN_2966; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] _GEN_2968 = 6'h21 == archit_ptr_31 ? 2'h3 : _GEN_2967; // @[Regfiles.scala 242:{25,25}]
  wire  _GEN_5 = _T_114 & _T_37; // @[Regfiles.scala 227:13]
  assign io_rename_0_req_ready = _io_rename_0_req_ready_T_98 > 6'h0; // @[Regfiles.scala 165:70]
  assign io_rgRsp_0_valid = io_rgRsp_0_valid_REG; // @[Regfiles.scala 191:26]
  assign io_exe_writeBack_0_ready = 1'h1; // @[Regfiles.scala 207:31]
  assign io_commit_0_is_writeback = _GEN_1619 == 2'h3; // @[Regfiles.scala 219:46]
  always @(posedge clock) begin
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_0 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h0 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_0 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h0 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_0 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_0 <= _GEN_1620;
      end
    end else begin
      log_reg_0 <= _GEN_1620;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_1 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h1 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_1 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h1 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_1 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_1 <= _GEN_1621;
      end
    end else begin
      log_reg_1 <= _GEN_1621;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_2 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h2 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_2 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h2 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_2 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_2 <= _GEN_1622;
      end
    end else begin
      log_reg_2 <= _GEN_1622;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_3 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h3 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_3 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h3 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_3 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_3 <= _GEN_1623;
      end
    end else begin
      log_reg_3 <= _GEN_1623;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_4 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h4 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_4 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h4 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_4 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_4 <= _GEN_1624;
      end
    end else begin
      log_reg_4 <= _GEN_1624;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_5 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h5 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_5 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h5 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_5 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_5 <= _GEN_1625;
      end
    end else begin
      log_reg_5 <= _GEN_1625;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_6 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h6 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_6 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h6 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_6 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_6 <= _GEN_1626;
      end
    end else begin
      log_reg_6 <= _GEN_1626;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_7 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h7 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_7 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h7 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_7 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_7 <= _GEN_1627;
      end
    end else begin
      log_reg_7 <= _GEN_1627;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_8 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h8 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_8 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h8 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_8 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_8 <= _GEN_1628;
      end
    end else begin
      log_reg_8 <= _GEN_1628;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_9 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h9 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_9 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h9 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_9 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_9 <= _GEN_1629;
      end
    end else begin
      log_reg_9 <= _GEN_1629;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_10 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'ha == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_10 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'ha == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_10 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_10 <= _GEN_1630;
      end
    end else begin
      log_reg_10 <= _GEN_1630;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_11 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'hb == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_11 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'hb == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_11 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_11 <= _GEN_1631;
      end
    end else begin
      log_reg_11 <= _GEN_1631;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_12 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'hc == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_12 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'hc == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_12 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_12 <= _GEN_1632;
      end
    end else begin
      log_reg_12 <= _GEN_1632;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_13 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'hd == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_13 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'hd == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_13 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_13 <= _GEN_1633;
      end
    end else begin
      log_reg_13 <= _GEN_1633;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_14 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'he == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_14 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'he == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_14 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_14 <= _GEN_1634;
      end
    end else begin
      log_reg_14 <= _GEN_1634;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_15 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'hf == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_15 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'hf == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_15 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_15 <= _GEN_1635;
      end
    end else begin
      log_reg_15 <= _GEN_1635;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_16 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h10 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_16 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h10 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_16 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_16 <= _GEN_1636;
      end
    end else begin
      log_reg_16 <= _GEN_1636;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_17 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h11 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_17 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h11 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_17 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_17 <= _GEN_1637;
      end
    end else begin
      log_reg_17 <= _GEN_1637;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_18 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h12 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_18 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h12 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_18 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_18 <= _GEN_1638;
      end
    end else begin
      log_reg_18 <= _GEN_1638;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_19 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h13 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_19 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h13 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_19 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_19 <= _GEN_1639;
      end
    end else begin
      log_reg_19 <= _GEN_1639;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_20 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h14 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_20 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h14 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_20 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_20 <= _GEN_1640;
      end
    end else begin
      log_reg_20 <= _GEN_1640;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_21 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h15 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_21 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h15 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_21 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_21 <= _GEN_1641;
      end
    end else begin
      log_reg_21 <= _GEN_1641;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_22 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h16 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_22 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h16 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_22 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_22 <= _GEN_1642;
      end
    end else begin
      log_reg_22 <= _GEN_1642;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_23 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h17 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_23 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h17 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_23 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_23 <= _GEN_1643;
      end
    end else begin
      log_reg_23 <= _GEN_1643;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_24 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h18 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_24 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h18 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_24 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_24 <= _GEN_1644;
      end
    end else begin
      log_reg_24 <= _GEN_1644;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_25 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h19 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_25 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h19 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_25 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_25 <= _GEN_1645;
      end
    end else begin
      log_reg_25 <= _GEN_1645;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_26 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h1a == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_26 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h1a == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_26 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_26 <= _GEN_1646;
      end
    end else begin
      log_reg_26 <= _GEN_1646;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_27 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h1b == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_27 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h1b == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_27 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_27 <= _GEN_1647;
      end
    end else begin
      log_reg_27 <= _GEN_1647;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_28 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h1c == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_28 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h1c == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_28 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_28 <= _GEN_1648;
      end
    end else begin
      log_reg_28 <= _GEN_1648;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_29 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h1d == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_29 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h1d == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_29 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_29 <= _GEN_1649;
      end
    end else begin
      log_reg_29 <= _GEN_1649;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_30 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h1e == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_30 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h1e == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_30 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_30 <= _GEN_1650;
      end
    end else begin
      log_reg_30 <= _GEN_1650;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_31 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h1f == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_31 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h1f == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_31 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_31 <= _GEN_1651;
      end
    end else begin
      log_reg_31 <= _GEN_1651;
    end
    if (reset) begin // @[Regfiles.scala 101:12]
      log_reg_32 <= 2'h0; // @[Regfiles.scala 101:12]
    end else if (io_commit_0_is_MisPredict | io_commit_0_is_comfirm) begin // @[Regfiles.scala 225:66]
      if (6'h20 == io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        log_reg_32 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (6'h20 == _GEN_1684) begin // @[Regfiles.scala 229:35]
        log_reg_32 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        log_reg_32 <= _GEN_1652;
      end
    end else begin
      log_reg_32 <= _GEN_1652;
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_0 <= 6'h0; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h0 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_0 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_1 <= 6'h1; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_1 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_2 <= 6'h2; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h2 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_2 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_3 <= 6'h3; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h3 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_3 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_4 <= 6'h4; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h4 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_4 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_5 <= 6'h5; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h5 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_5 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_6 <= 6'h6; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h6 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_6 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_7 <= 6'h7; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h7 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_7 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_8 <= 6'h8; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h8 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_8 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_9 <= 6'h9; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h9 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_9 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_10 <= 6'ha; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'ha == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_10 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_11 <= 6'hb; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'hb == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_11 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_12 <= 6'hc; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'hc == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_12 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_13 <= 6'hd; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'hd == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_13 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_14 <= 6'he; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'he == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_14 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_15 <= 6'hf; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'hf == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_15 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_16 <= 6'h10; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h10 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_16 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_17 <= 6'h11; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h11 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_17 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_18 <= 6'h12; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h12 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_18 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_19 <= 6'h13; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h13 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_19 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_20 <= 6'h14; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h14 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_20 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_21 <= 6'h15; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h15 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_21 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_22 <= 6'h16; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h16 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_22 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_23 <= 6'h17; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h17 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_23 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_24 <= 6'h18; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h18 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_24 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_25 <= 6'h19; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h19 == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_25 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_26 <= 6'h1a; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1a == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_26 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_27 <= 6'h1b; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1b == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_27 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_28 <= 6'h1c; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1c == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_28 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_29 <= 6'h1d; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1d == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_29 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_30 <= 6'h1e; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1e == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_30 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 130:27]
      archit_ptr_31 <= 6'h1f; // @[Regfiles.scala 130:27]
    end else if (_T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1f == io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        archit_ptr_31 <= io_commit_0_phy; // @[Regfiles.scala 236:26]
      end
    end
    if (reset) begin // @[Regfiles.scala 191:36]
      io_rgRsp_0_valid_REG <= 1'h0; // @[Regfiles.scala 191:36]
    end else begin
      io_rgRsp_0_valid_REG <= io_rgReq_0_valid; // @[Regfiles.scala 191:36]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_34 & ~reset & ~(_GEN_1155 == 2'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Regfiles.scala:160 assert( log(molloc_idx(i)) === \"b00\".U )\n"); // @[Regfiles.scala 160:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_1155 == 2'h0) & (_T_34 & ~reset)) begin
          $fatal; // @[Regfiles.scala 160:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_rgRsp_0_valid & _T_37 & ~(_GEN_1419 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed while reading operator, log is not ready!\n    at Regfiles.scala:194 when( io.rgRsp(i).valid ) {  assert( log(io.rgReq(i).bits) === \"b11\".U, \"Assert Failed while reading operator, log is not ready!\" ) }\n"
            ); // @[Regfiles.scala 194:40]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_1419 == 2'h3) & (io_rgRsp_0_valid & _T_37)) begin
          $fatal; // @[Regfiles.scala 194:40]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_108 & _T_37 & ~(_GEN_1453 == 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed when writeback at chn0, log(XRegFiles.io.exe_writeBack[0].bits.rd0: IO[UInt<6>])\n    at Regfiles.scala:203 assert( log(idx) === \"b01\".U, \"Assert Failed when writeback at chn\" + i + \", log(\" + idx + \")\" )\n"
            ); // @[Regfiles.scala 203:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_1453 == 2'h1) & (_T_108 & _T_37)) begin
          $fatal; // @[Regfiles.scala 203:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_114 & _T_37 & ~io_commit_0_is_writeback) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Regfiles.scala:227 assert( io.commit(m).is_writeback )\n"); // @[Regfiles.scala 227:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~io_commit_0_is_writeback & (_T_114 & _T_37)) begin
          $fatal; // @[Regfiles.scala 227:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_5 & ~(_GEN_1618 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: log_reg which going to commit to will be overrided to \"b11\" if there is an abort in-front.\n    at Regfiles.scala:231 assert( log_reg(phy(m)) === \"b11\".U, \"log_reg which going to commit to will be overrided to \\\"b11\\\" if there is an abort in-front.\" )\n"
            ); // @[Regfiles.scala 231:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_1618 == 2'h3) & (_T_114 & _T_37)) begin
          $fatal; // @[Regfiles.scala 231:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_1914 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[0]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_1914 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_1948 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[1]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_1948 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_1982 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[2]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_1982 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2016 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[3]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2016 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2050 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[4]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2050 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2084 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[5]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2084 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2118 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[6]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2118 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2152 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[7]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2152 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2186 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[8]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2186 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2220 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[9]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2220 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2254 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[10]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2254 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2288 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[11]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2288 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2322 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[12]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2322 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2356 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[13]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2356 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2390 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[14]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2390 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2424 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[15]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2424 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2458 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[16]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2458 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2492 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[17]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2492 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2526 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[18]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2526 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2560 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[19]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2560 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2594 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[20]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2594 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2628 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[21]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2628 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2662 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[22]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2662 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2696 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[23]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2696 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2730 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[24]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2730 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2764 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[25]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2764 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2798 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[26]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2798 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2832 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[27]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2832 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2866 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[28]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2866 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2900 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[29]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2900 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2934 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[30]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2934 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_37 & ~(_GEN_2968 == 2'h3)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[31]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_GEN_2968 == 2'h3) & _T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  log_reg_0 = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  log_reg_1 = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  log_reg_2 = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  log_reg_3 = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  log_reg_4 = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  log_reg_5 = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  log_reg_6 = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  log_reg_7 = _RAND_7[1:0];
  _RAND_8 = {1{`RANDOM}};
  log_reg_8 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  log_reg_9 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  log_reg_10 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  log_reg_11 = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  log_reg_12 = _RAND_12[1:0];
  _RAND_13 = {1{`RANDOM}};
  log_reg_13 = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  log_reg_14 = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  log_reg_15 = _RAND_15[1:0];
  _RAND_16 = {1{`RANDOM}};
  log_reg_16 = _RAND_16[1:0];
  _RAND_17 = {1{`RANDOM}};
  log_reg_17 = _RAND_17[1:0];
  _RAND_18 = {1{`RANDOM}};
  log_reg_18 = _RAND_18[1:0];
  _RAND_19 = {1{`RANDOM}};
  log_reg_19 = _RAND_19[1:0];
  _RAND_20 = {1{`RANDOM}};
  log_reg_20 = _RAND_20[1:0];
  _RAND_21 = {1{`RANDOM}};
  log_reg_21 = _RAND_21[1:0];
  _RAND_22 = {1{`RANDOM}};
  log_reg_22 = _RAND_22[1:0];
  _RAND_23 = {1{`RANDOM}};
  log_reg_23 = _RAND_23[1:0];
  _RAND_24 = {1{`RANDOM}};
  log_reg_24 = _RAND_24[1:0];
  _RAND_25 = {1{`RANDOM}};
  log_reg_25 = _RAND_25[1:0];
  _RAND_26 = {1{`RANDOM}};
  log_reg_26 = _RAND_26[1:0];
  _RAND_27 = {1{`RANDOM}};
  log_reg_27 = _RAND_27[1:0];
  _RAND_28 = {1{`RANDOM}};
  log_reg_28 = _RAND_28[1:0];
  _RAND_29 = {1{`RANDOM}};
  log_reg_29 = _RAND_29[1:0];
  _RAND_30 = {1{`RANDOM}};
  log_reg_30 = _RAND_30[1:0];
  _RAND_31 = {1{`RANDOM}};
  log_reg_31 = _RAND_31[1:0];
  _RAND_32 = {1{`RANDOM}};
  log_reg_32 = _RAND_32[1:0];
  _RAND_33 = {1{`RANDOM}};
  archit_ptr_0 = _RAND_33[5:0];
  _RAND_34 = {1{`RANDOM}};
  archit_ptr_1 = _RAND_34[5:0];
  _RAND_35 = {1{`RANDOM}};
  archit_ptr_2 = _RAND_35[5:0];
  _RAND_36 = {1{`RANDOM}};
  archit_ptr_3 = _RAND_36[5:0];
  _RAND_37 = {1{`RANDOM}};
  archit_ptr_4 = _RAND_37[5:0];
  _RAND_38 = {1{`RANDOM}};
  archit_ptr_5 = _RAND_38[5:0];
  _RAND_39 = {1{`RANDOM}};
  archit_ptr_6 = _RAND_39[5:0];
  _RAND_40 = {1{`RANDOM}};
  archit_ptr_7 = _RAND_40[5:0];
  _RAND_41 = {1{`RANDOM}};
  archit_ptr_8 = _RAND_41[5:0];
  _RAND_42 = {1{`RANDOM}};
  archit_ptr_9 = _RAND_42[5:0];
  _RAND_43 = {1{`RANDOM}};
  archit_ptr_10 = _RAND_43[5:0];
  _RAND_44 = {1{`RANDOM}};
  archit_ptr_11 = _RAND_44[5:0];
  _RAND_45 = {1{`RANDOM}};
  archit_ptr_12 = _RAND_45[5:0];
  _RAND_46 = {1{`RANDOM}};
  archit_ptr_13 = _RAND_46[5:0];
  _RAND_47 = {1{`RANDOM}};
  archit_ptr_14 = _RAND_47[5:0];
  _RAND_48 = {1{`RANDOM}};
  archit_ptr_15 = _RAND_48[5:0];
  _RAND_49 = {1{`RANDOM}};
  archit_ptr_16 = _RAND_49[5:0];
  _RAND_50 = {1{`RANDOM}};
  archit_ptr_17 = _RAND_50[5:0];
  _RAND_51 = {1{`RANDOM}};
  archit_ptr_18 = _RAND_51[5:0];
  _RAND_52 = {1{`RANDOM}};
  archit_ptr_19 = _RAND_52[5:0];
  _RAND_53 = {1{`RANDOM}};
  archit_ptr_20 = _RAND_53[5:0];
  _RAND_54 = {1{`RANDOM}};
  archit_ptr_21 = _RAND_54[5:0];
  _RAND_55 = {1{`RANDOM}};
  archit_ptr_22 = _RAND_55[5:0];
  _RAND_56 = {1{`RANDOM}};
  archit_ptr_23 = _RAND_56[5:0];
  _RAND_57 = {1{`RANDOM}};
  archit_ptr_24 = _RAND_57[5:0];
  _RAND_58 = {1{`RANDOM}};
  archit_ptr_25 = _RAND_58[5:0];
  _RAND_59 = {1{`RANDOM}};
  archit_ptr_26 = _RAND_59[5:0];
  _RAND_60 = {1{`RANDOM}};
  archit_ptr_27 = _RAND_60[5:0];
  _RAND_61 = {1{`RANDOM}};
  archit_ptr_28 = _RAND_61[5:0];
  _RAND_62 = {1{`RANDOM}};
  archit_ptr_29 = _RAND_62[5:0];
  _RAND_63 = {1{`RANDOM}};
  archit_ptr_30 = _RAND_63[5:0];
  _RAND_64 = {1{`RANDOM}};
  archit_ptr_31 = _RAND_64[5:0];
  _RAND_65 = {1{`RANDOM}};
  io_rgRsp_0_valid_REG = _RAND_65[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module FakeFRegFiles(
  input   clock,
  input   reset,
  input   io_exe_writeBack_0_valid,
  input   io_exe_writeBack_1_valid
);
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_exe_writeBack_0_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Regfiles.scala:324 assert( ~io.exe_writeBack(i).valid )\n"); // @[Regfiles.scala 324:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_exe_writeBack_0_valid) & ~reset) begin
          $fatal; // @[Regfiles.scala 324:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_exe_writeBack_1_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Regfiles.scala:324 assert( ~io.exe_writeBack(i).valid )\n"); // @[Regfiles.scala 324:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_exe_writeBack_1_valid) & ~reset) begin
          $fatal; // @[Regfiles.scala 324:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module XArbiter(
  input        io_enq_0_valid,
  input  [5:0] io_enq_0_bits_rd0,
  input        io_enq_1_valid,
  input  [5:0] io_enq_1_bits_rd0,
  input        io_enq_2_valid,
  input  [5:0] io_enq_2_bits_rd0,
  input        io_enq_3_valid,
  input  [5:0] io_enq_3_bits_rd0,
  input        io_enq_4_valid,
  input  [5:0] io_enq_4_bits_rd0,
  input        io_enq_5_valid,
  input  [5:0] io_enq_5_bits_rd0,
  output       io_deq_0_valid,
  output [5:0] io_deq_0_bits_rd0,
  output [2:0] io_chosen_0
);
  wire [2:0] _GEN_0 = io_enq_5_valid ? 3'h5 : 3'h0; // @[XArbiter.scala 34:18 36:31 37:38]
  wire [2:0] _GEN_1 = io_enq_4_valid ? 3'h4 : _GEN_0; // @[XArbiter.scala 36:31 37:38]
  wire [2:0] _GEN_2 = io_enq_3_valid ? 3'h3 : _GEN_1; // @[XArbiter.scala 36:31 37:38]
  wire [2:0] _GEN_3 = io_enq_2_valid ? 3'h2 : _GEN_2; // @[XArbiter.scala 36:31 37:38]
  wire [2:0] _GEN_4 = io_enq_1_valid ? 3'h1 : _GEN_3; // @[XArbiter.scala 36:31 37:38]
  wire [1:0] _T_6 = io_enq_1_valid + io_enq_2_valid; // @[XArbiter.scala 53:23]
  wire [1:0] _GEN_12 = {{1'd0}, io_enq_0_valid}; // @[XArbiter.scala 53:23]
  wire [2:0] _T_8 = _GEN_12 + _T_6; // @[XArbiter.scala 53:23]
  wire [1:0] _T_10 = io_enq_4_valid + io_enq_5_valid; // @[XArbiter.scala 53:23]
  wire [1:0] _GEN_13 = {{1'd0}, io_enq_3_valid}; // @[XArbiter.scala 53:23]
  wire [2:0] _T_12 = _GEN_13 + _T_10; // @[XArbiter.scala 53:23]
  wire [2:0] _T_14 = _T_8[1:0] + _T_12[1:0]; // @[XArbiter.scala 53:23]
  wire [5:0] _GEN_7 = 3'h1 == io_chosen_0 ? io_enq_1_bits_rd0 : io_enq_0_bits_rd0; // @[XArbiter.scala 55:{22,22}]
  wire [5:0] _GEN_8 = 3'h2 == io_chosen_0 ? io_enq_2_bits_rd0 : _GEN_7; // @[XArbiter.scala 55:{22,22}]
  wire [5:0] _GEN_9 = 3'h3 == io_chosen_0 ? io_enq_3_bits_rd0 : _GEN_8; // @[XArbiter.scala 55:{22,22}]
  wire [5:0] _GEN_10 = 3'h4 == io_chosen_0 ? io_enq_4_bits_rd0 : _GEN_9; // @[XArbiter.scala 55:{22,22}]
  assign io_deq_0_valid = _T_14 > 3'h0; // @[XArbiter.scala 53:68]
  assign io_deq_0_bits_rd0 = 3'h5 == io_chosen_0 ? io_enq_5_bits_rd0 : _GEN_10; // @[XArbiter.scala 55:{22,22}]
  assign io_chosen_0 = io_enq_0_valid ? 3'h0 : _GEN_4; // @[XArbiter.scala 36:31 37:38]
endmodule
module WriteBack(
  input        clock,
  input        reset,
  input        io_xRename_0_req_valid,
  input        io_irgReq_0_valid,
  input  [5:0] io_irgReq_0_bits,
  input        io_alu_iWriteBack_0_valid,
  input  [5:0] io_alu_iWriteBack_0_bits_rd0,
  input        io_bru_iWriteBack_valid,
  input  [5:0] io_bru_iWriteBack_bits_rd0,
  input        io_csr_iWriteBack_valid,
  input  [5:0] io_csr_iWriteBack_bits_rd0,
  input        io_mem_iWriteBack_valid,
  input  [5:0] io_mem_iWriteBack_bits_rd0,
  input        io_mul_iWriteBack_0_valid,
  input  [5:0] io_mul_iWriteBack_0_bits_rd0,
  input        io_fpu_iWriteBack_0_valid,
  input  [5:0] io_fpu_iWriteBack_0_bits_rd0,
  input        io_mem_fWriteBack_valid,
  input        io_fpu_fWriteBack_0_valid,
  input        io_commit_0_is_comfirm,
  input        io_commit_0_is_MisPredict,
  input        io_commit_0_is_abort,
  input  [4:0] io_commit_0_raw,
  input  [5:0] io_commit_0_phy,
  input        io_commit_0_toX
);
  wire  iReg_clock; // @[WriteBack.scala 70:20]
  wire  iReg_reset; // @[WriteBack.scala 70:20]
  wire  iReg_io_rename_0_req_ready; // @[WriteBack.scala 70:20]
  wire  iReg_io_rename_0_req_valid; // @[WriteBack.scala 70:20]
  wire  iReg_io_rgReq_0_valid; // @[WriteBack.scala 70:20]
  wire [5:0] iReg_io_rgReq_0_bits; // @[WriteBack.scala 70:20]
  wire  iReg_io_rgRsp_0_valid; // @[WriteBack.scala 70:20]
  wire  iReg_io_exe_writeBack_0_ready; // @[WriteBack.scala 70:20]
  wire  iReg_io_exe_writeBack_0_valid; // @[WriteBack.scala 70:20]
  wire [5:0] iReg_io_exe_writeBack_0_bits_rd0; // @[WriteBack.scala 70:20]
  wire  iReg_io_commit_0_is_comfirm; // @[WriteBack.scala 70:20]
  wire  iReg_io_commit_0_is_MisPredict; // @[WriteBack.scala 70:20]
  wire  iReg_io_commit_0_is_abort; // @[WriteBack.scala 70:20]
  wire [4:0] iReg_io_commit_0_raw; // @[WriteBack.scala 70:20]
  wire [5:0] iReg_io_commit_0_phy; // @[WriteBack.scala 70:20]
  wire  iReg_io_commit_0_is_writeback; // @[WriteBack.scala 70:20]
  wire  fReg_clock; // @[WriteBack.scala 71:97]
  wire  fReg_reset; // @[WriteBack.scala 71:97]
  wire  fReg_io_exe_writeBack_0_valid; // @[WriteBack.scala 71:97]
  wire  fReg_io_exe_writeBack_1_valid; // @[WriteBack.scala 71:97]
  wire  iwriteBack_arb_io_enq_0_valid; // @[WriteBack.scala 127:21]
  wire [5:0] iwriteBack_arb_io_enq_0_bits_rd0; // @[WriteBack.scala 127:21]
  wire  iwriteBack_arb_io_enq_1_valid; // @[WriteBack.scala 127:21]
  wire [5:0] iwriteBack_arb_io_enq_1_bits_rd0; // @[WriteBack.scala 127:21]
  wire  iwriteBack_arb_io_enq_2_valid; // @[WriteBack.scala 127:21]
  wire [5:0] iwriteBack_arb_io_enq_2_bits_rd0; // @[WriteBack.scala 127:21]
  wire  iwriteBack_arb_io_enq_3_valid; // @[WriteBack.scala 127:21]
  wire [5:0] iwriteBack_arb_io_enq_3_bits_rd0; // @[WriteBack.scala 127:21]
  wire  iwriteBack_arb_io_enq_4_valid; // @[WriteBack.scala 127:21]
  wire [5:0] iwriteBack_arb_io_enq_4_bits_rd0; // @[WriteBack.scala 127:21]
  wire  iwriteBack_arb_io_enq_5_valid; // @[WriteBack.scala 127:21]
  wire [5:0] iwriteBack_arb_io_enq_5_bits_rd0; // @[WriteBack.scala 127:21]
  wire  iwriteBack_arb_io_deq_0_valid; // @[WriteBack.scala 127:21]
  wire [5:0] iwriteBack_arb_io_deq_0_bits_rd0; // @[WriteBack.scala 127:21]
  wire [2:0] iwriteBack_arb_io_chosen_0; // @[WriteBack.scala 127:21]
  XRegFiles iReg ( // @[WriteBack.scala 70:20]
    .clock(iReg_clock),
    .reset(iReg_reset),
    .io_rename_0_req_ready(iReg_io_rename_0_req_ready),
    .io_rename_0_req_valid(iReg_io_rename_0_req_valid),
    .io_rgReq_0_valid(iReg_io_rgReq_0_valid),
    .io_rgReq_0_bits(iReg_io_rgReq_0_bits),
    .io_rgRsp_0_valid(iReg_io_rgRsp_0_valid),
    .io_exe_writeBack_0_ready(iReg_io_exe_writeBack_0_ready),
    .io_exe_writeBack_0_valid(iReg_io_exe_writeBack_0_valid),
    .io_exe_writeBack_0_bits_rd0(iReg_io_exe_writeBack_0_bits_rd0),
    .io_commit_0_is_comfirm(iReg_io_commit_0_is_comfirm),
    .io_commit_0_is_MisPredict(iReg_io_commit_0_is_MisPredict),
    .io_commit_0_is_abort(iReg_io_commit_0_is_abort),
    .io_commit_0_raw(iReg_io_commit_0_raw),
    .io_commit_0_phy(iReg_io_commit_0_phy),
    .io_commit_0_is_writeback(iReg_io_commit_0_is_writeback)
  );
  FakeFRegFiles fReg ( // @[WriteBack.scala 71:97]
    .clock(fReg_clock),
    .reset(fReg_reset),
    .io_exe_writeBack_0_valid(fReg_io_exe_writeBack_0_valid),
    .io_exe_writeBack_1_valid(fReg_io_exe_writeBack_1_valid)
  );
  XArbiter iwriteBack_arb ( // @[WriteBack.scala 127:21]
    .io_enq_0_valid(iwriteBack_arb_io_enq_0_valid),
    .io_enq_0_bits_rd0(iwriteBack_arb_io_enq_0_bits_rd0),
    .io_enq_1_valid(iwriteBack_arb_io_enq_1_valid),
    .io_enq_1_bits_rd0(iwriteBack_arb_io_enq_1_bits_rd0),
    .io_enq_2_valid(iwriteBack_arb_io_enq_2_valid),
    .io_enq_2_bits_rd0(iwriteBack_arb_io_enq_2_bits_rd0),
    .io_enq_3_valid(iwriteBack_arb_io_enq_3_valid),
    .io_enq_3_bits_rd0(iwriteBack_arb_io_enq_3_bits_rd0),
    .io_enq_4_valid(iwriteBack_arb_io_enq_4_valid),
    .io_enq_4_bits_rd0(iwriteBack_arb_io_enq_4_bits_rd0),
    .io_enq_5_valid(iwriteBack_arb_io_enq_5_valid),
    .io_enq_5_bits_rd0(iwriteBack_arb_io_enq_5_bits_rd0),
    .io_deq_0_valid(iwriteBack_arb_io_deq_0_valid),
    .io_deq_0_bits_rd0(iwriteBack_arb_io_deq_0_bits_rd0),
    .io_chosen_0(iwriteBack_arb_io_chosen_0)
  );
  assign iReg_clock = clock;
  assign iReg_reset = reset;
  assign iReg_io_rename_0_req_valid = io_xRename_0_req_valid; // @[WriteBack.scala 76:23]
  assign iReg_io_rgReq_0_valid = io_irgReq_0_valid; // @[WriteBack.scala 112:17]
  assign iReg_io_rgReq_0_bits = io_irgReq_0_bits; // @[WriteBack.scala 112:17]
  assign iReg_io_exe_writeBack_0_valid = iwriteBack_arb_io_deq_0_valid; // @[WriteBack.scala 136:16]
  assign iReg_io_exe_writeBack_0_bits_rd0 = iwriteBack_arb_io_deq_0_bits_rd0; // @[WriteBack.scala 136:16]
  assign iReg_io_commit_0_is_comfirm = io_commit_0_toX & io_commit_0_is_comfirm; // @[WriteBack.scala 102:{41,60} 84:37]
  assign iReg_io_commit_0_is_MisPredict = io_commit_0_is_MisPredict; // @[WriteBack.scala 102:{41,60} 85:37]
  assign iReg_io_commit_0_is_abort = io_commit_0_is_abort; // @[WriteBack.scala 102:{41,60} 86:37]
  assign iReg_io_commit_0_raw = io_commit_0_toX ? io_commit_0_raw : 5'h0; // @[WriteBack.scala 102:{41,60} 87:37]
  assign iReg_io_commit_0_phy = io_commit_0_toX ? io_commit_0_phy : 6'h0; // @[WriteBack.scala 102:{41,60} 88:37]
  assign fReg_clock = clock;
  assign fReg_reset = reset;
  assign fReg_io_exe_writeBack_0_valid = io_mem_fWriteBack_valid; // @[WriteBack.scala 141:28]
  assign fReg_io_exe_writeBack_1_valid = io_fpu_fWriteBack_0_valid; // @[WriteBack.scala 142:28]
  assign iwriteBack_arb_io_enq_0_valid = io_alu_iWriteBack_0_valid; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_0_bits_rd0 = io_alu_iWriteBack_0_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_1_valid = io_bru_iWriteBack_valid; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_1_bits_rd0 = io_bru_iWriteBack_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_2_valid = io_csr_iWriteBack_valid; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_2_bits_rd0 = io_csr_iWriteBack_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_3_valid = io_mem_iWriteBack_valid; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_3_bits_rd0 = io_mem_iWriteBack_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_4_valid = io_mul_iWriteBack_0_valid; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_4_bits_rd0 = io_mul_iWriteBack_0_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_5_valid = io_fpu_iWriteBack_0_valid; // @[WriteBack.scala 129:16]
  assign iwriteBack_arb_io_enq_5_bits_rd0 = io_fpu_iWriteBack_0_bits_rd0; // @[WriteBack.scala 129:16]
endmodule
module ReDirect_3(
  output  io_enq_0_ready,
  input   io_enq_0_valid,
  input   io_enq_0_bits_isPredictTaken,
  input   io_enq_0_bits_isFinalTaken,
  input   io_deq_0_ready,
  output  io_deq_0_valid,
  output  io_deq_0_bits_isPredictTaken,
  output  io_deq_0_bits_isFinalTaken,
  input   io_mapper_0
);
  assign io_enq_0_ready = io_mapper_0 & io_deq_0_ready; // @[RePort.scala 161:22 180:{28,40}]
  assign io_deq_0_valid = io_mapper_0 & io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign io_deq_0_bits_isPredictTaken = io_mapper_0 & io_enq_0_bits_isPredictTaken; // @[RePort.scala 160:21 180:{28,40}]
  assign io_deq_0_bits_isFinalTaken = io_mapper_0 & io_enq_0_bits_isFinalTaken; // @[RePort.scala 160:21 180:{28,40}]
endmodule
module ReDirect_4(
  output        io_enq_0_ready,
  input         io_enq_0_valid,
  input  [38:0] io_enq_0_bits_btbResp_target,
  input  [38:0] io_enq_0_bits_rasResp_target,
  input         io_enq_0_bits_isRas,
  input  [63:0] io_enq_0_bits_finalTarget,
  input         io_deq_0_ready,
  output        io_deq_0_valid,
  output [38:0] io_deq_0_bits_btbResp_target,
  output [38:0] io_deq_0_bits_rasResp_target,
  output        io_deq_0_bits_isRas,
  output [63:0] io_deq_0_bits_finalTarget,
  input         io_mapper_0
);
  assign io_enq_0_ready = io_mapper_0 & io_deq_0_ready; // @[RePort.scala 161:22 180:{28,40}]
  assign io_deq_0_valid = io_mapper_0 & io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign io_deq_0_bits_btbResp_target = io_mapper_0 ? io_enq_0_bits_btbResp_target : 39'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign io_deq_0_bits_rasResp_target = io_mapper_0 ? io_enq_0_bits_rasResp_target : 39'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign io_deq_0_bits_isRas = io_mapper_0 & io_enq_0_bits_isRas; // @[RePort.scala 160:21 180:{28,40}]
  assign io_deq_0_bits_finalTarget = io_mapper_0 ? io_enq_0_bits_finalTarget : 64'h0; // @[RePort.scala 160:21 180:{28,40}]
endmodule
module ReDirect_5(
  input         io_enq_0_valid,
  input  [11:0] io_enq_0_bits_addr,
  input  [63:0] io_enq_0_bits_dat_i,
  input         io_enq_0_bits_op_rw,
  input         io_enq_0_bits_op_rs,
  input         io_enq_0_bits_op_rc,
  input         io_deq_0_ready,
  output        io_deq_0_valid,
  output [11:0] io_deq_0_bits_addr,
  output [63:0] io_deq_0_bits_dat_i,
  output        io_deq_0_bits_op_rw,
  output        io_deq_0_bits_op_rs,
  output        io_deq_0_bits_op_rc,
  input         io_mapper_0
);
  assign io_deq_0_valid = io_mapper_0 & io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign io_deq_0_bits_addr = io_mapper_0 ? io_enq_0_bits_addr : 12'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign io_deq_0_bits_dat_i = io_mapper_0 ? io_enq_0_bits_dat_i : 64'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign io_deq_0_bits_op_rw = io_mapper_0 & io_enq_0_bits_op_rw; // @[RePort.scala 160:21 180:{28,40}]
  assign io_deq_0_bits_op_rs = io_mapper_0 & io_enq_0_bits_op_rs; // @[RePort.scala 160:21 180:{28,40}]
  assign io_deq_0_bits_op_rc = io_mapper_0 & io_enq_0_bits_op_rc; // @[RePort.scala 160:21 180:{28,40}]
endmodule
module Commit(
  input         clock,
  input         reset,
  input         io_cm_op_0_is_writeback,
  input         io_rod_0_valid,
  input         io_rod_0_bits_is_branch,
  input         io_rod_0_bits_is_jalr,
  input         io_rod_0_bits_is_lu,
  input         io_rod_0_bits_is_su,
  input         io_rod_0_bits_is_amo,
  input         io_rod_0_bits_is_fence_i,
  input         io_rod_0_bits_is_sfence_vma,
  input         io_rod_0_bits_is_wfi,
  input         io_rod_0_bits_is_csr,
  input         io_rod_0_bits_is_fpu,
  input         io_rod_0_bits_is_fcsr,
  input         io_rod_0_bits_privil_ecall,
  input         io_rod_0_bits_privil_ebreak,
  input         io_rod_0_bits_privil_mret,
  input         io_rod_0_bits_privil_sret,
  input         io_rod_0_bits_privil_dret,
  input         io_rod_0_bits_privil_is_access_fault,
  input         io_rod_0_bits_privil_is_paging_fault,
  input         io_rod_0_bits_is_illeage,
  input         io_lsu_cmm_is_access_fault,
  input         io_lsu_cmm_is_paging_fault,
  input         io_lsu_cmm_is_misAlign,
  input         io_csr_addr_valid,
  input  [11:0] io_csr_addr_bits,
  input         io_csr_cmm_op_valid,
  input  [11:0] io_csr_cmm_op_bits_addr,
  input  [63:0] io_csr_cmm_op_bits_dat_i,
  input         io_csr_cmm_op_bits_op_rw,
  input         io_csr_cmm_op_bits_op_rs,
  input         io_csr_cmm_op_bits_op_rc,
  output        io_bctq_ready,
  input         io_bctq_valid,
  input         io_bctq_bits_isPredictTaken,
  input         io_bctq_bits_isFinalTaken,
  output        io_jctq_ready,
  input         io_jctq_valid,
  input  [38:0] io_jctq_bits_btbResp_target,
  input  [38:0] io_jctq_bits_rasResp_target,
  input         io_jctq_bits_isRas,
  input  [63:0] io_jctq_bits_finalTarget,
  input         io_fcsr_cmm_op_0_valid,
  input  [11:0] io_fcsr_cmm_op_0_bits_addr,
  input  [63:0] io_fcsr_cmm_op_0_bits_dat_i,
  input         io_fcsr_cmm_op_0_bits_op_rw,
  input         io_fcsr_cmm_op_0_bits_op_rs,
  input         io_fcsr_cmm_op_0_bits_op_rc,
  input         io_dm_hartResetReq,
  input         io_dm_hartHaltReq,
  input         io_aclint_msi,
  input         io_aclint_mti,
  input         io_aclint_ssi,
  input         io_aclint_sti,
  input         io_plic_mei,
  input         io_plic_sei
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [63:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
`endif // RANDOMIZE_REG_INIT
  wire  bctq_mdl_io_enq_0_ready; // @[RePort.scala 188:21]
  wire  bctq_mdl_io_enq_0_valid; // @[RePort.scala 188:21]
  wire  bctq_mdl_io_enq_0_bits_isPredictTaken; // @[RePort.scala 188:21]
  wire  bctq_mdl_io_enq_0_bits_isFinalTaken; // @[RePort.scala 188:21]
  wire  bctq_mdl_io_deq_0_ready; // @[RePort.scala 188:21]
  wire  bctq_mdl_io_deq_0_valid; // @[RePort.scala 188:21]
  wire  bctq_mdl_io_deq_0_bits_isPredictTaken; // @[RePort.scala 188:21]
  wire  bctq_mdl_io_deq_0_bits_isFinalTaken; // @[RePort.scala 188:21]
  wire  bctq_mdl_io_mapper_0; // @[RePort.scala 188:21]
  wire  jctq_mdl_io_enq_0_ready; // @[RePort.scala 188:21]
  wire  jctq_mdl_io_enq_0_valid; // @[RePort.scala 188:21]
  wire [38:0] jctq_mdl_io_enq_0_bits_btbResp_target; // @[RePort.scala 188:21]
  wire [38:0] jctq_mdl_io_enq_0_bits_rasResp_target; // @[RePort.scala 188:21]
  wire  jctq_mdl_io_enq_0_bits_isRas; // @[RePort.scala 188:21]
  wire [63:0] jctq_mdl_io_enq_0_bits_finalTarget; // @[RePort.scala 188:21]
  wire  jctq_mdl_io_deq_0_ready; // @[RePort.scala 188:21]
  wire  jctq_mdl_io_deq_0_valid; // @[RePort.scala 188:21]
  wire [38:0] jctq_mdl_io_deq_0_bits_btbResp_target; // @[RePort.scala 188:21]
  wire [38:0] jctq_mdl_io_deq_0_bits_rasResp_target; // @[RePort.scala 188:21]
  wire  jctq_mdl_io_deq_0_bits_isRas; // @[RePort.scala 188:21]
  wire [63:0] jctq_mdl_io_deq_0_bits_finalTarget; // @[RePort.scala 188:21]
  wire  jctq_mdl_io_mapper_0; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_enq_0_valid; // @[RePort.scala 188:21]
  wire [11:0] csrExe_mdl_io_enq_0_bits_addr; // @[RePort.scala 188:21]
  wire [63:0] csrExe_mdl_io_enq_0_bits_dat_i; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_enq_0_bits_op_rw; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_enq_0_bits_op_rs; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_enq_0_bits_op_rc; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_deq_0_ready; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_deq_0_valid; // @[RePort.scala 188:21]
  wire [11:0] csrExe_mdl_io_deq_0_bits_addr; // @[RePort.scala 188:21]
  wire [63:0] csrExe_mdl_io_deq_0_bits_dat_i; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_deq_0_bits_op_rw; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_deq_0_bits_op_rs; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_deq_0_bits_op_rc; // @[RePort.scala 188:21]
  wire  csrExe_mdl_io_mapper_0; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_enq_0_valid; // @[RePort.scala 188:21]
  wire [11:0] fcsrExe_mdl_io_enq_0_bits_addr; // @[RePort.scala 188:21]
  wire [63:0] fcsrExe_mdl_io_enq_0_bits_dat_i; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_enq_0_bits_op_rw; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_enq_0_bits_op_rs; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_enq_0_bits_op_rc; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_deq_0_ready; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_deq_0_valid; // @[RePort.scala 188:21]
  wire [11:0] fcsrExe_mdl_io_deq_0_bits_addr; // @[RePort.scala 188:21]
  wire [63:0] fcsrExe_mdl_io_deq_0_bits_dat_i; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_deq_0_bits_op_rw; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_deq_0_bits_op_rs; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_deq_0_bits_op_rc; // @[RePort.scala 188:21]
  wire  fcsrExe_mdl_io_mapper_0; // @[RePort.scala 188:21]
  reg [1:0] csrfiles_priv_lvl; // @[Commit.scala 322:21]
  reg  csrfiles_DMode; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_sd; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_tsr; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_tw; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_tvm; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_mxr; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_sum; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_mprv; // @[Commit.scala 322:21]
  reg [1:0] csrfiles_mstatus_fs; // @[Commit.scala 322:21]
  reg [1:0] csrfiles_mstatus_mpp; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_spp; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_mpie; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_spie; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_mie; // @[Commit.scala 322:21]
  reg  csrfiles_mstatus_sie; // @[Commit.scala 322:21]
  reg [63:0] csrfiles_medeleg; // @[Commit.scala 322:21]
  reg [63:0] csrfiles_mideleg; // @[Commit.scala 322:21]
  reg  csrfiles_mie_mei; // @[Commit.scala 322:21]
  reg  csrfiles_mie_sei; // @[Commit.scala 322:21]
  reg  csrfiles_mie_mti; // @[Commit.scala 322:21]
  reg  csrfiles_mie_sti; // @[Commit.scala 322:21]
  reg  csrfiles_mie_msi; // @[Commit.scala 322:21]
  reg  csrfiles_mie_ssi; // @[Commit.scala 322:21]
  reg [31:0] csrfiles_mcounteren_hpm; // @[Commit.scala 322:21]
  reg  csrfiles_mip_mei; // @[Commit.scala 322:21]
  reg  csrfiles_mip_sei; // @[Commit.scala 322:21]
  reg  csrfiles_mip_mti; // @[Commit.scala 322:21]
  reg  csrfiles_mip_sti; // @[Commit.scala 322:21]
  reg  csrfiles_mip_msi; // @[Commit.scala 322:21]
  reg  csrfiles_mip_ssi; // @[Commit.scala 322:21]
  reg  csrfiles_dcsr_ebreakm; // @[Commit.scala 322:21]
  reg  csrfiles_dcsr_ebreaks; // @[Commit.scala 322:21]
  reg  csrfiles_dcsr_ebreaku; // @[Commit.scala 322:21]
  reg [2:0] csrfiles_dcsr_cause; // @[Commit.scala 322:21]
  reg  csrfiles_dcsr_step; // @[Commit.scala 322:21]
  reg [1:0] csrfiles_dcsr_prv; // @[Commit.scala 322:21]
  wire  _is_xRet_is_mRet_T = csrfiles_priv_lvl == 2'h3; // @[Commit.scala 165:55]
  wire  is_xRet_is_mRet = io_rod_0_bits_privil_mret & csrfiles_priv_lvl == 2'h3; // @[Commit.scala 165:35]
  wire  _is_xRet_is_sRet_T_1 = csrfiles_priv_lvl == 2'h1; // @[Commit.scala 170:91]
  wire  is_xRet_is_sRet = io_rod_0_bits_privil_sret & (_is_xRet_is_mRet_T | csrfiles_priv_lvl == 2'h1 & ~
    csrfiles_mstatus_tsr); // @[Commit.scala 170:35]
  wire  is_xRet_is_dRet = io_rod_0_bits_privil_dret & csrfiles_DMode; // @[Commit.scala 175:35]
  wire  is_xRet = is_xRet_is_mRet | is_xRet_is_sRet | is_xRet_is_dRet; // @[Commit.scala 217:37]
  wire  is_trap_is_interrupt_is_m_interrupt_is_msi = csrfiles_mip_msi & csrfiles_mie_msi & csrfiles_mstatus_mie; // @[CsrFiles.scala 284:36]
  wire  is_trap_is_interrupt_is_m_interrupt_is_mti = csrfiles_mip_mti & csrfiles_mie_mti & csrfiles_mstatus_mie; // @[CsrFiles.scala 292:36]
  wire  is_trap_is_interrupt_is_m_interrupt_is_mei = csrfiles_mip_mei & csrfiles_mie_mei & csrfiles_mstatus_mie; // @[CsrFiles.scala 300:36]
  wire  is_trap_is_interrupt_is_m_interrupt = is_trap_is_interrupt_is_m_interrupt_is_msi |
    is_trap_is_interrupt_is_m_interrupt_is_mti | is_trap_is_interrupt_is_m_interrupt_is_mei; // @[CsrFiles.scala 304:42]
  wire  is_trap_is_interrupt_is_s_interrupt_is_ssi = csrfiles_mip_ssi & csrfiles_mie_ssi & csrfiles_mstatus_sie & ~(
    _is_xRet_is_mRet_T & csrfiles_mideleg[1]); // @[CsrFiles.scala 280:50]
  wire  is_trap_is_interrupt_is_s_interrupt_is_sti = csrfiles_mip_sti & csrfiles_mie_sti & csrfiles_mstatus_sie & ~(
    _is_xRet_is_mRet_T & csrfiles_mideleg[5]); // @[CsrFiles.scala 288:50]
  wire  is_trap_is_interrupt_is_s_interrupt_is_sei = csrfiles_mip_sei & csrfiles_mie_sei & csrfiles_mstatus_sie & ~(
    _is_xRet_is_mRet_T & csrfiles_mideleg[9]); // @[CsrFiles.scala 296:50]
  wire  is_trap_is_interrupt_is_s_interrupt = is_trap_is_interrupt_is_s_interrupt_is_ssi |
    is_trap_is_interrupt_is_s_interrupt_is_sti | is_trap_is_interrupt_is_s_interrupt_is_sei; // @[CsrFiles.scala 308:42]
  wire  _is_trap_is_interrupt_T_2 = ~csrfiles_DMode; // @[Commit.scala 207:80]
  reg  is_single_step; // @[Commit.scala 404:31]
  wire  _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_T_2 = is_single_step | io_dm_hartHaltReq; // @[Commit.scala 260:24]
  wire  _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3 =
    csrfiles_priv_lvl == 2'h0; // @[Commit.scala 232:29]
  wire  _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_8 =
    _is_xRet_is_mRet_T & csrfiles_dcsr_ebreakm | _is_xRet_is_sRet_T_1 & csrfiles_dcsr_ebreaks |
    _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3 &
    csrfiles_dcsr_ebreaku; // @[Mux.scala 27:73]
  wire  is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn =
    _is_trap_is_interrupt_T_2 &
    _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_8; // @[Commit.scala 228:49]
  wire  is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm = io_rod_0_bits_privil_ebreak &
    is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn; // @[Commit.scala 253:42]
  wire  _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_T_3 =
    _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_T_2 |
    is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm; // @[Commit.scala 261:25]
  wire  is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt = _is_trap_is_interrupt_T_2 &
    _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_T_3; // @[Commit.scala 258:46]
  reg  emu_reset; // @[Commit.scala 363:26]
  wire  is_trap_is_interrupt_is_nomask_interrupt = is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt |
    emu_reset; // @[Commit.scala 268:50]
  wire  is_trap_is_interrupt = ((is_trap_is_interrupt_is_m_interrupt | is_trap_is_interrupt_is_s_interrupt) & ~
    csrfiles_DMode | is_trap_is_interrupt_is_nomask_interrupt) & ~csrfiles_DMode; // @[Commit.scala 207:123]
  wire  is_trap_is_exception_is_ebreak_exc = io_rod_0_bits_privil_ebreak & ~
    is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn; // @[Commit.scala 120:43]
  wire  _is_trap_is_exception_T = io_rod_0_bits_privil_ecall | is_trap_is_exception_is_ebreak_exc; // @[Commit.scala 192:32]
  wire  _is_trap_is_exception_T_1 = _is_trap_is_exception_T | io_rod_0_bits_privil_is_access_fault; // @[Commit.scala 193:32]
  wire  _is_trap_is_exception_T_2 = _is_trap_is_exception_T_1 | io_rod_0_bits_privil_is_paging_fault; // @[Commit.scala 194:32]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_0 = io_csr_addr_bits == 12'h3a0; // @[CsrFiles.scala 314:58]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_1 = io_csr_addr_bits == 12'h3a2; // @[CsrFiles.scala 314:58]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_2 = io_csr_addr_bits == 12'h3a4; // @[CsrFiles.scala 314:58]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_3 = io_csr_addr_bits == 12'h3a6; // @[CsrFiles.scala 314:58]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_4 = io_csr_addr_bits == 12'h3a8; // @[CsrFiles.scala 314:58]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_5 = io_csr_addr_bits == 12'h3aa; // @[CsrFiles.scala 314:58]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_6 = io_csr_addr_bits == 12'h3ac; // @[CsrFiles.scala 314:58]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_7 = io_csr_addr_bits == 12'h3ae; // @[CsrFiles.scala 314:58]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_0_1 = io_csr_addr_bits == 12'h3b0; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_1_1 = io_csr_addr_bits == 12'h3b1; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_2_1 = io_csr_addr_bits == 12'h3b2; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_3_1 = io_csr_addr_bits == 12'h3b3; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_4_1 = io_csr_addr_bits == 12'h3b4; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_5_1 = io_csr_addr_bits == 12'h3b5; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_6_1 = io_csr_addr_bits == 12'h3b6; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_7_1 = io_csr_addr_bits == 12'h3b7; // @[CsrFiles.scala 320:60]
  wire  _cmm_state_0_is_csrr_illegal_res_T_15 = cmm_state_0_is_csrr_illegal_addr_chk_7_1 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _cmm_state_0_is_csrr_illegal_res_T_240 = cmm_state_0_is_csrr_illegal_addr_chk_0 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_1 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_2 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_3 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_4 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_5 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_6 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_7 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_0_1 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_1_1 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_2_1 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_3_1 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_4_1 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_5_1 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_6_1 &
    _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_res_T_15; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_8 = io_csr_addr_bits == 12'h3b8; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_9 = io_csr_addr_bits == 12'h3b9; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_10 = io_csr_addr_bits == 12'h3ba; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_11 = io_csr_addr_bits == 12'h3bb; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_12 = io_csr_addr_bits == 12'h3bc; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_13 = io_csr_addr_bits == 12'h3bd; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_14 = io_csr_addr_bits == 12'h3be; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_15 = io_csr_addr_bits == 12'h3bf; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_16 = io_csr_addr_bits == 12'h3c0; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_17 = io_csr_addr_bits == 12'h3c1; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_18 = io_csr_addr_bits == 12'h3c2; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_19 = io_csr_addr_bits == 12'h3c3; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_20 = io_csr_addr_bits == 12'h3c4; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_21 = io_csr_addr_bits == 12'h3c5; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_22 = io_csr_addr_bits == 12'h3c6; // @[CsrFiles.scala 320:60]
  wire  _cmm_state_0_is_csrr_illegal_res_T_255 = _cmm_state_0_is_csrr_illegal_res_T_240 |
    cmm_state_0_is_csrr_illegal_addr_chk_8 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_9 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_10 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_11 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_12 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_13 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_14 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_15 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_16 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_17 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_18 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_19 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_20 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_21 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_22 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_23 = io_csr_addr_bits == 12'h3c7; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_24 = io_csr_addr_bits == 12'h3c8; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_25 = io_csr_addr_bits == 12'h3c9; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_26 = io_csr_addr_bits == 12'h3ca; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_27 = io_csr_addr_bits == 12'h3cb; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_28 = io_csr_addr_bits == 12'h3cc; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_29 = io_csr_addr_bits == 12'h3cd; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_30 = io_csr_addr_bits == 12'h3ce; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_31 = io_csr_addr_bits == 12'h3cf; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_32 = io_csr_addr_bits == 12'h3d0; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_33 = io_csr_addr_bits == 12'h3d1; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_34 = io_csr_addr_bits == 12'h3d2; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_35 = io_csr_addr_bits == 12'h3d3; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_36 = io_csr_addr_bits == 12'h3d4; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_37 = io_csr_addr_bits == 12'h3d5; // @[CsrFiles.scala 320:60]
  wire  _cmm_state_0_is_csrr_illegal_res_T_270 = _cmm_state_0_is_csrr_illegal_res_T_255 |
    cmm_state_0_is_csrr_illegal_addr_chk_23 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_24 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_25 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_26 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_27 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_28 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_29 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_30 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_31 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_32 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_33 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_34 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_35 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_36 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_37 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_38 = io_csr_addr_bits == 12'h3d6; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_39 = io_csr_addr_bits == 12'h3d7; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_40 = io_csr_addr_bits == 12'h3d8; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_41 = io_csr_addr_bits == 12'h3d9; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_42 = io_csr_addr_bits == 12'h3da; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_43 = io_csr_addr_bits == 12'h3db; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_44 = io_csr_addr_bits == 12'h3dc; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_45 = io_csr_addr_bits == 12'h3dd; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_46 = io_csr_addr_bits == 12'h3de; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_47 = io_csr_addr_bits == 12'h3df; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_48 = io_csr_addr_bits == 12'h3e0; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_49 = io_csr_addr_bits == 12'h3e1; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_50 = io_csr_addr_bits == 12'h3e2; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_51 = io_csr_addr_bits == 12'h3e3; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_52 = io_csr_addr_bits == 12'h3e4; // @[CsrFiles.scala 320:60]
  wire  _cmm_state_0_is_csrr_illegal_res_T_285 = _cmm_state_0_is_csrr_illegal_res_T_270 |
    cmm_state_0_is_csrr_illegal_addr_chk_38 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_39 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_40 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_41 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_42 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_43 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_44 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_45 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_46 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_47 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_48 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_49 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_50 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_51 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_52 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_53 = io_csr_addr_bits == 12'h3e5; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_54 = io_csr_addr_bits == 12'h3e6; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_55 = io_csr_addr_bits == 12'h3e7; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_56 = io_csr_addr_bits == 12'h3e8; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_57 = io_csr_addr_bits == 12'h3e9; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_58 = io_csr_addr_bits == 12'h3ea; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_59 = io_csr_addr_bits == 12'h3eb; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_60 = io_csr_addr_bits == 12'h3ec; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_61 = io_csr_addr_bits == 12'h3ed; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_62 = io_csr_addr_bits == 12'h3ee; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_63 = io_csr_addr_bits == 12'h3ef; // @[CsrFiles.scala 320:60]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_0_2 = io_csr_addr_bits == 12'hc03; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_1_2 = io_csr_addr_bits == 12'hc04; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_2_2 = io_csr_addr_bits == 12'hc05; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_3_2 = io_csr_addr_bits == 12'hc06; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_4_2 = io_csr_addr_bits == 12'hc07; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_5_2 = io_csr_addr_bits == 12'hc08; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_6_2 = io_csr_addr_bits == 12'hc09; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_7_2 = io_csr_addr_bits == 12'hc0a; // @[CsrFiles.scala 326:59]
  wire  _cmm_state_0_is_csrr_illegal_res_T_304 = _cmm_state_0_is_csrr_illegal_res_T_285 |
    cmm_state_0_is_csrr_illegal_addr_chk_53 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_54 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_55 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_56 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_57 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_58 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_59 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_60 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_61 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_62 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_63 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_0_2 | cmm_state_0_is_csrr_illegal_addr_chk_1_2 |
    cmm_state_0_is_csrr_illegal_addr_chk_2_2 | cmm_state_0_is_csrr_illegal_addr_chk_3_2 |
    cmm_state_0_is_csrr_illegal_addr_chk_4_2 | cmm_state_0_is_csrr_illegal_addr_chk_5_2 |
    cmm_state_0_is_csrr_illegal_addr_chk_6_2 | cmm_state_0_is_csrr_illegal_addr_chk_7_2; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_8_1 = io_csr_addr_bits == 12'hc0b; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_9_1 = io_csr_addr_bits == 12'hc0c; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_10_1 = io_csr_addr_bits == 12'hc0d; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_11_1 = io_csr_addr_bits == 12'hc0e; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_12_1 = io_csr_addr_bits == 12'hc0f; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_13_1 = io_csr_addr_bits == 12'hc10; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_14_1 = io_csr_addr_bits == 12'hc11; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_15_1 = io_csr_addr_bits == 12'hc12; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_16_1 = io_csr_addr_bits == 12'hc13; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_17_1 = io_csr_addr_bits == 12'hc14; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_18_1 = io_csr_addr_bits == 12'hc15; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_19_1 = io_csr_addr_bits == 12'hc16; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_20_1 = io_csr_addr_bits == 12'hc17; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_21_1 = io_csr_addr_bits == 12'hc18; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_22_1 = io_csr_addr_bits == 12'hc19; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_23_1 = io_csr_addr_bits == 12'hc1a; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_24_1 = io_csr_addr_bits == 12'hc1b; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_25_1 = io_csr_addr_bits == 12'hc1c; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_26_1 = io_csr_addr_bits == 12'hc1d; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_27_1 = io_csr_addr_bits == 12'hc1e; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_28_1 = io_csr_addr_bits == 12'hc1f; // @[CsrFiles.scala 326:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_0_3 = io_csr_addr_bits == 12'hb03; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_0_2 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[3]
    ; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_1_3 = io_csr_addr_bits == 12'hb04; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_1_2 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[4]
    ; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_2_3 = io_csr_addr_bits == 12'hb05; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_2_2 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[5]
    ; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_3_3 = io_csr_addr_bits == 12'hb06; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_3_2 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[6]
    ; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_4_3 = io_csr_addr_bits == 12'hb07; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_4_2 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[7]
    ; // @[CsrFiles.scala 333:75]
  wire  _cmm_state_0_is_csrr_illegal_res_T_105 = cmm_state_0_is_csrr_illegal_addr_chk_4_3 &
    cmm_state_0_is_csrr_illegal_reg_sel_4_2; // @[Mux.scala 27:73]
  wire  _cmm_state_0_is_csrr_illegal_res_T_330 = _cmm_state_0_is_csrr_illegal_res_T_304 |
    cmm_state_0_is_csrr_illegal_addr_chk_8_1 | cmm_state_0_is_csrr_illegal_addr_chk_9_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_10_1 | cmm_state_0_is_csrr_illegal_addr_chk_11_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_12_1 | cmm_state_0_is_csrr_illegal_addr_chk_13_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_14_1 | cmm_state_0_is_csrr_illegal_addr_chk_15_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_16_1 | cmm_state_0_is_csrr_illegal_addr_chk_17_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_18_1 | cmm_state_0_is_csrr_illegal_addr_chk_19_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_20_1 | cmm_state_0_is_csrr_illegal_addr_chk_21_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_22_1 | cmm_state_0_is_csrr_illegal_addr_chk_23_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_24_1 | cmm_state_0_is_csrr_illegal_addr_chk_25_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_26_1 | cmm_state_0_is_csrr_illegal_addr_chk_27_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_28_1 | cmm_state_0_is_csrr_illegal_addr_chk_0_3 &
    cmm_state_0_is_csrr_illegal_reg_sel_0_2 | cmm_state_0_is_csrr_illegal_addr_chk_1_3 &
    cmm_state_0_is_csrr_illegal_reg_sel_1_2 | cmm_state_0_is_csrr_illegal_addr_chk_2_3 &
    cmm_state_0_is_csrr_illegal_reg_sel_2_2 | cmm_state_0_is_csrr_illegal_addr_chk_3_3 &
    cmm_state_0_is_csrr_illegal_reg_sel_3_2 | _cmm_state_0_is_csrr_illegal_res_T_105; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_5_3 = io_csr_addr_bits == 12'hb08; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_5_2 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[8]
    ; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_6_3 = io_csr_addr_bits == 12'hb09; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_6_2 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[9]
    ; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_7_3 = io_csr_addr_bits == 12'hb0a; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_7_2 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[10
    ]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_8_2 = io_csr_addr_bits == 12'hb0b; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_8_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[11
    ]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_9_2 = io_csr_addr_bits == 12'hb0c; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_9_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[12
    ]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_10_2 = io_csr_addr_bits == 12'hb0d; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_10_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    13]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_11_2 = io_csr_addr_bits == 12'hb0e; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_11_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    14]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_12_2 = io_csr_addr_bits == 12'hb0f; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_12_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    15]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_13_2 = io_csr_addr_bits == 12'hb10; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_13_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    16]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_14_2 = io_csr_addr_bits == 12'hb11; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_14_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    17]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_15_2 = io_csr_addr_bits == 12'hb12; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_15_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    18]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_16_2 = io_csr_addr_bits == 12'hb13; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_16_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    19]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_17_2 = io_csr_addr_bits == 12'hb14; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_17_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    20]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_18_2 = io_csr_addr_bits == 12'hb15; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_18_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    21]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_19_2 = io_csr_addr_bits == 12'hb16; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_19_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    22]; // @[CsrFiles.scala 333:75]
  wire  _cmm_state_0_is_csrr_illegal_res_T_345 = _cmm_state_0_is_csrr_illegal_res_T_330 |
    cmm_state_0_is_csrr_illegal_addr_chk_5_3 & cmm_state_0_is_csrr_illegal_reg_sel_5_2 |
    cmm_state_0_is_csrr_illegal_addr_chk_6_3 & cmm_state_0_is_csrr_illegal_reg_sel_6_2 |
    cmm_state_0_is_csrr_illegal_addr_chk_7_3 & cmm_state_0_is_csrr_illegal_reg_sel_7_2 |
    cmm_state_0_is_csrr_illegal_addr_chk_8_2 & cmm_state_0_is_csrr_illegal_reg_sel_8_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_9_2 & cmm_state_0_is_csrr_illegal_reg_sel_9_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_10_2 & cmm_state_0_is_csrr_illegal_reg_sel_10_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_11_2 & cmm_state_0_is_csrr_illegal_reg_sel_11_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_12_2 & cmm_state_0_is_csrr_illegal_reg_sel_12_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_13_2 & cmm_state_0_is_csrr_illegal_reg_sel_13_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_14_2 & cmm_state_0_is_csrr_illegal_reg_sel_14_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_15_2 & cmm_state_0_is_csrr_illegal_reg_sel_15_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_16_2 & cmm_state_0_is_csrr_illegal_reg_sel_16_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_17_2 & cmm_state_0_is_csrr_illegal_reg_sel_17_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_18_2 & cmm_state_0_is_csrr_illegal_reg_sel_18_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_19_2 & cmm_state_0_is_csrr_illegal_reg_sel_19_1; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_20_2 = io_csr_addr_bits == 12'hb17; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_20_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    23]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_21_2 = io_csr_addr_bits == 12'hb18; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_21_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    24]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_22_2 = io_csr_addr_bits == 12'hb19; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_22_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    25]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_23_2 = io_csr_addr_bits == 12'hb1a; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_23_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    26]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_24_2 = io_csr_addr_bits == 12'hb1b; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_24_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    27]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_25_2 = io_csr_addr_bits == 12'hb1c; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_25_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    28]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_26_2 = io_csr_addr_bits == 12'hb1d; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_26_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    29]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_27_2 = io_csr_addr_bits == 12'hb1e; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_27_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    30]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_28_2 = io_csr_addr_bits == 12'hb1f; // @[CsrFiles.scala 332:59]
  wire  cmm_state_0_is_csrr_illegal_reg_sel_28_1 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[
    31]; // @[CsrFiles.scala 333:75]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_0_4 = io_csr_addr_bits == 12'h323; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_1_4 = io_csr_addr_bits == 12'h324; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_2_4 = io_csr_addr_bits == 12'h325; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_3_4 = io_csr_addr_bits == 12'h326; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_4_4 = io_csr_addr_bits == 12'h327; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_5_4 = io_csr_addr_bits == 12'h328; // @[CsrFiles.scala 338:59]
  wire  _cmm_state_0_is_csrr_illegal_res_T_360 = _cmm_state_0_is_csrr_illegal_res_T_345 |
    cmm_state_0_is_csrr_illegal_addr_chk_20_2 & cmm_state_0_is_csrr_illegal_reg_sel_20_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_21_2 & cmm_state_0_is_csrr_illegal_reg_sel_21_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_22_2 & cmm_state_0_is_csrr_illegal_reg_sel_22_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_23_2 & cmm_state_0_is_csrr_illegal_reg_sel_23_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_24_2 & cmm_state_0_is_csrr_illegal_reg_sel_24_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_25_2 & cmm_state_0_is_csrr_illegal_reg_sel_25_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_26_2 & cmm_state_0_is_csrr_illegal_reg_sel_26_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_27_2 & cmm_state_0_is_csrr_illegal_reg_sel_27_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_28_2 & cmm_state_0_is_csrr_illegal_reg_sel_28_1 |
    cmm_state_0_is_csrr_illegal_addr_chk_0_4 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_1_4 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_2_4 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_3_4 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_4_4 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_5_4 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_6_4 = io_csr_addr_bits == 12'h329; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_7_4 = io_csr_addr_bits == 12'h32a; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_8_3 = io_csr_addr_bits == 12'h32b; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_9_3 = io_csr_addr_bits == 12'h32c; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_10_3 = io_csr_addr_bits == 12'h32d; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_11_3 = io_csr_addr_bits == 12'h32e; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_12_3 = io_csr_addr_bits == 12'h32f; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_13_3 = io_csr_addr_bits == 12'h330; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_14_3 = io_csr_addr_bits == 12'h331; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_15_3 = io_csr_addr_bits == 12'h332; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_16_3 = io_csr_addr_bits == 12'h333; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_17_3 = io_csr_addr_bits == 12'h334; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_18_3 = io_csr_addr_bits == 12'h335; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_19_3 = io_csr_addr_bits == 12'h336; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_20_3 = io_csr_addr_bits == 12'h337; // @[CsrFiles.scala 338:59]
  wire  _cmm_state_0_is_csrr_illegal_res_T_375 = _cmm_state_0_is_csrr_illegal_res_T_360 |
    cmm_state_0_is_csrr_illegal_addr_chk_6_4 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_7_4 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_8_3 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_9_3 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_10_3 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_11_3 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_12_3 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_13_3 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_14_3 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_15_3 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_16_3 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_17_3 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_18_3 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_19_3 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_20_3 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_21_3 = io_csr_addr_bits == 12'h338; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_22_3 = io_csr_addr_bits == 12'h339; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_23_3 = io_csr_addr_bits == 12'h33a; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_24_3 = io_csr_addr_bits == 12'h33b; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_25_3 = io_csr_addr_bits == 12'h33c; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_26_3 = io_csr_addr_bits == 12'h33d; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_27_3 = io_csr_addr_bits == 12'h33e; // @[CsrFiles.scala 338:59]
  wire  cmm_state_0_is_csrr_illegal_addr_chk_28_3 = io_csr_addr_bits == 12'h33f; // @[CsrFiles.scala 338:59]
  wire  _cmm_state_0_is_csrr_illegal_T = io_csr_addr_bits == 12'h1; // @[CsrFiles.scala 352:18]
  wire  _cmm_state_0_is_csrr_illegal_T_2 = io_csr_addr_bits == 12'h2; // @[CsrFiles.scala 353:18]
  wire  _cmm_state_0_is_csrr_illegal_T_4 = io_csr_addr_bits == 12'h3; // @[CsrFiles.scala 354:18]
  wire  _cmm_state_0_is_csrr_illegal_T_6 = io_csr_addr_bits == 12'hc00; // @[CsrFiles.scala 355:18]
  wire  _cmm_state_0_is_csrr_illegal_T_8 = io_csr_addr_bits == 12'hc01; // @[CsrFiles.scala 356:18]
  wire  _cmm_state_0_is_csrr_illegal_T_10 = io_csr_addr_bits == 12'hc02; // @[CsrFiles.scala 357:18]
  wire  _cmm_state_0_is_csrr_illegal_T_12 = io_csr_addr_bits == 12'h100; // @[CsrFiles.scala 358:18]
  wire  _cmm_state_0_is_csrr_illegal_T_14 = io_csr_addr_bits == 12'h104; // @[CsrFiles.scala 361:18]
  wire  _cmm_state_0_is_csrr_illegal_T_15 = csrfiles_priv_lvl >= 2'h1; // @[CsrFiles.scala 361:46]
  wire  _cmm_state_0_is_csrr_illegal_T_16 = io_csr_addr_bits == 12'h105; // @[CsrFiles.scala 362:18]
  wire  _cmm_state_0_is_csrr_illegal_T_18 = io_csr_addr_bits == 12'h106; // @[CsrFiles.scala 363:18]
  wire  _cmm_state_0_is_csrr_illegal_T_20 = io_csr_addr_bits == 12'h140; // @[CsrFiles.scala 364:18]
  wire  _cmm_state_0_is_csrr_illegal_res_T_169 = _cmm_state_0_is_csrr_illegal_T_20 & _cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  _cmm_state_0_is_csrr_illegal_res_T_394 = _cmm_state_0_is_csrr_illegal_res_T_375 |
    cmm_state_0_is_csrr_illegal_addr_chk_21_3 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_22_3 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_23_3 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_24_3 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_25_3 &
    _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_26_3 & _is_xRet_is_mRet_T |
    cmm_state_0_is_csrr_illegal_addr_chk_27_3 & _is_xRet_is_mRet_T | cmm_state_0_is_csrr_illegal_addr_chk_28_3 &
    _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T | _cmm_state_0_is_csrr_illegal_T_2 |
    _cmm_state_0_is_csrr_illegal_T_4 | _cmm_state_0_is_csrr_illegal_T_6 | _cmm_state_0_is_csrr_illegal_T_8 |
    _cmm_state_0_is_csrr_illegal_T_10 | _cmm_state_0_is_csrr_illegal_T_12 | _cmm_state_0_is_csrr_illegal_T_14 &
    _cmm_state_0_is_csrr_illegal_T_15 | _cmm_state_0_is_csrr_illegal_T_16 & _cmm_state_0_is_csrr_illegal_T_15 |
    _cmm_state_0_is_csrr_illegal_T_18 & _cmm_state_0_is_csrr_illegal_T_15 | _cmm_state_0_is_csrr_illegal_res_T_169; // @[Mux.scala 27:73]
  wire  _cmm_state_0_is_csrr_illegal_T_22 = io_csr_addr_bits == 12'h141; // @[CsrFiles.scala 365:18]
  wire  _cmm_state_0_is_csrr_illegal_T_24 = io_csr_addr_bits == 12'h142; // @[CsrFiles.scala 366:18]
  wire  _cmm_state_0_is_csrr_illegal_T_26 = io_csr_addr_bits == 12'h143; // @[CsrFiles.scala 367:18]
  wire  _cmm_state_0_is_csrr_illegal_T_28 = io_csr_addr_bits == 12'h144; // @[CsrFiles.scala 368:18]
  wire  _cmm_state_0_is_csrr_illegal_T_30 = io_csr_addr_bits == 12'h180; // @[CsrFiles.scala 369:18]
  wire  _cmm_state_0_is_csrr_illegal_T_33 = ~csrfiles_mstatus_tvm; // @[CsrFiles.scala 369:98]
  wire  _cmm_state_0_is_csrr_illegal_T_35 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & ~csrfiles_mstatus_tvm; // @[CsrFiles.scala 369:60]
  wire  _cmm_state_0_is_csrr_illegal_T_58 = io_csr_addr_bits == 12'hf11; // @[CsrFiles.scala 392:18]
  wire  _cmm_state_0_is_csrr_illegal_T_60 = io_csr_addr_bits == 12'hf12; // @[CsrFiles.scala 393:18]
  wire  _cmm_state_0_is_csrr_illegal_T_62 = io_csr_addr_bits == 12'hf13; // @[CsrFiles.scala 394:18]
  wire  _cmm_state_0_is_csrr_illegal_T_64 = io_csr_addr_bits == 12'hf14; // @[CsrFiles.scala 395:18]
  wire  _cmm_state_0_is_csrr_illegal_T_66 = io_csr_addr_bits == 12'h300; // @[CsrFiles.scala 396:18]
  wire  _cmm_state_0_is_csrr_illegal_T_68 = io_csr_addr_bits == 12'h301; // @[CsrFiles.scala 397:18]
  wire  _cmm_state_0_is_csrr_illegal_T_70 = io_csr_addr_bits == 12'h302; // @[CsrFiles.scala 398:18]
  wire  _cmm_state_0_is_csrr_illegal_T_72 = io_csr_addr_bits == 12'h303; // @[CsrFiles.scala 399:18]
  wire  _cmm_state_0_is_csrr_illegal_T_74 = io_csr_addr_bits == 12'h304; // @[CsrFiles.scala 400:18]
  wire  _cmm_state_0_is_csrr_illegal_T_76 = io_csr_addr_bits == 12'h305; // @[CsrFiles.scala 401:18]
  wire  _cmm_state_0_is_csrr_illegal_res_T_431 = _cmm_state_0_is_csrr_illegal_res_T_394 |
    _cmm_state_0_is_csrr_illegal_T_22 & _cmm_state_0_is_csrr_illegal_T_15 | _cmm_state_0_is_csrr_illegal_T_24 &
    _cmm_state_0_is_csrr_illegal_T_15 | _cmm_state_0_is_csrr_illegal_T_26 & _cmm_state_0_is_csrr_illegal_T_15 |
    _cmm_state_0_is_csrr_illegal_T_28 & _cmm_state_0_is_csrr_illegal_T_15 | _cmm_state_0_is_csrr_illegal_T_30 &
    _cmm_state_0_is_csrr_illegal_T_35 | _cmm_state_0_is_csrr_illegal_T_58 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_60 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_62 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_64 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_66 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_68 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_70 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_72 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_74 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_76 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _cmm_state_0_is_csrr_illegal_T_78 = io_csr_addr_bits == 12'h306; // @[CsrFiles.scala 402:18]
  wire  _cmm_state_0_is_csrr_illegal_T_80 = io_csr_addr_bits == 12'h340; // @[CsrFiles.scala 403:18]
  wire  _cmm_state_0_is_csrr_illegal_T_82 = io_csr_addr_bits == 12'h341; // @[CsrFiles.scala 404:18]
  wire  _cmm_state_0_is_csrr_illegal_T_84 = io_csr_addr_bits == 12'h342; // @[CsrFiles.scala 405:18]
  wire  _cmm_state_0_is_csrr_illegal_T_86 = io_csr_addr_bits == 12'h343; // @[CsrFiles.scala 406:18]
  wire  _cmm_state_0_is_csrr_illegal_T_88 = io_csr_addr_bits == 12'h344; // @[CsrFiles.scala 407:18]
  wire  _cmm_state_0_is_csrr_illegal_T_90 = io_csr_addr_bits == 12'h34a; // @[CsrFiles.scala 408:18]
  wire  _cmm_state_0_is_csrr_illegal_T_92 = io_csr_addr_bits == 12'h34b; // @[CsrFiles.scala 409:18]
  wire  _cmm_state_0_is_csrr_illegal_T_94 = io_csr_addr_bits == 12'hb00; // @[CsrFiles.scala 411:18]
  wire  _cmm_state_0_is_csrr_illegal_T_99 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[0]; // @[CsrFiles.scala 411:58]
  wire  _cmm_state_0_is_csrr_illegal_T_100 = io_csr_addr_bits == 12'hb02; // @[CsrFiles.scala 412:18]
  wire  _cmm_state_0_is_csrr_illegal_T_105 = _is_xRet_is_mRet_T | _is_xRet_is_sRet_T_1 & csrfiles_mcounteren_hpm[2]; // @[CsrFiles.scala 412:58]
  wire  _cmm_state_0_is_csrr_illegal_T_106 = io_csr_addr_bits == 12'h320; // @[CsrFiles.scala 413:18]
  wire  _cmm_state_0_is_csrr_illegal_T_108 = io_csr_addr_bits == 12'h7a0; // @[CsrFiles.scala 414:18]
  wire  _cmm_state_0_is_csrr_illegal_T_110 = io_csr_addr_bits == 12'h7a1; // @[CsrFiles.scala 415:18]
  wire  _cmm_state_0_is_csrr_illegal_T_112 = io_csr_addr_bits == 12'h7a2; // @[CsrFiles.scala 416:18]
  wire  _cmm_state_0_is_csrr_illegal_T_114 = io_csr_addr_bits == 12'h7a3; // @[CsrFiles.scala 417:18]
  wire  _cmm_state_0_is_csrr_illegal_res_T_446 = _cmm_state_0_is_csrr_illegal_res_T_431 |
    _cmm_state_0_is_csrr_illegal_T_78 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_80 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_82 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_84 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_86 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_88 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_90 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_92 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_94 & _cmm_state_0_is_csrr_illegal_T_99 | _cmm_state_0_is_csrr_illegal_T_100 &
    _cmm_state_0_is_csrr_illegal_T_105 | _cmm_state_0_is_csrr_illegal_T_106 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_108 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_110 & _is_xRet_is_mRet_T |
    _cmm_state_0_is_csrr_illegal_T_112 & _is_xRet_is_mRet_T | _cmm_state_0_is_csrr_illegal_T_114 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _cmm_state_0_is_csrr_illegal_T_116 = io_csr_addr_bits == 12'h7b0; // @[CsrFiles.scala 418:18]
  wire  _cmm_state_0_is_csrr_illegal_T_117 = io_csr_addr_bits == 12'h7b1; // @[CsrFiles.scala 419:18]
  wire  _cmm_state_0_is_csrr_illegal_T_118 = io_csr_addr_bits == 12'h7b2; // @[CsrFiles.scala 420:18]
  wire  _cmm_state_0_is_csrr_illegal_T_119 = io_csr_addr_bits == 12'h7b3; // @[CsrFiles.scala 421:18]
  wire  cmm_state_0_is_csrr_illegal_res = _cmm_state_0_is_csrr_illegal_res_T_446 | _cmm_state_0_is_csrr_illegal_T_116 &
    csrfiles_DMode | _cmm_state_0_is_csrr_illegal_T_117 & csrfiles_DMode | _cmm_state_0_is_csrr_illegal_T_118 &
    csrfiles_DMode | _cmm_state_0_is_csrr_illegal_T_119 & csrfiles_DMode; // @[Mux.scala 27:73]
  wire  _cmm_state_0_is_csrr_illegal_T_120 = ~cmm_state_0_is_csrr_illegal_res; // @[CsrFiles.scala 425:5]
  wire  cmm_state_0_is_csrr_illegal = _cmm_state_0_is_csrr_illegal_T_120 & io_csr_addr_valid; // @[Commit.scala 647:101]
  wire  _is_trap_is_exception_is_csr_illegal_T_1 = ~io_cm_op_0_is_writeback; // @[Commit.scala 148:40]
  wire  cmm_state_0_csrExe_op_rc = csrExe_mdl_io_deq_0_bits_op_rc; // @[Commit.scala 330:23 642:26]
  wire  cmm_state_0_csrExe_op_rs = csrExe_mdl_io_deq_0_bits_op_rs; // @[Commit.scala 330:23 642:26]
  wire  cmm_state_0_csrExe_op_rw = csrExe_mdl_io_deq_0_bits_op_rw; // @[Commit.scala 330:23 642:26]
  wire [11:0] cmm_state_0_csrExe_addr = csrExe_mdl_io_deq_0_bits_addr; // @[Commit.scala 330:23 642:26]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0 = cmm_state_0_csrExe_addr == 12'h3a0; // @[CsrFiles.scala 431:58]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1 = cmm_state_0_csrExe_addr == 12'h3a2; // @[CsrFiles.scala 431:58]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2 = cmm_state_0_csrExe_addr == 12'h3a4; // @[CsrFiles.scala 431:58]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3 = cmm_state_0_csrExe_addr == 12'h3a6; // @[CsrFiles.scala 431:58]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4 = cmm_state_0_csrExe_addr == 12'h3a8; // @[CsrFiles.scala 431:58]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5 = cmm_state_0_csrExe_addr == 12'h3aa; // @[CsrFiles.scala 431:58]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6 = cmm_state_0_csrExe_addr == 12'h3ac; // @[CsrFiles.scala 431:58]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7 = cmm_state_0_csrExe_addr == 12'h3ae; // @[CsrFiles.scala 431:58]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_1 = cmm_state_0_csrExe_addr == 12'h3b0; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_1 = cmm_state_0_csrExe_addr == 12'h3b1; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_1 = cmm_state_0_csrExe_addr == 12'h3b2; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_1 = cmm_state_0_csrExe_addr == 12'h3b3; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_1 = cmm_state_0_csrExe_addr == 12'h3b4; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_1 = cmm_state_0_csrExe_addr == 12'h3b5; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_1 = cmm_state_0_csrExe_addr == 12'h3b6; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_1 = cmm_state_0_csrExe_addr == 12'h3b7; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8 = cmm_state_0_csrExe_addr == 12'h3b8; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9 = cmm_state_0_csrExe_addr == 12'h3b9; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10 = cmm_state_0_csrExe_addr == 12'h3ba; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11 = cmm_state_0_csrExe_addr == 12'h3bb; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12 = cmm_state_0_csrExe_addr == 12'h3bc; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13 = cmm_state_0_csrExe_addr == 12'h3bd; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14 = cmm_state_0_csrExe_addr == 12'h3be; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15 = cmm_state_0_csrExe_addr == 12'h3bf; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16 = cmm_state_0_csrExe_addr == 12'h3c0; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17 = cmm_state_0_csrExe_addr == 12'h3c1; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18 = cmm_state_0_csrExe_addr == 12'h3c2; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19 = cmm_state_0_csrExe_addr == 12'h3c3; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20 = cmm_state_0_csrExe_addr == 12'h3c4; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21 = cmm_state_0_csrExe_addr == 12'h3c5; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22 = cmm_state_0_csrExe_addr == 12'h3c6; // @[CsrFiles.scala 437:60]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_255 =
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22; // @[Mux.scala 27:73]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23 = cmm_state_0_csrExe_addr == 12'h3c7; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24 = cmm_state_0_csrExe_addr == 12'h3c8; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25 = cmm_state_0_csrExe_addr == 12'h3c9; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26 = cmm_state_0_csrExe_addr == 12'h3ca; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27 = cmm_state_0_csrExe_addr == 12'h3cb; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28 = cmm_state_0_csrExe_addr == 12'h3cc; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_29 = cmm_state_0_csrExe_addr == 12'h3cd; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_30 = cmm_state_0_csrExe_addr == 12'h3ce; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_31 = cmm_state_0_csrExe_addr == 12'h3cf; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_32 = cmm_state_0_csrExe_addr == 12'h3d0; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_33 = cmm_state_0_csrExe_addr == 12'h3d1; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_34 = cmm_state_0_csrExe_addr == 12'h3d2; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_35 = cmm_state_0_csrExe_addr == 12'h3d3; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_36 = cmm_state_0_csrExe_addr == 12'h3d4; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_37 = cmm_state_0_csrExe_addr == 12'h3d5; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_38 = cmm_state_0_csrExe_addr == 12'h3d6; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_39 = cmm_state_0_csrExe_addr == 12'h3d7; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_40 = cmm_state_0_csrExe_addr == 12'h3d8; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_41 = cmm_state_0_csrExe_addr == 12'h3d9; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_42 = cmm_state_0_csrExe_addr == 12'h3da; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_43 = cmm_state_0_csrExe_addr == 12'h3db; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_44 = cmm_state_0_csrExe_addr == 12'h3dc; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_45 = cmm_state_0_csrExe_addr == 12'h3dd; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_46 = cmm_state_0_csrExe_addr == 12'h3de; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_47 = cmm_state_0_csrExe_addr == 12'h3df; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_48 = cmm_state_0_csrExe_addr == 12'h3e0; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_49 = cmm_state_0_csrExe_addr == 12'h3e1; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_50 = cmm_state_0_csrExe_addr == 12'h3e2; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_51 = cmm_state_0_csrExe_addr == 12'h3e3; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_52 = cmm_state_0_csrExe_addr == 12'h3e4; // @[CsrFiles.scala 437:60]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_285 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_255 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_29 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_30 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_31 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_32 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_33 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_34 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_35 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_36 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_37 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_38 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_39 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_40 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_41 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_42 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_43 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_44 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_45 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_46 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_47 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_48 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_49 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_50 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_51 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_52; // @[Mux.scala 27:73]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_53 = cmm_state_0_csrExe_addr == 12'h3e5; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_54 = cmm_state_0_csrExe_addr == 12'h3e6; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_55 = cmm_state_0_csrExe_addr == 12'h3e7; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_56 = cmm_state_0_csrExe_addr == 12'h3e8; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_57 = cmm_state_0_csrExe_addr == 12'h3e9; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_58 = cmm_state_0_csrExe_addr == 12'h3ea; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_59 = cmm_state_0_csrExe_addr == 12'h3eb; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_60 = cmm_state_0_csrExe_addr == 12'h3ec; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_61 = cmm_state_0_csrExe_addr == 12'h3ed; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_62 = cmm_state_0_csrExe_addr == 12'h3ee; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_63 = cmm_state_0_csrExe_addr == 12'h3ef; // @[CsrFiles.scala 437:60]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_2 = cmm_state_0_csrExe_addr == 12'hc03; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_2 = cmm_state_0_csrExe_addr == 12'hc04; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_2 = cmm_state_0_csrExe_addr == 12'hc05; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_2 = cmm_state_0_csrExe_addr == 12'hc06; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_2 = cmm_state_0_csrExe_addr == 12'hc07; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_2 = cmm_state_0_csrExe_addr == 12'hc08; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_2 = cmm_state_0_csrExe_addr == 12'hc09; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_2 = cmm_state_0_csrExe_addr == 12'hc0a; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_1 = cmm_state_0_csrExe_addr == 12'hc0b; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_1 = cmm_state_0_csrExe_addr == 12'hc0c; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_1 = cmm_state_0_csrExe_addr == 12'hc0d; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_1 = cmm_state_0_csrExe_addr == 12'hc0e; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_1 = cmm_state_0_csrExe_addr == 12'hc0f; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_1 = cmm_state_0_csrExe_addr == 12'hc10; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_1 = cmm_state_0_csrExe_addr == 12'hc11; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_1 = cmm_state_0_csrExe_addr == 12'hc12; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_1 = cmm_state_0_csrExe_addr == 12'hc13; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_1 = cmm_state_0_csrExe_addr == 12'hc14; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_1 = cmm_state_0_csrExe_addr == 12'hc15; // @[CsrFiles.scala 443:59]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_315 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_285 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_53 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_54 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_55 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_56 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_57 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_58 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_59 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_60 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_61 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_62 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_63 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_1; // @[Mux.scala 27:73]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_1 = cmm_state_0_csrExe_addr == 12'hc16; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_1 = cmm_state_0_csrExe_addr == 12'hc17; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_1 = cmm_state_0_csrExe_addr == 12'hc18; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_1 = cmm_state_0_csrExe_addr == 12'hc19; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_1 = cmm_state_0_csrExe_addr == 12'hc1a; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_1 = cmm_state_0_csrExe_addr == 12'hc1b; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_1 = cmm_state_0_csrExe_addr == 12'hc1c; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_1 = cmm_state_0_csrExe_addr == 12'hc1d; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_1 = cmm_state_0_csrExe_addr == 12'hc1e; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_1 = cmm_state_0_csrExe_addr == 12'hc1f; // @[CsrFiles.scala 443:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_3 = cmm_state_0_csrExe_addr == 12'hb03; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_3 = cmm_state_0_csrExe_addr == 12'hb04; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_3 = cmm_state_0_csrExe_addr == 12'hb05; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_3 = cmm_state_0_csrExe_addr == 12'hb06; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_3 = cmm_state_0_csrExe_addr == 12'hb07; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_3 = cmm_state_0_csrExe_addr == 12'hb08; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_3 = cmm_state_0_csrExe_addr == 12'hb09; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_3 = cmm_state_0_csrExe_addr == 12'hb0a; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_2 = cmm_state_0_csrExe_addr == 12'hb0b; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_2 = cmm_state_0_csrExe_addr == 12'hb0c; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_2 = cmm_state_0_csrExe_addr == 12'hb0d; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_2 = cmm_state_0_csrExe_addr == 12'hb0e; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_2 = cmm_state_0_csrExe_addr == 12'hb0f; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_2 = cmm_state_0_csrExe_addr == 12'hb10; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_2 = cmm_state_0_csrExe_addr == 12'hb11; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_2 = cmm_state_0_csrExe_addr == 12'hb12; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_2 = cmm_state_0_csrExe_addr == 12'hb13; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_2 = cmm_state_0_csrExe_addr == 12'hb14; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_2 = cmm_state_0_csrExe_addr == 12'hb15; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_2 = cmm_state_0_csrExe_addr == 12'hb16; // @[CsrFiles.scala 449:59]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_345 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_315 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_2; // @[Mux.scala 27:73]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_2 = cmm_state_0_csrExe_addr == 12'hb17; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_2 = cmm_state_0_csrExe_addr == 12'hb18; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_2 = cmm_state_0_csrExe_addr == 12'hb19; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_2 = cmm_state_0_csrExe_addr == 12'hb1a; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_2 = cmm_state_0_csrExe_addr == 12'hb1b; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_2 = cmm_state_0_csrExe_addr == 12'hb1c; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_2 = cmm_state_0_csrExe_addr == 12'hb1d; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_2 = cmm_state_0_csrExe_addr == 12'hb1e; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_2 = cmm_state_0_csrExe_addr == 12'hb1f; // @[CsrFiles.scala 449:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_4 = cmm_state_0_csrExe_addr == 12'h323; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_4 = cmm_state_0_csrExe_addr == 12'h324; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_4 = cmm_state_0_csrExe_addr == 12'h325; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_4 = cmm_state_0_csrExe_addr == 12'h326; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_4 = cmm_state_0_csrExe_addr == 12'h327; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_4 = cmm_state_0_csrExe_addr == 12'h328; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_4 = cmm_state_0_csrExe_addr == 12'h329; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_4 = cmm_state_0_csrExe_addr == 12'h32a; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_3 = cmm_state_0_csrExe_addr == 12'h32b; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_3 = cmm_state_0_csrExe_addr == 12'h32c; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_3 = cmm_state_0_csrExe_addr == 12'h32d; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_3 = cmm_state_0_csrExe_addr == 12'h32e; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_3 = cmm_state_0_csrExe_addr == 12'h32f; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_3 = cmm_state_0_csrExe_addr == 12'h330; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_3 = cmm_state_0_csrExe_addr == 12'h331; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_3 = cmm_state_0_csrExe_addr == 12'h332; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_3 = cmm_state_0_csrExe_addr == 12'h333; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_3 = cmm_state_0_csrExe_addr == 12'h334; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_3 = cmm_state_0_csrExe_addr == 12'h335; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_3 = cmm_state_0_csrExe_addr == 12'h336; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_3 = cmm_state_0_csrExe_addr == 12'h337; // @[CsrFiles.scala 455:59]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_375 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_345 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_4 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_3; // @[Mux.scala 27:73]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_3 = cmm_state_0_csrExe_addr == 12'h338; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_3 = cmm_state_0_csrExe_addr == 12'h339; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_3 = cmm_state_0_csrExe_addr == 12'h33a; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_3 = cmm_state_0_csrExe_addr == 12'h33b; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_3 = cmm_state_0_csrExe_addr == 12'h33c; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_3 = cmm_state_0_csrExe_addr == 12'h33d; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_3 = cmm_state_0_csrExe_addr == 12'h33e; // @[CsrFiles.scala 455:59]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_3 = cmm_state_0_csrExe_addr == 12'h33f; // @[CsrFiles.scala 455:59]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_2 = cmm_state_0_csrExe_addr == 12'h1; // @[CsrFiles.scala 469:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_3 = cmm_state_0_csrExe_addr == 12'h2; // @[CsrFiles.scala 470:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_4 = cmm_state_0_csrExe_addr == 12'h3; // @[CsrFiles.scala 471:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_5 = cmm_state_0_csrExe_addr == 12'hc00; // @[CsrFiles.scala 472:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_6 = cmm_state_0_csrExe_addr == 12'hc01; // @[CsrFiles.scala 473:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_7 = cmm_state_0_csrExe_addr == 12'hc02; // @[CsrFiles.scala 474:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_8 = cmm_state_0_csrExe_addr == 12'h100; // @[CsrFiles.scala 475:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_9 = cmm_state_0_csrExe_addr == 12'h104; // @[CsrFiles.scala 478:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_10 = cmm_state_0_csrExe_addr == 12'h105; // @[CsrFiles.scala 479:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_11 = cmm_state_0_csrExe_addr == 12'h106; // @[CsrFiles.scala 480:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_12 = cmm_state_0_csrExe_addr == 12'h140; // @[CsrFiles.scala 481:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_13 = cmm_state_0_csrExe_addr == 12'h141; // @[CsrFiles.scala 482:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_14 = cmm_state_0_csrExe_addr == 12'h142; // @[CsrFiles.scala 483:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_15 = cmm_state_0_csrExe_addr == 12'h143; // @[CsrFiles.scala 484:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_16 = cmm_state_0_csrExe_addr == 12'h144; // @[CsrFiles.scala 485:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_17 = cmm_state_0_csrExe_addr == 12'h180; // @[CsrFiles.scala 486:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_40 = cmm_state_0_csrExe_addr == 12'hf11; // @[CsrFiles.scala 509:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_41 = cmm_state_0_csrExe_addr == 12'hf12; // @[CsrFiles.scala 510:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_42 = cmm_state_0_csrExe_addr == 12'hf13; // @[CsrFiles.scala 511:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_43 = cmm_state_0_csrExe_addr == 12'hf14; // @[CsrFiles.scala 512:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_44 = cmm_state_0_csrExe_addr == 12'h300; // @[CsrFiles.scala 513:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_45 = cmm_state_0_csrExe_addr == 12'h301; // @[CsrFiles.scala 514:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_46 = cmm_state_0_csrExe_addr == 12'h302; // @[CsrFiles.scala 515:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_47 = cmm_state_0_csrExe_addr == 12'h303; // @[CsrFiles.scala 516:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_48 = cmm_state_0_csrExe_addr == 12'h304; // @[CsrFiles.scala 517:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_430 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_375 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_3 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_3 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_2 | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_3
     | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_4 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_8 | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_9
     | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_10 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_11 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_12 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_13 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_14 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_15 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_16 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_17 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_40 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_41 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_42 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_43 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_44 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_45 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_46 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_47 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_48; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_49 = cmm_state_0_csrExe_addr == 12'h305; // @[CsrFiles.scala 518:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_50 = cmm_state_0_csrExe_addr == 12'h306; // @[CsrFiles.scala 519:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_51 = cmm_state_0_csrExe_addr == 12'h340; // @[CsrFiles.scala 520:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_52 = cmm_state_0_csrExe_addr == 12'h341; // @[CsrFiles.scala 521:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_53 = cmm_state_0_csrExe_addr == 12'h342; // @[CsrFiles.scala 522:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_54 = cmm_state_0_csrExe_addr == 12'h343; // @[CsrFiles.scala 523:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_55 = cmm_state_0_csrExe_addr == 12'h344; // @[CsrFiles.scala 524:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_56 = cmm_state_0_csrExe_addr == 12'h34a; // @[CsrFiles.scala 525:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_57 = cmm_state_0_csrExe_addr == 12'h34b; // @[CsrFiles.scala 526:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_58 = cmm_state_0_csrExe_addr == 12'hb00; // @[CsrFiles.scala 528:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_59 = cmm_state_0_csrExe_addr == 12'hb02; // @[CsrFiles.scala 529:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_60 = cmm_state_0_csrExe_addr == 12'h320; // @[CsrFiles.scala 530:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_61 = cmm_state_0_csrExe_addr == 12'h7a0; // @[CsrFiles.scala 531:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_62 = cmm_state_0_csrExe_addr == 12'h7a1; // @[CsrFiles.scala 532:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_63 = cmm_state_0_csrExe_addr == 12'h7a2; // @[CsrFiles.scala 533:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_64 = cmm_state_0_csrExe_addr == 12'h7a3; // @[CsrFiles.scala 534:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_65 = cmm_state_0_csrExe_addr == 12'h7b0; // @[CsrFiles.scala 535:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_66 = cmm_state_0_csrExe_addr == 12'h7b1; // @[CsrFiles.scala 536:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_67 = cmm_state_0_csrExe_addr == 12'h7b2; // @[CsrFiles.scala 537:18]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_68 = cmm_state_0_csrExe_addr == 12'h7b3; // @[CsrFiles.scala 538:18]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_430 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_49 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_50 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_51 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_52 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_53 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_54 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_55 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_56 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_57 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_58 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_59 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_60 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_61 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_62 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_63 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_64 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_65 & csrfiles_DMode |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_66 & csrfiles_DMode |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_67 & csrfiles_DMode |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_68 & csrfiles_DMode; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_69 = ~
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res; // @[CsrFiles.scala 542:5]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_466 =
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_1 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_691 =
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_1 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_1 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_1 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_1 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_1 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_1 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_1 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_466; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_706 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_691 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_721 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_706 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_29 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_30 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_31 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_32 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_33 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_34 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_35 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_36 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_37 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_736 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_721 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_38 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_39 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_40 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_41 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_42 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_43 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_44 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_45 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_46 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_47 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_48 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_49 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_50 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_51 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_52 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_755 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_736 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_53 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_54 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_55 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_56 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_57 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_58 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_59 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_60 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_61 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_62 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_63 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_2; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_556 =
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_3 & cmm_state_0_is_csrr_illegal_reg_sel_4_2; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_781 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_755 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_3 & cmm_state_0_is_csrr_illegal_reg_sel_0_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_3 & cmm_state_0_is_csrr_illegal_reg_sel_1_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_3 & cmm_state_0_is_csrr_illegal_reg_sel_2_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_3 & cmm_state_0_is_csrr_illegal_reg_sel_3_2 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_556; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_796 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_781 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_3 & cmm_state_0_is_csrr_illegal_reg_sel_5_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_3 & cmm_state_0_is_csrr_illegal_reg_sel_6_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_3 & cmm_state_0_is_csrr_illegal_reg_sel_7_2 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_2 & cmm_state_0_is_csrr_illegal_reg_sel_8_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_2 & cmm_state_0_is_csrr_illegal_reg_sel_9_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_2 & cmm_state_0_is_csrr_illegal_reg_sel_10_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_2 & cmm_state_0_is_csrr_illegal_reg_sel_11_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_2 & cmm_state_0_is_csrr_illegal_reg_sel_12_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_2 & cmm_state_0_is_csrr_illegal_reg_sel_13_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_2 & cmm_state_0_is_csrr_illegal_reg_sel_14_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_2 & cmm_state_0_is_csrr_illegal_reg_sel_15_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_2 & cmm_state_0_is_csrr_illegal_reg_sel_16_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_2 & cmm_state_0_is_csrr_illegal_reg_sel_17_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_2 & cmm_state_0_is_csrr_illegal_reg_sel_18_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_2 & cmm_state_0_is_csrr_illegal_reg_sel_19_1; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_811 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_796 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_2 & cmm_state_0_is_csrr_illegal_reg_sel_20_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_2 & cmm_state_0_is_csrr_illegal_reg_sel_21_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_2 & cmm_state_0_is_csrr_illegal_reg_sel_22_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_2 & cmm_state_0_is_csrr_illegal_reg_sel_23_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_2 & cmm_state_0_is_csrr_illegal_reg_sel_24_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_2 & cmm_state_0_is_csrr_illegal_reg_sel_25_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_2 & cmm_state_0_is_csrr_illegal_reg_sel_26_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_2 & cmm_state_0_is_csrr_illegal_reg_sel_27_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_2 & cmm_state_0_is_csrr_illegal_reg_sel_28_1 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_4 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_4 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_4 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_4 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_4 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_4 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_826 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_811 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_4 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_4 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_3 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_620 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_12 & _cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_845 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_826 |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_3 & _is_xRet_is_mRet_T |
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_3 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_2 | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_3
     | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_4 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_5 | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_6
     | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_7 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_8 | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_9
     & _cmm_state_0_is_csrr_illegal_T_15 | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_10 &
    _cmm_state_0_is_csrr_illegal_T_15 | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_11 &
    _cmm_state_0_is_csrr_illegal_T_15 | _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_620; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_882 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_845 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_13 & _cmm_state_0_is_csrr_illegal_T_15 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_14 & _cmm_state_0_is_csrr_illegal_T_15 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_15 & _cmm_state_0_is_csrr_illegal_T_15 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_16 & _cmm_state_0_is_csrr_illegal_T_15 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_17 & _cmm_state_0_is_csrr_illegal_T_35 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_40 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_41 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_42 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_43 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_44 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_45 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_46 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_47 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_48 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_49 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_897 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_882 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_50 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_51 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_52 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_53 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_54 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_55 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_56 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_57 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_58 & _cmm_state_0_is_csrr_illegal_T_99 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_59 & _cmm_state_0_is_csrr_illegal_T_105 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_60 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_61 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_62 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_63 & _is_xRet_is_mRet_T |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_64 & _is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_1 =
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_897 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_65 & csrfiles_DMode |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_66 & csrfiles_DMode |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_67 & csrfiles_DMode |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_68 & csrfiles_DMode; // @[Mux.scala 27:73]
  wire  _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_190 = ~
    is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_1; // @[CsrFiles.scala 425:5]
  wire  is_trap_is_exception_is_csr_illegal_is_csrw_illegal = (cmm_state_0_csrExe_op_rc | cmm_state_0_csrExe_op_rs |
    cmm_state_0_csrExe_op_rw) & (_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_69 |
    _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_190); // @[Commit.scala 135:74]
  wire  _is_trap_is_exception_is_csr_illegal_T_4 = is_trap_is_exception_is_csr_illegal_is_csrw_illegal &
    io_rod_0_bits_is_csr & io_cm_op_0_is_writeback; // @[Commit.scala 149:38]
  wire  _is_trap_is_exception_is_csr_illegal_T_5 = cmm_state_0_is_csrr_illegal & io_rod_0_bits_is_csr & ~
    io_cm_op_0_is_writeback | _is_trap_is_exception_is_csr_illegal_T_4; // @[Commit.scala 148:48]
  wire  cmm_state_0_fcsrExe_op_rc = fcsrExe_mdl_io_deq_0_bits_op_rc; // @[Commit.scala 330:23 643:26]
  wire  cmm_state_0_fcsrExe_op_rs = fcsrExe_mdl_io_deq_0_bits_op_rs; // @[Commit.scala 330:23 643:26]
  wire  cmm_state_0_fcsrExe_op_rw = fcsrExe_mdl_io_deq_0_bits_op_rw; // @[Commit.scala 330:23 643:26]
  wire  _is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T_2 = csrfiles_mstatus_fs == 2'h0; // @[Commit.scala 140:101]
  wire  is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal = (cmm_state_0_fcsrExe_op_rc | cmm_state_0_fcsrExe_op_rs |
    cmm_state_0_fcsrExe_op_rw) & csrfiles_mstatus_fs == 2'h0; // @[Commit.scala 140:78]
  wire  _is_trap_is_exception_is_csr_illegal_T_7 = is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal &
    io_rod_0_bits_is_fcsr & io_cm_op_0_is_writeback; // @[Commit.scala 150:39]
  wire  is_trap_is_exception_is_csr_illegal = _is_trap_is_exception_is_csr_illegal_T_5 |
    _is_trap_is_exception_is_csr_illegal_T_7; // @[Commit.scala 149:48]
  wire  is_trap_is_exception_is_ill_sfence = io_cm_op_0_is_writeback & io_rod_0_bits_is_sfence_vma & (
    csrfiles_mstatus_tvm & _is_xRet_is_sRet_T_1 |
    _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3); // @[Commit.scala 152:51]
  wire  is_trap_is_exception_is_ill_wfi = io_cm_op_0_is_writeback & io_rod_0_bits_is_wfi & (csrfiles_mstatus_tw &
    csrfiles_priv_lvl < 2'h3); // @[Commit.scala 153:49]
  wire  is_trap_is_exception_is_ill_mRet = io_rod_0_bits_privil_mret & csrfiles_priv_lvl != 2'h3; // @[Commit.scala 155:39]
  wire  is_trap_is_exception_is_ill_sRet = io_rod_0_bits_privil_sret & (
    _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3 |
    _is_xRet_is_sRet_T_1 & csrfiles_mstatus_tsr); // @[Commit.scala 156:39]
  wire  is_trap_is_exception_is_ill_dRet = io_rod_0_bits_privil_dret & _is_trap_is_interrupt_T_2; // @[Commit.scala 157:39]
  wire  is_trap_is_exception_is_ill_fpus = io_cm_op_0_is_writeback & io_rod_0_bits_is_fpu &
    _is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T_2; // @[Commit.scala 158:45]
  wire  is_trap_is_exception_is_illeage = io_rod_0_bits_is_illeage | is_trap_is_exception_is_csr_illegal |
    is_trap_is_exception_is_ill_sfence | is_trap_is_exception_is_ill_wfi | is_trap_is_exception_is_ill_mRet |
    is_trap_is_exception_is_ill_sRet | is_trap_is_exception_is_ill_dRet | is_trap_is_exception_is_ill_fpus; // @[Commit.scala 160:125]
  wire  _is_trap_is_exception_T_4 = _is_trap_is_exception_T_2 | is_trap_is_exception_is_illeage; // @[Commit.scala 195:32]
  wire  is_trap_is_exception_is_load_accessFault = io_lsu_cmm_is_access_fault & io_rod_0_bits_is_lu &
    _is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 66:67]
  wire  _is_trap_is_exception_T_5 = _is_trap_is_exception_T_4 | is_trap_is_exception_is_load_accessFault; // @[Commit.scala 196:32]
  wire  _is_trap_is_exception_is_store_accessFault_T = io_rod_0_bits_is_su | io_rod_0_bits_is_amo; // @[Commit.scala 71:70]
  wire  is_trap_is_exception_is_store_accessFault = io_lsu_cmm_is_access_fault & (io_rod_0_bits_is_su |
    io_rod_0_bits_is_amo) & _is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 71:85]
  wire  _is_trap_is_exception_T_6 = _is_trap_is_exception_T_5 | is_trap_is_exception_is_store_accessFault; // @[Commit.scala 197:32]
  wire  is_trap_is_exception_is_load_misAlign = io_lsu_cmm_is_misAlign & io_rod_0_bits_is_lu &
    _is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 86:60]
  wire  _is_trap_is_exception_T_7 = _is_trap_is_exception_T_6 | is_trap_is_exception_is_load_misAlign; // @[Commit.scala 198:32]
  wire  is_trap_is_exception_is_store_misAlign = io_lsu_cmm_is_misAlign & _is_trap_is_exception_is_store_accessFault_T
     & _is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 95:76]
  wire  _is_trap_is_exception_T_8 = _is_trap_is_exception_T_7 | is_trap_is_exception_is_store_misAlign; // @[Commit.scala 199:32]
  wire  is_trap_is_exception_is_load_pagingFault = io_lsu_cmm_is_paging_fault & io_rod_0_bits_is_lu &
    _is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 76:67]
  wire  _is_trap_is_exception_T_9 = _is_trap_is_exception_T_8 | is_trap_is_exception_is_load_pagingFault; // @[Commit.scala 200:32]
  wire  is_trap_is_exception_is_store_pagingFault = io_lsu_cmm_is_paging_fault &
    _is_trap_is_exception_is_store_accessFault_T & _is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 81:85]
  wire  is_trap_is_exception = _is_trap_is_exception_T_9 | is_trap_is_exception_is_store_pagingFault; // @[Commit.scala 201:32]
  wire  is_trap = is_trap_is_interrupt | is_trap_is_exception; // @[Commit.scala 212:32]
  wire  is_fence_i = io_rod_0_bits_is_fence_i & io_cm_op_0_is_writeback; // @[Commit.scala 180:37]
  wire  is_sfence_vma = io_rod_0_bits_is_sfence_vma & io_cm_op_0_is_writeback & (_cmm_state_0_is_csrr_illegal_T_33 &
    _is_xRet_is_sRet_T_1 | _is_xRet_is_mRet_T); // @[Commit.scala 185:51]
  wire  _T_9 = is_xRet | is_trap | is_fence_i | is_sfence_vma; // @[Commit.scala 426:81]
  wire  _T_10 = bctq_mdl_io_deq_0_bits_isPredictTaken != bctq_mdl_io_deq_0_bits_isFinalTaken; // @[frontend.scala 245:37]
  wire [63:0] _GEN_2 = {{25'd0}, jctq_mdl_io_deq_0_bits_rasResp_target}; // @[frontend.scala 250:48]
  wire [63:0] _GEN_3 = {{25'd0}, jctq_mdl_io_deq_0_bits_btbResp_target}; // @[frontend.scala 250:80]
  wire  _T_15 = jctq_mdl_io_deq_0_bits_isRas ? _GEN_2 != jctq_mdl_io_deq_0_bits_finalTarget : _GEN_3 !=
    jctq_mdl_io_deq_0_bits_finalTarget; // @[frontend.scala 250:25]
  wire  is_step_1 = csrfiles_dcsr_step & _is_trap_is_interrupt_T_2; // @[Commit.scala 243:38]
  wire  _T_23 = ~csrExe_mdl_io_deq_0_valid; // @[Commit.scala 435:40]
  wire  _T_25 = ~fcsrExe_mdl_io_deq_0_valid; // @[Commit.scala 435:87]
  wire [1:0] _GEN_462 = io_rod_0_bits_is_csr & ~csrExe_mdl_io_deq_0_valid | io_rod_0_bits_is_fcsr & ~
    fcsrExe_mdl_io_deq_0_valid | io_rod_0_bits_is_branch & ~bctq_mdl_io_deq_0_valid | io_rod_0_bits_is_jalr & ~
    jctq_mdl_io_deq_0_valid ? 2'h0 : 2'h3; // @[Commit.scala 435:200 436:27 438:27]
  wire [1:0] _GEN_463 = io_cm_op_0_is_writeback ? _GEN_462 : 2'h0; // @[Commit.scala 434:41 442:25]
  wire [1:0] _GEN_464 = (io_rod_0_bits_is_branch & _T_10 & bctq_mdl_io_deq_0_valid | io_rod_0_bits_is_jalr & _T_15 &
    jctq_mdl_io_deq_0_valid) & io_cm_op_0_is_writeback & ~is_step_1 ? 2'h2 : _GEN_463; // @[Commit.scala 431:213 432:27]
  wire [1:0] _GEN_465 = _T_9 ? 2'h1 : _GEN_464; // @[Commit.scala 427:11 428:25]
  wire [1:0] commit_state_0 = ~io_rod_0_valid ? 2'h0 : _GEN_465; // @[Commit.scala 419:33 420:23]
  wire  commit_state_is_comfirm_0 = commit_state_0 == 2'h3; // @[Commit.scala 324:87]
  wire  commit_state_is_misPredict_0 = commit_state_0 == 2'h2; // @[Commit.scala 325:87]
  wire  commit_state_is_abort_0 = commit_state_0 == 2'h1; // @[Commit.scala 326:87]
  wire  is_retired_0 = commit_state_is_comfirm_0 | commit_state_is_misPredict_0; // @[Commit.scala 333:77]
  wire  _GEN_0 = emu_reset ? 1'h0 : emu_reset; // @[Commit.scala 363:26 365:{26,38}]
  wire  _GEN_1 = io_dm_hartResetReq | _GEN_0; // @[Commit.scala 364:{30,42}]
  wire  _T_1 = is_retired_0 | commit_state_is_abort_0; // @[Commit.scala 398:59]
  wire [1:0] _GEN_469 = emu_reset ? 2'h3 : csrfiles_priv_lvl; // @[CsrFiles.scala 707:{30,41}]
  wire [1:0] _GEN_470 = is_xRet_is_dRet ? csrfiles_dcsr_prv : _GEN_469; // @[CsrFiles.scala 710:{24,35}]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_74 = ~csrfiles_medeleg[15] ? 2'h3 : 2'h1; // @[CsrFiles.scala 736:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_75 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_74; // @[CsrFiles.scala 736:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_69 = ~csrfiles_medeleg[13] ? 2'h3 : 2'h1; // @[CsrFiles.scala 735:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_70 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_69; // @[CsrFiles.scala 735:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_64 = ~csrfiles_medeleg[12] ? 2'h3 : 2'h1; // @[CsrFiles.scala 734:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_65 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_64; // @[CsrFiles.scala 734:58]
  wire  csr_state_0_csrfiles_priv_lvl_is_ecall_M = io_rod_0_bits_privil_ecall & _is_xRet_is_mRet_T; // @[Commit.scala 115:31]
  wire  csr_state_0_csrfiles_priv_lvl_is_ecall_S = io_rod_0_bits_privil_ecall & _is_xRet_is_sRet_T_1; // @[Commit.scala 110:31]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_60 = ~csrfiles_medeleg[9] ? 2'h3 : 2'h1; // @[CsrFiles.scala 732:58]
  wire  csr_state_0_csrfiles_priv_lvl_is_ecall_U = io_rod_0_bits_privil_ecall &
    _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3; // @[Commit.scala 105:31]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_57 = ~csrfiles_medeleg[8] ? 2'h3 : 2'h1; // @[CsrFiles.scala 731:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_53 = ~csrfiles_medeleg[7] ? 2'h3 : 2'h1; // @[CsrFiles.scala 730:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_54 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_53; // @[CsrFiles.scala 730:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_48 = ~csrfiles_medeleg[6] ? 2'h3 : 2'h1; // @[CsrFiles.scala 729:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_49 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_48; // @[CsrFiles.scala 729:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_43 = ~csrfiles_medeleg[5] ? 2'h3 : 2'h1; // @[CsrFiles.scala 728:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_44 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_43; // @[CsrFiles.scala 728:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_38 = ~csrfiles_medeleg[4] ? 2'h3 : 2'h1; // @[CsrFiles.scala 727:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_39 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_38; // @[CsrFiles.scala 727:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_33 = ~csrfiles_medeleg[3] ? 2'h3 : 2'h1; // @[CsrFiles.scala 726:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_34 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_33; // @[CsrFiles.scala 726:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_28 = ~csrfiles_medeleg[2] ? 2'h3 : 2'h1; // @[CsrFiles.scala 725:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_29 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_28; // @[CsrFiles.scala 725:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_23 = ~csrfiles_medeleg[1] ? 2'h3 : 2'h1; // @[CsrFiles.scala 724:106]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_24 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_23; // @[CsrFiles.scala 724:58]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_13 = ~csrfiles_mideleg[9] ? 2'h3 : 2'h1; // @[CsrFiles.scala 719:97]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_14 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_13; // @[CsrFiles.scala 719:49]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_8 = ~csrfiles_mideleg[5] ? 2'h3 : 2'h1; // @[CsrFiles.scala 717:97]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_9 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_8; // @[CsrFiles.scala 717:49]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_3 = ~csrfiles_mideleg[1] ? 2'h3 : 2'h1; // @[CsrFiles.scala 715:97]
  wire [1:0] _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_4 = _is_xRet_is_mRet_T ? 2'h3 :
    _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_3; // @[CsrFiles.scala 715:49]
  wire [1:0] _GEN_471 = is_xRet_is_mRet ? csrfiles_mstatus_mpp : _GEN_469; // @[CsrFiles.scala 712:{24,35}]
  wire [1:0] _GEN_472 = is_xRet_is_sRet ? {{1'd0}, csrfiles_mstatus_spp} : _GEN_471; // @[CsrFiles.scala 713:{24,35}]
  wire [1:0] _GEN_473 = is_trap_is_interrupt_is_s_interrupt_is_ssi ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_4 :
    _GEN_472; // @[CsrFiles.scala 715:{32,43}]
  wire [1:0] _GEN_474 = is_trap_is_interrupt_is_m_interrupt_is_msi ? 2'h3 : _GEN_473; // @[CsrFiles.scala 716:{32,43}]
  wire [1:0] _GEN_475 = is_trap_is_interrupt_is_s_interrupt_is_sti ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_9 :
    _GEN_474; // @[CsrFiles.scala 717:{32,43}]
  wire [1:0] _GEN_476 = is_trap_is_interrupt_is_m_interrupt_is_mti ? 2'h3 : _GEN_475; // @[CsrFiles.scala 718:{32,43}]
  wire [1:0] _GEN_477 = is_trap_is_interrupt_is_s_interrupt_is_sei ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_14 :
    _GEN_476; // @[CsrFiles.scala 719:{32,43}]
  wire [1:0] _GEN_478 = is_trap_is_interrupt_is_m_interrupt_is_mei ? 2'h3 : _GEN_477; // @[CsrFiles.scala 720:{32,43}]
  wire [1:0] _GEN_480 = io_rod_0_bits_privil_is_access_fault ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_24 : _GEN_478; // @[CsrFiles.scala 724:{41,52}]
  wire [1:0] _GEN_481 = is_trap_is_exception_is_illeage ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_29 : _GEN_480; // @[CsrFiles.scala 725:{41,52}]
  wire [1:0] _GEN_482 = is_trap_is_exception_is_ebreak_exc ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_34 : _GEN_481; // @[CsrFiles.scala 726:{41,52}]
  wire [1:0] _GEN_483 = is_trap_is_exception_is_load_misAlign ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_39 : _GEN_482; // @[CsrFiles.scala 727:{41,52}]
  wire [1:0] _GEN_484 = is_trap_is_exception_is_load_accessFault ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_44 :
    _GEN_483; // @[CsrFiles.scala 728:{41,52}]
  wire [1:0] _GEN_485 = is_trap_is_exception_is_store_misAlign ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_49 : _GEN_484
    ; // @[CsrFiles.scala 729:{41,52}]
  wire [1:0] _GEN_486 = is_trap_is_exception_is_store_accessFault ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_54 :
    _GEN_485; // @[CsrFiles.scala 730:{41,52}]
  wire [1:0] _GEN_487 = csr_state_0_csrfiles_priv_lvl_is_ecall_U ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_57 :
    _GEN_486; // @[CsrFiles.scala 731:{41,52}]
  wire [1:0] _GEN_488 = csr_state_0_csrfiles_priv_lvl_is_ecall_S ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_60 :
    _GEN_487; // @[CsrFiles.scala 732:{41,52}]
  wire [1:0] _GEN_489 = csr_state_0_csrfiles_priv_lvl_is_ecall_M ? 2'h3 : _GEN_488; // @[CsrFiles.scala 733:{41,52}]
  wire [1:0] _GEN_490 = io_rod_0_bits_privil_is_paging_fault ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_65 : _GEN_489; // @[CsrFiles.scala 734:{41,52}]
  wire [1:0] _GEN_491 = is_trap_is_exception_is_load_pagingFault ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_70 :
    _GEN_490; // @[CsrFiles.scala 735:{41,52}]
  wire [1:0] _GEN_492 = is_trap_is_exception_is_store_pagingFault ? _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_75 :
    _GEN_491; // @[CsrFiles.scala 736:{41,52}]
  wire [1:0] csr_state_0_csrfiles_priv_lvl_priv_lvl = csrfiles_DMode ? _GEN_470 : _GEN_492; // @[CsrFiles.scala 709:31]
  wire  _GEN_494 = is_xRet_is_dRet ? 1'h0 : csrfiles_DMode; // @[CsrFiles.scala 1872:{31,39}]
  wire  csr_state_0_csrfiles_DMode_DMode = is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt | _GEN_494; // @[CsrFiles.scala 1871:{37,45}]
  wire [63:0] cmm_state_0_csrExe_dat_i = csrExe_mdl_io_deq_0_bits_dat_i; // @[Commit.scala 330:23 642:26]
  wire  csr_state_0_csrfiles_mstatus_is_fpu_state_change = ~is_trap & io_rod_0_bits_is_fpu; // @[Commit.scala 222:40]
  wire  csr_state_0_csrfiles_mstatus_enable0 = _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_8 & (
    cmm_state_0_csrExe_op_rw | cmm_state_0_csrExe_op_rs | cmm_state_0_csrExe_op_rc); // @[CsrFiles.scala 42:37]
  wire [63:0] _csr_state_0_csrfiles_mstatus_dnxt_T_3 = cmm_state_0_csrExe_op_rw ? cmm_state_0_csrExe_dat_i : 64'h0; // @[Mux.scala 27:73]
  wire [46:0] csr_state_0_csrfiles_mstatus_hi = {csrfiles_mstatus_sd,25'h0,2'h0,13'h1400,csrfiles_mstatus_tsr,
    csrfiles_mstatus_tw,csrfiles_mstatus_tvm,csrfiles_mstatus_mxr,csrfiles_mstatus_sum,csrfiles_mstatus_mprv}; // @[CsrFiles.scala 755:62]
  wire [5:0] csr_state_0_csrfiles_mstatus_lo_lo = {csrfiles_mstatus_spie,1'h0,csrfiles_mstatus_mie,1'h0,
    csrfiles_mstatus_sie,1'h0}; // @[CsrFiles.scala 755:62]
  wire [63:0] _csr_state_0_csrfiles_mstatus_T = {csr_state_0_csrfiles_mstatus_hi,2'h0,csrfiles_mstatus_fs,
    csrfiles_mstatus_mpp,2'h0,csrfiles_mstatus_spp,csrfiles_mstatus_mpie,1'h0,csr_state_0_csrfiles_mstatus_lo_lo}; // @[CsrFiles.scala 755:62]
  wire [63:0] _csr_state_0_csrfiles_mstatus_dnxt_T = _csr_state_0_csrfiles_mstatus_T | cmm_state_0_csrExe_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_mstatus_dnxt_T_4 = cmm_state_0_csrExe_op_rs ? _csr_state_0_csrfiles_mstatus_dnxt_T
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_mstatus_dnxt_T_6 = _csr_state_0_csrfiles_mstatus_dnxt_T_3 |
    _csr_state_0_csrfiles_mstatus_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_mstatus_dnxt_T_1 = ~cmm_state_0_csrExe_dat_i; // @[CsrFiles.scala 46:32]
  wire [63:0] _csr_state_0_csrfiles_mstatus_dnxt_T_2 = _csr_state_0_csrfiles_mstatus_T &
    _csr_state_0_csrfiles_mstatus_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] _csr_state_0_csrfiles_mstatus_dnxt_T_5 = cmm_state_0_csrExe_op_rc ? _csr_state_0_csrfiles_mstatus_dnxt_T_2
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] csr_state_0_csrfiles_mstatus_dnxt0 = _csr_state_0_csrfiles_mstatus_dnxt_T_6 |
    _csr_state_0_csrfiles_mstatus_dnxt_T_5; // @[Mux.scala 27:73]
  wire  csr_state_0_csrfiles_mstatus_enable1 = _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_44 & (
    cmm_state_0_csrExe_op_rw | cmm_state_0_csrExe_op_rs | cmm_state_0_csrExe_op_rc); // @[CsrFiles.scala 42:37]
  wire [1:0] _GEN_722 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[14:13] :
    csrfiles_mstatus_fs; // @[CsrFiles.scala 792:24 799:20]
  wire [1:0] _GEN_731 = csr_state_0_csrfiles_mstatus_enable0 ? csr_state_0_csrfiles_mstatus_dnxt0[14:13] : _GEN_722; // @[CsrFiles.scala 783:24 787:20]
  wire [1:0] _GEN_747 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_fs : _GEN_731; // @[CsrFiles.scala 777:51]
  wire [1:0] _GEN_763 = is_xRet_is_mRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_fs : _GEN_747; // @[CsrFiles.scala 770:50]
  wire [1:0] _GEN_777 = is_trap & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_fs : _GEN_763; // @[CsrFiles.scala 758:45]
  wire [1:0] csr_state_0_csrfiles_mstatus_mstatus_fs = csr_state_0_csrfiles_mstatus_is_fpu_state_change &
    csrfiles_mstatus_fs != 2'h0 ? 2'h3 : _GEN_777; // @[CsrFiles.scala 808:67 809:18]
  wire  csr_state_0_csrfiles_mstatus_mstatus_sd = csr_state_0_csrfiles_mstatus_mstatus_fs == 2'h3; // @[CsrFiles.scala 747:57]
  wire  _GEN_716 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[22] : csrfiles_mstatus_tsr; // @[CsrFiles.scala 792:24 793:20]
  wire  _GEN_735 = csr_state_0_csrfiles_mstatus_enable0 ? csrfiles_mstatus_tsr : _GEN_716; // @[CsrFiles.scala 783:24]
  wire  _GEN_749 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_tsr : _GEN_735; // @[CsrFiles.scala 777:51]
  wire  _GEN_717 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[21] : csrfiles_mstatus_tw; // @[CsrFiles.scala 792:24 794:20]
  wire  _GEN_736 = csr_state_0_csrfiles_mstatus_enable0 ? csrfiles_mstatus_tw : _GEN_717; // @[CsrFiles.scala 783:24]
  wire  _GEN_750 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_tw : _GEN_736; // @[CsrFiles.scala 777:51]
  wire  _GEN_718 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[20] : csrfiles_mstatus_tvm; // @[CsrFiles.scala 792:24 795:20]
  wire  _GEN_737 = csr_state_0_csrfiles_mstatus_enable0 ? csrfiles_mstatus_tvm : _GEN_718; // @[CsrFiles.scala 783:24]
  wire  _GEN_751 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_tvm : _GEN_737; // @[CsrFiles.scala 777:51]
  wire  _GEN_719 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[19] : csrfiles_mstatus_mxr; // @[CsrFiles.scala 792:24 796:20]
  wire  _GEN_729 = csr_state_0_csrfiles_mstatus_enable0 ? csr_state_0_csrfiles_mstatus_dnxt0[19] : _GEN_719; // @[CsrFiles.scala 783:24 785:20]
  wire  _GEN_745 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_mxr : _GEN_729; // @[CsrFiles.scala 777:51]
  wire  _GEN_720 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[18] : csrfiles_mstatus_sum; // @[CsrFiles.scala 792:24 797:20]
  wire  _GEN_730 = csr_state_0_csrfiles_mstatus_enable0 ? csr_state_0_csrfiles_mstatus_dnxt0[18] : _GEN_720; // @[CsrFiles.scala 783:24 786:20]
  wire  _GEN_746 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_sum : _GEN_730; // @[CsrFiles.scala 777:51]
  wire  _csr_state_0_csrfiles_mstatus_mstatus_mprv_T_8 = csr_state_0_csrfiles_priv_lvl_priv_lvl != 2'h3 ? 1'h0 :
    csrfiles_mstatus_mprv; // @[CsrFiles.scala 775:26]
  wire  _GEN_721 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[17] : csrfiles_mstatus_mprv
    ; // @[CsrFiles.scala 792:24 798:20]
  wire  _GEN_738 = csr_state_0_csrfiles_mstatus_enable0 ? csrfiles_mstatus_mprv : _GEN_721; // @[CsrFiles.scala 783:24]
  wire  _GEN_744 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? _csr_state_0_csrfiles_mstatus_mstatus_mprv_T_8 :
    _GEN_738; // @[CsrFiles.scala 777:51 781:20]
  wire [1:0] _GEN_723 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[12:11] :
    csrfiles_mstatus_mpp; // @[CsrFiles.scala 792:24 800:20]
  wire [1:0] _GEN_739 = csr_state_0_csrfiles_mstatus_enable0 ? csrfiles_mstatus_mpp : _GEN_723; // @[CsrFiles.scala 783:24]
  wire [1:0] _GEN_752 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_mpp : _GEN_739; // @[CsrFiles.scala 777:51]
  wire  _csr_state_0_csrfiles_mstatus_mstatus_spp_T_1 =
    _is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3 ? 1'h0 : 1'h1; // @[CsrFiles.scala 765:28]
  wire  _GEN_724 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[8] : csrfiles_mstatus_spp; // @[CsrFiles.scala 792:24 801:20]
  wire  _GEN_732 = csr_state_0_csrfiles_mstatus_enable0 ? csr_state_0_csrfiles_mstatus_dnxt0[8] : _GEN_724; // @[CsrFiles.scala 783:24 788:20]
  wire  _GEN_748 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_spp : _GEN_732; // @[CsrFiles.scala 777:51]
  wire  _GEN_725 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[7] : csrfiles_mstatus_mpie; // @[CsrFiles.scala 792:24 802:20]
  wire  _GEN_740 = csr_state_0_csrfiles_mstatus_enable0 ? csrfiles_mstatus_mpie : _GEN_725; // @[CsrFiles.scala 783:24]
  wire  _GEN_753 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_mpie : _GEN_740; // @[CsrFiles.scala 777:51]
  wire  _GEN_756 = is_xRet_is_mRet & _is_trap_is_interrupt_T_2 | _GEN_753; // @[CsrFiles.scala 770:50 772:20]
  wire  _GEN_726 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[5] : csrfiles_mstatus_spie; // @[CsrFiles.scala 792:24 803:20]
  wire  _GEN_733 = csr_state_0_csrfiles_mstatus_enable0 ? csr_state_0_csrfiles_mstatus_dnxt0[5] : _GEN_726; // @[CsrFiles.scala 783:24 789:20]
  wire  _GEN_742 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 | _GEN_733; // @[CsrFiles.scala 777:51 778:20]
  wire  _GEN_727 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[3] : csrfiles_mstatus_mie; // @[CsrFiles.scala 792:24 804:20]
  wire  _GEN_741 = csr_state_0_csrfiles_mstatus_enable0 ? csrfiles_mstatus_mie : _GEN_727; // @[CsrFiles.scala 783:24]
  wire  _GEN_754 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_mie : _GEN_741; // @[CsrFiles.scala 777:51]
  wire  _GEN_728 = csr_state_0_csrfiles_mstatus_enable1 ? csr_state_0_csrfiles_mstatus_dnxt0[1] : csrfiles_mstatus_sie; // @[CsrFiles.scala 792:24 805:20]
  wire  _GEN_734 = csr_state_0_csrfiles_mstatus_enable0 ? csr_state_0_csrfiles_mstatus_dnxt0[1] : _GEN_728; // @[CsrFiles.scala 783:24 790:20]
  wire  _GEN_743 = is_xRet_is_sRet & _is_trap_is_interrupt_T_2 ? csrfiles_mstatus_spie : _GEN_734; // @[CsrFiles.scala 777:51 779:20]
  wire  csr_state_0_csrfiles_medeleg_enable = _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_46 & (
    cmm_state_0_csrExe_op_rw | cmm_state_0_csrExe_op_rs | cmm_state_0_csrExe_op_rc); // @[CsrFiles.scala 42:37]
  wire [63:0] _csr_state_0_csrfiles_medeleg_dnxt_T = csrfiles_medeleg | cmm_state_0_csrExe_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_medeleg_dnxt_T_4 = cmm_state_0_csrExe_op_rs ? _csr_state_0_csrfiles_medeleg_dnxt_T
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_medeleg_dnxt_T_6 = _csr_state_0_csrfiles_mstatus_dnxt_T_3 |
    _csr_state_0_csrfiles_medeleg_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_medeleg_dnxt_T_2 = csrfiles_medeleg & _csr_state_0_csrfiles_mstatus_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] _csr_state_0_csrfiles_medeleg_dnxt_T_5 = cmm_state_0_csrExe_op_rc ? _csr_state_0_csrfiles_medeleg_dnxt_T_2
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] csr_state_0_csrfiles_medeleg_dnxt = _csr_state_0_csrfiles_medeleg_dnxt_T_6 |
    _csr_state_0_csrfiles_medeleg_dnxt_T_5; // @[Mux.scala 27:73]
  wire  csr_state_0_csrfiles_mideleg_enable = _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_47 & (
    cmm_state_0_csrExe_op_rw | cmm_state_0_csrExe_op_rs | cmm_state_0_csrExe_op_rc); // @[CsrFiles.scala 42:37]
  wire [63:0] _csr_state_0_csrfiles_mideleg_dnxt_T = csrfiles_mideleg | cmm_state_0_csrExe_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_mideleg_dnxt_T_4 = cmm_state_0_csrExe_op_rs ? _csr_state_0_csrfiles_mideleg_dnxt_T
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_mideleg_dnxt_T_6 = _csr_state_0_csrfiles_mstatus_dnxt_T_3 |
    _csr_state_0_csrfiles_mideleg_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_mideleg_dnxt_T_2 = csrfiles_mideleg & _csr_state_0_csrfiles_mstatus_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] _csr_state_0_csrfiles_mideleg_dnxt_T_5 = cmm_state_0_csrExe_op_rc ? _csr_state_0_csrfiles_mideleg_dnxt_T_2
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] csr_state_0_csrfiles_mideleg_dnxt = _csr_state_0_csrfiles_mideleg_dnxt_T_6 |
    _csr_state_0_csrfiles_mideleg_dnxt_T_5; // @[Mux.scala 27:73]
  wire  csr_state_0_csrfiles_mie_enable0 = _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_48 & (
    cmm_state_0_csrExe_op_rw | cmm_state_0_csrExe_op_rs | cmm_state_0_csrExe_op_rc); // @[CsrFiles.scala 42:37]
  wire [5:0] csr_state_0_csrfiles_mie_lo = {csrfiles_mie_sti,1'h0,csrfiles_mie_msi,1'h0,csrfiles_mie_ssi,1'h0}; // @[CsrFiles.scala 879:58]
  wire [15:0] _csr_state_0_csrfiles_mie_T = {4'h0,csrfiles_mie_mei,1'h0,csrfiles_mie_sei,1'h0,csrfiles_mie_mti,1'h0,
    csr_state_0_csrfiles_mie_lo}; // @[CsrFiles.scala 879:58]
  wire [63:0] _GEN_4 = {{48'd0}, _csr_state_0_csrfiles_mie_T}; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_mie_dnxt_T = _GEN_4 | cmm_state_0_csrExe_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_mie_dnxt_T_4 = cmm_state_0_csrExe_op_rs ? _csr_state_0_csrfiles_mie_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_mie_dnxt_T_6 = _csr_state_0_csrfiles_mstatus_dnxt_T_3 |
    _csr_state_0_csrfiles_mie_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_mie_dnxt_T_2 = _GEN_4 & _csr_state_0_csrfiles_mstatus_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] _csr_state_0_csrfiles_mie_dnxt_T_5 = cmm_state_0_csrExe_op_rc ? _csr_state_0_csrfiles_mie_dnxt_T_2 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] csr_state_0_csrfiles_mie_dnxt0 = _csr_state_0_csrfiles_mie_dnxt_T_6 | _csr_state_0_csrfiles_mie_dnxt_T_5; // @[Mux.scala 27:73]
  wire  csr_state_0_csrfiles_mie_enable1 = _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_9 & (
    cmm_state_0_csrExe_op_rw | cmm_state_0_csrExe_op_rs | cmm_state_0_csrExe_op_rc); // @[CsrFiles.scala 42:37]
  wire  csr_state_0_csrfiles_mcounteren_enable = _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_50 & (
    cmm_state_0_csrExe_op_rw | cmm_state_0_csrExe_op_rs | cmm_state_0_csrExe_op_rc); // @[CsrFiles.scala 42:37]
  wire [63:0] _GEN_10 = {{32'd0}, csrfiles_mcounteren_hpm}; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_mcounteren_dnxt_T = _GEN_10 | cmm_state_0_csrExe_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_mcounteren_dnxt_T_4 = cmm_state_0_csrExe_op_rs ?
    _csr_state_0_csrfiles_mcounteren_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_mcounteren_dnxt_T_6 = _csr_state_0_csrfiles_mstatus_dnxt_T_3 |
    _csr_state_0_csrfiles_mcounteren_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_mcounteren_dnxt_T_2 = _GEN_10 & _csr_state_0_csrfiles_mstatus_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] _csr_state_0_csrfiles_mcounteren_dnxt_T_5 = cmm_state_0_csrExe_op_rc ?
    _csr_state_0_csrfiles_mcounteren_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] csr_state_0_csrfiles_mcounteren_dnxt = _csr_state_0_csrfiles_mcounteren_dnxt_T_6 |
    _csr_state_0_csrfiles_mcounteren_dnxt_T_5; // @[Mux.scala 27:73]
  wire [63:0] _GEN_794 = csr_state_0_csrfiles_mcounteren_enable ? csr_state_0_csrfiles_mcounteren_dnxt : {{32'd0},
    csrfiles_mcounteren_hpm}; // @[CsrFiles.scala 933:{18,35}]
  wire [31:0] csr_state_0_csrfiles_mcounteren_mcounteren_hpm = _GEN_794[31:0];
  wire  csr_state_0_csrfiles_dcsr_enable = _is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_65 & (
    cmm_state_0_csrExe_op_rw | cmm_state_0_csrExe_op_rs | cmm_state_0_csrExe_op_rc); // @[CsrFiles.scala 42:37]
  wire [9:0] csr_state_0_csrfiles_dcsr_lo = {1'h0,csrfiles_dcsr_cause,2'h0,1'h0,csrfiles_dcsr_step,csrfiles_dcsr_prv}; // @[CsrFiles.scala 1794:59]
  wire [31:0] _csr_state_0_csrfiles_dcsr_T = {16'h4000,csrfiles_dcsr_ebreakm,1'h0,csrfiles_dcsr_ebreaks,
    csrfiles_dcsr_ebreaku,2'h0,csr_state_0_csrfiles_dcsr_lo}; // @[CsrFiles.scala 1794:59]
  wire [63:0] _GEN_12 = {{32'd0}, _csr_state_0_csrfiles_dcsr_T}; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_dcsr_dnxt_T = _GEN_12 | cmm_state_0_csrExe_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] _csr_state_0_csrfiles_dcsr_dnxt_T_4 = cmm_state_0_csrExe_op_rs ? _csr_state_0_csrfiles_dcsr_dnxt_T : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_dcsr_dnxt_T_6 = _csr_state_0_csrfiles_mstatus_dnxt_T_3 |
    _csr_state_0_csrfiles_dcsr_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] _csr_state_0_csrfiles_dcsr_dnxt_T_2 = _GEN_12 & _csr_state_0_csrfiles_mstatus_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] _csr_state_0_csrfiles_dcsr_dnxt_T_5 = cmm_state_0_csrExe_op_rc ? _csr_state_0_csrfiles_dcsr_dnxt_T_2 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] csr_state_0_csrfiles_dcsr_dnxt = _csr_state_0_csrfiles_dcsr_dnxt_T_6 | _csr_state_0_csrfiles_dcsr_dnxt_T_5
    ; // @[Mux.scala 27:73]
  wire [2:0] _csr_state_0_csrfiles_dcsr_dcsr_cause_T = is_single_step ? 3'h4 : 3'h0; // @[Mux.scala 101:16]
  wire [2:0] _csr_state_0_csrfiles_dcsr_dcsr_cause_T_1 = io_dm_hartHaltReq ? 3'h3 :
    _csr_state_0_csrfiles_dcsr_dcsr_cause_T; // @[Mux.scala 101:16]
  wire  _GEN_460 = csrfiles_DMode ? 1'h0 : is_single_step; // @[Commit.scala 404:{171,188,31}]
  wire  _mdl_io_deq_0_ready_T = is_retired_0 & io_rod_0_bits_is_branch; // @[Commit.scala 679:36]
  wire  _T_34 = bctq_mdl_io_deq_0_ready & bctq_mdl_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_38 = ~reset; // @[Commit.scala 680:11]
  wire  _T_41 = io_bctq_ready & io_bctq_valid; // @[Decoupled.scala 52:35]
  wire  _mdl_io_deq_0_ready_T_1 = is_retired_0 & io_rod_0_bits_is_jalr; // @[Commit.scala 685:36]
  wire  _T_46 = jctq_mdl_io_deq_0_ready & jctq_mdl_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  _T_53 = io_jctq_ready & io_jctq_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _T_77 = is_xRet + is_trap; // @[Bitwise.scala 51:90]
  wire [1:0] _T_79 = is_fence_i + is_sfence_vma; // @[Bitwise.scala 51:90]
  wire [2:0] _T_81 = _T_77 + _T_79; // @[Bitwise.scala 51:90]
  ReDirect_3 bctq_mdl ( // @[RePort.scala 188:21]
    .io_enq_0_ready(bctq_mdl_io_enq_0_ready),
    .io_enq_0_valid(bctq_mdl_io_enq_0_valid),
    .io_enq_0_bits_isPredictTaken(bctq_mdl_io_enq_0_bits_isPredictTaken),
    .io_enq_0_bits_isFinalTaken(bctq_mdl_io_enq_0_bits_isFinalTaken),
    .io_deq_0_ready(bctq_mdl_io_deq_0_ready),
    .io_deq_0_valid(bctq_mdl_io_deq_0_valid),
    .io_deq_0_bits_isPredictTaken(bctq_mdl_io_deq_0_bits_isPredictTaken),
    .io_deq_0_bits_isFinalTaken(bctq_mdl_io_deq_0_bits_isFinalTaken),
    .io_mapper_0(bctq_mdl_io_mapper_0)
  );
  ReDirect_4 jctq_mdl ( // @[RePort.scala 188:21]
    .io_enq_0_ready(jctq_mdl_io_enq_0_ready),
    .io_enq_0_valid(jctq_mdl_io_enq_0_valid),
    .io_enq_0_bits_btbResp_target(jctq_mdl_io_enq_0_bits_btbResp_target),
    .io_enq_0_bits_rasResp_target(jctq_mdl_io_enq_0_bits_rasResp_target),
    .io_enq_0_bits_isRas(jctq_mdl_io_enq_0_bits_isRas),
    .io_enq_0_bits_finalTarget(jctq_mdl_io_enq_0_bits_finalTarget),
    .io_deq_0_ready(jctq_mdl_io_deq_0_ready),
    .io_deq_0_valid(jctq_mdl_io_deq_0_valid),
    .io_deq_0_bits_btbResp_target(jctq_mdl_io_deq_0_bits_btbResp_target),
    .io_deq_0_bits_rasResp_target(jctq_mdl_io_deq_0_bits_rasResp_target),
    .io_deq_0_bits_isRas(jctq_mdl_io_deq_0_bits_isRas),
    .io_deq_0_bits_finalTarget(jctq_mdl_io_deq_0_bits_finalTarget),
    .io_mapper_0(jctq_mdl_io_mapper_0)
  );
  ReDirect_5 csrExe_mdl ( // @[RePort.scala 188:21]
    .io_enq_0_valid(csrExe_mdl_io_enq_0_valid),
    .io_enq_0_bits_addr(csrExe_mdl_io_enq_0_bits_addr),
    .io_enq_0_bits_dat_i(csrExe_mdl_io_enq_0_bits_dat_i),
    .io_enq_0_bits_op_rw(csrExe_mdl_io_enq_0_bits_op_rw),
    .io_enq_0_bits_op_rs(csrExe_mdl_io_enq_0_bits_op_rs),
    .io_enq_0_bits_op_rc(csrExe_mdl_io_enq_0_bits_op_rc),
    .io_deq_0_ready(csrExe_mdl_io_deq_0_ready),
    .io_deq_0_valid(csrExe_mdl_io_deq_0_valid),
    .io_deq_0_bits_addr(csrExe_mdl_io_deq_0_bits_addr),
    .io_deq_0_bits_dat_i(csrExe_mdl_io_deq_0_bits_dat_i),
    .io_deq_0_bits_op_rw(csrExe_mdl_io_deq_0_bits_op_rw),
    .io_deq_0_bits_op_rs(csrExe_mdl_io_deq_0_bits_op_rs),
    .io_deq_0_bits_op_rc(csrExe_mdl_io_deq_0_bits_op_rc),
    .io_mapper_0(csrExe_mdl_io_mapper_0)
  );
  ReDirect_5 fcsrExe_mdl ( // @[RePort.scala 188:21]
    .io_enq_0_valid(fcsrExe_mdl_io_enq_0_valid),
    .io_enq_0_bits_addr(fcsrExe_mdl_io_enq_0_bits_addr),
    .io_enq_0_bits_dat_i(fcsrExe_mdl_io_enq_0_bits_dat_i),
    .io_enq_0_bits_op_rw(fcsrExe_mdl_io_enq_0_bits_op_rw),
    .io_enq_0_bits_op_rs(fcsrExe_mdl_io_enq_0_bits_op_rs),
    .io_enq_0_bits_op_rc(fcsrExe_mdl_io_enq_0_bits_op_rc),
    .io_deq_0_ready(fcsrExe_mdl_io_deq_0_ready),
    .io_deq_0_valid(fcsrExe_mdl_io_deq_0_valid),
    .io_deq_0_bits_addr(fcsrExe_mdl_io_deq_0_bits_addr),
    .io_deq_0_bits_dat_i(fcsrExe_mdl_io_deq_0_bits_dat_i),
    .io_deq_0_bits_op_rw(fcsrExe_mdl_io_deq_0_bits_op_rw),
    .io_deq_0_bits_op_rs(fcsrExe_mdl_io_deq_0_bits_op_rs),
    .io_deq_0_bits_op_rc(fcsrExe_mdl_io_deq_0_bits_op_rc),
    .io_mapper_0(fcsrExe_mdl_io_mapper_0)
  );
  assign io_bctq_ready = bctq_mdl_io_enq_0_ready; // @[Commit.scala 344:19 RePort.scala 190:9]
  assign io_jctq_ready = jctq_mdl_io_enq_0_ready; // @[Commit.scala 351:19 RePort.scala 190:9]
  assign bctq_mdl_io_enq_0_valid = io_bctq_valid; // @[Commit.scala 344:19 346:12]
  assign bctq_mdl_io_enq_0_bits_isPredictTaken = io_bctq_bits_isPredictTaken; // @[Commit.scala 344:19 346:12]
  assign bctq_mdl_io_enq_0_bits_isFinalTaken = io_bctq_bits_isFinalTaken; // @[Commit.scala 344:19 346:12]
  assign bctq_mdl_io_deq_0_ready = is_retired_0 & io_rod_0_bits_is_branch; // @[Commit.scala 679:36]
  assign bctq_mdl_io_mapper_0 = io_rod_0_bits_is_branch; // @[Commit.scala 357:{42,42}]
  assign jctq_mdl_io_enq_0_valid = io_jctq_valid; // @[Commit.scala 351:19 353:12]
  assign jctq_mdl_io_enq_0_bits_btbResp_target = io_jctq_bits_btbResp_target; // @[Commit.scala 351:19 353:12]
  assign jctq_mdl_io_enq_0_bits_rasResp_target = io_jctq_bits_rasResp_target; // @[Commit.scala 351:19 353:12]
  assign jctq_mdl_io_enq_0_bits_isRas = io_jctq_bits_isRas; // @[Commit.scala 351:19 353:12]
  assign jctq_mdl_io_enq_0_bits_finalTarget = io_jctq_bits_finalTarget; // @[Commit.scala 351:19 353:12]
  assign jctq_mdl_io_deq_0_ready = is_retired_0 & io_rod_0_bits_is_jalr; // @[Commit.scala 685:36]
  assign jctq_mdl_io_mapper_0 = io_rod_0_bits_is_jalr; // @[Commit.scala 358:{42,42}]
  assign csrExe_mdl_io_enq_0_valid = io_csr_cmm_op_valid; // @[Commit.scala 337:19 339:12]
  assign csrExe_mdl_io_enq_0_bits_addr = io_csr_cmm_op_bits_addr; // @[Commit.scala 337:19 339:12]
  assign csrExe_mdl_io_enq_0_bits_dat_i = io_csr_cmm_op_bits_dat_i; // @[Commit.scala 337:19 339:12]
  assign csrExe_mdl_io_enq_0_bits_op_rw = io_csr_cmm_op_bits_op_rw; // @[Commit.scala 337:19 339:12]
  assign csrExe_mdl_io_enq_0_bits_op_rs = io_csr_cmm_op_bits_op_rs; // @[Commit.scala 337:19 339:12]
  assign csrExe_mdl_io_enq_0_bits_op_rc = io_csr_cmm_op_bits_op_rc; // @[Commit.scala 337:19 339:12]
  assign csrExe_mdl_io_deq_0_ready = commit_state_is_comfirm_0 & io_rod_0_bits_is_csr; // @[Commit.scala 802:51]
  assign csrExe_mdl_io_mapper_0 = io_rod_0_bits_is_csr; // @[Commit.scala 360:{48,48}]
  assign fcsrExe_mdl_io_enq_0_valid = io_fcsr_cmm_op_0_valid; // @[RePort.scala 190:9]
  assign fcsrExe_mdl_io_enq_0_bits_addr = io_fcsr_cmm_op_0_bits_addr; // @[RePort.scala 190:9]
  assign fcsrExe_mdl_io_enq_0_bits_dat_i = io_fcsr_cmm_op_0_bits_dat_i; // @[RePort.scala 190:9]
  assign fcsrExe_mdl_io_enq_0_bits_op_rw = io_fcsr_cmm_op_0_bits_op_rw; // @[RePort.scala 190:9]
  assign fcsrExe_mdl_io_enq_0_bits_op_rs = io_fcsr_cmm_op_0_bits_op_rs; // @[RePort.scala 190:9]
  assign fcsrExe_mdl_io_enq_0_bits_op_rc = io_fcsr_cmm_op_0_bits_op_rc; // @[RePort.scala 190:9]
  assign fcsrExe_mdl_io_deq_0_ready = commit_state_is_comfirm_0 & io_rod_0_bits_is_fcsr; // @[Commit.scala 812:34]
  assign fcsrExe_mdl_io_mapper_0 = io_rod_0_bits_is_fcsr; // @[Commit.scala 361:{50,50}]
  always @(posedge clock) begin
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_priv_lvl <= 2'h3; // @[Commit.scala 449:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csrfiles_DMode) begin // @[CsrFiles.scala 709:31]
        if (is_xRet_is_dRet) begin // @[CsrFiles.scala 710:24]
          csrfiles_priv_lvl <= csrfiles_dcsr_prv; // @[CsrFiles.scala 710:35]
        end else begin
          csrfiles_priv_lvl <= _GEN_469;
        end
      end else if (is_trap_is_exception_is_store_pagingFault) begin // @[CsrFiles.scala 736:41]
        csrfiles_priv_lvl <= _csr_state_0_csrfiles_priv_lvl_priv_lvl_T_75; // @[CsrFiles.scala 736:52]
      end else begin
        csrfiles_priv_lvl <= _GEN_491;
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_DMode <= 1'h0; // @[Commit.scala 450:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_DMode <= csr_state_0_csrfiles_DMode_DMode; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_sd <= 1'h0; // @[Commit.scala 487:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_mstatus_sd <= csr_state_0_csrfiles_mstatus_mstatus_sd; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_tsr <= 1'h0; // @[Commit.scala 472:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 758:45]
        if (!(is_xRet_is_mRet & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 770:50]
          csrfiles_mstatus_tsr <= _GEN_749;
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_tw <= 1'h0; // @[Commit.scala 473:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 758:45]
        if (!(is_xRet_is_mRet & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 770:50]
          csrfiles_mstatus_tw <= _GEN_750;
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_tvm <= 1'h0; // @[Commit.scala 474:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 758:45]
        if (!(is_xRet_is_mRet & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 770:50]
          csrfiles_mstatus_tvm <= _GEN_751;
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_mxr <= 1'h0; // @[Commit.scala 475:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 758:45]
        if (!(is_xRet_is_mRet & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 770:50]
          csrfiles_mstatus_mxr <= _GEN_745;
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_sum <= 1'h0; // @[Commit.scala 476:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 758:45]
        if (!(is_xRet_is_mRet & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 770:50]
          csrfiles_mstatus_sum <= _GEN_746;
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_mprv <= 1'h0; // @[Commit.scala 477:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 758:45]
        if (is_xRet_is_mRet & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 770:50]
          csrfiles_mstatus_mprv <= _csr_state_0_csrfiles_mstatus_mstatus_mprv_T_8; // @[CsrFiles.scala 775:20]
        end else begin
          csrfiles_mstatus_mprv <= _GEN_744;
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_fs <= 2'h0; // @[Commit.scala 479:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_mstatus_is_fpu_state_change & csrfiles_mstatus_fs != 2'h0) begin // @[CsrFiles.scala 808:67]
        csrfiles_mstatus_fs <= 2'h3; // @[CsrFiles.scala 809:18]
      end else if (!(is_trap & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 758:45]
        csrfiles_mstatus_fs <= _GEN_763;
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_mpp <= 2'h3; // @[Commit.scala 480:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (is_trap & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 758:45]
        if (csr_state_0_csrfiles_priv_lvl_priv_lvl == 2'h3) begin // @[CsrFiles.scala 759:47]
          csrfiles_mstatus_mpp <= csrfiles_priv_lvl; // @[CsrFiles.scala 762:22]
        end
      end else if (is_xRet_is_mRet & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 770:50]
        csrfiles_mstatus_mpp <= 2'h0; // @[CsrFiles.scala 773:20]
      end else begin
        csrfiles_mstatus_mpp <= _GEN_752;
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_spp <= 1'h0; // @[Commit.scala 481:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (is_trap & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 758:45]
        if (csr_state_0_csrfiles_priv_lvl_priv_lvl == 2'h1) begin // @[CsrFiles.scala 764:47]
          csrfiles_mstatus_spp <= _csr_state_0_csrfiles_mstatus_mstatus_spp_T_1; // @[CsrFiles.scala 765:22]
        end
      end else if (!(is_xRet_is_mRet & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 770:50]
        csrfiles_mstatus_spp <= _GEN_748;
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_mpie <= 1'h0; // @[Commit.scala 482:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (is_trap & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 758:45]
        if (csr_state_0_csrfiles_priv_lvl_priv_lvl == 2'h3) begin // @[CsrFiles.scala 759:47]
          csrfiles_mstatus_mpie <= csrfiles_mstatus_mie; // @[CsrFiles.scala 760:22]
        end
      end else begin
        csrfiles_mstatus_mpie <= _GEN_756;
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_spie <= 1'h0; // @[Commit.scala 484:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (is_trap & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 758:45]
        if (csr_state_0_csrfiles_priv_lvl_priv_lvl == 2'h1) begin // @[CsrFiles.scala 764:47]
          csrfiles_mstatus_spie <= csrfiles_mstatus_sie; // @[CsrFiles.scala 766:22]
        end
      end else if (!(is_xRet_is_mRet & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 770:50]
        csrfiles_mstatus_spie <= _GEN_742;
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_mie <= 1'h0; // @[Commit.scala 485:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (is_trap & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 758:45]
        if (csr_state_0_csrfiles_priv_lvl_priv_lvl == 2'h3) begin // @[CsrFiles.scala 759:47]
          csrfiles_mstatus_mie <= 1'h0; // @[CsrFiles.scala 761:22]
        end
      end else if (is_xRet_is_mRet & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 770:50]
        csrfiles_mstatus_mie <= csrfiles_mstatus_mpie; // @[CsrFiles.scala 771:20]
      end else begin
        csrfiles_mstatus_mie <= _GEN_754;
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mstatus_sie <= 1'h0; // @[Commit.scala 486:27]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (is_trap & _is_trap_is_interrupt_T_2) begin // @[CsrFiles.scala 758:45]
        if (csr_state_0_csrfiles_priv_lvl_priv_lvl == 2'h1) begin // @[CsrFiles.scala 764:47]
          csrfiles_mstatus_sie <= 1'h0; // @[CsrFiles.scala 767:22]
        end
      end else if (!(is_xRet_is_mRet & _is_trap_is_interrupt_T_2)) begin // @[CsrFiles.scala 770:50]
        csrfiles_mstatus_sie <= _GEN_743;
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_medeleg <= 64'h0; // @[Commit.scala 490:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_medeleg_enable) begin // @[CsrFiles.scala 850:18]
        csrfiles_medeleg <= csr_state_0_csrfiles_medeleg_dnxt; // @[CsrFiles.scala 850:28]
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mideleg <= 64'h0; // @[Commit.scala 491:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_mideleg_enable) begin // @[CsrFiles.scala 862:18]
        csrfiles_mideleg <= csr_state_0_csrfiles_mideleg_dnxt; // @[CsrFiles.scala 862:28]
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mie_mei <= 1'h0; // @[Commit.scala 492:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        csrfiles_mie_mei <= csr_state_0_csrfiles_mie_dnxt0[11]; // @[CsrFiles.scala 883:15]
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mie_sei <= 1'h0; // @[Commit.scala 492:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        csrfiles_mie_sei <= csr_state_0_csrfiles_mie_dnxt0[9]; // @[CsrFiles.scala 884:15]
      end else if (csr_state_0_csrfiles_mie_enable1) begin // @[CsrFiles.scala 890:24]
        csrfiles_mie_sei <= csr_state_0_csrfiles_mie_dnxt0[9]; // @[CsrFiles.scala 891:15]
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mie_mti <= 1'h0; // @[Commit.scala 492:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        csrfiles_mie_mti <= csr_state_0_csrfiles_mie_dnxt0[7]; // @[CsrFiles.scala 885:15]
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mie_sti <= 1'h0; // @[Commit.scala 492:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        csrfiles_mie_sti <= csr_state_0_csrfiles_mie_dnxt0[5]; // @[CsrFiles.scala 886:15]
      end else if (csr_state_0_csrfiles_mie_enable1) begin // @[CsrFiles.scala 890:24]
        csrfiles_mie_sti <= csr_state_0_csrfiles_mie_dnxt0[5]; // @[CsrFiles.scala 892:15]
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mie_msi <= 1'h0; // @[Commit.scala 492:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        csrfiles_mie_msi <= csr_state_0_csrfiles_mie_dnxt0[3]; // @[CsrFiles.scala 887:15]
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mie_ssi <= 1'h0; // @[Commit.scala 492:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        csrfiles_mie_ssi <= csr_state_0_csrfiles_mie_dnxt0[1]; // @[CsrFiles.scala 888:15]
      end else if (csr_state_0_csrfiles_mie_enable1) begin // @[CsrFiles.scala 890:24]
        csrfiles_mie_ssi <= csr_state_0_csrfiles_mie_dnxt0[1]; // @[CsrFiles.scala 893:15]
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mcounteren_hpm <= 32'h0; // @[Commit.scala 494:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_mcounteren_hpm <= csr_state_0_csrfiles_mcounteren_mcounteren_hpm; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mip_mei <= 1'h0; // @[Commit.scala 499:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_mip_mei <= io_plic_mei; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mip_sei <= 1'h0; // @[Commit.scala 499:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_mip_sei <= io_plic_sei; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mip_mti <= 1'h0; // @[Commit.scala 499:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_mip_mti <= io_aclint_mti; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mip_sti <= 1'h0; // @[Commit.scala 499:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_mip_sti <= io_aclint_sti; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mip_msi <= 1'h0; // @[Commit.scala 499:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_mip_msi <= io_aclint_msi; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_mip_ssi <= 1'h0; // @[Commit.scala 499:28]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      csrfiles_mip_ssi <= io_aclint_ssi; // @[Commit.scala 398:100]
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_dcsr_ebreakm <= 1'h0; // @[Commit.scala 511:29]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt)) begin // @[CsrFiles.scala 1796:41]
        if (csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
          csrfiles_dcsr_ebreakm <= csr_state_0_csrfiles_dcsr_dnxt[15]; // @[CsrFiles.scala 1809:24]
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_dcsr_ebreaks <= 1'h0; // @[Commit.scala 512:29]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt)) begin // @[CsrFiles.scala 1796:41]
        if (csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
          csrfiles_dcsr_ebreaks <= csr_state_0_csrfiles_dcsr_dnxt[13]; // @[CsrFiles.scala 1810:24]
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_dcsr_ebreaku <= 1'h0; // @[Commit.scala 513:29]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt)) begin // @[CsrFiles.scala 1796:41]
        if (csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
          csrfiles_dcsr_ebreaku <= csr_state_0_csrfiles_dcsr_dnxt[12]; // @[CsrFiles.scala 1811:24]
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_dcsr_cause <= 3'h0; // @[Commit.scala 517:29]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt) begin // @[CsrFiles.scala 1796:41]
        if (is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm) begin // @[Mux.scala 101:16]
          csrfiles_dcsr_cause <= 3'h1;
        end else begin
          csrfiles_dcsr_cause <= _csr_state_0_csrfiles_dcsr_dcsr_cause_T_1;
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_dcsr_step <= 1'h0; // @[Commit.scala 520:29]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (!(is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt)) begin // @[CsrFiles.scala 1796:41]
        if (csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
          csrfiles_dcsr_step <= csr_state_0_csrfiles_dcsr_dnxt[2]; // @[CsrFiles.scala 1812:19]
        end
      end
    end
    if (reset) begin // @[Commit.scala 399:24]
      csrfiles_dcsr_prv <= 2'h3; // @[Commit.scala 521:29]
    end else if (is_retired_0 | commit_state_is_abort_0) begin // @[Commit.scala 398:89]
      if (is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt) begin // @[CsrFiles.scala 1796:41]
        csrfiles_dcsr_prv <= csrfiles_priv_lvl; // @[CsrFiles.scala 1797:18]
      end else if (csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
        csrfiles_dcsr_prv <= csr_state_0_csrfiles_dcsr_dnxt[1:0]; // @[CsrFiles.scala 1813:19]
      end
    end
    if (reset) begin // @[Commit.scala 404:31]
      is_single_step <= 1'h0; // @[Commit.scala 404:31]
    end else begin
      is_single_step <= _T_1 & is_step_1 | _GEN_460;
    end
    if (reset) begin // @[Commit.scala 363:26]
      emu_reset <= 1'h0; // @[Commit.scala 363:26]
    end else begin
      emu_reset <= _GEN_1;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_34 == _mdl_io_deq_0_ready_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:680 assert( bctq(i).fire === (is_retired(i) & io.rod(i).bits.is_branch) )\n"
            ); // @[Commit.scala 680:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_34 == _mdl_io_deq_0_ready_T) & ~reset) begin
          $fatal; // @[Commit.scala 680:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_38 & ~(_T_34 == _T_41)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:681 assert( bctq.map{_.fire}.reduce(_|_) === io.bctq.fire )\n"); // @[Commit.scala 681:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_34 == _T_41) & _T_38) begin
          $fatal; // @[Commit.scala 681:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_38 & ~(_T_46 == _mdl_io_deq_0_ready_T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:686 assert( jctq(i).fire === (is_retired(i) & io.rod(i).bits.is_jalr) )\n"
            ); // @[Commit.scala 686:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_46 == _mdl_io_deq_0_ready_T_1) & _T_38) begin
          $fatal; // @[Commit.scala 686:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_38 & ~(_T_46 == _T_53)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:687 assert( jctq.map{_.fire}.reduce(_|_) === io.jctq.fire )\n"); // @[Commit.scala 687:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_46 == _T_53) & _T_38) begin
          $fatal; // @[Commit.scala 687:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (commit_state_is_abort_0 & csrfiles_DMode & is_trap_is_interrupt & _T_38) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, All interrupts (including NMI) are masked in Dmode! Page-39\n    at Commit.scala:730 assert(false.B, \"Assert Failed, All interrupts (including NMI) are masked in Dmode! Page-39\")\n"
            ); // @[Commit.scala 730:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (commit_state_is_abort_0 & csrfiles_DMode & is_trap_is_interrupt & _T_38)) begin
          $fatal; // @[Commit.scala 730:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (commit_state_is_abort_0 & _is_trap_is_interrupt_T_2 & _T_38 & ~(_T_81 <= 3'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:768 assert( PopCount(Seq( cmm_state(i).is_xRet, cmm_state(i).is_trap, cmm_state(i).is_fence_i, cmm_state(i).is_sfence_vma)) <= 1.U )\n"
            ); // @[Commit.scala 768:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_81 <= 3'h1) & (commit_state_is_abort_0 & _is_trap_is_interrupt_T_2 & _T_38)) begin
          $fatal; // @[Commit.scala 768:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_38 & ~(~(csrExe_mdl_io_deq_0_ready & _T_23))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:803 assert( ~(csrExe(i).ready & ~csrExe(i).valid) )\n"); // @[Commit.scala 803:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(csrExe_mdl_io_deq_0_ready & _T_23)) & _T_38) begin
          $fatal; // @[Commit.scala 803:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_38 & ~(~(fcsrExe_mdl_io_deq_0_ready & _T_25))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:814 assert( ~(fcsrExe(i).ready & ~fcsrExe(i).valid) )\n"); // @[Commit.scala 814:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(fcsrExe_mdl_io_deq_0_ready & _T_25)) & _T_38) begin
          $fatal; // @[Commit.scala 814:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  csrfiles_priv_lvl = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  csrfiles_DMode = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  csrfiles_mstatus_sd = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  csrfiles_mstatus_tsr = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  csrfiles_mstatus_tw = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  csrfiles_mstatus_tvm = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  csrfiles_mstatus_mxr = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  csrfiles_mstatus_sum = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  csrfiles_mstatus_mprv = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  csrfiles_mstatus_fs = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  csrfiles_mstatus_mpp = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  csrfiles_mstatus_spp = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  csrfiles_mstatus_mpie = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  csrfiles_mstatus_spie = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  csrfiles_mstatus_mie = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  csrfiles_mstatus_sie = _RAND_15[0:0];
  _RAND_16 = {2{`RANDOM}};
  csrfiles_medeleg = _RAND_16[63:0];
  _RAND_17 = {2{`RANDOM}};
  csrfiles_mideleg = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  csrfiles_mie_mei = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  csrfiles_mie_sei = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  csrfiles_mie_mti = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  csrfiles_mie_sti = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  csrfiles_mie_msi = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  csrfiles_mie_ssi = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  csrfiles_mcounteren_hpm = _RAND_24[31:0];
  _RAND_25 = {1{`RANDOM}};
  csrfiles_mip_mei = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  csrfiles_mip_sei = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  csrfiles_mip_mti = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  csrfiles_mip_sti = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  csrfiles_mip_msi = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  csrfiles_mip_ssi = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  csrfiles_dcsr_ebreakm = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  csrfiles_dcsr_ebreaks = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  csrfiles_dcsr_ebreaku = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  csrfiles_dcsr_cause = _RAND_34[2:0];
  _RAND_35 = {1{`RANDOM}};
  csrfiles_dcsr_step = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  csrfiles_dcsr_prv = _RAND_36[1:0];
  _RAND_37 = {1{`RANDOM}};
  is_single_step = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  emu_reset = _RAND_38[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MaxPeriodFibonacciLFSR(
  input   clock,
  input   reset,
  output  io_out_0,
  output  io_out_1
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg  state_0; // @[PRNG.scala 55:49]
  reg  state_1; // @[PRNG.scala 55:49]
  wire  _T = state_1 ^ state_0; // @[LFSR.scala 15:41]
  assign io_out_0 = state_0; // @[PRNG.scala 78:10]
  assign io_out_1 = state_1; // @[PRNG.scala 78:10]
  always @(posedge clock) begin
    state_0 <= reset | _T; // @[PRNG.scala 55:{49,49}]
    if (reset) begin // @[PRNG.scala 55:49]
      state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      state_1 <= state_0;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  state_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLB(
  input         clock,
  input         reset,
  input         io_req_valid,
  input  [63:0] io_req_bits_vaddr,
  output        io_is_hit,
  input  [15:0] io_asid_i,
  input         io_tlb_renew_valid,
  input         io_tlb_renew_bits_is_giga_page,
  input         io_tlb_renew_bits_is_mega_page,
  input  [15:0] io_tlb_renew_bits_asid,
  input  [8:0]  io_tlb_renew_bits_vpn_0,
  input  [8:0]  io_tlb_renew_bits_vpn_1,
  input  [8:0]  io_tlb_renew_bits_vpn_2,
  input         io_sfence_vma
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
`endif // RANDOMIZE_REG_INIT
  wire  random_idx_prng_clock; // @[PRNG.scala 91:22]
  wire  random_idx_prng_reset; // @[PRNG.scala 91:22]
  wire  random_idx_prng_io_out_0; // @[PRNG.scala 91:22]
  wire  random_idx_prng_io_out_1; // @[PRNG.scala 91:22]
  wire  random_idx_prng_1_clock; // @[PRNG.scala 91:22]
  wire  random_idx_prng_1_reset; // @[PRNG.scala 91:22]
  wire  random_idx_prng_1_io_out_0; // @[PRNG.scala 91:22]
  wire  random_idx_prng_1_io_out_1; // @[PRNG.scala 91:22]
  wire  random_idx_prng_2_clock; // @[PRNG.scala 91:22]
  wire  random_idx_prng_2_reset; // @[PRNG.scala 91:22]
  wire  random_idx_prng_2_io_out_0; // @[PRNG.scala 91:22]
  wire  random_idx_prng_2_io_out_1; // @[PRNG.scala 91:22]
  wire  random_idx_prng_3_clock; // @[PRNG.scala 91:22]
  wire  random_idx_prng_3_reset; // @[PRNG.scala 91:22]
  wire  random_idx_prng_3_io_out_0; // @[PRNG.scala 91:22]
  wire  random_idx_prng_3_io_out_1; // @[PRNG.scala 91:22]
  reg  tag_0_is_valid; // @[TLB.scala 59:20]
  reg [15:0] tag_0_asid; // @[TLB.scala 59:20]
  reg [8:0] tag_0_vpn_0; // @[TLB.scala 59:20]
  reg [8:0] tag_0_vpn_1; // @[TLB.scala 59:20]
  reg [8:0] tag_0_vpn_2; // @[TLB.scala 59:20]
  reg  tag_1_is_valid; // @[TLB.scala 59:20]
  reg [15:0] tag_1_asid; // @[TLB.scala 59:20]
  reg [8:0] tag_1_vpn_0; // @[TLB.scala 59:20]
  reg [8:0] tag_1_vpn_1; // @[TLB.scala 59:20]
  reg [8:0] tag_1_vpn_2; // @[TLB.scala 59:20]
  reg  pte_0_is_giga_page; // @[TLB.scala 62:20]
  reg  pte_0_is_mega_page; // @[TLB.scala 62:20]
  reg  pte_1_is_giga_page; // @[TLB.scala 62:20]
  reg  pte_1_is_mega_page; // @[TLB.scala 62:20]
  wire  is_runout = tag_0_is_valid & tag_1_is_valid; // @[TLB.scala 85:31]
  wire [1:0] random_idx = {random_idx_prng_io_out_1,random_idx_prng_io_out_0}; // @[PRNG.scala 95:17]
  wire  empty_idx = ~tag_0_is_valid ? 1'h0 : 1'h1; // @[TLB.scala 88:36]
  wire [1:0] _T = is_runout ? random_idx : {{1'd0}, empty_idx}; // @[TLB.scala 90:15]
  wire  _GEN_0 = ~_T[0] | tag_0_is_valid; // @[TLB.scala 59:20 68:{34,34}]
  wire  _GEN_1 = _T[0] | tag_1_is_valid; // @[TLB.scala 59:20 68:{34,34}]
  wire [1:0] random_idx_1 = {random_idx_prng_1_io_out_1,random_idx_prng_1_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] _T_2 = is_runout ? random_idx_1 : {{1'd0}, empty_idx}; // @[TLB.scala 90:15]
  wire [1:0] random_idx_2 = {random_idx_prng_2_io_out_1,random_idx_prng_2_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] _T_4 = is_runout ? random_idx_2 : {{1'd0}, empty_idx}; // @[TLB.scala 90:15]
  wire [1:0] random_idx_3 = {random_idx_prng_3_io_out_1,random_idx_prng_3_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] _T_6 = is_runout ? random_idx_3 : {{1'd0}, empty_idx}; // @[TLB.scala 90:15]
  wire  tlb_hit_lvl2 = tag_0_is_valid & io_asid_i == tag_0_asid & io_req_bits_vaddr[38:30] == tag_0_vpn_2; // @[TLB.scala 102:62]
  wire  tlb_hit_lvl1 = io_req_bits_vaddr[29:21] == tag_0_vpn_1; // @[TLB.scala 103:43]
  wire  tlb_hit_lvl0 = io_req_bits_vaddr[20:12] == tag_0_vpn_0; // @[TLB.scala 104:43]
  wire  tlb_hit_0 = tlb_hit_lvl2 & (pte_0_is_giga_page | tlb_hit_lvl1 & (pte_0_is_mega_page | tlb_hit_lvl0)); // @[TLB.scala 106:12]
  wire  tlb_hit_lvl2_1 = tag_1_is_valid & io_asid_i == tag_1_asid & io_req_bits_vaddr[38:30] == tag_1_vpn_2; // @[TLB.scala 102:62]
  wire  tlb_hit_lvl1_1 = io_req_bits_vaddr[29:21] == tag_1_vpn_1; // @[TLB.scala 103:43]
  wire  tlb_hit_lvl0_1 = io_req_bits_vaddr[20:12] == tag_1_vpn_0; // @[TLB.scala 104:43]
  wire  tlb_hit_1 = tlb_hit_lvl2_1 & (pte_1_is_giga_page | tlb_hit_lvl1_1 & (pte_1_is_mega_page | tlb_hit_lvl0_1)); // @[TLB.scala 106:12]
  wire [1:0] _T_8 = {tlb_hit_1,tlb_hit_0}; // @[TLB.scala 110:29]
  wire [1:0] _T_11 = _T_8[0] + _T_8[1]; // @[Bitwise.scala 51:90]
  MaxPeriodFibonacciLFSR random_idx_prng ( // @[PRNG.scala 91:22]
    .clock(random_idx_prng_clock),
    .reset(random_idx_prng_reset),
    .io_out_0(random_idx_prng_io_out_0),
    .io_out_1(random_idx_prng_io_out_1)
  );
  MaxPeriodFibonacciLFSR random_idx_prng_1 ( // @[PRNG.scala 91:22]
    .clock(random_idx_prng_1_clock),
    .reset(random_idx_prng_1_reset),
    .io_out_0(random_idx_prng_1_io_out_0),
    .io_out_1(random_idx_prng_1_io_out_1)
  );
  MaxPeriodFibonacciLFSR random_idx_prng_2 ( // @[PRNG.scala 91:22]
    .clock(random_idx_prng_2_clock),
    .reset(random_idx_prng_2_reset),
    .io_out_0(random_idx_prng_2_io_out_0),
    .io_out_1(random_idx_prng_2_io_out_1)
  );
  MaxPeriodFibonacciLFSR random_idx_prng_3 ( // @[PRNG.scala 91:22]
    .clock(random_idx_prng_3_clock),
    .reset(random_idx_prng_3_reset),
    .io_out_0(random_idx_prng_3_io_out_0),
    .io_out_1(random_idx_prng_3_io_out_1)
  );
  assign io_is_hit = (tlb_hit_0 | tlb_hit_1) & io_req_valid; // @[TLB.scala 113:41]
  assign random_idx_prng_clock = clock;
  assign random_idx_prng_reset = reset;
  assign random_idx_prng_1_clock = clock;
  assign random_idx_prng_1_reset = reset;
  assign random_idx_prng_2_clock = clock;
  assign random_idx_prng_2_reset = reset;
  assign random_idx_prng_3_clock = clock;
  assign random_idx_prng_3_reset = reset;
  always @(posedge clock) begin
    if (reset) begin // @[TLB.scala 59:20]
      tag_0_is_valid <= 1'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_0_is_valid <= 1'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      tag_0_is_valid <= _GEN_0;
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_0_asid <= 16'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_0_asid <= 16'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~_T_2[0]) begin // @[TLB.scala 69:32]
        tag_0_asid <= io_tlb_renew_bits_asid; // @[TLB.scala 69:32]
      end
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_0_vpn_0 <= 9'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_0_vpn_0 <= 9'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~_T_4[0]) begin // @[TLB.scala 70:32]
        tag_0_vpn_0 <= io_tlb_renew_bits_vpn_0; // @[TLB.scala 70:32]
      end
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_0_vpn_1 <= 9'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_0_vpn_1 <= 9'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~_T_4[0]) begin // @[TLB.scala 70:32]
        tag_0_vpn_1 <= io_tlb_renew_bits_vpn_1; // @[TLB.scala 70:32]
      end
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_0_vpn_2 <= 9'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_0_vpn_2 <= 9'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~_T_4[0]) begin // @[TLB.scala 70:32]
        tag_0_vpn_2 <= io_tlb_renew_bits_vpn_2; // @[TLB.scala 70:32]
      end
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_1_is_valid <= 1'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_1_is_valid <= 1'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      tag_1_is_valid <= _GEN_1;
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_1_asid <= 16'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_1_asid <= 16'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (_T_2[0]) begin // @[TLB.scala 69:32]
        tag_1_asid <= io_tlb_renew_bits_asid; // @[TLB.scala 69:32]
      end
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_1_vpn_0 <= 9'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_1_vpn_0 <= 9'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (_T_4[0]) begin // @[TLB.scala 70:32]
        tag_1_vpn_0 <= io_tlb_renew_bits_vpn_0; // @[TLB.scala 70:32]
      end
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_1_vpn_1 <= 9'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_1_vpn_1 <= 9'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (_T_4[0]) begin // @[TLB.scala 70:32]
        tag_1_vpn_1 <= io_tlb_renew_bits_vpn_1; // @[TLB.scala 70:32]
      end
    end
    if (reset) begin // @[TLB.scala 59:20]
      tag_1_vpn_2 <= 9'h0; // @[TLB.scala 59:20]
    end else if (io_sfence_vma) begin // @[TLB.scala 64:25]
      tag_1_vpn_2 <= 9'h0; // @[TLB.scala 65:47]
    end else if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (_T_4[0]) begin // @[TLB.scala 70:32]
        tag_1_vpn_2 <= io_tlb_renew_bits_vpn_2; // @[TLB.scala 70:32]
      end
    end
    if (reset) begin // @[TLB.scala 62:20]
      pte_0_is_giga_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (~_T_6[0]) begin // @[TLB.scala 71:32]
          pte_0_is_giga_page <= io_tlb_renew_bits_is_giga_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (reset) begin // @[TLB.scala 62:20]
      pte_0_is_mega_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (~_T_6[0]) begin // @[TLB.scala 71:32]
          pte_0_is_mega_page <= io_tlb_renew_bits_is_mega_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (reset) begin // @[TLB.scala 62:20]
      pte_1_is_giga_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (_T_6[0]) begin // @[TLB.scala 71:32]
          pte_1_is_giga_page <= io_tlb_renew_bits_is_giga_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (reset) begin // @[TLB.scala 62:20]
      pte_1_is_mega_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (_T_6[0]) begin // @[TLB.scala 71:32]
          pte_1_is_mega_page <= io_tlb_renew_bits_is_mega_page; // @[TLB.scala 71:32]
        end
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_11 <= 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail at tlb, more than 1 entry hit!\n    at TLB.scala:110 assert( PopCount( tlb_hit.asUInt ) <= 1.U, \"Assert Fail at tlb, more than 1 entry hit!\"  )\n"
            ); // @[TLB.scala 110:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_11 <= 2'h1) & ~reset) begin
          $fatal; // @[TLB.scala 110:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  tag_0_is_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  tag_0_asid = _RAND_1[15:0];
  _RAND_2 = {1{`RANDOM}};
  tag_0_vpn_0 = _RAND_2[8:0];
  _RAND_3 = {1{`RANDOM}};
  tag_0_vpn_1 = _RAND_3[8:0];
  _RAND_4 = {1{`RANDOM}};
  tag_0_vpn_2 = _RAND_4[8:0];
  _RAND_5 = {1{`RANDOM}};
  tag_1_is_valid = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  tag_1_asid = _RAND_6[15:0];
  _RAND_7 = {1{`RANDOM}};
  tag_1_vpn_0 = _RAND_7[8:0];
  _RAND_8 = {1{`RANDOM}};
  tag_1_vpn_1 = _RAND_8[8:0];
  _RAND_9 = {1{`RANDOM}};
  tag_1_vpn_2 = _RAND_9[8:0];
  _RAND_10 = {1{`RANDOM}};
  pte_0_is_giga_page = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  pte_0_is_mega_page = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  pte_1_is_giga_page = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  pte_1_is_mega_page = _RAND_13[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module PTW(
  input         clock,
  input         reset,
  output        io_ptw_i_ready,
  input         io_ptw_i_valid,
  input         io_ptw_i_bits_is_X,
  input  [63:0] io_ptw_i_bits_vaddr,
  input         io_ptw_o_ready,
  output        io_ptw_o_valid,
  output        io_ptw_o_bits_is_X,
  output        io_ptw_o_bits_renew_is_giga_page,
  output        io_ptw_o_bits_renew_is_mega_page,
  output [15:0] io_ptw_o_bits_renew_asid,
  output [8:0]  io_ptw_o_bits_renew_vpn_0,
  output [8:0]  io_ptw_o_bits_renew_vpn_1,
  output [8:0]  io_ptw_o_bits_renew_vpn_2,
  output        io_ptw_o_bits_is_ptw_fail,
  input  [63:0] io_cmm_mmu_satp,
  input         io_cmm_mmu_sfence_vma,
  output        io_ptw_access_ready,
  input         io_ptw_access_valid,
  input  [2:0]  io_ptw_access_bits_opcode,
  input  [2:0]  io_ptw_access_bits_size,
  input  [63:0] io_ptw_access_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [63:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] currState; // @[PTW.scala 87:26]
  reg  kill_trans; // @[PTW.scala 89:27]
  wire  _T = io_ptw_access_ready & io_ptw_access_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _beats1_decode_T_1 = 11'hf << io_ptw_access_bits_size; // @[package.scala 234:77]
  wire [3:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  beats1_decode = _beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  beats1_opdata = io_ptw_access_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  beats1 = beats1_opdata & beats1_decode; // @[Edges.scala 220:14]
  reg  counter; // @[Edges.scala 228:27]
  wire  counter1 = counter - 1'h1; // @[Edges.scala 229:28]
  wire  first = ~counter; // @[Edges.scala 230:25]
  wire  last = counter | ~beats1; // @[Edges.scala 231:37]
  wire  is_trans_done = last & _T; // @[Edges.scala 232:22]
  reg [31:0] addr_qout; // @[PTW.scala 95:26]
  wire  _walkReq_T = currState == 2'h0; // @[PTW.scala 102:63]
  wire  _nextState_T = io_ptw_i_ready & io_ptw_i_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _nextState_T_1 = _nextState_T ? 2'h1 : 2'h0; // @[PTW.scala 112:23]
  reg [63:0] ptw_access_data_lo_0; // @[PTW.scala 218:31]
  wire [127:0] ptw_access_data = {io_ptw_access_bits_data,ptw_access_data_lo_0}; // @[Cat.scala 33:92]
  wire [127:0] pte_value_data = is_trans_done ? ptw_access_data : 128'h0; // @[PTW.scala 226:27 227:12]
  wire [6:0] _pte_value_data_sel_T_1 = {addr_qout[3], 6'h0}; // @[PTW.scala 231:54]
  wire [127:0] _pte_value_data_sel_T_2 = pte_value_data >> _pte_value_data_sel_T_1; // @[PTW.scala 230:22]
  wire [63:0] pte_value_data_sel = _pte_value_data_sel_T_2[63:0]; // @[PTW.scala 224:24 230:14]
  reg [63:0] pte_value_value; // @[PTW.scala 234:24]
  wire [63:0] pte_value = is_trans_done ? pte_value_data_sel : pte_value_value; // @[PTW.scala 240:8]
  wire  is_ptw_end = pte_value[1] & pte_value[3]; // @[PTW.scala 164:22]
  wire  _is_ptw_fail_T_1 = currState == 2'h1; // @[PTW.scala 172:20]
  wire [8:0] is_ptw_fail_hetVecWire__0 = pte_value[18:10]; // @[MMU.scala 44:37]
  wire  _is_ptw_fail_T_5 = is_ptw_fail_hetVecWire__0 != 9'h0; // @[PTW.scala 172:57]
  wire [8:0] is_ptw_fail_hetVecWire_1_1 = pte_value[27:19]; // @[MMU.scala 44:51]
  wire  _is_ptw_fail_T_10 = is_ptw_fail_hetVecWire__0 != 9'h0 | is_ptw_fail_hetVecWire_1_1 != 9'h0; // @[PTW.scala 172:65]
  wire  _is_ptw_fail_T_11 = currState == 2'h2; // @[PTW.scala 173:20]
  wire  _is_ptw_fail_T_22 = _is_ptw_fail_T_1 & _is_ptw_fail_T_10 | _is_ptw_fail_T_11 & _is_ptw_fail_T_5; // @[Mux.scala 27:73]
  wire  _is_ptw_fail_T_24 = is_ptw_end & _is_ptw_fail_T_22; // @[PTW.scala 169:18]
  wire  _is_ptw_fail_T_34 = ~pte_value[1] & pte_value[2]; // @[PTW.scala 179:26]
  wire  _is_ptw_fail_T_35 = ~pte_value[0] | _is_ptw_fail_T_34; // @[PTW.scala 178:27]
  wire  is_ptw_fail = _is_ptw_fail_T_24 | _is_ptw_fail_T_35; // @[PTW.scala 176:7]
  wire  _nextState_T_4 = is_ptw_end | is_ptw_fail | kill_trans; // @[PTW.scala 118:41]
  wire [1:0] _nextState_T_5 = is_ptw_end | is_ptw_fail | kill_trans ? 2'h0 : 2'h2; // @[PTW.scala 118:14]
  wire [1:0] _nextState_T_6 = is_trans_done ? _nextState_T_5 : 2'h1; // @[PTW.scala 116:12]
  wire [1:0] _nextState_T_10 = _nextState_T_4 ? 2'h0 : 2'h3; // @[PTW.scala 126:14]
  wire [1:0] _nextState_T_11 = is_trans_done ? _nextState_T_10 : 2'h2; // @[PTW.scala 124:12]
  wire [1:0] _nextState_T_16 = is_trans_done ? 2'h0 : 2'h3; // @[PTW.scala 132:12]
  wire [1:0] _GEN_6 = 2'h3 == currState ? _nextState_T_16 : 2'h0; // @[PTW.scala 110:23 131:17]
  wire [1:0] _GEN_7 = 2'h2 == currState ? _nextState_T_11 : _GEN_6; // @[PTW.scala 110:23 123:17]
  wire [1:0] _GEN_8 = 2'h1 == currState ? _nextState_T_6 : _GEN_7; // @[PTW.scala 110:23 115:17]
  wire [1:0] nextState = 2'h0 == currState ? _nextState_T_1 : _GEN_8; // @[PTW.scala 110:23 112:17]
  wire  _walkReq_T_2 = currState == 2'h0 & nextState != 2'h0; // @[PTW.scala 102:83]
  reg  walkReq_is_X; // @[Reg.scala 19:16]
  reg [63:0] walkReq_vaddr; // @[Reg.scala 19:16]
  reg [15:0] asidReq; // @[Reg.scala 19:16]
  reg  walkRspBits_is_X; // @[PTW.scala 104:28]
  reg  walkRspBits_renew_is_giga_page; // @[PTW.scala 104:28]
  reg  walkRspBits_renew_is_mega_page; // @[PTW.scala 104:28]
  reg [15:0] walkRspBits_renew_asid; // @[PTW.scala 104:28]
  reg [8:0] walkRspBits_renew_vpn_0; // @[PTW.scala 104:28]
  reg [8:0] walkRspBits_renew_vpn_1; // @[PTW.scala 104:28]
  reg [8:0] walkRspBits_renew_vpn_2; // @[PTW.scala 104:28]
  reg  walkRspBits_is_ptw_fail; // @[PTW.scala 104:28]
  reg  walkRspValid; // @[PTW.scala 105:29]
  wire  _a_T = nextState == 2'h1; // @[PTW.scala 148:19]
  wire  _a_T_2 = nextState == 2'h2; // @[PTW.scala 149:19]
  wire [25:0] a_hetVecWire__2 = pte_value[53:28]; // @[MMU.scala 44:65]
  wire [43:0] _a_T_12 = {a_hetVecWire__2,is_ptw_fail_hetVecWire_1_1,is_ptw_fail_hetVecWire__0}; // @[Cat.scala 33:92]
  wire  _a_T_13 = nextState == 2'h3; // @[PTW.scala 150:19]
  wire [43:0] _a_T_24 = _a_T ? io_cmm_mmu_satp[43:0] : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] _a_T_25 = _a_T_2 ? _a_T_12 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] _a_T_26 = _a_T_13 ? _a_T_12 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] _a_T_27 = _a_T_24 | _a_T_25; // @[Mux.scala 27:73]
  wire [43:0] a = _a_T_27 | _a_T_26; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_2 = {io_ptw_i_bits_vaddr[38:30],3'h0}; // @[Cat.scala 33:92]
  wire [11:0] _addr_dnxt_T_5 = {walkReq_vaddr[29:21],3'h0}; // @[Cat.scala 33:92]
  wire [11:0] _addr_dnxt_T_8 = {walkReq_vaddr[20:12],3'h0}; // @[Cat.scala 33:92]
  wire [11:0] _addr_dnxt_T_9 = _a_T ? _addr_dnxt_T_2 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_10 = _a_T_2 ? _addr_dnxt_T_5 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_11 = _a_T_13 ? _addr_dnxt_T_8 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_12 = _addr_dnxt_T_9 | _addr_dnxt_T_10; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_13 = _addr_dnxt_T_12 | _addr_dnxt_T_11; // @[Mux.scala 27:73]
  wire [55:0] _addr_dnxt_T_14 = {a,_addr_dnxt_T_13}; // @[Cat.scala 33:92]
  wire  pte_is_mega_page = is_ptw_end & _is_ptw_fail_T_11; // @[PTW.scala 184:34]
  wire  pte_is_giga_page = is_ptw_end & _is_ptw_fail_T_1; // @[PTW.scala 185:34]
  wire  _T_10 = currState != 2'h0; // @[PTW.scala 197:51]
  wire  _T_11 = nextState == 2'h0 & currState != 2'h0; // @[PTW.scala 197:39]
  wire  _T_12 = ~io_ptw_o_valid; // @[PTW.scala 210:28]
  wire  _T_16 = io_ptw_o_ready & io_ptw_o_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_12 = _T_16 ? 1'h0 : walkRspValid; // @[PTW.scala 211:32 212:18 105:29]
  wire  _GEN_25 = nextState == 2'h0 & currState != 2'h0 | _GEN_12; // @[PTW.scala 197:73 208:18]
  reg  ptw_access_ready; // @[PTW.scala 343:33]
  wire  _GEN_33 = _T ? 1'h0 : ptw_access_ready; // @[PTW.scala 361:37 362:22 343:33]
  wire  _GEN_34 = io_ptw_access_valid & ~io_ptw_access_ready | _GEN_33; // @[PTW.scala 359:53 360:22]
  wire  _GEN_35 = _walkReq_T ? 1'h0 : kill_trans; // @[PTW.scala 384:48 385:16 89:27]
  wire  _GEN_36 = io_cmm_mmu_sfence_vma & _T_10 | _GEN_35; // @[PTW.scala 382:65 383:16]
  wire  _io_ptw_o_valid_T = ~kill_trans; // @[PTW.scala 390:36]
  wire [31:0] addr_dnxt = _addr_dnxt_T_14[31:0]; // @[PTW.scala 153:13 94:23]
  assign io_ptw_i_ready = _walkReq_T & _T_12 & ~io_cmm_mmu_sfence_vma & _io_ptw_o_valid_T; // @[PTW.scala 393:94]
  assign io_ptw_o_valid = walkRspValid & ~kill_trans; // @[PTW.scala 390:34]
  assign io_ptw_o_bits_is_X = walkRspBits_is_X; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_is_giga_page = walkRspBits_renew_is_giga_page; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_is_mega_page = walkRspBits_renew_is_mega_page; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_asid = walkRspBits_renew_asid; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_vpn_0 = walkRspBits_renew_vpn_0; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_vpn_1 = walkRspBits_renew_vpn_1; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_vpn_2 = walkRspBits_renew_vpn_2; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_is_ptw_fail = walkRspBits_is_ptw_fail; // @[PTW.scala 389:18]
  assign io_ptw_access_ready = ptw_access_ready; // @[PTW.scala 346:23]
  always @(posedge clock) begin
    if (reset) begin // @[PTW.scala 87:26]
      currState <= 2'h0; // @[PTW.scala 87:26]
    end else if (2'h0 == currState) begin // @[PTW.scala 110:23]
      if (_nextState_T) begin // @[PTW.scala 112:23]
        currState <= 2'h1;
      end else begin
        currState <= 2'h0;
      end
    end else if (2'h1 == currState) begin // @[PTW.scala 110:23]
      if (is_trans_done) begin // @[PTW.scala 116:12]
        currState <= _nextState_T_5;
      end else begin
        currState <= 2'h1;
      end
    end else if (2'h2 == currState) begin // @[PTW.scala 110:23]
      currState <= _nextState_T_11; // @[PTW.scala 123:17]
    end else begin
      currState <= _GEN_6;
    end
    if (reset) begin // @[PTW.scala 89:27]
      kill_trans <= 1'h0; // @[PTW.scala 89:27]
    end else begin
      kill_trans <= _GEN_36;
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        counter <= beats1;
      end else begin
        counter <= counter1;
      end
    end
    if (reset) begin // @[PTW.scala 95:26]
      addr_qout <= 32'h0; // @[PTW.scala 95:26]
    end else begin
      addr_qout <= addr_dnxt; // @[PTW.scala 95:26]
    end
    if (_T & ~is_trans_done) begin // @[PTW.scala 243:46]
      ptw_access_data_lo_0 <= io_ptw_access_bits_data; // @[PTW.scala 244:34]
    end
    if (reset) begin // @[PTW.scala 234:24]
      pte_value_value <= 64'h0; // @[PTW.scala 234:24]
    end else if (is_trans_done) begin // @[PTW.scala 240:8]
      pte_value_value <= pte_value_data_sel;
    end
    if (_walkReq_T_2) begin // @[Reg.scala 20:18]
      walkReq_is_X <= io_ptw_i_bits_is_X; // @[Reg.scala 20:22]
    end
    if (_walkReq_T_2) begin // @[Reg.scala 20:18]
      walkReq_vaddr <= io_ptw_i_bits_vaddr; // @[Reg.scala 20:22]
    end
    if (_walkReq_T_2) begin // @[Reg.scala 20:18]
      asidReq <= io_cmm_mmu_satp[59:44]; // @[Reg.scala 20:22]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_is_X <= 1'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_is_X <= walkReq_is_X; // @[PTW.scala 199:22]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_is_giga_page <= 1'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_is_giga_page <= pte_is_giga_page; // @[PTW.scala 202:58]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_is_mega_page <= 1'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_is_mega_page <= pte_is_mega_page; // @[PTW.scala 202:58]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_asid <= 16'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_asid <= asidReq; // @[PTW.scala 206:30]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_vpn_0 <= 9'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_vpn_0 <= walkReq_vaddr[20:12]; // @[PTW.scala 203:30]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_vpn_1 <= 9'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_vpn_1 <= walkReq_vaddr[29:21]; // @[PTW.scala 204:30]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_vpn_2 <= 9'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_vpn_2 <= walkReq_vaddr[38:30]; // @[PTW.scala 205:30]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_is_ptw_fail <= 1'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_is_ptw_fail <= is_ptw_fail; // @[PTW.scala 198:29]
    end
    if (reset) begin // @[PTW.scala 105:29]
      walkRspValid <= 1'h0; // @[PTW.scala 105:29]
    end else begin
      walkRspValid <= _GEN_25;
    end
    if (reset) begin // @[PTW.scala 343:33]
      ptw_access_ready <= 1'h0; // @[PTW.scala 343:33]
    end else begin
      ptw_access_ready <= _GEN_34;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_11 & ~reset & ~(~io_ptw_o_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at PTW.scala:210 assert( io.ptw_o.valid === false.B )\n"); // @[PTW.scala 210:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_ptw_o_valid) & (_T_11 & ~reset)) begin
          $fatal; // @[PTW.scala 210:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  currState = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  kill_trans = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  counter = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  addr_qout = _RAND_3[31:0];
  _RAND_4 = {2{`RANDOM}};
  ptw_access_data_lo_0 = _RAND_4[63:0];
  _RAND_5 = {2{`RANDOM}};
  pte_value_value = _RAND_5[63:0];
  _RAND_6 = {1{`RANDOM}};
  walkReq_is_X = _RAND_6[0:0];
  _RAND_7 = {2{`RANDOM}};
  walkReq_vaddr = _RAND_7[63:0];
  _RAND_8 = {1{`RANDOM}};
  asidReq = _RAND_8[15:0];
  _RAND_9 = {1{`RANDOM}};
  walkRspBits_is_X = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  walkRspBits_renew_is_giga_page = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  walkRspBits_renew_is_mega_page = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  walkRspBits_renew_asid = _RAND_12[15:0];
  _RAND_13 = {1{`RANDOM}};
  walkRspBits_renew_vpn_0 = _RAND_13[8:0];
  _RAND_14 = {1{`RANDOM}};
  walkRspBits_renew_vpn_1 = _RAND_14[8:0];
  _RAND_15 = {1{`RANDOM}};
  walkRspBits_renew_vpn_2 = _RAND_15[8:0];
  _RAND_16 = {1{`RANDOM}};
  walkRspBits_is_ptw_fail = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  walkRspValid = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  ptw_access_ready = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module PTW_1(
  input         clock,
  input         reset,
  output        io_ptw_i_ready,
  input         io_ptw_i_valid,
  input         io_ptw_i_bits_is_X,
  input  [63:0] io_ptw_i_bits_vaddr,
  input         io_ptw_o_ready,
  output        io_ptw_o_valid,
  output        io_ptw_o_bits_is_X,
  output        io_ptw_o_bits_renew_is_giga_page,
  output        io_ptw_o_bits_renew_is_mega_page,
  output [15:0] io_ptw_o_bits_renew_asid,
  output [8:0]  io_ptw_o_bits_renew_vpn_0,
  output [8:0]  io_ptw_o_bits_renew_vpn_1,
  output [8:0]  io_ptw_o_bits_renew_vpn_2,
  output        io_ptw_o_bits_is_ptw_fail,
  input  [63:0] io_cmm_mmu_satp,
  input         io_cmm_mmu_sfence_vma,
  output        io_ptw_access_ready,
  input         io_ptw_access_valid,
  input  [2:0]  io_ptw_access_bits_opcode,
  input  [2:0]  io_ptw_access_bits_size,
  input  [63:0] io_ptw_access_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [63:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] currState; // @[PTW.scala 87:26]
  reg  kill_trans; // @[PTW.scala 89:27]
  wire  _T = io_ptw_access_ready & io_ptw_access_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _beats1_decode_T_1 = 11'hf << io_ptw_access_bits_size; // @[package.scala 234:77]
  wire [3:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  beats1_decode = _beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  beats1_opdata = io_ptw_access_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  beats1 = beats1_opdata & beats1_decode; // @[Edges.scala 220:14]
  reg  counter; // @[Edges.scala 228:27]
  wire  counter1 = counter - 1'h1; // @[Edges.scala 229:28]
  wire  first = ~counter; // @[Edges.scala 230:25]
  wire  last = counter | ~beats1; // @[Edges.scala 231:37]
  wire  is_trans_done = last & _T; // @[Edges.scala 232:22]
  reg [31:0] addr_qout; // @[PTW.scala 95:26]
  wire  _walkReq_T = currState == 2'h0; // @[PTW.scala 102:63]
  wire  _nextState_T = io_ptw_i_ready & io_ptw_i_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _nextState_T_1 = _nextState_T ? 2'h1 : 2'h0; // @[PTW.scala 112:23]
  reg [63:0] ptw_access_data_lo_0; // @[PTW.scala 218:31]
  wire [127:0] ptw_access_data = {io_ptw_access_bits_data,ptw_access_data_lo_0}; // @[Cat.scala 33:92]
  wire [127:0] pte_value_data = is_trans_done ? ptw_access_data : 128'h0; // @[PTW.scala 226:27 227:12]
  wire [6:0] _pte_value_data_sel_T_1 = {addr_qout[3], 6'h0}; // @[PTW.scala 231:54]
  wire [127:0] _pte_value_data_sel_T_2 = pte_value_data >> _pte_value_data_sel_T_1; // @[PTW.scala 230:22]
  wire [63:0] pte_value_data_sel = _pte_value_data_sel_T_2[63:0]; // @[PTW.scala 224:24 230:14]
  reg [63:0] pte_value_value; // @[PTW.scala 234:24]
  wire [63:0] pte_value = is_trans_done ? pte_value_data_sel : pte_value_value; // @[PTW.scala 240:8]
  wire  is_ptw_end = pte_value[1] & pte_value[3]; // @[PTW.scala 164:22]
  wire  _is_ptw_fail_T_1 = currState == 2'h1; // @[PTW.scala 172:20]
  wire [8:0] is_ptw_fail_hetVecWire__0 = pte_value[18:10]; // @[MMU.scala 44:37]
  wire  _is_ptw_fail_T_5 = is_ptw_fail_hetVecWire__0 != 9'h0; // @[PTW.scala 172:57]
  wire [8:0] is_ptw_fail_hetVecWire_1_1 = pte_value[27:19]; // @[MMU.scala 44:51]
  wire  _is_ptw_fail_T_10 = is_ptw_fail_hetVecWire__0 != 9'h0 | is_ptw_fail_hetVecWire_1_1 != 9'h0; // @[PTW.scala 172:65]
  wire  _is_ptw_fail_T_11 = currState == 2'h2; // @[PTW.scala 173:20]
  wire  _is_ptw_fail_T_22 = _is_ptw_fail_T_1 & _is_ptw_fail_T_10 | _is_ptw_fail_T_11 & _is_ptw_fail_T_5; // @[Mux.scala 27:73]
  wire  _is_ptw_fail_T_24 = is_ptw_end & _is_ptw_fail_T_22; // @[PTW.scala 169:18]
  wire  _is_ptw_fail_T_34 = ~pte_value[1] & pte_value[2]; // @[PTW.scala 179:26]
  wire  _is_ptw_fail_T_35 = ~pte_value[0] | _is_ptw_fail_T_34; // @[PTW.scala 178:27]
  wire  is_ptw_fail = _is_ptw_fail_T_24 | _is_ptw_fail_T_35; // @[PTW.scala 176:7]
  wire  _nextState_T_4 = is_ptw_end | is_ptw_fail | kill_trans; // @[PTW.scala 118:41]
  wire [1:0] _nextState_T_5 = is_ptw_end | is_ptw_fail | kill_trans ? 2'h0 : 2'h2; // @[PTW.scala 118:14]
  wire [1:0] _nextState_T_6 = is_trans_done ? _nextState_T_5 : 2'h1; // @[PTW.scala 116:12]
  wire [1:0] _nextState_T_10 = _nextState_T_4 ? 2'h0 : 2'h3; // @[PTW.scala 126:14]
  wire [1:0] _nextState_T_11 = is_trans_done ? _nextState_T_10 : 2'h2; // @[PTW.scala 124:12]
  wire [1:0] _nextState_T_16 = is_trans_done ? 2'h0 : 2'h3; // @[PTW.scala 132:12]
  wire [1:0] _GEN_6 = 2'h3 == currState ? _nextState_T_16 : 2'h0; // @[PTW.scala 110:23 131:17]
  wire [1:0] _GEN_7 = 2'h2 == currState ? _nextState_T_11 : _GEN_6; // @[PTW.scala 110:23 123:17]
  wire [1:0] _GEN_8 = 2'h1 == currState ? _nextState_T_6 : _GEN_7; // @[PTW.scala 110:23 115:17]
  wire [1:0] nextState = 2'h0 == currState ? _nextState_T_1 : _GEN_8; // @[PTW.scala 110:23 112:17]
  wire  _walkReq_T_2 = currState == 2'h0 & nextState != 2'h0; // @[PTW.scala 102:83]
  reg  walkReq_is_X; // @[Reg.scala 19:16]
  reg [63:0] walkReq_vaddr; // @[Reg.scala 19:16]
  reg [15:0] asidReq; // @[Reg.scala 19:16]
  reg  walkRspBits_is_X; // @[PTW.scala 104:28]
  reg  walkRspBits_renew_is_giga_page; // @[PTW.scala 104:28]
  reg  walkRspBits_renew_is_mega_page; // @[PTW.scala 104:28]
  reg [15:0] walkRspBits_renew_asid; // @[PTW.scala 104:28]
  reg [8:0] walkRspBits_renew_vpn_0; // @[PTW.scala 104:28]
  reg [8:0] walkRspBits_renew_vpn_1; // @[PTW.scala 104:28]
  reg [8:0] walkRspBits_renew_vpn_2; // @[PTW.scala 104:28]
  reg  walkRspBits_is_ptw_fail; // @[PTW.scala 104:28]
  reg  walkRspValid; // @[PTW.scala 105:29]
  wire  _a_T = nextState == 2'h1; // @[PTW.scala 148:19]
  wire  _a_T_2 = nextState == 2'h2; // @[PTW.scala 149:19]
  wire [25:0] a_hetVecWire__2 = pte_value[53:28]; // @[MMU.scala 44:65]
  wire [43:0] _a_T_12 = {a_hetVecWire__2,is_ptw_fail_hetVecWire_1_1,is_ptw_fail_hetVecWire__0}; // @[Cat.scala 33:92]
  wire  _a_T_13 = nextState == 2'h3; // @[PTW.scala 150:19]
  wire [43:0] _a_T_24 = _a_T ? io_cmm_mmu_satp[43:0] : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] _a_T_25 = _a_T_2 ? _a_T_12 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] _a_T_26 = _a_T_13 ? _a_T_12 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] _a_T_27 = _a_T_24 | _a_T_25; // @[Mux.scala 27:73]
  wire [43:0] a = _a_T_27 | _a_T_26; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_2 = {io_ptw_i_bits_vaddr[38:30],3'h0}; // @[Cat.scala 33:92]
  wire [11:0] _addr_dnxt_T_5 = {walkReq_vaddr[29:21],3'h0}; // @[Cat.scala 33:92]
  wire [11:0] _addr_dnxt_T_8 = {walkReq_vaddr[20:12],3'h0}; // @[Cat.scala 33:92]
  wire [11:0] _addr_dnxt_T_9 = _a_T ? _addr_dnxt_T_2 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_10 = _a_T_2 ? _addr_dnxt_T_5 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_11 = _a_T_13 ? _addr_dnxt_T_8 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_12 = _addr_dnxt_T_9 | _addr_dnxt_T_10; // @[Mux.scala 27:73]
  wire [11:0] _addr_dnxt_T_13 = _addr_dnxt_T_12 | _addr_dnxt_T_11; // @[Mux.scala 27:73]
  wire [55:0] _addr_dnxt_T_14 = {a,_addr_dnxt_T_13}; // @[Cat.scala 33:92]
  wire  pte_is_mega_page = is_ptw_end & _is_ptw_fail_T_11; // @[PTW.scala 184:34]
  wire  pte_is_giga_page = is_ptw_end & _is_ptw_fail_T_1; // @[PTW.scala 185:34]
  wire  _T_10 = currState != 2'h0; // @[PTW.scala 197:51]
  wire  _T_11 = nextState == 2'h0 & currState != 2'h0; // @[PTW.scala 197:39]
  wire  _T_12 = ~io_ptw_o_valid; // @[PTW.scala 210:28]
  wire  _T_16 = io_ptw_o_ready & io_ptw_o_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_12 = _T_16 ? 1'h0 : walkRspValid; // @[PTW.scala 211:32 212:18 105:29]
  wire  _GEN_25 = nextState == 2'h0 & currState != 2'h0 | _GEN_12; // @[PTW.scala 197:73 208:18]
  reg  ptw_access_ready; // @[PTW.scala 343:33]
  wire  _GEN_33 = _T ? 1'h0 : ptw_access_ready; // @[PTW.scala 361:37 362:22 343:33]
  wire  _GEN_34 = io_ptw_access_valid & ~io_ptw_access_ready | _GEN_33; // @[PTW.scala 359:53 360:22]
  wire  _GEN_35 = _walkReq_T ? 1'h0 : kill_trans; // @[PTW.scala 384:48 385:16 89:27]
  wire  _GEN_36 = io_cmm_mmu_sfence_vma & _T_10 | _GEN_35; // @[PTW.scala 382:65 383:16]
  wire  _io_ptw_o_valid_T = ~kill_trans; // @[PTW.scala 390:36]
  wire [31:0] addr_dnxt = _addr_dnxt_T_14[31:0]; // @[PTW.scala 153:13 94:23]
  assign io_ptw_i_ready = _walkReq_T & _T_12 & ~io_cmm_mmu_sfence_vma & _io_ptw_o_valid_T; // @[PTW.scala 393:94]
  assign io_ptw_o_valid = walkRspValid & ~kill_trans; // @[PTW.scala 390:34]
  assign io_ptw_o_bits_is_X = walkRspBits_is_X; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_is_giga_page = walkRspBits_renew_is_giga_page; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_is_mega_page = walkRspBits_renew_is_mega_page; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_asid = walkRspBits_renew_asid; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_vpn_0 = walkRspBits_renew_vpn_0; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_vpn_1 = walkRspBits_renew_vpn_1; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_renew_vpn_2 = walkRspBits_renew_vpn_2; // @[PTW.scala 389:18]
  assign io_ptw_o_bits_is_ptw_fail = walkRspBits_is_ptw_fail; // @[PTW.scala 389:18]
  assign io_ptw_access_ready = ptw_access_ready; // @[PTW.scala 346:23]
  always @(posedge clock) begin
    if (reset) begin // @[PTW.scala 87:26]
      currState <= 2'h0; // @[PTW.scala 87:26]
    end else if (2'h0 == currState) begin // @[PTW.scala 110:23]
      if (_nextState_T) begin // @[PTW.scala 112:23]
        currState <= 2'h1;
      end else begin
        currState <= 2'h0;
      end
    end else if (2'h1 == currState) begin // @[PTW.scala 110:23]
      if (is_trans_done) begin // @[PTW.scala 116:12]
        currState <= _nextState_T_5;
      end else begin
        currState <= 2'h1;
      end
    end else if (2'h2 == currState) begin // @[PTW.scala 110:23]
      currState <= _nextState_T_11; // @[PTW.scala 123:17]
    end else begin
      currState <= _GEN_6;
    end
    if (reset) begin // @[PTW.scala 89:27]
      kill_trans <= 1'h0; // @[PTW.scala 89:27]
    end else begin
      kill_trans <= _GEN_36;
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        counter <= beats1;
      end else begin
        counter <= counter1;
      end
    end
    if (reset) begin // @[PTW.scala 95:26]
      addr_qout <= 32'h0; // @[PTW.scala 95:26]
    end else begin
      addr_qout <= addr_dnxt; // @[PTW.scala 95:26]
    end
    if (_T & ~is_trans_done) begin // @[PTW.scala 243:46]
      ptw_access_data_lo_0 <= io_ptw_access_bits_data; // @[PTW.scala 244:34]
    end
    if (reset) begin // @[PTW.scala 234:24]
      pte_value_value <= 64'h0; // @[PTW.scala 234:24]
    end else if (is_trans_done) begin // @[PTW.scala 240:8]
      pte_value_value <= pte_value_data_sel;
    end
    if (_walkReq_T_2) begin // @[Reg.scala 20:18]
      walkReq_is_X <= io_ptw_i_bits_is_X; // @[Reg.scala 20:22]
    end
    if (_walkReq_T_2) begin // @[Reg.scala 20:18]
      walkReq_vaddr <= io_ptw_i_bits_vaddr; // @[Reg.scala 20:22]
    end
    if (_walkReq_T_2) begin // @[Reg.scala 20:18]
      asidReq <= io_cmm_mmu_satp[59:44]; // @[Reg.scala 20:22]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_is_X <= 1'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_is_X <= walkReq_is_X; // @[PTW.scala 199:22]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_is_giga_page <= 1'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_is_giga_page <= pte_is_giga_page; // @[PTW.scala 202:58]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_is_mega_page <= 1'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_is_mega_page <= pte_is_mega_page; // @[PTW.scala 202:58]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_asid <= 16'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_asid <= asidReq; // @[PTW.scala 206:30]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_vpn_0 <= 9'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_vpn_0 <= walkReq_vaddr[20:12]; // @[PTW.scala 203:30]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_vpn_1 <= 9'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_vpn_1 <= walkReq_vaddr[29:21]; // @[PTW.scala 204:30]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_renew_vpn_2 <= 9'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_renew_vpn_2 <= walkReq_vaddr[38:30]; // @[PTW.scala 205:30]
    end
    if (reset) begin // @[PTW.scala 104:28]
      walkRspBits_is_ptw_fail <= 1'h0; // @[PTW.scala 104:28]
    end else if (nextState == 2'h0 & currState != 2'h0) begin // @[PTW.scala 197:73]
      walkRspBits_is_ptw_fail <= is_ptw_fail; // @[PTW.scala 198:29]
    end
    if (reset) begin // @[PTW.scala 105:29]
      walkRspValid <= 1'h0; // @[PTW.scala 105:29]
    end else begin
      walkRspValid <= _GEN_25;
    end
    if (reset) begin // @[PTW.scala 343:33]
      ptw_access_ready <= 1'h0; // @[PTW.scala 343:33]
    end else begin
      ptw_access_ready <= _GEN_34;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_11 & ~reset & ~(~io_ptw_o_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at PTW.scala:210 assert( io.ptw_o.valid === false.B )\n"); // @[PTW.scala 210:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_ptw_o_valid) & (_T_11 & ~reset)) begin
          $fatal; // @[PTW.scala 210:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  currState = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  kill_trans = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  counter = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  addr_qout = _RAND_3[31:0];
  _RAND_4 = {2{`RANDOM}};
  ptw_access_data_lo_0 = _RAND_4[63:0];
  _RAND_5 = {2{`RANDOM}};
  pte_value_value = _RAND_5[63:0];
  _RAND_6 = {1{`RANDOM}};
  walkReq_is_X = _RAND_6[0:0];
  _RAND_7 = {2{`RANDOM}};
  walkReq_vaddr = _RAND_7[63:0];
  _RAND_8 = {1{`RANDOM}};
  asidReq = _RAND_8[15:0];
  _RAND_9 = {1{`RANDOM}};
  walkRspBits_is_X = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  walkRspBits_renew_is_giga_page = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  walkRspBits_renew_is_mega_page = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  walkRspBits_renew_asid = _RAND_12[15:0];
  _RAND_13 = {1{`RANDOM}};
  walkRspBits_renew_vpn_0 = _RAND_13[8:0];
  _RAND_14 = {1{`RANDOM}};
  walkRspBits_renew_vpn_1 = _RAND_14[8:0];
  _RAND_15 = {1{`RANDOM}};
  walkRspBits_renew_vpn_2 = _RAND_15[8:0];
  _RAND_16 = {1{`RANDOM}};
  walkRspBits_is_ptw_fail = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  walkRspValid = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  ptw_access_ready = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MMU(
  input         clock,
  input         reset,
  input         io_if_mmu_valid,
  input         io_if_mmu_bits_is_X,
  input  [63:0] io_if_mmu_bits_vaddr,
  input         io_mmu_if_ready,
  input         io_if_flush,
  output        io_lsu_mmu_ready,
  input         io_lsu_mmu_valid,
  input         io_lsu_mmu_bits_is_X,
  input  [63:0] io_lsu_mmu_bits_vaddr,
  input         io_mmu_lsu_ready,
  output        io_mmu_lsu_valid,
  input         io_lsu_flush,
  input  [63:0] io_cmm_mmu_satp,
  input  [1:0]  io_cmm_mmu_priv_lvl_if,
  input  [1:0]  io_cmm_mmu_priv_lvl_ls,
  input         io_cmm_mmu_sfence_vma,
  input         io_ptw_access_valid,
  input  [2:0]  io_ptw_access_bits_opcode,
  input  [2:0]  io_ptw_access_bits_size,
  input         io_ptw_access_bits_source,
  input  [63:0] io_ptw_access_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  itlb_clock; // @[MMU.scala 131:20]
  wire  itlb_reset; // @[MMU.scala 131:20]
  wire  itlb_io_req_valid; // @[MMU.scala 131:20]
  wire [63:0] itlb_io_req_bits_vaddr; // @[MMU.scala 131:20]
  wire  itlb_io_is_hit; // @[MMU.scala 131:20]
  wire [15:0] itlb_io_asid_i; // @[MMU.scala 131:20]
  wire  itlb_io_tlb_renew_valid; // @[MMU.scala 131:20]
  wire  itlb_io_tlb_renew_bits_is_giga_page; // @[MMU.scala 131:20]
  wire  itlb_io_tlb_renew_bits_is_mega_page; // @[MMU.scala 131:20]
  wire [15:0] itlb_io_tlb_renew_bits_asid; // @[MMU.scala 131:20]
  wire [8:0] itlb_io_tlb_renew_bits_vpn_0; // @[MMU.scala 131:20]
  wire [8:0] itlb_io_tlb_renew_bits_vpn_1; // @[MMU.scala 131:20]
  wire [8:0] itlb_io_tlb_renew_bits_vpn_2; // @[MMU.scala 131:20]
  wire  itlb_io_sfence_vma; // @[MMU.scala 131:20]
  wire  dtlb_clock; // @[MMU.scala 132:20]
  wire  dtlb_reset; // @[MMU.scala 132:20]
  wire  dtlb_io_req_valid; // @[MMU.scala 132:20]
  wire [63:0] dtlb_io_req_bits_vaddr; // @[MMU.scala 132:20]
  wire  dtlb_io_is_hit; // @[MMU.scala 132:20]
  wire [15:0] dtlb_io_asid_i; // @[MMU.scala 132:20]
  wire  dtlb_io_tlb_renew_valid; // @[MMU.scala 132:20]
  wire  dtlb_io_tlb_renew_bits_is_giga_page; // @[MMU.scala 132:20]
  wire  dtlb_io_tlb_renew_bits_is_mega_page; // @[MMU.scala 132:20]
  wire [15:0] dtlb_io_tlb_renew_bits_asid; // @[MMU.scala 132:20]
  wire [8:0] dtlb_io_tlb_renew_bits_vpn_0; // @[MMU.scala 132:20]
  wire [8:0] dtlb_io_tlb_renew_bits_vpn_1; // @[MMU.scala 132:20]
  wire [8:0] dtlb_io_tlb_renew_bits_vpn_2; // @[MMU.scala 132:20]
  wire  dtlb_io_sfence_vma; // @[MMU.scala 132:20]
  wire  iptw_clock; // @[MMU.scala 133:21]
  wire  iptw_reset; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_i_ready; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_i_valid; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_i_bits_is_X; // @[MMU.scala 133:21]
  wire [63:0] iptw_io_ptw_i_bits_vaddr; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_o_ready; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_o_valid; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_o_bits_is_X; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_o_bits_renew_is_giga_page; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_o_bits_renew_is_mega_page; // @[MMU.scala 133:21]
  wire [15:0] iptw_io_ptw_o_bits_renew_asid; // @[MMU.scala 133:21]
  wire [8:0] iptw_io_ptw_o_bits_renew_vpn_0; // @[MMU.scala 133:21]
  wire [8:0] iptw_io_ptw_o_bits_renew_vpn_1; // @[MMU.scala 133:21]
  wire [8:0] iptw_io_ptw_o_bits_renew_vpn_2; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_o_bits_is_ptw_fail; // @[MMU.scala 133:21]
  wire [63:0] iptw_io_cmm_mmu_satp; // @[MMU.scala 133:21]
  wire  iptw_io_cmm_mmu_sfence_vma; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_access_ready; // @[MMU.scala 133:21]
  wire  iptw_io_ptw_access_valid; // @[MMU.scala 133:21]
  wire [2:0] iptw_io_ptw_access_bits_opcode; // @[MMU.scala 133:21]
  wire [2:0] iptw_io_ptw_access_bits_size; // @[MMU.scala 133:21]
  wire [63:0] iptw_io_ptw_access_bits_data; // @[MMU.scala 133:21]
  wire  dptw_clock; // @[MMU.scala 134:21]
  wire  dptw_reset; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_i_ready; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_i_valid; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_i_bits_is_X; // @[MMU.scala 134:21]
  wire [63:0] dptw_io_ptw_i_bits_vaddr; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_o_ready; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_o_valid; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_o_bits_is_X; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_o_bits_renew_is_giga_page; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_o_bits_renew_is_mega_page; // @[MMU.scala 134:21]
  wire [15:0] dptw_io_ptw_o_bits_renew_asid; // @[MMU.scala 134:21]
  wire [8:0] dptw_io_ptw_o_bits_renew_vpn_0; // @[MMU.scala 134:21]
  wire [8:0] dptw_io_ptw_o_bits_renew_vpn_1; // @[MMU.scala 134:21]
  wire [8:0] dptw_io_ptw_o_bits_renew_vpn_2; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_o_bits_is_ptw_fail; // @[MMU.scala 134:21]
  wire [63:0] dptw_io_cmm_mmu_satp; // @[MMU.scala 134:21]
  wire  dptw_io_cmm_mmu_sfence_vma; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_access_ready; // @[MMU.scala 134:21]
  wire  dptw_io_ptw_access_valid; // @[MMU.scala 134:21]
  wire [2:0] dptw_io_ptw_access_bits_opcode; // @[MMU.scala 134:21]
  wire [2:0] dptw_io_ptw_access_bits_size; // @[MMU.scala 134:21]
  wire [63:0] dptw_io_ptw_access_bits_data; // @[MMU.scala 134:21]
  wire  _is_bypass_if_T_1 = io_cmm_mmu_satp[63:60] == 4'h0; // @[MMU.scala 136:45]
  wire  is_bypass_if = io_cmm_mmu_satp[63:60] == 4'h0 | io_cmm_mmu_priv_lvl_if == 2'h3; // @[MMU.scala 136:53]
  wire  is_bypass_ls = _is_bypass_if_T_1 | io_cmm_mmu_priv_lvl_ls == 2'h3; // @[MMU.scala 137:53]
  reg  kill_iptw; // @[MMU.scala 141:26]
  reg  kill_dptw; // @[MMU.scala 142:26]
  wire  _GEN_0 = iptw_io_ptw_i_ready ? 1'h0 : kill_iptw; // @[MMU.scala 147:39 148:15 141:26]
  wire  _GEN_1 = io_if_flush | _GEN_0; // @[MMU.scala 145:23 146:15]
  wire  _GEN_2 = dptw_io_ptw_i_ready ? 1'h0 : kill_dptw; // @[MMU.scala 152:39 153:15 142:26]
  wire  _GEN_3 = io_lsu_flush | _GEN_2; // @[MMU.scala 150:24 151:15]
  wire  _io_lsu_mmu_ready_T = io_mmu_lsu_ready & io_mmu_lsu_valid; // @[Decoupled.scala 52:35]
  wire  _io_lsu_mmu_ready_T_1 = ~io_lsu_flush; // @[MMU.scala 168:23]
  wire  _io_lsu_mmu_ready_T_3 = ~kill_dptw; // @[MMU.scala 168:39]
  wire  _T = io_lsu_mmu_ready & io_lsu_mmu_valid; // @[Decoupled.scala 52:35]
  wire  _T_4 = ~reset; // @[MMU.scala 170:9]
  wire  _iptw_io_ptw_i_valid_T_4 = ~kill_iptw; // @[MMU.scala 180:78]
  wire  _io_mmu_lsu_valid_T_4 = io_lsu_mmu_valid & dtlb_io_is_hit; // @[MMU.scala 247:27]
  wire  _io_mmu_lsu_valid_T_5 = io_lsu_mmu_valid & is_bypass_ls | _io_mmu_lsu_valid_T_4; // @[MMU.scala 246:43]
  wire  _io_mmu_lsu_valid_T_6 = ~dptw_io_ptw_o_bits_is_X; // @[MMU.scala 248:30]
  wire  _io_mmu_lsu_valid_T_7 = ~dptw_io_ptw_o_bits_is_X & dptw_io_ptw_o_valid; // @[MMU.scala 248:55]
  wire  _io_mmu_lsu_valid_T_8 = io_lsu_mmu_valid & (~dptw_io_ptw_o_bits_is_X & dptw_io_ptw_o_valid); // @[MMU.scala 248:27]
  wire  _io_mmu_lsu_valid_T_9 = _io_mmu_lsu_valid_T_5 | _io_mmu_lsu_valid_T_8; // @[MMU.scala 247:45]
  wire  _itlb_io_tlb_renew_valid_T = iptw_io_ptw_o_ready & iptw_io_ptw_o_valid; // @[Decoupled.scala 52:35]
  wire  _dtlb_io_tlb_renew_valid_T = dptw_io_ptw_o_ready & dptw_io_ptw_o_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_5 = io_ptw_access_bits_source & io_ptw_access_valid; // @[MMU.scala 294:52 295:24 280:28]
  wire [2:0] _GEN_6 = io_ptw_access_bits_source ? io_ptw_access_bits_opcode : 3'h0; // @[MMU.scala 294:52 295:24 282:27]
  wire [2:0] _GEN_8 = io_ptw_access_bits_source ? io_ptw_access_bits_size : 3'h0; // @[MMU.scala 294:52 295:24 282:27]
  wire [63:0] _GEN_12 = io_ptw_access_bits_source ? io_ptw_access_bits_data : 64'h0; // @[MMU.scala 294:52 295:24 282:27]
  TLB itlb ( // @[MMU.scala 131:20]
    .clock(itlb_clock),
    .reset(itlb_reset),
    .io_req_valid(itlb_io_req_valid),
    .io_req_bits_vaddr(itlb_io_req_bits_vaddr),
    .io_is_hit(itlb_io_is_hit),
    .io_asid_i(itlb_io_asid_i),
    .io_tlb_renew_valid(itlb_io_tlb_renew_valid),
    .io_tlb_renew_bits_is_giga_page(itlb_io_tlb_renew_bits_is_giga_page),
    .io_tlb_renew_bits_is_mega_page(itlb_io_tlb_renew_bits_is_mega_page),
    .io_tlb_renew_bits_asid(itlb_io_tlb_renew_bits_asid),
    .io_tlb_renew_bits_vpn_0(itlb_io_tlb_renew_bits_vpn_0),
    .io_tlb_renew_bits_vpn_1(itlb_io_tlb_renew_bits_vpn_1),
    .io_tlb_renew_bits_vpn_2(itlb_io_tlb_renew_bits_vpn_2),
    .io_sfence_vma(itlb_io_sfence_vma)
  );
  TLB dtlb ( // @[MMU.scala 132:20]
    .clock(dtlb_clock),
    .reset(dtlb_reset),
    .io_req_valid(dtlb_io_req_valid),
    .io_req_bits_vaddr(dtlb_io_req_bits_vaddr),
    .io_is_hit(dtlb_io_is_hit),
    .io_asid_i(dtlb_io_asid_i),
    .io_tlb_renew_valid(dtlb_io_tlb_renew_valid),
    .io_tlb_renew_bits_is_giga_page(dtlb_io_tlb_renew_bits_is_giga_page),
    .io_tlb_renew_bits_is_mega_page(dtlb_io_tlb_renew_bits_is_mega_page),
    .io_tlb_renew_bits_asid(dtlb_io_tlb_renew_bits_asid),
    .io_tlb_renew_bits_vpn_0(dtlb_io_tlb_renew_bits_vpn_0),
    .io_tlb_renew_bits_vpn_1(dtlb_io_tlb_renew_bits_vpn_1),
    .io_tlb_renew_bits_vpn_2(dtlb_io_tlb_renew_bits_vpn_2),
    .io_sfence_vma(dtlb_io_sfence_vma)
  );
  PTW iptw ( // @[MMU.scala 133:21]
    .clock(iptw_clock),
    .reset(iptw_reset),
    .io_ptw_i_ready(iptw_io_ptw_i_ready),
    .io_ptw_i_valid(iptw_io_ptw_i_valid),
    .io_ptw_i_bits_is_X(iptw_io_ptw_i_bits_is_X),
    .io_ptw_i_bits_vaddr(iptw_io_ptw_i_bits_vaddr),
    .io_ptw_o_ready(iptw_io_ptw_o_ready),
    .io_ptw_o_valid(iptw_io_ptw_o_valid),
    .io_ptw_o_bits_is_X(iptw_io_ptw_o_bits_is_X),
    .io_ptw_o_bits_renew_is_giga_page(iptw_io_ptw_o_bits_renew_is_giga_page),
    .io_ptw_o_bits_renew_is_mega_page(iptw_io_ptw_o_bits_renew_is_mega_page),
    .io_ptw_o_bits_renew_asid(iptw_io_ptw_o_bits_renew_asid),
    .io_ptw_o_bits_renew_vpn_0(iptw_io_ptw_o_bits_renew_vpn_0),
    .io_ptw_o_bits_renew_vpn_1(iptw_io_ptw_o_bits_renew_vpn_1),
    .io_ptw_o_bits_renew_vpn_2(iptw_io_ptw_o_bits_renew_vpn_2),
    .io_ptw_o_bits_is_ptw_fail(iptw_io_ptw_o_bits_is_ptw_fail),
    .io_cmm_mmu_satp(iptw_io_cmm_mmu_satp),
    .io_cmm_mmu_sfence_vma(iptw_io_cmm_mmu_sfence_vma),
    .io_ptw_access_ready(iptw_io_ptw_access_ready),
    .io_ptw_access_valid(iptw_io_ptw_access_valid),
    .io_ptw_access_bits_opcode(iptw_io_ptw_access_bits_opcode),
    .io_ptw_access_bits_size(iptw_io_ptw_access_bits_size),
    .io_ptw_access_bits_data(iptw_io_ptw_access_bits_data)
  );
  PTW_1 dptw ( // @[MMU.scala 134:21]
    .clock(dptw_clock),
    .reset(dptw_reset),
    .io_ptw_i_ready(dptw_io_ptw_i_ready),
    .io_ptw_i_valid(dptw_io_ptw_i_valid),
    .io_ptw_i_bits_is_X(dptw_io_ptw_i_bits_is_X),
    .io_ptw_i_bits_vaddr(dptw_io_ptw_i_bits_vaddr),
    .io_ptw_o_ready(dptw_io_ptw_o_ready),
    .io_ptw_o_valid(dptw_io_ptw_o_valid),
    .io_ptw_o_bits_is_X(dptw_io_ptw_o_bits_is_X),
    .io_ptw_o_bits_renew_is_giga_page(dptw_io_ptw_o_bits_renew_is_giga_page),
    .io_ptw_o_bits_renew_is_mega_page(dptw_io_ptw_o_bits_renew_is_mega_page),
    .io_ptw_o_bits_renew_asid(dptw_io_ptw_o_bits_renew_asid),
    .io_ptw_o_bits_renew_vpn_0(dptw_io_ptw_o_bits_renew_vpn_0),
    .io_ptw_o_bits_renew_vpn_1(dptw_io_ptw_o_bits_renew_vpn_1),
    .io_ptw_o_bits_renew_vpn_2(dptw_io_ptw_o_bits_renew_vpn_2),
    .io_ptw_o_bits_is_ptw_fail(dptw_io_ptw_o_bits_is_ptw_fail),
    .io_cmm_mmu_satp(dptw_io_cmm_mmu_satp),
    .io_cmm_mmu_sfence_vma(dptw_io_cmm_mmu_sfence_vma),
    .io_ptw_access_ready(dptw_io_ptw_access_ready),
    .io_ptw_access_valid(dptw_io_ptw_access_valid),
    .io_ptw_access_bits_opcode(dptw_io_ptw_access_bits_opcode),
    .io_ptw_access_bits_size(dptw_io_ptw_access_bits_size),
    .io_ptw_access_bits_data(dptw_io_ptw_access_bits_data)
  );
  assign io_lsu_mmu_ready = _io_lsu_mmu_ready_T & ~io_lsu_flush & ~kill_dptw; // @[MMU.scala 168:37]
  assign io_mmu_lsu_valid = _io_lsu_mmu_ready_T_1 & _io_lsu_mmu_ready_T_3 & _io_mmu_lsu_valid_T_9; // @[MMU.scala 245:34]
  assign itlb_clock = clock;
  assign itlb_reset = reset;
  assign itlb_io_req_valid = io_if_mmu_valid; // @[MMU.scala 156:21]
  assign itlb_io_req_bits_vaddr = io_if_mmu_bits_vaddr; // @[MMU.scala 157:21]
  assign itlb_io_asid_i = io_cmm_mmu_satp[59:44]; // @[MMU.scala 158:37]
  assign itlb_io_tlb_renew_valid = _itlb_io_tlb_renew_valid_T & iptw_io_ptw_o_bits_is_X & ~
    iptw_io_ptw_o_bits_is_ptw_fail & _iptw_io_ptw_i_valid_T_4; // @[MMU.scala 268:110]
  assign itlb_io_tlb_renew_bits_is_giga_page = iptw_io_ptw_o_bits_renew_is_giga_page; // @[MMU.scala 265:26]
  assign itlb_io_tlb_renew_bits_is_mega_page = iptw_io_ptw_o_bits_renew_is_mega_page; // @[MMU.scala 265:26]
  assign itlb_io_tlb_renew_bits_asid = iptw_io_ptw_o_bits_renew_asid; // @[MMU.scala 265:26]
  assign itlb_io_tlb_renew_bits_vpn_0 = iptw_io_ptw_o_bits_renew_vpn_0; // @[MMU.scala 265:26]
  assign itlb_io_tlb_renew_bits_vpn_1 = iptw_io_ptw_o_bits_renew_vpn_1; // @[MMU.scala 265:26]
  assign itlb_io_tlb_renew_bits_vpn_2 = iptw_io_ptw_o_bits_renew_vpn_2; // @[MMU.scala 265:26]
  assign itlb_io_sfence_vma = io_cmm_mmu_sfence_vma; // @[MMU.scala 298:22]
  assign dtlb_clock = clock;
  assign dtlb_reset = reset;
  assign dtlb_io_req_valid = io_lsu_mmu_valid; // @[MMU.scala 164:21]
  assign dtlb_io_req_bits_vaddr = io_lsu_mmu_bits_vaddr; // @[MMU.scala 165:21]
  assign dtlb_io_asid_i = io_cmm_mmu_satp[59:44]; // @[MMU.scala 166:37]
  assign dtlb_io_tlb_renew_valid = _dtlb_io_tlb_renew_valid_T & _io_mmu_lsu_valid_T_6 & ~dptw_io_ptw_o_bits_is_ptw_fail
     & _io_lsu_mmu_ready_T_3; // @[MMU.scala 269:110]
  assign dtlb_io_tlb_renew_bits_is_giga_page = dptw_io_ptw_o_bits_renew_is_giga_page; // @[MMU.scala 266:26]
  assign dtlb_io_tlb_renew_bits_is_mega_page = dptw_io_ptw_o_bits_renew_is_mega_page; // @[MMU.scala 266:26]
  assign dtlb_io_tlb_renew_bits_asid = dptw_io_ptw_o_bits_renew_asid; // @[MMU.scala 266:26]
  assign dtlb_io_tlb_renew_bits_vpn_0 = dptw_io_ptw_o_bits_renew_vpn_0; // @[MMU.scala 266:26]
  assign dtlb_io_tlb_renew_bits_vpn_1 = dptw_io_ptw_o_bits_renew_vpn_1; // @[MMU.scala 266:26]
  assign dtlb_io_tlb_renew_bits_vpn_2 = dptw_io_ptw_o_bits_renew_vpn_2; // @[MMU.scala 266:26]
  assign dtlb_io_sfence_vma = io_cmm_mmu_sfence_vma; // @[MMU.scala 299:22]
  assign iptw_clock = clock;
  assign iptw_reset = reset;
  assign iptw_io_ptw_i_valid = io_if_mmu_valid & ~itlb_io_is_hit & ~is_bypass_if & ~kill_iptw; // @[MMU.scala 180:76]
  assign iptw_io_ptw_i_bits_is_X = io_if_mmu_bits_is_X; // @[MMU.scala 181:23]
  assign iptw_io_ptw_i_bits_vaddr = io_if_mmu_bits_vaddr; // @[MMU.scala 181:23]
  assign iptw_io_ptw_o_ready = io_mmu_if_ready | kill_iptw | io_if_flush; // @[MMU.scala 259:55]
  assign iptw_io_cmm_mmu_satp = io_cmm_mmu_satp; // @[MMU.scala 174:19]
  assign iptw_io_cmm_mmu_sfence_vma = io_cmm_mmu_sfence_vma; // @[MMU.scala 174:19]
  assign iptw_io_ptw_access_valid = ~io_ptw_access_bits_source & io_ptw_access_valid; // @[MMU.scala 292:45 293:24 279:28]
  assign iptw_io_ptw_access_bits_opcode = ~io_ptw_access_bits_source ? io_ptw_access_bits_opcode : 3'h0; // @[MMU.scala 292:45 293:24 281:27]
  assign iptw_io_ptw_access_bits_size = ~io_ptw_access_bits_source ? io_ptw_access_bits_size : 3'h0; // @[MMU.scala 292:45 293:24 281:27]
  assign iptw_io_ptw_access_bits_data = ~io_ptw_access_bits_source ? io_ptw_access_bits_data : 64'h0; // @[MMU.scala 292:45 293:24 281:27]
  assign dptw_clock = clock;
  assign dptw_reset = reset;
  assign dptw_io_ptw_i_valid = io_lsu_mmu_valid & ~dtlb_io_is_hit & ~is_bypass_ls & _io_lsu_mmu_ready_T_3; // @[MMU.scala 183:77]
  assign dptw_io_ptw_i_bits_is_X = io_lsu_mmu_bits_is_X; // @[MMU.scala 184:23]
  assign dptw_io_ptw_i_bits_vaddr = io_lsu_mmu_bits_vaddr; // @[MMU.scala 184:23]
  assign dptw_io_ptw_o_ready = io_mmu_lsu_ready | kill_dptw | io_lsu_flush; // @[MMU.scala 262:55]
  assign dptw_io_cmm_mmu_satp = io_cmm_mmu_satp; // @[MMU.scala 175:19]
  assign dptw_io_cmm_mmu_sfence_vma = io_cmm_mmu_sfence_vma; // @[MMU.scala 175:19]
  assign dptw_io_ptw_access_valid = ~io_ptw_access_bits_source ? 1'h0 : _GEN_5; // @[MMU.scala 280:28 292:45]
  assign dptw_io_ptw_access_bits_opcode = ~io_ptw_access_bits_source ? 3'h0 : _GEN_6; // @[MMU.scala 282:27 292:45]
  assign dptw_io_ptw_access_bits_size = ~io_ptw_access_bits_source ? 3'h0 : _GEN_8; // @[MMU.scala 282:27 292:45]
  assign dptw_io_ptw_access_bits_data = ~io_ptw_access_bits_source ? 64'h0 : _GEN_12; // @[MMU.scala 282:27 292:45]
  always @(posedge clock) begin
    if (reset) begin // @[MMU.scala 141:26]
      kill_iptw <= 1'h0; // @[MMU.scala 141:26]
    end else begin
      kill_iptw <= _GEN_1;
    end
    if (reset) begin // @[MMU.scala 142:26]
      kill_dptw <= 1'h0; // @[MMU.scala 142:26]
    end else begin
      kill_dptw <= _GEN_3;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T == _io_lsu_mmu_ready_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MMU.scala:170 assert( io.lsu_mmu.fire === io.mmu_lsu.fire )\n"
            ); // @[MMU.scala 170:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T == _io_lsu_mmu_ready_T) & ~reset) begin
          $fatal; // @[MMU.scala 170:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_4 & ~(~(iptw_io_ptw_o_bits_is_X & iptw_io_ptw_o_valid & itlb_io_is_hit & _iptw_io_ptw_i_valid_T_4))
          ) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MMU.scala:220 assert( ~((iptw.io.ptw_o.bits.is_X & iptw.io.ptw_o.valid) & itlb.io.is_hit & ~kill_iptw )  )\n"
            ); // @[MMU.scala 220:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(iptw_io_ptw_o_bits_is_X & iptw_io_ptw_o_valid & itlb_io_is_hit & _iptw_io_ptw_i_valid_T_4)) & _T_4
          ) begin
          $fatal; // @[MMU.scala 220:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_4 & ~(~(_io_mmu_lsu_valid_T_7 & dtlb_io_is_hit & _io_lsu_mmu_ready_T_3))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MMU.scala:256 assert( ~((~dptw.io.ptw_o.bits.is_X & dptw.io.ptw_o.valid) & dtlb.io.is_hit & ~kill_dptw)  )\n"
            ); // @[MMU.scala 256:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_io_mmu_lsu_valid_T_7 & dtlb_io_is_hit & _io_lsu_mmu_ready_T_3)) & _T_4) begin
          $fatal; // @[MMU.scala 256:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_cmm_mmu_sfence_vma & _T_4 & ~(io_if_flush & io_lsu_flush)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MMU.scala:338 assert( io.if_flush & io.lsu_flush )\n"); // @[MMU.scala 338:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(io_if_flush & io_lsu_flush) & (io_cmm_mmu_sfence_vma & _T_4)) begin
          $fatal; // @[MMU.scala 338:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  kill_iptw = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  kill_dptw = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module diff(
  input  [63:0] io_diffXReg_0,
  input  [63:0] io_diffXReg_1,
  input  [63:0] io_diffXReg_2,
  input  [63:0] io_diffXReg_3,
  input  [63:0] io_diffXReg_4,
  input  [63:0] io_diffXReg_5,
  input  [63:0] io_diffXReg_6,
  input  [63:0] io_diffXReg_7,
  input  [63:0] io_diffXReg_8,
  input  [63:0] io_diffXReg_9,
  input  [63:0] io_diffXReg_10,
  input  [63:0] io_diffXReg_11,
  input  [63:0] io_diffXReg_12,
  input  [63:0] io_diffXReg_13,
  input  [63:0] io_diffXReg_14,
  input  [63:0] io_diffXReg_15,
  input  [63:0] io_diffXReg_16,
  input  [63:0] io_diffXReg_17,
  input  [63:0] io_diffXReg_18,
  input  [63:0] io_diffXReg_19,
  input  [63:0] io_diffXReg_20,
  input  [63:0] io_diffXReg_21,
  input  [63:0] io_diffXReg_22,
  input  [63:0] io_diffXReg_23,
  input  [63:0] io_diffXReg_24,
  input  [63:0] io_diffXReg_25,
  input  [63:0] io_diffXReg_26,
  input  [63:0] io_diffXReg_27,
  input  [63:0] io_diffXReg_28,
  input  [63:0] io_diffXReg_29,
  input  [63:0] io_diffXReg_30,
  input  [63:0] io_diffXReg_31,
  input  [64:0] io_diffFReg_0,
  input  [64:0] io_diffFReg_1,
  input  [64:0] io_diffFReg_2,
  input  [64:0] io_diffFReg_3,
  input  [64:0] io_diffFReg_4,
  input  [64:0] io_diffFReg_5,
  input  [64:0] io_diffFReg_6,
  input  [64:0] io_diffFReg_7,
  input  [64:0] io_diffFReg_8,
  input  [64:0] io_diffFReg_9,
  input  [64:0] io_diffFReg_10,
  input  [64:0] io_diffFReg_11,
  input  [64:0] io_diffFReg_12,
  input  [64:0] io_diffFReg_13,
  input  [64:0] io_diffFReg_14,
  input  [64:0] io_diffFReg_15,
  input  [64:0] io_diffFReg_16,
  input  [64:0] io_diffFReg_17,
  input  [64:0] io_diffFReg_18,
  input  [64:0] io_diffFReg_19,
  input  [64:0] io_diffFReg_20,
  input  [64:0] io_diffFReg_21,
  input  [64:0] io_diffFReg_22,
  input  [64:0] io_diffFReg_23,
  input  [64:0] io_diffFReg_24,
  input  [64:0] io_diffFReg_25,
  input  [64:0] io_diffFReg_26,
  input  [64:0] io_diffFReg_27,
  input  [64:0] io_diffFReg_28,
  input  [64:0] io_diffFReg_29,
  input  [64:0] io_diffFReg_30,
  input  [64:0] io_diffFReg_31,
  input  [63:0] io_commit_pc_0,
  input         io_commit_comfirm_0,
  input         io_commit_abort_0,
  input  [1:0]  io_commit_priv_lvl,
  input         io_commit_is_ecall_M,
  input         io_commit_is_ecall_S,
  input         io_commit_is_ecall_U,
  input  [63:0] io_csr_mstatus,
  input  [63:0] io_csr_mtvec,
  input  [63:0] io_csr_mscratch,
  input  [63:0] io_csr_mepc,
  input  [63:0] io_csr_mcause,
  input  [63:0] io_csr_mtval,
  input  [63:0] io_csr_mvendorid,
  input  [63:0] io_csr_marchid,
  input  [63:0] io_csr_mimpid,
  input  [63:0] io_csr_mhartid,
  input  [63:0] io_csr_misa,
  input  [63:0] io_csr_mie,
  input  [63:0] io_csr_mip,
  input  [63:0] io_csr_medeleg,
  input  [63:0] io_csr_mideleg,
  input  [63:0] io_csr_pmpcfg_0,
  input  [63:0] io_csr_pmpaddr_0,
  input  [63:0] io_csr_pmpaddr_1,
  input  [63:0] io_csr_pmpaddr_2,
  input  [63:0] io_csr_pmpaddr_3,
  input  [63:0] io_csr_pmpaddr_4,
  input  [63:0] io_csr_pmpaddr_5,
  input  [63:0] io_csr_pmpaddr_6,
  input  [63:0] io_csr_pmpaddr_7,
  input  [63:0] io_csr_stvec,
  input  [63:0] io_csr_sscratch,
  input  [63:0] io_csr_sepc,
  input  [63:0] io_csr_scause,
  input  [63:0] io_csr_stval,
  input  [63:0] io_csr_satp,
  input  [31:0] io_csr_fflags,
  input  [7:0]  io_csr_frm,
  input  [63:0] io_csr_mcycle,
  input  [63:0] io_csr_minstret,
  input  [63:0] io_csr_mhpmcounter_0,
  input  [63:0] io_csr_mhpmcounter_1,
  input  [63:0] io_csr_mhpmcounter_2,
  input  [63:0] io_csr_mhpmcounter_3,
  input  [63:0] io_csr_mhpmcounter_4,
  input  [63:0] io_csr_mhpmcounter_5,
  input  [63:0] io_csr_mhpmcounter_6,
  input  [63:0] io_csr_mhpmcounter_7,
  input  [63:0] io_csr_mhpmcounter_8,
  input  [63:0] io_csr_mhpmcounter_9,
  input  [63:0] io_csr_mhpmcounter_10,
  input  [63:0] io_csr_mhpmcounter_11,
  input  [63:0] io_csr_mhpmcounter_12,
  input  [63:0] io_csr_mhpmcounter_13,
  input  [63:0] io_csr_mhpmcounter_14,
  input  [63:0] io_csr_mhpmcounter_15,
  input  [63:0] io_csr_mhpmcounter_16,
  input  [63:0] io_csr_mhpmcounter_17,
  input  [63:0] io_csr_mhpmcounter_18,
  input  [63:0] io_csr_mhpmcounter_19,
  input  [63:0] io_csr_mhpmcounter_20,
  input  [63:0] io_csr_mhpmcounter_21,
  input  [63:0] io_csr_mhpmcounter_22,
  input  [63:0] io_csr_mhpmcounter_23,
  input  [63:0] io_csr_mhpmcounter_24,
  input  [63:0] io_csr_mhpmcounter_25,
  input  [63:0] io_csr_mhpmcounter_26,
  input  [63:0] io_csr_mhpmcounter_27,
  input  [63:0] io_csr_mhpmcounter_28,
  input  [63:0] io_csr_mhpmcounter_29,
  input  [63:0] io_csr_mhpmcounter_30,
  input  [63:0] io_csr_mhpmcounter_31
);
  wire [32:0] FReg1_ft_0_unbx_floats_0 = {io_diffFReg_0[31],io_diffFReg_0[52],io_diffFReg_0[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_0_unbx_isbox = &io_diffFReg_0[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_0_unbx_T = FReg1_ft_0_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_0_unbx = FReg1_ft_0_unbx_floats_0 | _FReg1_ft_0_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_0_ie_rawIn_exp = FReg1_ft_0_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_0_ie_rawIn_isZero = FReg1_ft_0_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_0_ie_rawIn_isSpecial = FReg1_ft_0_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_0_ie_rawIn__isNaN = FReg1_ft_0_ie_rawIn_isSpecial & FReg1_ft_0_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_0_ie_rawIn__isInf = FReg1_ft_0_ie_rawIn_isSpecial & ~FReg1_ft_0_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_0_ie_rawIn__sign = FReg1_ft_0_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_0_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_0_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_0_ie_rawIn_out_sig_T = ~FReg1_ft_0_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_0_ie_rawIn__sig = {1'h0,_FReg1_ft_0_ie_rawIn_out_sig_T,FReg1_ft_0_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_0_ie_isSubnormal = $signed(FReg1_ft_0_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_0_ie_denormShiftDist = 5'h1 - FReg1_ft_0_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_0_ie_denormFract_T_1 = FReg1_ft_0_ie_rawIn__sig[24:1] >> FReg1_ft_0_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_0_ie_denormFract = _FReg1_ft_0_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_0_ie_expOut_T_2 = FReg1_ft_0_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_0_ie_expOut_T_3 = FReg1_ft_0_ie_isSubnormal ? 8'h0 : _FReg1_ft_0_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_0_ie_expOut_T_4 = FReg1_ft_0_ie_rawIn__isNaN | FReg1_ft_0_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_0_ie_expOut_T_6 = _FReg1_ft_0_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_0_ie_expOut = _FReg1_ft_0_ie_expOut_T_3 | _FReg1_ft_0_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_0_ie_fractOut_T_1 = FReg1_ft_0_ie_rawIn__isInf ? 23'h0 : FReg1_ft_0_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_0_ie_fractOut = FReg1_ft_0_ie_isSubnormal ? FReg1_ft_0_ie_denormFract :
    _FReg1_ft_0_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_0_ie = {FReg1_ft_0_ie_rawIn__sign,FReg1_ft_0_ie_expOut,FReg1_ft_0_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_0_T_3 = FReg1_ft_0_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_1_unbx_floats_0 = {io_diffFReg_1[31],io_diffFReg_1[52],io_diffFReg_1[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_1_unbx_isbox = &io_diffFReg_1[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_1_unbx_T = FReg1_ft_1_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_1_unbx = FReg1_ft_1_unbx_floats_0 | _FReg1_ft_1_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_1_ie_rawIn_exp = FReg1_ft_1_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_1_ie_rawIn_isZero = FReg1_ft_1_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_1_ie_rawIn_isSpecial = FReg1_ft_1_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_1_ie_rawIn__isNaN = FReg1_ft_1_ie_rawIn_isSpecial & FReg1_ft_1_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_1_ie_rawIn__isInf = FReg1_ft_1_ie_rawIn_isSpecial & ~FReg1_ft_1_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_1_ie_rawIn__sign = FReg1_ft_1_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_1_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_1_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_1_ie_rawIn_out_sig_T = ~FReg1_ft_1_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_1_ie_rawIn__sig = {1'h0,_FReg1_ft_1_ie_rawIn_out_sig_T,FReg1_ft_1_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_1_ie_isSubnormal = $signed(FReg1_ft_1_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_1_ie_denormShiftDist = 5'h1 - FReg1_ft_1_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_1_ie_denormFract_T_1 = FReg1_ft_1_ie_rawIn__sig[24:1] >> FReg1_ft_1_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_1_ie_denormFract = _FReg1_ft_1_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_1_ie_expOut_T_2 = FReg1_ft_1_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_1_ie_expOut_T_3 = FReg1_ft_1_ie_isSubnormal ? 8'h0 : _FReg1_ft_1_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_1_ie_expOut_T_4 = FReg1_ft_1_ie_rawIn__isNaN | FReg1_ft_1_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_1_ie_expOut_T_6 = _FReg1_ft_1_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_1_ie_expOut = _FReg1_ft_1_ie_expOut_T_3 | _FReg1_ft_1_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_1_ie_fractOut_T_1 = FReg1_ft_1_ie_rawIn__isInf ? 23'h0 : FReg1_ft_1_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_1_ie_fractOut = FReg1_ft_1_ie_isSubnormal ? FReg1_ft_1_ie_denormFract :
    _FReg1_ft_1_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_1_ie = {FReg1_ft_1_ie_rawIn__sign,FReg1_ft_1_ie_expOut,FReg1_ft_1_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_1_T_3 = FReg1_ft_1_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_2_unbx_floats_0 = {io_diffFReg_2[31],io_diffFReg_2[52],io_diffFReg_2[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_2_unbx_isbox = &io_diffFReg_2[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_2_unbx_T = FReg1_ft_2_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_2_unbx = FReg1_ft_2_unbx_floats_0 | _FReg1_ft_2_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_2_ie_rawIn_exp = FReg1_ft_2_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_2_ie_rawIn_isZero = FReg1_ft_2_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_2_ie_rawIn_isSpecial = FReg1_ft_2_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_2_ie_rawIn__isNaN = FReg1_ft_2_ie_rawIn_isSpecial & FReg1_ft_2_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_2_ie_rawIn__isInf = FReg1_ft_2_ie_rawIn_isSpecial & ~FReg1_ft_2_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_2_ie_rawIn__sign = FReg1_ft_2_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_2_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_2_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_2_ie_rawIn_out_sig_T = ~FReg1_ft_2_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_2_ie_rawIn__sig = {1'h0,_FReg1_ft_2_ie_rawIn_out_sig_T,FReg1_ft_2_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_2_ie_isSubnormal = $signed(FReg1_ft_2_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_2_ie_denormShiftDist = 5'h1 - FReg1_ft_2_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_2_ie_denormFract_T_1 = FReg1_ft_2_ie_rawIn__sig[24:1] >> FReg1_ft_2_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_2_ie_denormFract = _FReg1_ft_2_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_2_ie_expOut_T_2 = FReg1_ft_2_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_2_ie_expOut_T_3 = FReg1_ft_2_ie_isSubnormal ? 8'h0 : _FReg1_ft_2_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_2_ie_expOut_T_4 = FReg1_ft_2_ie_rawIn__isNaN | FReg1_ft_2_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_2_ie_expOut_T_6 = _FReg1_ft_2_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_2_ie_expOut = _FReg1_ft_2_ie_expOut_T_3 | _FReg1_ft_2_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_2_ie_fractOut_T_1 = FReg1_ft_2_ie_rawIn__isInf ? 23'h0 : FReg1_ft_2_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_2_ie_fractOut = FReg1_ft_2_ie_isSubnormal ? FReg1_ft_2_ie_denormFract :
    _FReg1_ft_2_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_2_ie = {FReg1_ft_2_ie_rawIn__sign,FReg1_ft_2_ie_expOut,FReg1_ft_2_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_2_T_3 = FReg1_ft_2_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_3_unbx_floats_0 = {io_diffFReg_3[31],io_diffFReg_3[52],io_diffFReg_3[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_3_unbx_isbox = &io_diffFReg_3[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_3_unbx_T = FReg1_ft_3_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_3_unbx = FReg1_ft_3_unbx_floats_0 | _FReg1_ft_3_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_3_ie_rawIn_exp = FReg1_ft_3_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_3_ie_rawIn_isZero = FReg1_ft_3_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_3_ie_rawIn_isSpecial = FReg1_ft_3_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_3_ie_rawIn__isNaN = FReg1_ft_3_ie_rawIn_isSpecial & FReg1_ft_3_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_3_ie_rawIn__isInf = FReg1_ft_3_ie_rawIn_isSpecial & ~FReg1_ft_3_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_3_ie_rawIn__sign = FReg1_ft_3_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_3_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_3_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_3_ie_rawIn_out_sig_T = ~FReg1_ft_3_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_3_ie_rawIn__sig = {1'h0,_FReg1_ft_3_ie_rawIn_out_sig_T,FReg1_ft_3_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_3_ie_isSubnormal = $signed(FReg1_ft_3_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_3_ie_denormShiftDist = 5'h1 - FReg1_ft_3_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_3_ie_denormFract_T_1 = FReg1_ft_3_ie_rawIn__sig[24:1] >> FReg1_ft_3_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_3_ie_denormFract = _FReg1_ft_3_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_3_ie_expOut_T_2 = FReg1_ft_3_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_3_ie_expOut_T_3 = FReg1_ft_3_ie_isSubnormal ? 8'h0 : _FReg1_ft_3_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_3_ie_expOut_T_4 = FReg1_ft_3_ie_rawIn__isNaN | FReg1_ft_3_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_3_ie_expOut_T_6 = _FReg1_ft_3_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_3_ie_expOut = _FReg1_ft_3_ie_expOut_T_3 | _FReg1_ft_3_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_3_ie_fractOut_T_1 = FReg1_ft_3_ie_rawIn__isInf ? 23'h0 : FReg1_ft_3_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_3_ie_fractOut = FReg1_ft_3_ie_isSubnormal ? FReg1_ft_3_ie_denormFract :
    _FReg1_ft_3_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_3_ie = {FReg1_ft_3_ie_rawIn__sign,FReg1_ft_3_ie_expOut,FReg1_ft_3_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_3_T_3 = FReg1_ft_3_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_4_unbx_floats_0 = {io_diffFReg_4[31],io_diffFReg_4[52],io_diffFReg_4[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_4_unbx_isbox = &io_diffFReg_4[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_4_unbx_T = FReg1_ft_4_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_4_unbx = FReg1_ft_4_unbx_floats_0 | _FReg1_ft_4_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_4_ie_rawIn_exp = FReg1_ft_4_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_4_ie_rawIn_isZero = FReg1_ft_4_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_4_ie_rawIn_isSpecial = FReg1_ft_4_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_4_ie_rawIn__isNaN = FReg1_ft_4_ie_rawIn_isSpecial & FReg1_ft_4_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_4_ie_rawIn__isInf = FReg1_ft_4_ie_rawIn_isSpecial & ~FReg1_ft_4_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_4_ie_rawIn__sign = FReg1_ft_4_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_4_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_4_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_4_ie_rawIn_out_sig_T = ~FReg1_ft_4_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_4_ie_rawIn__sig = {1'h0,_FReg1_ft_4_ie_rawIn_out_sig_T,FReg1_ft_4_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_4_ie_isSubnormal = $signed(FReg1_ft_4_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_4_ie_denormShiftDist = 5'h1 - FReg1_ft_4_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_4_ie_denormFract_T_1 = FReg1_ft_4_ie_rawIn__sig[24:1] >> FReg1_ft_4_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_4_ie_denormFract = _FReg1_ft_4_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_4_ie_expOut_T_2 = FReg1_ft_4_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_4_ie_expOut_T_3 = FReg1_ft_4_ie_isSubnormal ? 8'h0 : _FReg1_ft_4_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_4_ie_expOut_T_4 = FReg1_ft_4_ie_rawIn__isNaN | FReg1_ft_4_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_4_ie_expOut_T_6 = _FReg1_ft_4_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_4_ie_expOut = _FReg1_ft_4_ie_expOut_T_3 | _FReg1_ft_4_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_4_ie_fractOut_T_1 = FReg1_ft_4_ie_rawIn__isInf ? 23'h0 : FReg1_ft_4_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_4_ie_fractOut = FReg1_ft_4_ie_isSubnormal ? FReg1_ft_4_ie_denormFract :
    _FReg1_ft_4_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_4_ie = {FReg1_ft_4_ie_rawIn__sign,FReg1_ft_4_ie_expOut,FReg1_ft_4_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_4_T_3 = FReg1_ft_4_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_5_unbx_floats_0 = {io_diffFReg_5[31],io_diffFReg_5[52],io_diffFReg_5[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_5_unbx_isbox = &io_diffFReg_5[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_5_unbx_T = FReg1_ft_5_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_5_unbx = FReg1_ft_5_unbx_floats_0 | _FReg1_ft_5_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_5_ie_rawIn_exp = FReg1_ft_5_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_5_ie_rawIn_isZero = FReg1_ft_5_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_5_ie_rawIn_isSpecial = FReg1_ft_5_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_5_ie_rawIn__isNaN = FReg1_ft_5_ie_rawIn_isSpecial & FReg1_ft_5_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_5_ie_rawIn__isInf = FReg1_ft_5_ie_rawIn_isSpecial & ~FReg1_ft_5_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_5_ie_rawIn__sign = FReg1_ft_5_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_5_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_5_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_5_ie_rawIn_out_sig_T = ~FReg1_ft_5_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_5_ie_rawIn__sig = {1'h0,_FReg1_ft_5_ie_rawIn_out_sig_T,FReg1_ft_5_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_5_ie_isSubnormal = $signed(FReg1_ft_5_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_5_ie_denormShiftDist = 5'h1 - FReg1_ft_5_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_5_ie_denormFract_T_1 = FReg1_ft_5_ie_rawIn__sig[24:1] >> FReg1_ft_5_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_5_ie_denormFract = _FReg1_ft_5_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_5_ie_expOut_T_2 = FReg1_ft_5_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_5_ie_expOut_T_3 = FReg1_ft_5_ie_isSubnormal ? 8'h0 : _FReg1_ft_5_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_5_ie_expOut_T_4 = FReg1_ft_5_ie_rawIn__isNaN | FReg1_ft_5_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_5_ie_expOut_T_6 = _FReg1_ft_5_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_5_ie_expOut = _FReg1_ft_5_ie_expOut_T_3 | _FReg1_ft_5_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_5_ie_fractOut_T_1 = FReg1_ft_5_ie_rawIn__isInf ? 23'h0 : FReg1_ft_5_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_5_ie_fractOut = FReg1_ft_5_ie_isSubnormal ? FReg1_ft_5_ie_denormFract :
    _FReg1_ft_5_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_5_ie = {FReg1_ft_5_ie_rawIn__sign,FReg1_ft_5_ie_expOut,FReg1_ft_5_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_5_T_3 = FReg1_ft_5_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_6_unbx_floats_0 = {io_diffFReg_6[31],io_diffFReg_6[52],io_diffFReg_6[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_6_unbx_isbox = &io_diffFReg_6[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_6_unbx_T = FReg1_ft_6_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_6_unbx = FReg1_ft_6_unbx_floats_0 | _FReg1_ft_6_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_6_ie_rawIn_exp = FReg1_ft_6_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_6_ie_rawIn_isZero = FReg1_ft_6_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_6_ie_rawIn_isSpecial = FReg1_ft_6_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_6_ie_rawIn__isNaN = FReg1_ft_6_ie_rawIn_isSpecial & FReg1_ft_6_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_6_ie_rawIn__isInf = FReg1_ft_6_ie_rawIn_isSpecial & ~FReg1_ft_6_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_6_ie_rawIn__sign = FReg1_ft_6_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_6_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_6_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_6_ie_rawIn_out_sig_T = ~FReg1_ft_6_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_6_ie_rawIn__sig = {1'h0,_FReg1_ft_6_ie_rawIn_out_sig_T,FReg1_ft_6_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_6_ie_isSubnormal = $signed(FReg1_ft_6_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_6_ie_denormShiftDist = 5'h1 - FReg1_ft_6_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_6_ie_denormFract_T_1 = FReg1_ft_6_ie_rawIn__sig[24:1] >> FReg1_ft_6_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_6_ie_denormFract = _FReg1_ft_6_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_6_ie_expOut_T_2 = FReg1_ft_6_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_6_ie_expOut_T_3 = FReg1_ft_6_ie_isSubnormal ? 8'h0 : _FReg1_ft_6_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_6_ie_expOut_T_4 = FReg1_ft_6_ie_rawIn__isNaN | FReg1_ft_6_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_6_ie_expOut_T_6 = _FReg1_ft_6_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_6_ie_expOut = _FReg1_ft_6_ie_expOut_T_3 | _FReg1_ft_6_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_6_ie_fractOut_T_1 = FReg1_ft_6_ie_rawIn__isInf ? 23'h0 : FReg1_ft_6_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_6_ie_fractOut = FReg1_ft_6_ie_isSubnormal ? FReg1_ft_6_ie_denormFract :
    _FReg1_ft_6_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_6_ie = {FReg1_ft_6_ie_rawIn__sign,FReg1_ft_6_ie_expOut,FReg1_ft_6_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_6_T_3 = FReg1_ft_6_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_7_unbx_floats_0 = {io_diffFReg_7[31],io_diffFReg_7[52],io_diffFReg_7[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_7_unbx_isbox = &io_diffFReg_7[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_7_unbx_T = FReg1_ft_7_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_7_unbx = FReg1_ft_7_unbx_floats_0 | _FReg1_ft_7_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_7_ie_rawIn_exp = FReg1_ft_7_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_7_ie_rawIn_isZero = FReg1_ft_7_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_7_ie_rawIn_isSpecial = FReg1_ft_7_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_7_ie_rawIn__isNaN = FReg1_ft_7_ie_rawIn_isSpecial & FReg1_ft_7_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_7_ie_rawIn__isInf = FReg1_ft_7_ie_rawIn_isSpecial & ~FReg1_ft_7_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_7_ie_rawIn__sign = FReg1_ft_7_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_7_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_7_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_7_ie_rawIn_out_sig_T = ~FReg1_ft_7_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_7_ie_rawIn__sig = {1'h0,_FReg1_ft_7_ie_rawIn_out_sig_T,FReg1_ft_7_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_7_ie_isSubnormal = $signed(FReg1_ft_7_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_7_ie_denormShiftDist = 5'h1 - FReg1_ft_7_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_7_ie_denormFract_T_1 = FReg1_ft_7_ie_rawIn__sig[24:1] >> FReg1_ft_7_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_7_ie_denormFract = _FReg1_ft_7_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_7_ie_expOut_T_2 = FReg1_ft_7_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_7_ie_expOut_T_3 = FReg1_ft_7_ie_isSubnormal ? 8'h0 : _FReg1_ft_7_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_7_ie_expOut_T_4 = FReg1_ft_7_ie_rawIn__isNaN | FReg1_ft_7_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_7_ie_expOut_T_6 = _FReg1_ft_7_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_7_ie_expOut = _FReg1_ft_7_ie_expOut_T_3 | _FReg1_ft_7_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_7_ie_fractOut_T_1 = FReg1_ft_7_ie_rawIn__isInf ? 23'h0 : FReg1_ft_7_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_7_ie_fractOut = FReg1_ft_7_ie_isSubnormal ? FReg1_ft_7_ie_denormFract :
    _FReg1_ft_7_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_7_ie = {FReg1_ft_7_ie_rawIn__sign,FReg1_ft_7_ie_expOut,FReg1_ft_7_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_7_T_3 = FReg1_ft_7_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_0_unbx_floats_0 = {io_diffFReg_8[31],io_diffFReg_8[52],io_diffFReg_8[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_0_unbx_isbox = &io_diffFReg_8[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_0_unbx_T = FReg1_fs_0_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_0_unbx = FReg1_fs_0_unbx_floats_0 | _FReg1_fs_0_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_0_ie_rawIn_exp = FReg1_fs_0_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_0_ie_rawIn_isZero = FReg1_fs_0_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_0_ie_rawIn_isSpecial = FReg1_fs_0_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_0_ie_rawIn__isNaN = FReg1_fs_0_ie_rawIn_isSpecial & FReg1_fs_0_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_0_ie_rawIn__isInf = FReg1_fs_0_ie_rawIn_isSpecial & ~FReg1_fs_0_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_0_ie_rawIn__sign = FReg1_fs_0_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_0_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_0_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_0_ie_rawIn_out_sig_T = ~FReg1_fs_0_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_0_ie_rawIn__sig = {1'h0,_FReg1_fs_0_ie_rawIn_out_sig_T,FReg1_fs_0_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_0_ie_isSubnormal = $signed(FReg1_fs_0_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_0_ie_denormShiftDist = 5'h1 - FReg1_fs_0_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_0_ie_denormFract_T_1 = FReg1_fs_0_ie_rawIn__sig[24:1] >> FReg1_fs_0_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_0_ie_denormFract = _FReg1_fs_0_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_0_ie_expOut_T_2 = FReg1_fs_0_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_0_ie_expOut_T_3 = FReg1_fs_0_ie_isSubnormal ? 8'h0 : _FReg1_fs_0_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_0_ie_expOut_T_4 = FReg1_fs_0_ie_rawIn__isNaN | FReg1_fs_0_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_0_ie_expOut_T_6 = _FReg1_fs_0_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_0_ie_expOut = _FReg1_fs_0_ie_expOut_T_3 | _FReg1_fs_0_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_0_ie_fractOut_T_1 = FReg1_fs_0_ie_rawIn__isInf ? 23'h0 : FReg1_fs_0_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_0_ie_fractOut = FReg1_fs_0_ie_isSubnormal ? FReg1_fs_0_ie_denormFract :
    _FReg1_fs_0_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_0_ie = {FReg1_fs_0_ie_rawIn__sign,FReg1_fs_0_ie_expOut,FReg1_fs_0_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_0_T_3 = FReg1_fs_0_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_1_unbx_floats_0 = {io_diffFReg_9[31],io_diffFReg_9[52],io_diffFReg_9[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_1_unbx_isbox = &io_diffFReg_9[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_1_unbx_T = FReg1_fs_1_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_1_unbx = FReg1_fs_1_unbx_floats_0 | _FReg1_fs_1_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_1_ie_rawIn_exp = FReg1_fs_1_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_1_ie_rawIn_isZero = FReg1_fs_1_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_1_ie_rawIn_isSpecial = FReg1_fs_1_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_1_ie_rawIn__isNaN = FReg1_fs_1_ie_rawIn_isSpecial & FReg1_fs_1_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_1_ie_rawIn__isInf = FReg1_fs_1_ie_rawIn_isSpecial & ~FReg1_fs_1_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_1_ie_rawIn__sign = FReg1_fs_1_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_1_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_1_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_1_ie_rawIn_out_sig_T = ~FReg1_fs_1_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_1_ie_rawIn__sig = {1'h0,_FReg1_fs_1_ie_rawIn_out_sig_T,FReg1_fs_1_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_1_ie_isSubnormal = $signed(FReg1_fs_1_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_1_ie_denormShiftDist = 5'h1 - FReg1_fs_1_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_1_ie_denormFract_T_1 = FReg1_fs_1_ie_rawIn__sig[24:1] >> FReg1_fs_1_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_1_ie_denormFract = _FReg1_fs_1_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_1_ie_expOut_T_2 = FReg1_fs_1_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_1_ie_expOut_T_3 = FReg1_fs_1_ie_isSubnormal ? 8'h0 : _FReg1_fs_1_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_1_ie_expOut_T_4 = FReg1_fs_1_ie_rawIn__isNaN | FReg1_fs_1_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_1_ie_expOut_T_6 = _FReg1_fs_1_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_1_ie_expOut = _FReg1_fs_1_ie_expOut_T_3 | _FReg1_fs_1_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_1_ie_fractOut_T_1 = FReg1_fs_1_ie_rawIn__isInf ? 23'h0 : FReg1_fs_1_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_1_ie_fractOut = FReg1_fs_1_ie_isSubnormal ? FReg1_fs_1_ie_denormFract :
    _FReg1_fs_1_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_1_ie = {FReg1_fs_1_ie_rawIn__sign,FReg1_fs_1_ie_expOut,FReg1_fs_1_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_1_T_3 = FReg1_fs_1_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fa_0_unbx_floats_0 = {io_diffFReg_10[31],io_diffFReg_10[52],io_diffFReg_10[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_0_unbx_isbox = &io_diffFReg_10[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fa_0_unbx_T = FReg1_fa_0_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fa_0_unbx = FReg1_fa_0_unbx_floats_0 | _FReg1_fa_0_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fa_0_ie_rawIn_exp = FReg1_fa_0_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fa_0_ie_rawIn_isZero = FReg1_fa_0_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fa_0_ie_rawIn_isSpecial = FReg1_fa_0_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fa_0_ie_rawIn__isNaN = FReg1_fa_0_ie_rawIn_isSpecial & FReg1_fa_0_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fa_0_ie_rawIn__isInf = FReg1_fa_0_ie_rawIn_isSpecial & ~FReg1_fa_0_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fa_0_ie_rawIn__sign = FReg1_fa_0_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fa_0_ie_rawIn__sExp = {1'b0,$signed(FReg1_fa_0_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fa_0_ie_rawIn_out_sig_T = ~FReg1_fa_0_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fa_0_ie_rawIn__sig = {1'h0,_FReg1_fa_0_ie_rawIn_out_sig_T,FReg1_fa_0_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_0_ie_isSubnormal = $signed(FReg1_fa_0_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fa_0_ie_denormShiftDist = 5'h1 - FReg1_fa_0_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fa_0_ie_denormFract_T_1 = FReg1_fa_0_ie_rawIn__sig[24:1] >> FReg1_fa_0_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fa_0_ie_denormFract = _FReg1_fa_0_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fa_0_ie_expOut_T_2 = FReg1_fa_0_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fa_0_ie_expOut_T_3 = FReg1_fa_0_ie_isSubnormal ? 8'h0 : _FReg1_fa_0_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fa_0_ie_expOut_T_4 = FReg1_fa_0_ie_rawIn__isNaN | FReg1_fa_0_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fa_0_ie_expOut_T_6 = _FReg1_fa_0_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fa_0_ie_expOut = _FReg1_fa_0_ie_expOut_T_3 | _FReg1_fa_0_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fa_0_ie_fractOut_T_1 = FReg1_fa_0_ie_rawIn__isInf ? 23'h0 : FReg1_fa_0_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fa_0_ie_fractOut = FReg1_fa_0_ie_isSubnormal ? FReg1_fa_0_ie_denormFract :
    _FReg1_fa_0_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fa_0_ie = {FReg1_fa_0_ie_rawIn__sign,FReg1_fa_0_ie_expOut,FReg1_fa_0_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fa_0_T_3 = FReg1_fa_0_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fa_1_unbx_floats_0 = {io_diffFReg_11[31],io_diffFReg_11[52],io_diffFReg_11[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_1_unbx_isbox = &io_diffFReg_11[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fa_1_unbx_T = FReg1_fa_1_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fa_1_unbx = FReg1_fa_1_unbx_floats_0 | _FReg1_fa_1_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fa_1_ie_rawIn_exp = FReg1_fa_1_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fa_1_ie_rawIn_isZero = FReg1_fa_1_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fa_1_ie_rawIn_isSpecial = FReg1_fa_1_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fa_1_ie_rawIn__isNaN = FReg1_fa_1_ie_rawIn_isSpecial & FReg1_fa_1_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fa_1_ie_rawIn__isInf = FReg1_fa_1_ie_rawIn_isSpecial & ~FReg1_fa_1_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fa_1_ie_rawIn__sign = FReg1_fa_1_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fa_1_ie_rawIn__sExp = {1'b0,$signed(FReg1_fa_1_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fa_1_ie_rawIn_out_sig_T = ~FReg1_fa_1_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fa_1_ie_rawIn__sig = {1'h0,_FReg1_fa_1_ie_rawIn_out_sig_T,FReg1_fa_1_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_1_ie_isSubnormal = $signed(FReg1_fa_1_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fa_1_ie_denormShiftDist = 5'h1 - FReg1_fa_1_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fa_1_ie_denormFract_T_1 = FReg1_fa_1_ie_rawIn__sig[24:1] >> FReg1_fa_1_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fa_1_ie_denormFract = _FReg1_fa_1_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fa_1_ie_expOut_T_2 = FReg1_fa_1_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fa_1_ie_expOut_T_3 = FReg1_fa_1_ie_isSubnormal ? 8'h0 : _FReg1_fa_1_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fa_1_ie_expOut_T_4 = FReg1_fa_1_ie_rawIn__isNaN | FReg1_fa_1_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fa_1_ie_expOut_T_6 = _FReg1_fa_1_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fa_1_ie_expOut = _FReg1_fa_1_ie_expOut_T_3 | _FReg1_fa_1_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fa_1_ie_fractOut_T_1 = FReg1_fa_1_ie_rawIn__isInf ? 23'h0 : FReg1_fa_1_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fa_1_ie_fractOut = FReg1_fa_1_ie_isSubnormal ? FReg1_fa_1_ie_denormFract :
    _FReg1_fa_1_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fa_1_ie = {FReg1_fa_1_ie_rawIn__sign,FReg1_fa_1_ie_expOut,FReg1_fa_1_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fa_1_T_3 = FReg1_fa_1_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fa_2_unbx_floats_0 = {io_diffFReg_12[31],io_diffFReg_12[52],io_diffFReg_12[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_2_unbx_isbox = &io_diffFReg_12[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fa_2_unbx_T = FReg1_fa_2_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fa_2_unbx = FReg1_fa_2_unbx_floats_0 | _FReg1_fa_2_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fa_2_ie_rawIn_exp = FReg1_fa_2_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fa_2_ie_rawIn_isZero = FReg1_fa_2_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fa_2_ie_rawIn_isSpecial = FReg1_fa_2_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fa_2_ie_rawIn__isNaN = FReg1_fa_2_ie_rawIn_isSpecial & FReg1_fa_2_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fa_2_ie_rawIn__isInf = FReg1_fa_2_ie_rawIn_isSpecial & ~FReg1_fa_2_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fa_2_ie_rawIn__sign = FReg1_fa_2_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fa_2_ie_rawIn__sExp = {1'b0,$signed(FReg1_fa_2_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fa_2_ie_rawIn_out_sig_T = ~FReg1_fa_2_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fa_2_ie_rawIn__sig = {1'h0,_FReg1_fa_2_ie_rawIn_out_sig_T,FReg1_fa_2_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_2_ie_isSubnormal = $signed(FReg1_fa_2_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fa_2_ie_denormShiftDist = 5'h1 - FReg1_fa_2_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fa_2_ie_denormFract_T_1 = FReg1_fa_2_ie_rawIn__sig[24:1] >> FReg1_fa_2_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fa_2_ie_denormFract = _FReg1_fa_2_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fa_2_ie_expOut_T_2 = FReg1_fa_2_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fa_2_ie_expOut_T_3 = FReg1_fa_2_ie_isSubnormal ? 8'h0 : _FReg1_fa_2_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fa_2_ie_expOut_T_4 = FReg1_fa_2_ie_rawIn__isNaN | FReg1_fa_2_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fa_2_ie_expOut_T_6 = _FReg1_fa_2_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fa_2_ie_expOut = _FReg1_fa_2_ie_expOut_T_3 | _FReg1_fa_2_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fa_2_ie_fractOut_T_1 = FReg1_fa_2_ie_rawIn__isInf ? 23'h0 : FReg1_fa_2_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fa_2_ie_fractOut = FReg1_fa_2_ie_isSubnormal ? FReg1_fa_2_ie_denormFract :
    _FReg1_fa_2_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fa_2_ie = {FReg1_fa_2_ie_rawIn__sign,FReg1_fa_2_ie_expOut,FReg1_fa_2_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fa_2_T_3 = FReg1_fa_2_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fa_3_unbx_floats_0 = {io_diffFReg_13[31],io_diffFReg_13[52],io_diffFReg_13[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_3_unbx_isbox = &io_diffFReg_13[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fa_3_unbx_T = FReg1_fa_3_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fa_3_unbx = FReg1_fa_3_unbx_floats_0 | _FReg1_fa_3_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fa_3_ie_rawIn_exp = FReg1_fa_3_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fa_3_ie_rawIn_isZero = FReg1_fa_3_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fa_3_ie_rawIn_isSpecial = FReg1_fa_3_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fa_3_ie_rawIn__isNaN = FReg1_fa_3_ie_rawIn_isSpecial & FReg1_fa_3_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fa_3_ie_rawIn__isInf = FReg1_fa_3_ie_rawIn_isSpecial & ~FReg1_fa_3_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fa_3_ie_rawIn__sign = FReg1_fa_3_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fa_3_ie_rawIn__sExp = {1'b0,$signed(FReg1_fa_3_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fa_3_ie_rawIn_out_sig_T = ~FReg1_fa_3_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fa_3_ie_rawIn__sig = {1'h0,_FReg1_fa_3_ie_rawIn_out_sig_T,FReg1_fa_3_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_3_ie_isSubnormal = $signed(FReg1_fa_3_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fa_3_ie_denormShiftDist = 5'h1 - FReg1_fa_3_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fa_3_ie_denormFract_T_1 = FReg1_fa_3_ie_rawIn__sig[24:1] >> FReg1_fa_3_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fa_3_ie_denormFract = _FReg1_fa_3_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fa_3_ie_expOut_T_2 = FReg1_fa_3_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fa_3_ie_expOut_T_3 = FReg1_fa_3_ie_isSubnormal ? 8'h0 : _FReg1_fa_3_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fa_3_ie_expOut_T_4 = FReg1_fa_3_ie_rawIn__isNaN | FReg1_fa_3_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fa_3_ie_expOut_T_6 = _FReg1_fa_3_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fa_3_ie_expOut = _FReg1_fa_3_ie_expOut_T_3 | _FReg1_fa_3_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fa_3_ie_fractOut_T_1 = FReg1_fa_3_ie_rawIn__isInf ? 23'h0 : FReg1_fa_3_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fa_3_ie_fractOut = FReg1_fa_3_ie_isSubnormal ? FReg1_fa_3_ie_denormFract :
    _FReg1_fa_3_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fa_3_ie = {FReg1_fa_3_ie_rawIn__sign,FReg1_fa_3_ie_expOut,FReg1_fa_3_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fa_3_T_3 = FReg1_fa_3_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fa_4_unbx_floats_0 = {io_diffFReg_14[31],io_diffFReg_14[52],io_diffFReg_14[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_4_unbx_isbox = &io_diffFReg_14[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fa_4_unbx_T = FReg1_fa_4_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fa_4_unbx = FReg1_fa_4_unbx_floats_0 | _FReg1_fa_4_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fa_4_ie_rawIn_exp = FReg1_fa_4_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fa_4_ie_rawIn_isZero = FReg1_fa_4_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fa_4_ie_rawIn_isSpecial = FReg1_fa_4_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fa_4_ie_rawIn__isNaN = FReg1_fa_4_ie_rawIn_isSpecial & FReg1_fa_4_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fa_4_ie_rawIn__isInf = FReg1_fa_4_ie_rawIn_isSpecial & ~FReg1_fa_4_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fa_4_ie_rawIn__sign = FReg1_fa_4_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fa_4_ie_rawIn__sExp = {1'b0,$signed(FReg1_fa_4_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fa_4_ie_rawIn_out_sig_T = ~FReg1_fa_4_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fa_4_ie_rawIn__sig = {1'h0,_FReg1_fa_4_ie_rawIn_out_sig_T,FReg1_fa_4_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_4_ie_isSubnormal = $signed(FReg1_fa_4_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fa_4_ie_denormShiftDist = 5'h1 - FReg1_fa_4_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fa_4_ie_denormFract_T_1 = FReg1_fa_4_ie_rawIn__sig[24:1] >> FReg1_fa_4_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fa_4_ie_denormFract = _FReg1_fa_4_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fa_4_ie_expOut_T_2 = FReg1_fa_4_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fa_4_ie_expOut_T_3 = FReg1_fa_4_ie_isSubnormal ? 8'h0 : _FReg1_fa_4_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fa_4_ie_expOut_T_4 = FReg1_fa_4_ie_rawIn__isNaN | FReg1_fa_4_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fa_4_ie_expOut_T_6 = _FReg1_fa_4_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fa_4_ie_expOut = _FReg1_fa_4_ie_expOut_T_3 | _FReg1_fa_4_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fa_4_ie_fractOut_T_1 = FReg1_fa_4_ie_rawIn__isInf ? 23'h0 : FReg1_fa_4_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fa_4_ie_fractOut = FReg1_fa_4_ie_isSubnormal ? FReg1_fa_4_ie_denormFract :
    _FReg1_fa_4_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fa_4_ie = {FReg1_fa_4_ie_rawIn__sign,FReg1_fa_4_ie_expOut,FReg1_fa_4_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fa_4_T_3 = FReg1_fa_4_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fa_5_unbx_floats_0 = {io_diffFReg_15[31],io_diffFReg_15[52],io_diffFReg_15[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_5_unbx_isbox = &io_diffFReg_15[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fa_5_unbx_T = FReg1_fa_5_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fa_5_unbx = FReg1_fa_5_unbx_floats_0 | _FReg1_fa_5_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fa_5_ie_rawIn_exp = FReg1_fa_5_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fa_5_ie_rawIn_isZero = FReg1_fa_5_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fa_5_ie_rawIn_isSpecial = FReg1_fa_5_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fa_5_ie_rawIn__isNaN = FReg1_fa_5_ie_rawIn_isSpecial & FReg1_fa_5_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fa_5_ie_rawIn__isInf = FReg1_fa_5_ie_rawIn_isSpecial & ~FReg1_fa_5_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fa_5_ie_rawIn__sign = FReg1_fa_5_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fa_5_ie_rawIn__sExp = {1'b0,$signed(FReg1_fa_5_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fa_5_ie_rawIn_out_sig_T = ~FReg1_fa_5_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fa_5_ie_rawIn__sig = {1'h0,_FReg1_fa_5_ie_rawIn_out_sig_T,FReg1_fa_5_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_5_ie_isSubnormal = $signed(FReg1_fa_5_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fa_5_ie_denormShiftDist = 5'h1 - FReg1_fa_5_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fa_5_ie_denormFract_T_1 = FReg1_fa_5_ie_rawIn__sig[24:1] >> FReg1_fa_5_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fa_5_ie_denormFract = _FReg1_fa_5_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fa_5_ie_expOut_T_2 = FReg1_fa_5_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fa_5_ie_expOut_T_3 = FReg1_fa_5_ie_isSubnormal ? 8'h0 : _FReg1_fa_5_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fa_5_ie_expOut_T_4 = FReg1_fa_5_ie_rawIn__isNaN | FReg1_fa_5_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fa_5_ie_expOut_T_6 = _FReg1_fa_5_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fa_5_ie_expOut = _FReg1_fa_5_ie_expOut_T_3 | _FReg1_fa_5_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fa_5_ie_fractOut_T_1 = FReg1_fa_5_ie_rawIn__isInf ? 23'h0 : FReg1_fa_5_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fa_5_ie_fractOut = FReg1_fa_5_ie_isSubnormal ? FReg1_fa_5_ie_denormFract :
    _FReg1_fa_5_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fa_5_ie = {FReg1_fa_5_ie_rawIn__sign,FReg1_fa_5_ie_expOut,FReg1_fa_5_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fa_5_T_3 = FReg1_fa_5_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fa_6_unbx_floats_0 = {io_diffFReg_16[31],io_diffFReg_16[52],io_diffFReg_16[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_6_unbx_isbox = &io_diffFReg_16[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fa_6_unbx_T = FReg1_fa_6_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fa_6_unbx = FReg1_fa_6_unbx_floats_0 | _FReg1_fa_6_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fa_6_ie_rawIn_exp = FReg1_fa_6_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fa_6_ie_rawIn_isZero = FReg1_fa_6_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fa_6_ie_rawIn_isSpecial = FReg1_fa_6_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fa_6_ie_rawIn__isNaN = FReg1_fa_6_ie_rawIn_isSpecial & FReg1_fa_6_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fa_6_ie_rawIn__isInf = FReg1_fa_6_ie_rawIn_isSpecial & ~FReg1_fa_6_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fa_6_ie_rawIn__sign = FReg1_fa_6_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fa_6_ie_rawIn__sExp = {1'b0,$signed(FReg1_fa_6_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fa_6_ie_rawIn_out_sig_T = ~FReg1_fa_6_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fa_6_ie_rawIn__sig = {1'h0,_FReg1_fa_6_ie_rawIn_out_sig_T,FReg1_fa_6_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_6_ie_isSubnormal = $signed(FReg1_fa_6_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fa_6_ie_denormShiftDist = 5'h1 - FReg1_fa_6_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fa_6_ie_denormFract_T_1 = FReg1_fa_6_ie_rawIn__sig[24:1] >> FReg1_fa_6_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fa_6_ie_denormFract = _FReg1_fa_6_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fa_6_ie_expOut_T_2 = FReg1_fa_6_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fa_6_ie_expOut_T_3 = FReg1_fa_6_ie_isSubnormal ? 8'h0 : _FReg1_fa_6_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fa_6_ie_expOut_T_4 = FReg1_fa_6_ie_rawIn__isNaN | FReg1_fa_6_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fa_6_ie_expOut_T_6 = _FReg1_fa_6_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fa_6_ie_expOut = _FReg1_fa_6_ie_expOut_T_3 | _FReg1_fa_6_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fa_6_ie_fractOut_T_1 = FReg1_fa_6_ie_rawIn__isInf ? 23'h0 : FReg1_fa_6_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fa_6_ie_fractOut = FReg1_fa_6_ie_isSubnormal ? FReg1_fa_6_ie_denormFract :
    _FReg1_fa_6_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fa_6_ie = {FReg1_fa_6_ie_rawIn__sign,FReg1_fa_6_ie_expOut,FReg1_fa_6_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fa_6_T_3 = FReg1_fa_6_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fa_7_unbx_floats_0 = {io_diffFReg_17[31],io_diffFReg_17[52],io_diffFReg_17[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_7_unbx_isbox = &io_diffFReg_17[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fa_7_unbx_T = FReg1_fa_7_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fa_7_unbx = FReg1_fa_7_unbx_floats_0 | _FReg1_fa_7_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fa_7_ie_rawIn_exp = FReg1_fa_7_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fa_7_ie_rawIn_isZero = FReg1_fa_7_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fa_7_ie_rawIn_isSpecial = FReg1_fa_7_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fa_7_ie_rawIn__isNaN = FReg1_fa_7_ie_rawIn_isSpecial & FReg1_fa_7_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fa_7_ie_rawIn__isInf = FReg1_fa_7_ie_rawIn_isSpecial & ~FReg1_fa_7_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fa_7_ie_rawIn__sign = FReg1_fa_7_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fa_7_ie_rawIn__sExp = {1'b0,$signed(FReg1_fa_7_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fa_7_ie_rawIn_out_sig_T = ~FReg1_fa_7_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fa_7_ie_rawIn__sig = {1'h0,_FReg1_fa_7_ie_rawIn_out_sig_T,FReg1_fa_7_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fa_7_ie_isSubnormal = $signed(FReg1_fa_7_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fa_7_ie_denormShiftDist = 5'h1 - FReg1_fa_7_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fa_7_ie_denormFract_T_1 = FReg1_fa_7_ie_rawIn__sig[24:1] >> FReg1_fa_7_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fa_7_ie_denormFract = _FReg1_fa_7_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fa_7_ie_expOut_T_2 = FReg1_fa_7_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fa_7_ie_expOut_T_3 = FReg1_fa_7_ie_isSubnormal ? 8'h0 : _FReg1_fa_7_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fa_7_ie_expOut_T_4 = FReg1_fa_7_ie_rawIn__isNaN | FReg1_fa_7_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fa_7_ie_expOut_T_6 = _FReg1_fa_7_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fa_7_ie_expOut = _FReg1_fa_7_ie_expOut_T_3 | _FReg1_fa_7_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fa_7_ie_fractOut_T_1 = FReg1_fa_7_ie_rawIn__isInf ? 23'h0 : FReg1_fa_7_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fa_7_ie_fractOut = FReg1_fa_7_ie_isSubnormal ? FReg1_fa_7_ie_denormFract :
    _FReg1_fa_7_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fa_7_ie = {FReg1_fa_7_ie_rawIn__sign,FReg1_fa_7_ie_expOut,FReg1_fa_7_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fa_7_T_3 = FReg1_fa_7_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_2_unbx_floats_0 = {io_diffFReg_18[31],io_diffFReg_18[52],io_diffFReg_18[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_2_unbx_isbox = &io_diffFReg_18[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_2_unbx_T = FReg1_fs_2_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_2_unbx = FReg1_fs_2_unbx_floats_0 | _FReg1_fs_2_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_2_ie_rawIn_exp = FReg1_fs_2_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_2_ie_rawIn_isZero = FReg1_fs_2_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_2_ie_rawIn_isSpecial = FReg1_fs_2_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_2_ie_rawIn__isNaN = FReg1_fs_2_ie_rawIn_isSpecial & FReg1_fs_2_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_2_ie_rawIn__isInf = FReg1_fs_2_ie_rawIn_isSpecial & ~FReg1_fs_2_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_2_ie_rawIn__sign = FReg1_fs_2_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_2_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_2_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_2_ie_rawIn_out_sig_T = ~FReg1_fs_2_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_2_ie_rawIn__sig = {1'h0,_FReg1_fs_2_ie_rawIn_out_sig_T,FReg1_fs_2_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_2_ie_isSubnormal = $signed(FReg1_fs_2_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_2_ie_denormShiftDist = 5'h1 - FReg1_fs_2_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_2_ie_denormFract_T_1 = FReg1_fs_2_ie_rawIn__sig[24:1] >> FReg1_fs_2_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_2_ie_denormFract = _FReg1_fs_2_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_2_ie_expOut_T_2 = FReg1_fs_2_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_2_ie_expOut_T_3 = FReg1_fs_2_ie_isSubnormal ? 8'h0 : _FReg1_fs_2_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_2_ie_expOut_T_4 = FReg1_fs_2_ie_rawIn__isNaN | FReg1_fs_2_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_2_ie_expOut_T_6 = _FReg1_fs_2_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_2_ie_expOut = _FReg1_fs_2_ie_expOut_T_3 | _FReg1_fs_2_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_2_ie_fractOut_T_1 = FReg1_fs_2_ie_rawIn__isInf ? 23'h0 : FReg1_fs_2_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_2_ie_fractOut = FReg1_fs_2_ie_isSubnormal ? FReg1_fs_2_ie_denormFract :
    _FReg1_fs_2_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_2_ie = {FReg1_fs_2_ie_rawIn__sign,FReg1_fs_2_ie_expOut,FReg1_fs_2_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_2_T_3 = FReg1_fs_2_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_3_unbx_floats_0 = {io_diffFReg_19[31],io_diffFReg_19[52],io_diffFReg_19[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_3_unbx_isbox = &io_diffFReg_19[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_3_unbx_T = FReg1_fs_3_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_3_unbx = FReg1_fs_3_unbx_floats_0 | _FReg1_fs_3_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_3_ie_rawIn_exp = FReg1_fs_3_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_3_ie_rawIn_isZero = FReg1_fs_3_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_3_ie_rawIn_isSpecial = FReg1_fs_3_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_3_ie_rawIn__isNaN = FReg1_fs_3_ie_rawIn_isSpecial & FReg1_fs_3_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_3_ie_rawIn__isInf = FReg1_fs_3_ie_rawIn_isSpecial & ~FReg1_fs_3_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_3_ie_rawIn__sign = FReg1_fs_3_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_3_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_3_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_3_ie_rawIn_out_sig_T = ~FReg1_fs_3_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_3_ie_rawIn__sig = {1'h0,_FReg1_fs_3_ie_rawIn_out_sig_T,FReg1_fs_3_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_3_ie_isSubnormal = $signed(FReg1_fs_3_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_3_ie_denormShiftDist = 5'h1 - FReg1_fs_3_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_3_ie_denormFract_T_1 = FReg1_fs_3_ie_rawIn__sig[24:1] >> FReg1_fs_3_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_3_ie_denormFract = _FReg1_fs_3_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_3_ie_expOut_T_2 = FReg1_fs_3_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_3_ie_expOut_T_3 = FReg1_fs_3_ie_isSubnormal ? 8'h0 : _FReg1_fs_3_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_3_ie_expOut_T_4 = FReg1_fs_3_ie_rawIn__isNaN | FReg1_fs_3_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_3_ie_expOut_T_6 = _FReg1_fs_3_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_3_ie_expOut = _FReg1_fs_3_ie_expOut_T_3 | _FReg1_fs_3_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_3_ie_fractOut_T_1 = FReg1_fs_3_ie_rawIn__isInf ? 23'h0 : FReg1_fs_3_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_3_ie_fractOut = FReg1_fs_3_ie_isSubnormal ? FReg1_fs_3_ie_denormFract :
    _FReg1_fs_3_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_3_ie = {FReg1_fs_3_ie_rawIn__sign,FReg1_fs_3_ie_expOut,FReg1_fs_3_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_3_T_3 = FReg1_fs_3_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_4_unbx_floats_0 = {io_diffFReg_20[31],io_diffFReg_20[52],io_diffFReg_20[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_4_unbx_isbox = &io_diffFReg_20[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_4_unbx_T = FReg1_fs_4_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_4_unbx = FReg1_fs_4_unbx_floats_0 | _FReg1_fs_4_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_4_ie_rawIn_exp = FReg1_fs_4_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_4_ie_rawIn_isZero = FReg1_fs_4_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_4_ie_rawIn_isSpecial = FReg1_fs_4_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_4_ie_rawIn__isNaN = FReg1_fs_4_ie_rawIn_isSpecial & FReg1_fs_4_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_4_ie_rawIn__isInf = FReg1_fs_4_ie_rawIn_isSpecial & ~FReg1_fs_4_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_4_ie_rawIn__sign = FReg1_fs_4_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_4_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_4_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_4_ie_rawIn_out_sig_T = ~FReg1_fs_4_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_4_ie_rawIn__sig = {1'h0,_FReg1_fs_4_ie_rawIn_out_sig_T,FReg1_fs_4_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_4_ie_isSubnormal = $signed(FReg1_fs_4_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_4_ie_denormShiftDist = 5'h1 - FReg1_fs_4_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_4_ie_denormFract_T_1 = FReg1_fs_4_ie_rawIn__sig[24:1] >> FReg1_fs_4_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_4_ie_denormFract = _FReg1_fs_4_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_4_ie_expOut_T_2 = FReg1_fs_4_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_4_ie_expOut_T_3 = FReg1_fs_4_ie_isSubnormal ? 8'h0 : _FReg1_fs_4_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_4_ie_expOut_T_4 = FReg1_fs_4_ie_rawIn__isNaN | FReg1_fs_4_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_4_ie_expOut_T_6 = _FReg1_fs_4_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_4_ie_expOut = _FReg1_fs_4_ie_expOut_T_3 | _FReg1_fs_4_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_4_ie_fractOut_T_1 = FReg1_fs_4_ie_rawIn__isInf ? 23'h0 : FReg1_fs_4_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_4_ie_fractOut = FReg1_fs_4_ie_isSubnormal ? FReg1_fs_4_ie_denormFract :
    _FReg1_fs_4_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_4_ie = {FReg1_fs_4_ie_rawIn__sign,FReg1_fs_4_ie_expOut,FReg1_fs_4_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_4_T_3 = FReg1_fs_4_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_5_unbx_floats_0 = {io_diffFReg_21[31],io_diffFReg_21[52],io_diffFReg_21[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_5_unbx_isbox = &io_diffFReg_21[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_5_unbx_T = FReg1_fs_5_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_5_unbx = FReg1_fs_5_unbx_floats_0 | _FReg1_fs_5_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_5_ie_rawIn_exp = FReg1_fs_5_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_5_ie_rawIn_isZero = FReg1_fs_5_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_5_ie_rawIn_isSpecial = FReg1_fs_5_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_5_ie_rawIn__isNaN = FReg1_fs_5_ie_rawIn_isSpecial & FReg1_fs_5_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_5_ie_rawIn__isInf = FReg1_fs_5_ie_rawIn_isSpecial & ~FReg1_fs_5_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_5_ie_rawIn__sign = FReg1_fs_5_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_5_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_5_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_5_ie_rawIn_out_sig_T = ~FReg1_fs_5_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_5_ie_rawIn__sig = {1'h0,_FReg1_fs_5_ie_rawIn_out_sig_T,FReg1_fs_5_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_5_ie_isSubnormal = $signed(FReg1_fs_5_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_5_ie_denormShiftDist = 5'h1 - FReg1_fs_5_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_5_ie_denormFract_T_1 = FReg1_fs_5_ie_rawIn__sig[24:1] >> FReg1_fs_5_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_5_ie_denormFract = _FReg1_fs_5_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_5_ie_expOut_T_2 = FReg1_fs_5_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_5_ie_expOut_T_3 = FReg1_fs_5_ie_isSubnormal ? 8'h0 : _FReg1_fs_5_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_5_ie_expOut_T_4 = FReg1_fs_5_ie_rawIn__isNaN | FReg1_fs_5_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_5_ie_expOut_T_6 = _FReg1_fs_5_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_5_ie_expOut = _FReg1_fs_5_ie_expOut_T_3 | _FReg1_fs_5_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_5_ie_fractOut_T_1 = FReg1_fs_5_ie_rawIn__isInf ? 23'h0 : FReg1_fs_5_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_5_ie_fractOut = FReg1_fs_5_ie_isSubnormal ? FReg1_fs_5_ie_denormFract :
    _FReg1_fs_5_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_5_ie = {FReg1_fs_5_ie_rawIn__sign,FReg1_fs_5_ie_expOut,FReg1_fs_5_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_5_T_3 = FReg1_fs_5_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_6_unbx_floats_0 = {io_diffFReg_22[31],io_diffFReg_22[52],io_diffFReg_22[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_6_unbx_isbox = &io_diffFReg_22[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_6_unbx_T = FReg1_fs_6_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_6_unbx = FReg1_fs_6_unbx_floats_0 | _FReg1_fs_6_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_6_ie_rawIn_exp = FReg1_fs_6_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_6_ie_rawIn_isZero = FReg1_fs_6_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_6_ie_rawIn_isSpecial = FReg1_fs_6_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_6_ie_rawIn__isNaN = FReg1_fs_6_ie_rawIn_isSpecial & FReg1_fs_6_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_6_ie_rawIn__isInf = FReg1_fs_6_ie_rawIn_isSpecial & ~FReg1_fs_6_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_6_ie_rawIn__sign = FReg1_fs_6_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_6_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_6_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_6_ie_rawIn_out_sig_T = ~FReg1_fs_6_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_6_ie_rawIn__sig = {1'h0,_FReg1_fs_6_ie_rawIn_out_sig_T,FReg1_fs_6_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_6_ie_isSubnormal = $signed(FReg1_fs_6_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_6_ie_denormShiftDist = 5'h1 - FReg1_fs_6_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_6_ie_denormFract_T_1 = FReg1_fs_6_ie_rawIn__sig[24:1] >> FReg1_fs_6_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_6_ie_denormFract = _FReg1_fs_6_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_6_ie_expOut_T_2 = FReg1_fs_6_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_6_ie_expOut_T_3 = FReg1_fs_6_ie_isSubnormal ? 8'h0 : _FReg1_fs_6_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_6_ie_expOut_T_4 = FReg1_fs_6_ie_rawIn__isNaN | FReg1_fs_6_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_6_ie_expOut_T_6 = _FReg1_fs_6_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_6_ie_expOut = _FReg1_fs_6_ie_expOut_T_3 | _FReg1_fs_6_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_6_ie_fractOut_T_1 = FReg1_fs_6_ie_rawIn__isInf ? 23'h0 : FReg1_fs_6_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_6_ie_fractOut = FReg1_fs_6_ie_isSubnormal ? FReg1_fs_6_ie_denormFract :
    _FReg1_fs_6_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_6_ie = {FReg1_fs_6_ie_rawIn__sign,FReg1_fs_6_ie_expOut,FReg1_fs_6_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_6_T_3 = FReg1_fs_6_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_7_unbx_floats_0 = {io_diffFReg_23[31],io_diffFReg_23[52],io_diffFReg_23[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_7_unbx_isbox = &io_diffFReg_23[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_7_unbx_T = FReg1_fs_7_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_7_unbx = FReg1_fs_7_unbx_floats_0 | _FReg1_fs_7_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_7_ie_rawIn_exp = FReg1_fs_7_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_7_ie_rawIn_isZero = FReg1_fs_7_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_7_ie_rawIn_isSpecial = FReg1_fs_7_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_7_ie_rawIn__isNaN = FReg1_fs_7_ie_rawIn_isSpecial & FReg1_fs_7_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_7_ie_rawIn__isInf = FReg1_fs_7_ie_rawIn_isSpecial & ~FReg1_fs_7_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_7_ie_rawIn__sign = FReg1_fs_7_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_7_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_7_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_7_ie_rawIn_out_sig_T = ~FReg1_fs_7_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_7_ie_rawIn__sig = {1'h0,_FReg1_fs_7_ie_rawIn_out_sig_T,FReg1_fs_7_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_7_ie_isSubnormal = $signed(FReg1_fs_7_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_7_ie_denormShiftDist = 5'h1 - FReg1_fs_7_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_7_ie_denormFract_T_1 = FReg1_fs_7_ie_rawIn__sig[24:1] >> FReg1_fs_7_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_7_ie_denormFract = _FReg1_fs_7_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_7_ie_expOut_T_2 = FReg1_fs_7_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_7_ie_expOut_T_3 = FReg1_fs_7_ie_isSubnormal ? 8'h0 : _FReg1_fs_7_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_7_ie_expOut_T_4 = FReg1_fs_7_ie_rawIn__isNaN | FReg1_fs_7_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_7_ie_expOut_T_6 = _FReg1_fs_7_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_7_ie_expOut = _FReg1_fs_7_ie_expOut_T_3 | _FReg1_fs_7_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_7_ie_fractOut_T_1 = FReg1_fs_7_ie_rawIn__isInf ? 23'h0 : FReg1_fs_7_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_7_ie_fractOut = FReg1_fs_7_ie_isSubnormal ? FReg1_fs_7_ie_denormFract :
    _FReg1_fs_7_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_7_ie = {FReg1_fs_7_ie_rawIn__sign,FReg1_fs_7_ie_expOut,FReg1_fs_7_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_7_T_3 = FReg1_fs_7_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_8_unbx_floats_0 = {io_diffFReg_24[31],io_diffFReg_24[52],io_diffFReg_24[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_8_unbx_isbox = &io_diffFReg_24[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_8_unbx_T = FReg1_fs_8_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_8_unbx = FReg1_fs_8_unbx_floats_0 | _FReg1_fs_8_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_8_ie_rawIn_exp = FReg1_fs_8_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_8_ie_rawIn_isZero = FReg1_fs_8_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_8_ie_rawIn_isSpecial = FReg1_fs_8_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_8_ie_rawIn__isNaN = FReg1_fs_8_ie_rawIn_isSpecial & FReg1_fs_8_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_8_ie_rawIn__isInf = FReg1_fs_8_ie_rawIn_isSpecial & ~FReg1_fs_8_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_8_ie_rawIn__sign = FReg1_fs_8_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_8_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_8_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_8_ie_rawIn_out_sig_T = ~FReg1_fs_8_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_8_ie_rawIn__sig = {1'h0,_FReg1_fs_8_ie_rawIn_out_sig_T,FReg1_fs_8_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_8_ie_isSubnormal = $signed(FReg1_fs_8_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_8_ie_denormShiftDist = 5'h1 - FReg1_fs_8_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_8_ie_denormFract_T_1 = FReg1_fs_8_ie_rawIn__sig[24:1] >> FReg1_fs_8_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_8_ie_denormFract = _FReg1_fs_8_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_8_ie_expOut_T_2 = FReg1_fs_8_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_8_ie_expOut_T_3 = FReg1_fs_8_ie_isSubnormal ? 8'h0 : _FReg1_fs_8_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_8_ie_expOut_T_4 = FReg1_fs_8_ie_rawIn__isNaN | FReg1_fs_8_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_8_ie_expOut_T_6 = _FReg1_fs_8_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_8_ie_expOut = _FReg1_fs_8_ie_expOut_T_3 | _FReg1_fs_8_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_8_ie_fractOut_T_1 = FReg1_fs_8_ie_rawIn__isInf ? 23'h0 : FReg1_fs_8_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_8_ie_fractOut = FReg1_fs_8_ie_isSubnormal ? FReg1_fs_8_ie_denormFract :
    _FReg1_fs_8_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_8_ie = {FReg1_fs_8_ie_rawIn__sign,FReg1_fs_8_ie_expOut,FReg1_fs_8_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_8_T_3 = FReg1_fs_8_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_9_unbx_floats_0 = {io_diffFReg_25[31],io_diffFReg_25[52],io_diffFReg_25[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_9_unbx_isbox = &io_diffFReg_25[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_9_unbx_T = FReg1_fs_9_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_9_unbx = FReg1_fs_9_unbx_floats_0 | _FReg1_fs_9_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_9_ie_rawIn_exp = FReg1_fs_9_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_9_ie_rawIn_isZero = FReg1_fs_9_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_9_ie_rawIn_isSpecial = FReg1_fs_9_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_9_ie_rawIn__isNaN = FReg1_fs_9_ie_rawIn_isSpecial & FReg1_fs_9_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_9_ie_rawIn__isInf = FReg1_fs_9_ie_rawIn_isSpecial & ~FReg1_fs_9_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_9_ie_rawIn__sign = FReg1_fs_9_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_9_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_9_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_9_ie_rawIn_out_sig_T = ~FReg1_fs_9_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_9_ie_rawIn__sig = {1'h0,_FReg1_fs_9_ie_rawIn_out_sig_T,FReg1_fs_9_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_9_ie_isSubnormal = $signed(FReg1_fs_9_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_9_ie_denormShiftDist = 5'h1 - FReg1_fs_9_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_9_ie_denormFract_T_1 = FReg1_fs_9_ie_rawIn__sig[24:1] >> FReg1_fs_9_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_9_ie_denormFract = _FReg1_fs_9_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_9_ie_expOut_T_2 = FReg1_fs_9_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_9_ie_expOut_T_3 = FReg1_fs_9_ie_isSubnormal ? 8'h0 : _FReg1_fs_9_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_9_ie_expOut_T_4 = FReg1_fs_9_ie_rawIn__isNaN | FReg1_fs_9_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_9_ie_expOut_T_6 = _FReg1_fs_9_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_9_ie_expOut = _FReg1_fs_9_ie_expOut_T_3 | _FReg1_fs_9_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_9_ie_fractOut_T_1 = FReg1_fs_9_ie_rawIn__isInf ? 23'h0 : FReg1_fs_9_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_9_ie_fractOut = FReg1_fs_9_ie_isSubnormal ? FReg1_fs_9_ie_denormFract :
    _FReg1_fs_9_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_9_ie = {FReg1_fs_9_ie_rawIn__sign,FReg1_fs_9_ie_expOut,FReg1_fs_9_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_9_T_3 = FReg1_fs_9_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_10_unbx_floats_0 = {io_diffFReg_26[31],io_diffFReg_26[52],io_diffFReg_26[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_10_unbx_isbox = &io_diffFReg_26[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_10_unbx_T = FReg1_fs_10_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_10_unbx = FReg1_fs_10_unbx_floats_0 | _FReg1_fs_10_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_10_ie_rawIn_exp = FReg1_fs_10_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_10_ie_rawIn_isZero = FReg1_fs_10_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_10_ie_rawIn_isSpecial = FReg1_fs_10_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_10_ie_rawIn__isNaN = FReg1_fs_10_ie_rawIn_isSpecial & FReg1_fs_10_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_10_ie_rawIn__isInf = FReg1_fs_10_ie_rawIn_isSpecial & ~FReg1_fs_10_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_10_ie_rawIn__sign = FReg1_fs_10_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_10_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_10_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_10_ie_rawIn_out_sig_T = ~FReg1_fs_10_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_10_ie_rawIn__sig = {1'h0,_FReg1_fs_10_ie_rawIn_out_sig_T,FReg1_fs_10_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_10_ie_isSubnormal = $signed(FReg1_fs_10_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_10_ie_denormShiftDist = 5'h1 - FReg1_fs_10_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_10_ie_denormFract_T_1 = FReg1_fs_10_ie_rawIn__sig[24:1] >> FReg1_fs_10_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_10_ie_denormFract = _FReg1_fs_10_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_10_ie_expOut_T_2 = FReg1_fs_10_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_10_ie_expOut_T_3 = FReg1_fs_10_ie_isSubnormal ? 8'h0 : _FReg1_fs_10_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_10_ie_expOut_T_4 = FReg1_fs_10_ie_rawIn__isNaN | FReg1_fs_10_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_10_ie_expOut_T_6 = _FReg1_fs_10_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_10_ie_expOut = _FReg1_fs_10_ie_expOut_T_3 | _FReg1_fs_10_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_10_ie_fractOut_T_1 = FReg1_fs_10_ie_rawIn__isInf ? 23'h0 : FReg1_fs_10_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_10_ie_fractOut = FReg1_fs_10_ie_isSubnormal ? FReg1_fs_10_ie_denormFract :
    _FReg1_fs_10_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_10_ie = {FReg1_fs_10_ie_rawIn__sign,FReg1_fs_10_ie_expOut,FReg1_fs_10_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_10_T_3 = FReg1_fs_10_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_fs_11_unbx_floats_0 = {io_diffFReg_27[31],io_diffFReg_27[52],io_diffFReg_27[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_11_unbx_isbox = &io_diffFReg_27[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_fs_11_unbx_T = FReg1_fs_11_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_fs_11_unbx = FReg1_fs_11_unbx_floats_0 | _FReg1_fs_11_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_fs_11_ie_rawIn_exp = FReg1_fs_11_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_fs_11_ie_rawIn_isZero = FReg1_fs_11_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_fs_11_ie_rawIn_isSpecial = FReg1_fs_11_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_fs_11_ie_rawIn__isNaN = FReg1_fs_11_ie_rawIn_isSpecial & FReg1_fs_11_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_fs_11_ie_rawIn__isInf = FReg1_fs_11_ie_rawIn_isSpecial & ~FReg1_fs_11_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_fs_11_ie_rawIn__sign = FReg1_fs_11_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_fs_11_ie_rawIn__sExp = {1'b0,$signed(FReg1_fs_11_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_fs_11_ie_rawIn_out_sig_T = ~FReg1_fs_11_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_fs_11_ie_rawIn__sig = {1'h0,_FReg1_fs_11_ie_rawIn_out_sig_T,FReg1_fs_11_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_fs_11_ie_isSubnormal = $signed(FReg1_fs_11_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_fs_11_ie_denormShiftDist = 5'h1 - FReg1_fs_11_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_fs_11_ie_denormFract_T_1 = FReg1_fs_11_ie_rawIn__sig[24:1] >> FReg1_fs_11_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_fs_11_ie_denormFract = _FReg1_fs_11_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_fs_11_ie_expOut_T_2 = FReg1_fs_11_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_fs_11_ie_expOut_T_3 = FReg1_fs_11_ie_isSubnormal ? 8'h0 : _FReg1_fs_11_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_fs_11_ie_expOut_T_4 = FReg1_fs_11_ie_rawIn__isNaN | FReg1_fs_11_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_fs_11_ie_expOut_T_6 = _FReg1_fs_11_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_fs_11_ie_expOut = _FReg1_fs_11_ie_expOut_T_3 | _FReg1_fs_11_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_fs_11_ie_fractOut_T_1 = FReg1_fs_11_ie_rawIn__isInf ? 23'h0 : FReg1_fs_11_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_fs_11_ie_fractOut = FReg1_fs_11_ie_isSubnormal ? FReg1_fs_11_ie_denormFract :
    _FReg1_fs_11_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_fs_11_ie = {FReg1_fs_11_ie_rawIn__sign,FReg1_fs_11_ie_expOut,FReg1_fs_11_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_fs_11_T_3 = FReg1_fs_11_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_8_unbx_floats_0 = {io_diffFReg_28[31],io_diffFReg_28[52],io_diffFReg_28[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_8_unbx_isbox = &io_diffFReg_28[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_8_unbx_T = FReg1_ft_8_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_8_unbx = FReg1_ft_8_unbx_floats_0 | _FReg1_ft_8_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_8_ie_rawIn_exp = FReg1_ft_8_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_8_ie_rawIn_isZero = FReg1_ft_8_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_8_ie_rawIn_isSpecial = FReg1_ft_8_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_8_ie_rawIn__isNaN = FReg1_ft_8_ie_rawIn_isSpecial & FReg1_ft_8_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_8_ie_rawIn__isInf = FReg1_ft_8_ie_rawIn_isSpecial & ~FReg1_ft_8_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_8_ie_rawIn__sign = FReg1_ft_8_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_8_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_8_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_8_ie_rawIn_out_sig_T = ~FReg1_ft_8_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_8_ie_rawIn__sig = {1'h0,_FReg1_ft_8_ie_rawIn_out_sig_T,FReg1_ft_8_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_8_ie_isSubnormal = $signed(FReg1_ft_8_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_8_ie_denormShiftDist = 5'h1 - FReg1_ft_8_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_8_ie_denormFract_T_1 = FReg1_ft_8_ie_rawIn__sig[24:1] >> FReg1_ft_8_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_8_ie_denormFract = _FReg1_ft_8_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_8_ie_expOut_T_2 = FReg1_ft_8_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_8_ie_expOut_T_3 = FReg1_ft_8_ie_isSubnormal ? 8'h0 : _FReg1_ft_8_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_8_ie_expOut_T_4 = FReg1_ft_8_ie_rawIn__isNaN | FReg1_ft_8_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_8_ie_expOut_T_6 = _FReg1_ft_8_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_8_ie_expOut = _FReg1_ft_8_ie_expOut_T_3 | _FReg1_ft_8_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_8_ie_fractOut_T_1 = FReg1_ft_8_ie_rawIn__isInf ? 23'h0 : FReg1_ft_8_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_8_ie_fractOut = FReg1_ft_8_ie_isSubnormal ? FReg1_ft_8_ie_denormFract :
    _FReg1_ft_8_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_8_ie = {FReg1_ft_8_ie_rawIn__sign,FReg1_ft_8_ie_expOut,FReg1_ft_8_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_8_T_3 = FReg1_ft_8_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_9_unbx_floats_0 = {io_diffFReg_29[31],io_diffFReg_29[52],io_diffFReg_29[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_9_unbx_isbox = &io_diffFReg_29[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_9_unbx_T = FReg1_ft_9_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_9_unbx = FReg1_ft_9_unbx_floats_0 | _FReg1_ft_9_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_9_ie_rawIn_exp = FReg1_ft_9_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_9_ie_rawIn_isZero = FReg1_ft_9_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_9_ie_rawIn_isSpecial = FReg1_ft_9_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_9_ie_rawIn__isNaN = FReg1_ft_9_ie_rawIn_isSpecial & FReg1_ft_9_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_9_ie_rawIn__isInf = FReg1_ft_9_ie_rawIn_isSpecial & ~FReg1_ft_9_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_9_ie_rawIn__sign = FReg1_ft_9_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_9_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_9_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_9_ie_rawIn_out_sig_T = ~FReg1_ft_9_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_9_ie_rawIn__sig = {1'h0,_FReg1_ft_9_ie_rawIn_out_sig_T,FReg1_ft_9_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_9_ie_isSubnormal = $signed(FReg1_ft_9_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_9_ie_denormShiftDist = 5'h1 - FReg1_ft_9_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_9_ie_denormFract_T_1 = FReg1_ft_9_ie_rawIn__sig[24:1] >> FReg1_ft_9_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_9_ie_denormFract = _FReg1_ft_9_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_9_ie_expOut_T_2 = FReg1_ft_9_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_9_ie_expOut_T_3 = FReg1_ft_9_ie_isSubnormal ? 8'h0 : _FReg1_ft_9_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_9_ie_expOut_T_4 = FReg1_ft_9_ie_rawIn__isNaN | FReg1_ft_9_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_9_ie_expOut_T_6 = _FReg1_ft_9_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_9_ie_expOut = _FReg1_ft_9_ie_expOut_T_3 | _FReg1_ft_9_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_9_ie_fractOut_T_1 = FReg1_ft_9_ie_rawIn__isInf ? 23'h0 : FReg1_ft_9_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_9_ie_fractOut = FReg1_ft_9_ie_isSubnormal ? FReg1_ft_9_ie_denormFract :
    _FReg1_ft_9_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_9_ie = {FReg1_ft_9_ie_rawIn__sign,FReg1_ft_9_ie_expOut,FReg1_ft_9_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_9_T_3 = FReg1_ft_9_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_10_unbx_floats_0 = {io_diffFReg_30[31],io_diffFReg_30[52],io_diffFReg_30[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_10_unbx_isbox = &io_diffFReg_30[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_10_unbx_T = FReg1_ft_10_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_10_unbx = FReg1_ft_10_unbx_floats_0 | _FReg1_ft_10_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_10_ie_rawIn_exp = FReg1_ft_10_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_10_ie_rawIn_isZero = FReg1_ft_10_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_10_ie_rawIn_isSpecial = FReg1_ft_10_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_10_ie_rawIn__isNaN = FReg1_ft_10_ie_rawIn_isSpecial & FReg1_ft_10_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_10_ie_rawIn__isInf = FReg1_ft_10_ie_rawIn_isSpecial & ~FReg1_ft_10_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_10_ie_rawIn__sign = FReg1_ft_10_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_10_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_10_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_10_ie_rawIn_out_sig_T = ~FReg1_ft_10_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_10_ie_rawIn__sig = {1'h0,_FReg1_ft_10_ie_rawIn_out_sig_T,FReg1_ft_10_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_10_ie_isSubnormal = $signed(FReg1_ft_10_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_10_ie_denormShiftDist = 5'h1 - FReg1_ft_10_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_10_ie_denormFract_T_1 = FReg1_ft_10_ie_rawIn__sig[24:1] >> FReg1_ft_10_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_10_ie_denormFract = _FReg1_ft_10_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_10_ie_expOut_T_2 = FReg1_ft_10_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_10_ie_expOut_T_3 = FReg1_ft_10_ie_isSubnormal ? 8'h0 : _FReg1_ft_10_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_10_ie_expOut_T_4 = FReg1_ft_10_ie_rawIn__isNaN | FReg1_ft_10_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_10_ie_expOut_T_6 = _FReg1_ft_10_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_10_ie_expOut = _FReg1_ft_10_ie_expOut_T_3 | _FReg1_ft_10_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_10_ie_fractOut_T_1 = FReg1_ft_10_ie_rawIn__isInf ? 23'h0 : FReg1_ft_10_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_10_ie_fractOut = FReg1_ft_10_ie_isSubnormal ? FReg1_ft_10_ie_denormFract :
    _FReg1_ft_10_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_10_ie = {FReg1_ft_10_ie_rawIn__sign,FReg1_ft_10_ie_expOut,FReg1_ft_10_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_10_T_3 = FReg1_ft_10_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [32:0] FReg1_ft_11_unbx_floats_0 = {io_diffFReg_31[31],io_diffFReg_31[52],io_diffFReg_31[30:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_11_unbx_isbox = &io_diffFReg_31[64:60]; // @[Fpu.scala 118:84]
  wire [32:0] _FReg1_ft_11_unbx_T = FReg1_ft_11_unbx_isbox ? 33'h0 : 33'he0400000; // @[Fpu.scala 163:31]
  wire [32:0] FReg1_ft_11_unbx = FReg1_ft_11_unbx_floats_0 | _FReg1_ft_11_unbx_T; // @[Fpu.scala 163:26]
  wire [8:0] FReg1_ft_11_ie_rawIn_exp = FReg1_ft_11_unbx[31:23]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg1_ft_11_ie_rawIn_isZero = FReg1_ft_11_ie_rawIn_exp[8:6] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg1_ft_11_ie_rawIn_isSpecial = FReg1_ft_11_ie_rawIn_exp[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg1_ft_11_ie_rawIn__isNaN = FReg1_ft_11_ie_rawIn_isSpecial & FReg1_ft_11_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg1_ft_11_ie_rawIn__isInf = FReg1_ft_11_ie_rawIn_isSpecial & ~FReg1_ft_11_ie_rawIn_exp[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg1_ft_11_ie_rawIn__sign = FReg1_ft_11_unbx[32]; // @[rawFloatFromRecFN.scala 58:25]
  wire [9:0] FReg1_ft_11_ie_rawIn__sExp = {1'b0,$signed(FReg1_ft_11_ie_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg1_ft_11_ie_rawIn_out_sig_T = ~FReg1_ft_11_ie_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg1_ft_11_ie_rawIn__sig = {1'h0,_FReg1_ft_11_ie_rawIn_out_sig_T,FReg1_ft_11_unbx[22:0]}; // @[Cat.scala 33:92]
  wire  FReg1_ft_11_ie_isSubnormal = $signed(FReg1_ft_11_ie_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg1_ft_11_ie_denormShiftDist = 5'h1 - FReg1_ft_11_ie_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg1_ft_11_ie_denormFract_T_1 = FReg1_ft_11_ie_rawIn__sig[24:1] >> FReg1_ft_11_ie_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg1_ft_11_ie_denormFract = _FReg1_ft_11_ie_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg1_ft_11_ie_expOut_T_2 = FReg1_ft_11_ie_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg1_ft_11_ie_expOut_T_3 = FReg1_ft_11_ie_isSubnormal ? 8'h0 : _FReg1_ft_11_ie_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg1_ft_11_ie_expOut_T_4 = FReg1_ft_11_ie_rawIn__isNaN | FReg1_ft_11_ie_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg1_ft_11_ie_expOut_T_6 = _FReg1_ft_11_ie_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg1_ft_11_ie_expOut = _FReg1_ft_11_ie_expOut_T_3 | _FReg1_ft_11_ie_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg1_ft_11_ie_fractOut_T_1 = FReg1_ft_11_ie_rawIn__isInf ? 23'h0 : FReg1_ft_11_ie_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg1_ft_11_ie_fractOut = FReg1_ft_11_ie_isSubnormal ? FReg1_ft_11_ie_denormFract :
    _FReg1_ft_11_ie_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg1_ft_11_ie = {FReg1_ft_11_ie_rawIn__sign,FReg1_ft_11_ie_expOut,FReg1_ft_11_ie_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] _FReg1_ft_11_T_3 = FReg1_ft_11_ie[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire  FReg2_ft_0_unbx_sign = FReg1_ft_0_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_0_unbx_fractIn = FReg1_ft_0_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_0_unbx_expIn = FReg1_ft_0_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_0_unbx_expOut_expCode = FReg2_ft_0_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_0_unbx_expOut_T = FReg2_ft_0_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_0_unrecoded_rawIn_exp = io_diffFReg_0[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_0_unrecoded_rawIn_isZero = FReg2_ft_0_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_0_unrecoded_rawIn_isSpecial = FReg2_ft_0_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_0_unrecoded_rawIn__isNaN = FReg2_ft_0_unrecoded_rawIn_isSpecial & FReg2_ft_0_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_0_unrecoded_rawIn__isInf = FReg2_ft_0_unrecoded_rawIn_isSpecial & ~FReg2_ft_0_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_0_unrecoded_rawIn__sign = io_diffFReg_0[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_0_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_0_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_0_unrecoded_rawIn_out_sig_T = ~FReg2_ft_0_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_0_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_0_unrecoded_rawIn_out_sig_T,io_diffFReg_0[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_0_unrecoded_isSubnormal = $signed(FReg2_ft_0_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_0_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_0_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_0_unrecoded_denormFract_T_1 = FReg2_ft_0_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_0_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_0_unrecoded_denormFract = _FReg2_ft_0_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_0_unrecoded_expOut_T_2 = FReg2_ft_0_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_0_unrecoded_expOut_T_3 = FReg2_ft_0_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_0_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_0_unrecoded_expOut_T_4 = FReg2_ft_0_unrecoded_rawIn__isNaN | FReg2_ft_0_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_0_unrecoded_expOut_T_6 = _FReg2_ft_0_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_0_unrecoded_expOut = _FReg2_ft_0_unrecoded_expOut_T_3 | _FReg2_ft_0_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_0_unrecoded_fractOut_T_1 = FReg2_ft_0_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_0_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_0_unrecoded_fractOut = FReg2_ft_0_unrecoded_isSubnormal ? FReg2_ft_0_unrecoded_denormFract :
    _FReg2_ft_0_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_0_unrecoded = {FReg2_ft_0_unrecoded_rawIn__sign,FReg2_ft_0_unrecoded_expOut,
    FReg2_ft_0_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_0_prevUnrecoded_rawIn_isSpecial = FReg2_ft_0_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_0_prevUnrecoded_rawIn__isNaN = FReg2_ft_0_prevUnrecoded_rawIn_isSpecial & FReg2_ft_0_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_0_prevUnrecoded_rawIn__isInf = FReg2_ft_0_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_0_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_0_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_0_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_0_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_0_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_0_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_0_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_0_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_0_prevUnrecoded_isSubnormal = $signed(FReg2_ft_0_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_0_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_0_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_0_prevUnrecoded_denormFract_T_1 = FReg2_ft_0_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_0_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_0_prevUnrecoded_denormFract = _FReg2_ft_0_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_0_prevUnrecoded_expOut_T_2 = FReg2_ft_0_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_0_prevUnrecoded_expOut_T_3 = FReg2_ft_0_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_0_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_0_prevUnrecoded_expOut_T_4 = FReg2_ft_0_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_0_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_0_prevUnrecoded_expOut_T_6 = _FReg2_ft_0_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_0_prevUnrecoded_expOut = _FReg2_ft_0_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_0_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_0_prevUnrecoded_fractOut_T_1 = FReg2_ft_0_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_0_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_0_prevUnrecoded_fractOut = FReg2_ft_0_prevUnrecoded_isSubnormal ?
    FReg2_ft_0_prevUnrecoded_denormFract : _FReg2_ft_0_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_0_prevUnrecoded = {FReg2_ft_0_unbx_sign,FReg2_ft_0_prevUnrecoded_expOut,
    FReg2_ft_0_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_0_T_2 = &io_diffFReg_0[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_0_T_4 = _FReg2_ft_0_T_2 ? FReg2_ft_0_prevUnrecoded : FReg2_ft_0_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_1_unbx_sign = FReg1_ft_1_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_1_unbx_fractIn = FReg1_ft_1_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_1_unbx_expIn = FReg1_ft_1_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_1_unbx_expOut_expCode = FReg2_ft_1_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_1_unbx_expOut_T = FReg2_ft_1_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_1_unrecoded_rawIn_exp = io_diffFReg_1[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_1_unrecoded_rawIn_isZero = FReg2_ft_1_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_1_unrecoded_rawIn_isSpecial = FReg2_ft_1_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_1_unrecoded_rawIn__isNaN = FReg2_ft_1_unrecoded_rawIn_isSpecial & FReg2_ft_1_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_1_unrecoded_rawIn__isInf = FReg2_ft_1_unrecoded_rawIn_isSpecial & ~FReg2_ft_1_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_1_unrecoded_rawIn__sign = io_diffFReg_1[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_1_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_1_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_1_unrecoded_rawIn_out_sig_T = ~FReg2_ft_1_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_1_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_1_unrecoded_rawIn_out_sig_T,io_diffFReg_1[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_1_unrecoded_isSubnormal = $signed(FReg2_ft_1_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_1_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_1_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_1_unrecoded_denormFract_T_1 = FReg2_ft_1_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_1_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_1_unrecoded_denormFract = _FReg2_ft_1_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_1_unrecoded_expOut_T_2 = FReg2_ft_1_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_1_unrecoded_expOut_T_3 = FReg2_ft_1_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_1_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_1_unrecoded_expOut_T_4 = FReg2_ft_1_unrecoded_rawIn__isNaN | FReg2_ft_1_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_1_unrecoded_expOut_T_6 = _FReg2_ft_1_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_1_unrecoded_expOut = _FReg2_ft_1_unrecoded_expOut_T_3 | _FReg2_ft_1_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_1_unrecoded_fractOut_T_1 = FReg2_ft_1_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_1_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_1_unrecoded_fractOut = FReg2_ft_1_unrecoded_isSubnormal ? FReg2_ft_1_unrecoded_denormFract :
    _FReg2_ft_1_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_1_unrecoded = {FReg2_ft_1_unrecoded_rawIn__sign,FReg2_ft_1_unrecoded_expOut,
    FReg2_ft_1_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_1_prevUnrecoded_rawIn_isSpecial = FReg2_ft_1_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_1_prevUnrecoded_rawIn__isNaN = FReg2_ft_1_prevUnrecoded_rawIn_isSpecial & FReg2_ft_1_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_1_prevUnrecoded_rawIn__isInf = FReg2_ft_1_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_1_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_1_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_1_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_1_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_1_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_1_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_1_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_1_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_1_prevUnrecoded_isSubnormal = $signed(FReg2_ft_1_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_1_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_1_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_1_prevUnrecoded_denormFract_T_1 = FReg2_ft_1_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_1_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_1_prevUnrecoded_denormFract = _FReg2_ft_1_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_1_prevUnrecoded_expOut_T_2 = FReg2_ft_1_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_1_prevUnrecoded_expOut_T_3 = FReg2_ft_1_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_1_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_1_prevUnrecoded_expOut_T_4 = FReg2_ft_1_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_1_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_1_prevUnrecoded_expOut_T_6 = _FReg2_ft_1_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_1_prevUnrecoded_expOut = _FReg2_ft_1_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_1_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_1_prevUnrecoded_fractOut_T_1 = FReg2_ft_1_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_1_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_1_prevUnrecoded_fractOut = FReg2_ft_1_prevUnrecoded_isSubnormal ?
    FReg2_ft_1_prevUnrecoded_denormFract : _FReg2_ft_1_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_1_prevUnrecoded = {FReg2_ft_1_unbx_sign,FReg2_ft_1_prevUnrecoded_expOut,
    FReg2_ft_1_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_1_T_2 = &io_diffFReg_1[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_1_T_4 = _FReg2_ft_1_T_2 ? FReg2_ft_1_prevUnrecoded : FReg2_ft_1_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_2_unbx_sign = FReg1_ft_2_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_2_unbx_fractIn = FReg1_ft_2_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_2_unbx_expIn = FReg1_ft_2_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_2_unbx_expOut_expCode = FReg2_ft_2_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_2_unbx_expOut_T = FReg2_ft_2_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_2_unrecoded_rawIn_exp = io_diffFReg_2[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_2_unrecoded_rawIn_isZero = FReg2_ft_2_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_2_unrecoded_rawIn_isSpecial = FReg2_ft_2_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_2_unrecoded_rawIn__isNaN = FReg2_ft_2_unrecoded_rawIn_isSpecial & FReg2_ft_2_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_2_unrecoded_rawIn__isInf = FReg2_ft_2_unrecoded_rawIn_isSpecial & ~FReg2_ft_2_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_2_unrecoded_rawIn__sign = io_diffFReg_2[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_2_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_2_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_2_unrecoded_rawIn_out_sig_T = ~FReg2_ft_2_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_2_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_2_unrecoded_rawIn_out_sig_T,io_diffFReg_2[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_2_unrecoded_isSubnormal = $signed(FReg2_ft_2_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_2_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_2_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_2_unrecoded_denormFract_T_1 = FReg2_ft_2_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_2_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_2_unrecoded_denormFract = _FReg2_ft_2_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_2_unrecoded_expOut_T_2 = FReg2_ft_2_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_2_unrecoded_expOut_T_3 = FReg2_ft_2_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_2_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_2_unrecoded_expOut_T_4 = FReg2_ft_2_unrecoded_rawIn__isNaN | FReg2_ft_2_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_2_unrecoded_expOut_T_6 = _FReg2_ft_2_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_2_unrecoded_expOut = _FReg2_ft_2_unrecoded_expOut_T_3 | _FReg2_ft_2_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_2_unrecoded_fractOut_T_1 = FReg2_ft_2_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_2_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_2_unrecoded_fractOut = FReg2_ft_2_unrecoded_isSubnormal ? FReg2_ft_2_unrecoded_denormFract :
    _FReg2_ft_2_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_2_unrecoded = {FReg2_ft_2_unrecoded_rawIn__sign,FReg2_ft_2_unrecoded_expOut,
    FReg2_ft_2_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_2_prevUnrecoded_rawIn_isSpecial = FReg2_ft_2_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_2_prevUnrecoded_rawIn__isNaN = FReg2_ft_2_prevUnrecoded_rawIn_isSpecial & FReg2_ft_2_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_2_prevUnrecoded_rawIn__isInf = FReg2_ft_2_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_2_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_2_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_2_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_2_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_2_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_2_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_2_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_2_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_2_prevUnrecoded_isSubnormal = $signed(FReg2_ft_2_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_2_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_2_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_2_prevUnrecoded_denormFract_T_1 = FReg2_ft_2_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_2_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_2_prevUnrecoded_denormFract = _FReg2_ft_2_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_2_prevUnrecoded_expOut_T_2 = FReg2_ft_2_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_2_prevUnrecoded_expOut_T_3 = FReg2_ft_2_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_2_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_2_prevUnrecoded_expOut_T_4 = FReg2_ft_2_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_2_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_2_prevUnrecoded_expOut_T_6 = _FReg2_ft_2_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_2_prevUnrecoded_expOut = _FReg2_ft_2_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_2_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_2_prevUnrecoded_fractOut_T_1 = FReg2_ft_2_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_2_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_2_prevUnrecoded_fractOut = FReg2_ft_2_prevUnrecoded_isSubnormal ?
    FReg2_ft_2_prevUnrecoded_denormFract : _FReg2_ft_2_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_2_prevUnrecoded = {FReg2_ft_2_unbx_sign,FReg2_ft_2_prevUnrecoded_expOut,
    FReg2_ft_2_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_2_T_2 = &io_diffFReg_2[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_2_T_4 = _FReg2_ft_2_T_2 ? FReg2_ft_2_prevUnrecoded : FReg2_ft_2_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_3_unbx_sign = FReg1_ft_3_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_3_unbx_fractIn = FReg1_ft_3_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_3_unbx_expIn = FReg1_ft_3_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_3_unbx_expOut_expCode = FReg2_ft_3_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_3_unbx_expOut_T = FReg2_ft_3_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_3_unrecoded_rawIn_exp = io_diffFReg_3[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_3_unrecoded_rawIn_isZero = FReg2_ft_3_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_3_unrecoded_rawIn_isSpecial = FReg2_ft_3_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_3_unrecoded_rawIn__isNaN = FReg2_ft_3_unrecoded_rawIn_isSpecial & FReg2_ft_3_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_3_unrecoded_rawIn__isInf = FReg2_ft_3_unrecoded_rawIn_isSpecial & ~FReg2_ft_3_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_3_unrecoded_rawIn__sign = io_diffFReg_3[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_3_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_3_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_3_unrecoded_rawIn_out_sig_T = ~FReg2_ft_3_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_3_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_3_unrecoded_rawIn_out_sig_T,io_diffFReg_3[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_3_unrecoded_isSubnormal = $signed(FReg2_ft_3_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_3_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_3_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_3_unrecoded_denormFract_T_1 = FReg2_ft_3_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_3_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_3_unrecoded_denormFract = _FReg2_ft_3_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_3_unrecoded_expOut_T_2 = FReg2_ft_3_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_3_unrecoded_expOut_T_3 = FReg2_ft_3_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_3_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_3_unrecoded_expOut_T_4 = FReg2_ft_3_unrecoded_rawIn__isNaN | FReg2_ft_3_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_3_unrecoded_expOut_T_6 = _FReg2_ft_3_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_3_unrecoded_expOut = _FReg2_ft_3_unrecoded_expOut_T_3 | _FReg2_ft_3_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_3_unrecoded_fractOut_T_1 = FReg2_ft_3_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_3_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_3_unrecoded_fractOut = FReg2_ft_3_unrecoded_isSubnormal ? FReg2_ft_3_unrecoded_denormFract :
    _FReg2_ft_3_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_3_unrecoded = {FReg2_ft_3_unrecoded_rawIn__sign,FReg2_ft_3_unrecoded_expOut,
    FReg2_ft_3_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_3_prevUnrecoded_rawIn_isSpecial = FReg2_ft_3_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_3_prevUnrecoded_rawIn__isNaN = FReg2_ft_3_prevUnrecoded_rawIn_isSpecial & FReg2_ft_3_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_3_prevUnrecoded_rawIn__isInf = FReg2_ft_3_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_3_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_3_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_3_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_3_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_3_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_3_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_3_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_3_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_3_prevUnrecoded_isSubnormal = $signed(FReg2_ft_3_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_3_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_3_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_3_prevUnrecoded_denormFract_T_1 = FReg2_ft_3_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_3_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_3_prevUnrecoded_denormFract = _FReg2_ft_3_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_3_prevUnrecoded_expOut_T_2 = FReg2_ft_3_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_3_prevUnrecoded_expOut_T_3 = FReg2_ft_3_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_3_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_3_prevUnrecoded_expOut_T_4 = FReg2_ft_3_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_3_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_3_prevUnrecoded_expOut_T_6 = _FReg2_ft_3_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_3_prevUnrecoded_expOut = _FReg2_ft_3_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_3_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_3_prevUnrecoded_fractOut_T_1 = FReg2_ft_3_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_3_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_3_prevUnrecoded_fractOut = FReg2_ft_3_prevUnrecoded_isSubnormal ?
    FReg2_ft_3_prevUnrecoded_denormFract : _FReg2_ft_3_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_3_prevUnrecoded = {FReg2_ft_3_unbx_sign,FReg2_ft_3_prevUnrecoded_expOut,
    FReg2_ft_3_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_3_T_2 = &io_diffFReg_3[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_3_T_4 = _FReg2_ft_3_T_2 ? FReg2_ft_3_prevUnrecoded : FReg2_ft_3_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_4_unbx_sign = FReg1_ft_4_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_4_unbx_fractIn = FReg1_ft_4_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_4_unbx_expIn = FReg1_ft_4_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_4_unbx_expOut_expCode = FReg2_ft_4_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_4_unbx_expOut_T = FReg2_ft_4_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_4_unrecoded_rawIn_exp = io_diffFReg_4[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_4_unrecoded_rawIn_isZero = FReg2_ft_4_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_4_unrecoded_rawIn_isSpecial = FReg2_ft_4_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_4_unrecoded_rawIn__isNaN = FReg2_ft_4_unrecoded_rawIn_isSpecial & FReg2_ft_4_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_4_unrecoded_rawIn__isInf = FReg2_ft_4_unrecoded_rawIn_isSpecial & ~FReg2_ft_4_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_4_unrecoded_rawIn__sign = io_diffFReg_4[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_4_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_4_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_4_unrecoded_rawIn_out_sig_T = ~FReg2_ft_4_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_4_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_4_unrecoded_rawIn_out_sig_T,io_diffFReg_4[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_4_unrecoded_isSubnormal = $signed(FReg2_ft_4_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_4_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_4_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_4_unrecoded_denormFract_T_1 = FReg2_ft_4_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_4_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_4_unrecoded_denormFract = _FReg2_ft_4_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_4_unrecoded_expOut_T_2 = FReg2_ft_4_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_4_unrecoded_expOut_T_3 = FReg2_ft_4_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_4_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_4_unrecoded_expOut_T_4 = FReg2_ft_4_unrecoded_rawIn__isNaN | FReg2_ft_4_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_4_unrecoded_expOut_T_6 = _FReg2_ft_4_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_4_unrecoded_expOut = _FReg2_ft_4_unrecoded_expOut_T_3 | _FReg2_ft_4_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_4_unrecoded_fractOut_T_1 = FReg2_ft_4_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_4_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_4_unrecoded_fractOut = FReg2_ft_4_unrecoded_isSubnormal ? FReg2_ft_4_unrecoded_denormFract :
    _FReg2_ft_4_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_4_unrecoded = {FReg2_ft_4_unrecoded_rawIn__sign,FReg2_ft_4_unrecoded_expOut,
    FReg2_ft_4_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_4_prevUnrecoded_rawIn_isSpecial = FReg2_ft_4_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_4_prevUnrecoded_rawIn__isNaN = FReg2_ft_4_prevUnrecoded_rawIn_isSpecial & FReg2_ft_4_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_4_prevUnrecoded_rawIn__isInf = FReg2_ft_4_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_4_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_4_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_4_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_4_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_4_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_4_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_4_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_4_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_4_prevUnrecoded_isSubnormal = $signed(FReg2_ft_4_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_4_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_4_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_4_prevUnrecoded_denormFract_T_1 = FReg2_ft_4_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_4_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_4_prevUnrecoded_denormFract = _FReg2_ft_4_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_4_prevUnrecoded_expOut_T_2 = FReg2_ft_4_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_4_prevUnrecoded_expOut_T_3 = FReg2_ft_4_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_4_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_4_prevUnrecoded_expOut_T_4 = FReg2_ft_4_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_4_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_4_prevUnrecoded_expOut_T_6 = _FReg2_ft_4_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_4_prevUnrecoded_expOut = _FReg2_ft_4_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_4_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_4_prevUnrecoded_fractOut_T_1 = FReg2_ft_4_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_4_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_4_prevUnrecoded_fractOut = FReg2_ft_4_prevUnrecoded_isSubnormal ?
    FReg2_ft_4_prevUnrecoded_denormFract : _FReg2_ft_4_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_4_prevUnrecoded = {FReg2_ft_4_unbx_sign,FReg2_ft_4_prevUnrecoded_expOut,
    FReg2_ft_4_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_4_T_2 = &io_diffFReg_4[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_4_T_4 = _FReg2_ft_4_T_2 ? FReg2_ft_4_prevUnrecoded : FReg2_ft_4_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_5_unbx_sign = FReg1_ft_5_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_5_unbx_fractIn = FReg1_ft_5_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_5_unbx_expIn = FReg1_ft_5_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_5_unbx_expOut_expCode = FReg2_ft_5_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_5_unbx_expOut_T = FReg2_ft_5_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_5_unrecoded_rawIn_exp = io_diffFReg_5[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_5_unrecoded_rawIn_isZero = FReg2_ft_5_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_5_unrecoded_rawIn_isSpecial = FReg2_ft_5_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_5_unrecoded_rawIn__isNaN = FReg2_ft_5_unrecoded_rawIn_isSpecial & FReg2_ft_5_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_5_unrecoded_rawIn__isInf = FReg2_ft_5_unrecoded_rawIn_isSpecial & ~FReg2_ft_5_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_5_unrecoded_rawIn__sign = io_diffFReg_5[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_5_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_5_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_5_unrecoded_rawIn_out_sig_T = ~FReg2_ft_5_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_5_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_5_unrecoded_rawIn_out_sig_T,io_diffFReg_5[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_5_unrecoded_isSubnormal = $signed(FReg2_ft_5_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_5_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_5_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_5_unrecoded_denormFract_T_1 = FReg2_ft_5_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_5_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_5_unrecoded_denormFract = _FReg2_ft_5_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_5_unrecoded_expOut_T_2 = FReg2_ft_5_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_5_unrecoded_expOut_T_3 = FReg2_ft_5_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_5_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_5_unrecoded_expOut_T_4 = FReg2_ft_5_unrecoded_rawIn__isNaN | FReg2_ft_5_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_5_unrecoded_expOut_T_6 = _FReg2_ft_5_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_5_unrecoded_expOut = _FReg2_ft_5_unrecoded_expOut_T_3 | _FReg2_ft_5_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_5_unrecoded_fractOut_T_1 = FReg2_ft_5_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_5_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_5_unrecoded_fractOut = FReg2_ft_5_unrecoded_isSubnormal ? FReg2_ft_5_unrecoded_denormFract :
    _FReg2_ft_5_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_5_unrecoded = {FReg2_ft_5_unrecoded_rawIn__sign,FReg2_ft_5_unrecoded_expOut,
    FReg2_ft_5_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_5_prevUnrecoded_rawIn_isSpecial = FReg2_ft_5_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_5_prevUnrecoded_rawIn__isNaN = FReg2_ft_5_prevUnrecoded_rawIn_isSpecial & FReg2_ft_5_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_5_prevUnrecoded_rawIn__isInf = FReg2_ft_5_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_5_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_5_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_5_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_5_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_5_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_5_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_5_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_5_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_5_prevUnrecoded_isSubnormal = $signed(FReg2_ft_5_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_5_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_5_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_5_prevUnrecoded_denormFract_T_1 = FReg2_ft_5_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_5_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_5_prevUnrecoded_denormFract = _FReg2_ft_5_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_5_prevUnrecoded_expOut_T_2 = FReg2_ft_5_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_5_prevUnrecoded_expOut_T_3 = FReg2_ft_5_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_5_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_5_prevUnrecoded_expOut_T_4 = FReg2_ft_5_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_5_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_5_prevUnrecoded_expOut_T_6 = _FReg2_ft_5_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_5_prevUnrecoded_expOut = _FReg2_ft_5_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_5_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_5_prevUnrecoded_fractOut_T_1 = FReg2_ft_5_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_5_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_5_prevUnrecoded_fractOut = FReg2_ft_5_prevUnrecoded_isSubnormal ?
    FReg2_ft_5_prevUnrecoded_denormFract : _FReg2_ft_5_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_5_prevUnrecoded = {FReg2_ft_5_unbx_sign,FReg2_ft_5_prevUnrecoded_expOut,
    FReg2_ft_5_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_5_T_2 = &io_diffFReg_5[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_5_T_4 = _FReg2_ft_5_T_2 ? FReg2_ft_5_prevUnrecoded : FReg2_ft_5_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_6_unbx_sign = FReg1_ft_6_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_6_unbx_fractIn = FReg1_ft_6_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_6_unbx_expIn = FReg1_ft_6_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_6_unbx_expOut_expCode = FReg2_ft_6_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_6_unbx_expOut_T = FReg2_ft_6_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_6_unrecoded_rawIn_exp = io_diffFReg_6[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_6_unrecoded_rawIn_isZero = FReg2_ft_6_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_6_unrecoded_rawIn_isSpecial = FReg2_ft_6_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_6_unrecoded_rawIn__isNaN = FReg2_ft_6_unrecoded_rawIn_isSpecial & FReg2_ft_6_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_6_unrecoded_rawIn__isInf = FReg2_ft_6_unrecoded_rawIn_isSpecial & ~FReg2_ft_6_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_6_unrecoded_rawIn__sign = io_diffFReg_6[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_6_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_6_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_6_unrecoded_rawIn_out_sig_T = ~FReg2_ft_6_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_6_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_6_unrecoded_rawIn_out_sig_T,io_diffFReg_6[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_6_unrecoded_isSubnormal = $signed(FReg2_ft_6_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_6_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_6_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_6_unrecoded_denormFract_T_1 = FReg2_ft_6_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_6_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_6_unrecoded_denormFract = _FReg2_ft_6_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_6_unrecoded_expOut_T_2 = FReg2_ft_6_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_6_unrecoded_expOut_T_3 = FReg2_ft_6_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_6_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_6_unrecoded_expOut_T_4 = FReg2_ft_6_unrecoded_rawIn__isNaN | FReg2_ft_6_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_6_unrecoded_expOut_T_6 = _FReg2_ft_6_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_6_unrecoded_expOut = _FReg2_ft_6_unrecoded_expOut_T_3 | _FReg2_ft_6_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_6_unrecoded_fractOut_T_1 = FReg2_ft_6_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_6_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_6_unrecoded_fractOut = FReg2_ft_6_unrecoded_isSubnormal ? FReg2_ft_6_unrecoded_denormFract :
    _FReg2_ft_6_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_6_unrecoded = {FReg2_ft_6_unrecoded_rawIn__sign,FReg2_ft_6_unrecoded_expOut,
    FReg2_ft_6_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_6_prevUnrecoded_rawIn_isSpecial = FReg2_ft_6_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_6_prevUnrecoded_rawIn__isNaN = FReg2_ft_6_prevUnrecoded_rawIn_isSpecial & FReg2_ft_6_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_6_prevUnrecoded_rawIn__isInf = FReg2_ft_6_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_6_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_6_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_6_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_6_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_6_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_6_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_6_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_6_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_6_prevUnrecoded_isSubnormal = $signed(FReg2_ft_6_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_6_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_6_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_6_prevUnrecoded_denormFract_T_1 = FReg2_ft_6_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_6_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_6_prevUnrecoded_denormFract = _FReg2_ft_6_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_6_prevUnrecoded_expOut_T_2 = FReg2_ft_6_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_6_prevUnrecoded_expOut_T_3 = FReg2_ft_6_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_6_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_6_prevUnrecoded_expOut_T_4 = FReg2_ft_6_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_6_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_6_prevUnrecoded_expOut_T_6 = _FReg2_ft_6_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_6_prevUnrecoded_expOut = _FReg2_ft_6_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_6_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_6_prevUnrecoded_fractOut_T_1 = FReg2_ft_6_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_6_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_6_prevUnrecoded_fractOut = FReg2_ft_6_prevUnrecoded_isSubnormal ?
    FReg2_ft_6_prevUnrecoded_denormFract : _FReg2_ft_6_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_6_prevUnrecoded = {FReg2_ft_6_unbx_sign,FReg2_ft_6_prevUnrecoded_expOut,
    FReg2_ft_6_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_6_T_2 = &io_diffFReg_6[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_6_T_4 = _FReg2_ft_6_T_2 ? FReg2_ft_6_prevUnrecoded : FReg2_ft_6_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_7_unbx_sign = FReg1_ft_7_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_7_unbx_fractIn = FReg1_ft_7_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_7_unbx_expIn = FReg1_ft_7_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_7_unbx_expOut_expCode = FReg2_ft_7_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_7_unbx_expOut_T = FReg2_ft_7_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_7_unrecoded_rawIn_exp = io_diffFReg_7[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_7_unrecoded_rawIn_isZero = FReg2_ft_7_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_7_unrecoded_rawIn_isSpecial = FReg2_ft_7_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_7_unrecoded_rawIn__isNaN = FReg2_ft_7_unrecoded_rawIn_isSpecial & FReg2_ft_7_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_7_unrecoded_rawIn__isInf = FReg2_ft_7_unrecoded_rawIn_isSpecial & ~FReg2_ft_7_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_7_unrecoded_rawIn__sign = io_diffFReg_7[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_7_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_7_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_7_unrecoded_rawIn_out_sig_T = ~FReg2_ft_7_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_7_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_7_unrecoded_rawIn_out_sig_T,io_diffFReg_7[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_7_unrecoded_isSubnormal = $signed(FReg2_ft_7_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_7_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_7_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_7_unrecoded_denormFract_T_1 = FReg2_ft_7_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_7_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_7_unrecoded_denormFract = _FReg2_ft_7_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_7_unrecoded_expOut_T_2 = FReg2_ft_7_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_7_unrecoded_expOut_T_3 = FReg2_ft_7_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_7_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_7_unrecoded_expOut_T_4 = FReg2_ft_7_unrecoded_rawIn__isNaN | FReg2_ft_7_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_7_unrecoded_expOut_T_6 = _FReg2_ft_7_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_7_unrecoded_expOut = _FReg2_ft_7_unrecoded_expOut_T_3 | _FReg2_ft_7_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_7_unrecoded_fractOut_T_1 = FReg2_ft_7_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_7_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_7_unrecoded_fractOut = FReg2_ft_7_unrecoded_isSubnormal ? FReg2_ft_7_unrecoded_denormFract :
    _FReg2_ft_7_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_7_unrecoded = {FReg2_ft_7_unrecoded_rawIn__sign,FReg2_ft_7_unrecoded_expOut,
    FReg2_ft_7_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_7_prevUnrecoded_rawIn_isSpecial = FReg2_ft_7_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_7_prevUnrecoded_rawIn__isNaN = FReg2_ft_7_prevUnrecoded_rawIn_isSpecial & FReg2_ft_7_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_7_prevUnrecoded_rawIn__isInf = FReg2_ft_7_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_7_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_7_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_7_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_7_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_7_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_7_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_7_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_7_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_7_prevUnrecoded_isSubnormal = $signed(FReg2_ft_7_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_7_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_7_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_7_prevUnrecoded_denormFract_T_1 = FReg2_ft_7_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_7_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_7_prevUnrecoded_denormFract = _FReg2_ft_7_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_7_prevUnrecoded_expOut_T_2 = FReg2_ft_7_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_7_prevUnrecoded_expOut_T_3 = FReg2_ft_7_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_7_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_7_prevUnrecoded_expOut_T_4 = FReg2_ft_7_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_7_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_7_prevUnrecoded_expOut_T_6 = _FReg2_ft_7_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_7_prevUnrecoded_expOut = _FReg2_ft_7_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_7_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_7_prevUnrecoded_fractOut_T_1 = FReg2_ft_7_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_7_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_7_prevUnrecoded_fractOut = FReg2_ft_7_prevUnrecoded_isSubnormal ?
    FReg2_ft_7_prevUnrecoded_denormFract : _FReg2_ft_7_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_7_prevUnrecoded = {FReg2_ft_7_unbx_sign,FReg2_ft_7_prevUnrecoded_expOut,
    FReg2_ft_7_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_7_T_2 = &io_diffFReg_7[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_7_T_4 = _FReg2_ft_7_T_2 ? FReg2_ft_7_prevUnrecoded : FReg2_ft_7_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_0_unbx_sign = FReg1_fs_0_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_0_unbx_fractIn = FReg1_fs_0_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_0_unbx_expIn = FReg1_fs_0_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_0_unbx_expOut_expCode = FReg2_fs_0_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_0_unbx_expOut_T = FReg2_fs_0_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_0_unrecoded_rawIn_exp = io_diffFReg_8[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_0_unrecoded_rawIn_isZero = FReg2_fs_0_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_0_unrecoded_rawIn_isSpecial = FReg2_fs_0_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_0_unrecoded_rawIn__isNaN = FReg2_fs_0_unrecoded_rawIn_isSpecial & FReg2_fs_0_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_0_unrecoded_rawIn__isInf = FReg2_fs_0_unrecoded_rawIn_isSpecial & ~FReg2_fs_0_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_0_unrecoded_rawIn__sign = io_diffFReg_8[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_0_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_0_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_0_unrecoded_rawIn_out_sig_T = ~FReg2_fs_0_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_0_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_0_unrecoded_rawIn_out_sig_T,io_diffFReg_8[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_0_unrecoded_isSubnormal = $signed(FReg2_fs_0_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_0_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_0_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_0_unrecoded_denormFract_T_1 = FReg2_fs_0_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_0_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_0_unrecoded_denormFract = _FReg2_fs_0_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_0_unrecoded_expOut_T_2 = FReg2_fs_0_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_0_unrecoded_expOut_T_3 = FReg2_fs_0_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_0_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_0_unrecoded_expOut_T_4 = FReg2_fs_0_unrecoded_rawIn__isNaN | FReg2_fs_0_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_0_unrecoded_expOut_T_6 = _FReg2_fs_0_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_0_unrecoded_expOut = _FReg2_fs_0_unrecoded_expOut_T_3 | _FReg2_fs_0_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_0_unrecoded_fractOut_T_1 = FReg2_fs_0_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_0_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_0_unrecoded_fractOut = FReg2_fs_0_unrecoded_isSubnormal ? FReg2_fs_0_unrecoded_denormFract :
    _FReg2_fs_0_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_0_unrecoded = {FReg2_fs_0_unrecoded_rawIn__sign,FReg2_fs_0_unrecoded_expOut,
    FReg2_fs_0_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_0_prevUnrecoded_rawIn_isSpecial = FReg2_fs_0_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_0_prevUnrecoded_rawIn__isNaN = FReg2_fs_0_prevUnrecoded_rawIn_isSpecial & FReg2_fs_0_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_0_prevUnrecoded_rawIn__isInf = FReg2_fs_0_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_0_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_0_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_0_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_0_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_0_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_0_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_0_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_0_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_0_prevUnrecoded_isSubnormal = $signed(FReg2_fs_0_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_0_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_0_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_0_prevUnrecoded_denormFract_T_1 = FReg2_fs_0_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_0_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_0_prevUnrecoded_denormFract = _FReg2_fs_0_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_0_prevUnrecoded_expOut_T_2 = FReg2_fs_0_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_0_prevUnrecoded_expOut_T_3 = FReg2_fs_0_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_0_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_0_prevUnrecoded_expOut_T_4 = FReg2_fs_0_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_0_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_0_prevUnrecoded_expOut_T_6 = _FReg2_fs_0_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_0_prevUnrecoded_expOut = _FReg2_fs_0_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_0_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_0_prevUnrecoded_fractOut_T_1 = FReg2_fs_0_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_0_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_0_prevUnrecoded_fractOut = FReg2_fs_0_prevUnrecoded_isSubnormal ?
    FReg2_fs_0_prevUnrecoded_denormFract : _FReg2_fs_0_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_0_prevUnrecoded = {FReg2_fs_0_unbx_sign,FReg2_fs_0_prevUnrecoded_expOut,
    FReg2_fs_0_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_0_T_2 = &io_diffFReg_8[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_0_T_4 = _FReg2_fs_0_T_2 ? FReg2_fs_0_prevUnrecoded : FReg2_fs_0_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_1_unbx_sign = FReg1_fs_1_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_1_unbx_fractIn = FReg1_fs_1_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_1_unbx_expIn = FReg1_fs_1_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_1_unbx_expOut_expCode = FReg2_fs_1_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_1_unbx_expOut_T = FReg2_fs_1_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_1_unrecoded_rawIn_exp = io_diffFReg_9[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_1_unrecoded_rawIn_isZero = FReg2_fs_1_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_1_unrecoded_rawIn_isSpecial = FReg2_fs_1_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_1_unrecoded_rawIn__isNaN = FReg2_fs_1_unrecoded_rawIn_isSpecial & FReg2_fs_1_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_1_unrecoded_rawIn__isInf = FReg2_fs_1_unrecoded_rawIn_isSpecial & ~FReg2_fs_1_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_1_unrecoded_rawIn__sign = io_diffFReg_9[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_1_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_1_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_1_unrecoded_rawIn_out_sig_T = ~FReg2_fs_1_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_1_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_1_unrecoded_rawIn_out_sig_T,io_diffFReg_9[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_1_unrecoded_isSubnormal = $signed(FReg2_fs_1_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_1_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_1_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_1_unrecoded_denormFract_T_1 = FReg2_fs_1_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_1_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_1_unrecoded_denormFract = _FReg2_fs_1_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_1_unrecoded_expOut_T_2 = FReg2_fs_1_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_1_unrecoded_expOut_T_3 = FReg2_fs_1_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_1_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_1_unrecoded_expOut_T_4 = FReg2_fs_1_unrecoded_rawIn__isNaN | FReg2_fs_1_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_1_unrecoded_expOut_T_6 = _FReg2_fs_1_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_1_unrecoded_expOut = _FReg2_fs_1_unrecoded_expOut_T_3 | _FReg2_fs_1_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_1_unrecoded_fractOut_T_1 = FReg2_fs_1_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_1_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_1_unrecoded_fractOut = FReg2_fs_1_unrecoded_isSubnormal ? FReg2_fs_1_unrecoded_denormFract :
    _FReg2_fs_1_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_1_unrecoded = {FReg2_fs_1_unrecoded_rawIn__sign,FReg2_fs_1_unrecoded_expOut,
    FReg2_fs_1_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_1_prevUnrecoded_rawIn_isSpecial = FReg2_fs_1_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_1_prevUnrecoded_rawIn__isNaN = FReg2_fs_1_prevUnrecoded_rawIn_isSpecial & FReg2_fs_1_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_1_prevUnrecoded_rawIn__isInf = FReg2_fs_1_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_1_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_1_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_1_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_1_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_1_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_1_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_1_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_1_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_1_prevUnrecoded_isSubnormal = $signed(FReg2_fs_1_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_1_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_1_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_1_prevUnrecoded_denormFract_T_1 = FReg2_fs_1_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_1_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_1_prevUnrecoded_denormFract = _FReg2_fs_1_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_1_prevUnrecoded_expOut_T_2 = FReg2_fs_1_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_1_prevUnrecoded_expOut_T_3 = FReg2_fs_1_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_1_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_1_prevUnrecoded_expOut_T_4 = FReg2_fs_1_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_1_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_1_prevUnrecoded_expOut_T_6 = _FReg2_fs_1_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_1_prevUnrecoded_expOut = _FReg2_fs_1_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_1_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_1_prevUnrecoded_fractOut_T_1 = FReg2_fs_1_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_1_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_1_prevUnrecoded_fractOut = FReg2_fs_1_prevUnrecoded_isSubnormal ?
    FReg2_fs_1_prevUnrecoded_denormFract : _FReg2_fs_1_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_1_prevUnrecoded = {FReg2_fs_1_unbx_sign,FReg2_fs_1_prevUnrecoded_expOut,
    FReg2_fs_1_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_1_T_2 = &io_diffFReg_9[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_1_T_4 = _FReg2_fs_1_T_2 ? FReg2_fs_1_prevUnrecoded : FReg2_fs_1_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fa_0_unbx_sign = FReg1_fa_0_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fa_0_unbx_fractIn = FReg1_fa_0_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fa_0_unbx_expIn = FReg1_fa_0_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fa_0_unbx_expOut_expCode = FReg2_fa_0_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fa_0_unbx_expOut_T = FReg2_fa_0_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fa_0_unrecoded_rawIn_exp = io_diffFReg_10[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fa_0_unrecoded_rawIn_isZero = FReg2_fa_0_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fa_0_unrecoded_rawIn_isSpecial = FReg2_fa_0_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_0_unrecoded_rawIn__isNaN = FReg2_fa_0_unrecoded_rawIn_isSpecial & FReg2_fa_0_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_0_unrecoded_rawIn__isInf = FReg2_fa_0_unrecoded_rawIn_isSpecial & ~FReg2_fa_0_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fa_0_unrecoded_rawIn__sign = io_diffFReg_10[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fa_0_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_0_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_0_unrecoded_rawIn_out_sig_T = ~FReg2_fa_0_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fa_0_unrecoded_rawIn__sig = {1'h0,_FReg2_fa_0_unrecoded_rawIn_out_sig_T,io_diffFReg_10[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fa_0_unrecoded_isSubnormal = $signed(FReg2_fa_0_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fa_0_unrecoded_denormShiftDist = 6'h1 - FReg2_fa_0_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fa_0_unrecoded_denormFract_T_1 = FReg2_fa_0_unrecoded_rawIn__sig[53:1] >>
    FReg2_fa_0_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fa_0_unrecoded_denormFract = _FReg2_fa_0_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fa_0_unrecoded_expOut_T_2 = FReg2_fa_0_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fa_0_unrecoded_expOut_T_3 = FReg2_fa_0_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fa_0_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_0_unrecoded_expOut_T_4 = FReg2_fa_0_unrecoded_rawIn__isNaN | FReg2_fa_0_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fa_0_unrecoded_expOut_T_6 = _FReg2_fa_0_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fa_0_unrecoded_expOut = _FReg2_fa_0_unrecoded_expOut_T_3 | _FReg2_fa_0_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fa_0_unrecoded_fractOut_T_1 = FReg2_fa_0_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fa_0_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fa_0_unrecoded_fractOut = FReg2_fa_0_unrecoded_isSubnormal ? FReg2_fa_0_unrecoded_denormFract :
    _FReg2_fa_0_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fa_0_unrecoded = {FReg2_fa_0_unrecoded_rawIn__sign,FReg2_fa_0_unrecoded_expOut,
    FReg2_fa_0_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fa_0_prevUnrecoded_rawIn_isSpecial = FReg2_fa_0_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_0_prevUnrecoded_rawIn__isNaN = FReg2_fa_0_prevUnrecoded_rawIn_isSpecial & FReg2_fa_0_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_0_prevUnrecoded_rawIn__isInf = FReg2_fa_0_prevUnrecoded_rawIn_isSpecial & ~FReg2_fa_0_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fa_0_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_0_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_0_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fa_0_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fa_0_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fa_0_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fa_0_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fa_0_prevUnrecoded_isSubnormal = $signed(FReg2_fa_0_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fa_0_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fa_0_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fa_0_prevUnrecoded_denormFract_T_1 = FReg2_fa_0_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fa_0_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fa_0_prevUnrecoded_denormFract = _FReg2_fa_0_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fa_0_prevUnrecoded_expOut_T_2 = FReg2_fa_0_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fa_0_prevUnrecoded_expOut_T_3 = FReg2_fa_0_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fa_0_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_0_prevUnrecoded_expOut_T_4 = FReg2_fa_0_prevUnrecoded_rawIn__isNaN |
    FReg2_fa_0_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fa_0_prevUnrecoded_expOut_T_6 = _FReg2_fa_0_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fa_0_prevUnrecoded_expOut = _FReg2_fa_0_prevUnrecoded_expOut_T_3 |
    _FReg2_fa_0_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fa_0_prevUnrecoded_fractOut_T_1 = FReg2_fa_0_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fa_0_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fa_0_prevUnrecoded_fractOut = FReg2_fa_0_prevUnrecoded_isSubnormal ?
    FReg2_fa_0_prevUnrecoded_denormFract : _FReg2_fa_0_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fa_0_prevUnrecoded = {FReg2_fa_0_unbx_sign,FReg2_fa_0_prevUnrecoded_expOut,
    FReg2_fa_0_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fa_0_T_2 = &io_diffFReg_10[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fa_0_T_4 = _FReg2_fa_0_T_2 ? FReg2_fa_0_prevUnrecoded : FReg2_fa_0_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fa_1_unbx_sign = FReg1_fa_1_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fa_1_unbx_fractIn = FReg1_fa_1_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fa_1_unbx_expIn = FReg1_fa_1_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fa_1_unbx_expOut_expCode = FReg2_fa_1_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fa_1_unbx_expOut_T = FReg2_fa_1_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fa_1_unrecoded_rawIn_exp = io_diffFReg_11[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fa_1_unrecoded_rawIn_isZero = FReg2_fa_1_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fa_1_unrecoded_rawIn_isSpecial = FReg2_fa_1_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_1_unrecoded_rawIn__isNaN = FReg2_fa_1_unrecoded_rawIn_isSpecial & FReg2_fa_1_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_1_unrecoded_rawIn__isInf = FReg2_fa_1_unrecoded_rawIn_isSpecial & ~FReg2_fa_1_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fa_1_unrecoded_rawIn__sign = io_diffFReg_11[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fa_1_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_1_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_1_unrecoded_rawIn_out_sig_T = ~FReg2_fa_1_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fa_1_unrecoded_rawIn__sig = {1'h0,_FReg2_fa_1_unrecoded_rawIn_out_sig_T,io_diffFReg_11[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fa_1_unrecoded_isSubnormal = $signed(FReg2_fa_1_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fa_1_unrecoded_denormShiftDist = 6'h1 - FReg2_fa_1_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fa_1_unrecoded_denormFract_T_1 = FReg2_fa_1_unrecoded_rawIn__sig[53:1] >>
    FReg2_fa_1_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fa_1_unrecoded_denormFract = _FReg2_fa_1_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fa_1_unrecoded_expOut_T_2 = FReg2_fa_1_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fa_1_unrecoded_expOut_T_3 = FReg2_fa_1_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fa_1_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_1_unrecoded_expOut_T_4 = FReg2_fa_1_unrecoded_rawIn__isNaN | FReg2_fa_1_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fa_1_unrecoded_expOut_T_6 = _FReg2_fa_1_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fa_1_unrecoded_expOut = _FReg2_fa_1_unrecoded_expOut_T_3 | _FReg2_fa_1_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fa_1_unrecoded_fractOut_T_1 = FReg2_fa_1_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fa_1_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fa_1_unrecoded_fractOut = FReg2_fa_1_unrecoded_isSubnormal ? FReg2_fa_1_unrecoded_denormFract :
    _FReg2_fa_1_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fa_1_unrecoded = {FReg2_fa_1_unrecoded_rawIn__sign,FReg2_fa_1_unrecoded_expOut,
    FReg2_fa_1_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fa_1_prevUnrecoded_rawIn_isSpecial = FReg2_fa_1_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_1_prevUnrecoded_rawIn__isNaN = FReg2_fa_1_prevUnrecoded_rawIn_isSpecial & FReg2_fa_1_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_1_prevUnrecoded_rawIn__isInf = FReg2_fa_1_prevUnrecoded_rawIn_isSpecial & ~FReg2_fa_1_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fa_1_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_1_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_1_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fa_1_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fa_1_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fa_1_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fa_1_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fa_1_prevUnrecoded_isSubnormal = $signed(FReg2_fa_1_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fa_1_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fa_1_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fa_1_prevUnrecoded_denormFract_T_1 = FReg2_fa_1_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fa_1_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fa_1_prevUnrecoded_denormFract = _FReg2_fa_1_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fa_1_prevUnrecoded_expOut_T_2 = FReg2_fa_1_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fa_1_prevUnrecoded_expOut_T_3 = FReg2_fa_1_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fa_1_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_1_prevUnrecoded_expOut_T_4 = FReg2_fa_1_prevUnrecoded_rawIn__isNaN |
    FReg2_fa_1_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fa_1_prevUnrecoded_expOut_T_6 = _FReg2_fa_1_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fa_1_prevUnrecoded_expOut = _FReg2_fa_1_prevUnrecoded_expOut_T_3 |
    _FReg2_fa_1_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fa_1_prevUnrecoded_fractOut_T_1 = FReg2_fa_1_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fa_1_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fa_1_prevUnrecoded_fractOut = FReg2_fa_1_prevUnrecoded_isSubnormal ?
    FReg2_fa_1_prevUnrecoded_denormFract : _FReg2_fa_1_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fa_1_prevUnrecoded = {FReg2_fa_1_unbx_sign,FReg2_fa_1_prevUnrecoded_expOut,
    FReg2_fa_1_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fa_1_T_2 = &io_diffFReg_11[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fa_1_T_4 = _FReg2_fa_1_T_2 ? FReg2_fa_1_prevUnrecoded : FReg2_fa_1_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fa_2_unbx_sign = FReg1_fa_2_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fa_2_unbx_fractIn = FReg1_fa_2_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fa_2_unbx_expIn = FReg1_fa_2_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fa_2_unbx_expOut_expCode = FReg2_fa_2_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fa_2_unbx_expOut_T = FReg2_fa_2_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fa_2_unrecoded_rawIn_exp = io_diffFReg_12[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fa_2_unrecoded_rawIn_isZero = FReg2_fa_2_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fa_2_unrecoded_rawIn_isSpecial = FReg2_fa_2_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_2_unrecoded_rawIn__isNaN = FReg2_fa_2_unrecoded_rawIn_isSpecial & FReg2_fa_2_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_2_unrecoded_rawIn__isInf = FReg2_fa_2_unrecoded_rawIn_isSpecial & ~FReg2_fa_2_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fa_2_unrecoded_rawIn__sign = io_diffFReg_12[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fa_2_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_2_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_2_unrecoded_rawIn_out_sig_T = ~FReg2_fa_2_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fa_2_unrecoded_rawIn__sig = {1'h0,_FReg2_fa_2_unrecoded_rawIn_out_sig_T,io_diffFReg_12[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fa_2_unrecoded_isSubnormal = $signed(FReg2_fa_2_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fa_2_unrecoded_denormShiftDist = 6'h1 - FReg2_fa_2_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fa_2_unrecoded_denormFract_T_1 = FReg2_fa_2_unrecoded_rawIn__sig[53:1] >>
    FReg2_fa_2_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fa_2_unrecoded_denormFract = _FReg2_fa_2_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fa_2_unrecoded_expOut_T_2 = FReg2_fa_2_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fa_2_unrecoded_expOut_T_3 = FReg2_fa_2_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fa_2_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_2_unrecoded_expOut_T_4 = FReg2_fa_2_unrecoded_rawIn__isNaN | FReg2_fa_2_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fa_2_unrecoded_expOut_T_6 = _FReg2_fa_2_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fa_2_unrecoded_expOut = _FReg2_fa_2_unrecoded_expOut_T_3 | _FReg2_fa_2_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fa_2_unrecoded_fractOut_T_1 = FReg2_fa_2_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fa_2_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fa_2_unrecoded_fractOut = FReg2_fa_2_unrecoded_isSubnormal ? FReg2_fa_2_unrecoded_denormFract :
    _FReg2_fa_2_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fa_2_unrecoded = {FReg2_fa_2_unrecoded_rawIn__sign,FReg2_fa_2_unrecoded_expOut,
    FReg2_fa_2_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fa_2_prevUnrecoded_rawIn_isSpecial = FReg2_fa_2_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_2_prevUnrecoded_rawIn__isNaN = FReg2_fa_2_prevUnrecoded_rawIn_isSpecial & FReg2_fa_2_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_2_prevUnrecoded_rawIn__isInf = FReg2_fa_2_prevUnrecoded_rawIn_isSpecial & ~FReg2_fa_2_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fa_2_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_2_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_2_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fa_2_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fa_2_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fa_2_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fa_2_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fa_2_prevUnrecoded_isSubnormal = $signed(FReg2_fa_2_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fa_2_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fa_2_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fa_2_prevUnrecoded_denormFract_T_1 = FReg2_fa_2_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fa_2_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fa_2_prevUnrecoded_denormFract = _FReg2_fa_2_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fa_2_prevUnrecoded_expOut_T_2 = FReg2_fa_2_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fa_2_prevUnrecoded_expOut_T_3 = FReg2_fa_2_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fa_2_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_2_prevUnrecoded_expOut_T_4 = FReg2_fa_2_prevUnrecoded_rawIn__isNaN |
    FReg2_fa_2_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fa_2_prevUnrecoded_expOut_T_6 = _FReg2_fa_2_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fa_2_prevUnrecoded_expOut = _FReg2_fa_2_prevUnrecoded_expOut_T_3 |
    _FReg2_fa_2_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fa_2_prevUnrecoded_fractOut_T_1 = FReg2_fa_2_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fa_2_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fa_2_prevUnrecoded_fractOut = FReg2_fa_2_prevUnrecoded_isSubnormal ?
    FReg2_fa_2_prevUnrecoded_denormFract : _FReg2_fa_2_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fa_2_prevUnrecoded = {FReg2_fa_2_unbx_sign,FReg2_fa_2_prevUnrecoded_expOut,
    FReg2_fa_2_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fa_2_T_2 = &io_diffFReg_12[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fa_2_T_4 = _FReg2_fa_2_T_2 ? FReg2_fa_2_prevUnrecoded : FReg2_fa_2_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fa_3_unbx_sign = FReg1_fa_3_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fa_3_unbx_fractIn = FReg1_fa_3_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fa_3_unbx_expIn = FReg1_fa_3_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fa_3_unbx_expOut_expCode = FReg2_fa_3_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fa_3_unbx_expOut_T = FReg2_fa_3_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fa_3_unrecoded_rawIn_exp = io_diffFReg_13[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fa_3_unrecoded_rawIn_isZero = FReg2_fa_3_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fa_3_unrecoded_rawIn_isSpecial = FReg2_fa_3_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_3_unrecoded_rawIn__isNaN = FReg2_fa_3_unrecoded_rawIn_isSpecial & FReg2_fa_3_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_3_unrecoded_rawIn__isInf = FReg2_fa_3_unrecoded_rawIn_isSpecial & ~FReg2_fa_3_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fa_3_unrecoded_rawIn__sign = io_diffFReg_13[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fa_3_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_3_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_3_unrecoded_rawIn_out_sig_T = ~FReg2_fa_3_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fa_3_unrecoded_rawIn__sig = {1'h0,_FReg2_fa_3_unrecoded_rawIn_out_sig_T,io_diffFReg_13[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fa_3_unrecoded_isSubnormal = $signed(FReg2_fa_3_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fa_3_unrecoded_denormShiftDist = 6'h1 - FReg2_fa_3_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fa_3_unrecoded_denormFract_T_1 = FReg2_fa_3_unrecoded_rawIn__sig[53:1] >>
    FReg2_fa_3_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fa_3_unrecoded_denormFract = _FReg2_fa_3_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fa_3_unrecoded_expOut_T_2 = FReg2_fa_3_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fa_3_unrecoded_expOut_T_3 = FReg2_fa_3_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fa_3_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_3_unrecoded_expOut_T_4 = FReg2_fa_3_unrecoded_rawIn__isNaN | FReg2_fa_3_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fa_3_unrecoded_expOut_T_6 = _FReg2_fa_3_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fa_3_unrecoded_expOut = _FReg2_fa_3_unrecoded_expOut_T_3 | _FReg2_fa_3_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fa_3_unrecoded_fractOut_T_1 = FReg2_fa_3_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fa_3_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fa_3_unrecoded_fractOut = FReg2_fa_3_unrecoded_isSubnormal ? FReg2_fa_3_unrecoded_denormFract :
    _FReg2_fa_3_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fa_3_unrecoded = {FReg2_fa_3_unrecoded_rawIn__sign,FReg2_fa_3_unrecoded_expOut,
    FReg2_fa_3_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fa_3_prevUnrecoded_rawIn_isSpecial = FReg2_fa_3_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_3_prevUnrecoded_rawIn__isNaN = FReg2_fa_3_prevUnrecoded_rawIn_isSpecial & FReg2_fa_3_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_3_prevUnrecoded_rawIn__isInf = FReg2_fa_3_prevUnrecoded_rawIn_isSpecial & ~FReg2_fa_3_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fa_3_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_3_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_3_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fa_3_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fa_3_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fa_3_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fa_3_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fa_3_prevUnrecoded_isSubnormal = $signed(FReg2_fa_3_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fa_3_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fa_3_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fa_3_prevUnrecoded_denormFract_T_1 = FReg2_fa_3_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fa_3_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fa_3_prevUnrecoded_denormFract = _FReg2_fa_3_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fa_3_prevUnrecoded_expOut_T_2 = FReg2_fa_3_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fa_3_prevUnrecoded_expOut_T_3 = FReg2_fa_3_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fa_3_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_3_prevUnrecoded_expOut_T_4 = FReg2_fa_3_prevUnrecoded_rawIn__isNaN |
    FReg2_fa_3_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fa_3_prevUnrecoded_expOut_T_6 = _FReg2_fa_3_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fa_3_prevUnrecoded_expOut = _FReg2_fa_3_prevUnrecoded_expOut_T_3 |
    _FReg2_fa_3_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fa_3_prevUnrecoded_fractOut_T_1 = FReg2_fa_3_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fa_3_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fa_3_prevUnrecoded_fractOut = FReg2_fa_3_prevUnrecoded_isSubnormal ?
    FReg2_fa_3_prevUnrecoded_denormFract : _FReg2_fa_3_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fa_3_prevUnrecoded = {FReg2_fa_3_unbx_sign,FReg2_fa_3_prevUnrecoded_expOut,
    FReg2_fa_3_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fa_3_T_2 = &io_diffFReg_13[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fa_3_T_4 = _FReg2_fa_3_T_2 ? FReg2_fa_3_prevUnrecoded : FReg2_fa_3_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fa_4_unbx_sign = FReg1_fa_4_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fa_4_unbx_fractIn = FReg1_fa_4_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fa_4_unbx_expIn = FReg1_fa_4_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fa_4_unbx_expOut_expCode = FReg2_fa_4_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fa_4_unbx_expOut_T = FReg2_fa_4_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fa_4_unrecoded_rawIn_exp = io_diffFReg_14[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fa_4_unrecoded_rawIn_isZero = FReg2_fa_4_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fa_4_unrecoded_rawIn_isSpecial = FReg2_fa_4_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_4_unrecoded_rawIn__isNaN = FReg2_fa_4_unrecoded_rawIn_isSpecial & FReg2_fa_4_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_4_unrecoded_rawIn__isInf = FReg2_fa_4_unrecoded_rawIn_isSpecial & ~FReg2_fa_4_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fa_4_unrecoded_rawIn__sign = io_diffFReg_14[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fa_4_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_4_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_4_unrecoded_rawIn_out_sig_T = ~FReg2_fa_4_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fa_4_unrecoded_rawIn__sig = {1'h0,_FReg2_fa_4_unrecoded_rawIn_out_sig_T,io_diffFReg_14[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fa_4_unrecoded_isSubnormal = $signed(FReg2_fa_4_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fa_4_unrecoded_denormShiftDist = 6'h1 - FReg2_fa_4_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fa_4_unrecoded_denormFract_T_1 = FReg2_fa_4_unrecoded_rawIn__sig[53:1] >>
    FReg2_fa_4_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fa_4_unrecoded_denormFract = _FReg2_fa_4_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fa_4_unrecoded_expOut_T_2 = FReg2_fa_4_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fa_4_unrecoded_expOut_T_3 = FReg2_fa_4_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fa_4_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_4_unrecoded_expOut_T_4 = FReg2_fa_4_unrecoded_rawIn__isNaN | FReg2_fa_4_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fa_4_unrecoded_expOut_T_6 = _FReg2_fa_4_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fa_4_unrecoded_expOut = _FReg2_fa_4_unrecoded_expOut_T_3 | _FReg2_fa_4_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fa_4_unrecoded_fractOut_T_1 = FReg2_fa_4_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fa_4_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fa_4_unrecoded_fractOut = FReg2_fa_4_unrecoded_isSubnormal ? FReg2_fa_4_unrecoded_denormFract :
    _FReg2_fa_4_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fa_4_unrecoded = {FReg2_fa_4_unrecoded_rawIn__sign,FReg2_fa_4_unrecoded_expOut,
    FReg2_fa_4_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fa_4_prevUnrecoded_rawIn_isSpecial = FReg2_fa_4_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_4_prevUnrecoded_rawIn__isNaN = FReg2_fa_4_prevUnrecoded_rawIn_isSpecial & FReg2_fa_4_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_4_prevUnrecoded_rawIn__isInf = FReg2_fa_4_prevUnrecoded_rawIn_isSpecial & ~FReg2_fa_4_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fa_4_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_4_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_4_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fa_4_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fa_4_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fa_4_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fa_4_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fa_4_prevUnrecoded_isSubnormal = $signed(FReg2_fa_4_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fa_4_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fa_4_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fa_4_prevUnrecoded_denormFract_T_1 = FReg2_fa_4_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fa_4_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fa_4_prevUnrecoded_denormFract = _FReg2_fa_4_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fa_4_prevUnrecoded_expOut_T_2 = FReg2_fa_4_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fa_4_prevUnrecoded_expOut_T_3 = FReg2_fa_4_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fa_4_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_4_prevUnrecoded_expOut_T_4 = FReg2_fa_4_prevUnrecoded_rawIn__isNaN |
    FReg2_fa_4_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fa_4_prevUnrecoded_expOut_T_6 = _FReg2_fa_4_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fa_4_prevUnrecoded_expOut = _FReg2_fa_4_prevUnrecoded_expOut_T_3 |
    _FReg2_fa_4_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fa_4_prevUnrecoded_fractOut_T_1 = FReg2_fa_4_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fa_4_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fa_4_prevUnrecoded_fractOut = FReg2_fa_4_prevUnrecoded_isSubnormal ?
    FReg2_fa_4_prevUnrecoded_denormFract : _FReg2_fa_4_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fa_4_prevUnrecoded = {FReg2_fa_4_unbx_sign,FReg2_fa_4_prevUnrecoded_expOut,
    FReg2_fa_4_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fa_4_T_2 = &io_diffFReg_14[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fa_4_T_4 = _FReg2_fa_4_T_2 ? FReg2_fa_4_prevUnrecoded : FReg2_fa_4_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fa_5_unbx_sign = FReg1_fa_5_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fa_5_unbx_fractIn = FReg1_fa_5_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fa_5_unbx_expIn = FReg1_fa_5_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fa_5_unbx_expOut_expCode = FReg2_fa_5_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fa_5_unbx_expOut_T = FReg2_fa_5_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fa_5_unrecoded_rawIn_exp = io_diffFReg_15[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fa_5_unrecoded_rawIn_isZero = FReg2_fa_5_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fa_5_unrecoded_rawIn_isSpecial = FReg2_fa_5_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_5_unrecoded_rawIn__isNaN = FReg2_fa_5_unrecoded_rawIn_isSpecial & FReg2_fa_5_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_5_unrecoded_rawIn__isInf = FReg2_fa_5_unrecoded_rawIn_isSpecial & ~FReg2_fa_5_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fa_5_unrecoded_rawIn__sign = io_diffFReg_15[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fa_5_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_5_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_5_unrecoded_rawIn_out_sig_T = ~FReg2_fa_5_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fa_5_unrecoded_rawIn__sig = {1'h0,_FReg2_fa_5_unrecoded_rawIn_out_sig_T,io_diffFReg_15[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fa_5_unrecoded_isSubnormal = $signed(FReg2_fa_5_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fa_5_unrecoded_denormShiftDist = 6'h1 - FReg2_fa_5_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fa_5_unrecoded_denormFract_T_1 = FReg2_fa_5_unrecoded_rawIn__sig[53:1] >>
    FReg2_fa_5_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fa_5_unrecoded_denormFract = _FReg2_fa_5_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fa_5_unrecoded_expOut_T_2 = FReg2_fa_5_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fa_5_unrecoded_expOut_T_3 = FReg2_fa_5_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fa_5_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_5_unrecoded_expOut_T_4 = FReg2_fa_5_unrecoded_rawIn__isNaN | FReg2_fa_5_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fa_5_unrecoded_expOut_T_6 = _FReg2_fa_5_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fa_5_unrecoded_expOut = _FReg2_fa_5_unrecoded_expOut_T_3 | _FReg2_fa_5_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fa_5_unrecoded_fractOut_T_1 = FReg2_fa_5_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fa_5_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fa_5_unrecoded_fractOut = FReg2_fa_5_unrecoded_isSubnormal ? FReg2_fa_5_unrecoded_denormFract :
    _FReg2_fa_5_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fa_5_unrecoded = {FReg2_fa_5_unrecoded_rawIn__sign,FReg2_fa_5_unrecoded_expOut,
    FReg2_fa_5_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fa_5_prevUnrecoded_rawIn_isSpecial = FReg2_fa_5_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_5_prevUnrecoded_rawIn__isNaN = FReg2_fa_5_prevUnrecoded_rawIn_isSpecial & FReg2_fa_5_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_5_prevUnrecoded_rawIn__isInf = FReg2_fa_5_prevUnrecoded_rawIn_isSpecial & ~FReg2_fa_5_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fa_5_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_5_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_5_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fa_5_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fa_5_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fa_5_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fa_5_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fa_5_prevUnrecoded_isSubnormal = $signed(FReg2_fa_5_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fa_5_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fa_5_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fa_5_prevUnrecoded_denormFract_T_1 = FReg2_fa_5_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fa_5_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fa_5_prevUnrecoded_denormFract = _FReg2_fa_5_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fa_5_prevUnrecoded_expOut_T_2 = FReg2_fa_5_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fa_5_prevUnrecoded_expOut_T_3 = FReg2_fa_5_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fa_5_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_5_prevUnrecoded_expOut_T_4 = FReg2_fa_5_prevUnrecoded_rawIn__isNaN |
    FReg2_fa_5_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fa_5_prevUnrecoded_expOut_T_6 = _FReg2_fa_5_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fa_5_prevUnrecoded_expOut = _FReg2_fa_5_prevUnrecoded_expOut_T_3 |
    _FReg2_fa_5_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fa_5_prevUnrecoded_fractOut_T_1 = FReg2_fa_5_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fa_5_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fa_5_prevUnrecoded_fractOut = FReg2_fa_5_prevUnrecoded_isSubnormal ?
    FReg2_fa_5_prevUnrecoded_denormFract : _FReg2_fa_5_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fa_5_prevUnrecoded = {FReg2_fa_5_unbx_sign,FReg2_fa_5_prevUnrecoded_expOut,
    FReg2_fa_5_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fa_5_T_2 = &io_diffFReg_15[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fa_5_T_4 = _FReg2_fa_5_T_2 ? FReg2_fa_5_prevUnrecoded : FReg2_fa_5_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fa_6_unbx_sign = FReg1_fa_6_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fa_6_unbx_fractIn = FReg1_fa_6_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fa_6_unbx_expIn = FReg1_fa_6_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fa_6_unbx_expOut_expCode = FReg2_fa_6_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fa_6_unbx_expOut_T = FReg2_fa_6_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fa_6_unrecoded_rawIn_exp = io_diffFReg_16[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fa_6_unrecoded_rawIn_isZero = FReg2_fa_6_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fa_6_unrecoded_rawIn_isSpecial = FReg2_fa_6_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_6_unrecoded_rawIn__isNaN = FReg2_fa_6_unrecoded_rawIn_isSpecial & FReg2_fa_6_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_6_unrecoded_rawIn__isInf = FReg2_fa_6_unrecoded_rawIn_isSpecial & ~FReg2_fa_6_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fa_6_unrecoded_rawIn__sign = io_diffFReg_16[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fa_6_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_6_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_6_unrecoded_rawIn_out_sig_T = ~FReg2_fa_6_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fa_6_unrecoded_rawIn__sig = {1'h0,_FReg2_fa_6_unrecoded_rawIn_out_sig_T,io_diffFReg_16[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fa_6_unrecoded_isSubnormal = $signed(FReg2_fa_6_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fa_6_unrecoded_denormShiftDist = 6'h1 - FReg2_fa_6_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fa_6_unrecoded_denormFract_T_1 = FReg2_fa_6_unrecoded_rawIn__sig[53:1] >>
    FReg2_fa_6_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fa_6_unrecoded_denormFract = _FReg2_fa_6_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fa_6_unrecoded_expOut_T_2 = FReg2_fa_6_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fa_6_unrecoded_expOut_T_3 = FReg2_fa_6_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fa_6_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_6_unrecoded_expOut_T_4 = FReg2_fa_6_unrecoded_rawIn__isNaN | FReg2_fa_6_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fa_6_unrecoded_expOut_T_6 = _FReg2_fa_6_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fa_6_unrecoded_expOut = _FReg2_fa_6_unrecoded_expOut_T_3 | _FReg2_fa_6_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fa_6_unrecoded_fractOut_T_1 = FReg2_fa_6_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fa_6_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fa_6_unrecoded_fractOut = FReg2_fa_6_unrecoded_isSubnormal ? FReg2_fa_6_unrecoded_denormFract :
    _FReg2_fa_6_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fa_6_unrecoded = {FReg2_fa_6_unrecoded_rawIn__sign,FReg2_fa_6_unrecoded_expOut,
    FReg2_fa_6_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fa_6_prevUnrecoded_rawIn_isSpecial = FReg2_fa_6_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_6_prevUnrecoded_rawIn__isNaN = FReg2_fa_6_prevUnrecoded_rawIn_isSpecial & FReg2_fa_6_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_6_prevUnrecoded_rawIn__isInf = FReg2_fa_6_prevUnrecoded_rawIn_isSpecial & ~FReg2_fa_6_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fa_6_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_6_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_6_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fa_6_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fa_6_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fa_6_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fa_6_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fa_6_prevUnrecoded_isSubnormal = $signed(FReg2_fa_6_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fa_6_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fa_6_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fa_6_prevUnrecoded_denormFract_T_1 = FReg2_fa_6_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fa_6_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fa_6_prevUnrecoded_denormFract = _FReg2_fa_6_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fa_6_prevUnrecoded_expOut_T_2 = FReg2_fa_6_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fa_6_prevUnrecoded_expOut_T_3 = FReg2_fa_6_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fa_6_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_6_prevUnrecoded_expOut_T_4 = FReg2_fa_6_prevUnrecoded_rawIn__isNaN |
    FReg2_fa_6_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fa_6_prevUnrecoded_expOut_T_6 = _FReg2_fa_6_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fa_6_prevUnrecoded_expOut = _FReg2_fa_6_prevUnrecoded_expOut_T_3 |
    _FReg2_fa_6_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fa_6_prevUnrecoded_fractOut_T_1 = FReg2_fa_6_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fa_6_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fa_6_prevUnrecoded_fractOut = FReg2_fa_6_prevUnrecoded_isSubnormal ?
    FReg2_fa_6_prevUnrecoded_denormFract : _FReg2_fa_6_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fa_6_prevUnrecoded = {FReg2_fa_6_unbx_sign,FReg2_fa_6_prevUnrecoded_expOut,
    FReg2_fa_6_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fa_6_T_2 = &io_diffFReg_16[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fa_6_T_4 = _FReg2_fa_6_T_2 ? FReg2_fa_6_prevUnrecoded : FReg2_fa_6_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fa_7_unbx_sign = FReg1_fa_7_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fa_7_unbx_fractIn = FReg1_fa_7_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fa_7_unbx_expIn = FReg1_fa_7_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fa_7_unbx_expOut_expCode = FReg2_fa_7_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fa_7_unbx_expOut_T = FReg2_fa_7_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fa_7_unrecoded_rawIn_exp = io_diffFReg_17[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fa_7_unrecoded_rawIn_isZero = FReg2_fa_7_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fa_7_unrecoded_rawIn_isSpecial = FReg2_fa_7_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_7_unrecoded_rawIn__isNaN = FReg2_fa_7_unrecoded_rawIn_isSpecial & FReg2_fa_7_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_7_unrecoded_rawIn__isInf = FReg2_fa_7_unrecoded_rawIn_isSpecial & ~FReg2_fa_7_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fa_7_unrecoded_rawIn__sign = io_diffFReg_17[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fa_7_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_7_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_7_unrecoded_rawIn_out_sig_T = ~FReg2_fa_7_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fa_7_unrecoded_rawIn__sig = {1'h0,_FReg2_fa_7_unrecoded_rawIn_out_sig_T,io_diffFReg_17[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fa_7_unrecoded_isSubnormal = $signed(FReg2_fa_7_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fa_7_unrecoded_denormShiftDist = 6'h1 - FReg2_fa_7_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fa_7_unrecoded_denormFract_T_1 = FReg2_fa_7_unrecoded_rawIn__sig[53:1] >>
    FReg2_fa_7_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fa_7_unrecoded_denormFract = _FReg2_fa_7_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fa_7_unrecoded_expOut_T_2 = FReg2_fa_7_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fa_7_unrecoded_expOut_T_3 = FReg2_fa_7_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fa_7_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_7_unrecoded_expOut_T_4 = FReg2_fa_7_unrecoded_rawIn__isNaN | FReg2_fa_7_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fa_7_unrecoded_expOut_T_6 = _FReg2_fa_7_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fa_7_unrecoded_expOut = _FReg2_fa_7_unrecoded_expOut_T_3 | _FReg2_fa_7_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fa_7_unrecoded_fractOut_T_1 = FReg2_fa_7_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fa_7_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fa_7_unrecoded_fractOut = FReg2_fa_7_unrecoded_isSubnormal ? FReg2_fa_7_unrecoded_denormFract :
    _FReg2_fa_7_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fa_7_unrecoded = {FReg2_fa_7_unrecoded_rawIn__sign,FReg2_fa_7_unrecoded_expOut,
    FReg2_fa_7_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fa_7_prevUnrecoded_rawIn_isSpecial = FReg2_fa_7_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fa_7_prevUnrecoded_rawIn__isNaN = FReg2_fa_7_prevUnrecoded_rawIn_isSpecial & FReg2_fa_7_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fa_7_prevUnrecoded_rawIn__isInf = FReg2_fa_7_prevUnrecoded_rawIn_isSpecial & ~FReg2_fa_7_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fa_7_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fa_7_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fa_7_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fa_7_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fa_7_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fa_7_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fa_7_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fa_7_prevUnrecoded_isSubnormal = $signed(FReg2_fa_7_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fa_7_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fa_7_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fa_7_prevUnrecoded_denormFract_T_1 = FReg2_fa_7_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fa_7_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fa_7_prevUnrecoded_denormFract = _FReg2_fa_7_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fa_7_prevUnrecoded_expOut_T_2 = FReg2_fa_7_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fa_7_prevUnrecoded_expOut_T_3 = FReg2_fa_7_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fa_7_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fa_7_prevUnrecoded_expOut_T_4 = FReg2_fa_7_prevUnrecoded_rawIn__isNaN |
    FReg2_fa_7_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fa_7_prevUnrecoded_expOut_T_6 = _FReg2_fa_7_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fa_7_prevUnrecoded_expOut = _FReg2_fa_7_prevUnrecoded_expOut_T_3 |
    _FReg2_fa_7_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fa_7_prevUnrecoded_fractOut_T_1 = FReg2_fa_7_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fa_7_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fa_7_prevUnrecoded_fractOut = FReg2_fa_7_prevUnrecoded_isSubnormal ?
    FReg2_fa_7_prevUnrecoded_denormFract : _FReg2_fa_7_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fa_7_prevUnrecoded = {FReg2_fa_7_unbx_sign,FReg2_fa_7_prevUnrecoded_expOut,
    FReg2_fa_7_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fa_7_T_2 = &io_diffFReg_17[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fa_7_T_4 = _FReg2_fa_7_T_2 ? FReg2_fa_7_prevUnrecoded : FReg2_fa_7_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_2_unbx_sign = FReg1_fs_2_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_2_unbx_fractIn = FReg1_fs_2_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_2_unbx_expIn = FReg1_fs_2_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_2_unbx_expOut_expCode = FReg2_fs_2_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_2_unbx_expOut_T = FReg2_fs_2_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_2_unrecoded_rawIn_exp = io_diffFReg_18[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_2_unrecoded_rawIn_isZero = FReg2_fs_2_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_2_unrecoded_rawIn_isSpecial = FReg2_fs_2_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_2_unrecoded_rawIn__isNaN = FReg2_fs_2_unrecoded_rawIn_isSpecial & FReg2_fs_2_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_2_unrecoded_rawIn__isInf = FReg2_fs_2_unrecoded_rawIn_isSpecial & ~FReg2_fs_2_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_2_unrecoded_rawIn__sign = io_diffFReg_18[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_2_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_2_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_2_unrecoded_rawIn_out_sig_T = ~FReg2_fs_2_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_2_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_2_unrecoded_rawIn_out_sig_T,io_diffFReg_18[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_2_unrecoded_isSubnormal = $signed(FReg2_fs_2_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_2_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_2_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_2_unrecoded_denormFract_T_1 = FReg2_fs_2_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_2_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_2_unrecoded_denormFract = _FReg2_fs_2_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_2_unrecoded_expOut_T_2 = FReg2_fs_2_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_2_unrecoded_expOut_T_3 = FReg2_fs_2_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_2_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_2_unrecoded_expOut_T_4 = FReg2_fs_2_unrecoded_rawIn__isNaN | FReg2_fs_2_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_2_unrecoded_expOut_T_6 = _FReg2_fs_2_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_2_unrecoded_expOut = _FReg2_fs_2_unrecoded_expOut_T_3 | _FReg2_fs_2_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_2_unrecoded_fractOut_T_1 = FReg2_fs_2_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_2_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_2_unrecoded_fractOut = FReg2_fs_2_unrecoded_isSubnormal ? FReg2_fs_2_unrecoded_denormFract :
    _FReg2_fs_2_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_2_unrecoded = {FReg2_fs_2_unrecoded_rawIn__sign,FReg2_fs_2_unrecoded_expOut,
    FReg2_fs_2_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_2_prevUnrecoded_rawIn_isSpecial = FReg2_fs_2_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_2_prevUnrecoded_rawIn__isNaN = FReg2_fs_2_prevUnrecoded_rawIn_isSpecial & FReg2_fs_2_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_2_prevUnrecoded_rawIn__isInf = FReg2_fs_2_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_2_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_2_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_2_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_2_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_2_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_2_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_2_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_2_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_2_prevUnrecoded_isSubnormal = $signed(FReg2_fs_2_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_2_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_2_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_2_prevUnrecoded_denormFract_T_1 = FReg2_fs_2_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_2_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_2_prevUnrecoded_denormFract = _FReg2_fs_2_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_2_prevUnrecoded_expOut_T_2 = FReg2_fs_2_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_2_prevUnrecoded_expOut_T_3 = FReg2_fs_2_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_2_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_2_prevUnrecoded_expOut_T_4 = FReg2_fs_2_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_2_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_2_prevUnrecoded_expOut_T_6 = _FReg2_fs_2_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_2_prevUnrecoded_expOut = _FReg2_fs_2_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_2_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_2_prevUnrecoded_fractOut_T_1 = FReg2_fs_2_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_2_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_2_prevUnrecoded_fractOut = FReg2_fs_2_prevUnrecoded_isSubnormal ?
    FReg2_fs_2_prevUnrecoded_denormFract : _FReg2_fs_2_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_2_prevUnrecoded = {FReg2_fs_2_unbx_sign,FReg2_fs_2_prevUnrecoded_expOut,
    FReg2_fs_2_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_2_T_2 = &io_diffFReg_18[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_2_T_4 = _FReg2_fs_2_T_2 ? FReg2_fs_2_prevUnrecoded : FReg2_fs_2_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_3_unbx_sign = FReg1_fs_3_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_3_unbx_fractIn = FReg1_fs_3_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_3_unbx_expIn = FReg1_fs_3_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_3_unbx_expOut_expCode = FReg2_fs_3_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_3_unbx_expOut_T = FReg2_fs_3_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_3_unrecoded_rawIn_exp = io_diffFReg_19[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_3_unrecoded_rawIn_isZero = FReg2_fs_3_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_3_unrecoded_rawIn_isSpecial = FReg2_fs_3_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_3_unrecoded_rawIn__isNaN = FReg2_fs_3_unrecoded_rawIn_isSpecial & FReg2_fs_3_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_3_unrecoded_rawIn__isInf = FReg2_fs_3_unrecoded_rawIn_isSpecial & ~FReg2_fs_3_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_3_unrecoded_rawIn__sign = io_diffFReg_19[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_3_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_3_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_3_unrecoded_rawIn_out_sig_T = ~FReg2_fs_3_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_3_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_3_unrecoded_rawIn_out_sig_T,io_diffFReg_19[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_3_unrecoded_isSubnormal = $signed(FReg2_fs_3_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_3_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_3_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_3_unrecoded_denormFract_T_1 = FReg2_fs_3_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_3_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_3_unrecoded_denormFract = _FReg2_fs_3_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_3_unrecoded_expOut_T_2 = FReg2_fs_3_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_3_unrecoded_expOut_T_3 = FReg2_fs_3_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_3_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_3_unrecoded_expOut_T_4 = FReg2_fs_3_unrecoded_rawIn__isNaN | FReg2_fs_3_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_3_unrecoded_expOut_T_6 = _FReg2_fs_3_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_3_unrecoded_expOut = _FReg2_fs_3_unrecoded_expOut_T_3 | _FReg2_fs_3_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_3_unrecoded_fractOut_T_1 = FReg2_fs_3_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_3_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_3_unrecoded_fractOut = FReg2_fs_3_unrecoded_isSubnormal ? FReg2_fs_3_unrecoded_denormFract :
    _FReg2_fs_3_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_3_unrecoded = {FReg2_fs_3_unrecoded_rawIn__sign,FReg2_fs_3_unrecoded_expOut,
    FReg2_fs_3_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_3_prevUnrecoded_rawIn_isSpecial = FReg2_fs_3_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_3_prevUnrecoded_rawIn__isNaN = FReg2_fs_3_prevUnrecoded_rawIn_isSpecial & FReg2_fs_3_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_3_prevUnrecoded_rawIn__isInf = FReg2_fs_3_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_3_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_3_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_3_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_3_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_3_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_3_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_3_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_3_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_3_prevUnrecoded_isSubnormal = $signed(FReg2_fs_3_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_3_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_3_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_3_prevUnrecoded_denormFract_T_1 = FReg2_fs_3_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_3_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_3_prevUnrecoded_denormFract = _FReg2_fs_3_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_3_prevUnrecoded_expOut_T_2 = FReg2_fs_3_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_3_prevUnrecoded_expOut_T_3 = FReg2_fs_3_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_3_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_3_prevUnrecoded_expOut_T_4 = FReg2_fs_3_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_3_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_3_prevUnrecoded_expOut_T_6 = _FReg2_fs_3_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_3_prevUnrecoded_expOut = _FReg2_fs_3_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_3_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_3_prevUnrecoded_fractOut_T_1 = FReg2_fs_3_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_3_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_3_prevUnrecoded_fractOut = FReg2_fs_3_prevUnrecoded_isSubnormal ?
    FReg2_fs_3_prevUnrecoded_denormFract : _FReg2_fs_3_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_3_prevUnrecoded = {FReg2_fs_3_unbx_sign,FReg2_fs_3_prevUnrecoded_expOut,
    FReg2_fs_3_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_3_T_2 = &io_diffFReg_19[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_3_T_4 = _FReg2_fs_3_T_2 ? FReg2_fs_3_prevUnrecoded : FReg2_fs_3_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_4_unbx_sign = FReg1_fs_4_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_4_unbx_fractIn = FReg1_fs_4_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_4_unbx_expIn = FReg1_fs_4_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_4_unbx_expOut_expCode = FReg2_fs_4_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_4_unbx_expOut_T = FReg2_fs_4_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_4_unrecoded_rawIn_exp = io_diffFReg_20[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_4_unrecoded_rawIn_isZero = FReg2_fs_4_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_4_unrecoded_rawIn_isSpecial = FReg2_fs_4_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_4_unrecoded_rawIn__isNaN = FReg2_fs_4_unrecoded_rawIn_isSpecial & FReg2_fs_4_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_4_unrecoded_rawIn__isInf = FReg2_fs_4_unrecoded_rawIn_isSpecial & ~FReg2_fs_4_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_4_unrecoded_rawIn__sign = io_diffFReg_20[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_4_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_4_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_4_unrecoded_rawIn_out_sig_T = ~FReg2_fs_4_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_4_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_4_unrecoded_rawIn_out_sig_T,io_diffFReg_20[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_4_unrecoded_isSubnormal = $signed(FReg2_fs_4_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_4_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_4_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_4_unrecoded_denormFract_T_1 = FReg2_fs_4_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_4_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_4_unrecoded_denormFract = _FReg2_fs_4_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_4_unrecoded_expOut_T_2 = FReg2_fs_4_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_4_unrecoded_expOut_T_3 = FReg2_fs_4_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_4_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_4_unrecoded_expOut_T_4 = FReg2_fs_4_unrecoded_rawIn__isNaN | FReg2_fs_4_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_4_unrecoded_expOut_T_6 = _FReg2_fs_4_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_4_unrecoded_expOut = _FReg2_fs_4_unrecoded_expOut_T_3 | _FReg2_fs_4_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_4_unrecoded_fractOut_T_1 = FReg2_fs_4_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_4_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_4_unrecoded_fractOut = FReg2_fs_4_unrecoded_isSubnormal ? FReg2_fs_4_unrecoded_denormFract :
    _FReg2_fs_4_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_4_unrecoded = {FReg2_fs_4_unrecoded_rawIn__sign,FReg2_fs_4_unrecoded_expOut,
    FReg2_fs_4_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_4_prevUnrecoded_rawIn_isSpecial = FReg2_fs_4_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_4_prevUnrecoded_rawIn__isNaN = FReg2_fs_4_prevUnrecoded_rawIn_isSpecial & FReg2_fs_4_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_4_prevUnrecoded_rawIn__isInf = FReg2_fs_4_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_4_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_4_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_4_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_4_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_4_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_4_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_4_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_4_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_4_prevUnrecoded_isSubnormal = $signed(FReg2_fs_4_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_4_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_4_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_4_prevUnrecoded_denormFract_T_1 = FReg2_fs_4_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_4_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_4_prevUnrecoded_denormFract = _FReg2_fs_4_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_4_prevUnrecoded_expOut_T_2 = FReg2_fs_4_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_4_prevUnrecoded_expOut_T_3 = FReg2_fs_4_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_4_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_4_prevUnrecoded_expOut_T_4 = FReg2_fs_4_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_4_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_4_prevUnrecoded_expOut_T_6 = _FReg2_fs_4_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_4_prevUnrecoded_expOut = _FReg2_fs_4_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_4_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_4_prevUnrecoded_fractOut_T_1 = FReg2_fs_4_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_4_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_4_prevUnrecoded_fractOut = FReg2_fs_4_prevUnrecoded_isSubnormal ?
    FReg2_fs_4_prevUnrecoded_denormFract : _FReg2_fs_4_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_4_prevUnrecoded = {FReg2_fs_4_unbx_sign,FReg2_fs_4_prevUnrecoded_expOut,
    FReg2_fs_4_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_4_T_2 = &io_diffFReg_20[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_4_T_4 = _FReg2_fs_4_T_2 ? FReg2_fs_4_prevUnrecoded : FReg2_fs_4_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_5_unbx_sign = FReg1_fs_5_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_5_unbx_fractIn = FReg1_fs_5_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_5_unbx_expIn = FReg1_fs_5_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_5_unbx_expOut_expCode = FReg2_fs_5_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_5_unbx_expOut_T = FReg2_fs_5_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_5_unrecoded_rawIn_exp = io_diffFReg_21[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_5_unrecoded_rawIn_isZero = FReg2_fs_5_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_5_unrecoded_rawIn_isSpecial = FReg2_fs_5_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_5_unrecoded_rawIn__isNaN = FReg2_fs_5_unrecoded_rawIn_isSpecial & FReg2_fs_5_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_5_unrecoded_rawIn__isInf = FReg2_fs_5_unrecoded_rawIn_isSpecial & ~FReg2_fs_5_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_5_unrecoded_rawIn__sign = io_diffFReg_21[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_5_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_5_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_5_unrecoded_rawIn_out_sig_T = ~FReg2_fs_5_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_5_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_5_unrecoded_rawIn_out_sig_T,io_diffFReg_21[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_5_unrecoded_isSubnormal = $signed(FReg2_fs_5_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_5_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_5_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_5_unrecoded_denormFract_T_1 = FReg2_fs_5_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_5_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_5_unrecoded_denormFract = _FReg2_fs_5_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_5_unrecoded_expOut_T_2 = FReg2_fs_5_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_5_unrecoded_expOut_T_3 = FReg2_fs_5_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_5_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_5_unrecoded_expOut_T_4 = FReg2_fs_5_unrecoded_rawIn__isNaN | FReg2_fs_5_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_5_unrecoded_expOut_T_6 = _FReg2_fs_5_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_5_unrecoded_expOut = _FReg2_fs_5_unrecoded_expOut_T_3 | _FReg2_fs_5_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_5_unrecoded_fractOut_T_1 = FReg2_fs_5_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_5_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_5_unrecoded_fractOut = FReg2_fs_5_unrecoded_isSubnormal ? FReg2_fs_5_unrecoded_denormFract :
    _FReg2_fs_5_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_5_unrecoded = {FReg2_fs_5_unrecoded_rawIn__sign,FReg2_fs_5_unrecoded_expOut,
    FReg2_fs_5_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_5_prevUnrecoded_rawIn_isSpecial = FReg2_fs_5_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_5_prevUnrecoded_rawIn__isNaN = FReg2_fs_5_prevUnrecoded_rawIn_isSpecial & FReg2_fs_5_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_5_prevUnrecoded_rawIn__isInf = FReg2_fs_5_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_5_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_5_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_5_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_5_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_5_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_5_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_5_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_5_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_5_prevUnrecoded_isSubnormal = $signed(FReg2_fs_5_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_5_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_5_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_5_prevUnrecoded_denormFract_T_1 = FReg2_fs_5_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_5_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_5_prevUnrecoded_denormFract = _FReg2_fs_5_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_5_prevUnrecoded_expOut_T_2 = FReg2_fs_5_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_5_prevUnrecoded_expOut_T_3 = FReg2_fs_5_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_5_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_5_prevUnrecoded_expOut_T_4 = FReg2_fs_5_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_5_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_5_prevUnrecoded_expOut_T_6 = _FReg2_fs_5_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_5_prevUnrecoded_expOut = _FReg2_fs_5_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_5_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_5_prevUnrecoded_fractOut_T_1 = FReg2_fs_5_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_5_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_5_prevUnrecoded_fractOut = FReg2_fs_5_prevUnrecoded_isSubnormal ?
    FReg2_fs_5_prevUnrecoded_denormFract : _FReg2_fs_5_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_5_prevUnrecoded = {FReg2_fs_5_unbx_sign,FReg2_fs_5_prevUnrecoded_expOut,
    FReg2_fs_5_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_5_T_2 = &io_diffFReg_21[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_5_T_4 = _FReg2_fs_5_T_2 ? FReg2_fs_5_prevUnrecoded : FReg2_fs_5_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_6_unbx_sign = FReg1_fs_6_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_6_unbx_fractIn = FReg1_fs_6_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_6_unbx_expIn = FReg1_fs_6_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_6_unbx_expOut_expCode = FReg2_fs_6_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_6_unbx_expOut_T = FReg2_fs_6_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_6_unrecoded_rawIn_exp = io_diffFReg_22[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_6_unrecoded_rawIn_isZero = FReg2_fs_6_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_6_unrecoded_rawIn_isSpecial = FReg2_fs_6_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_6_unrecoded_rawIn__isNaN = FReg2_fs_6_unrecoded_rawIn_isSpecial & FReg2_fs_6_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_6_unrecoded_rawIn__isInf = FReg2_fs_6_unrecoded_rawIn_isSpecial & ~FReg2_fs_6_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_6_unrecoded_rawIn__sign = io_diffFReg_22[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_6_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_6_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_6_unrecoded_rawIn_out_sig_T = ~FReg2_fs_6_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_6_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_6_unrecoded_rawIn_out_sig_T,io_diffFReg_22[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_6_unrecoded_isSubnormal = $signed(FReg2_fs_6_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_6_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_6_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_6_unrecoded_denormFract_T_1 = FReg2_fs_6_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_6_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_6_unrecoded_denormFract = _FReg2_fs_6_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_6_unrecoded_expOut_T_2 = FReg2_fs_6_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_6_unrecoded_expOut_T_3 = FReg2_fs_6_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_6_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_6_unrecoded_expOut_T_4 = FReg2_fs_6_unrecoded_rawIn__isNaN | FReg2_fs_6_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_6_unrecoded_expOut_T_6 = _FReg2_fs_6_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_6_unrecoded_expOut = _FReg2_fs_6_unrecoded_expOut_T_3 | _FReg2_fs_6_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_6_unrecoded_fractOut_T_1 = FReg2_fs_6_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_6_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_6_unrecoded_fractOut = FReg2_fs_6_unrecoded_isSubnormal ? FReg2_fs_6_unrecoded_denormFract :
    _FReg2_fs_6_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_6_unrecoded = {FReg2_fs_6_unrecoded_rawIn__sign,FReg2_fs_6_unrecoded_expOut,
    FReg2_fs_6_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_6_prevUnrecoded_rawIn_isSpecial = FReg2_fs_6_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_6_prevUnrecoded_rawIn__isNaN = FReg2_fs_6_prevUnrecoded_rawIn_isSpecial & FReg2_fs_6_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_6_prevUnrecoded_rawIn__isInf = FReg2_fs_6_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_6_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_6_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_6_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_6_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_6_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_6_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_6_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_6_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_6_prevUnrecoded_isSubnormal = $signed(FReg2_fs_6_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_6_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_6_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_6_prevUnrecoded_denormFract_T_1 = FReg2_fs_6_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_6_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_6_prevUnrecoded_denormFract = _FReg2_fs_6_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_6_prevUnrecoded_expOut_T_2 = FReg2_fs_6_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_6_prevUnrecoded_expOut_T_3 = FReg2_fs_6_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_6_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_6_prevUnrecoded_expOut_T_4 = FReg2_fs_6_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_6_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_6_prevUnrecoded_expOut_T_6 = _FReg2_fs_6_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_6_prevUnrecoded_expOut = _FReg2_fs_6_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_6_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_6_prevUnrecoded_fractOut_T_1 = FReg2_fs_6_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_6_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_6_prevUnrecoded_fractOut = FReg2_fs_6_prevUnrecoded_isSubnormal ?
    FReg2_fs_6_prevUnrecoded_denormFract : _FReg2_fs_6_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_6_prevUnrecoded = {FReg2_fs_6_unbx_sign,FReg2_fs_6_prevUnrecoded_expOut,
    FReg2_fs_6_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_6_T_2 = &io_diffFReg_22[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_6_T_4 = _FReg2_fs_6_T_2 ? FReg2_fs_6_prevUnrecoded : FReg2_fs_6_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_7_unbx_sign = FReg1_fs_7_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_7_unbx_fractIn = FReg1_fs_7_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_7_unbx_expIn = FReg1_fs_7_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_7_unbx_expOut_expCode = FReg2_fs_7_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_7_unbx_expOut_T = FReg2_fs_7_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_7_unrecoded_rawIn_exp = io_diffFReg_23[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_7_unrecoded_rawIn_isZero = FReg2_fs_7_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_7_unrecoded_rawIn_isSpecial = FReg2_fs_7_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_7_unrecoded_rawIn__isNaN = FReg2_fs_7_unrecoded_rawIn_isSpecial & FReg2_fs_7_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_7_unrecoded_rawIn__isInf = FReg2_fs_7_unrecoded_rawIn_isSpecial & ~FReg2_fs_7_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_7_unrecoded_rawIn__sign = io_diffFReg_23[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_7_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_7_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_7_unrecoded_rawIn_out_sig_T = ~FReg2_fs_7_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_7_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_7_unrecoded_rawIn_out_sig_T,io_diffFReg_23[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_7_unrecoded_isSubnormal = $signed(FReg2_fs_7_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_7_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_7_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_7_unrecoded_denormFract_T_1 = FReg2_fs_7_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_7_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_7_unrecoded_denormFract = _FReg2_fs_7_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_7_unrecoded_expOut_T_2 = FReg2_fs_7_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_7_unrecoded_expOut_T_3 = FReg2_fs_7_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_7_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_7_unrecoded_expOut_T_4 = FReg2_fs_7_unrecoded_rawIn__isNaN | FReg2_fs_7_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_7_unrecoded_expOut_T_6 = _FReg2_fs_7_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_7_unrecoded_expOut = _FReg2_fs_7_unrecoded_expOut_T_3 | _FReg2_fs_7_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_7_unrecoded_fractOut_T_1 = FReg2_fs_7_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_7_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_7_unrecoded_fractOut = FReg2_fs_7_unrecoded_isSubnormal ? FReg2_fs_7_unrecoded_denormFract :
    _FReg2_fs_7_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_7_unrecoded = {FReg2_fs_7_unrecoded_rawIn__sign,FReg2_fs_7_unrecoded_expOut,
    FReg2_fs_7_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_7_prevUnrecoded_rawIn_isSpecial = FReg2_fs_7_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_7_prevUnrecoded_rawIn__isNaN = FReg2_fs_7_prevUnrecoded_rawIn_isSpecial & FReg2_fs_7_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_7_prevUnrecoded_rawIn__isInf = FReg2_fs_7_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_7_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_7_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_7_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_7_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_7_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_7_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_7_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_7_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_7_prevUnrecoded_isSubnormal = $signed(FReg2_fs_7_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_7_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_7_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_7_prevUnrecoded_denormFract_T_1 = FReg2_fs_7_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_7_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_7_prevUnrecoded_denormFract = _FReg2_fs_7_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_7_prevUnrecoded_expOut_T_2 = FReg2_fs_7_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_7_prevUnrecoded_expOut_T_3 = FReg2_fs_7_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_7_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_7_prevUnrecoded_expOut_T_4 = FReg2_fs_7_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_7_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_7_prevUnrecoded_expOut_T_6 = _FReg2_fs_7_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_7_prevUnrecoded_expOut = _FReg2_fs_7_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_7_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_7_prevUnrecoded_fractOut_T_1 = FReg2_fs_7_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_7_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_7_prevUnrecoded_fractOut = FReg2_fs_7_prevUnrecoded_isSubnormal ?
    FReg2_fs_7_prevUnrecoded_denormFract : _FReg2_fs_7_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_7_prevUnrecoded = {FReg2_fs_7_unbx_sign,FReg2_fs_7_prevUnrecoded_expOut,
    FReg2_fs_7_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_7_T_2 = &io_diffFReg_23[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_7_T_4 = _FReg2_fs_7_T_2 ? FReg2_fs_7_prevUnrecoded : FReg2_fs_7_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_8_unbx_sign = FReg1_fs_8_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_8_unbx_fractIn = FReg1_fs_8_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_8_unbx_expIn = FReg1_fs_8_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_8_unbx_expOut_expCode = FReg2_fs_8_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_8_unbx_expOut_T = FReg2_fs_8_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_8_unrecoded_rawIn_exp = io_diffFReg_24[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_8_unrecoded_rawIn_isZero = FReg2_fs_8_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_8_unrecoded_rawIn_isSpecial = FReg2_fs_8_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_8_unrecoded_rawIn__isNaN = FReg2_fs_8_unrecoded_rawIn_isSpecial & FReg2_fs_8_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_8_unrecoded_rawIn__isInf = FReg2_fs_8_unrecoded_rawIn_isSpecial & ~FReg2_fs_8_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_8_unrecoded_rawIn__sign = io_diffFReg_24[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_8_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_8_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_8_unrecoded_rawIn_out_sig_T = ~FReg2_fs_8_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_8_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_8_unrecoded_rawIn_out_sig_T,io_diffFReg_24[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_8_unrecoded_isSubnormal = $signed(FReg2_fs_8_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_8_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_8_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_8_unrecoded_denormFract_T_1 = FReg2_fs_8_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_8_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_8_unrecoded_denormFract = _FReg2_fs_8_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_8_unrecoded_expOut_T_2 = FReg2_fs_8_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_8_unrecoded_expOut_T_3 = FReg2_fs_8_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_8_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_8_unrecoded_expOut_T_4 = FReg2_fs_8_unrecoded_rawIn__isNaN | FReg2_fs_8_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_8_unrecoded_expOut_T_6 = _FReg2_fs_8_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_8_unrecoded_expOut = _FReg2_fs_8_unrecoded_expOut_T_3 | _FReg2_fs_8_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_8_unrecoded_fractOut_T_1 = FReg2_fs_8_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_8_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_8_unrecoded_fractOut = FReg2_fs_8_unrecoded_isSubnormal ? FReg2_fs_8_unrecoded_denormFract :
    _FReg2_fs_8_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_8_unrecoded = {FReg2_fs_8_unrecoded_rawIn__sign,FReg2_fs_8_unrecoded_expOut,
    FReg2_fs_8_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_8_prevUnrecoded_rawIn_isSpecial = FReg2_fs_8_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_8_prevUnrecoded_rawIn__isNaN = FReg2_fs_8_prevUnrecoded_rawIn_isSpecial & FReg2_fs_8_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_8_prevUnrecoded_rawIn__isInf = FReg2_fs_8_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_8_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_8_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_8_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_8_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_8_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_8_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_8_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_8_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_8_prevUnrecoded_isSubnormal = $signed(FReg2_fs_8_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_8_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_8_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_8_prevUnrecoded_denormFract_T_1 = FReg2_fs_8_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_8_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_8_prevUnrecoded_denormFract = _FReg2_fs_8_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_8_prevUnrecoded_expOut_T_2 = FReg2_fs_8_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_8_prevUnrecoded_expOut_T_3 = FReg2_fs_8_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_8_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_8_prevUnrecoded_expOut_T_4 = FReg2_fs_8_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_8_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_8_prevUnrecoded_expOut_T_6 = _FReg2_fs_8_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_8_prevUnrecoded_expOut = _FReg2_fs_8_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_8_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_8_prevUnrecoded_fractOut_T_1 = FReg2_fs_8_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_8_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_8_prevUnrecoded_fractOut = FReg2_fs_8_prevUnrecoded_isSubnormal ?
    FReg2_fs_8_prevUnrecoded_denormFract : _FReg2_fs_8_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_8_prevUnrecoded = {FReg2_fs_8_unbx_sign,FReg2_fs_8_prevUnrecoded_expOut,
    FReg2_fs_8_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_8_T_2 = &io_diffFReg_24[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_8_T_4 = _FReg2_fs_8_T_2 ? FReg2_fs_8_prevUnrecoded : FReg2_fs_8_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_9_unbx_sign = FReg1_fs_9_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_9_unbx_fractIn = FReg1_fs_9_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_9_unbx_expIn = FReg1_fs_9_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_9_unbx_expOut_expCode = FReg2_fs_9_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_9_unbx_expOut_T = FReg2_fs_9_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_9_unrecoded_rawIn_exp = io_diffFReg_25[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_9_unrecoded_rawIn_isZero = FReg2_fs_9_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_9_unrecoded_rawIn_isSpecial = FReg2_fs_9_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_9_unrecoded_rawIn__isNaN = FReg2_fs_9_unrecoded_rawIn_isSpecial & FReg2_fs_9_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_9_unrecoded_rawIn__isInf = FReg2_fs_9_unrecoded_rawIn_isSpecial & ~FReg2_fs_9_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_9_unrecoded_rawIn__sign = io_diffFReg_25[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_9_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_9_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_9_unrecoded_rawIn_out_sig_T = ~FReg2_fs_9_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_9_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_9_unrecoded_rawIn_out_sig_T,io_diffFReg_25[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_9_unrecoded_isSubnormal = $signed(FReg2_fs_9_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_9_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_9_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_9_unrecoded_denormFract_T_1 = FReg2_fs_9_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_9_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_9_unrecoded_denormFract = _FReg2_fs_9_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_9_unrecoded_expOut_T_2 = FReg2_fs_9_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_9_unrecoded_expOut_T_3 = FReg2_fs_9_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_9_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_9_unrecoded_expOut_T_4 = FReg2_fs_9_unrecoded_rawIn__isNaN | FReg2_fs_9_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_9_unrecoded_expOut_T_6 = _FReg2_fs_9_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_9_unrecoded_expOut = _FReg2_fs_9_unrecoded_expOut_T_3 | _FReg2_fs_9_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_9_unrecoded_fractOut_T_1 = FReg2_fs_9_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_9_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_9_unrecoded_fractOut = FReg2_fs_9_unrecoded_isSubnormal ? FReg2_fs_9_unrecoded_denormFract :
    _FReg2_fs_9_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_9_unrecoded = {FReg2_fs_9_unrecoded_rawIn__sign,FReg2_fs_9_unrecoded_expOut,
    FReg2_fs_9_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_9_prevUnrecoded_rawIn_isSpecial = FReg2_fs_9_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_9_prevUnrecoded_rawIn__isNaN = FReg2_fs_9_prevUnrecoded_rawIn_isSpecial & FReg2_fs_9_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_9_prevUnrecoded_rawIn__isInf = FReg2_fs_9_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_9_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_9_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_9_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_9_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_9_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_9_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_9_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_9_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_9_prevUnrecoded_isSubnormal = $signed(FReg2_fs_9_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_9_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_9_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_9_prevUnrecoded_denormFract_T_1 = FReg2_fs_9_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_9_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_9_prevUnrecoded_denormFract = _FReg2_fs_9_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_9_prevUnrecoded_expOut_T_2 = FReg2_fs_9_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_9_prevUnrecoded_expOut_T_3 = FReg2_fs_9_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_9_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_9_prevUnrecoded_expOut_T_4 = FReg2_fs_9_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_9_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_9_prevUnrecoded_expOut_T_6 = _FReg2_fs_9_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_9_prevUnrecoded_expOut = _FReg2_fs_9_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_9_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_9_prevUnrecoded_fractOut_T_1 = FReg2_fs_9_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_9_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_9_prevUnrecoded_fractOut = FReg2_fs_9_prevUnrecoded_isSubnormal ?
    FReg2_fs_9_prevUnrecoded_denormFract : _FReg2_fs_9_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_9_prevUnrecoded = {FReg2_fs_9_unbx_sign,FReg2_fs_9_prevUnrecoded_expOut,
    FReg2_fs_9_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_9_T_2 = &io_diffFReg_25[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_9_T_4 = _FReg2_fs_9_T_2 ? FReg2_fs_9_prevUnrecoded : FReg2_fs_9_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_10_unbx_sign = FReg1_fs_10_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_10_unbx_fractIn = FReg1_fs_10_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_10_unbx_expIn = FReg1_fs_10_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_10_unbx_expOut_expCode = FReg2_fs_10_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_10_unbx_expOut_T = FReg2_fs_10_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_10_unrecoded_rawIn_exp = io_diffFReg_26[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_10_unrecoded_rawIn_isZero = FReg2_fs_10_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_10_unrecoded_rawIn_isSpecial = FReg2_fs_10_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_10_unrecoded_rawIn__isNaN = FReg2_fs_10_unrecoded_rawIn_isSpecial & FReg2_fs_10_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_10_unrecoded_rawIn__isInf = FReg2_fs_10_unrecoded_rawIn_isSpecial & ~FReg2_fs_10_unrecoded_rawIn_exp[9]
    ; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_10_unrecoded_rawIn__sign = io_diffFReg_26[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_10_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_10_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_10_unrecoded_rawIn_out_sig_T = ~FReg2_fs_10_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_10_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_10_unrecoded_rawIn_out_sig_T,io_diffFReg_26[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_10_unrecoded_isSubnormal = $signed(FReg2_fs_10_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_10_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_10_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_10_unrecoded_denormFract_T_1 = FReg2_fs_10_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_10_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_10_unrecoded_denormFract = _FReg2_fs_10_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_10_unrecoded_expOut_T_2 = FReg2_fs_10_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_10_unrecoded_expOut_T_3 = FReg2_fs_10_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_10_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_10_unrecoded_expOut_T_4 = FReg2_fs_10_unrecoded_rawIn__isNaN | FReg2_fs_10_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_10_unrecoded_expOut_T_6 = _FReg2_fs_10_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_10_unrecoded_expOut = _FReg2_fs_10_unrecoded_expOut_T_3 | _FReg2_fs_10_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_10_unrecoded_fractOut_T_1 = FReg2_fs_10_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_10_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_10_unrecoded_fractOut = FReg2_fs_10_unrecoded_isSubnormal ? FReg2_fs_10_unrecoded_denormFract :
    _FReg2_fs_10_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_10_unrecoded = {FReg2_fs_10_unrecoded_rawIn__sign,FReg2_fs_10_unrecoded_expOut,
    FReg2_fs_10_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_10_prevUnrecoded_rawIn_isSpecial = FReg2_fs_10_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_10_prevUnrecoded_rawIn__isNaN = FReg2_fs_10_prevUnrecoded_rawIn_isSpecial & FReg2_fs_10_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_10_prevUnrecoded_rawIn__isInf = FReg2_fs_10_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_10_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_10_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_10_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_10_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_10_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_10_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_10_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_10_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_10_prevUnrecoded_isSubnormal = $signed(FReg2_fs_10_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_10_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_10_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_10_prevUnrecoded_denormFract_T_1 = FReg2_fs_10_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_10_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_10_prevUnrecoded_denormFract = _FReg2_fs_10_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_10_prevUnrecoded_expOut_T_2 = FReg2_fs_10_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_10_prevUnrecoded_expOut_T_3 = FReg2_fs_10_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_10_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_10_prevUnrecoded_expOut_T_4 = FReg2_fs_10_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_10_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_10_prevUnrecoded_expOut_T_6 = _FReg2_fs_10_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_10_prevUnrecoded_expOut = _FReg2_fs_10_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_10_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_10_prevUnrecoded_fractOut_T_1 = FReg2_fs_10_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_10_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_10_prevUnrecoded_fractOut = FReg2_fs_10_prevUnrecoded_isSubnormal ?
    FReg2_fs_10_prevUnrecoded_denormFract : _FReg2_fs_10_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_10_prevUnrecoded = {FReg2_fs_10_unbx_sign,FReg2_fs_10_prevUnrecoded_expOut,
    FReg2_fs_10_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_10_T_2 = &io_diffFReg_26[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_10_T_4 = _FReg2_fs_10_T_2 ? FReg2_fs_10_prevUnrecoded : FReg2_fs_10_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_fs_11_unbx_sign = FReg1_fs_11_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_fs_11_unbx_fractIn = FReg1_fs_11_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_fs_11_unbx_expIn = FReg1_fs_11_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_fs_11_unbx_expOut_expCode = FReg2_fs_11_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_fs_11_unbx_expOut_T = FReg2_fs_11_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_fs_11_unrecoded_rawIn_exp = io_diffFReg_27[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_fs_11_unrecoded_rawIn_isZero = FReg2_fs_11_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_fs_11_unrecoded_rawIn_isSpecial = FReg2_fs_11_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_11_unrecoded_rawIn__isNaN = FReg2_fs_11_unrecoded_rawIn_isSpecial & FReg2_fs_11_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_11_unrecoded_rawIn__isInf = FReg2_fs_11_unrecoded_rawIn_isSpecial & ~FReg2_fs_11_unrecoded_rawIn_exp[9]
    ; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_fs_11_unrecoded_rawIn__sign = io_diffFReg_27[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_fs_11_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_11_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_11_unrecoded_rawIn_out_sig_T = ~FReg2_fs_11_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_fs_11_unrecoded_rawIn__sig = {1'h0,_FReg2_fs_11_unrecoded_rawIn_out_sig_T,io_diffFReg_27[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_fs_11_unrecoded_isSubnormal = $signed(FReg2_fs_11_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_fs_11_unrecoded_denormShiftDist = 6'h1 - FReg2_fs_11_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_fs_11_unrecoded_denormFract_T_1 = FReg2_fs_11_unrecoded_rawIn__sig[53:1] >>
    FReg2_fs_11_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_fs_11_unrecoded_denormFract = _FReg2_fs_11_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_fs_11_unrecoded_expOut_T_2 = FReg2_fs_11_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_fs_11_unrecoded_expOut_T_3 = FReg2_fs_11_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_fs_11_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_11_unrecoded_expOut_T_4 = FReg2_fs_11_unrecoded_rawIn__isNaN | FReg2_fs_11_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_fs_11_unrecoded_expOut_T_6 = _FReg2_fs_11_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_fs_11_unrecoded_expOut = _FReg2_fs_11_unrecoded_expOut_T_3 | _FReg2_fs_11_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_fs_11_unrecoded_fractOut_T_1 = FReg2_fs_11_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_fs_11_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_fs_11_unrecoded_fractOut = FReg2_fs_11_unrecoded_isSubnormal ? FReg2_fs_11_unrecoded_denormFract :
    _FReg2_fs_11_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_fs_11_unrecoded = {FReg2_fs_11_unrecoded_rawIn__sign,FReg2_fs_11_unrecoded_expOut,
    FReg2_fs_11_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_fs_11_prevUnrecoded_rawIn_isSpecial = FReg2_fs_11_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_fs_11_prevUnrecoded_rawIn__isNaN = FReg2_fs_11_prevUnrecoded_rawIn_isSpecial & FReg2_fs_11_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_fs_11_prevUnrecoded_rawIn__isInf = FReg2_fs_11_prevUnrecoded_rawIn_isSpecial & ~FReg2_fs_11_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_fs_11_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_fs_11_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_fs_11_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_fs_11_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_fs_11_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_fs_11_prevUnrecoded_rawIn_out_sig_T,
    FReg2_fs_11_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_fs_11_prevUnrecoded_isSubnormal = $signed(FReg2_fs_11_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_fs_11_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_fs_11_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_fs_11_prevUnrecoded_denormFract_T_1 = FReg2_fs_11_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_fs_11_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_fs_11_prevUnrecoded_denormFract = _FReg2_fs_11_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_fs_11_prevUnrecoded_expOut_T_2 = FReg2_fs_11_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_fs_11_prevUnrecoded_expOut_T_3 = FReg2_fs_11_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_fs_11_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_fs_11_prevUnrecoded_expOut_T_4 = FReg2_fs_11_prevUnrecoded_rawIn__isNaN |
    FReg2_fs_11_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_fs_11_prevUnrecoded_expOut_T_6 = _FReg2_fs_11_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_fs_11_prevUnrecoded_expOut = _FReg2_fs_11_prevUnrecoded_expOut_T_3 |
    _FReg2_fs_11_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_fs_11_prevUnrecoded_fractOut_T_1 = FReg2_fs_11_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_fs_11_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_fs_11_prevUnrecoded_fractOut = FReg2_fs_11_prevUnrecoded_isSubnormal ?
    FReg2_fs_11_prevUnrecoded_denormFract : _FReg2_fs_11_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_fs_11_prevUnrecoded = {FReg2_fs_11_unbx_sign,FReg2_fs_11_prevUnrecoded_expOut,
    FReg2_fs_11_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_fs_11_T_2 = &io_diffFReg_27[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_fs_11_T_4 = _FReg2_fs_11_T_2 ? FReg2_fs_11_prevUnrecoded : FReg2_fs_11_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_8_unbx_sign = FReg1_ft_8_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_8_unbx_fractIn = FReg1_ft_8_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_8_unbx_expIn = FReg1_ft_8_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_8_unbx_expOut_expCode = FReg2_ft_8_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_8_unbx_expOut_T = FReg2_ft_8_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_8_unrecoded_rawIn_exp = io_diffFReg_28[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_8_unrecoded_rawIn_isZero = FReg2_ft_8_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_8_unrecoded_rawIn_isSpecial = FReg2_ft_8_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_8_unrecoded_rawIn__isNaN = FReg2_ft_8_unrecoded_rawIn_isSpecial & FReg2_ft_8_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_8_unrecoded_rawIn__isInf = FReg2_ft_8_unrecoded_rawIn_isSpecial & ~FReg2_ft_8_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_8_unrecoded_rawIn__sign = io_diffFReg_28[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_8_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_8_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_8_unrecoded_rawIn_out_sig_T = ~FReg2_ft_8_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_8_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_8_unrecoded_rawIn_out_sig_T,io_diffFReg_28[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_8_unrecoded_isSubnormal = $signed(FReg2_ft_8_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_8_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_8_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_8_unrecoded_denormFract_T_1 = FReg2_ft_8_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_8_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_8_unrecoded_denormFract = _FReg2_ft_8_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_8_unrecoded_expOut_T_2 = FReg2_ft_8_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_8_unrecoded_expOut_T_3 = FReg2_ft_8_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_8_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_8_unrecoded_expOut_T_4 = FReg2_ft_8_unrecoded_rawIn__isNaN | FReg2_ft_8_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_8_unrecoded_expOut_T_6 = _FReg2_ft_8_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_8_unrecoded_expOut = _FReg2_ft_8_unrecoded_expOut_T_3 | _FReg2_ft_8_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_8_unrecoded_fractOut_T_1 = FReg2_ft_8_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_8_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_8_unrecoded_fractOut = FReg2_ft_8_unrecoded_isSubnormal ? FReg2_ft_8_unrecoded_denormFract :
    _FReg2_ft_8_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_8_unrecoded = {FReg2_ft_8_unrecoded_rawIn__sign,FReg2_ft_8_unrecoded_expOut,
    FReg2_ft_8_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_8_prevUnrecoded_rawIn_isSpecial = FReg2_ft_8_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_8_prevUnrecoded_rawIn__isNaN = FReg2_ft_8_prevUnrecoded_rawIn_isSpecial & FReg2_ft_8_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_8_prevUnrecoded_rawIn__isInf = FReg2_ft_8_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_8_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_8_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_8_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_8_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_8_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_8_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_8_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_8_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_8_prevUnrecoded_isSubnormal = $signed(FReg2_ft_8_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_8_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_8_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_8_prevUnrecoded_denormFract_T_1 = FReg2_ft_8_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_8_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_8_prevUnrecoded_denormFract = _FReg2_ft_8_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_8_prevUnrecoded_expOut_T_2 = FReg2_ft_8_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_8_prevUnrecoded_expOut_T_3 = FReg2_ft_8_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_8_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_8_prevUnrecoded_expOut_T_4 = FReg2_ft_8_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_8_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_8_prevUnrecoded_expOut_T_6 = _FReg2_ft_8_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_8_prevUnrecoded_expOut = _FReg2_ft_8_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_8_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_8_prevUnrecoded_fractOut_T_1 = FReg2_ft_8_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_8_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_8_prevUnrecoded_fractOut = FReg2_ft_8_prevUnrecoded_isSubnormal ?
    FReg2_ft_8_prevUnrecoded_denormFract : _FReg2_ft_8_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_8_prevUnrecoded = {FReg2_ft_8_unbx_sign,FReg2_ft_8_prevUnrecoded_expOut,
    FReg2_ft_8_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_8_T_2 = &io_diffFReg_28[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_8_T_4 = _FReg2_ft_8_T_2 ? FReg2_ft_8_prevUnrecoded : FReg2_ft_8_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_9_unbx_sign = FReg1_ft_9_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_9_unbx_fractIn = FReg1_ft_9_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_9_unbx_expIn = FReg1_ft_9_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_9_unbx_expOut_expCode = FReg2_ft_9_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_9_unbx_expOut_T = FReg2_ft_9_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_9_unrecoded_rawIn_exp = io_diffFReg_29[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_9_unrecoded_rawIn_isZero = FReg2_ft_9_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_9_unrecoded_rawIn_isSpecial = FReg2_ft_9_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_9_unrecoded_rawIn__isNaN = FReg2_ft_9_unrecoded_rawIn_isSpecial & FReg2_ft_9_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_9_unrecoded_rawIn__isInf = FReg2_ft_9_unrecoded_rawIn_isSpecial & ~FReg2_ft_9_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_9_unrecoded_rawIn__sign = io_diffFReg_29[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_9_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_9_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_9_unrecoded_rawIn_out_sig_T = ~FReg2_ft_9_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_9_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_9_unrecoded_rawIn_out_sig_T,io_diffFReg_29[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_9_unrecoded_isSubnormal = $signed(FReg2_ft_9_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_9_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_9_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_9_unrecoded_denormFract_T_1 = FReg2_ft_9_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_9_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_9_unrecoded_denormFract = _FReg2_ft_9_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_9_unrecoded_expOut_T_2 = FReg2_ft_9_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_9_unrecoded_expOut_T_3 = FReg2_ft_9_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_9_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_9_unrecoded_expOut_T_4 = FReg2_ft_9_unrecoded_rawIn__isNaN | FReg2_ft_9_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_9_unrecoded_expOut_T_6 = _FReg2_ft_9_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_9_unrecoded_expOut = _FReg2_ft_9_unrecoded_expOut_T_3 | _FReg2_ft_9_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_9_unrecoded_fractOut_T_1 = FReg2_ft_9_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_9_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_9_unrecoded_fractOut = FReg2_ft_9_unrecoded_isSubnormal ? FReg2_ft_9_unrecoded_denormFract :
    _FReg2_ft_9_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_9_unrecoded = {FReg2_ft_9_unrecoded_rawIn__sign,FReg2_ft_9_unrecoded_expOut,
    FReg2_ft_9_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_9_prevUnrecoded_rawIn_isSpecial = FReg2_ft_9_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_9_prevUnrecoded_rawIn__isNaN = FReg2_ft_9_prevUnrecoded_rawIn_isSpecial & FReg2_ft_9_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_9_prevUnrecoded_rawIn__isInf = FReg2_ft_9_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_9_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_9_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_9_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_9_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_9_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_9_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_9_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_9_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_9_prevUnrecoded_isSubnormal = $signed(FReg2_ft_9_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_9_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_9_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_9_prevUnrecoded_denormFract_T_1 = FReg2_ft_9_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_9_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_9_prevUnrecoded_denormFract = _FReg2_ft_9_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_9_prevUnrecoded_expOut_T_2 = FReg2_ft_9_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_9_prevUnrecoded_expOut_T_3 = FReg2_ft_9_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_9_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_9_prevUnrecoded_expOut_T_4 = FReg2_ft_9_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_9_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_9_prevUnrecoded_expOut_T_6 = _FReg2_ft_9_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_9_prevUnrecoded_expOut = _FReg2_ft_9_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_9_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_9_prevUnrecoded_fractOut_T_1 = FReg2_ft_9_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_9_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_9_prevUnrecoded_fractOut = FReg2_ft_9_prevUnrecoded_isSubnormal ?
    FReg2_ft_9_prevUnrecoded_denormFract : _FReg2_ft_9_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_9_prevUnrecoded = {FReg2_ft_9_unbx_sign,FReg2_ft_9_prevUnrecoded_expOut,
    FReg2_ft_9_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_9_T_2 = &io_diffFReg_29[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_9_T_4 = _FReg2_ft_9_T_2 ? FReg2_ft_9_prevUnrecoded : FReg2_ft_9_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_10_unbx_sign = FReg1_ft_10_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_10_unbx_fractIn = FReg1_ft_10_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_10_unbx_expIn = FReg1_ft_10_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_10_unbx_expOut_expCode = FReg2_ft_10_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_10_unbx_expOut_T = FReg2_ft_10_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_10_unrecoded_rawIn_exp = io_diffFReg_30[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_10_unrecoded_rawIn_isZero = FReg2_ft_10_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_10_unrecoded_rawIn_isSpecial = FReg2_ft_10_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_10_unrecoded_rawIn__isNaN = FReg2_ft_10_unrecoded_rawIn_isSpecial & FReg2_ft_10_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_10_unrecoded_rawIn__isInf = FReg2_ft_10_unrecoded_rawIn_isSpecial & ~FReg2_ft_10_unrecoded_rawIn_exp[9]
    ; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_10_unrecoded_rawIn__sign = io_diffFReg_30[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_10_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_10_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_10_unrecoded_rawIn_out_sig_T = ~FReg2_ft_10_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_10_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_10_unrecoded_rawIn_out_sig_T,io_diffFReg_30[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_10_unrecoded_isSubnormal = $signed(FReg2_ft_10_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_10_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_10_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_10_unrecoded_denormFract_T_1 = FReg2_ft_10_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_10_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_10_unrecoded_denormFract = _FReg2_ft_10_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_10_unrecoded_expOut_T_2 = FReg2_ft_10_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_10_unrecoded_expOut_T_3 = FReg2_ft_10_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_10_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_10_unrecoded_expOut_T_4 = FReg2_ft_10_unrecoded_rawIn__isNaN | FReg2_ft_10_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_10_unrecoded_expOut_T_6 = _FReg2_ft_10_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_10_unrecoded_expOut = _FReg2_ft_10_unrecoded_expOut_T_3 | _FReg2_ft_10_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_10_unrecoded_fractOut_T_1 = FReg2_ft_10_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_10_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_10_unrecoded_fractOut = FReg2_ft_10_unrecoded_isSubnormal ? FReg2_ft_10_unrecoded_denormFract :
    _FReg2_ft_10_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_10_unrecoded = {FReg2_ft_10_unrecoded_rawIn__sign,FReg2_ft_10_unrecoded_expOut,
    FReg2_ft_10_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_10_prevUnrecoded_rawIn_isSpecial = FReg2_ft_10_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_10_prevUnrecoded_rawIn__isNaN = FReg2_ft_10_prevUnrecoded_rawIn_isSpecial & FReg2_ft_10_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_10_prevUnrecoded_rawIn__isInf = FReg2_ft_10_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_10_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_10_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_10_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_10_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_10_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_10_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_10_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_10_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_10_prevUnrecoded_isSubnormal = $signed(FReg2_ft_10_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_10_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_10_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_10_prevUnrecoded_denormFract_T_1 = FReg2_ft_10_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_10_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_10_prevUnrecoded_denormFract = _FReg2_ft_10_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_10_prevUnrecoded_expOut_T_2 = FReg2_ft_10_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_10_prevUnrecoded_expOut_T_3 = FReg2_ft_10_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_10_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_10_prevUnrecoded_expOut_T_4 = FReg2_ft_10_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_10_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_10_prevUnrecoded_expOut_T_6 = _FReg2_ft_10_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_10_prevUnrecoded_expOut = _FReg2_ft_10_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_10_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_10_prevUnrecoded_fractOut_T_1 = FReg2_ft_10_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_10_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_10_prevUnrecoded_fractOut = FReg2_ft_10_prevUnrecoded_isSubnormal ?
    FReg2_ft_10_prevUnrecoded_denormFract : _FReg2_ft_10_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_10_prevUnrecoded = {FReg2_ft_10_unbx_sign,FReg2_ft_10_prevUnrecoded_expOut,
    FReg2_ft_10_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_10_T_2 = &io_diffFReg_30[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_10_T_4 = _FReg2_ft_10_T_2 ? FReg2_ft_10_prevUnrecoded : FReg2_ft_10_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire  FReg2_ft_11_unbx_sign = FReg1_ft_11_unbx_floats_0[32]; // @[Fpu.scala 59:17]
  wire [22:0] FReg2_ft_11_unbx_fractIn = FReg1_ft_11_unbx_floats_0[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] FReg2_ft_11_unbx_expIn = FReg1_ft_11_unbx_floats_0[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] FReg2_ft_11_unbx_expOut_expCode = FReg2_ft_11_unbx_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  _FReg2_ft_11_unbx_expOut_T = FReg2_ft_11_unbx_expOut_expCode == 3'h0; // @[Fpu.scala 66:19]
  wire [11:0] FReg2_ft_11_unrecoded_rawIn_exp = io_diffFReg_31[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire  FReg2_ft_11_unrecoded_rawIn_isZero = FReg2_ft_11_unrecoded_rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire  FReg2_ft_11_unrecoded_rawIn_isSpecial = FReg2_ft_11_unrecoded_rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_11_unrecoded_rawIn__isNaN = FReg2_ft_11_unrecoded_rawIn_isSpecial & FReg2_ft_11_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_11_unrecoded_rawIn__isInf = FReg2_ft_11_unrecoded_rawIn_isSpecial & ~FReg2_ft_11_unrecoded_rawIn_exp[9]
    ; // @[rawFloatFromRecFN.scala 56:33]
  wire  FReg2_ft_11_unrecoded_rawIn__sign = io_diffFReg_31[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] FReg2_ft_11_unrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_11_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_11_unrecoded_rawIn_out_sig_T = ~FReg2_ft_11_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [53:0] FReg2_ft_11_unrecoded_rawIn__sig = {1'h0,_FReg2_ft_11_unrecoded_rawIn_out_sig_T,io_diffFReg_31[51:0]}; // @[Cat.scala 33:92]
  wire  FReg2_ft_11_unrecoded_isSubnormal = $signed(FReg2_ft_11_unrecoded_rawIn__sExp) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] FReg2_ft_11_unrecoded_denormShiftDist = 6'h1 - FReg2_ft_11_unrecoded_rawIn__sExp[5:0]; // @[fNFromRecFN.scala 51:39]
  wire [52:0] _FReg2_ft_11_unrecoded_denormFract_T_1 = FReg2_ft_11_unrecoded_rawIn__sig[53:1] >>
    FReg2_ft_11_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] FReg2_ft_11_unrecoded_denormFract = _FReg2_ft_11_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] _FReg2_ft_11_unrecoded_expOut_T_2 = FReg2_ft_11_unrecoded_rawIn__sExp[10:0] - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] _FReg2_ft_11_unrecoded_expOut_T_3 = FReg2_ft_11_unrecoded_isSubnormal ? 11'h0 :
    _FReg2_ft_11_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_11_unrecoded_expOut_T_4 = FReg2_ft_11_unrecoded_rawIn__isNaN | FReg2_ft_11_unrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [10:0] _FReg2_ft_11_unrecoded_expOut_T_6 = _FReg2_ft_11_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] FReg2_ft_11_unrecoded_expOut = _FReg2_ft_11_unrecoded_expOut_T_3 | _FReg2_ft_11_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] _FReg2_ft_11_unrecoded_fractOut_T_1 = FReg2_ft_11_unrecoded_rawIn__isInf ? 52'h0 :
    FReg2_ft_11_unrecoded_rawIn__sig[51:0]; // @[fNFromRecFN.scala 63:20]
  wire [51:0] FReg2_ft_11_unrecoded_fractOut = FReg2_ft_11_unrecoded_isSubnormal ? FReg2_ft_11_unrecoded_denormFract :
    _FReg2_ft_11_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] FReg2_ft_11_unrecoded = {FReg2_ft_11_unrecoded_rawIn__sign,FReg2_ft_11_unrecoded_expOut,
    FReg2_ft_11_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  FReg2_ft_11_prevUnrecoded_rawIn_isSpecial = FReg2_ft_11_unbx_expIn[8:7] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  FReg2_ft_11_prevUnrecoded_rawIn__isNaN = FReg2_ft_11_prevUnrecoded_rawIn_isSpecial & FReg2_ft_11_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 55:33]
  wire  FReg2_ft_11_prevUnrecoded_rawIn__isInf = FReg2_ft_11_prevUnrecoded_rawIn_isSpecial & ~FReg2_ft_11_unbx_expIn[6]; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] FReg2_ft_11_prevUnrecoded_rawIn__sExp = {1'b0,$signed(FReg2_ft_11_unbx_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  _FReg2_ft_11_prevUnrecoded_rawIn_out_sig_T = ~_FReg2_ft_11_unbx_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] FReg2_ft_11_prevUnrecoded_rawIn__sig = {1'h0,_FReg2_ft_11_prevUnrecoded_rawIn_out_sig_T,
    FReg2_ft_11_unbx_fractIn}; // @[Cat.scala 33:92]
  wire  FReg2_ft_11_prevUnrecoded_isSubnormal = $signed(FReg2_ft_11_prevUnrecoded_rawIn__sExp) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] FReg2_ft_11_prevUnrecoded_denormShiftDist = 5'h1 - FReg2_ft_11_prevUnrecoded_rawIn__sExp[4:0]; // @[fNFromRecFN.scala 51:39]
  wire [23:0] _FReg2_ft_11_prevUnrecoded_denormFract_T_1 = FReg2_ft_11_prevUnrecoded_rawIn__sig[24:1] >>
    FReg2_ft_11_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] FReg2_ft_11_prevUnrecoded_denormFract = _FReg2_ft_11_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] _FReg2_ft_11_prevUnrecoded_expOut_T_2 = FReg2_ft_11_prevUnrecoded_rawIn__sExp[7:0] - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] _FReg2_ft_11_prevUnrecoded_expOut_T_3 = FReg2_ft_11_prevUnrecoded_isSubnormal ? 8'h0 :
    _FReg2_ft_11_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  _FReg2_ft_11_prevUnrecoded_expOut_T_4 = FReg2_ft_11_prevUnrecoded_rawIn__isNaN |
    FReg2_ft_11_prevUnrecoded_rawIn__isInf; // @[fNFromRecFN.scala 59:44]
  wire [7:0] _FReg2_ft_11_prevUnrecoded_expOut_T_6 = _FReg2_ft_11_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] FReg2_ft_11_prevUnrecoded_expOut = _FReg2_ft_11_prevUnrecoded_expOut_T_3 |
    _FReg2_ft_11_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] _FReg2_ft_11_prevUnrecoded_fractOut_T_1 = FReg2_ft_11_prevUnrecoded_rawIn__isInf ? 23'h0 :
    FReg2_ft_11_prevUnrecoded_rawIn__sig[22:0]; // @[fNFromRecFN.scala 63:20]
  wire [22:0] FReg2_ft_11_prevUnrecoded_fractOut = FReg2_ft_11_prevUnrecoded_isSubnormal ?
    FReg2_ft_11_prevUnrecoded_denormFract : _FReg2_ft_11_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] FReg2_ft_11_prevUnrecoded = {FReg2_ft_11_unbx_sign,FReg2_ft_11_prevUnrecoded_expOut,
    FReg2_ft_11_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire  _FReg2_ft_11_T_2 = &io_diffFReg_31[63:61]; // @[Fpu.scala 34:56]
  wire [31:0] _FReg2_ft_11_T_4 = _FReg2_ft_11_T_2 ? FReg2_ft_11_prevUnrecoded : FReg2_ft_11_unrecoded[31:0]; // @[Fpu.scala 243:44]
  wire [63:0] XReg_zero = io_diffXReg_0; // @[diff.scala 116:18 119:13]
  wire [63:0] XReg_ra = io_diffXReg_1; // @[diff.scala 116:18 120:13]
  wire [63:0] XReg_sp = io_diffXReg_2; // @[diff.scala 116:18 121:13]
  wire [63:0] XReg_gp = io_diffXReg_3; // @[diff.scala 116:18 122:13]
  wire [63:0] XReg_tp = io_diffXReg_4; // @[diff.scala 116:18 123:13]
  wire [63:0] XReg_t_0 = io_diffXReg_5; // @[diff.scala 116:18 124:15]
  wire [63:0] XReg_t_1 = io_diffXReg_6; // @[diff.scala 116:18 125:15]
  wire [63:0] XReg_t_2 = io_diffXReg_7; // @[diff.scala 116:18 126:15]
  wire [63:0] XReg_t_3 = io_diffXReg_28; // @[diff.scala 116:18 147:15]
  wire [63:0] XReg_t_4 = io_diffXReg_29; // @[diff.scala 116:18 148:15]
  wire [63:0] XReg_t_5 = io_diffXReg_30; // @[diff.scala 116:18 149:15]
  wire [63:0] XReg_t_6 = io_diffXReg_31; // @[diff.scala 116:18 150:15]
  wire [63:0] XReg_s_0 = io_diffXReg_8; // @[diff.scala 116:18 127:15]
  wire [63:0] XReg_s_1 = io_diffXReg_9; // @[diff.scala 116:18 128:15]
  wire [63:0] XReg_s_2 = io_diffXReg_18; // @[diff.scala 116:18 137:15]
  wire [63:0] XReg_s_3 = io_diffXReg_19; // @[diff.scala 116:18 138:15]
  wire [63:0] XReg_s_4 = io_diffXReg_20; // @[diff.scala 116:18 139:15]
  wire [63:0] XReg_s_5 = io_diffXReg_21; // @[diff.scala 116:18 140:15]
  wire [63:0] XReg_s_6 = io_diffXReg_22; // @[diff.scala 116:18 141:15]
  wire [63:0] XReg_s_7 = io_diffXReg_23; // @[diff.scala 116:18 142:15]
  wire [63:0] XReg_s_8 = io_diffXReg_24; // @[diff.scala 116:18 143:15]
  wire [63:0] XReg_s_9 = io_diffXReg_25; // @[diff.scala 116:18 144:15]
  wire [63:0] XReg_s_10 = io_diffXReg_26; // @[diff.scala 116:18 145:15]
  wire [63:0] XReg_s_11 = io_diffXReg_27; // @[diff.scala 116:18 146:15]
  wire [63:0] XReg_a_0 = io_diffXReg_10; // @[diff.scala 116:18 129:15]
  wire [63:0] XReg_a_1 = io_diffXReg_11; // @[diff.scala 116:18 130:15]
  wire [63:0] XReg_a_2 = io_diffXReg_12; // @[diff.scala 116:18 131:15]
  wire [63:0] XReg_a_3 = io_diffXReg_13; // @[diff.scala 116:18 132:15]
  wire [63:0] XReg_a_4 = io_diffXReg_14; // @[diff.scala 116:18 133:15]
  wire [63:0] XReg_a_5 = io_diffXReg_15; // @[diff.scala 116:18 134:15]
  wire [63:0] XReg_a_6 = io_diffXReg_16; // @[diff.scala 116:18 135:15]
  wire [63:0] XReg_a_7 = io_diffXReg_17; // @[diff.scala 116:18 136:15]
  wire [63:0] FReg1_ft_0 = {_FReg1_ft_0_T_3,FReg1_ft_0_ie_rawIn__sign,FReg1_ft_0_ie_expOut,FReg1_ft_0_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_1 = {_FReg1_ft_1_T_3,FReg1_ft_1_ie_rawIn__sign,FReg1_ft_1_ie_expOut,FReg1_ft_1_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_2 = {_FReg1_ft_2_T_3,FReg1_ft_2_ie_rawIn__sign,FReg1_ft_2_ie_expOut,FReg1_ft_2_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_3 = {_FReg1_ft_3_T_3,FReg1_ft_3_ie_rawIn__sign,FReg1_ft_3_ie_expOut,FReg1_ft_3_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_4 = {_FReg1_ft_4_T_3,FReg1_ft_4_ie_rawIn__sign,FReg1_ft_4_ie_expOut,FReg1_ft_4_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_5 = {_FReg1_ft_5_T_3,FReg1_ft_5_ie_rawIn__sign,FReg1_ft_5_ie_expOut,FReg1_ft_5_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_6 = {_FReg1_ft_6_T_3,FReg1_ft_6_ie_rawIn__sign,FReg1_ft_6_ie_expOut,FReg1_ft_6_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_7 = {_FReg1_ft_7_T_3,FReg1_ft_7_ie_rawIn__sign,FReg1_ft_7_ie_expOut,FReg1_ft_7_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_8 = {_FReg1_ft_8_T_3,FReg1_ft_8_ie_rawIn__sign,FReg1_ft_8_ie_expOut,FReg1_ft_8_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_9 = {_FReg1_ft_9_T_3,FReg1_ft_9_ie_rawIn__sign,FReg1_ft_9_ie_expOut,FReg1_ft_9_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_10 = {_FReg1_ft_10_T_3,FReg1_ft_10_ie_rawIn__sign,FReg1_ft_10_ie_expOut,FReg1_ft_10_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_ft_11 = {_FReg1_ft_11_T_3,FReg1_ft_11_ie_rawIn__sign,FReg1_ft_11_ie_expOut,FReg1_ft_11_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_0 = {_FReg1_fs_0_T_3,FReg1_fs_0_ie_rawIn__sign,FReg1_fs_0_ie_expOut,FReg1_fs_0_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_1 = {_FReg1_fs_1_T_3,FReg1_fs_1_ie_rawIn__sign,FReg1_fs_1_ie_expOut,FReg1_fs_1_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_2 = {_FReg1_fs_2_T_3,FReg1_fs_2_ie_rawIn__sign,FReg1_fs_2_ie_expOut,FReg1_fs_2_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_3 = {_FReg1_fs_3_T_3,FReg1_fs_3_ie_rawIn__sign,FReg1_fs_3_ie_expOut,FReg1_fs_3_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_4 = {_FReg1_fs_4_T_3,FReg1_fs_4_ie_rawIn__sign,FReg1_fs_4_ie_expOut,FReg1_fs_4_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_5 = {_FReg1_fs_5_T_3,FReg1_fs_5_ie_rawIn__sign,FReg1_fs_5_ie_expOut,FReg1_fs_5_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_6 = {_FReg1_fs_6_T_3,FReg1_fs_6_ie_rawIn__sign,FReg1_fs_6_ie_expOut,FReg1_fs_6_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_7 = {_FReg1_fs_7_T_3,FReg1_fs_7_ie_rawIn__sign,FReg1_fs_7_ie_expOut,FReg1_fs_7_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_8 = {_FReg1_fs_8_T_3,FReg1_fs_8_ie_rawIn__sign,FReg1_fs_8_ie_expOut,FReg1_fs_8_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_9 = {_FReg1_fs_9_T_3,FReg1_fs_9_ie_rawIn__sign,FReg1_fs_9_ie_expOut,FReg1_fs_9_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_10 = {_FReg1_fs_10_T_3,FReg1_fs_10_ie_rawIn__sign,FReg1_fs_10_ie_expOut,FReg1_fs_10_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fs_11 = {_FReg1_fs_11_T_3,FReg1_fs_11_ie_rawIn__sign,FReg1_fs_11_ie_expOut,FReg1_fs_11_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fa_0 = {_FReg1_fa_0_T_3,FReg1_fa_0_ie_rawIn__sign,FReg1_fa_0_ie_expOut,FReg1_fa_0_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fa_1 = {_FReg1_fa_1_T_3,FReg1_fa_1_ie_rawIn__sign,FReg1_fa_1_ie_expOut,FReg1_fa_1_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fa_2 = {_FReg1_fa_2_T_3,FReg1_fa_2_ie_rawIn__sign,FReg1_fa_2_ie_expOut,FReg1_fa_2_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fa_3 = {_FReg1_fa_3_T_3,FReg1_fa_3_ie_rawIn__sign,FReg1_fa_3_ie_expOut,FReg1_fa_3_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fa_4 = {_FReg1_fa_4_T_3,FReg1_fa_4_ie_rawIn__sign,FReg1_fa_4_ie_expOut,FReg1_fa_4_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fa_5 = {_FReg1_fa_5_T_3,FReg1_fa_5_ie_rawIn__sign,FReg1_fa_5_ie_expOut,FReg1_fa_5_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fa_6 = {_FReg1_fa_6_T_3,FReg1_fa_6_ie_rawIn__sign,FReg1_fa_6_ie_expOut,FReg1_fa_6_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg1_fa_7 = {_FReg1_fa_7_T_3,FReg1_fa_7_ie_rawIn__sign,FReg1_fa_7_ie_expOut,FReg1_fa_7_ie_fractOut}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_0 = {FReg2_ft_0_unrecoded[63:32],_FReg2_ft_0_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_1 = {FReg2_ft_1_unrecoded[63:32],_FReg2_ft_1_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_2 = {FReg2_ft_2_unrecoded[63:32],_FReg2_ft_2_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_3 = {FReg2_ft_3_unrecoded[63:32],_FReg2_ft_3_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_4 = {FReg2_ft_4_unrecoded[63:32],_FReg2_ft_4_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_5 = {FReg2_ft_5_unrecoded[63:32],_FReg2_ft_5_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_6 = {FReg2_ft_6_unrecoded[63:32],_FReg2_ft_6_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_7 = {FReg2_ft_7_unrecoded[63:32],_FReg2_ft_7_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_8 = {FReg2_ft_8_unrecoded[63:32],_FReg2_ft_8_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_9 = {FReg2_ft_9_unrecoded[63:32],_FReg2_ft_9_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_10 = {FReg2_ft_10_unrecoded[63:32],_FReg2_ft_10_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_ft_11 = {FReg2_ft_11_unrecoded[63:32],_FReg2_ft_11_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_0 = {FReg2_fs_0_unrecoded[63:32],_FReg2_fs_0_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_1 = {FReg2_fs_1_unrecoded[63:32],_FReg2_fs_1_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_2 = {FReg2_fs_2_unrecoded[63:32],_FReg2_fs_2_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_3 = {FReg2_fs_3_unrecoded[63:32],_FReg2_fs_3_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_4 = {FReg2_fs_4_unrecoded[63:32],_FReg2_fs_4_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_5 = {FReg2_fs_5_unrecoded[63:32],_FReg2_fs_5_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_6 = {FReg2_fs_6_unrecoded[63:32],_FReg2_fs_6_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_7 = {FReg2_fs_7_unrecoded[63:32],_FReg2_fs_7_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_8 = {FReg2_fs_8_unrecoded[63:32],_FReg2_fs_8_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_9 = {FReg2_fs_9_unrecoded[63:32],_FReg2_fs_9_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_10 = {FReg2_fs_10_unrecoded[63:32],_FReg2_fs_10_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fs_11 = {FReg2_fs_11_unrecoded[63:32],_FReg2_fs_11_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fa_0 = {FReg2_fa_0_unrecoded[63:32],_FReg2_fa_0_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fa_1 = {FReg2_fa_1_unrecoded[63:32],_FReg2_fa_1_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fa_2 = {FReg2_fa_2_unrecoded[63:32],_FReg2_fa_2_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fa_3 = {FReg2_fa_3_unrecoded[63:32],_FReg2_fa_3_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fa_4 = {FReg2_fa_4_unrecoded[63:32],_FReg2_fa_4_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fa_5 = {FReg2_fa_5_unrecoded[63:32],_FReg2_fa_5_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fa_6 = {FReg2_fa_6_unrecoded[63:32],_FReg2_fa_6_T_4}; // @[Cat.scala 33:92]
  wire [63:0] FReg2_fa_7 = {FReg2_fa_7_unrecoded[63:32],_FReg2_fa_7_T_4}; // @[Cat.scala 33:92]
endmodule
module Rift2Core(
  input         clock,
  input         reset,
  output        auto_prefetch_clinet_out_a_valid,
  output [2:0]  auto_prefetch_clinet_out_a_bits_opcode,
  output [2:0]  auto_prefetch_clinet_out_a_bits_param,
  output [2:0]  auto_prefetch_clinet_out_a_bits_size,
  output        auto_prefetch_clinet_out_a_bits_source,
  output [31:0] auto_prefetch_clinet_out_a_bits_address,
  output [7:0]  auto_prefetch_clinet_out_a_bits_mask,
  output [63:0] auto_prefetch_clinet_out_a_bits_data,
  output        auto_prefetch_clinet_out_a_bits_corrupt,
  output        auto_prefetch_clinet_out_d_ready,
  input         auto_mmu_client_out_a_ready,
  output        auto_mmu_client_out_a_valid,
  output [2:0]  auto_mmu_client_out_a_bits_opcode,
  output [2:0]  auto_mmu_client_out_a_bits_param,
  output [2:0]  auto_mmu_client_out_a_bits_size,
  output        auto_mmu_client_out_a_bits_source,
  output [31:0] auto_mmu_client_out_a_bits_address,
  output [7:0]  auto_mmu_client_out_a_bits_mask,
  output [63:0] auto_mmu_client_out_a_bits_data,
  output        auto_mmu_client_out_a_bits_corrupt,
  output        auto_mmu_client_out_d_ready,
  input         auto_mmu_client_out_d_valid,
  input  [2:0]  auto_mmu_client_out_d_bits_opcode,
  input  [2:0]  auto_mmu_client_out_d_bits_size,
  input         auto_mmu_client_out_d_bits_source,
  input  [63:0] auto_mmu_client_out_d_bits_data,
  input         auto_periph_client_out_a_ready,
  output        auto_periph_client_out_a_valid,
  output [2:0]  auto_periph_client_out_a_bits_opcode,
  output [2:0]  auto_periph_client_out_a_bits_param,
  output [1:0]  auto_periph_client_out_a_bits_size,
  output        auto_periph_client_out_a_bits_source,
  output [31:0] auto_periph_client_out_a_bits_address,
  output [7:0]  auto_periph_client_out_a_bits_mask,
  output [63:0] auto_periph_client_out_a_bits_data,
  output        auto_periph_client_out_a_bits_corrupt,
  output        auto_periph_client_out_d_ready,
  input         auto_periph_client_out_d_valid,
  input  [2:0]  auto_periph_client_out_d_bits_opcode,
  input  [63:0] auto_periph_client_out_d_bits_data,
  input         auto_system_client_out_a_ready,
  output        auto_system_client_out_a_valid,
  output [2:0]  auto_system_client_out_a_bits_opcode,
  output [2:0]  auto_system_client_out_a_bits_param,
  output [1:0]  auto_system_client_out_a_bits_size,
  output        auto_system_client_out_a_bits_source,
  output [31:0] auto_system_client_out_a_bits_address,
  output [7:0]  auto_system_client_out_a_bits_mask,
  output [63:0] auto_system_client_out_a_bits_data,
  output        auto_system_client_out_a_bits_corrupt,
  output        auto_system_client_out_d_ready,
  input         auto_system_client_out_d_valid,
  input  [2:0]  auto_system_client_out_d_bits_opcode,
  input  [63:0] auto_system_client_out_d_bits_data,
  input         auto_dcache_client_out_a_ready,
  output        auto_dcache_client_out_a_valid,
  output [2:0]  auto_dcache_client_out_a_bits_opcode,
  output [2:0]  auto_dcache_client_out_a_bits_param,
  output [2:0]  auto_dcache_client_out_a_bits_size,
  output        auto_dcache_client_out_a_bits_source,
  output [31:0] auto_dcache_client_out_a_bits_address,
  output [7:0]  auto_dcache_client_out_a_bits_mask,
  output [63:0] auto_dcache_client_out_a_bits_data,
  output        auto_dcache_client_out_a_bits_corrupt,
  output        auto_dcache_client_out_b_ready,
  input         auto_dcache_client_out_b_valid,
  input  [31:0] auto_dcache_client_out_b_bits_address,
  input         auto_dcache_client_out_c_ready,
  output        auto_dcache_client_out_c_valid,
  output [2:0]  auto_dcache_client_out_c_bits_opcode,
  output [2:0]  auto_dcache_client_out_c_bits_param,
  output [2:0]  auto_dcache_client_out_c_bits_size,
  output        auto_dcache_client_out_c_bits_source,
  output [31:0] auto_dcache_client_out_c_bits_address,
  output [63:0] auto_dcache_client_out_c_bits_data,
  output        auto_dcache_client_out_c_bits_corrupt,
  output        auto_dcache_client_out_d_ready,
  input         auto_dcache_client_out_d_valid,
  input  [2:0]  auto_dcache_client_out_d_bits_opcode,
  input  [2:0]  auto_dcache_client_out_d_bits_size,
  input         auto_dcache_client_out_d_bits_source,
  input  [4:0]  auto_dcache_client_out_d_bits_sink,
  input  [63:0] auto_dcache_client_out_d_bits_data,
  input         auto_dcache_client_out_e_ready,
  output        auto_dcache_client_out_e_valid,
  output [4:0]  auto_dcache_client_out_e_bits_sink,
  input         auto_icache_client_out_a_ready,
  output        auto_icache_client_out_a_valid,
  output [2:0]  auto_icache_client_out_a_bits_opcode,
  output [2:0]  auto_icache_client_out_a_bits_param,
  output [2:0]  auto_icache_client_out_a_bits_size,
  output        auto_icache_client_out_a_bits_source,
  output [31:0] auto_icache_client_out_a_bits_address,
  output [7:0]  auto_icache_client_out_a_bits_mask,
  output [63:0] auto_icache_client_out_a_bits_data,
  output        auto_icache_client_out_a_bits_corrupt,
  output        auto_icache_client_out_d_ready,
  input         auto_icache_client_out_d_valid,
  input  [2:0]  auto_icache_client_out_d_bits_opcode,
  input  [2:0]  auto_icache_client_out_d_bits_size,
  input  [63:0] auto_icache_client_out_d_bits_data,
  output        io_dm_hartIsInReset,
  input         io_dm_hartResetReq,
  input         io_dm_hartHaltReq,
  input         io_rtc_clock,
  input         io_aclint_msi,
  input         io_aclint_mti,
  input         io_aclint_ssi,
  input         io_aclint_sti,
  input         io_plic_mei,
  input         io_plic_sei
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_91;
  reg [63:0] _RAND_104;
  reg [63:0] _RAND_106;
  reg [31:0] _RAND_112;
  reg [31:0] _RAND_115;
  reg [31:0] _RAND_118;
  reg [31:0] _RAND_119;
  reg [63:0] _RAND_169;
  reg [31:0] _RAND_947;
  reg [31:0] _RAND_948;
  reg [31:0] _RAND_949;
  reg [31:0] _RAND_950;
  reg [31:0] _RAND_951;
  reg [31:0] _RAND_952;
  reg [31:0] _RAND_953;
  reg [31:0] _RAND_954;
  reg [31:0] _RAND_955;
  reg [31:0] _RAND_956;
  reg [31:0] _RAND_957;
  reg [63:0] _RAND_958;
  reg [63:0] _RAND_959;
  reg [31:0] _RAND_961;
  reg [31:0] _RAND_962;
  reg [31:0] _RAND_963;
  reg [31:0] _RAND_964;
  reg [31:0] _RAND_965;
  reg [31:0] _RAND_966;
  reg [31:0] _RAND_967;
  reg [31:0] _RAND_968;
  reg [31:0] _RAND_969;
  reg [31:0] _RAND_970;
  reg [31:0] _RAND_971;
  reg [31:0] _RAND_972;
  reg [31:0] _RAND_973;
  reg [31:0] _RAND_974;
  reg [63:0] _RAND_975;
  reg [63:0] _RAND_976;
  reg [31:0] _RAND_978;
  reg [31:0] _RAND_979;
  reg [31:0] _RAND_980;
  reg [31:0] _RAND_981;
  reg [31:0] _RAND_982;
  reg [31:0] _RAND_983;
  reg [31:0] _RAND_984;
  reg [31:0] _RAND_985;
  reg [31:0] _RAND_986;
  reg [63:0] _RAND_987;
  reg [63:0] _RAND_988;
  reg [63:0] _RAND_989;
  reg [63:0] _RAND_990;
  reg [31:0] _RAND_992;
  reg [31:0] _RAND_993;
  reg [31:0] _RAND_994;
  reg [31:0] _RAND_995;
  reg [63:0] _RAND_996;
  reg [63:0] _RAND_997;
  reg [31:0] _RAND_999;
  reg [31:0] _RAND_1000;
  reg [31:0] _RAND_1001;
  reg [31:0] _RAND_1002;
  reg [31:0] _RAND_1003;
  reg [31:0] _RAND_1004;
  reg [31:0] _RAND_1005;
  reg [31:0] _RAND_1006;
  reg [31:0] _RAND_1007;
  reg [31:0] _RAND_1008;
  reg [31:0] _RAND_1009;
  reg [31:0] _RAND_1010;
  reg [31:0] _RAND_1011;
  reg [31:0] _RAND_1012;
  reg [31:0] _RAND_1013;
  reg [31:0] _RAND_1014;
  reg [31:0] _RAND_1015;
  reg [31:0] _RAND_1016;
  reg [31:0] _RAND_1017;
  reg [31:0] _RAND_1018;
  reg [31:0] _RAND_1019;
  reg [31:0] _RAND_1020;
  reg [31:0] _RAND_1021;
  reg [31:0] _RAND_1022;
  reg [31:0] _RAND_1023;
  reg [31:0] _RAND_1024;
  reg [31:0] _RAND_1025;
  reg [31:0] _RAND_1026;
  reg [31:0] _RAND_1027;
  reg [31:0] _RAND_1028;
  reg [31:0] _RAND_1029;
  reg [31:0] _RAND_1030;
  reg [31:0] _RAND_1031;
  reg [31:0] _RAND_1032;
  reg [31:0] _RAND_1033;
  reg [31:0] _RAND_1034;
  reg [31:0] _RAND_1035;
  reg [31:0] _RAND_1036;
  reg [31:0] _RAND_1037;
  reg [31:0] _RAND_1038;
  reg [31:0] _RAND_1039;
  reg [63:0] _RAND_1040;
  reg [63:0] _RAND_1041;
  reg [31:0] _RAND_1266;
  reg [63:0] _RAND_1267;
  reg [31:0] _RAND_1269;
  reg [63:0] _RAND_1270;
  reg [63:0] _RAND_1272;
  reg [31:0] _RAND_1273;
  reg [31:0] _RAND_1274;
  reg [31:0] _RAND_1275;
  reg [31:0] _RAND_1276;
  reg [63:0] _RAND_1277;
  reg [63:0] _RAND_1279;
  reg [63:0] _RAND_1280;
  reg [63:0] _RAND_1281;
  reg [31:0] _RAND_1282;
  reg [63:0] _RAND_1283;
  reg [31:0] _RAND_1468;
  reg [31:0] _RAND_1470;
  reg [127:0] _RAND_1471;
  reg [31:0] _RAND_1472;
  reg [31:0] _RAND_1473;
  reg [31:0] _RAND_1474;
  reg [31:0] _RAND_1475;
  reg [31:0] _RAND_1484;
  reg [31:0] _RAND_1485;
  reg [127:0] _RAND_1486;
  reg [31:0] _RAND_1487;
  reg [31:0] _RAND_1488;
  reg [31:0] _RAND_1489;
  reg [31:0] _RAND_1490;
  reg [31:0] _RAND_1491;
  reg [31:0] _RAND_1492;
  reg [31:0] _RAND_1493;
  reg [31:0] _RAND_1494;
  reg [31:0] _RAND_1495;
  reg [31:0] _RAND_1496;
  reg [31:0] _RAND_1497;
  reg [31:0] _RAND_1498;
  reg [31:0] _RAND_1499;
  reg [31:0] _RAND_1500;
  reg [31:0] _RAND_1501;
  reg [31:0] _RAND_1502;
  reg [31:0] _RAND_1503;
  reg [31:0] _RAND_1504;
  reg [31:0] _RAND_1505;
  reg [31:0] _RAND_1506;
  reg [31:0] _RAND_1507;
  reg [31:0] _RAND_1508;
  reg [31:0] _RAND_1509;
  reg [31:0] _RAND_1510;
  reg [31:0] _RAND_1511;
  reg [31:0] _RAND_1512;
  reg [31:0] _RAND_1513;
  reg [31:0] _RAND_1514;
  reg [31:0] _RAND_1515;
  reg [31:0] _RAND_1516;
  reg [31:0] _RAND_1517;
  reg [31:0] _RAND_1518;
  reg [31:0] _RAND_1519;
  reg [31:0] _RAND_1520;
  reg [31:0] _RAND_1521;
  reg [31:0] _RAND_1522;
  reg [31:0] _RAND_1523;
  reg [31:0] _RAND_1524;
  reg [31:0] _RAND_1525;
  reg [31:0] _RAND_1526;
  reg [31:0] _RAND_1527;
  reg [31:0] _RAND_1528;
  reg [31:0] _RAND_1532;
  reg [31:0] _RAND_1533;
  reg [63:0] _RAND_1534;
  reg [31:0] _RAND_1535;
  reg [31:0] _RAND_1536;
  reg [31:0] _RAND_1537;
  reg [31:0] _RAND_1541;
  reg [31:0] _RAND_1542;
  reg [127:0] _RAND_1543;
  reg [31:0] _RAND_1544;
  reg [31:0] _RAND_1545;
  reg [31:0] _RAND_1546;
  reg [31:0] _RAND_1547;
  reg [31:0] _RAND_1548;
  reg [31:0] _RAND_1549;
  reg [31:0] _RAND_1550;
  reg [31:0] _RAND_1551;
  reg [31:0] _RAND_1552;
  reg [31:0] _RAND_1553;
  reg [31:0] _RAND_1554;
  reg [31:0] _RAND_1555;
  reg [31:0] _RAND_1556;
  reg [31:0] _RAND_1557;
  reg [31:0] _RAND_1558;
  reg [31:0] _RAND_1559;
  reg [31:0] _RAND_1560;
  reg [31:0] _RAND_1561;
  reg [31:0] _RAND_1562;
  reg [31:0] _RAND_1563;
  reg [31:0] _RAND_1564;
  reg [31:0] _RAND_1565;
  reg [31:0] _RAND_1566;
  reg [31:0] _RAND_1567;
  reg [31:0] _RAND_1568;
  reg [31:0] _RAND_1569;
  reg [31:0] _RAND_1570;
  reg [31:0] _RAND_1571;
  reg [31:0] _RAND_1572;
  reg [31:0] _RAND_1573;
  reg [31:0] _RAND_1574;
  reg [31:0] _RAND_1575;
  reg [31:0] _RAND_1576;
  reg [31:0] _RAND_1577;
  reg [31:0] _RAND_1578;
  reg [31:0] _RAND_1579;
  reg [31:0] _RAND_1580;
  reg [31:0] _RAND_1581;
  reg [31:0] _RAND_1582;
  reg [31:0] _RAND_1583;
  reg [31:0] _RAND_1584;
  reg [31:0] _RAND_1585;
  reg [31:0] _RAND_1587;
  reg [31:0] _RAND_1590;
  reg [31:0] _RAND_1593;
  reg [31:0] _RAND_1596;
  reg [31:0] _RAND_1599;
  reg [31:0] _RAND_1602;
  reg [31:0] _RAND_1605;
  reg [31:0] _RAND_1608;
  reg [31:0] _RAND_1611;
  reg [31:0] _RAND_1614;
  reg [31:0] _RAND_1617;
  reg [31:0] _RAND_1620;
  reg [31:0] _RAND_1623;
  reg [31:0] _RAND_1626;
  reg [31:0] _RAND_1629;
  reg [31:0] _RAND_1632;
  reg [31:0] _RAND_1635;
  reg [31:0] _RAND_1791;
  reg [63:0] _RAND_1792;
  reg [31:0] _RAND_1795;
  reg [63:0] _RAND_1796;
  reg [31:0] _RAND_1798;
  reg [63:0] _RAND_1799;
  reg [31:0] _RAND_1808;
  reg [63:0] _RAND_1809;
  reg [31:0] _RAND_1811;
  reg [63:0] _RAND_1812;
  reg [31:0] _RAND_1813;
  reg [31:0] _RAND_1814;
  reg [31:0] _RAND_1815;
  reg [31:0] _RAND_1817;
  reg [63:0] _RAND_1818;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [63:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [63:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [63:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [63:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [63:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
  reg [31:0] _RAND_94;
  reg [63:0] _RAND_95;
  reg [31:0] _RAND_96;
  reg [31:0] _RAND_97;
  reg [31:0] _RAND_98;
  reg [31:0] _RAND_99;
  reg [31:0] _RAND_100;
  reg [63:0] _RAND_101;
  reg [31:0] _RAND_102;
  reg [31:0] _RAND_103;
  reg [31:0] _RAND_105;
  reg [31:0] _RAND_107;
  reg [31:0] _RAND_108;
  reg [31:0] _RAND_109;
  reg [31:0] _RAND_110;
  reg [31:0] _RAND_111;
  reg [31:0] _RAND_113;
  reg [31:0] _RAND_114;
  reg [31:0] _RAND_116;
  reg [31:0] _RAND_117;
  reg [31:0] _RAND_120;
  reg [31:0] _RAND_121;
  reg [31:0] _RAND_122;
  reg [31:0] _RAND_123;
  reg [63:0] _RAND_124;
  reg [63:0] _RAND_125;
  reg [31:0] _RAND_126;
  reg [31:0] _RAND_127;
  reg [31:0] _RAND_128;
  reg [31:0] _RAND_129;
  reg [31:0] _RAND_130;
  reg [31:0] _RAND_131;
  reg [31:0] _RAND_132;
  reg [31:0] _RAND_133;
  reg [31:0] _RAND_134;
  reg [31:0] _RAND_135;
  reg [31:0] _RAND_136;
  reg [31:0] _RAND_137;
  reg [31:0] _RAND_138;
  reg [31:0] _RAND_139;
  reg [31:0] _RAND_140;
  reg [31:0] _RAND_141;
  reg [31:0] _RAND_142;
  reg [31:0] _RAND_143;
  reg [63:0] _RAND_144;
  reg [31:0] _RAND_145;
  reg [63:0] _RAND_146;
  reg [31:0] _RAND_147;
  reg [31:0] _RAND_148;
  reg [63:0] _RAND_149;
  reg [31:0] _RAND_150;
  reg [63:0] _RAND_151;
  reg [31:0] _RAND_152;
  reg [31:0] _RAND_153;
  reg [63:0] _RAND_154;
  reg [31:0] _RAND_155;
  reg [63:0] _RAND_156;
  reg [31:0] _RAND_157;
  reg [31:0] _RAND_158;
  reg [63:0] _RAND_159;
  reg [31:0] _RAND_160;
  reg [63:0] _RAND_161;
  reg [31:0] _RAND_162;
  reg [31:0] _RAND_163;
  reg [31:0] _RAND_164;
  reg [31:0] _RAND_165;
  reg [31:0] _RAND_166;
  reg [31:0] _RAND_167;
  reg [31:0] _RAND_168;
  reg [31:0] _RAND_170;
  reg [31:0] _RAND_171;
  reg [63:0] _RAND_172;
  reg [31:0] _RAND_173;
  reg [31:0] _RAND_174;
  reg [31:0] _RAND_175;
  reg [31:0] _RAND_176;
  reg [31:0] _RAND_177;
  reg [31:0] _RAND_178;
  reg [31:0] _RAND_179;
  reg [31:0] _RAND_180;
  reg [31:0] _RAND_181;
  reg [31:0] _RAND_182;
  reg [31:0] _RAND_183;
  reg [31:0] _RAND_184;
  reg [31:0] _RAND_185;
  reg [31:0] _RAND_186;
  reg [31:0] _RAND_187;
  reg [31:0] _RAND_188;
  reg [31:0] _RAND_189;
  reg [31:0] _RAND_190;
  reg [31:0] _RAND_191;
  reg [31:0] _RAND_192;
  reg [31:0] _RAND_193;
  reg [31:0] _RAND_194;
  reg [31:0] _RAND_195;
  reg [31:0] _RAND_196;
  reg [31:0] _RAND_197;
  reg [31:0] _RAND_198;
  reg [31:0] _RAND_199;
  reg [31:0] _RAND_200;
  reg [31:0] _RAND_201;
  reg [31:0] _RAND_202;
  reg [31:0] _RAND_203;
  reg [31:0] _RAND_204;
  reg [31:0] _RAND_205;
  reg [31:0] _RAND_206;
  reg [31:0] _RAND_207;
  reg [31:0] _RAND_208;
  reg [31:0] _RAND_209;
  reg [31:0] _RAND_210;
  reg [31:0] _RAND_211;
  reg [31:0] _RAND_212;
  reg [31:0] _RAND_213;
  reg [31:0] _RAND_214;
  reg [31:0] _RAND_215;
  reg [31:0] _RAND_216;
  reg [31:0] _RAND_217;
  reg [31:0] _RAND_218;
  reg [31:0] _RAND_219;
  reg [31:0] _RAND_220;
  reg [31:0] _RAND_221;
  reg [31:0] _RAND_222;
  reg [31:0] _RAND_223;
  reg [31:0] _RAND_224;
  reg [31:0] _RAND_225;
  reg [31:0] _RAND_226;
  reg [31:0] _RAND_227;
  reg [31:0] _RAND_228;
  reg [31:0] _RAND_229;
  reg [31:0] _RAND_230;
  reg [31:0] _RAND_231;
  reg [31:0] _RAND_232;
  reg [31:0] _RAND_233;
  reg [31:0] _RAND_234;
  reg [31:0] _RAND_235;
  reg [31:0] _RAND_236;
  reg [31:0] _RAND_237;
  reg [31:0] _RAND_238;
  reg [31:0] _RAND_239;
  reg [31:0] _RAND_240;
  reg [31:0] _RAND_241;
  reg [31:0] _RAND_242;
  reg [31:0] _RAND_243;
  reg [31:0] _RAND_244;
  reg [31:0] _RAND_245;
  reg [31:0] _RAND_246;
  reg [31:0] _RAND_247;
  reg [31:0] _RAND_248;
  reg [31:0] _RAND_249;
  reg [31:0] _RAND_250;
  reg [31:0] _RAND_251;
  reg [31:0] _RAND_252;
  reg [31:0] _RAND_253;
  reg [31:0] _RAND_254;
  reg [31:0] _RAND_255;
  reg [31:0] _RAND_256;
  reg [31:0] _RAND_257;
  reg [31:0] _RAND_258;
  reg [31:0] _RAND_259;
  reg [31:0] _RAND_260;
  reg [31:0] _RAND_261;
  reg [31:0] _RAND_262;
  reg [31:0] _RAND_263;
  reg [31:0] _RAND_264;
  reg [31:0] _RAND_265;
  reg [31:0] _RAND_266;
  reg [31:0] _RAND_267;
  reg [31:0] _RAND_268;
  reg [31:0] _RAND_269;
  reg [31:0] _RAND_270;
  reg [31:0] _RAND_271;
  reg [31:0] _RAND_272;
  reg [31:0] _RAND_273;
  reg [31:0] _RAND_274;
  reg [31:0] _RAND_275;
  reg [31:0] _RAND_276;
  reg [31:0] _RAND_277;
  reg [31:0] _RAND_278;
  reg [31:0] _RAND_279;
  reg [31:0] _RAND_280;
  reg [31:0] _RAND_281;
  reg [31:0] _RAND_282;
  reg [31:0] _RAND_283;
  reg [31:0] _RAND_284;
  reg [31:0] _RAND_285;
  reg [31:0] _RAND_286;
  reg [31:0] _RAND_287;
  reg [31:0] _RAND_288;
  reg [31:0] _RAND_289;
  reg [31:0] _RAND_290;
  reg [31:0] _RAND_291;
  reg [31:0] _RAND_292;
  reg [31:0] _RAND_293;
  reg [31:0] _RAND_294;
  reg [31:0] _RAND_295;
  reg [31:0] _RAND_296;
  reg [31:0] _RAND_297;
  reg [31:0] _RAND_298;
  reg [31:0] _RAND_299;
  reg [31:0] _RAND_300;
  reg [31:0] _RAND_301;
  reg [31:0] _RAND_302;
  reg [31:0] _RAND_303;
  reg [31:0] _RAND_304;
  reg [31:0] _RAND_305;
  reg [31:0] _RAND_306;
  reg [31:0] _RAND_307;
  reg [31:0] _RAND_308;
  reg [31:0] _RAND_309;
  reg [31:0] _RAND_310;
  reg [31:0] _RAND_311;
  reg [31:0] _RAND_312;
  reg [31:0] _RAND_313;
  reg [31:0] _RAND_314;
  reg [31:0] _RAND_315;
  reg [31:0] _RAND_316;
  reg [31:0] _RAND_317;
  reg [31:0] _RAND_318;
  reg [31:0] _RAND_319;
  reg [31:0] _RAND_320;
  reg [31:0] _RAND_321;
  reg [31:0] _RAND_322;
  reg [31:0] _RAND_323;
  reg [31:0] _RAND_324;
  reg [31:0] _RAND_325;
  reg [31:0] _RAND_326;
  reg [31:0] _RAND_327;
  reg [31:0] _RAND_328;
  reg [31:0] _RAND_329;
  reg [31:0] _RAND_330;
  reg [31:0] _RAND_331;
  reg [31:0] _RAND_332;
  reg [31:0] _RAND_333;
  reg [31:0] _RAND_334;
  reg [31:0] _RAND_335;
  reg [31:0] _RAND_336;
  reg [31:0] _RAND_337;
  reg [31:0] _RAND_338;
  reg [31:0] _RAND_339;
  reg [31:0] _RAND_340;
  reg [31:0] _RAND_341;
  reg [31:0] _RAND_342;
  reg [31:0] _RAND_343;
  reg [31:0] _RAND_344;
  reg [31:0] _RAND_345;
  reg [31:0] _RAND_346;
  reg [31:0] _RAND_347;
  reg [31:0] _RAND_348;
  reg [31:0] _RAND_349;
  reg [31:0] _RAND_350;
  reg [31:0] _RAND_351;
  reg [31:0] _RAND_352;
  reg [31:0] _RAND_353;
  reg [31:0] _RAND_354;
  reg [31:0] _RAND_355;
  reg [31:0] _RAND_356;
  reg [31:0] _RAND_357;
  reg [31:0] _RAND_358;
  reg [63:0] _RAND_359;
  reg [63:0] _RAND_360;
  reg [31:0] _RAND_361;
  reg [31:0] _RAND_362;
  reg [31:0] _RAND_363;
  reg [31:0] _RAND_364;
  reg [31:0] _RAND_365;
  reg [31:0] _RAND_366;
  reg [31:0] _RAND_367;
  reg [31:0] _RAND_368;
  reg [31:0] _RAND_369;
  reg [31:0] _RAND_370;
  reg [31:0] _RAND_371;
  reg [31:0] _RAND_372;
  reg [31:0] _RAND_373;
  reg [31:0] _RAND_374;
  reg [31:0] _RAND_375;
  reg [31:0] _RAND_376;
  reg [31:0] _RAND_377;
  reg [31:0] _RAND_378;
  reg [31:0] _RAND_379;
  reg [31:0] _RAND_380;
  reg [31:0] _RAND_381;
  reg [31:0] _RAND_382;
  reg [31:0] _RAND_383;
  reg [31:0] _RAND_384;
  reg [31:0] _RAND_385;
  reg [31:0] _RAND_386;
  reg [31:0] _RAND_387;
  reg [31:0] _RAND_388;
  reg [31:0] _RAND_389;
  reg [31:0] _RAND_390;
  reg [31:0] _RAND_391;
  reg [31:0] _RAND_392;
  reg [31:0] _RAND_393;
  reg [31:0] _RAND_394;
  reg [31:0] _RAND_395;
  reg [31:0] _RAND_396;
  reg [31:0] _RAND_397;
  reg [31:0] _RAND_398;
  reg [31:0] _RAND_399;
  reg [31:0] _RAND_400;
  reg [31:0] _RAND_401;
  reg [31:0] _RAND_402;
  reg [31:0] _RAND_403;
  reg [31:0] _RAND_404;
  reg [31:0] _RAND_405;
  reg [31:0] _RAND_406;
  reg [31:0] _RAND_407;
  reg [31:0] _RAND_408;
  reg [31:0] _RAND_409;
  reg [31:0] _RAND_410;
  reg [31:0] _RAND_411;
  reg [31:0] _RAND_412;
  reg [31:0] _RAND_413;
  reg [31:0] _RAND_414;
  reg [31:0] _RAND_415;
  reg [31:0] _RAND_416;
  reg [31:0] _RAND_417;
  reg [31:0] _RAND_418;
  reg [31:0] _RAND_419;
  reg [31:0] _RAND_420;
  reg [31:0] _RAND_421;
  reg [31:0] _RAND_422;
  reg [31:0] _RAND_423;
  reg [31:0] _RAND_424;
  reg [31:0] _RAND_425;
  reg [31:0] _RAND_426;
  reg [31:0] _RAND_427;
  reg [31:0] _RAND_428;
  reg [31:0] _RAND_429;
  reg [31:0] _RAND_430;
  reg [31:0] _RAND_431;
  reg [31:0] _RAND_432;
  reg [31:0] _RAND_433;
  reg [31:0] _RAND_434;
  reg [31:0] _RAND_435;
  reg [31:0] _RAND_436;
  reg [31:0] _RAND_437;
  reg [31:0] _RAND_438;
  reg [31:0] _RAND_439;
  reg [31:0] _RAND_440;
  reg [31:0] _RAND_441;
  reg [31:0] _RAND_442;
  reg [31:0] _RAND_443;
  reg [31:0] _RAND_444;
  reg [31:0] _RAND_445;
  reg [31:0] _RAND_446;
  reg [31:0] _RAND_447;
  reg [31:0] _RAND_448;
  reg [31:0] _RAND_449;
  reg [31:0] _RAND_450;
  reg [31:0] _RAND_451;
  reg [31:0] _RAND_452;
  reg [31:0] _RAND_453;
  reg [31:0] _RAND_454;
  reg [31:0] _RAND_455;
  reg [31:0] _RAND_456;
  reg [31:0] _RAND_457;
  reg [31:0] _RAND_458;
  reg [31:0] _RAND_459;
  reg [31:0] _RAND_460;
  reg [31:0] _RAND_461;
  reg [31:0] _RAND_462;
  reg [31:0] _RAND_463;
  reg [31:0] _RAND_464;
  reg [31:0] _RAND_465;
  reg [31:0] _RAND_466;
  reg [31:0] _RAND_467;
  reg [31:0] _RAND_468;
  reg [31:0] _RAND_469;
  reg [31:0] _RAND_470;
  reg [31:0] _RAND_471;
  reg [31:0] _RAND_472;
  reg [31:0] _RAND_473;
  reg [31:0] _RAND_474;
  reg [31:0] _RAND_475;
  reg [31:0] _RAND_476;
  reg [31:0] _RAND_477;
  reg [31:0] _RAND_478;
  reg [31:0] _RAND_479;
  reg [31:0] _RAND_480;
  reg [31:0] _RAND_481;
  reg [31:0] _RAND_482;
  reg [31:0] _RAND_483;
  reg [31:0] _RAND_484;
  reg [31:0] _RAND_485;
  reg [31:0] _RAND_486;
  reg [31:0] _RAND_487;
  reg [31:0] _RAND_488;
  reg [31:0] _RAND_489;
  reg [31:0] _RAND_490;
  reg [31:0] _RAND_491;
  reg [31:0] _RAND_492;
  reg [31:0] _RAND_493;
  reg [31:0] _RAND_494;
  reg [31:0] _RAND_495;
  reg [31:0] _RAND_496;
  reg [31:0] _RAND_497;
  reg [31:0] _RAND_498;
  reg [31:0] _RAND_499;
  reg [31:0] _RAND_500;
  reg [31:0] _RAND_501;
  reg [31:0] _RAND_502;
  reg [31:0] _RAND_503;
  reg [31:0] _RAND_504;
  reg [31:0] _RAND_505;
  reg [31:0] _RAND_506;
  reg [31:0] _RAND_507;
  reg [31:0] _RAND_508;
  reg [31:0] _RAND_509;
  reg [31:0] _RAND_510;
  reg [31:0] _RAND_511;
  reg [31:0] _RAND_512;
  reg [31:0] _RAND_513;
  reg [31:0] _RAND_514;
  reg [31:0] _RAND_515;
  reg [31:0] _RAND_516;
  reg [31:0] _RAND_517;
  reg [31:0] _RAND_518;
  reg [31:0] _RAND_519;
  reg [31:0] _RAND_520;
  reg [31:0] _RAND_521;
  reg [31:0] _RAND_522;
  reg [31:0] _RAND_523;
  reg [31:0] _RAND_524;
  reg [31:0] _RAND_525;
  reg [31:0] _RAND_526;
  reg [31:0] _RAND_527;
  reg [31:0] _RAND_528;
  reg [31:0] _RAND_529;
  reg [31:0] _RAND_530;
  reg [31:0] _RAND_531;
  reg [31:0] _RAND_532;
  reg [31:0] _RAND_533;
  reg [31:0] _RAND_534;
  reg [31:0] _RAND_535;
  reg [31:0] _RAND_536;
  reg [31:0] _RAND_537;
  reg [31:0] _RAND_538;
  reg [31:0] _RAND_539;
  reg [31:0] _RAND_540;
  reg [31:0] _RAND_541;
  reg [31:0] _RAND_542;
  reg [31:0] _RAND_543;
  reg [31:0] _RAND_544;
  reg [31:0] _RAND_545;
  reg [31:0] _RAND_546;
  reg [31:0] _RAND_547;
  reg [31:0] _RAND_548;
  reg [31:0] _RAND_549;
  reg [63:0] _RAND_550;
  reg [63:0] _RAND_551;
  reg [31:0] _RAND_552;
  reg [31:0] _RAND_553;
  reg [31:0] _RAND_554;
  reg [31:0] _RAND_555;
  reg [31:0] _RAND_556;
  reg [31:0] _RAND_557;
  reg [31:0] _RAND_558;
  reg [63:0] _RAND_559;
  reg [31:0] _RAND_560;
  reg [31:0] _RAND_561;
  reg [31:0] _RAND_562;
  reg [63:0] _RAND_563;
  reg [31:0] _RAND_564;
  reg [31:0] _RAND_565;
  reg [31:0] _RAND_566;
  reg [31:0] _RAND_567;
  reg [31:0] _RAND_568;
  reg [31:0] _RAND_569;
  reg [31:0] _RAND_570;
  reg [63:0] _RAND_571;
  reg [63:0] _RAND_572;
  reg [63:0] _RAND_573;
  reg [31:0] _RAND_574;
  reg [63:0] _RAND_575;
  reg [63:0] _RAND_576;
  reg [63:0] _RAND_577;
  reg [31:0] _RAND_578;
  reg [31:0] _RAND_579;
  reg [31:0] _RAND_580;
  reg [31:0] _RAND_581;
  reg [31:0] _RAND_582;
  reg [31:0] _RAND_583;
  reg [31:0] _RAND_584;
  reg [31:0] _RAND_585;
  reg [31:0] _RAND_586;
  reg [31:0] _RAND_587;
  reg [31:0] _RAND_588;
  reg [31:0] _RAND_589;
  reg [31:0] _RAND_590;
  reg [31:0] _RAND_591;
  reg [31:0] _RAND_592;
  reg [31:0] _RAND_593;
  reg [31:0] _RAND_594;
  reg [31:0] _RAND_595;
  reg [31:0] _RAND_596;
  reg [31:0] _RAND_597;
  reg [31:0] _RAND_598;
  reg [31:0] _RAND_599;
  reg [31:0] _RAND_600;
  reg [31:0] _RAND_601;
  reg [31:0] _RAND_602;
  reg [31:0] _RAND_603;
  reg [31:0] _RAND_604;
  reg [31:0] _RAND_605;
  reg [31:0] _RAND_606;
  reg [31:0] _RAND_607;
  reg [31:0] _RAND_608;
  reg [31:0] _RAND_609;
  reg [31:0] _RAND_610;
  reg [31:0] _RAND_611;
  reg [31:0] _RAND_612;
  reg [31:0] _RAND_613;
  reg [31:0] _RAND_614;
  reg [31:0] _RAND_615;
  reg [31:0] _RAND_616;
  reg [31:0] _RAND_617;
  reg [31:0] _RAND_618;
  reg [31:0] _RAND_619;
  reg [31:0] _RAND_620;
  reg [31:0] _RAND_621;
  reg [31:0] _RAND_622;
  reg [31:0] _RAND_623;
  reg [31:0] _RAND_624;
  reg [31:0] _RAND_625;
  reg [31:0] _RAND_626;
  reg [31:0] _RAND_627;
  reg [31:0] _RAND_628;
  reg [31:0] _RAND_629;
  reg [31:0] _RAND_630;
  reg [31:0] _RAND_631;
  reg [31:0] _RAND_632;
  reg [31:0] _RAND_633;
  reg [31:0] _RAND_634;
  reg [31:0] _RAND_635;
  reg [31:0] _RAND_636;
  reg [31:0] _RAND_637;
  reg [31:0] _RAND_638;
  reg [31:0] _RAND_639;
  reg [31:0] _RAND_640;
  reg [31:0] _RAND_641;
  reg [31:0] _RAND_642;
  reg [31:0] _RAND_643;
  reg [31:0] _RAND_644;
  reg [31:0] _RAND_645;
  reg [31:0] _RAND_646;
  reg [31:0] _RAND_647;
  reg [31:0] _RAND_648;
  reg [31:0] _RAND_649;
  reg [31:0] _RAND_650;
  reg [31:0] _RAND_651;
  reg [31:0] _RAND_652;
  reg [31:0] _RAND_653;
  reg [31:0] _RAND_654;
  reg [31:0] _RAND_655;
  reg [31:0] _RAND_656;
  reg [31:0] _RAND_657;
  reg [31:0] _RAND_658;
  reg [31:0] _RAND_659;
  reg [31:0] _RAND_660;
  reg [31:0] _RAND_661;
  reg [31:0] _RAND_662;
  reg [31:0] _RAND_663;
  reg [31:0] _RAND_664;
  reg [31:0] _RAND_665;
  reg [31:0] _RAND_666;
  reg [31:0] _RAND_667;
  reg [31:0] _RAND_668;
  reg [31:0] _RAND_669;
  reg [31:0] _RAND_670;
  reg [31:0] _RAND_671;
  reg [31:0] _RAND_672;
  reg [31:0] _RAND_673;
  reg [31:0] _RAND_674;
  reg [31:0] _RAND_675;
  reg [31:0] _RAND_676;
  reg [31:0] _RAND_677;
  reg [31:0] _RAND_678;
  reg [31:0] _RAND_679;
  reg [31:0] _RAND_680;
  reg [31:0] _RAND_681;
  reg [31:0] _RAND_682;
  reg [31:0] _RAND_683;
  reg [31:0] _RAND_684;
  reg [31:0] _RAND_685;
  reg [31:0] _RAND_686;
  reg [31:0] _RAND_687;
  reg [31:0] _RAND_688;
  reg [31:0] _RAND_689;
  reg [31:0] _RAND_690;
  reg [31:0] _RAND_691;
  reg [31:0] _RAND_692;
  reg [31:0] _RAND_693;
  reg [31:0] _RAND_694;
  reg [31:0] _RAND_695;
  reg [31:0] _RAND_696;
  reg [31:0] _RAND_697;
  reg [31:0] _RAND_698;
  reg [31:0] _RAND_699;
  reg [31:0] _RAND_700;
  reg [31:0] _RAND_701;
  reg [31:0] _RAND_702;
  reg [31:0] _RAND_703;
  reg [31:0] _RAND_704;
  reg [31:0] _RAND_705;
  reg [31:0] _RAND_706;
  reg [31:0] _RAND_707;
  reg [31:0] _RAND_708;
  reg [31:0] _RAND_709;
  reg [31:0] _RAND_710;
  reg [31:0] _RAND_711;
  reg [31:0] _RAND_712;
  reg [31:0] _RAND_713;
  reg [31:0] _RAND_714;
  reg [31:0] _RAND_715;
  reg [31:0] _RAND_716;
  reg [31:0] _RAND_717;
  reg [31:0] _RAND_718;
  reg [31:0] _RAND_719;
  reg [31:0] _RAND_720;
  reg [31:0] _RAND_721;
  reg [31:0] _RAND_722;
  reg [31:0] _RAND_723;
  reg [31:0] _RAND_724;
  reg [31:0] _RAND_725;
  reg [31:0] _RAND_726;
  reg [31:0] _RAND_727;
  reg [31:0] _RAND_728;
  reg [31:0] _RAND_729;
  reg [63:0] _RAND_730;
  reg [63:0] _RAND_731;
  reg [31:0] _RAND_732;
  reg [31:0] _RAND_733;
  reg [31:0] _RAND_734;
  reg [31:0] _RAND_735;
  reg [31:0] _RAND_736;
  reg [31:0] _RAND_737;
  reg [31:0] _RAND_738;
  reg [31:0] _RAND_739;
  reg [31:0] _RAND_740;
  reg [31:0] _RAND_741;
  reg [31:0] _RAND_742;
  reg [31:0] _RAND_743;
  reg [31:0] _RAND_744;
  reg [31:0] _RAND_745;
  reg [31:0] _RAND_746;
  reg [31:0] _RAND_747;
  reg [31:0] _RAND_748;
  reg [31:0] _RAND_749;
  reg [31:0] _RAND_750;
  reg [31:0] _RAND_751;
  reg [31:0] _RAND_752;
  reg [31:0] _RAND_753;
  reg [31:0] _RAND_754;
  reg [31:0] _RAND_755;
  reg [31:0] _RAND_756;
  reg [31:0] _RAND_757;
  reg [31:0] _RAND_758;
  reg [31:0] _RAND_759;
  reg [31:0] _RAND_760;
  reg [31:0] _RAND_761;
  reg [31:0] _RAND_762;
  reg [31:0] _RAND_763;
  reg [31:0] _RAND_764;
  reg [31:0] _RAND_765;
  reg [31:0] _RAND_766;
  reg [31:0] _RAND_767;
  reg [31:0] _RAND_768;
  reg [31:0] _RAND_769;
  reg [31:0] _RAND_770;
  reg [31:0] _RAND_771;
  reg [31:0] _RAND_772;
  reg [31:0] _RAND_773;
  reg [31:0] _RAND_774;
  reg [31:0] _RAND_775;
  reg [31:0] _RAND_776;
  reg [31:0] _RAND_777;
  reg [31:0] _RAND_778;
  reg [31:0] _RAND_779;
  reg [31:0] _RAND_780;
  reg [31:0] _RAND_781;
  reg [31:0] _RAND_782;
  reg [31:0] _RAND_783;
  reg [31:0] _RAND_784;
  reg [31:0] _RAND_785;
  reg [31:0] _RAND_786;
  reg [31:0] _RAND_787;
  reg [31:0] _RAND_788;
  reg [31:0] _RAND_789;
  reg [31:0] _RAND_790;
  reg [31:0] _RAND_791;
  reg [31:0] _RAND_792;
  reg [31:0] _RAND_793;
  reg [31:0] _RAND_794;
  reg [31:0] _RAND_795;
  reg [31:0] _RAND_796;
  reg [31:0] _RAND_797;
  reg [31:0] _RAND_798;
  reg [31:0] _RAND_799;
  reg [31:0] _RAND_800;
  reg [31:0] _RAND_801;
  reg [31:0] _RAND_802;
  reg [31:0] _RAND_803;
  reg [31:0] _RAND_804;
  reg [31:0] _RAND_805;
  reg [31:0] _RAND_806;
  reg [31:0] _RAND_807;
  reg [31:0] _RAND_808;
  reg [31:0] _RAND_809;
  reg [31:0] _RAND_810;
  reg [31:0] _RAND_811;
  reg [31:0] _RAND_812;
  reg [31:0] _RAND_813;
  reg [31:0] _RAND_814;
  reg [31:0] _RAND_815;
  reg [31:0] _RAND_816;
  reg [31:0] _RAND_817;
  reg [31:0] _RAND_818;
  reg [31:0] _RAND_819;
  reg [31:0] _RAND_820;
  reg [31:0] _RAND_821;
  reg [31:0] _RAND_822;
  reg [31:0] _RAND_823;
  reg [31:0] _RAND_824;
  reg [31:0] _RAND_825;
  reg [31:0] _RAND_826;
  reg [31:0] _RAND_827;
  reg [31:0] _RAND_828;
  reg [31:0] _RAND_829;
  reg [31:0] _RAND_830;
  reg [31:0] _RAND_831;
  reg [31:0] _RAND_832;
  reg [31:0] _RAND_833;
  reg [31:0] _RAND_834;
  reg [31:0] _RAND_835;
  reg [31:0] _RAND_836;
  reg [31:0] _RAND_837;
  reg [31:0] _RAND_838;
  reg [31:0] _RAND_839;
  reg [31:0] _RAND_840;
  reg [31:0] _RAND_841;
  reg [31:0] _RAND_842;
  reg [31:0] _RAND_843;
  reg [31:0] _RAND_844;
  reg [31:0] _RAND_845;
  reg [31:0] _RAND_846;
  reg [31:0] _RAND_847;
  reg [31:0] _RAND_848;
  reg [31:0] _RAND_849;
  reg [31:0] _RAND_850;
  reg [31:0] _RAND_851;
  reg [31:0] _RAND_852;
  reg [31:0] _RAND_853;
  reg [31:0] _RAND_854;
  reg [31:0] _RAND_855;
  reg [31:0] _RAND_856;
  reg [31:0] _RAND_857;
  reg [31:0] _RAND_858;
  reg [31:0] _RAND_859;
  reg [31:0] _RAND_860;
  reg [31:0] _RAND_861;
  reg [31:0] _RAND_862;
  reg [31:0] _RAND_863;
  reg [31:0] _RAND_864;
  reg [31:0] _RAND_865;
  reg [31:0] _RAND_866;
  reg [31:0] _RAND_867;
  reg [31:0] _RAND_868;
  reg [31:0] _RAND_869;
  reg [31:0] _RAND_870;
  reg [31:0] _RAND_871;
  reg [31:0] _RAND_872;
  reg [31:0] _RAND_873;
  reg [31:0] _RAND_874;
  reg [31:0] _RAND_875;
  reg [31:0] _RAND_876;
  reg [31:0] _RAND_877;
  reg [31:0] _RAND_878;
  reg [31:0] _RAND_879;
  reg [31:0] _RAND_880;
  reg [31:0] _RAND_881;
  reg [31:0] _RAND_882;
  reg [31:0] _RAND_883;
  reg [63:0] _RAND_884;
  reg [63:0] _RAND_885;
  reg [31:0] _RAND_886;
  reg [31:0] _RAND_887;
  reg [31:0] _RAND_888;
  reg [31:0] _RAND_889;
  reg [31:0] _RAND_890;
  reg [31:0] _RAND_891;
  reg [31:0] _RAND_892;
  reg [31:0] _RAND_893;
  reg [31:0] _RAND_894;
  reg [63:0] _RAND_895;
  reg [31:0] _RAND_896;
  reg [31:0] _RAND_897;
  reg [31:0] _RAND_898;
  reg [31:0] _RAND_899;
  reg [31:0] _RAND_900;
  reg [31:0] _RAND_901;
  reg [31:0] _RAND_902;
  reg [31:0] _RAND_903;
  reg [31:0] _RAND_904;
  reg [31:0] _RAND_905;
  reg [31:0] _RAND_906;
  reg [31:0] _RAND_907;
  reg [31:0] _RAND_908;
  reg [31:0] _RAND_909;
  reg [31:0] _RAND_910;
  reg [31:0] _RAND_911;
  reg [31:0] _RAND_912;
  reg [31:0] _RAND_913;
  reg [31:0] _RAND_914;
  reg [31:0] _RAND_915;
  reg [31:0] _RAND_916;
  reg [31:0] _RAND_917;
  reg [31:0] _RAND_918;
  reg [63:0] _RAND_919;
  reg [31:0] _RAND_920;
  reg [31:0] _RAND_921;
  reg [31:0] _RAND_922;
  reg [31:0] _RAND_923;
  reg [31:0] _RAND_924;
  reg [31:0] _RAND_925;
  reg [31:0] _RAND_926;
  reg [31:0] _RAND_927;
  reg [31:0] _RAND_928;
  reg [31:0] _RAND_929;
  reg [31:0] _RAND_930;
  reg [31:0] _RAND_931;
  reg [31:0] _RAND_932;
  reg [31:0] _RAND_933;
  reg [31:0] _RAND_934;
  reg [31:0] _RAND_935;
  reg [31:0] _RAND_936;
  reg [31:0] _RAND_937;
  reg [31:0] _RAND_938;
  reg [31:0] _RAND_939;
  reg [31:0] _RAND_940;
  reg [31:0] _RAND_941;
  reg [31:0] _RAND_942;
  reg [31:0] _RAND_943;
  reg [31:0] _RAND_944;
  reg [31:0] _RAND_945;
  reg [31:0] _RAND_946;
  reg [31:0] _RAND_960;
  reg [31:0] _RAND_977;
  reg [31:0] _RAND_991;
  reg [31:0] _RAND_998;
  reg [31:0] _RAND_1042;
  reg [31:0] _RAND_1043;
  reg [31:0] _RAND_1044;
  reg [31:0] _RAND_1045;
  reg [31:0] _RAND_1046;
  reg [31:0] _RAND_1047;
  reg [31:0] _RAND_1048;
  reg [31:0] _RAND_1049;
  reg [31:0] _RAND_1050;
  reg [31:0] _RAND_1051;
  reg [31:0] _RAND_1052;
  reg [31:0] _RAND_1053;
  reg [31:0] _RAND_1054;
  reg [31:0] _RAND_1055;
  reg [31:0] _RAND_1056;
  reg [31:0] _RAND_1057;
  reg [31:0] _RAND_1058;
  reg [31:0] _RAND_1059;
  reg [31:0] _RAND_1060;
  reg [31:0] _RAND_1061;
  reg [31:0] _RAND_1062;
  reg [31:0] _RAND_1063;
  reg [31:0] _RAND_1064;
  reg [31:0] _RAND_1065;
  reg [31:0] _RAND_1066;
  reg [31:0] _RAND_1067;
  reg [31:0] _RAND_1068;
  reg [31:0] _RAND_1069;
  reg [31:0] _RAND_1070;
  reg [31:0] _RAND_1071;
  reg [31:0] _RAND_1072;
  reg [31:0] _RAND_1073;
  reg [31:0] _RAND_1074;
  reg [31:0] _RAND_1075;
  reg [31:0] _RAND_1076;
  reg [31:0] _RAND_1077;
  reg [31:0] _RAND_1078;
  reg [31:0] _RAND_1079;
  reg [31:0] _RAND_1080;
  reg [31:0] _RAND_1081;
  reg [31:0] _RAND_1082;
  reg [31:0] _RAND_1083;
  reg [31:0] _RAND_1084;
  reg [31:0] _RAND_1085;
  reg [31:0] _RAND_1086;
  reg [31:0] _RAND_1087;
  reg [31:0] _RAND_1088;
  reg [31:0] _RAND_1089;
  reg [31:0] _RAND_1090;
  reg [31:0] _RAND_1091;
  reg [31:0] _RAND_1092;
  reg [31:0] _RAND_1093;
  reg [31:0] _RAND_1094;
  reg [31:0] _RAND_1095;
  reg [31:0] _RAND_1096;
  reg [31:0] _RAND_1097;
  reg [31:0] _RAND_1098;
  reg [31:0] _RAND_1099;
  reg [31:0] _RAND_1100;
  reg [31:0] _RAND_1101;
  reg [31:0] _RAND_1102;
  reg [31:0] _RAND_1103;
  reg [31:0] _RAND_1104;
  reg [31:0] _RAND_1105;
  reg [31:0] _RAND_1106;
  reg [31:0] _RAND_1107;
  reg [31:0] _RAND_1108;
  reg [31:0] _RAND_1109;
  reg [31:0] _RAND_1110;
  reg [31:0] _RAND_1111;
  reg [31:0] _RAND_1112;
  reg [31:0] _RAND_1113;
  reg [31:0] _RAND_1114;
  reg [31:0] _RAND_1115;
  reg [31:0] _RAND_1116;
  reg [31:0] _RAND_1117;
  reg [31:0] _RAND_1118;
  reg [31:0] _RAND_1119;
  reg [31:0] _RAND_1120;
  reg [31:0] _RAND_1121;
  reg [31:0] _RAND_1122;
  reg [31:0] _RAND_1123;
  reg [31:0] _RAND_1124;
  reg [31:0] _RAND_1125;
  reg [31:0] _RAND_1126;
  reg [31:0] _RAND_1127;
  reg [31:0] _RAND_1128;
  reg [31:0] _RAND_1129;
  reg [31:0] _RAND_1130;
  reg [31:0] _RAND_1131;
  reg [31:0] _RAND_1132;
  reg [31:0] _RAND_1133;
  reg [31:0] _RAND_1134;
  reg [31:0] _RAND_1135;
  reg [31:0] _RAND_1136;
  reg [31:0] _RAND_1137;
  reg [31:0] _RAND_1138;
  reg [31:0] _RAND_1139;
  reg [31:0] _RAND_1140;
  reg [31:0] _RAND_1141;
  reg [31:0] _RAND_1142;
  reg [31:0] _RAND_1143;
  reg [63:0] _RAND_1144;
  reg [63:0] _RAND_1145;
  reg [31:0] _RAND_1146;
  reg [31:0] _RAND_1147;
  reg [31:0] _RAND_1148;
  reg [31:0] _RAND_1149;
  reg [31:0] _RAND_1150;
  reg [31:0] _RAND_1151;
  reg [31:0] _RAND_1152;
  reg [31:0] _RAND_1153;
  reg [31:0] _RAND_1154;
  reg [31:0] _RAND_1155;
  reg [31:0] _RAND_1156;
  reg [31:0] _RAND_1157;
  reg [31:0] _RAND_1158;
  reg [31:0] _RAND_1159;
  reg [31:0] _RAND_1160;
  reg [31:0] _RAND_1161;
  reg [31:0] _RAND_1162;
  reg [31:0] _RAND_1163;
  reg [31:0] _RAND_1164;
  reg [31:0] _RAND_1165;
  reg [31:0] _RAND_1166;
  reg [31:0] _RAND_1167;
  reg [31:0] _RAND_1168;
  reg [31:0] _RAND_1169;
  reg [31:0] _RAND_1170;
  reg [31:0] _RAND_1171;
  reg [31:0] _RAND_1172;
  reg [31:0] _RAND_1173;
  reg [31:0] _RAND_1174;
  reg [31:0] _RAND_1175;
  reg [31:0] _RAND_1176;
  reg [31:0] _RAND_1177;
  reg [31:0] _RAND_1178;
  reg [31:0] _RAND_1179;
  reg [31:0] _RAND_1180;
  reg [31:0] _RAND_1181;
  reg [31:0] _RAND_1182;
  reg [31:0] _RAND_1183;
  reg [31:0] _RAND_1184;
  reg [31:0] _RAND_1185;
  reg [31:0] _RAND_1186;
  reg [31:0] _RAND_1187;
  reg [31:0] _RAND_1188;
  reg [31:0] _RAND_1189;
  reg [31:0] _RAND_1190;
  reg [31:0] _RAND_1191;
  reg [31:0] _RAND_1192;
  reg [31:0] _RAND_1193;
  reg [31:0] _RAND_1194;
  reg [31:0] _RAND_1195;
  reg [31:0] _RAND_1196;
  reg [31:0] _RAND_1197;
  reg [31:0] _RAND_1198;
  reg [31:0] _RAND_1199;
  reg [31:0] _RAND_1200;
  reg [31:0] _RAND_1201;
  reg [31:0] _RAND_1202;
  reg [31:0] _RAND_1203;
  reg [31:0] _RAND_1204;
  reg [31:0] _RAND_1205;
  reg [31:0] _RAND_1206;
  reg [31:0] _RAND_1207;
  reg [31:0] _RAND_1208;
  reg [31:0] _RAND_1209;
  reg [31:0] _RAND_1210;
  reg [31:0] _RAND_1211;
  reg [31:0] _RAND_1212;
  reg [31:0] _RAND_1213;
  reg [31:0] _RAND_1214;
  reg [31:0] _RAND_1215;
  reg [31:0] _RAND_1216;
  reg [31:0] _RAND_1217;
  reg [31:0] _RAND_1218;
  reg [31:0] _RAND_1219;
  reg [31:0] _RAND_1220;
  reg [31:0] _RAND_1221;
  reg [31:0] _RAND_1222;
  reg [31:0] _RAND_1223;
  reg [31:0] _RAND_1224;
  reg [31:0] _RAND_1225;
  reg [31:0] _RAND_1226;
  reg [31:0] _RAND_1227;
  reg [31:0] _RAND_1228;
  reg [31:0] _RAND_1229;
  reg [31:0] _RAND_1230;
  reg [31:0] _RAND_1231;
  reg [31:0] _RAND_1232;
  reg [31:0] _RAND_1233;
  reg [31:0] _RAND_1234;
  reg [31:0] _RAND_1235;
  reg [31:0] _RAND_1236;
  reg [31:0] _RAND_1237;
  reg [31:0] _RAND_1238;
  reg [31:0] _RAND_1239;
  reg [31:0] _RAND_1240;
  reg [31:0] _RAND_1241;
  reg [31:0] _RAND_1242;
  reg [31:0] _RAND_1243;
  reg [31:0] _RAND_1244;
  reg [31:0] _RAND_1245;
  reg [31:0] _RAND_1246;
  reg [31:0] _RAND_1247;
  reg [31:0] _RAND_1248;
  reg [63:0] _RAND_1249;
  reg [63:0] _RAND_1250;
  reg [31:0] _RAND_1251;
  reg [31:0] _RAND_1252;
  reg [31:0] _RAND_1253;
  reg [31:0] _RAND_1254;
  reg [31:0] _RAND_1255;
  reg [31:0] _RAND_1256;
  reg [31:0] _RAND_1257;
  reg [31:0] _RAND_1258;
  reg [95:0] _RAND_1259;
  reg [95:0] _RAND_1260;
  reg [95:0] _RAND_1261;
  reg [95:0] _RAND_1262;
  reg [31:0] _RAND_1263;
  reg [31:0] _RAND_1264;
  reg [31:0] _RAND_1265;
  reg [31:0] _RAND_1268;
  reg [31:0] _RAND_1271;
  reg [31:0] _RAND_1278;
  reg [31:0] _RAND_1284;
  reg [31:0] _RAND_1285;
  reg [31:0] _RAND_1286;
  reg [31:0] _RAND_1287;
  reg [31:0] _RAND_1288;
  reg [31:0] _RAND_1289;
  reg [31:0] _RAND_1290;
  reg [31:0] _RAND_1291;
  reg [31:0] _RAND_1292;
  reg [31:0] _RAND_1293;
  reg [31:0] _RAND_1294;
  reg [31:0] _RAND_1295;
  reg [31:0] _RAND_1296;
  reg [31:0] _RAND_1297;
  reg [31:0] _RAND_1298;
  reg [31:0] _RAND_1299;
  reg [31:0] _RAND_1300;
  reg [31:0] _RAND_1301;
  reg [31:0] _RAND_1302;
  reg [31:0] _RAND_1303;
  reg [31:0] _RAND_1304;
  reg [31:0] _RAND_1305;
  reg [31:0] _RAND_1306;
  reg [31:0] _RAND_1307;
  reg [31:0] _RAND_1308;
  reg [31:0] _RAND_1309;
  reg [31:0] _RAND_1310;
  reg [31:0] _RAND_1311;
  reg [31:0] _RAND_1312;
  reg [31:0] _RAND_1313;
  reg [31:0] _RAND_1314;
  reg [31:0] _RAND_1315;
  reg [31:0] _RAND_1316;
  reg [31:0] _RAND_1317;
  reg [31:0] _RAND_1318;
  reg [31:0] _RAND_1319;
  reg [31:0] _RAND_1320;
  reg [31:0] _RAND_1321;
  reg [31:0] _RAND_1322;
  reg [31:0] _RAND_1323;
  reg [63:0] _RAND_1324;
  reg [63:0] _RAND_1325;
  reg [31:0] _RAND_1326;
  reg [31:0] _RAND_1327;
  reg [31:0] _RAND_1328;
  reg [31:0] _RAND_1329;
  reg [31:0] _RAND_1330;
  reg [31:0] _RAND_1331;
  reg [31:0] _RAND_1332;
  reg [31:0] _RAND_1333;
  reg [31:0] _RAND_1334;
  reg [31:0] _RAND_1335;
  reg [31:0] _RAND_1336;
  reg [31:0] _RAND_1337;
  reg [31:0] _RAND_1338;
  reg [31:0] _RAND_1339;
  reg [31:0] _RAND_1340;
  reg [31:0] _RAND_1341;
  reg [31:0] _RAND_1342;
  reg [31:0] _RAND_1343;
  reg [31:0] _RAND_1344;
  reg [31:0] _RAND_1345;
  reg [31:0] _RAND_1346;
  reg [31:0] _RAND_1347;
  reg [31:0] _RAND_1348;
  reg [31:0] _RAND_1349;
  reg [31:0] _RAND_1350;
  reg [31:0] _RAND_1351;
  reg [31:0] _RAND_1352;
  reg [31:0] _RAND_1353;
  reg [31:0] _RAND_1354;
  reg [31:0] _RAND_1355;
  reg [31:0] _RAND_1356;
  reg [31:0] _RAND_1357;
  reg [31:0] _RAND_1358;
  reg [31:0] _RAND_1359;
  reg [31:0] _RAND_1360;
  reg [31:0] _RAND_1361;
  reg [31:0] _RAND_1362;
  reg [31:0] _RAND_1363;
  reg [63:0] _RAND_1364;
  reg [63:0] _RAND_1365;
  reg [31:0] _RAND_1366;
  reg [31:0] _RAND_1367;
  reg [31:0] _RAND_1368;
  reg [31:0] _RAND_1369;
  reg [31:0] _RAND_1370;
  reg [31:0] _RAND_1371;
  reg [31:0] _RAND_1372;
  reg [31:0] _RAND_1373;
  reg [31:0] _RAND_1374;
  reg [31:0] _RAND_1375;
  reg [31:0] _RAND_1376;
  reg [31:0] _RAND_1377;
  reg [31:0] _RAND_1378;
  reg [31:0] _RAND_1379;
  reg [31:0] _RAND_1380;
  reg [31:0] _RAND_1381;
  reg [31:0] _RAND_1382;
  reg [31:0] _RAND_1383;
  reg [31:0] _RAND_1384;
  reg [31:0] _RAND_1385;
  reg [31:0] _RAND_1386;
  reg [31:0] _RAND_1387;
  reg [31:0] _RAND_1388;
  reg [31:0] _RAND_1389;
  reg [31:0] _RAND_1390;
  reg [31:0] _RAND_1391;
  reg [31:0] _RAND_1392;
  reg [31:0] _RAND_1393;
  reg [31:0] _RAND_1394;
  reg [31:0] _RAND_1395;
  reg [31:0] _RAND_1396;
  reg [31:0] _RAND_1397;
  reg [31:0] _RAND_1398;
  reg [31:0] _RAND_1399;
  reg [31:0] _RAND_1400;
  reg [31:0] _RAND_1401;
  reg [31:0] _RAND_1402;
  reg [31:0] _RAND_1403;
  reg [31:0] _RAND_1404;
  reg [31:0] _RAND_1405;
  reg [31:0] _RAND_1406;
  reg [31:0] _RAND_1407;
  reg [31:0] _RAND_1408;
  reg [31:0] _RAND_1409;
  reg [31:0] _RAND_1410;
  reg [63:0] _RAND_1411;
  reg [63:0] _RAND_1412;
  reg [31:0] _RAND_1413;
  reg [31:0] _RAND_1414;
  reg [31:0] _RAND_1415;
  reg [31:0] _RAND_1416;
  reg [31:0] _RAND_1417;
  reg [31:0] _RAND_1418;
  reg [31:0] _RAND_1419;
  reg [31:0] _RAND_1420;
  reg [31:0] _RAND_1421;
  reg [31:0] _RAND_1422;
  reg [31:0] _RAND_1423;
  reg [31:0] _RAND_1424;
  reg [31:0] _RAND_1425;
  reg [31:0] _RAND_1426;
  reg [31:0] _RAND_1427;
  reg [31:0] _RAND_1428;
  reg [31:0] _RAND_1429;
  reg [31:0] _RAND_1430;
  reg [31:0] _RAND_1431;
  reg [31:0] _RAND_1432;
  reg [31:0] _RAND_1433;
  reg [31:0] _RAND_1434;
  reg [31:0] _RAND_1435;
  reg [31:0] _RAND_1436;
  reg [31:0] _RAND_1437;
  reg [31:0] _RAND_1438;
  reg [31:0] _RAND_1439;
  reg [31:0] _RAND_1440;
  reg [31:0] _RAND_1441;
  reg [31:0] _RAND_1442;
  reg [31:0] _RAND_1443;
  reg [31:0] _RAND_1444;
  reg [31:0] _RAND_1445;
  reg [31:0] _RAND_1446;
  reg [31:0] _RAND_1447;
  reg [31:0] _RAND_1448;
  reg [31:0] _RAND_1449;
  reg [31:0] _RAND_1450;
  reg [31:0] _RAND_1451;
  reg [31:0] _RAND_1452;
  reg [63:0] _RAND_1453;
  reg [63:0] _RAND_1454;
  reg [31:0] _RAND_1455;
  reg [31:0] _RAND_1456;
  reg [31:0] _RAND_1457;
  reg [31:0] _RAND_1458;
  reg [63:0] _RAND_1459;
  reg [63:0] _RAND_1460;
  reg [31:0] _RAND_1461;
  reg [31:0] _RAND_1462;
  reg [31:0] _RAND_1463;
  reg [31:0] _RAND_1464;
  reg [31:0] _RAND_1465;
  reg [31:0] _RAND_1466;
  reg [31:0] _RAND_1467;
  reg [31:0] _RAND_1469;
  reg [31:0] _RAND_1476;
  reg [31:0] _RAND_1477;
  reg [31:0] _RAND_1478;
  reg [31:0] _RAND_1479;
  reg [31:0] _RAND_1480;
  reg [31:0] _RAND_1481;
  reg [31:0] _RAND_1482;
  reg [31:0] _RAND_1483;
  reg [31:0] _RAND_1529;
  reg [31:0] _RAND_1530;
  reg [31:0] _RAND_1531;
  reg [31:0] _RAND_1538;
  reg [31:0] _RAND_1539;
  reg [31:0] _RAND_1540;
  reg [31:0] _RAND_1586;
  reg [31:0] _RAND_1588;
  reg [31:0] _RAND_1589;
  reg [31:0] _RAND_1591;
  reg [31:0] _RAND_1592;
  reg [31:0] _RAND_1594;
  reg [31:0] _RAND_1595;
  reg [31:0] _RAND_1597;
  reg [31:0] _RAND_1598;
  reg [31:0] _RAND_1600;
  reg [31:0] _RAND_1601;
  reg [31:0] _RAND_1603;
  reg [31:0] _RAND_1604;
  reg [31:0] _RAND_1606;
  reg [31:0] _RAND_1607;
  reg [31:0] _RAND_1609;
  reg [31:0] _RAND_1610;
  reg [31:0] _RAND_1612;
  reg [31:0] _RAND_1613;
  reg [31:0] _RAND_1615;
  reg [31:0] _RAND_1616;
  reg [31:0] _RAND_1618;
  reg [31:0] _RAND_1619;
  reg [31:0] _RAND_1621;
  reg [31:0] _RAND_1622;
  reg [31:0] _RAND_1624;
  reg [31:0] _RAND_1625;
  reg [31:0] _RAND_1627;
  reg [31:0] _RAND_1628;
  reg [31:0] _RAND_1630;
  reg [31:0] _RAND_1631;
  reg [31:0] _RAND_1633;
  reg [31:0] _RAND_1634;
  reg [31:0] _RAND_1636;
  reg [31:0] _RAND_1637;
  reg [31:0] _RAND_1638;
  reg [31:0] _RAND_1639;
  reg [31:0] _RAND_1640;
  reg [127:0] _RAND_1641;
  reg [31:0] _RAND_1642;
  reg [31:0] _RAND_1643;
  reg [31:0] _RAND_1644;
  reg [31:0] _RAND_1645;
  reg [31:0] _RAND_1646;
  reg [31:0] _RAND_1647;
  reg [31:0] _RAND_1648;
  reg [31:0] _RAND_1649;
  reg [31:0] _RAND_1650;
  reg [31:0] _RAND_1651;
  reg [31:0] _RAND_1652;
  reg [31:0] _RAND_1653;
  reg [31:0] _RAND_1654;
  reg [31:0] _RAND_1655;
  reg [31:0] _RAND_1656;
  reg [31:0] _RAND_1657;
  reg [31:0] _RAND_1658;
  reg [31:0] _RAND_1659;
  reg [31:0] _RAND_1660;
  reg [31:0] _RAND_1661;
  reg [31:0] _RAND_1662;
  reg [31:0] _RAND_1663;
  reg [31:0] _RAND_1664;
  reg [31:0] _RAND_1665;
  reg [31:0] _RAND_1666;
  reg [31:0] _RAND_1667;
  reg [31:0] _RAND_1668;
  reg [31:0] _RAND_1669;
  reg [31:0] _RAND_1670;
  reg [31:0] _RAND_1671;
  reg [31:0] _RAND_1672;
  reg [31:0] _RAND_1673;
  reg [31:0] _RAND_1674;
  reg [31:0] _RAND_1675;
  reg [31:0] _RAND_1676;
  reg [31:0] _RAND_1677;
  reg [31:0] _RAND_1678;
  reg [31:0] _RAND_1679;
  reg [31:0] _RAND_1680;
  reg [31:0] _RAND_1681;
  reg [31:0] _RAND_1682;
  reg [31:0] _RAND_1683;
  reg [31:0] _RAND_1684;
  reg [31:0] _RAND_1685;
  reg [31:0] _RAND_1686;
  reg [31:0] _RAND_1687;
  reg [31:0] _RAND_1688;
  reg [31:0] _RAND_1689;
  reg [31:0] _RAND_1690;
  reg [31:0] _RAND_1691;
  reg [31:0] _RAND_1692;
  reg [31:0] _RAND_1693;
  reg [31:0] _RAND_1694;
  reg [31:0] _RAND_1695;
  reg [31:0] _RAND_1696;
  reg [31:0] _RAND_1697;
  reg [31:0] _RAND_1698;
  reg [31:0] _RAND_1699;
  reg [31:0] _RAND_1700;
  reg [31:0] _RAND_1701;
  reg [31:0] _RAND_1702;
  reg [31:0] _RAND_1703;
  reg [31:0] _RAND_1704;
  reg [31:0] _RAND_1705;
  reg [31:0] _RAND_1706;
  reg [31:0] _RAND_1707;
  reg [31:0] _RAND_1708;
  reg [31:0] _RAND_1709;
  reg [31:0] _RAND_1710;
  reg [31:0] _RAND_1711;
  reg [31:0] _RAND_1712;
  reg [31:0] _RAND_1713;
  reg [31:0] _RAND_1714;
  reg [31:0] _RAND_1715;
  reg [31:0] _RAND_1716;
  reg [31:0] _RAND_1717;
  reg [31:0] _RAND_1718;
  reg [31:0] _RAND_1719;
  reg [31:0] _RAND_1720;
  reg [31:0] _RAND_1721;
  reg [31:0] _RAND_1722;
  reg [31:0] _RAND_1723;
  reg [31:0] _RAND_1724;
  reg [31:0] _RAND_1725;
  reg [31:0] _RAND_1726;
  reg [31:0] _RAND_1727;
  reg [31:0] _RAND_1728;
  reg [31:0] _RAND_1729;
  reg [31:0] _RAND_1730;
  reg [127:0] _RAND_1731;
  reg [31:0] _RAND_1732;
  reg [31:0] _RAND_1733;
  reg [31:0] _RAND_1734;
  reg [31:0] _RAND_1735;
  reg [31:0] _RAND_1736;
  reg [127:0] _RAND_1737;
  reg [31:0] _RAND_1738;
  reg [31:0] _RAND_1739;
  reg [31:0] _RAND_1740;
  reg [31:0] _RAND_1741;
  reg [31:0] _RAND_1742;
  reg [31:0] _RAND_1743;
  reg [31:0] _RAND_1744;
  reg [31:0] _RAND_1745;
  reg [31:0] _RAND_1746;
  reg [31:0] _RAND_1747;
  reg [31:0] _RAND_1748;
  reg [31:0] _RAND_1749;
  reg [31:0] _RAND_1750;
  reg [31:0] _RAND_1751;
  reg [31:0] _RAND_1752;
  reg [31:0] _RAND_1753;
  reg [31:0] _RAND_1754;
  reg [31:0] _RAND_1755;
  reg [31:0] _RAND_1756;
  reg [31:0] _RAND_1757;
  reg [31:0] _RAND_1758;
  reg [31:0] _RAND_1759;
  reg [31:0] _RAND_1760;
  reg [31:0] _RAND_1761;
  reg [31:0] _RAND_1762;
  reg [31:0] _RAND_1763;
  reg [31:0] _RAND_1764;
  reg [31:0] _RAND_1765;
  reg [31:0] _RAND_1766;
  reg [31:0] _RAND_1767;
  reg [31:0] _RAND_1768;
  reg [31:0] _RAND_1769;
  reg [31:0] _RAND_1770;
  reg [31:0] _RAND_1771;
  reg [31:0] _RAND_1772;
  reg [31:0] _RAND_1773;
  reg [31:0] _RAND_1774;
  reg [31:0] _RAND_1775;
  reg [31:0] _RAND_1776;
  reg [31:0] _RAND_1777;
  reg [31:0] _RAND_1778;
  reg [31:0] _RAND_1779;
  reg [31:0] _RAND_1780;
  reg [31:0] _RAND_1781;
  reg [31:0] _RAND_1782;
  reg [63:0] _RAND_1783;
  reg [31:0] _RAND_1784;
  reg [31:0] _RAND_1785;
  reg [31:0] _RAND_1786;
  reg [31:0] _RAND_1787;
  reg [31:0] _RAND_1788;
  reg [31:0] _RAND_1789;
  reg [31:0] _RAND_1790;
  reg [31:0] _RAND_1793;
  reg [31:0] _RAND_1794;
  reg [31:0] _RAND_1797;
  reg [31:0] _RAND_1800;
  reg [31:0] _RAND_1801;
  reg [31:0] _RAND_1802;
  reg [31:0] _RAND_1803;
  reg [31:0] _RAND_1804;
  reg [31:0] _RAND_1805;
  reg [31:0] _RAND_1806;
  reg [63:0] _RAND_1807;
  reg [31:0] _RAND_1810;
  reg [31:0] _RAND_1816;
  reg [31:0] _RAND_1819;
  reg [31:0] _RAND_1820;
  reg [31:0] _RAND_1821;
  reg [127:0] _RAND_1822;
  reg [63:0] _RAND_1823;
  reg [31:0] _RAND_1824;
  reg [31:0] _RAND_1825;
  reg [31:0] _RAND_1826;
  reg [31:0] _RAND_1827;
  reg [31:0] _RAND_1828;
  reg [31:0] _RAND_1829;
  reg [31:0] _RAND_1830;
  reg [31:0] _RAND_1831;
  reg [31:0] _RAND_1832;
  reg [63:0] _RAND_1833;
  reg [63:0] _RAND_1834;
  reg [31:0] _RAND_1835;
  reg [31:0] _RAND_1836;
  reg [31:0] _RAND_1837;
  reg [31:0] _RAND_1838;
  reg [31:0] _RAND_1839;
  reg [31:0] _RAND_1840;
  reg [31:0] _RAND_1841;
  reg [31:0] _RAND_1842;
  reg [31:0] _RAND_1843;
  reg [31:0] _RAND_1844;
  reg [31:0] _RAND_1845;
  reg [31:0] _RAND_1846;
  reg [31:0] _RAND_1847;
  reg [31:0] _RAND_1848;
  reg [31:0] _RAND_1849;
  reg [31:0] _RAND_1850;
  reg [31:0] _RAND_1851;
  reg [31:0] _RAND_1852;
  reg [31:0] _RAND_1853;
  reg [31:0] _RAND_1854;
  reg [31:0] _RAND_1855;
  reg [31:0] _RAND_1856;
  reg [31:0] _RAND_1857;
  reg [31:0] _RAND_1858;
  reg [31:0] _RAND_1859;
  reg [31:0] _RAND_1860;
  reg [31:0] _RAND_1861;
  reg [31:0] _RAND_1862;
  reg [31:0] _RAND_1863;
  reg [31:0] _RAND_1864;
  reg [31:0] _RAND_1865;
  reg [31:0] _RAND_1866;
  reg [31:0] _RAND_1867;
  reg [63:0] _RAND_1868;
  reg [63:0] _RAND_1869;
  reg [63:0] _RAND_1870;
  reg [63:0] _RAND_1871;
  reg [63:0] _RAND_1872;
  reg [63:0] _RAND_1873;
  reg [63:0] _RAND_1874;
  reg [63:0] _RAND_1875;
  reg [63:0] _RAND_1876;
  reg [63:0] _RAND_1877;
  reg [63:0] _RAND_1878;
  reg [63:0] _RAND_1879;
  reg [63:0] _RAND_1880;
  reg [63:0] _RAND_1881;
  reg [63:0] _RAND_1882;
  reg [63:0] _RAND_1883;
  reg [63:0] _RAND_1884;
  reg [63:0] _RAND_1885;
  reg [63:0] _RAND_1886;
  reg [63:0] _RAND_1887;
  reg [63:0] _RAND_1888;
  reg [63:0] _RAND_1889;
  reg [63:0] _RAND_1890;
  reg [63:0] _RAND_1891;
  reg [63:0] _RAND_1892;
  reg [63:0] _RAND_1893;
  reg [63:0] _RAND_1894;
  reg [63:0] _RAND_1895;
  reg [63:0] _RAND_1896;
  reg [63:0] _RAND_1897;
  reg [63:0] _RAND_1898;
  reg [63:0] _RAND_1899;
  reg [63:0] _RAND_1900;
  reg [31:0] _RAND_1901;
  reg [31:0] _RAND_1902;
  reg [31:0] _RAND_1903;
  reg [31:0] _RAND_1904;
  reg [31:0] _RAND_1905;
  reg [31:0] _RAND_1906;
  reg [31:0] _RAND_1907;
  reg [31:0] _RAND_1908;
  reg [31:0] _RAND_1909;
  reg [31:0] _RAND_1910;
  reg [31:0] _RAND_1911;
  reg [31:0] _RAND_1912;
  reg [31:0] _RAND_1913;
  reg [31:0] _RAND_1914;
  reg [31:0] _RAND_1915;
  reg [31:0] _RAND_1916;
  reg [31:0] _RAND_1917;
  reg [31:0] _RAND_1918;
  reg [31:0] _RAND_1919;
  reg [31:0] _RAND_1920;
  reg [31:0] _RAND_1921;
  reg [31:0] _RAND_1922;
  reg [31:0] _RAND_1923;
  reg [31:0] _RAND_1924;
  reg [31:0] _RAND_1925;
  reg [31:0] _RAND_1926;
  reg [31:0] _RAND_1927;
  reg [31:0] _RAND_1928;
  reg [31:0] _RAND_1929;
  reg [31:0] _RAND_1930;
  reg [31:0] _RAND_1931;
  reg [31:0] _RAND_1932;
  reg [31:0] _RAND_1933;
  reg [31:0] _RAND_1934;
  reg [31:0] _RAND_1935;
  reg [31:0] _RAND_1936;
  reg [31:0] _RAND_1937;
  reg [31:0] _RAND_1938;
  reg [31:0] _RAND_1939;
  reg [31:0] _RAND_1940;
  reg [31:0] _RAND_1941;
  reg [31:0] _RAND_1942;
  reg [31:0] _RAND_1943;
  reg [31:0] _RAND_1944;
  reg [31:0] _RAND_1945;
  reg [31:0] _RAND_1946;
  reg [31:0] _RAND_1947;
  reg [31:0] _RAND_1948;
  reg [31:0] _RAND_1949;
  reg [31:0] _RAND_1950;
  reg [31:0] _RAND_1951;
  reg [31:0] _RAND_1952;
  reg [31:0] _RAND_1953;
  reg [31:0] _RAND_1954;
  reg [31:0] _RAND_1955;
  reg [31:0] _RAND_1956;
  reg [31:0] _RAND_1957;
  reg [31:0] _RAND_1958;
  reg [31:0] _RAND_1959;
  reg [31:0] _RAND_1960;
  reg [31:0] _RAND_1961;
  reg [31:0] _RAND_1962;
  reg [31:0] _RAND_1963;
  reg [31:0] _RAND_1964;
  reg [31:0] _RAND_1965;
  reg [31:0] _RAND_1966;
  reg [63:0] _RAND_1967;
  reg [31:0] _RAND_1968;
  reg [31:0] _RAND_1969;
  reg [31:0] _RAND_1970;
  reg [31:0] _RAND_1971;
  reg [63:0] _RAND_1972;
  reg [63:0] _RAND_1973;
  reg [31:0] _RAND_1974;
  reg [63:0] _RAND_1975;
  reg [63:0] _RAND_1976;
  reg [31:0] _RAND_1977;
  reg [63:0] _RAND_1978;
  reg [63:0] _RAND_1979;
  reg [31:0] _RAND_1980;
  reg [31:0] _RAND_1981;
  reg [63:0] _RAND_1982;
  reg [63:0] _RAND_1983;
  reg [31:0] _RAND_1984;
  reg [31:0] _RAND_1985;
  reg [31:0] _RAND_1986;
  reg [31:0] _RAND_1987;
  reg [31:0] _RAND_1988;
  reg [31:0] _RAND_1989;
  reg [31:0] _RAND_1990;
  reg [31:0] _RAND_1991;
  reg [31:0] _RAND_1992;
  reg [31:0] _RAND_1993;
  reg [31:0] _RAND_1994;
  reg [31:0] _RAND_1995;
  reg [31:0] _RAND_1996;
  reg [31:0] _RAND_1997;
  reg [63:0] _RAND_1998;
  reg [63:0] _RAND_1999;
  reg [63:0] _RAND_2000;
  reg [31:0] _RAND_2001;
  reg [31:0] _RAND_2002;
  reg [31:0] _RAND_2003;
  reg [31:0] _RAND_2004;
  reg [31:0] _RAND_2005;
  reg [31:0] _RAND_2006;
  reg [63:0] _RAND_2007;
  reg [31:0] _RAND_2008;
  reg [63:0] _RAND_2009;
  reg [63:0] _RAND_2010;
  reg [31:0] _RAND_2011;
  reg [63:0] _RAND_2012;
  reg [63:0] _RAND_2013;
  reg [31:0] _RAND_2014;
  reg [31:0] _RAND_2015;
  reg [31:0] _RAND_2016;
  reg [31:0] _RAND_2017;
  reg [31:0] _RAND_2018;
  reg [31:0] _RAND_2019;
  reg [63:0] _RAND_2020;
  reg [63:0] _RAND_2021;
  reg [63:0] _RAND_2022;
  reg [63:0] _RAND_2023;
  reg [63:0] _RAND_2024;
  reg [63:0] _RAND_2025;
  reg [63:0] _RAND_2026;
  reg [63:0] _RAND_2027;
  reg [31:0] _RAND_2028;
  reg [31:0] _RAND_2029;
  reg [31:0] _RAND_2030;
  reg [31:0] _RAND_2031;
  reg [31:0] _RAND_2032;
  reg [31:0] _RAND_2033;
  reg [63:0] _RAND_2034;
  reg [63:0] _RAND_2035;
  reg [63:0] _RAND_2036;
  reg [63:0] _RAND_2037;
  reg [31:0] _RAND_2038;
  reg [31:0] _RAND_2039;
  reg [31:0] _RAND_2040;
  reg [31:0] _RAND_2041;
  reg [31:0] _RAND_2042;
  reg [31:0] _RAND_2043;
  reg [31:0] _RAND_2044;
  reg [31:0] _RAND_2045;
  reg [31:0] _RAND_2046;
  reg [31:0] _RAND_2047;
  reg [31:0] _RAND_2048;
  reg [31:0] _RAND_2049;
  reg [31:0] _RAND_2050;
  reg [31:0] _RAND_2051;
  reg [31:0] _RAND_2052;
  reg [31:0] _RAND_2053;
  reg [31:0] _RAND_2054;
  reg [31:0] _RAND_2055;
  reg [31:0] _RAND_2056;
  reg [31:0] _RAND_2057;
  reg [31:0] _RAND_2058;
  reg [31:0] _RAND_2059;
  reg [31:0] _RAND_2060;
  reg [31:0] _RAND_2061;
  reg [63:0] _RAND_2062;
  reg [31:0] _RAND_2063;
  reg [31:0] _RAND_2064;
  reg [63:0] _RAND_2065;
  reg [31:0] _RAND_2066;
  reg [31:0] _RAND_2067;
  reg [31:0] _RAND_2068;
  reg [31:0] _RAND_2069;
  reg [31:0] _RAND_2070;
  reg [31:0] _RAND_2071;
  reg [31:0] _RAND_2072;
  reg [31:0] _RAND_2073;
  reg [31:0] _RAND_2074;
  reg [31:0] _RAND_2075;
  reg [31:0] _RAND_2076;
  reg [31:0] _RAND_2077;
  reg [31:0] _RAND_2078;
  reg [31:0] _RAND_2079;
  reg [31:0] _RAND_2080;
  reg [31:0] _RAND_2081;
  reg [31:0] _RAND_2082;
  reg [31:0] _RAND_2083;
  reg [31:0] _RAND_2084;
  reg [31:0] _RAND_2085;
  reg [63:0] _RAND_2086;
  reg [31:0] _RAND_2087;
  reg [31:0] _RAND_2088;
  reg [63:0] _RAND_2089;
  reg [31:0] _RAND_2090;
  reg [31:0] _RAND_2091;
  reg [31:0] _RAND_2092;
  reg [31:0] _RAND_2093;
  reg [31:0] _RAND_2094;
  reg [31:0] _RAND_2095;
  reg [63:0] _RAND_2096;
  reg [63:0] _RAND_2097;
  reg [31:0] _RAND_2098;
  reg [63:0] _RAND_2099;
  reg [31:0] _RAND_2100;
  reg [31:0] _RAND_2101;
  reg [63:0] _RAND_2102;
  reg [31:0] _RAND_2103;
  reg [31:0] _RAND_2104;
  reg [31:0] _RAND_2105;
  reg [31:0] _RAND_2106;
  reg [31:0] _RAND_2107;
  reg [31:0] _RAND_2108;
  reg [31:0] _RAND_2109;
  reg [31:0] _RAND_2110;
  reg [31:0] _RAND_2111;
  reg [31:0] _RAND_2112;
  reg [31:0] _RAND_2113;
  reg [31:0] _RAND_2114;
  reg [31:0] _RAND_2115;
  reg [31:0] _RAND_2116;
  reg [31:0] _RAND_2117;
  reg [31:0] _RAND_2118;
  reg [63:0] _RAND_2119;
  reg [63:0] _RAND_2120;
  reg [31:0] _RAND_2121;
  reg [63:0] _RAND_2122;
  reg [31:0] _RAND_2123;
  reg [31:0] _RAND_2124;
  reg [63:0] _RAND_2125;
  reg [31:0] _RAND_2126;
  reg [31:0] _RAND_2127;
  reg [31:0] _RAND_2128;
  reg [31:0] _RAND_2129;
  reg [31:0] _RAND_2130;
  reg [31:0] _RAND_2131;
  reg [31:0] _RAND_2132;
  reg [31:0] _RAND_2133;
  reg [31:0] _RAND_2134;
  reg [31:0] _RAND_2135;
  reg [31:0] _RAND_2136;
  reg [31:0] _RAND_2137;
  reg [31:0] _RAND_2138;
  reg [31:0] _RAND_2139;
`endif // RANDOMIZE_REG_INIT
  wire  if1_clock;
  wire  if1_reset;
  wire  if1_io_if4Redirect_valid;
  wire [38:0] if1_io_if4Redirect_bits_target;
  wire  if1_io_cmmRedirect_valid;
  wire [63:0] if1_io_cmmRedirect_bits_pc;
  wire  if1_io_pc_gen_ready;
  wire  if1_io_pc_gen_valid;
  wire  if1_io_pc_gen_bits_isActive_0;
  wire  if1_io_pc_gen_bits_isActive_1;
  wire  if1_io_pc_gen_bits_isActive_2;
  wire  if1_io_pc_gen_bits_isActive_3;
  wire [63:0] if1_io_pc_gen_bits_pc;
  wire  if1_uBTB_io_resp_isActive_0;
  wire  if1_uBTB_io_resp_isActive_1;
  wire  if1_uBTB_io_resp_isActive_2;
  wire  if1_uBTB_io_resp_isActive_3;
  wire [1:0] if1_uBTB__io_resp_isActive_0_T_2 = 2'h3 - 2'h0; // @[uBTB.scala 150:42]
  reg [63:0] if1_pc_qout; // @[IF1.scala 42:24]
  wire  if1__pc_qout_v64_T = if1_io_if4Redirect_bits_target[38]; // @[Util.scala 47:31]
  wire [24:0] if1__pc_qout_v64_T_2 = if1__pc_qout_v64_T ? 25'h1ffffff : 25'h0; // @[Bitwise.scala 77:12]
  wire [63:0] if1__pc_qout_v64_T_4 = {if1__pc_qout_v64_T_2,if1_io_if4Redirect_bits_target}; // @[Cat.scala 33:92]
  wire  if1__T = if1_io_pc_gen_ready & if1_io_pc_gen_valid; // @[Decoupled.scala 52:35]
  wire [63:0] if1__pc_qout_T_2 = if1_pc_qout + 64'h8; // @[IF1.scala 117:25]
  wire [60:0] if1__pc_qout_T_3 = if1__pc_qout_T_2[63:3]; // @[IF1.scala 117:61]
  wire [63:0] if1__pc_qout_T_4 = {if1__pc_qout_T_3, 3'h0}; // @[IF1.scala 117:87]
  wire [63:0] if1__GEN_0 = if1__T ? if1__pc_qout_T_4 : if1_pc_qout; // @[IF1.scala 116:31 117:13 42:24]
  wire  if2_clock;
  wire  if2_reset;
  wire  if2_io_if2_req_ready;
  wire  if2_io_if2_req_valid;
  wire  if2_io_if2_req_bits_isActive_0;
  wire  if2_io_if2_req_bits_isActive_1;
  wire  if2_io_if2_req_bits_isActive_2;
  wire  if2_io_if2_req_bits_isActive_3;
  wire [63:0] if2_io_if2_req_bits_pc;
  wire  if2_io_if2_resp_0_ready;
  wire  if2_io_if2_resp_0_valid;
  wire [38:0] if2_io_if2_resp_0_bits_pc;
  wire [15:0] if2_io_if2_resp_0_bits_instr;
  wire  if2_io_if2_resp_0_bits_isRedirect;
  wire  if2_io_if2_resp_1_ready;
  wire  if2_io_if2_resp_1_valid;
  wire [38:0] if2_io_if2_resp_1_bits_pc;
  wire [15:0] if2_io_if2_resp_1_bits_instr;
  wire  if2_io_if2_resp_1_bits_isFault;
  wire  if2_io_if2_resp_1_bits_isRedirect;
  wire  if2_io_if2_resp_2_ready;
  wire  if2_io_if2_resp_2_valid;
  wire [38:0] if2_io_if2_resp_2_bits_pc;
  wire [15:0] if2_io_if2_resp_2_bits_instr;
  wire  if2_io_if2_resp_2_bits_isFault;
  wire  if2_io_if2_resp_2_bits_isRedirect;
  wire  if2_io_if2_resp_3_ready;
  wire  if2_io_if2_resp_3_valid;
  wire [38:0] if2_io_if2_resp_3_bits_pc;
  wire [15:0] if2_io_if2_resp_3_bits_instr;
  wire  if2_io_if2_resp_3_bits_isFault;
  wire  if2_io_if2_resp_3_bits_isRedirect;
  wire  if2_io_if_mmu_ready;
  wire  if2_io_if_mmu_valid;
  wire  if2_io_if_mmu_bits_is_X;
  wire [63:0] if2_io_if_mmu_bits_vaddr;
  wire  if2_io_mmu_if_ready;
  wire  if2_io_mmu_if_valid;
  wire [63:0] if2_io_mmu_if_bits_vaddr;
  wire [63:0] if2_io_mmu_if_bits_paddr;
  wire  if2_io_mmu_if_bits_is_paging_fault;
  wire  if2_io_mmu_if_bits_is_access_fault;
  wire [63:0] if2_io_if_cmm_ill_vaddr;
  wire  if2_io_icache_get_ready;
  wire  if2_io_icache_get_valid;
  wire [2:0] if2_io_icache_get_bits_opcode;
  wire [2:0] if2_io_icache_get_bits_param;
  wire [2:0] if2_io_icache_get_bits_size;
  wire  if2_io_icache_get_bits_source;
  wire [31:0] if2_io_icache_get_bits_address;
  wire [7:0] if2_io_icache_get_bits_mask;
  wire [63:0] if2_io_icache_get_bits_data;
  wire  if2_io_icache_get_bits_corrupt;
  wire  if2_io_icache_access_ready;
  wire  if2_io_icache_access_valid;
  wire [2:0] if2_io_icache_access_bits_opcode;
  wire [2:0] if2_io_icache_access_bits_size;
  wire [63:0] if2_io_icache_access_bits_data;
  wire  if2_io_flush;
  wire  if2_io_ifence;
  wire  if2_ibuf_clock;
  wire  if2_ibuf_reset;
  wire  if2_ibuf_io_enq_0_ready;
  wire  if2_ibuf_io_enq_0_valid;
  wire [38:0] if2_ibuf_io_enq_0_bits_pc;
  wire [15:0] if2_ibuf_io_enq_0_bits_instr;
  wire  if2_ibuf_io_enq_0_bits_isFault;
  wire  if2_ibuf_io_enq_1_ready;
  wire  if2_ibuf_io_enq_1_valid;
  wire [38:0] if2_ibuf_io_enq_1_bits_pc;
  wire [15:0] if2_ibuf_io_enq_1_bits_instr;
  wire  if2_ibuf_io_enq_2_ready;
  wire  if2_ibuf_io_enq_2_valid;
  wire [38:0] if2_ibuf_io_enq_2_bits_pc;
  wire [15:0] if2_ibuf_io_enq_2_bits_instr;
  wire  if2_ibuf_io_enq_3_ready;
  wire  if2_ibuf_io_enq_3_valid;
  wire [38:0] if2_ibuf_io_enq_3_bits_pc;
  wire [15:0] if2_ibuf_io_enq_3_bits_instr;
  wire  if2_ibuf_io_deq_0_ready;
  wire  if2_ibuf_io_deq_0_valid;
  wire [38:0] if2_ibuf_io_deq_0_bits_pc;
  wire [15:0] if2_ibuf_io_deq_0_bits_instr;
  wire  if2_ibuf_io_deq_0_bits_isRedirect;
  wire  if2_ibuf_io_deq_1_ready;
  wire  if2_ibuf_io_deq_1_valid;
  wire [38:0] if2_ibuf_io_deq_1_bits_pc;
  wire [15:0] if2_ibuf_io_deq_1_bits_instr;
  wire  if2_ibuf_io_deq_1_bits_isFault;
  wire  if2_ibuf_io_deq_1_bits_isRedirect;
  wire  if2_ibuf_io_deq_2_ready;
  wire  if2_ibuf_io_deq_2_valid;
  wire [38:0] if2_ibuf_io_deq_2_bits_pc;
  wire [15:0] if2_ibuf_io_deq_2_bits_instr;
  wire  if2_ibuf_io_deq_2_bits_isFault;
  wire  if2_ibuf_io_deq_2_bits_isRedirect;
  wire  if2_ibuf_io_deq_3_ready;
  wire  if2_ibuf_io_deq_3_valid;
  wire [38:0] if2_ibuf_io_deq_3_bits_pc;
  wire [15:0] if2_ibuf_io_deq_3_bits_instr;
  wire  if2_ibuf_io_deq_3_bits_isFault;
  wire  if2_ibuf_io_deq_3_bits_isRedirect;
  wire  if2_ibuf_io_flush;
  reg [38:0] if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 57:20]
  reg [15:0] if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_0_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if2_ibuf_buf_1_pc; // @[MultiPortFifo.scala 57:20]
  reg [15:0] if2_ibuf_buf_1_instr; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_1_isFault; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_1_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if2_ibuf_buf_2_pc; // @[MultiPortFifo.scala 57:20]
  reg [15:0] if2_ibuf_buf_2_instr; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_2_isFault; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_2_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if2_ibuf_buf_3_pc; // @[MultiPortFifo.scala 57:20]
  reg [15:0] if2_ibuf_buf_3_instr; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_3_isFault; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_3_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if2_ibuf_buf_4_pc; // @[MultiPortFifo.scala 57:20]
  reg [15:0] if2_ibuf_buf_4_instr; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_4_isFault; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_4_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if2_ibuf_buf_5_pc; // @[MultiPortFifo.scala 57:20]
  reg [15:0] if2_ibuf_buf_5_instr; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_5_isFault; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_5_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if2_ibuf_buf_6_pc; // @[MultiPortFifo.scala 57:20]
  reg [15:0] if2_ibuf_buf_6_instr; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_6_isFault; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_6_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if2_ibuf_buf_7_pc; // @[MultiPortFifo.scala 57:20]
  reg [15:0] if2_ibuf_buf_7_instr; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_7_isFault; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_7_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg  if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  if2_ibuf_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  if2_ibuf_buf_valid_2; // @[MultiPortFifo.scala 58:30]
  reg  if2_ibuf_buf_valid_3; // @[MultiPortFifo.scala 58:30]
  reg  if2_ibuf_buf_valid_4; // @[MultiPortFifo.scala 58:30]
  reg  if2_ibuf_buf_valid_5; // @[MultiPortFifo.scala 58:30]
  reg  if2_ibuf_buf_valid_6; // @[MultiPortFifo.scala 58:30]
  reg  if2_ibuf_buf_valid_7; // @[MultiPortFifo.scala 58:30]
  reg [2:0] if2_ibuf_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg [2:0] if2_ibuf_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [3:0] if2_ibuf__io_enq_0_ready_T = {{1'd0}, if2_ibuf_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire [2:0] if2_ibuf__io_enq_0_ready_T_1 = if2_ibuf__io_enq_0_ready_T[2:0]; // @[MultiPortFifo.scala 64:78]
  wire  if2_ibuf__GEN_1 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_valid_1 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_2 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_valid_2 : if2_ibuf__GEN_1; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_3 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_valid_3 : if2_ibuf__GEN_2; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_4 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_valid_4 : if2_ibuf__GEN_3; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_5 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_valid_5 : if2_ibuf__GEN_4; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_6 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_valid_6 : if2_ibuf__GEN_5; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_7 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_valid_7 : if2_ibuf__GEN_6; // @[MultiPortFifo.scala 64:{94,94}]
  wire [2:0] if2_ibuf__io_enq_1_ready_T_1 = if2_ibuf_wr_ptr + 3'h1; // @[MultiPortFifo.scala 64:78]
  wire  if2_ibuf__GEN_9 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_valid_1 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_10 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_valid_2 : if2_ibuf__GEN_9; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_11 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_valid_3 : if2_ibuf__GEN_10; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_12 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_valid_4 : if2_ibuf__GEN_11; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_13 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_valid_5 : if2_ibuf__GEN_12; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_14 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_valid_6 : if2_ibuf__GEN_13; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_15 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_valid_7 : if2_ibuf__GEN_14; // @[MultiPortFifo.scala 64:{94,94}]
  wire [2:0] if2_ibuf__io_enq_2_ready_T_1 = if2_ibuf_wr_ptr + 3'h2; // @[MultiPortFifo.scala 64:78]
  wire  if2_ibuf__GEN_17 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_valid_1 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_18 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_valid_2 : if2_ibuf__GEN_17; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_19 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_valid_3 : if2_ibuf__GEN_18; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_20 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_valid_4 : if2_ibuf__GEN_19; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_21 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_valid_5 : if2_ibuf__GEN_20; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_22 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_valid_6 : if2_ibuf__GEN_21; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_23 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_valid_7 : if2_ibuf__GEN_22; // @[MultiPortFifo.scala 64:{94,94}]
  wire [2:0] if2_ibuf__io_enq_3_ready_T_1 = if2_ibuf_wr_ptr + 3'h3; // @[MultiPortFifo.scala 64:78]
  wire  if2_ibuf__GEN_25 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_valid_1 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_26 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_valid_2 : if2_ibuf__GEN_25; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_27 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_valid_3 : if2_ibuf__GEN_26; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_28 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_valid_4 : if2_ibuf__GEN_27; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_29 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_valid_5 : if2_ibuf__GEN_28; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_30 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_valid_6 : if2_ibuf__GEN_29; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if2_ibuf__GEN_31 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_valid_7 : if2_ibuf__GEN_30; // @[MultiPortFifo.scala 64:{94,94}]
  wire [3:0] if2_ibuf__io_deq_0_valid_T = {{1'd0}, if2_ibuf_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire [2:0] if2_ibuf__io_deq_0_valid_T_1 = if2_ibuf__io_deq_0_valid_T[2:0]; // @[MultiPortFifo.scala 65:78]
  wire  if2_ibuf__GEN_33 = 3'h1 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_valid_1 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_34 = 3'h2 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_valid_2 : if2_ibuf__GEN_33; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_35 = 3'h3 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_valid_3 : if2_ibuf__GEN_34; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_36 = 3'h4 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_valid_4 : if2_ibuf__GEN_35; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_37 = 3'h5 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_valid_5 : if2_ibuf__GEN_36; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_38 = 3'h6 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_valid_6 : if2_ibuf__GEN_37; // @[MultiPortFifo.scala 65:{94,94}]
  wire [2:0] if2_ibuf__io_deq_1_valid_T_1 = if2_ibuf_rd_ptr + 3'h1; // @[MultiPortFifo.scala 65:78]
  wire  if2_ibuf__GEN_41 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_valid_1 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_42 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_valid_2 : if2_ibuf__GEN_41; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_43 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_valid_3 : if2_ibuf__GEN_42; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_44 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_valid_4 : if2_ibuf__GEN_43; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_45 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_valid_5 : if2_ibuf__GEN_44; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_46 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_valid_6 : if2_ibuf__GEN_45; // @[MultiPortFifo.scala 65:{94,94}]
  wire [2:0] if2_ibuf__io_deq_2_valid_T_1 = if2_ibuf_rd_ptr + 3'h2; // @[MultiPortFifo.scala 65:78]
  wire  if2_ibuf__GEN_49 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_valid_1 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_50 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_valid_2 : if2_ibuf__GEN_49; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_51 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_valid_3 : if2_ibuf__GEN_50; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_52 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_valid_4 : if2_ibuf__GEN_51; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_53 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_valid_5 : if2_ibuf__GEN_52; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_54 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_valid_6 : if2_ibuf__GEN_53; // @[MultiPortFifo.scala 65:{94,94}]
  wire [2:0] if2_ibuf__io_deq_3_valid_T_1 = if2_ibuf_rd_ptr + 3'h3; // @[MultiPortFifo.scala 65:78]
  wire  if2_ibuf__GEN_57 = 3'h1 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_valid_1 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_58 = 3'h2 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_valid_2 : if2_ibuf__GEN_57; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_59 = 3'h3 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_valid_3 : if2_ibuf__GEN_58; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_60 = 3'h4 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_valid_4 : if2_ibuf__GEN_59; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_61 = 3'h5 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_valid_5 : if2_ibuf__GEN_60; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__GEN_62 = 3'h6 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_valid_6 : if2_ibuf__GEN_61; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if2_ibuf__T = if2_ibuf_io_enq_0_ready & if2_ibuf_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_0 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_64 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 | if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_1 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_65 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 | if2_ibuf_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_2 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_66 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 | if2_ibuf_buf_valid_2; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_3 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_67 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 | if2_ibuf_buf_valid_3; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_4 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_68 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 | if2_ibuf_buf_valid_4; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_5 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_69 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 | if2_ibuf_buf_valid_5; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_6 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_70 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 | if2_ibuf_buf_valid_6; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  _GEN_7 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_71 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 | if2_ibuf_buf_valid_7; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if2_ibuf__GEN_72 = if2_ibuf__T ? if2_ibuf__GEN_64 : if2_ibuf_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if2_ibuf__GEN_73 = if2_ibuf__T ? if2_ibuf__GEN_65 : if2_ibuf_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if2_ibuf__GEN_74 = if2_ibuf__T ? if2_ibuf__GEN_66 : if2_ibuf_buf_valid_2; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if2_ibuf__GEN_75 = if2_ibuf__T ? if2_ibuf__GEN_67 : if2_ibuf_buf_valid_3; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if2_ibuf__GEN_76 = if2_ibuf__T ? if2_ibuf__GEN_68 : if2_ibuf_buf_valid_4; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if2_ibuf__GEN_77 = if2_ibuf__T ? if2_ibuf__GEN_69 : if2_ibuf_buf_valid_5; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if2_ibuf__GEN_78 = if2_ibuf__T ? if2_ibuf__GEN_70 : if2_ibuf_buf_valid_6; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if2_ibuf__GEN_79 = if2_ibuf__T ? if2_ibuf__GEN_71 : if2_ibuf_buf_valid_7; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if2_ibuf__T_1 = if2_ibuf_io_deq_0_ready & if2_ibuf_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if2_ibuf__GEN_80 = 3'h0 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_72; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_81 = 3'h1 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_73; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_82 = 3'h2 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_74; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_83 = 3'h3 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_75; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_84 = 3'h4 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_76; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_85 = 3'h5 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_77; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_86 = 3'h6 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_78; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_87 = 3'h7 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_79; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_88 = if2_ibuf__T_1 ? if2_ibuf__GEN_80 : if2_ibuf__GEN_72; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_89 = if2_ibuf__T_1 ? if2_ibuf__GEN_81 : if2_ibuf__GEN_73; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_90 = if2_ibuf__T_1 ? if2_ibuf__GEN_82 : if2_ibuf__GEN_74; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_91 = if2_ibuf__T_1 ? if2_ibuf__GEN_83 : if2_ibuf__GEN_75; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_92 = if2_ibuf__T_1 ? if2_ibuf__GEN_84 : if2_ibuf__GEN_76; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_93 = if2_ibuf__T_1 ? if2_ibuf__GEN_85 : if2_ibuf__GEN_77; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_94 = if2_ibuf__T_1 ? if2_ibuf__GEN_86 : if2_ibuf__GEN_78; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_95 = if2_ibuf__T_1 ? if2_ibuf__GEN_87 : if2_ibuf__GEN_79; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_101 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_102 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_103 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_1_isFault : if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_104 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_1_isRedirect : if2_ibuf_buf_0_isRedirect
    ; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_106 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_2_pc : if2_ibuf__GEN_101; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_107 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_2_instr : if2_ibuf__GEN_102; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_108 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_2_isFault : if2_ibuf__GEN_103; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_109 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_2_isRedirect : if2_ibuf__GEN_104; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_111 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_3_pc : if2_ibuf__GEN_106; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_112 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_3_instr : if2_ibuf__GEN_107; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_113 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_3_isFault : if2_ibuf__GEN_108; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_114 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_3_isRedirect : if2_ibuf__GEN_109; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_116 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_4_pc : if2_ibuf__GEN_111; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_117 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_4_instr : if2_ibuf__GEN_112; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_118 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_4_isFault : if2_ibuf__GEN_113; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_119 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_4_isRedirect : if2_ibuf__GEN_114; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_121 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_5_pc : if2_ibuf__GEN_116; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_122 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_5_instr : if2_ibuf__GEN_117; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_123 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_5_isFault : if2_ibuf__GEN_118; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_124 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_5_isRedirect : if2_ibuf__GEN_119; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_126 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_6_pc : if2_ibuf__GEN_121; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_127 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_6_instr : if2_ibuf__GEN_122; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_128 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_6_isFault : if2_ibuf__GEN_123; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_129 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_6_isRedirect : if2_ibuf__GEN_124; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_131 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_7_pc : if2_ibuf__GEN_126; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_132 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_7_instr : if2_ibuf__GEN_127; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_133 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_7_isFault : if2_ibuf__GEN_128; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_134 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf_buf_7_isRedirect : if2_ibuf__GEN_129; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__buf_T_1_pc = if2_ibuf__T ? if2_ibuf_io_enq_0_bits_pc : if2_ibuf__GEN_131; // @[MultiPortFifo.scala 101:33]
  wire [15:0] if2_ibuf__buf_T_1_instr = if2_ibuf__T ? if2_ibuf_io_enq_0_bits_instr : if2_ibuf__GEN_132; // @[MultiPortFifo.scala 101:33]
  wire  if2_ibuf__buf_T_1_isFault = if2_ibuf__T ? if2_ibuf_io_enq_0_bits_isFault : if2_ibuf__GEN_133; // @[MultiPortFifo.scala 101:33]
  wire  if2_ibuf__buf_T_1_isRedirect = if2_ibuf__T ? 1'h0 : if2_ibuf__GEN_134; // @[MultiPortFifo.scala 101:33]
  wire [38:0] if2_ibuf__GEN_136 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if2_ibuf__GEN_137 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf_buf_1_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if2_ibuf__GEN_138 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf_buf_2_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if2_ibuf__GEN_139 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf_buf_3_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if2_ibuf__GEN_140 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf_buf_4_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if2_ibuf__GEN_141 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf_buf_5_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if2_ibuf__GEN_142 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf_buf_6_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if2_ibuf__GEN_143 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf_buf_7_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [15:0] if2_ibuf__GEN_144 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [15:0] if2_ibuf__GEN_145 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf_buf_1_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [15:0] if2_ibuf__GEN_146 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf_buf_2_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [15:0] if2_ibuf__GEN_147 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf_buf_3_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [15:0] if2_ibuf__GEN_148 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf_buf_4_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [15:0] if2_ibuf__GEN_149 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf_buf_5_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [15:0] if2_ibuf__GEN_150 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf_buf_6_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [15:0] if2_ibuf__GEN_151 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf_buf_7_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_152 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_153 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf_buf_1_isFault; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_154 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf_buf_2_isFault; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_155 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf_buf_3_isFault; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_156 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf_buf_4_isFault; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_157 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf_buf_5_isFault; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_158 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf_buf_6_isFault; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_159 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf_buf_7_isFault; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_160 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect :
    if2_ibuf_buf_0_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_161 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect :
    if2_ibuf_buf_1_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_162 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect :
    if2_ibuf_buf_2_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_163 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect :
    if2_ibuf_buf_3_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_164 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect :
    if2_ibuf_buf_4_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_165 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect :
    if2_ibuf_buf_5_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_166 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect :
    if2_ibuf_buf_6_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_167 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect :
    if2_ibuf_buf_7_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if2_ibuf__GEN_176 = _GEN_0 | if2_ibuf__GEN_88; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_177 = _GEN_1 | if2_ibuf__GEN_89; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_178 = _GEN_2 | if2_ibuf__GEN_90; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_179 = _GEN_3 | if2_ibuf__GEN_91; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_180 = _GEN_4 | if2_ibuf__GEN_92; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_181 = _GEN_5 | if2_ibuf__GEN_93; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_182 = _GEN_6 | if2_ibuf__GEN_94; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_183 = _GEN_7 | if2_ibuf__GEN_95; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_184 = if2_ibuf__T ? if2_ibuf__GEN_176 : if2_ibuf__GEN_88; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_185 = if2_ibuf__T ? if2_ibuf__GEN_177 : if2_ibuf__GEN_89; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_186 = if2_ibuf__T ? if2_ibuf__GEN_178 : if2_ibuf__GEN_90; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_187 = if2_ibuf__T ? if2_ibuf__GEN_179 : if2_ibuf__GEN_91; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_188 = if2_ibuf__T ? if2_ibuf__GEN_180 : if2_ibuf__GEN_92; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_189 = if2_ibuf__T ? if2_ibuf__GEN_181 : if2_ibuf__GEN_93; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_190 = if2_ibuf__T ? if2_ibuf__GEN_182 : if2_ibuf__GEN_94; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_191 = if2_ibuf__T ? if2_ibuf__GEN_183 : if2_ibuf__GEN_95; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__T_3 = if2_ibuf_io_deq_1_ready & if2_ibuf_io_deq_1_valid; // @[Decoupled.scala 52:35]
  wire  if2_ibuf__GEN_192 = 3'h0 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_184; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_193 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_185; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_194 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_186; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_195 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_187; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_196 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_188; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_197 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_189; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_198 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_190; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_199 = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_191; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_200 = if2_ibuf__T_3 ? if2_ibuf__GEN_192 : if2_ibuf__GEN_184; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_201 = if2_ibuf__T_3 ? if2_ibuf__GEN_193 : if2_ibuf__GEN_185; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_202 = if2_ibuf__T_3 ? if2_ibuf__GEN_194 : if2_ibuf__GEN_186; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_203 = if2_ibuf__T_3 ? if2_ibuf__GEN_195 : if2_ibuf__GEN_187; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_204 = if2_ibuf__T_3 ? if2_ibuf__GEN_196 : if2_ibuf__GEN_188; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_205 = if2_ibuf__T_3 ? if2_ibuf__GEN_197 : if2_ibuf__GEN_189; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_206 = if2_ibuf__T_3 ? if2_ibuf__GEN_198 : if2_ibuf__GEN_190; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_207 = if2_ibuf__T_3 ? if2_ibuf__GEN_199 : if2_ibuf__GEN_191; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_248 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_136; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_249 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_137; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_250 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_138; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_251 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_139; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_252 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_140; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_253 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_141; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_254 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_142; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_255 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_143; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_256 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_144; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_257 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_145; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_258 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_146; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_259 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_147; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_260 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_148; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_261 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_149; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_262 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_150; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_263 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_151; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_264 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_152; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_265 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_153; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_266 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_154; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_267 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_155; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_268 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_156; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_269 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_157; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_270 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_158; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_271 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_159; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_272 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_160; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_273 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_161; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_274 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_162; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_275 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_163; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_276 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_164; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_277 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_165; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_278 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_166; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_279 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_167; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_288 = _GEN_0 | if2_ibuf__GEN_200; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_289 = _GEN_1 | if2_ibuf__GEN_201; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_290 = _GEN_2 | if2_ibuf__GEN_202; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_291 = _GEN_3 | if2_ibuf__GEN_203; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_292 = _GEN_4 | if2_ibuf__GEN_204; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_293 = _GEN_5 | if2_ibuf__GEN_205; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_294 = _GEN_6 | if2_ibuf__GEN_206; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_295 = _GEN_7 | if2_ibuf__GEN_207; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_296 = if2_ibuf__T ? if2_ibuf__GEN_288 : if2_ibuf__GEN_200; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_297 = if2_ibuf__T ? if2_ibuf__GEN_289 : if2_ibuf__GEN_201; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_298 = if2_ibuf__T ? if2_ibuf__GEN_290 : if2_ibuf__GEN_202; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_299 = if2_ibuf__T ? if2_ibuf__GEN_291 : if2_ibuf__GEN_203; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_300 = if2_ibuf__T ? if2_ibuf__GEN_292 : if2_ibuf__GEN_204; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_301 = if2_ibuf__T ? if2_ibuf__GEN_293 : if2_ibuf__GEN_205; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_302 = if2_ibuf__T ? if2_ibuf__GEN_294 : if2_ibuf__GEN_206; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_303 = if2_ibuf__T ? if2_ibuf__GEN_295 : if2_ibuf__GEN_207; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__T_5 = if2_ibuf_io_deq_2_ready & if2_ibuf_io_deq_2_valid; // @[Decoupled.scala 52:35]
  wire  if2_ibuf__GEN_304 = 3'h0 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_296; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_305 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_297; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_306 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_298; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_307 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_299; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_308 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_300; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_309 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_301; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_310 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_302; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_311 = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_303; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_312 = if2_ibuf__T_5 ? if2_ibuf__GEN_304 : if2_ibuf__GEN_296; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_313 = if2_ibuf__T_5 ? if2_ibuf__GEN_305 : if2_ibuf__GEN_297; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_314 = if2_ibuf__T_5 ? if2_ibuf__GEN_306 : if2_ibuf__GEN_298; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_315 = if2_ibuf__T_5 ? if2_ibuf__GEN_307 : if2_ibuf__GEN_299; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_316 = if2_ibuf__T_5 ? if2_ibuf__GEN_308 : if2_ibuf__GEN_300; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_317 = if2_ibuf__T_5 ? if2_ibuf__GEN_309 : if2_ibuf__GEN_301; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_318 = if2_ibuf__T_5 ? if2_ibuf__GEN_310 : if2_ibuf__GEN_302; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_319 = if2_ibuf__T_5 ? if2_ibuf__GEN_311 : if2_ibuf__GEN_303; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_360 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_248; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_361 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_249; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_362 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_250; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_363 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_251; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_364 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_252; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_365 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_253; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_366 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_254; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_367 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_255; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_368 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_256; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_369 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_257; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_370 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_258; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_371 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_259; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_372 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_260; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_373 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_261; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_374 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_262; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_375 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_263; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_376 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_264; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_377 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_265; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_378 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_266; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_379 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_267; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_380 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_268; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_381 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_269; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_382 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_270; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_383 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_271; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_384 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_272; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_385 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_273; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_386 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_274; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_387 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_275; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_388 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_276; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_389 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_277; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_390 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_278; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_391 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_279; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_400 = _GEN_0 | if2_ibuf__GEN_312; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_401 = _GEN_1 | if2_ibuf__GEN_313; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_402 = _GEN_2 | if2_ibuf__GEN_314; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_403 = _GEN_3 | if2_ibuf__GEN_315; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_404 = _GEN_4 | if2_ibuf__GEN_316; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_405 = _GEN_5 | if2_ibuf__GEN_317; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_406 = _GEN_6 | if2_ibuf__GEN_318; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_407 = _GEN_7 | if2_ibuf__GEN_319; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_408 = if2_ibuf__T ? if2_ibuf__GEN_400 : if2_ibuf__GEN_312; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_409 = if2_ibuf__T ? if2_ibuf__GEN_401 : if2_ibuf__GEN_313; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_410 = if2_ibuf__T ? if2_ibuf__GEN_402 : if2_ibuf__GEN_314; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_411 = if2_ibuf__T ? if2_ibuf__GEN_403 : if2_ibuf__GEN_315; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_412 = if2_ibuf__T ? if2_ibuf__GEN_404 : if2_ibuf__GEN_316; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_413 = if2_ibuf__T ? if2_ibuf__GEN_405 : if2_ibuf__GEN_317; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_414 = if2_ibuf__T ? if2_ibuf__GEN_406 : if2_ibuf__GEN_318; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_415 = if2_ibuf__T ? if2_ibuf__GEN_407 : if2_ibuf__GEN_319; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__T_7 = if2_ibuf_io_deq_3_ready & if2_ibuf_io_deq_3_valid; // @[Decoupled.scala 52:35]
  wire  if2_ibuf__GEN_416 = 3'h0 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_408; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_417 = 3'h1 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_409; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_418 = 3'h2 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_410; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_419 = 3'h3 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_411; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_420 = 3'h4 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_412; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_421 = 3'h5 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_413; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_422 = 3'h6 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_414; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_423 = 3'h7 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_415; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_424 = if2_ibuf__T_7 ? if2_ibuf__GEN_416 : if2_ibuf__GEN_408; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_425 = if2_ibuf__T_7 ? if2_ibuf__GEN_417 : if2_ibuf__GEN_409; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_426 = if2_ibuf__T_7 ? if2_ibuf__GEN_418 : if2_ibuf__GEN_410; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_427 = if2_ibuf__T_7 ? if2_ibuf__GEN_419 : if2_ibuf__GEN_411; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_428 = if2_ibuf__T_7 ? if2_ibuf__GEN_420 : if2_ibuf__GEN_412; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_429 = if2_ibuf__T_7 ? if2_ibuf__GEN_421 : if2_ibuf__GEN_413; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_430 = if2_ibuf__T_7 ? if2_ibuf__GEN_422 : if2_ibuf__GEN_414; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_431 = if2_ibuf__T_7 ? if2_ibuf__GEN_423 : if2_ibuf__GEN_415; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_472 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_360; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_473 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_361; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_474 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_362; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_475 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_363; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_476 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_364; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_477 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_365; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_478 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_366; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_479 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_pc : if2_ibuf__GEN_367; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_480 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_368; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_481 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_369; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_482 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_370; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_483 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_371; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_484 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_372; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_485 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_373; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_486 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_374; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_487 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_instr : if2_ibuf__GEN_375; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_488 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_376; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_489 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_377; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_490 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_378; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_491 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_379; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_492 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_380; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_493 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_381; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_494 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_382; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_495 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isFault : if2_ibuf__GEN_383; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_496 = 3'h0 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_384; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_497 = 3'h1 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_385; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_498 = 3'h2 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_386; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_499 = 3'h3 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_387; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_500 = 3'h4 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_388; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_501 = 3'h5 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_389; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_502 = 3'h6 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_390; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_503 = 3'h7 == if2_ibuf__io_enq_0_ready_T_1 ? if2_ibuf__buf_T_1_isRedirect : if2_ibuf__GEN_391; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__T_8 = if2_ibuf_io_enq_1_ready & if2_ibuf_io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  if2_ibuf__GEN_512 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_424; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_513 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_425; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_514 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_426; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_515 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_427; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_516 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_428; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_517 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_429; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_518 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_430; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_519 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_431; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_520 = if2_ibuf__T_8 ? if2_ibuf__GEN_512 : if2_ibuf__GEN_424; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_521 = if2_ibuf__T_8 ? if2_ibuf__GEN_513 : if2_ibuf__GEN_425; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_522 = if2_ibuf__T_8 ? if2_ibuf__GEN_514 : if2_ibuf__GEN_426; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_523 = if2_ibuf__T_8 ? if2_ibuf__GEN_515 : if2_ibuf__GEN_427; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_524 = if2_ibuf__T_8 ? if2_ibuf__GEN_516 : if2_ibuf__GEN_428; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_525 = if2_ibuf__T_8 ? if2_ibuf__GEN_517 : if2_ibuf__GEN_429; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_526 = if2_ibuf__T_8 ? if2_ibuf__GEN_518 : if2_ibuf__GEN_430; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_527 = if2_ibuf__T_8 ? if2_ibuf__GEN_519 : if2_ibuf__GEN_431; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_528 = 3'h0 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_520; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_529 = 3'h1 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_521; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_530 = 3'h2 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_522; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_531 = 3'h3 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_523; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_532 = 3'h4 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_524; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_533 = 3'h5 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_525; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_534 = 3'h6 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_526; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_535 = 3'h7 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_527; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_536 = if2_ibuf__T_1 ? if2_ibuf__GEN_528 : if2_ibuf__GEN_520; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_537 = if2_ibuf__T_1 ? if2_ibuf__GEN_529 : if2_ibuf__GEN_521; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_538 = if2_ibuf__T_1 ? if2_ibuf__GEN_530 : if2_ibuf__GEN_522; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_539 = if2_ibuf__T_1 ? if2_ibuf__GEN_531 : if2_ibuf__GEN_523; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_540 = if2_ibuf__T_1 ? if2_ibuf__GEN_532 : if2_ibuf__GEN_524; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_541 = if2_ibuf__T_1 ? if2_ibuf__GEN_533 : if2_ibuf__GEN_525; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_542 = if2_ibuf__T_1 ? if2_ibuf__GEN_534 : if2_ibuf__GEN_526; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_543 = if2_ibuf__T_1 ? if2_ibuf__GEN_535 : if2_ibuf__GEN_527; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_549 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_550 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_551 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_1_isFault : if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_552 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_1_isRedirect : if2_ibuf_buf_0_isRedirect
    ; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_554 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_2_pc : if2_ibuf__GEN_549; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_555 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_2_instr : if2_ibuf__GEN_550; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_556 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_2_isFault : if2_ibuf__GEN_551; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_557 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_2_isRedirect : if2_ibuf__GEN_552; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_559 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_3_pc : if2_ibuf__GEN_554; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_560 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_3_instr : if2_ibuf__GEN_555; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_561 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_3_isFault : if2_ibuf__GEN_556; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_562 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_3_isRedirect : if2_ibuf__GEN_557; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_564 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_4_pc : if2_ibuf__GEN_559; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_565 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_4_instr : if2_ibuf__GEN_560; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_566 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_4_isFault : if2_ibuf__GEN_561; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_567 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_4_isRedirect : if2_ibuf__GEN_562; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_569 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_5_pc : if2_ibuf__GEN_564; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_570 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_5_instr : if2_ibuf__GEN_565; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_571 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_5_isFault : if2_ibuf__GEN_566; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_572 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_5_isRedirect : if2_ibuf__GEN_567; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_574 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_6_pc : if2_ibuf__GEN_569; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_575 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_6_instr : if2_ibuf__GEN_570; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_576 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_6_isFault : if2_ibuf__GEN_571; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_577 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_6_isRedirect : if2_ibuf__GEN_572; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_579 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_7_pc : if2_ibuf__GEN_574; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_580 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_7_instr : if2_ibuf__GEN_575; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_581 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_7_isFault : if2_ibuf__GEN_576; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_582 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf_buf_7_isRedirect : if2_ibuf__GEN_577; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__buf_T_9_pc = if2_ibuf__T_8 ? if2_ibuf_io_enq_1_bits_pc : if2_ibuf__GEN_579; // @[MultiPortFifo.scala 101:33]
  wire [15:0] if2_ibuf__buf_T_9_instr = if2_ibuf__T_8 ? if2_ibuf_io_enq_1_bits_instr : if2_ibuf__GEN_580; // @[MultiPortFifo.scala 101:33]
  wire  if2_ibuf__buf_T_9_isFault = if2_ibuf__T_8 ? 1'h0 : if2_ibuf__GEN_581; // @[MultiPortFifo.scala 101:33]
  wire  if2_ibuf__buf_T_9_isRedirect = if2_ibuf__T_8 ? 1'h0 : if2_ibuf__GEN_582; // @[MultiPortFifo.scala 101:33]
  wire [38:0] if2_ibuf__GEN_584 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_472; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_585 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_473; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_586 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_474; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_587 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_475; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_588 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_476; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_589 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_477; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_590 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_478; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_591 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_479; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_592 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_480; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_593 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_481; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_594 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_482; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_595 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_483; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_596 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_484; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_597 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_485; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_598 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_486; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_599 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_487; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_600 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_488; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_601 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_489; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_602 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_490; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_603 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_491; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_604 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_492; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_605 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_493; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_606 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_494; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_607 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_495; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_608 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_496; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_609 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_497; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_610 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_498; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_611 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_499; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_612 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_500; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_613 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_501; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_614 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_502; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_615 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_503; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_624 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_536; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_625 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_537; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_626 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_538; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_627 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_539; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_628 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_540; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_629 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_541; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_630 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_542; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_631 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_543; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_632 = if2_ibuf__T_8 ? if2_ibuf__GEN_624 : if2_ibuf__GEN_536; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_633 = if2_ibuf__T_8 ? if2_ibuf__GEN_625 : if2_ibuf__GEN_537; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_634 = if2_ibuf__T_8 ? if2_ibuf__GEN_626 : if2_ibuf__GEN_538; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_635 = if2_ibuf__T_8 ? if2_ibuf__GEN_627 : if2_ibuf__GEN_539; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_636 = if2_ibuf__T_8 ? if2_ibuf__GEN_628 : if2_ibuf__GEN_540; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_637 = if2_ibuf__T_8 ? if2_ibuf__GEN_629 : if2_ibuf__GEN_541; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_638 = if2_ibuf__T_8 ? if2_ibuf__GEN_630 : if2_ibuf__GEN_542; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_639 = if2_ibuf__T_8 ? if2_ibuf__GEN_631 : if2_ibuf__GEN_543; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_640 = 3'h0 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_632; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_641 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_633; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_642 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_634; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_643 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_635; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_644 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_636; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_645 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_637; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_646 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_638; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_647 = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_639; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_648 = if2_ibuf__T_3 ? if2_ibuf__GEN_640 : if2_ibuf__GEN_632; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_649 = if2_ibuf__T_3 ? if2_ibuf__GEN_641 : if2_ibuf__GEN_633; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_650 = if2_ibuf__T_3 ? if2_ibuf__GEN_642 : if2_ibuf__GEN_634; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_651 = if2_ibuf__T_3 ? if2_ibuf__GEN_643 : if2_ibuf__GEN_635; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_652 = if2_ibuf__T_3 ? if2_ibuf__GEN_644 : if2_ibuf__GEN_636; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_653 = if2_ibuf__T_3 ? if2_ibuf__GEN_645 : if2_ibuf__GEN_637; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_654 = if2_ibuf__T_3 ? if2_ibuf__GEN_646 : if2_ibuf__GEN_638; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_655 = if2_ibuf__T_3 ? if2_ibuf__GEN_647 : if2_ibuf__GEN_639; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_696 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_584; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_697 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_585; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_698 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_586; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_699 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_587; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_700 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_588; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_701 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_589; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_702 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_590; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_703 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_591; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_704 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_592; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_705 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_593; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_706 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_594; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_707 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_595; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_708 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_596; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_709 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_597; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_710 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_598; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_711 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_599; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_712 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_600; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_713 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_601; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_714 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_602; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_715 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_603; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_716 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_604; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_717 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_605; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_718 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_606; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_719 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_607; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_720 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_608; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_721 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_609; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_722 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_610; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_723 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_611; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_724 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_612; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_725 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_613; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_726 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_614; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_727 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_615; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_736 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_648; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_737 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_649; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_738 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_650; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_739 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_651; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_740 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_652; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_741 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_653; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_742 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_654; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_743 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_655; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_744 = if2_ibuf__T_8 ? if2_ibuf__GEN_736 : if2_ibuf__GEN_648; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_745 = if2_ibuf__T_8 ? if2_ibuf__GEN_737 : if2_ibuf__GEN_649; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_746 = if2_ibuf__T_8 ? if2_ibuf__GEN_738 : if2_ibuf__GEN_650; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_747 = if2_ibuf__T_8 ? if2_ibuf__GEN_739 : if2_ibuf__GEN_651; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_748 = if2_ibuf__T_8 ? if2_ibuf__GEN_740 : if2_ibuf__GEN_652; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_749 = if2_ibuf__T_8 ? if2_ibuf__GEN_741 : if2_ibuf__GEN_653; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_750 = if2_ibuf__T_8 ? if2_ibuf__GEN_742 : if2_ibuf__GEN_654; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_751 = if2_ibuf__T_8 ? if2_ibuf__GEN_743 : if2_ibuf__GEN_655; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_752 = 3'h0 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_744; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_753 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_745; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_754 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_746; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_755 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_747; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_756 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_748; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_757 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_749; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_758 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_750; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_759 = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_751; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_760 = if2_ibuf__T_5 ? if2_ibuf__GEN_752 : if2_ibuf__GEN_744; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_761 = if2_ibuf__T_5 ? if2_ibuf__GEN_753 : if2_ibuf__GEN_745; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_762 = if2_ibuf__T_5 ? if2_ibuf__GEN_754 : if2_ibuf__GEN_746; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_763 = if2_ibuf__T_5 ? if2_ibuf__GEN_755 : if2_ibuf__GEN_747; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_764 = if2_ibuf__T_5 ? if2_ibuf__GEN_756 : if2_ibuf__GEN_748; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_765 = if2_ibuf__T_5 ? if2_ibuf__GEN_757 : if2_ibuf__GEN_749; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_766 = if2_ibuf__T_5 ? if2_ibuf__GEN_758 : if2_ibuf__GEN_750; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_767 = if2_ibuf__T_5 ? if2_ibuf__GEN_759 : if2_ibuf__GEN_751; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_808 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_696; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_809 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_697; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_810 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_698; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_811 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_699; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_812 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_700; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_813 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_701; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_814 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_702; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_815 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_703; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_816 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_704; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_817 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_705; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_818 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_706; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_819 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_707; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_820 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_708; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_821 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_709; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_822 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_710; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_823 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_711; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_824 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_712; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_825 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_713; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_826 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_714; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_827 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_715; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_828 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_716; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_829 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_717; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_830 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_718; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_831 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_719; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_832 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_720; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_833 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_721; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_834 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_722; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_835 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_723; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_836 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_724; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_837 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_725; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_838 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_726; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_839 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_727; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_848 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_760; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_849 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_761; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_850 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_762; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_851 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_763; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_852 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_764; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_853 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_765; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_854 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_766; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_855 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 | if2_ibuf__GEN_767; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_856 = if2_ibuf__T_8 ? if2_ibuf__GEN_848 : if2_ibuf__GEN_760; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_857 = if2_ibuf__T_8 ? if2_ibuf__GEN_849 : if2_ibuf__GEN_761; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_858 = if2_ibuf__T_8 ? if2_ibuf__GEN_850 : if2_ibuf__GEN_762; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_859 = if2_ibuf__T_8 ? if2_ibuf__GEN_851 : if2_ibuf__GEN_763; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_860 = if2_ibuf__T_8 ? if2_ibuf__GEN_852 : if2_ibuf__GEN_764; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_861 = if2_ibuf__T_8 ? if2_ibuf__GEN_853 : if2_ibuf__GEN_765; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_862 = if2_ibuf__T_8 ? if2_ibuf__GEN_854 : if2_ibuf__GEN_766; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_863 = if2_ibuf__T_8 ? if2_ibuf__GEN_855 : if2_ibuf__GEN_767; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_864 = 3'h0 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_856; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_865 = 3'h1 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_857; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_866 = 3'h2 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_858; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_867 = 3'h3 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_859; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_868 = 3'h4 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_860; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_869 = 3'h5 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_861; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_870 = 3'h6 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_862; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_871 = 3'h7 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_863; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_872 = if2_ibuf__T_7 ? if2_ibuf__GEN_864 : if2_ibuf__GEN_856; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_873 = if2_ibuf__T_7 ? if2_ibuf__GEN_865 : if2_ibuf__GEN_857; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_874 = if2_ibuf__T_7 ? if2_ibuf__GEN_866 : if2_ibuf__GEN_858; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_875 = if2_ibuf__T_7 ? if2_ibuf__GEN_867 : if2_ibuf__GEN_859; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_876 = if2_ibuf__T_7 ? if2_ibuf__GEN_868 : if2_ibuf__GEN_860; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_877 = if2_ibuf__T_7 ? if2_ibuf__GEN_869 : if2_ibuf__GEN_861; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_878 = if2_ibuf__T_7 ? if2_ibuf__GEN_870 : if2_ibuf__GEN_862; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_879 = if2_ibuf__T_7 ? if2_ibuf__GEN_871 : if2_ibuf__GEN_863; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_920 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_808; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_921 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_809; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_922 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_810; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_923 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_811; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_924 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_812; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_925 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_813; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_926 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_814; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_927 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_pc : if2_ibuf__GEN_815; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_928 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_816; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_929 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_817; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_930 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_818; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_931 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_819; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_932 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_820; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_933 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_821; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_934 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_822; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_935 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_instr : if2_ibuf__GEN_823; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_936 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_824; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_937 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_825; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_938 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_826; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_939 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_827; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_940 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_828; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_941 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_829; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_942 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_830; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_943 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isFault : if2_ibuf__GEN_831; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_944 = 3'h0 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_832; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_945 = 3'h1 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_833; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_946 = 3'h2 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_834; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_947 = 3'h3 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_835; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_948 = 3'h4 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_836; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_949 = 3'h5 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_837; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_950 = 3'h6 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_838; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_951 = 3'h7 == if2_ibuf__io_enq_1_ready_T_1 ? if2_ibuf__buf_T_9_isRedirect : if2_ibuf__GEN_839; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__T_16 = if2_ibuf_io_enq_2_ready & if2_ibuf_io_enq_2_valid; // @[Decoupled.scala 52:35]
  wire  if2_ibuf__GEN_960 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_872; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_961 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_873; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_962 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_874; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_963 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_875; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_964 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_876; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_965 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_877; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_966 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_878; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_967 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_879; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_968 = if2_ibuf__T_16 ? if2_ibuf__GEN_960 : if2_ibuf__GEN_872; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_969 = if2_ibuf__T_16 ? if2_ibuf__GEN_961 : if2_ibuf__GEN_873; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_970 = if2_ibuf__T_16 ? if2_ibuf__GEN_962 : if2_ibuf__GEN_874; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_971 = if2_ibuf__T_16 ? if2_ibuf__GEN_963 : if2_ibuf__GEN_875; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_972 = if2_ibuf__T_16 ? if2_ibuf__GEN_964 : if2_ibuf__GEN_876; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_973 = if2_ibuf__T_16 ? if2_ibuf__GEN_965 : if2_ibuf__GEN_877; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_974 = if2_ibuf__T_16 ? if2_ibuf__GEN_966 : if2_ibuf__GEN_878; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_975 = if2_ibuf__T_16 ? if2_ibuf__GEN_967 : if2_ibuf__GEN_879; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_976 = 3'h0 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_968; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_977 = 3'h1 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_969; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_978 = 3'h2 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_970; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_979 = 3'h3 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_971; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_980 = 3'h4 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_972; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_981 = 3'h5 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_973; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_982 = 3'h6 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_974; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_983 = 3'h7 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_975; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_984 = if2_ibuf__T_1 ? if2_ibuf__GEN_976 : if2_ibuf__GEN_968; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_985 = if2_ibuf__T_1 ? if2_ibuf__GEN_977 : if2_ibuf__GEN_969; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_986 = if2_ibuf__T_1 ? if2_ibuf__GEN_978 : if2_ibuf__GEN_970; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_987 = if2_ibuf__T_1 ? if2_ibuf__GEN_979 : if2_ibuf__GEN_971; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_988 = if2_ibuf__T_1 ? if2_ibuf__GEN_980 : if2_ibuf__GEN_972; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_989 = if2_ibuf__T_1 ? if2_ibuf__GEN_981 : if2_ibuf__GEN_973; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_990 = if2_ibuf__T_1 ? if2_ibuf__GEN_982 : if2_ibuf__GEN_974; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_991 = if2_ibuf__T_1 ? if2_ibuf__GEN_983 : if2_ibuf__GEN_975; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_997 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_998 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_999 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_1_isFault : if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1000 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_1_isRedirect :
    if2_ibuf_buf_0_isRedirect; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1002 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_2_pc : if2_ibuf__GEN_997; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1003 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_2_instr : if2_ibuf__GEN_998; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1004 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_2_isFault : if2_ibuf__GEN_999; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1005 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_2_isRedirect : if2_ibuf__GEN_1000; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1007 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_3_pc : if2_ibuf__GEN_1002; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1008 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_3_instr : if2_ibuf__GEN_1003; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1009 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_3_isFault : if2_ibuf__GEN_1004; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1010 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_3_isRedirect : if2_ibuf__GEN_1005; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1012 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_4_pc : if2_ibuf__GEN_1007; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1013 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_4_instr : if2_ibuf__GEN_1008; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1014 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_4_isFault : if2_ibuf__GEN_1009; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1015 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_4_isRedirect : if2_ibuf__GEN_1010; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1017 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_5_pc : if2_ibuf__GEN_1012; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1018 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_5_instr : if2_ibuf__GEN_1013; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1019 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_5_isFault : if2_ibuf__GEN_1014; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1020 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_5_isRedirect : if2_ibuf__GEN_1015; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1022 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_6_pc : if2_ibuf__GEN_1017; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1023 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_6_instr : if2_ibuf__GEN_1018; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1024 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_6_isFault : if2_ibuf__GEN_1019; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1025 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_6_isRedirect : if2_ibuf__GEN_1020; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1027 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_7_pc : if2_ibuf__GEN_1022; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1028 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_7_instr : if2_ibuf__GEN_1023; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1029 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_7_isFault : if2_ibuf__GEN_1024; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1030 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf_buf_7_isRedirect : if2_ibuf__GEN_1025; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__buf_T_17_pc = if2_ibuf__T_16 ? if2_ibuf_io_enq_2_bits_pc : if2_ibuf__GEN_1027; // @[MultiPortFifo.scala 101:33]
  wire [15:0] if2_ibuf__buf_T_17_instr = if2_ibuf__T_16 ? if2_ibuf_io_enq_2_bits_instr : if2_ibuf__GEN_1028; // @[MultiPortFifo.scala 101:33]
  wire  if2_ibuf__buf_T_17_isFault = if2_ibuf__T_16 ? 1'h0 : if2_ibuf__GEN_1029; // @[MultiPortFifo.scala 101:33]
  wire  if2_ibuf__buf_T_17_isRedirect = if2_ibuf__T_16 ? 1'h0 : if2_ibuf__GEN_1030; // @[MultiPortFifo.scala 101:33]
  wire [38:0] if2_ibuf__GEN_1032 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_920; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1033 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_921; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1034 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_922; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1035 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_923; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1036 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_924; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1037 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_925; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1038 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_926; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1039 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_927; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1040 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_928; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1041 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_929; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1042 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_930; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1043 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_931; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1044 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_932; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1045 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_933; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1046 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_934; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1047 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_935; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1048 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_936; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1049 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_937; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1050 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_938; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1051 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_939; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1052 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_940; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1053 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_941; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1054 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_942; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1055 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_943; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1056 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_944; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1057 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_945; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1058 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_946; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1059 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_947; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1060 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_948; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1061 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_949; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1062 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_950; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1063 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_951; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1072 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_984; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1073 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_985; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1074 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_986; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1075 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_987; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1076 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_988; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1077 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_989; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1078 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_990; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1079 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_991; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1080 = if2_ibuf__T_16 ? if2_ibuf__GEN_1072 : if2_ibuf__GEN_984; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1081 = if2_ibuf__T_16 ? if2_ibuf__GEN_1073 : if2_ibuf__GEN_985; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1082 = if2_ibuf__T_16 ? if2_ibuf__GEN_1074 : if2_ibuf__GEN_986; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1083 = if2_ibuf__T_16 ? if2_ibuf__GEN_1075 : if2_ibuf__GEN_987; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1084 = if2_ibuf__T_16 ? if2_ibuf__GEN_1076 : if2_ibuf__GEN_988; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1085 = if2_ibuf__T_16 ? if2_ibuf__GEN_1077 : if2_ibuf__GEN_989; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1086 = if2_ibuf__T_16 ? if2_ibuf__GEN_1078 : if2_ibuf__GEN_990; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1087 = if2_ibuf__T_16 ? if2_ibuf__GEN_1079 : if2_ibuf__GEN_991; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1088 = 3'h0 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1080; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1089 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1081; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1090 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1082; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1091 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1083; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1092 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1084; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1093 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1085; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1094 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1086; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1095 = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1087; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1096 = if2_ibuf__T_3 ? if2_ibuf__GEN_1088 : if2_ibuf__GEN_1080; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1097 = if2_ibuf__T_3 ? if2_ibuf__GEN_1089 : if2_ibuf__GEN_1081; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1098 = if2_ibuf__T_3 ? if2_ibuf__GEN_1090 : if2_ibuf__GEN_1082; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1099 = if2_ibuf__T_3 ? if2_ibuf__GEN_1091 : if2_ibuf__GEN_1083; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1100 = if2_ibuf__T_3 ? if2_ibuf__GEN_1092 : if2_ibuf__GEN_1084; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1101 = if2_ibuf__T_3 ? if2_ibuf__GEN_1093 : if2_ibuf__GEN_1085; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1102 = if2_ibuf__T_3 ? if2_ibuf__GEN_1094 : if2_ibuf__GEN_1086; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1103 = if2_ibuf__T_3 ? if2_ibuf__GEN_1095 : if2_ibuf__GEN_1087; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_1144 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1032; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1145 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1033; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1146 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1034; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1147 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1035; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1148 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1036; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1149 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1037; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1150 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1038; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1151 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1039; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1152 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1040; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1153 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1041; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1154 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1042; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1155 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1043; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1156 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1044; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1157 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1045; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1158 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1046; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1159 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1047; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1160 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1048; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1161 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1049; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1162 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1050; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1163 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1051; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1164 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1052; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1165 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1053; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1166 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1054; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1167 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1055; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1168 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1056; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1169 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1057; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1170 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1058; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1171 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1059; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1172 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1060; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1173 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1061; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1174 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1062; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1175 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1063; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1184 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1096; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1185 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1097; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1186 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1098; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1187 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1099; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1188 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1100; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1189 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1101; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1190 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1102; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1191 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1103; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1192 = if2_ibuf__T_16 ? if2_ibuf__GEN_1184 : if2_ibuf__GEN_1096; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1193 = if2_ibuf__T_16 ? if2_ibuf__GEN_1185 : if2_ibuf__GEN_1097; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1194 = if2_ibuf__T_16 ? if2_ibuf__GEN_1186 : if2_ibuf__GEN_1098; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1195 = if2_ibuf__T_16 ? if2_ibuf__GEN_1187 : if2_ibuf__GEN_1099; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1196 = if2_ibuf__T_16 ? if2_ibuf__GEN_1188 : if2_ibuf__GEN_1100; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1197 = if2_ibuf__T_16 ? if2_ibuf__GEN_1189 : if2_ibuf__GEN_1101; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1198 = if2_ibuf__T_16 ? if2_ibuf__GEN_1190 : if2_ibuf__GEN_1102; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1199 = if2_ibuf__T_16 ? if2_ibuf__GEN_1191 : if2_ibuf__GEN_1103; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1200 = 3'h0 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1192; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1201 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1193; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1202 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1194; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1203 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1195; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1204 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1196; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1205 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1197; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1206 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1198; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1207 = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1199; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1208 = if2_ibuf__T_5 ? if2_ibuf__GEN_1200 : if2_ibuf__GEN_1192; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1209 = if2_ibuf__T_5 ? if2_ibuf__GEN_1201 : if2_ibuf__GEN_1193; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1210 = if2_ibuf__T_5 ? if2_ibuf__GEN_1202 : if2_ibuf__GEN_1194; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1211 = if2_ibuf__T_5 ? if2_ibuf__GEN_1203 : if2_ibuf__GEN_1195; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1212 = if2_ibuf__T_5 ? if2_ibuf__GEN_1204 : if2_ibuf__GEN_1196; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1213 = if2_ibuf__T_5 ? if2_ibuf__GEN_1205 : if2_ibuf__GEN_1197; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1214 = if2_ibuf__T_5 ? if2_ibuf__GEN_1206 : if2_ibuf__GEN_1198; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1215 = if2_ibuf__T_5 ? if2_ibuf__GEN_1207 : if2_ibuf__GEN_1199; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_1256 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1144; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1257 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1145; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1258 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1146; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1259 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1147; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1260 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1148; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1261 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1149; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1262 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1150; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1263 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1151; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1264 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1152; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1265 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1153; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1266 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1154; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1267 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1155; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1268 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1156; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1269 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1157; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1270 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1158; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1271 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1159; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1272 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1160; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1273 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1161; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1274 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1162; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1275 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1163; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1276 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1164; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1277 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1165; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1278 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1166; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1279 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1167; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1280 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1168; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1281 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1169; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1282 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1170; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1283 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1171; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1284 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1172; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1285 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1173; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1286 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1174; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1287 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1175; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1296 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1208; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1297 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1209; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1298 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1210; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1299 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1211; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1300 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1212; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1301 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1213; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1302 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1214; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1303 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 | if2_ibuf__GEN_1215; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1304 = if2_ibuf__T_16 ? if2_ibuf__GEN_1296 : if2_ibuf__GEN_1208; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1305 = if2_ibuf__T_16 ? if2_ibuf__GEN_1297 : if2_ibuf__GEN_1209; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1306 = if2_ibuf__T_16 ? if2_ibuf__GEN_1298 : if2_ibuf__GEN_1210; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1307 = if2_ibuf__T_16 ? if2_ibuf__GEN_1299 : if2_ibuf__GEN_1211; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1308 = if2_ibuf__T_16 ? if2_ibuf__GEN_1300 : if2_ibuf__GEN_1212; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1309 = if2_ibuf__T_16 ? if2_ibuf__GEN_1301 : if2_ibuf__GEN_1213; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1310 = if2_ibuf__T_16 ? if2_ibuf__GEN_1302 : if2_ibuf__GEN_1214; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1311 = if2_ibuf__T_16 ? if2_ibuf__GEN_1303 : if2_ibuf__GEN_1215; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1312 = 3'h0 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1304; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1313 = 3'h1 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1305; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1314 = 3'h2 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1306; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1315 = 3'h3 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1307; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1316 = 3'h4 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1308; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1317 = 3'h5 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1309; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1318 = 3'h6 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1310; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1319 = 3'h7 == if2_ibuf__io_deq_3_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1311; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1320 = if2_ibuf__T_7 ? if2_ibuf__GEN_1312 : if2_ibuf__GEN_1304; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1321 = if2_ibuf__T_7 ? if2_ibuf__GEN_1313 : if2_ibuf__GEN_1305; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1322 = if2_ibuf__T_7 ? if2_ibuf__GEN_1314 : if2_ibuf__GEN_1306; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1323 = if2_ibuf__T_7 ? if2_ibuf__GEN_1315 : if2_ibuf__GEN_1307; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1324 = if2_ibuf__T_7 ? if2_ibuf__GEN_1316 : if2_ibuf__GEN_1308; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1325 = if2_ibuf__T_7 ? if2_ibuf__GEN_1317 : if2_ibuf__GEN_1309; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1326 = if2_ibuf__T_7 ? if2_ibuf__GEN_1318 : if2_ibuf__GEN_1310; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1327 = if2_ibuf__T_7 ? if2_ibuf__GEN_1319 : if2_ibuf__GEN_1311; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_1368 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1256; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1369 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1257; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1370 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1258; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1371 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1259; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1372 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1260; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1373 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1261; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1374 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1262; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1375 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_pc : if2_ibuf__GEN_1263; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1376 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1264; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1377 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1265; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1378 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1266; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1379 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1267; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1380 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1268; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1381 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1269; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1382 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1270; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1383 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_instr : if2_ibuf__GEN_1271; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1384 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1272; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1385 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1273; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1386 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1274; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1387 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1275; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1388 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1276; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1389 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1277; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1390 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1278; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1391 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isFault : if2_ibuf__GEN_1279; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1392 = 3'h0 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1280; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1393 = 3'h1 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1281; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1394 = 3'h2 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1282; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1395 = 3'h3 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1283; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1396 = 3'h4 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1284; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1397 = 3'h5 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1285; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1398 = 3'h6 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1286; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1399 = 3'h7 == if2_ibuf__io_enq_2_ready_T_1 ? if2_ibuf__buf_T_17_isRedirect : if2_ibuf__GEN_1287; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__T_24 = if2_ibuf_io_enq_3_ready & if2_ibuf_io_enq_3_valid; // @[Decoupled.scala 52:35]
  wire  if2_ibuf__GEN_1408 = 3'h0 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1320; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1409 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1321; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1410 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1322; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1411 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1323; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1412 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1324; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1413 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1325; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1414 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1326; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1415 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1327; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1416 = if2_ibuf__T_24 ? if2_ibuf__GEN_1408 : if2_ibuf__GEN_1320; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1417 = if2_ibuf__T_24 ? if2_ibuf__GEN_1409 : if2_ibuf__GEN_1321; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1418 = if2_ibuf__T_24 ? if2_ibuf__GEN_1410 : if2_ibuf__GEN_1322; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1419 = if2_ibuf__T_24 ? if2_ibuf__GEN_1411 : if2_ibuf__GEN_1323; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1420 = if2_ibuf__T_24 ? if2_ibuf__GEN_1412 : if2_ibuf__GEN_1324; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1421 = if2_ibuf__T_24 ? if2_ibuf__GEN_1413 : if2_ibuf__GEN_1325; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1422 = if2_ibuf__T_24 ? if2_ibuf__GEN_1414 : if2_ibuf__GEN_1326; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1423 = if2_ibuf__T_24 ? if2_ibuf__GEN_1415 : if2_ibuf__GEN_1327; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1424 = 3'h0 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1416; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1425 = 3'h1 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1417; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1426 = 3'h2 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1418; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1427 = 3'h3 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1419; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1428 = 3'h4 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1420; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1429 = 3'h5 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1421; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1430 = 3'h6 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1422; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1431 = 3'h7 == if2_ibuf__io_deq_0_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1423; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1432 = if2_ibuf__T_1 ? if2_ibuf__GEN_1424 : if2_ibuf__GEN_1416; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1433 = if2_ibuf__T_1 ? if2_ibuf__GEN_1425 : if2_ibuf__GEN_1417; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1434 = if2_ibuf__T_1 ? if2_ibuf__GEN_1426 : if2_ibuf__GEN_1418; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1435 = if2_ibuf__T_1 ? if2_ibuf__GEN_1427 : if2_ibuf__GEN_1419; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1436 = if2_ibuf__T_1 ? if2_ibuf__GEN_1428 : if2_ibuf__GEN_1420; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1437 = if2_ibuf__T_1 ? if2_ibuf__GEN_1429 : if2_ibuf__GEN_1421; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1438 = if2_ibuf__T_1 ? if2_ibuf__GEN_1430 : if2_ibuf__GEN_1422; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1439 = if2_ibuf__T_1 ? if2_ibuf__GEN_1431 : if2_ibuf__GEN_1423; // @[MultiPortFifo.scala 98:34]
  wire [38:0] if2_ibuf__GEN_1445 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1446 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1447 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_1_isFault : if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1448 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_1_isRedirect :
    if2_ibuf_buf_0_isRedirect; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1450 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_2_pc : if2_ibuf__GEN_1445; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1451 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_2_instr : if2_ibuf__GEN_1446; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1452 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_2_isFault : if2_ibuf__GEN_1447; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1453 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_2_isRedirect : if2_ibuf__GEN_1448; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1455 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_3_pc : if2_ibuf__GEN_1450; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1456 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_3_instr : if2_ibuf__GEN_1451; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1457 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_3_isFault : if2_ibuf__GEN_1452; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1458 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_3_isRedirect : if2_ibuf__GEN_1453; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1460 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_4_pc : if2_ibuf__GEN_1455; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1461 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_4_instr : if2_ibuf__GEN_1456; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1462 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_4_isFault : if2_ibuf__GEN_1457; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1463 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_4_isRedirect : if2_ibuf__GEN_1458; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1465 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_5_pc : if2_ibuf__GEN_1460; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1466 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_5_instr : if2_ibuf__GEN_1461; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1467 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_5_isFault : if2_ibuf__GEN_1462; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1468 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_5_isRedirect : if2_ibuf__GEN_1463; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1470 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_6_pc : if2_ibuf__GEN_1465; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1471 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_6_instr : if2_ibuf__GEN_1466; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1472 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_6_isFault : if2_ibuf__GEN_1467; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1473 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_6_isRedirect : if2_ibuf__GEN_1468; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__GEN_1475 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_7_pc : if2_ibuf__GEN_1470; // @[MultiPortFifo.scala 101:{33,33}]
  wire [15:0] if2_ibuf__GEN_1476 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_7_instr : if2_ibuf__GEN_1471; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1477 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_7_isFault : if2_ibuf__GEN_1472; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if2_ibuf__GEN_1478 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf_buf_7_isRedirect : if2_ibuf__GEN_1473; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if2_ibuf__buf_T_25_pc = if2_ibuf__T_24 ? if2_ibuf_io_enq_3_bits_pc : if2_ibuf__GEN_1475; // @[MultiPortFifo.scala 101:33]
  wire [15:0] if2_ibuf__buf_T_25_instr = if2_ibuf__T_24 ? if2_ibuf_io_enq_3_bits_instr : if2_ibuf__GEN_1476; // @[MultiPortFifo.scala 101:33]
  wire  if2_ibuf__buf_T_25_isFault = if2_ibuf__T_24 ? 1'h0 : if2_ibuf__GEN_1477; // @[MultiPortFifo.scala 101:33]
  wire  if2_ibuf__buf_T_25_isRedirect = if2_ibuf__T_24 ? 1'h0 : if2_ibuf__GEN_1478; // @[MultiPortFifo.scala 101:33]
  wire [38:0] if2_ibuf__GEN_1480 = 3'h0 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_pc : if2_ibuf__GEN_1368; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1481 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_pc : if2_ibuf__GEN_1369; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1482 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_pc : if2_ibuf__GEN_1370; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1483 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_pc : if2_ibuf__GEN_1371; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1484 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_pc : if2_ibuf__GEN_1372; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1485 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_pc : if2_ibuf__GEN_1373; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1486 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_pc : if2_ibuf__GEN_1374; // @[MultiPortFifo.scala 101:{27,27}]
  wire [38:0] if2_ibuf__GEN_1487 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_pc : if2_ibuf__GEN_1375; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1488 = 3'h0 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_instr : if2_ibuf__GEN_1376; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1489 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_instr : if2_ibuf__GEN_1377; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1490 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_instr : if2_ibuf__GEN_1378; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1491 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_instr : if2_ibuf__GEN_1379; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1492 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_instr : if2_ibuf__GEN_1380; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1493 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_instr : if2_ibuf__GEN_1381; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1494 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_instr : if2_ibuf__GEN_1382; // @[MultiPortFifo.scala 101:{27,27}]
  wire [15:0] if2_ibuf__GEN_1495 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_instr : if2_ibuf__GEN_1383; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1496 = 3'h0 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isFault : if2_ibuf__GEN_1384; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1497 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isFault : if2_ibuf__GEN_1385; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1498 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isFault : if2_ibuf__GEN_1386; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1499 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isFault : if2_ibuf__GEN_1387; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1500 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isFault : if2_ibuf__GEN_1388; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1501 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isFault : if2_ibuf__GEN_1389; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1502 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isFault : if2_ibuf__GEN_1390; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1503 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isFault : if2_ibuf__GEN_1391; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1504 = 3'h0 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isRedirect : if2_ibuf__GEN_1392; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1505 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isRedirect : if2_ibuf__GEN_1393; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1506 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isRedirect : if2_ibuf__GEN_1394; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1507 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isRedirect : if2_ibuf__GEN_1395; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1508 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isRedirect : if2_ibuf__GEN_1396; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1509 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isRedirect : if2_ibuf__GEN_1397; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1510 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isRedirect : if2_ibuf__GEN_1398; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1511 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 ? if2_ibuf__buf_T_25_isRedirect : if2_ibuf__GEN_1399; // @[MultiPortFifo.scala 101:{27,27}]
  wire  if2_ibuf__GEN_1520 = 3'h0 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1432; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1521 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1433; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1522 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1434; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1523 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1435; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1524 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1436; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1525 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1437; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1526 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1438; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1527 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1439; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1528 = if2_ibuf__T_24 ? if2_ibuf__GEN_1520 : if2_ibuf__GEN_1432; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1529 = if2_ibuf__T_24 ? if2_ibuf__GEN_1521 : if2_ibuf__GEN_1433; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1530 = if2_ibuf__T_24 ? if2_ibuf__GEN_1522 : if2_ibuf__GEN_1434; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1531 = if2_ibuf__T_24 ? if2_ibuf__GEN_1523 : if2_ibuf__GEN_1435; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1532 = if2_ibuf__T_24 ? if2_ibuf__GEN_1524 : if2_ibuf__GEN_1436; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1533 = if2_ibuf__T_24 ? if2_ibuf__GEN_1525 : if2_ibuf__GEN_1437; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1534 = if2_ibuf__T_24 ? if2_ibuf__GEN_1526 : if2_ibuf__GEN_1438; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1535 = if2_ibuf__T_24 ? if2_ibuf__GEN_1527 : if2_ibuf__GEN_1439; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1536 = 3'h0 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1528; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1537 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1529; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1538 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1530; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1539 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1531; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1540 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1532; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1541 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1533; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1542 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1534; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1543 = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1535; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1544 = if2_ibuf__T_3 ? if2_ibuf__GEN_1536 : if2_ibuf__GEN_1528; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1545 = if2_ibuf__T_3 ? if2_ibuf__GEN_1537 : if2_ibuf__GEN_1529; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1546 = if2_ibuf__T_3 ? if2_ibuf__GEN_1538 : if2_ibuf__GEN_1530; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1547 = if2_ibuf__T_3 ? if2_ibuf__GEN_1539 : if2_ibuf__GEN_1531; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1548 = if2_ibuf__T_3 ? if2_ibuf__GEN_1540 : if2_ibuf__GEN_1532; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1549 = if2_ibuf__T_3 ? if2_ibuf__GEN_1541 : if2_ibuf__GEN_1533; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1550 = if2_ibuf__T_3 ? if2_ibuf__GEN_1542 : if2_ibuf__GEN_1534; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1551 = if2_ibuf__T_3 ? if2_ibuf__GEN_1543 : if2_ibuf__GEN_1535; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1632 = 3'h0 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1544; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1633 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1545; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1634 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1546; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1635 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1547; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1636 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1548; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1637 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1549; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1638 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1550; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1639 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1551; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1640 = if2_ibuf__T_24 ? if2_ibuf__GEN_1632 : if2_ibuf__GEN_1544; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1641 = if2_ibuf__T_24 ? if2_ibuf__GEN_1633 : if2_ibuf__GEN_1545; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1642 = if2_ibuf__T_24 ? if2_ibuf__GEN_1634 : if2_ibuf__GEN_1546; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1643 = if2_ibuf__T_24 ? if2_ibuf__GEN_1635 : if2_ibuf__GEN_1547; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1644 = if2_ibuf__T_24 ? if2_ibuf__GEN_1636 : if2_ibuf__GEN_1548; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1645 = if2_ibuf__T_24 ? if2_ibuf__GEN_1637 : if2_ibuf__GEN_1549; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1646 = if2_ibuf__T_24 ? if2_ibuf__GEN_1638 : if2_ibuf__GEN_1550; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1647 = if2_ibuf__T_24 ? if2_ibuf__GEN_1639 : if2_ibuf__GEN_1551; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1648 = 3'h0 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1640; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1649 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1641; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1650 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1642; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1651 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1643; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1652 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1644; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1653 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1645; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1654 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1646; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1655 = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? 1'h0 : if2_ibuf__GEN_1647; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if2_ibuf__GEN_1656 = if2_ibuf__T_5 ? if2_ibuf__GEN_1648 : if2_ibuf__GEN_1640; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1657 = if2_ibuf__T_5 ? if2_ibuf__GEN_1649 : if2_ibuf__GEN_1641; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1658 = if2_ibuf__T_5 ? if2_ibuf__GEN_1650 : if2_ibuf__GEN_1642; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1659 = if2_ibuf__T_5 ? if2_ibuf__GEN_1651 : if2_ibuf__GEN_1643; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1660 = if2_ibuf__T_5 ? if2_ibuf__GEN_1652 : if2_ibuf__GEN_1644; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1661 = if2_ibuf__T_5 ? if2_ibuf__GEN_1653 : if2_ibuf__GEN_1645; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1662 = if2_ibuf__T_5 ? if2_ibuf__GEN_1654 : if2_ibuf__GEN_1646; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1663 = if2_ibuf__T_5 ? if2_ibuf__GEN_1655 : if2_ibuf__GEN_1647; // @[MultiPortFifo.scala 98:34]
  wire  if2_ibuf__GEN_1744 = 3'h0 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1656; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1745 = 3'h1 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1657; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1746 = 3'h2 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1658; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1747 = 3'h3 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1659; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1748 = 3'h4 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1660; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1749 = 3'h5 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1661; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1750 = 3'h6 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1662; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1751 = 3'h7 == if2_ibuf__io_enq_3_ready_T_1 | if2_ibuf__GEN_1663; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if2_ibuf__GEN_1752 = if2_ibuf__T_24 ? if2_ibuf__GEN_1744 : if2_ibuf__GEN_1656; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1753 = if2_ibuf__T_24 ? if2_ibuf__GEN_1745 : if2_ibuf__GEN_1657; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1754 = if2_ibuf__T_24 ? if2_ibuf__GEN_1746 : if2_ibuf__GEN_1658; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1755 = if2_ibuf__T_24 ? if2_ibuf__GEN_1747 : if2_ibuf__GEN_1659; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1756 = if2_ibuf__T_24 ? if2_ibuf__GEN_1748 : if2_ibuf__GEN_1660; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1757 = if2_ibuf__T_24 ? if2_ibuf__GEN_1749 : if2_ibuf__GEN_1661; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1758 = if2_ibuf__T_24 ? if2_ibuf__GEN_1750 : if2_ibuf__GEN_1662; // @[MultiPortFifo.scala 97:34]
  wire  if2_ibuf__GEN_1759 = if2_ibuf__T_24 ? if2_ibuf__GEN_1751 : if2_ibuf__GEN_1663; // @[MultiPortFifo.scala 97:34]
  wire [1:0] if2_ibuf__rd_ptr_T_1 = if2_ibuf__T_3 ? 2'h2 : {{1'd0}, if2_ibuf__T_1}; // @[Mux.scala 101:16]
  wire [1:0] if2_ibuf__rd_ptr_T_2 = if2_ibuf__T_5 ? 2'h3 : if2_ibuf__rd_ptr_T_1; // @[Mux.scala 101:16]
  wire [2:0] if2_ibuf__rd_ptr_T_3 = if2_ibuf__T_7 ? 3'h4 : {{1'd0}, if2_ibuf__rd_ptr_T_2}; // @[Mux.scala 101:16]
  wire [2:0] if2_ibuf__rd_ptr_T_5 = if2_ibuf_rd_ptr + if2_ibuf__rd_ptr_T_3; // @[MultiPortFifo.scala 106:26]
  wire [1:0] if2_ibuf__wr_ptr_T_1 = if2_ibuf__T_8 ? 2'h2 : {{1'd0}, if2_ibuf__T}; // @[Mux.scala 101:16]
  wire [1:0] if2_ibuf__wr_ptr_T_2 = if2_ibuf__T_16 ? 2'h3 : if2_ibuf__wr_ptr_T_1; // @[Mux.scala 101:16]
  wire [2:0] if2_ibuf__wr_ptr_T_3 = if2_ibuf__T_24 ? 3'h4 : {{1'd0}, if2_ibuf__wr_ptr_T_2}; // @[Mux.scala 101:16]
  wire [2:0] if2_ibuf__wr_ptr_T_5 = if2_ibuf_wr_ptr + if2_ibuf__wr_ptr_T_3; // @[MultiPortFifo.scala 107:26]
  wire [38:0] if2_ibuf__GEN_1911 = 3'h1 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1912 = 3'h1 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1914 = 3'h1 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_1_isRedirect :
    if2_ibuf_buf_0_isRedirect; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1916 = 3'h2 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_2_pc : if2_ibuf__GEN_1911; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1917 = 3'h2 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_2_instr : if2_ibuf__GEN_1912; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1919 = 3'h2 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_2_isRedirect : if2_ibuf__GEN_1914; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1921 = 3'h3 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_3_pc : if2_ibuf__GEN_1916; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1922 = 3'h3 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_3_instr : if2_ibuf__GEN_1917; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1924 = 3'h3 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_3_isRedirect : if2_ibuf__GEN_1919; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1926 = 3'h4 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_4_pc : if2_ibuf__GEN_1921; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1927 = 3'h4 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_4_instr : if2_ibuf__GEN_1922; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1929 = 3'h4 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_4_isRedirect : if2_ibuf__GEN_1924; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1931 = 3'h5 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_5_pc : if2_ibuf__GEN_1926; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1932 = 3'h5 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_5_instr : if2_ibuf__GEN_1927; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1934 = 3'h5 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_5_isRedirect : if2_ibuf__GEN_1929; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1936 = 3'h6 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_6_pc : if2_ibuf__GEN_1931; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1937 = 3'h6 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_6_instr : if2_ibuf__GEN_1932; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1939 = 3'h6 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_6_isRedirect : if2_ibuf__GEN_1934; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1951 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1952 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1953 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_1_isFault : if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1954 = 3'h1 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_1_isRedirect :
    if2_ibuf_buf_0_isRedirect; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1956 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_2_pc : if2_ibuf__GEN_1951; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1957 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_2_instr : if2_ibuf__GEN_1952; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1958 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_2_isFault : if2_ibuf__GEN_1953; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1959 = 3'h2 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_2_isRedirect : if2_ibuf__GEN_1954; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1961 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_3_pc : if2_ibuf__GEN_1956; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1962 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_3_instr : if2_ibuf__GEN_1957; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1963 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_3_isFault : if2_ibuf__GEN_1958; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1964 = 3'h3 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_3_isRedirect : if2_ibuf__GEN_1959; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1966 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_4_pc : if2_ibuf__GEN_1961; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1967 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_4_instr : if2_ibuf__GEN_1962; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1968 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_4_isFault : if2_ibuf__GEN_1963; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1969 = 3'h4 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_4_isRedirect : if2_ibuf__GEN_1964; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1971 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_5_pc : if2_ibuf__GEN_1966; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1972 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_5_instr : if2_ibuf__GEN_1967; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1973 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_5_isFault : if2_ibuf__GEN_1968; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1974 = 3'h5 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_5_isRedirect : if2_ibuf__GEN_1969; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1976 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_6_pc : if2_ibuf__GEN_1971; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1977 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_6_instr : if2_ibuf__GEN_1972; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1978 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_6_isFault : if2_ibuf__GEN_1973; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1979 = 3'h6 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_6_isRedirect : if2_ibuf__GEN_1974; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1991 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1992 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1993 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_1_isFault : if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1994 = 3'h1 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_1_isRedirect :
    if2_ibuf_buf_0_isRedirect; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_1996 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_2_pc : if2_ibuf__GEN_1991; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_1997 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_2_instr : if2_ibuf__GEN_1992; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1998 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_2_isFault : if2_ibuf__GEN_1993; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_1999 = 3'h2 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_2_isRedirect : if2_ibuf__GEN_1994; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2001 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_3_pc : if2_ibuf__GEN_1996; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2002 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_3_instr : if2_ibuf__GEN_1997; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2003 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_3_isFault : if2_ibuf__GEN_1998; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2004 = 3'h3 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_3_isRedirect : if2_ibuf__GEN_1999; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2006 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_4_pc : if2_ibuf__GEN_2001; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2007 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_4_instr : if2_ibuf__GEN_2002; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2008 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_4_isFault : if2_ibuf__GEN_2003; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2009 = 3'h4 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_4_isRedirect : if2_ibuf__GEN_2004; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2011 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_5_pc : if2_ibuf__GEN_2006; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2012 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_5_instr : if2_ibuf__GEN_2007; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2013 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_5_isFault : if2_ibuf__GEN_2008; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2014 = 3'h5 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_5_isRedirect : if2_ibuf__GEN_2009; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2016 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_6_pc : if2_ibuf__GEN_2011; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2017 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_6_instr : if2_ibuf__GEN_2012; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2018 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_6_isFault : if2_ibuf__GEN_2013; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2019 = 3'h6 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_6_isRedirect : if2_ibuf__GEN_2014; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2031 = 3'h1 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_1_pc : if2_ibuf_buf_0_pc; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2032 = 3'h1 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_1_instr : if2_ibuf_buf_0_instr; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2033 = 3'h1 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_1_isFault : if2_ibuf_buf_0_isFault; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2034 = 3'h1 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_1_isRedirect :
    if2_ibuf_buf_0_isRedirect; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2036 = 3'h2 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_2_pc : if2_ibuf__GEN_2031; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2037 = 3'h2 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_2_instr : if2_ibuf__GEN_2032; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2038 = 3'h2 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_2_isFault : if2_ibuf__GEN_2033; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2039 = 3'h2 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_2_isRedirect : if2_ibuf__GEN_2034; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2041 = 3'h3 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_3_pc : if2_ibuf__GEN_2036; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2042 = 3'h3 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_3_instr : if2_ibuf__GEN_2037; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2043 = 3'h3 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_3_isFault : if2_ibuf__GEN_2038; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2044 = 3'h3 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_3_isRedirect : if2_ibuf__GEN_2039; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2046 = 3'h4 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_4_pc : if2_ibuf__GEN_2041; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2047 = 3'h4 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_4_instr : if2_ibuf__GEN_2042; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2048 = 3'h4 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_4_isFault : if2_ibuf__GEN_2043; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2049 = 3'h4 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_4_isRedirect : if2_ibuf__GEN_2044; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2051 = 3'h5 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_5_pc : if2_ibuf__GEN_2046; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2052 = 3'h5 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_5_instr : if2_ibuf__GEN_2047; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2053 = 3'h5 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_5_isFault : if2_ibuf__GEN_2048; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2054 = 3'h5 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_5_isRedirect : if2_ibuf__GEN_2049; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if2_ibuf__GEN_2056 = 3'h6 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_6_pc : if2_ibuf__GEN_2051; // @[MultiPortFifo.scala 114:{14,14}]
  wire [15:0] if2_ibuf__GEN_2057 = 3'h6 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_6_instr : if2_ibuf__GEN_2052; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2058 = 3'h6 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_6_isFault : if2_ibuf__GEN_2053; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__GEN_2059 = 3'h6 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_6_isRedirect : if2_ibuf__GEN_2054; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if2_ibuf__T_33 = ~if2_ibuf_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if2_ibuf__T_34 = if2_ibuf_io_enq_0_valid & if2_ibuf__T_33; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_37 = ~if2_ibuf__T_34; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_39 = ~if2_ibuf_reset; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_40 = ~if2_ibuf__T_37; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_42 = ~if2_ibuf_io_enq_1_valid; // @[MultiPortFifo.scala 161:63]
  wire  if2_ibuf__T_51 = ~if2_ibuf_io_enq_2_valid; // @[MultiPortFifo.scala 161:63]
  wire  if2_ibuf__T_60 = ~if2_ibuf_io_enq_3_valid; // @[MultiPortFifo.scala 161:63]
  wire  if2_ibuf__T_70 = if2_ibuf_io_enq_1_valid & if2_ibuf__T_33; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_73 = ~if2_ibuf__T_70; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_76 = ~if2_ibuf__T_73; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_79 = if2_ibuf_io_enq_1_valid & if2_ibuf__T_42; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_82 = ~if2_ibuf__T_79; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_85 = ~if2_ibuf__T_82; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_106 = if2_ibuf_io_enq_2_valid & if2_ibuf__T_33; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_109 = ~if2_ibuf__T_106; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_112 = ~if2_ibuf__T_109; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_115 = if2_ibuf_io_enq_2_valid & if2_ibuf__T_42; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_118 = ~if2_ibuf__T_115; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_121 = ~if2_ibuf__T_118; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_124 = if2_ibuf_io_enq_2_valid & if2_ibuf__T_51; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_127 = ~if2_ibuf__T_124; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_130 = ~if2_ibuf__T_127; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_142 = if2_ibuf_io_enq_3_valid & if2_ibuf__T_33; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_145 = ~if2_ibuf__T_142; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_148 = ~if2_ibuf__T_145; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_151 = if2_ibuf_io_enq_3_valid & if2_ibuf__T_42; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_154 = ~if2_ibuf__T_151; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_157 = ~if2_ibuf__T_154; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_160 = if2_ibuf_io_enq_3_valid & if2_ibuf__T_51; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_163 = ~if2_ibuf__T_160; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_166 = ~if2_ibuf__T_163; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_169 = if2_ibuf_io_enq_3_valid & if2_ibuf__T_60; // @[MultiPortFifo.scala 161:44]
  wire  if2_ibuf__T_172 = ~if2_ibuf__T_169; // @[MultiPortFifo.scala 161:15]
  wire  if2_ibuf__T_175 = ~if2_ibuf__T_172; // @[MultiPortFifo.scala 161:13]
  wire  if2_ibuf__T_177 = ~if2_ibuf_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if2_ibuf__T_178 = if2_ibuf_io_deq_0_valid & if2_ibuf__T_177; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_181 = ~if2_ibuf__T_178; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_184 = ~if2_ibuf__T_181; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_186 = ~if2_ibuf_io_deq_1_valid; // @[MultiPortFifo.scala 164:63]
  wire  if2_ibuf__T_195 = ~if2_ibuf_io_deq_2_valid; // @[MultiPortFifo.scala 164:63]
  wire  if2_ibuf__T_204 = ~if2_ibuf_io_deq_3_valid; // @[MultiPortFifo.scala 164:63]
  wire  if2_ibuf__T_214 = if2_ibuf_io_deq_1_valid & if2_ibuf__T_177; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_217 = ~if2_ibuf__T_214; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_220 = ~if2_ibuf__T_217; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_223 = if2_ibuf_io_deq_1_valid & if2_ibuf__T_186; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_226 = ~if2_ibuf__T_223; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_229 = ~if2_ibuf__T_226; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_250 = if2_ibuf_io_deq_2_valid & if2_ibuf__T_177; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_253 = ~if2_ibuf__T_250; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_256 = ~if2_ibuf__T_253; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_259 = if2_ibuf_io_deq_2_valid & if2_ibuf__T_186; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_262 = ~if2_ibuf__T_259; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_265 = ~if2_ibuf__T_262; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_268 = if2_ibuf_io_deq_2_valid & if2_ibuf__T_195; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_271 = ~if2_ibuf__T_268; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_274 = ~if2_ibuf__T_271; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_286 = if2_ibuf_io_deq_3_valid & if2_ibuf__T_177; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_289 = ~if2_ibuf__T_286; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_292 = ~if2_ibuf__T_289; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_295 = if2_ibuf_io_deq_3_valid & if2_ibuf__T_186; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_298 = ~if2_ibuf__T_295; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_301 = ~if2_ibuf__T_298; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_304 = if2_ibuf_io_deq_3_valid & if2_ibuf__T_195; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_307 = ~if2_ibuf__T_304; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_310 = ~if2_ibuf__T_307; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_313 = if2_ibuf_io_deq_3_valid & if2_ibuf__T_204; // @[MultiPortFifo.scala 164:44]
  wire  if2_ibuf__T_316 = ~if2_ibuf__T_313; // @[MultiPortFifo.scala 164:15]
  wire  if2_ibuf__T_319 = ~if2_ibuf__T_316; // @[MultiPortFifo.scala 164:13]
  wire  if2_ibuf__T_325 = ~if2_ibuf__T; // @[MultiPortFifo.scala 169:17]
  wire  if2_ibuf__T_334 = ~if2_ibuf__T_8; // @[MultiPortFifo.scala 169:17]
  wire  if2_ibuf__T_347 = ~if2_ibuf__T_16; // @[MultiPortFifo.scala 169:17]
  wire  if2_ibuf__T_353 = ~if2_ibuf__T_1; // @[MultiPortFifo.scala 177:17]
  wire  if2_ibuf__T_362 = ~if2_ibuf__T_3; // @[MultiPortFifo.scala 177:17]
  wire  if2_ibuf__T_375 = ~if2_ibuf__T_5; // @[MultiPortFifo.scala 177:17]
  wire  if2_datRAM_0_clock;
  wire  if2_datRAM_0_io_addrr;
  wire  if2_datRAM_0_io_addrw;
  wire [7:0] if2_datRAM_0_io_dataw_0;
  wire [7:0] if2_datRAM_0_io_dataw_1;
  wire [7:0] if2_datRAM_0_io_dataw_2;
  wire [7:0] if2_datRAM_0_io_dataw_3;
  wire [7:0] if2_datRAM_0_io_dataw_4;
  wire [7:0] if2_datRAM_0_io_dataw_5;
  wire [7:0] if2_datRAM_0_io_dataw_6;
  wire [7:0] if2_datRAM_0_io_dataw_7;
  wire [7:0] if2_datRAM_0_io_dataw_8;
  wire [7:0] if2_datRAM_0_io_dataw_9;
  wire [7:0] if2_datRAM_0_io_dataw_10;
  wire [7:0] if2_datRAM_0_io_dataw_11;
  wire [7:0] if2_datRAM_0_io_dataw_12;
  wire [7:0] if2_datRAM_0_io_dataw_13;
  wire [7:0] if2_datRAM_0_io_dataw_14;
  wire [7:0] if2_datRAM_0_io_dataw_15;
  wire [7:0] if2_datRAM_0_io_datar_0;
  wire [7:0] if2_datRAM_0_io_datar_1;
  wire [7:0] if2_datRAM_0_io_datar_2;
  wire [7:0] if2_datRAM_0_io_datar_3;
  wire [7:0] if2_datRAM_0_io_datar_4;
  wire [7:0] if2_datRAM_0_io_datar_5;
  wire [7:0] if2_datRAM_0_io_datar_6;
  wire [7:0] if2_datRAM_0_io_datar_7;
  wire [7:0] if2_datRAM_0_io_datar_8;
  wire [7:0] if2_datRAM_0_io_datar_9;
  wire [7:0] if2_datRAM_0_io_datar_10;
  wire [7:0] if2_datRAM_0_io_datar_11;
  wire [7:0] if2_datRAM_0_io_datar_12;
  wire [7:0] if2_datRAM_0_io_datar_13;
  wire [7:0] if2_datRAM_0_io_datar_14;
  wire [7:0] if2_datRAM_0_io_datar_15;
  wire  if2_datRAM_0_io_enw;
  wire  if2_datRAM_0_io_enr;
  reg [7:0] if2_datRAM_0_datMem_0 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_0_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_0_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_0_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_0_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_0_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_0_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_0_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_0_clock;
  reg  if2_datRAM_0_datMem_0_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_0_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_1 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_1_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_1_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_1_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_1_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_1_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_1_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_1_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_1_clock;
  reg  if2_datRAM_0_datMem_1_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_1_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_2 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_2_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_2_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_2_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_2_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_2_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_2_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_2_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_2_clock;
  reg  if2_datRAM_0_datMem_2_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_2_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_3 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_3_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_3_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_3_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_3_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_3_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_3_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_3_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_3_clock;
  reg  if2_datRAM_0_datMem_3_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_3_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_4 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_4_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_4_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_4_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_4_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_4_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_4_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_4_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_4_clock;
  reg  if2_datRAM_0_datMem_4_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_4_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_5 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_5_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_5_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_5_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_5_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_5_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_5_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_5_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_5_clock;
  reg  if2_datRAM_0_datMem_5_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_5_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_6 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_6_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_6_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_6_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_6_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_6_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_6_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_6_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_6_clock;
  reg  if2_datRAM_0_datMem_6_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_6_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_7 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_7_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_7_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_7_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_7_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_7_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_7_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_7_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_7_clock;
  reg  if2_datRAM_0_datMem_7_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_7_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_8 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_8_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_8_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_8_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_8_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_8_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_8_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_8_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_8_clock;
  reg  if2_datRAM_0_datMem_8_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_8_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_9 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_9_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_9_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_9_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_9_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_9_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_9_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_9_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_9_clock;
  reg  if2_datRAM_0_datMem_9_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_9_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_10 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_10_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_10_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_10_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_10_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_10_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_10_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_10_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_10_clock;
  reg  if2_datRAM_0_datMem_10_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_10_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_11 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_11_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_11_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_11_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_11_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_11_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_11_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_11_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_11_clock;
  reg  if2_datRAM_0_datMem_11_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_11_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_12 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_12_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_12_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_12_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_12_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_12_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_12_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_12_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_12_clock;
  reg  if2_datRAM_0_datMem_12_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_12_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_13 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_13_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_13_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_13_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_13_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_13_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_13_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_13_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_13_clock;
  reg  if2_datRAM_0_datMem_13_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_13_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_14 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_14_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_14_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_14_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_14_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_14_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_14_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_14_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_14_clock;
  reg  if2_datRAM_0_datMem_14_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_14_MPORT_addr_pipe_0;
  reg [7:0] if2_datRAM_0_datMem_15 [0:1]; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_15_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_15_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_15_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] if2_datRAM_0_datMem_15_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_15_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_15_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_15_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  if2_datRAM_0_datMem_15_clock;
  reg  if2_datRAM_0_datMem_15_MPORT_en_pipe_0;
  reg  if2_datRAM_0_datMem_15_MPORT_addr_pipe_0;
  wire  if2_tagRAM_0_clock;
  wire  if2_tagRAM_0_io_addrr;
  wire  if2_tagRAM_0_io_addrw;
  wire [26:0] if2_tagRAM_0_io_dataw;
  wire [26:0] if2_tagRAM_0_io_datar;
  wire  if2_tagRAM_0_io_enw;
  wire  if2_tagRAM_0_io_enr;
  reg [26:0] if2_tagRAM_0_tagMem [0:1]; // @[CacheRAM.scala 152:27]
  wire  if2_tagRAM_0_tagMem_io_datar_MPORT_en; // @[CacheRAM.scala 152:27]
  wire  if2_tagRAM_0_tagMem_io_datar_MPORT_addr; // @[CacheRAM.scala 152:27]
  wire [26:0] if2_tagRAM_0_tagMem_io_datar_MPORT_data; // @[CacheRAM.scala 152:27]
  wire [26:0] if2_tagRAM_0_tagMem_MPORT_data; // @[CacheRAM.scala 152:27]
  wire  if2_tagRAM_0_tagMem_MPORT_addr; // @[CacheRAM.scala 152:27]
  wire  if2_tagRAM_0_tagMem_MPORT_mask; // @[CacheRAM.scala 152:27]
  wire  if2_tagRAM_0_tagMem_MPORT_en; // @[CacheRAM.scala 152:27]
  wire  if2_tagRAM_0_tagMem_clock;
  reg  if2_tagRAM_0_tagMem_io_datar_MPORT_en_pipe_0;
  reg  if2_tagRAM_0_tagMem_io_datar_MPORT_addr_pipe_0;
  wire  if2__T = if2_io_icache_access_ready & if2_io_icache_access_valid; // @[Decoupled.scala 52:35]
  wire [10:0] if2__beats1_decode_T_1 = 11'hf << if2_io_icache_access_bits_size; // @[package.scala 234:77]
  wire [3:0] if2__beats1_decode_T_2 = if2__beats1_decode_T_1[3:0]; // @[package.scala 234:82]
  wire [3:0] if2__beats1_decode_T_3 = ~if2__beats1_decode_T_2; // @[package.scala 234:46]
  wire  if2_beats1_decode = if2__beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  if2_beats1_opdata = if2_io_icache_access_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  if2_beats1 = if2_beats1_opdata & if2_beats1_decode; // @[Edges.scala 220:14]
  reg  if2_counter; // @[Edges.scala 228:27]
  wire  if2_counter1 = if2_counter - 1'h1; // @[Edges.scala 229:28]
  wire  if2_first = ~if2_counter; // @[Edges.scala 230:25]
  wire  if2__last_T_1 = ~if2_beats1; // @[Edges.scala 231:47]
  wire  if2_last = if2_counter | if2__last_T_1; // @[Edges.scala 231:37]
  wire  if2_is_trans_done = if2_last & if2__T; // @[Edges.scala 232:22]
  reg [63:0] if2_icache_access_data_lo_0; // @[IF2.scala 70:34]
  reg  if2_kill_trans; // @[IF2.scala 71:27]
  wire  if2_cl_sel = if2_io_mmu_if_bits_paddr[4]; // @[IF2.scala 79:36]
  wire [26:0] if2_tag_sel = if2_io_mmu_if_bits_paddr[31:5]; // @[IF2.scala 80:37]
  wire  if2__res_T = if2_tagRAM_0_io_datar == if2_tag_sel; // @[IF2.scala 189:29]
  reg  if2_is_valid_1_0; // @[IF2.scala 180:25]
  reg  if2_is_valid_0_0; // @[IF2.scala 180:25]
  wire  if2__GEN_4 = if2_cl_sel ? if2_is_valid_1_0 : if2_is_valid_0_0; // @[IF2.scala 189:{42,42}]
  wire  if2_res_0 = if2__res_T & if2__GEN_4; // @[IF2.scala 189:42]
  wire  if2_is_hit = |if2_res_0; // @[IF2.scala 86:33]
  reg [3:0] if2_icache_state_qout; // @[IF2.scala 98:34]
  reg  if2_fault_lock; // @[IF2.scala 100:27]
  wire  if2__io_mmu_if_ready_T_1 = ~if2_fault_lock; // @[IF2.scala 113:44]
  wire  if2__io_mmu_if_ready_T_2 = if2_ibuf__T & if2__io_mmu_if_ready_T_1; // @[IF2.scala 113:42]
  wire  if2__io_mmu_if_ready_T_3 = if2_io_mmu_if_bits_is_access_fault | if2_io_mmu_if_bits_is_paging_fault; // @[MMU.scala 77:34]
  wire  if2__io_mmu_if_ready_T_4 = ~if2__io_mmu_if_ready_T_3; // @[IF2.scala 113:58]
  wire  if2__is_access_fault_T = if2_io_mmu_if_valid & if2_io_mmu_if_bits_is_access_fault; // @[IF2.scala 117:38]
  wire  if2__is_paging_fault_T = if2_io_mmu_if_valid & if2_io_mmu_if_bits_is_paging_fault; // @[IF2.scala 118:38]
  wire  if2__T_2 = if2_io_mmu_if_valid & if2__io_mmu_if_ready_T_3; // @[IF2.scala 121:30]
  wire  if2__T_3 = ~if2_io_flush; // @[IF2.scala 121:58]
  wire  if2__T_4 = if2__T_2 & if2__T_3; // @[IF2.scala 121:56]
  wire  if2__T_6 = if2__T_4 & if2_ibuf__T; // @[IF2.scala 121:68]
  wire  if2__GEN_1 = if2__T_6 | if2_fault_lock; // @[IF2.scala 121:105 100:27 121:92]
  wire  if2__T_7 = if2__is_access_fault_T & if2__is_paging_fault_T; // @[IF2.scala 123:29]
  wire  if2__T_8 = ~if2__T_7; // @[IF2.scala 123:11]
  wire  if2__T_10 = ~if2_reset; // @[IF2.scala 123:9]
  wire  if2__T_11 = ~if2__T_8; // @[IF2.scala 123:9]
  wire  if2__icache_state_dnxt_T = if2_icache_state_qout == 4'h0; // @[IF2.scala 133:26]
  wire  if2__icache_state_dnxt_T_3 = if2_io_mmu_if_valid & if2__io_mmu_if_ready_T_4; // @[IF2.scala 134:32]
  wire  if2__icache_state_dnxt_T_5 = if2__icache_state_dnxt_T_3 & if2__T_3; // @[IF2.scala 134:59]
  wire  if2__icache_state_dnxt_T_6 = if2__icache_state_dnxt_T_5 & if2_ibuf_io_enq_3_ready; // @[IF2.scala 134:71]
  wire  if2__icache_state_dnxt_T_8 = if2__icache_state_dnxt_T_6 & if2__io_mmu_if_ready_T_1; // @[IF2.scala 134:100]
  wire  if2__icache_state_dnxt_T_10 = if2_icache_state_qout == 4'h1; // @[IF2.scala 135:26]
  wire  if2__icache_state_dnxt_T_11 = if2_io_icache_get_ready & if2_io_icache_get_valid; // @[Decoupled.scala 52:35]
  wire [1:0] if2__icache_state_dnxt_T_12 = if2__icache_state_dnxt_T_11 ? 2'h2 : 2'h1; // @[IF2.scala 138:26]
  wire [1:0] if2__icache_state_dnxt_T_13 = if2_is_hit ? 2'h0 : if2__icache_state_dnxt_T_12; // @[IF2.scala 137:14]
  wire [1:0] if2__icache_state_dnxt_T_14 = if2_io_flush ? 2'h0 : if2__icache_state_dnxt_T_13; // @[IF2.scala 136:12]
  wire  if2__icache_state_dnxt_T_15 = if2_icache_state_qout == 4'h2; // @[IF2.scala 139:26]
  wire [1:0] if2__icache_state_dnxt_T_16 = if2_is_trans_done ? 2'h0 : 2'h2; // @[IF2.scala 140:14]
  wire  if2__icache_state_dnxt_T_17 = if2__icache_state_dnxt_T & if2__icache_state_dnxt_T_8; // @[Mux.scala 27:73]
  wire [1:0] if2__icache_state_dnxt_T_18 = if2__icache_state_dnxt_T_10 ? if2__icache_state_dnxt_T_14 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] if2__icache_state_dnxt_T_19 = if2__icache_state_dnxt_T_15 ? if2__icache_state_dnxt_T_16 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_140 = {{1'd0}, if2__icache_state_dnxt_T_17}; // @[Mux.scala 27:73]
  wire [1:0] if2__icache_state_dnxt_T_20 = _GEN_140 | if2__icache_state_dnxt_T_18; // @[Mux.scala 27:73]
  wire [1:0] if2__icache_state_dnxt_T_21 = if2__icache_state_dnxt_T_20 | if2__icache_state_dnxt_T_19; // @[Mux.scala 27:73]
  wire [3:0] if2_icache_state_dnxt = {{2'd0}, if2__icache_state_dnxt_T_21}; // @[IF2.scala 131:21 97:31]
  wire  if2__datRAM_0_io_enw_T_1 = if2_icache_state_dnxt == 4'h0; // @[IF2.scala 244:73]
  wire  if2__datRAM_0_io_enw_T_2 = if2__icache_state_dnxt_T_15 & if2__datRAM_0_io_enw_T_1; // @[IF2.scala 244:53]
  wire  if2__datRAM_0_io_enw_T_5 = ~if2_kill_trans; // @[IF2.scala 244:103]
  wire  if2__datRAM_0_io_enw_T_6 = if2__datRAM_0_io_enw_T_2 & if2__datRAM_0_io_enw_T_5; // @[IF2.scala 244:101]
  wire  if2__datRAM_0_io_enw_T_8 = if2__datRAM_0_io_enw_T_6 & if2__T_3; // @[IF2.scala 244:115]
  wire [127:0] if2__icache_access_data_T = {if2_io_icache_access_bits_data,if2_icache_access_data_lo_0}; // @[Cat.scala 33:92]
  wire [63:0] if2_icache_sramrd_data_lo = {if2_datRAM_0_io_datar_7,if2_datRAM_0_io_datar_6,if2_datRAM_0_io_datar_5,
    if2_datRAM_0_io_datar_4,if2_datRAM_0_io_datar_3,if2_datRAM_0_io_datar_2,if2_datRAM_0_io_datar_1,
    if2_datRAM_0_io_datar_0}; // @[Cat.scala 33:92]
  wire [127:0] if2__icache_sramrd_data_T = {if2_datRAM_0_io_datar_15,if2_datRAM_0_io_datar_14,if2_datRAM_0_io_datar_13,
    if2_datRAM_0_io_datar_12,if2_datRAM_0_io_datar_11,if2_datRAM_0_io_datar_10,if2_datRAM_0_io_datar_9,
    if2_datRAM_0_io_datar_8,if2_icache_sramrd_data_lo}; // @[Cat.scala 33:92]
  wire  if2__GEN_5 = ~if2_cl_sel | if2_is_valid_0_0; // @[IF2.scala 180:25 266:{30,30}]
  wire  if2__GEN_6 = if2_cl_sel | if2_is_valid_1_0; // @[IF2.scala 180:25 266:{30,30}]
  wire  if2__io_icache_get_valid_T_1 = ~if2_is_hit; // @[IF2.scala 282:54]
  wire  if2__io_icache_get_valid_T_2 = if2__icache_state_dnxt_T_10 & if2__io_icache_get_valid_T_1; // @[IF2.scala 282:52]
  wire [31:0] if2__io_icache_get_bits_T = if2_io_mmu_if_bits_paddr[31:0]; // @[IF2.scala 286:39]
  wire [38:0] _GEN_142 = {{7'd0}, if2__io_icache_get_bits_T}; // @[IF2.scala 286:51]
  wire [38:0] if2__io_icache_get_bits_T_2 = _GEN_142 & 39'hffffffff0; // @[IF2.scala 286:51]
  wire  if2__T_42 = ~if2_is_trans_done; // @[IF2.scala 292:33]
  wire  if2__T_43 = if2__T & if2__T_42; // @[IF2.scala 292:31]
  reg [63:0] if2_REG; // @[IF2.scala 300:21]
  wire  if2__T_44 = if2_REG != if2_io_mmu_if_bits_paddr; // @[IF2.scala 300:44]
  wire  if2__T_46 = if2__T_44 & if2__icache_state_dnxt_T_15; // @[IF2.scala 300:70]
  reg  if2_REG_1; // @[IF2.scala 300:108]
  wire  if2__T_47 = ~if2_REG_1; // @[IF2.scala 300:100]
  wire  if2__T_48 = if2__T_46 & if2__T_47; // @[IF2.scala 300:98]
  reg  if2_REG_2; // @[IF2.scala 300:131]
  wire  if2__T_49 = ~if2_REG_2; // @[IF2.scala 300:123]
  wire  if2__T_50 = if2__T_48 & if2__T_49; // @[IF2.scala 300:121]
  wire  if2__T_51 = ~if2__T_50; // @[IF2.scala 300:11]
  wire  if2__T_54 = ~if2__T_51; // @[IF2.scala 300:9]
  wire [2:0] if2__reAlign_instr_shift_T = if2_io_mmu_if_bits_paddr[2:0]; // @[IF2.scala 315:38]
  wire [5:0] if2__reAlign_instr_shift_T_1 = {if2__reAlign_instr_shift_T,3'h0}; // @[Cat.scala 33:92]
  wire [127:0] if2__reAlign_instr_instr_raw_T_2 = if2__icache_state_dnxt_T_10 ? if2__icache_sramrd_data_T : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] if2__reAlign_instr_instr_raw_T_3 = if2__icache_state_dnxt_T_15 ? if2__icache_access_data_T : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] if2__reAlign_instr_instr_raw_T_4 = if2__reAlign_instr_instr_raw_T_2 | if2__reAlign_instr_instr_raw_T_3; // @[Mux.scala 27:73]
  wire  if2__reAlign_instr_instr_raw_T_5 = if2_io_mmu_if_bits_paddr[3]; // @[IF2.scala 322:57]
  wire [6:0] if2__reAlign_instr_instr_raw_T_6 = {if2__reAlign_instr_instr_raw_T_5, 6'h0}; // @[IF2.scala 322:100]
  wire [127:0] if2__reAlign_instr_instr_raw_T_7 = if2__reAlign_instr_instr_raw_T_4 >> if2__reAlign_instr_instr_raw_T_6; // @[IF2.scala 322:12]
  wire [63:0] if2_reAlign_instr_instr_raw = if2__reAlign_instr_instr_raw_T_7[63:0]; // @[IF2.scala 317:25 318:15]
  wire [63:0] if2__reAlign_instr_res_T = if2_reAlign_instr_instr_raw >> if2__reAlign_instr_shift_T_1; // @[IF2.scala 324:22]
  wire [64:0] if2__ibuf_io_enq_0_bits_pc_T = {{1'd0}, if2_io_mmu_if_bits_vaddr}; // @[IF2.scala 332:55]
  wire [63:0] if2__ibuf_io_enq_0_bits_pc_T_1 = if2__ibuf_io_enq_0_bits_pc_T[63:0]; // @[IF2.scala 332:55]
  wire [47:0] if2__ibuf_io_enq_1_bits_instr_T = if2__reAlign_instr_res_T[63:16]; // @[IF2.scala 331:48]
  wire [63:0] if2__ibuf_io_enq_1_bits_pc_T_1 = if2_io_mmu_if_bits_vaddr + 64'h2; // @[IF2.scala 332:55]
  wire [31:0] if2__ibuf_io_enq_2_bits_instr_T = if2__reAlign_instr_res_T[63:32]; // @[IF2.scala 331:48]
  wire [63:0] if2__ibuf_io_enq_2_bits_pc_T_1 = if2_io_mmu_if_bits_vaddr + 64'h4; // @[IF2.scala 332:55]
  wire [63:0] if2__ibuf_io_enq_3_bits_pc_T_1 = if2_io_mmu_if_bits_vaddr + 64'h6; // @[IF2.scala 332:55]
  wire [63:0] if2__GEN_12 = if2__is_paging_fault_T ? 64'h9c45 : if2__reAlign_instr_res_T; // @[IF2.scala 331:31 350:67 351:31]
  wire [63:0] if2__GEN_13 = if2__is_paging_fault_T ? if2_io_if2_req_bits_pc : if2__ibuf_io_enq_0_bits_pc_T_1; // @[IF2.scala 332:31 350:67 352:31]
  wire [63:0] if2__GEN_16 = if2__is_access_fault_T ? 64'h9c41 : if2__GEN_12; // @[IF2.scala 343:60 344:31]
  wire [63:0] if2__GEN_17 = if2__is_access_fault_T ? if2_io_if2_req_bits_pc : if2__GEN_13; // @[IF2.scala 343:60 345:31]
  wire  if2__ibuf_io_enq_0_valid_T_1 = if2__datRAM_0_io_enw_T_5 & if2_io_mmu_if_valid; // @[IF2.scala 361:18]
  wire  if2__ibuf_io_enq_0_valid_T_2 = if2_icache_state_qout != 4'h0; // @[IF2.scala 361:56]
  wire  if2__ibuf_io_enq_0_valid_T_3 = if2__ibuf_io_enq_0_valid_T_1 & if2__ibuf_io_enq_0_valid_T_2; // @[IF2.scala 361:36]
  wire  if2__ibuf_io_enq_0_valid_T_5 = if2__ibuf_io_enq_0_valid_T_3 & if2__datRAM_0_io_enw_T_1; // @[IF2.scala 361:64]
  wire  if2__ibuf_io_enq_0_valid_T_6 = if2__ibuf_io_enq_0_valid_T_5 & if2_ibuf_io_enq_3_ready; // @[IF2.scala 361:92]
  wire [1:0] if2__ibuf_io_enq_0_valid_T_7 = if2_io_mmu_if_bits_paddr[2:1]; // @[IF2.scala 361:145]
  wire  if2__ibuf_io_enq_0_valid_T_10 = if2__ibuf_io_enq_0_valid_T_6 & if2_io_if2_req_bits_isActive_0; // @[IF2.scala 361:191]
  wire  if2__ibuf_io_enq_0_valid_T_14 = if2__ibuf_io_enq_0_valid_T_1 & if2__io_mmu_if_ready_T_3; // @[IF2.scala 362:36]
  wire  if2__ibuf_io_enq_0_valid_T_16 = if2__ibuf_io_enq_0_valid_T_14 & if2__io_mmu_if_ready_T_1; // @[IF2.scala 362:62]
  wire  if2__ibuf_io_enq_1_valid_T_8 = if2__ibuf_io_enq_0_valid_T_7 <= 2'h2; // @[IF2.scala 365:197]
  wire  if2__ibuf_io_enq_1_valid_T_9 = if2__ibuf_io_enq_0_valid_T_6 & if2__ibuf_io_enq_1_valid_T_8; // @[IF2.scala 365:144]
  wire  if2__ibuf_io_enq_2_valid_T_8 = if2__ibuf_io_enq_0_valid_T_7 <= 2'h1; // @[IF2.scala 365:197]
  wire  if2__ibuf_io_enq_2_valid_T_9 = if2__ibuf_io_enq_0_valid_T_6 & if2__ibuf_io_enq_2_valid_T_8; // @[IF2.scala 365:144]
  wire  if2__ibuf_io_enq_3_valid_T_8 = if2__ibuf_io_enq_0_valid_T_7 <= 2'h0; // @[IF2.scala 365:197]
  wire  if2__ibuf_io_enq_3_valid_T_9 = if2__ibuf_io_enq_0_valid_T_6 & if2__ibuf_io_enq_3_valid_T_8; // @[IF2.scala 365:144]
  wire  if2__T_58 = if2_io_flush & if2__ibuf_io_enq_0_valid_T_2; // @[IF2.scala 371:18]
  wire  if2__T_61 = if2__datRAM_0_io_enw_T_1 | if2__icache_state_dnxt_T; // @[IF2.scala 373:42]
  wire  if2__GEN_20 = if2__T_61 ? 1'h0 : if2_kill_trans; // @[IF2.scala 373:72 374:16 71:27]
  wire  if2__GEN_21 = if2__T_58 | if2__GEN_20; // @[IF2.scala 371:48 372:16]
  wire  if3_clock;
  wire  if3_reset;
  wire  if3_io_if3_req_0_ready;
  wire  if3_io_if3_req_0_valid;
  wire [38:0] if3_io_if3_req_0_bits_pc;
  wire [15:0] if3_io_if3_req_0_bits_instr;
  wire  if3_io_if3_req_0_bits_isRedirect;
  wire  if3_io_if3_req_1_ready;
  wire  if3_io_if3_req_1_valid;
  wire [38:0] if3_io_if3_req_1_bits_pc;
  wire [15:0] if3_io_if3_req_1_bits_instr;
  wire  if3_io_if3_req_1_bits_isFault;
  wire  if3_io_if3_req_1_bits_isRedirect;
  wire  if3_io_if3_req_2_ready;
  wire  if3_io_if3_req_2_valid;
  wire [38:0] if3_io_if3_req_2_bits_pc;
  wire [15:0] if3_io_if3_req_2_bits_instr;
  wire  if3_io_if3_req_2_bits_isFault;
  wire  if3_io_if3_req_2_bits_isRedirect;
  wire  if3_io_if3_req_3_ready;
  wire  if3_io_if3_req_3_valid;
  wire [38:0] if3_io_if3_req_3_bits_pc;
  wire [15:0] if3_io_if3_req_3_bits_instr;
  wire  if3_io_if3_req_3_bits_isFault;
  wire  if3_io_if3_req_3_bits_isRedirect;
  wire  if3_io_if3_resp_0_ready;
  wire  if3_io_if3_resp_0_valid;
  wire  if3_io_if3_resp_0_bits_isRVC;
  wire [31:0] if3_io_if3_resp_0_bits_instr;
  wire [38:0] if3_io_if3_resp_0_bits_pc;
  wire  if3_io_if3_resp_0_bits_isRedirect;
  wire [38:0] if3_io_if3_resp_0_bits_target;
  wire  if3_io_btbResp_0_ready;
  wire  if3_io_btbResp_0_valid;
  wire [38:0] if3_io_btbResp_0_bits_target;
  wire  if3_io_bimResp_0_ready;
  wire  if3_io_bimResp_0_valid;
  wire  if3_io_bimResp_0_bits_bim_p;
  wire  if3_io_bimResp_0_bits_bim_h;
  wire  if3_io_tageResp_0_ready;
  wire  if3_io_jcmm_update_valid;
  wire [38:0] if3_io_jcmm_update_bits_pc;
  wire [63:0] if3_io_jcmm_update_bits_finalTarget;
  wire  if3_io_bcmm_update_valid;
  wire [38:0] if3_io_bcmm_update_bits_pc;
  wire  if3_io_bcmm_update_bits_bimResp_bim_p;
  wire  if3_io_bcmm_update_bits_bimResp_bim_h;
  wire  if3_io_bcmm_update_bits_isFinalTaken;
  wire  if3_io_if4Redirect_valid;
  wire  if3_io_flush;
  wire  if3_combPDT_clock;
  wire  if3_combPDT_reset;
  wire  if3_combPDT_io_enq_0_ready;
  wire  if3_combPDT_io_enq_0_valid;
  wire  if3_combPDT_io_enq_0_bits_isRVC;
  wire [31:0] if3_combPDT_io_enq_0_bits_instr;
  wire [38:0] if3_combPDT_io_enq_0_bits_pc;
  wire  if3_combPDT_io_enq_1_ready;
  wire  if3_combPDT_io_enq_1_valid;
  wire  if3_combPDT_io_enq_1_bits_isRVC;
  wire [31:0] if3_combPDT_io_enq_1_bits_instr;
  wire [38:0] if3_combPDT_io_enq_1_bits_pc;
  wire  if3_combPDT_io_enq_2_ready;
  wire  if3_combPDT_io_enq_2_valid;
  wire  if3_combPDT_io_enq_2_bits_isRVC;
  wire [31:0] if3_combPDT_io_enq_2_bits_instr;
  wire [38:0] if3_combPDT_io_enq_2_bits_pc;
  wire  if3_combPDT_io_enq_3_ready;
  wire  if3_combPDT_io_enq_3_valid;
  wire  if3_combPDT_io_enq_3_bits_isRVC;
  wire [31:0] if3_combPDT_io_enq_3_bits_instr;
  wire [38:0] if3_combPDT_io_enq_3_bits_pc;
  wire  if3_combPDT_io_deq_0_ready;
  wire  if3_combPDT_io_deq_0_valid;
  wire  if3_combPDT_io_deq_0_bits_isRVC;
  wire [31:0] if3_combPDT_io_deq_0_bits_instr;
  wire [38:0] if3_combPDT_io_deq_0_bits_pc;
  wire  if3_combPDT_io_deq_0_bits_isRedirect;
  wire [38:0] if3_combPDT_io_deq_0_bits_target;
  wire  if3_combPDT_io_deq_1_ready;
  wire  if3_combPDT_io_deq_1_valid;
  wire  if3_combPDT_io_deq_1_bits_isRVC;
  wire [31:0] if3_combPDT_io_deq_1_bits_instr;
  wire [38:0] if3_combPDT_io_deq_1_bits_pc;
  wire  if3_combPDT_io_deq_1_bits_isRedirect;
  wire [38:0] if3_combPDT_io_deq_1_bits_target;
  wire  if3_combPDT_io_deq_2_ready;
  wire  if3_combPDT_io_deq_2_valid;
  wire  if3_combPDT_io_deq_2_bits_isRVC;
  wire [31:0] if3_combPDT_io_deq_2_bits_instr;
  wire [38:0] if3_combPDT_io_deq_2_bits_pc;
  wire  if3_combPDT_io_deq_2_bits_isRedirect;
  wire [38:0] if3_combPDT_io_deq_2_bits_target;
  wire  if3_combPDT_io_deq_3_ready;
  wire  if3_combPDT_io_deq_3_valid;
  wire  if3_combPDT_io_deq_3_bits_isRVC;
  wire [31:0] if3_combPDT_io_deq_3_bits_instr;
  wire [38:0] if3_combPDT_io_deq_3_bits_pc;
  wire  if3_combPDT_io_deq_3_bits_isRedirect;
  wire [38:0] if3_combPDT_io_deq_3_bits_target;
  wire  if3_combPDT__T = if3_combPDT_io_enq_0_ready & if3_combPDT_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_combPDT__T_1 = if3_combPDT_io_enq_1_ready & if3_combPDT_io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  if3_combPDT__T_2 = if3_combPDT_io_enq_2_ready & if3_combPDT_io_enq_2_valid; // @[Decoupled.scala 52:35]
  wire  if3_combPDT__T_3 = if3_combPDT_io_enq_3_ready & if3_combPDT_io_enq_3_valid; // @[Decoupled.scala 52:35]
  wire [1:0] if3_combPDT__T_4 = if3_combPDT__T + if3_combPDT__T_1; // @[Bitwise.scala 51:90]
  wire [1:0] if3_combPDT__T_6 = if3_combPDT__T_2 + if3_combPDT__T_3; // @[Bitwise.scala 51:90]
  wire [2:0] if3_combPDT__T_8 = if3_combPDT__T_4 + if3_combPDT__T_6; // @[Bitwise.scala 51:90]
  wire  if3_combPDT__T_10 = if3_combPDT_io_deq_0_ready & if3_combPDT_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_combPDT__T_11 = if3_combPDT_io_deq_1_ready & if3_combPDT_io_deq_1_valid; // @[Decoupled.scala 52:35]
  wire  if3_combPDT__T_12 = if3_combPDT_io_deq_2_ready & if3_combPDT_io_deq_2_valid; // @[Decoupled.scala 52:35]
  wire  if3_combPDT__T_13 = if3_combPDT_io_deq_3_ready & if3_combPDT_io_deq_3_valid; // @[Decoupled.scala 52:35]
  wire [1:0] if3_combPDT__T_14 = if3_combPDT__T_10 + if3_combPDT__T_11; // @[Bitwise.scala 51:90]
  wire [1:0] if3_combPDT__T_16 = if3_combPDT__T_12 + if3_combPDT__T_13; // @[Bitwise.scala 51:90]
  wire [2:0] if3_combPDT__T_18 = if3_combPDT__T_14 + if3_combPDT__T_16; // @[Bitwise.scala 51:90]
  wire  if3_combPDT__T_20 = if3_combPDT__T_8 == if3_combPDT__T_18; // @[RePort.scala 32:45]
  wire  if3_combPDT__T_22 = ~if3_combPDT_reset; // @[RePort.scala 32:12]
  wire  if3_combPDT__T_23 = ~if3_combPDT__T_20; // @[RePort.scala 32:12]
  wire [3:0] if3_combPDT_in = {if3_combPDT_io_enq_3_valid,if3_combPDT_io_enq_2_valid,if3_combPDT_io_enq_1_valid,
    if3_combPDT_io_enq_0_valid}; // @[RePort.scala 61:48]
  wire  if3_combPDT__is_end_0_T = if3_combPDT_in == 4'h0; // @[RePort.scala 62:21]
  wire  if3_combPDT__sel_0_T = if3_combPDT_in[0]; // @[RePort.scala 63:26]
  wire  if3_combPDT__sel_0_T_1 = if3_combPDT_in[1]; // @[RePort.scala 63:26]
  wire  if3_combPDT__sel_0_T_2 = if3_combPDT_in[2]; // @[RePort.scala 63:26]
  wire [1:0] if3_combPDT__sel_0_T_8 = if3_combPDT__sel_0_T_2 ? 2'h2 : 2'h3; // @[RePort.scala 63:45]
  wire [1:0] if3_combPDT__sel_0_T_9 = if3_combPDT__sel_0_T_1 ? 2'h1 : if3_combPDT__sel_0_T_8; // @[RePort.scala 63:45]
  wire [1:0] if3_combPDT__sel_0_T_10 = if3_combPDT__sel_0_T ? 2'h0 : if3_combPDT__sel_0_T_9; // @[RePort.scala 63:45]
  wire [3:0] if3_combPDT__in_next_0_T = 4'h1 << if3_combPDT__sel_0_T_10; // @[OneHot.scala 57:35]
  wire [3:0] if3_combPDT__in_next_0_T_1 = ~if3_combPDT__in_next_0_T; // @[RePort.scala 64:24]
  wire [3:0] if3_combPDT__in_next_0_T_2 = if3_combPDT_in & if3_combPDT__in_next_0_T_1; // @[RePort.scala 64:22]
  wire  if3_combPDT__is_end_1_T = if3_combPDT__in_next_0_T_2 == 4'h0; // @[RePort.scala 69:21]
  wire  if3_combPDT__sel_1_T = if3_combPDT__in_next_0_T_2[0]; // @[RePort.scala 70:26]
  wire  if3_combPDT__sel_1_T_1 = if3_combPDT__in_next_0_T_2[1]; // @[RePort.scala 70:26]
  wire  if3_combPDT__sel_1_T_2 = if3_combPDT__in_next_0_T_2[2]; // @[RePort.scala 70:26]
  wire [1:0] if3_combPDT__sel_1_T_8 = if3_combPDT__sel_1_T_2 ? 2'h2 : 2'h3; // @[RePort.scala 70:45]
  wire [1:0] if3_combPDT__sel_1_T_9 = if3_combPDT__sel_1_T_1 ? 2'h1 : if3_combPDT__sel_1_T_8; // @[RePort.scala 70:45]
  wire [1:0] if3_combPDT__sel_1_T_10 = if3_combPDT__sel_1_T ? 2'h0 : if3_combPDT__sel_1_T_9; // @[RePort.scala 70:45]
  wire [3:0] if3_combPDT__in_next_1_T = 4'h1 << if3_combPDT__sel_1_T_10; // @[OneHot.scala 57:35]
  wire [3:0] if3_combPDT__in_next_1_T_1 = ~if3_combPDT__in_next_1_T; // @[RePort.scala 71:24]
  wire [3:0] if3_combPDT__in_next_1_T_2 = if3_combPDT__in_next_0_T_2 & if3_combPDT__in_next_1_T_1; // @[RePort.scala 71:22]
  wire  if3_combPDT__is_end_2_T = if3_combPDT__in_next_1_T_2 == 4'h0; // @[RePort.scala 69:21]
  wire  if3_combPDT__sel_2_T = if3_combPDT__in_next_1_T_2[0]; // @[RePort.scala 70:26]
  wire  if3_combPDT__sel_2_T_1 = if3_combPDT__in_next_1_T_2[1]; // @[RePort.scala 70:26]
  wire  if3_combPDT__sel_2_T_2 = if3_combPDT__in_next_1_T_2[2]; // @[RePort.scala 70:26]
  wire [1:0] if3_combPDT__sel_2_T_8 = if3_combPDT__sel_2_T_2 ? 2'h2 : 2'h3; // @[RePort.scala 70:45]
  wire [1:0] if3_combPDT__sel_2_T_9 = if3_combPDT__sel_2_T_1 ? 2'h1 : if3_combPDT__sel_2_T_8; // @[RePort.scala 70:45]
  wire [1:0] if3_combPDT__sel_2_T_10 = if3_combPDT__sel_2_T ? 2'h0 : if3_combPDT__sel_2_T_9; // @[RePort.scala 70:45]
  wire [3:0] if3_combPDT__in_next_2_T = 4'h1 << if3_combPDT__sel_2_T_10; // @[OneHot.scala 57:35]
  wire [3:0] if3_combPDT__in_next_2_T_1 = ~if3_combPDT__in_next_2_T; // @[RePort.scala 71:24]
  wire [3:0] if3_combPDT__in_next_2_T_2 = if3_combPDT__in_next_1_T_2 & if3_combPDT__in_next_2_T_1; // @[RePort.scala 71:22]
  wire  if3_combPDT__is_end_3_T = if3_combPDT__in_next_2_T_2 == 4'h0; // @[RePort.scala 69:21]
  wire  if3_combPDT__sel_3_T = if3_combPDT__in_next_2_T_2[0]; // @[RePort.scala 70:26]
  wire  if3_combPDT__sel_3_T_1 = if3_combPDT__in_next_2_T_2[1]; // @[RePort.scala 70:26]
  wire  if3_combPDT__sel_3_T_2 = if3_combPDT__in_next_2_T_2[2]; // @[RePort.scala 70:26]
  wire [1:0] if3_combPDT__sel_3_T_8 = if3_combPDT__sel_3_T_2 ? 2'h2 : 2'h3; // @[RePort.scala 70:45]
  wire [1:0] if3_combPDT__sel_3_T_9 = if3_combPDT__sel_3_T_1 ? 2'h1 : if3_combPDT__sel_3_T_8; // @[RePort.scala 70:45]
  wire [1:0] if3_combPDT__sel_3_T_10 = if3_combPDT__sel_3_T ? 2'h0 : if3_combPDT__sel_3_T_9; // @[RePort.scala 70:45]
  wire  if3_combPDT__T_24 = ~if3_combPDT__is_end_0_T; // @[RePort.scala 75:11]
  wire  if3_combPDT__GEN_1 = 2'h1 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_1_bits_isRVC :
    if3_combPDT_io_enq_0_bits_isRVC; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__GEN_2 = 2'h2 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_2_bits_isRVC : if3_combPDT__GEN_1; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__GEN_3 = 2'h3 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_3_bits_isRVC : if3_combPDT__GEN_2; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_41 = 2'h1 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_1_bits_instr :
    if3_combPDT_io_enq_0_bits_instr; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_42 = 2'h2 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_2_bits_instr :
    if3_combPDT__GEN_41; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_43 = 2'h3 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_3_bits_instr :
    if3_combPDT__GEN_42; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_45 = 2'h1 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_1_bits_pc :
    if3_combPDT_io_enq_0_bits_pc; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_46 = 2'h2 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_2_bits_pc : if3_combPDT__GEN_45
    ; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_47 = 2'h3 == if3_combPDT__sel_0_T_10 ? if3_combPDT_io_enq_3_bits_pc : if3_combPDT__GEN_46
    ; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__T_25 = ~if3_combPDT__is_end_1_T; // @[RePort.scala 75:11]
  wire  if3_combPDT__GEN_76 = 2'h1 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_1_bits_isRVC :
    if3_combPDT_io_enq_0_bits_isRVC; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__GEN_77 = 2'h2 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_2_bits_isRVC : if3_combPDT__GEN_76; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__GEN_78 = 2'h3 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_3_bits_isRVC : if3_combPDT__GEN_77; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_116 = 2'h1 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_1_bits_instr :
    if3_combPDT_io_enq_0_bits_instr; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_117 = 2'h2 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_2_bits_instr :
    if3_combPDT__GEN_116; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_118 = 2'h3 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_3_bits_instr :
    if3_combPDT__GEN_117; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_120 = 2'h1 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_1_bits_pc :
    if3_combPDT_io_enq_0_bits_pc; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_121 = 2'h2 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_2_bits_pc :
    if3_combPDT__GEN_120; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_122 = 2'h3 == if3_combPDT__sel_1_T_10 ? if3_combPDT_io_enq_3_bits_pc :
    if3_combPDT__GEN_121; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__T_26 = ~if3_combPDT__is_end_2_T; // @[RePort.scala 75:11]
  wire  if3_combPDT__GEN_151 = 2'h1 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_1_bits_isRVC :
    if3_combPDT_io_enq_0_bits_isRVC; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__GEN_152 = 2'h2 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_2_bits_isRVC : if3_combPDT__GEN_151; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__GEN_153 = 2'h3 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_3_bits_isRVC : if3_combPDT__GEN_152; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_191 = 2'h1 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_1_bits_instr :
    if3_combPDT_io_enq_0_bits_instr; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_192 = 2'h2 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_2_bits_instr :
    if3_combPDT__GEN_191; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_193 = 2'h3 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_3_bits_instr :
    if3_combPDT__GEN_192; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_195 = 2'h1 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_1_bits_pc :
    if3_combPDT_io_enq_0_bits_pc; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_196 = 2'h2 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_2_bits_pc :
    if3_combPDT__GEN_195; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_197 = 2'h3 == if3_combPDT__sel_2_T_10 ? if3_combPDT_io_enq_3_bits_pc :
    if3_combPDT__GEN_196; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__T_27 = ~if3_combPDT__is_end_3_T; // @[RePort.scala 75:11]
  wire  if3_combPDT__GEN_226 = 2'h1 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_1_bits_isRVC :
    if3_combPDT_io_enq_0_bits_isRVC; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__GEN_227 = 2'h2 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_2_bits_isRVC : if3_combPDT__GEN_226; // @[RePort.scala 76:{22,22}]
  wire  if3_combPDT__GEN_228 = 2'h3 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_3_bits_isRVC : if3_combPDT__GEN_227; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_266 = 2'h1 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_1_bits_instr :
    if3_combPDT_io_enq_0_bits_instr; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_267 = 2'h2 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_2_bits_instr :
    if3_combPDT__GEN_266; // @[RePort.scala 76:{22,22}]
  wire [31:0] if3_combPDT__GEN_268 = 2'h3 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_3_bits_instr :
    if3_combPDT__GEN_267; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_270 = 2'h1 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_1_bits_pc :
    if3_combPDT_io_enq_0_bits_pc; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_271 = 2'h2 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_2_bits_pc :
    if3_combPDT__GEN_270; // @[RePort.scala 76:{22,22}]
  wire [38:0] if3_combPDT__GEN_272 = 2'h3 == if3_combPDT__sel_3_T_10 ? if3_combPDT_io_enq_3_bits_pc :
    if3_combPDT__GEN_271; // @[RePort.scala 76:{22,22}]
  wire  if3_btb_clock;
  wire  if3_btb_reset;
  wire  if3_btb_io_req_ready;
  wire  if3_btb_io_req_valid;
  wire [38:0] if3_btb_io_req_bits_pc;
  wire  if3_btb_io_resp_ready;
  wire  if3_btb_io_resp_valid;
  wire [38:0] if3_btb_io_resp_bits_target;
  wire  if3_btb_io_update_valid;
  wire [38:0] if3_btb_io_update_bits_target;
  wire [38:0] if3_btb_io_update_bits_pc;
  wire  if3_btb_io_isReady;
  wire  if3_btb_bypassFifo_clock;
  wire  if3_btb_bypassFifo_reset;
  wire  if3_btb_bypassFifo_io_enq_ready;
  wire  if3_btb_bypassFifo_io_enq_valid;
  wire [38:0] if3_btb_bypassFifo_io_enq_bits_target;
  wire  if3_btb_bypassFifo_io_deq_ready;
  wire  if3_btb_bypassFifo_io_deq_valid;
  wire [38:0] if3_btb_bypassFifo_io_deq_bits_target;
  reg [38:0] if3_btb_bypassFifo_ram_target [0:0]; // @[Decoupled.scala 275:95]
  wire  if3_btb_bypassFifo_ram_target_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  if3_btb_bypassFifo_ram_target_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [38:0] if3_btb_bypassFifo_ram_target_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [38:0] if3_btb_bypassFifo_ram_target_MPORT_data; // @[Decoupled.scala 275:95]
  wire  if3_btb_bypassFifo_ram_target_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  if3_btb_bypassFifo_ram_target_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  if3_btb_bypassFifo_ram_target_MPORT_en; // @[Decoupled.scala 275:95]
  wire  if3_btb_bypassFifo_ram_target_clock;
  reg  if3_btb_bypassFifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  if3_btb_bypassFifo__empty_T = ~if3_btb_bypassFifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  if3_btb_bypassFifo__do_enq_T = if3_btb_bypassFifo_io_enq_ready & if3_btb_bypassFifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  if3_btb_bypassFifo__do_deq_T = if3_btb_bypassFifo_io_deq_ready & if3_btb_bypassFifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  if3_btb_bypassFifo__GEN_9 = if3_btb_bypassFifo_io_deq_ready ? 1'h0 : if3_btb_bypassFifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  if3_btb_bypassFifo__GEN_12 = if3_btb_bypassFifo__empty_T ? if3_btb_bypassFifo__GEN_9 :
    if3_btb_bypassFifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  if3_btb_bypassFifo__GEN_11 = if3_btb_bypassFifo__empty_T ? 1'h0 : if3_btb_bypassFifo__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  if3_btb_bypassFifo__T = if3_btb_bypassFifo__GEN_12 != if3_btb_bypassFifo__GEN_11; // @[Decoupled.scala 295:15]
  wire  if3_btb_bypassFifo__io_deq_valid_T = ~if3_btb_bypassFifo__empty_T; // @[Decoupled.scala 304:19]
  reg [38:0] if3_btb_btb_table_target [0:3]; // @[BTB.scala 54:32]
  wire  if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_en; // @[BTB.scala 54:32]
  wire [1:0] if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_addr; // @[BTB.scala 54:32]
  wire [38:0] if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_data; // @[BTB.scala 54:32]
  wire [38:0] if3_btb_btb_table_target_MPORT_data; // @[BTB.scala 54:32]
  wire [1:0] if3_btb_btb_table_target_MPORT_addr; // @[BTB.scala 54:32]
  wire  if3_btb_btb_table_target_MPORT_mask; // @[BTB.scala 54:32]
  wire  if3_btb_btb_table_target_MPORT_en; // @[BTB.scala 54:32]
  wire  if3_btb_btb_table_target_clock;
  reg  if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_en_pipe_0;
  reg [1:0] if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_addr_pipe_0;
  reg  if3_btb_por_reset; // @[BTB.scala 46:28]
  reg [1:0] if3_btb_reset_cl; // @[Counter.scala 61:40]
  wire  if3_btb_wrap_wrap = if3_btb_reset_cl == 2'h3; // @[Counter.scala 73:24]
  wire [1:0] if3_btb__wrap_value_T_1 = if3_btb_reset_cl + 2'h1; // @[Counter.scala 77:24]
  wire  if3_btb__GEN_1 = if3_btb_por_reset & if3_btb_wrap_wrap; // @[Counter.scala 136:24 137:12]
  wire  if3_btb__GEN_4 = if3_btb__GEN_1 ? 1'h0 : if3_btb_por_reset; // @[BTB.scala 48:23 46:28 48:35]
  wire [18:0] if3_btb__rd_cl_sel_out_out_T = if3_btb_io_req_bits_pc[18:0]; // @[Hash.scala 32:14]
  wire [19:0] if3_btb__rd_cl_sel_out_out_T_1 = if3_btb_io_req_bits_pc[38:19]; // @[Hash.scala 32:31]
  wire [19:0] _GEN_144 = {{1'd0}, if3_btb__rd_cl_sel_out_out_T}; // @[Hash.scala 32:27]
  wire [19:0] if3_btb__rd_cl_sel_out_out_T_2 = _GEN_144 ^ if3_btb__rd_cl_sel_out_out_T_1; // @[Hash.scala 32:27]
  wire [9:0] if3_btb__rd_cl_sel_out_out_out_T = if3_btb__rd_cl_sel_out_out_T_2[9:0]; // @[Hash.scala 32:14]
  wire [9:0] if3_btb__rd_cl_sel_out_out_out_T_1 = if3_btb__rd_cl_sel_out_out_T_2[19:10]; // @[Hash.scala 32:31]
  wire [9:0] if3_btb__rd_cl_sel_out_out_out_T_2 = if3_btb__rd_cl_sel_out_out_out_T ^ if3_btb__rd_cl_sel_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [4:0] if3_btb__rd_cl_sel_out_out_out_out_T = if3_btb__rd_cl_sel_out_out_out_T_2[4:0]; // @[Hash.scala 32:14]
  wire [4:0] if3_btb__rd_cl_sel_out_out_out_out_T_1 = if3_btb__rd_cl_sel_out_out_out_T_2[9:5]; // @[Hash.scala 32:31]
  wire [4:0] if3_btb__rd_cl_sel_out_out_out_out_T_2 = if3_btb__rd_cl_sel_out_out_out_out_T ^
    if3_btb__rd_cl_sel_out_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [1:0] if3_btb__rd_cl_sel_out_out_out_out_out_T = if3_btb__rd_cl_sel_out_out_out_out_T_2[1:0]; // @[Hash.scala 32:14]
  wire [2:0] if3_btb__rd_cl_sel_out_out_out_out_out_T_1 = if3_btb__rd_cl_sel_out_out_out_out_T_2[4:2]; // @[Hash.scala 32:31]
  wire [2:0] _GEN_145 = {{1'd0}, if3_btb__rd_cl_sel_out_out_out_out_out_T}; // @[Hash.scala 32:27]
  wire [2:0] if3_btb__rd_cl_sel_out_out_out_out_out_T_2 = _GEN_145 ^ if3_btb__rd_cl_sel_out_out_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [1:0] if3_btb__rd_cl_sel_out_out_out_out_in1_T = if3_btb__rd_cl_sel_out_out_out_out_out_T_2[1:0]; // @[Hash.scala 117:20]
  wire [1:0] if3_btb_rd_cl_sel_out_out_out_out_in1 = ~if3_btb__rd_cl_sel_out_out_out_out_in1_T; // @[Hash.scala 117:17]
  wire [2:0] _GEN_146 = {{1'd0}, if3_btb_rd_cl_sel_out_out_out_out_in1}; // @[Hash.scala 121:18]
  wire [2:0] if3_btb__rd_cl_sel_out_out_out_out_out_T_3 = _GEN_146 ^ if3_btb__rd_cl_sel_out_out_out_out_out_T_2; // @[Hash.scala 121:18]
  wire [18:0] if3_btb__wr_cl_sel_out_out_T = if3_btb_io_update_bits_pc[18:0]; // @[Hash.scala 32:14]
  wire [19:0] if3_btb__wr_cl_sel_out_out_T_1 = if3_btb_io_update_bits_pc[38:19]; // @[Hash.scala 32:31]
  wire [19:0] _GEN_147 = {{1'd0}, if3_btb__wr_cl_sel_out_out_T}; // @[Hash.scala 32:27]
  wire [19:0] if3_btb__wr_cl_sel_out_out_T_2 = _GEN_147 ^ if3_btb__wr_cl_sel_out_out_T_1; // @[Hash.scala 32:27]
  wire [9:0] if3_btb__wr_cl_sel_out_out_out_T = if3_btb__wr_cl_sel_out_out_T_2[9:0]; // @[Hash.scala 32:14]
  wire [9:0] if3_btb__wr_cl_sel_out_out_out_T_1 = if3_btb__wr_cl_sel_out_out_T_2[19:10]; // @[Hash.scala 32:31]
  wire [9:0] if3_btb__wr_cl_sel_out_out_out_T_2 = if3_btb__wr_cl_sel_out_out_out_T ^ if3_btb__wr_cl_sel_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [4:0] if3_btb__wr_cl_sel_out_out_out_out_T = if3_btb__wr_cl_sel_out_out_out_T_2[4:0]; // @[Hash.scala 32:14]
  wire [4:0] if3_btb__wr_cl_sel_out_out_out_out_T_1 = if3_btb__wr_cl_sel_out_out_out_T_2[9:5]; // @[Hash.scala 32:31]
  wire [4:0] if3_btb__wr_cl_sel_out_out_out_out_T_2 = if3_btb__wr_cl_sel_out_out_out_out_T ^
    if3_btb__wr_cl_sel_out_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [1:0] if3_btb__wr_cl_sel_out_out_out_out_out_T = if3_btb__wr_cl_sel_out_out_out_out_T_2[1:0]; // @[Hash.scala 32:14]
  wire [2:0] if3_btb__wr_cl_sel_out_out_out_out_out_T_1 = if3_btb__wr_cl_sel_out_out_out_out_T_2[4:2]; // @[Hash.scala 32:31]
  wire [2:0] _GEN_148 = {{1'd0}, if3_btb__wr_cl_sel_out_out_out_out_out_T}; // @[Hash.scala 32:27]
  wire [2:0] if3_btb__wr_cl_sel_out_out_out_out_out_T_2 = _GEN_148 ^ if3_btb__wr_cl_sel_out_out_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [1:0] if3_btb__wr_cl_sel_out_out_out_out_in1_T = if3_btb__wr_cl_sel_out_out_out_out_out_T_2[1:0]; // @[Hash.scala 117:20]
  wire [1:0] if3_btb_wr_cl_sel_out_out_out_out_in1 = ~if3_btb__wr_cl_sel_out_out_out_out_in1_T; // @[Hash.scala 117:17]
  wire [2:0] _GEN_149 = {{1'd0}, if3_btb_wr_cl_sel_out_out_out_out_in1}; // @[Hash.scala 121:18]
  wire [2:0] if3_btb__wr_cl_sel_out_out_out_out_out_T_3 = _GEN_149 ^ if3_btb__wr_cl_sel_out_out_out_out_out_T_2; // @[Hash.scala 121:18]
  wire [1:0] if3_btb_wr_cl_sel_out_out_out_out_out_1 = if3_btb__wr_cl_sel_out_out_out_out_out_T_3[1:0]; // @[Hash.scala 115:19 121:11]
  reg  if3_btb_bypassFifo_io_enq_valid_REG; // @[BTB.scala 74:37]
  wire  if3_bim_clock;
  wire  if3_bim_reset;
  wire  if3_bim_io_req_ready;
  wire  if3_bim_io_req_valid;
  wire [38:0] if3_bim_io_req_bits_pc;
  wire  if3_bim_io_resp_ready;
  wire  if3_bim_io_resp_valid;
  wire  if3_bim_io_resp_bits_bim_p;
  wire  if3_bim_io_resp_bits_bim_h;
  wire  if3_bim_io_update_valid;
  wire  if3_bim_io_update_bits_bim_p;
  wire  if3_bim_io_update_bits_bim_h;
  wire [38:0] if3_bim_io_update_bits_pc;
  wire  if3_bim_io_update_bits_isFinalTaken;
  wire  if3_bim_io_isReady;
  reg  if3_bim_bim_P [0:7]; // @[BIM.scala 46:26]
  wire  if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_en; // @[BIM.scala 46:26]
  wire [2:0] if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_addr; // @[BIM.scala 46:26]
  wire  if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_data; // @[BIM.scala 46:26]
  wire  if3_bim_bim_P_MPORT_data; // @[BIM.scala 46:26]
  wire [2:0] if3_bim_bim_P_MPORT_addr; // @[BIM.scala 46:26]
  wire  if3_bim_bim_P_MPORT_mask; // @[BIM.scala 46:26]
  wire  if3_bim_bim_P_MPORT_en; // @[BIM.scala 46:26]
  wire  if3_bim_bim_P_clock;
  reg  if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_en_pipe_0;
  reg [2:0] if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_addr_pipe_0;
  reg  if3_bim_bim_H [0:7]; // @[BIM.scala 52:26]
  wire  if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_en; // @[BIM.scala 52:26]
  wire [2:0] if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_addr; // @[BIM.scala 52:26]
  wire  if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_data; // @[BIM.scala 52:26]
  wire  if3_bim_bim_H_MPORT_1_data; // @[BIM.scala 52:26]
  wire [2:0] if3_bim_bim_H_MPORT_1_addr; // @[BIM.scala 52:26]
  wire  if3_bim_bim_H_MPORT_1_mask; // @[BIM.scala 52:26]
  wire  if3_bim_bim_H_MPORT_1_en; // @[BIM.scala 52:26]
  wire  if3_bim_bim_H_clock;
  reg  if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_en_pipe_0;
  reg [2:0] if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_addr_pipe_0;
  wire  if3_bim_bypassFifo_clock;
  wire  if3_bim_bypassFifo_reset;
  wire  if3_bim_bypassFifo_io_enq_ready;
  wire  if3_bim_bypassFifo_io_enq_valid;
  wire  if3_bim_bypassFifo_io_enq_bits_0;
  wire  if3_bim_bypassFifo_io_enq_bits_1;
  wire  if3_bim_bypassFifo_io_deq_ready;
  wire  if3_bim_bypassFifo_io_deq_valid;
  wire  if3_bim_bypassFifo_io_deq_bits_0;
  wire  if3_bim_bypassFifo_io_deq_bits_1;
  reg  if3_bim_bypassFifo_ram_0 [0:0]; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_0_clock;
  reg  if3_bim_bypassFifo_ram_1 [0:0]; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_1_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_1_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_1_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_1_MPORT_data; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_1_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_1_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_1_MPORT_en; // @[Decoupled.scala 275:95]
  wire  if3_bim_bypassFifo_ram_1_clock;
  reg  if3_bim_bypassFifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  if3_bim_bypassFifo__empty_T = ~if3_bim_bypassFifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  if3_bim_bypassFifo__do_enq_T = if3_bim_bypassFifo_io_enq_ready & if3_bim_bypassFifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  if3_bim_bypassFifo__do_deq_T = if3_bim_bypassFifo_io_deq_ready & if3_bim_bypassFifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  if3_bim_bypassFifo__GEN_10 = if3_bim_bypassFifo_io_deq_ready ? 1'h0 : if3_bim_bypassFifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  if3_bim_bypassFifo__GEN_14 = if3_bim_bypassFifo__empty_T ? if3_bim_bypassFifo__GEN_10 :
    if3_bim_bypassFifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  if3_bim_bypassFifo__GEN_13 = if3_bim_bypassFifo__empty_T ? 1'h0 : if3_bim_bypassFifo__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  if3_bim_bypassFifo__T = if3_bim_bypassFifo__GEN_14 != if3_bim_bypassFifo__GEN_13; // @[Decoupled.scala 295:15]
  wire  if3_bim_bypassFifo__io_deq_valid_T = ~if3_bim_bypassFifo__empty_T; // @[Decoupled.scala 304:19]
  reg  if3_bim_por_reset; // @[BIM.scala 37:26]
  reg [2:0] if3_bim_reset_cl; // @[Counter.scala 61:40]
  wire  if3_bim_wrap_wrap = if3_bim_reset_cl == 3'h7; // @[Counter.scala 73:24]
  wire [2:0] if3_bim__wrap_value_T_1 = if3_bim_reset_cl + 3'h1; // @[Counter.scala 77:24]
  wire  if3_bim__GEN_1 = if3_bim_por_reset & if3_bim_wrap_wrap; // @[Counter.scala 136:24 137:12]
  wire  if3_bim__GEN_4 = if3_bim__GEN_1 ? 1'h0 : if3_bim_por_reset; // @[BIM.scala 39:21 37:26 39:33]
  wire [18:0] if3_bim__wr_cl_out_out_T = if3_bim_io_update_bits_pc[18:0]; // @[Hash.scala 32:14]
  wire [19:0] if3_bim__wr_cl_out_out_T_1 = if3_bim_io_update_bits_pc[38:19]; // @[Hash.scala 32:31]
  wire [19:0] _GEN_150 = {{1'd0}, if3_bim__wr_cl_out_out_T}; // @[Hash.scala 32:27]
  wire [19:0] if3_bim__wr_cl_out_out_T_2 = _GEN_150 ^ if3_bim__wr_cl_out_out_T_1; // @[Hash.scala 32:27]
  wire [9:0] if3_bim__wr_cl_out_out_out_T = if3_bim__wr_cl_out_out_T_2[9:0]; // @[Hash.scala 32:14]
  wire [9:0] if3_bim__wr_cl_out_out_out_T_1 = if3_bim__wr_cl_out_out_T_2[19:10]; // @[Hash.scala 32:31]
  wire [9:0] if3_bim__wr_cl_out_out_out_T_2 = if3_bim__wr_cl_out_out_out_T ^ if3_bim__wr_cl_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [4:0] if3_bim__wr_cl_out_out_out_out_T = if3_bim__wr_cl_out_out_out_T_2[4:0]; // @[Hash.scala 32:14]
  wire [4:0] if3_bim__wr_cl_out_out_out_out_T_1 = if3_bim__wr_cl_out_out_out_T_2[9:5]; // @[Hash.scala 32:31]
  wire [4:0] if3_bim__wr_cl_out_out_out_out_T_2 = if3_bim__wr_cl_out_out_out_out_T ^ if3_bim__wr_cl_out_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [2:0] if3_bim__wr_cl_out_out_out_in1_T = if3_bim__wr_cl_out_out_out_out_T_2[2:0]; // @[Hash.scala 117:20]
  wire [2:0] if3_bim_wr_cl_out_out_out_in1 = ~if3_bim__wr_cl_out_out_out_in1_T; // @[Hash.scala 117:17]
  wire [3:0] if3_bim_wr_cl_out_out_out_in2 = if3_bim__wr_cl_out_out_out_out_T_2[4:1]; // @[Hash.scala 118:19]
  wire [3:0] _GEN_151 = {{1'd0}, if3_bim_wr_cl_out_out_out_in1}; // @[Hash.scala 121:18]
  wire [3:0] if3_bim__wr_cl_out_out_out_out_T_3 = _GEN_151 ^ if3_bim_wr_cl_out_out_out_in2; // @[Hash.scala 121:18]
  wire [18:0] if3_bim__rd_cl_out_out_T = if3_bim_io_req_bits_pc[18:0]; // @[Hash.scala 32:14]
  wire [19:0] if3_bim__rd_cl_out_out_T_1 = if3_bim_io_req_bits_pc[38:19]; // @[Hash.scala 32:31]
  wire [19:0] _GEN_152 = {{1'd0}, if3_bim__rd_cl_out_out_T}; // @[Hash.scala 32:27]
  wire [19:0] if3_bim__rd_cl_out_out_T_2 = _GEN_152 ^ if3_bim__rd_cl_out_out_T_1; // @[Hash.scala 32:27]
  wire [9:0] if3_bim__rd_cl_out_out_out_T = if3_bim__rd_cl_out_out_T_2[9:0]; // @[Hash.scala 32:14]
  wire [9:0] if3_bim__rd_cl_out_out_out_T_1 = if3_bim__rd_cl_out_out_T_2[19:10]; // @[Hash.scala 32:31]
  wire [9:0] if3_bim__rd_cl_out_out_out_T_2 = if3_bim__rd_cl_out_out_out_T ^ if3_bim__rd_cl_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [4:0] if3_bim__rd_cl_out_out_out_out_T = if3_bim__rd_cl_out_out_out_T_2[4:0]; // @[Hash.scala 32:14]
  wire [4:0] if3_bim__rd_cl_out_out_out_out_T_1 = if3_bim__rd_cl_out_out_out_T_2[9:5]; // @[Hash.scala 32:31]
  wire [4:0] if3_bim__rd_cl_out_out_out_out_T_2 = if3_bim__rd_cl_out_out_out_out_T ^ if3_bim__rd_cl_out_out_out_out_T_1; // @[Hash.scala 32:27]
  wire [2:0] if3_bim__rd_cl_out_out_out_in1_T = if3_bim__rd_cl_out_out_out_out_T_2[2:0]; // @[Hash.scala 117:20]
  wire [2:0] if3_bim_rd_cl_out_out_out_in1 = ~if3_bim__rd_cl_out_out_out_in1_T; // @[Hash.scala 117:17]
  wire [3:0] if3_bim_rd_cl_out_out_out_in2 = if3_bim__rd_cl_out_out_out_out_T_2[4:1]; // @[Hash.scala 118:19]
  wire [3:0] _GEN_153 = {{1'd0}, if3_bim_rd_cl_out_out_out_in1}; // @[Hash.scala 121:18]
  wire [3:0] if3_bim__rd_cl_out_out_out_out_T_3 = _GEN_153 ^ if3_bim_rd_cl_out_out_out_in2; // @[Hash.scala 121:18]
  wire  if3_bim__T = if3_bim_io_update_bits_isFinalTaken != if3_bim_io_update_bits_bim_p; // @[frontend.scala 117:35]
  wire  if3_bim__T_1 = if3_bim_io_update_valid & if3_bim__T; // @[BIM.scala 73:37]
  wire  if3_bim__T_2 = ~if3_bim_io_update_bits_bim_h; // @[BIM.scala 73:69]
  wire  if3_bim__T_3 = if3_bim__T_1 & if3_bim__T_2; // @[BIM.scala 73:67]
  wire [2:0] if3_bim_wr_cl_out_out_out_out_1 = if3_bim__wr_cl_out_out_out_out_T_3[2:0]; // @[Hash.scala 115:19 121:11]
  wire  if3_bim__T_6 = ~if3_bim_io_update_bits_bim_p; // @[BIM.scala 76:31]
  wire  if3_bim__T_12 = if3_bim__T ? if3_bim__T_2 : 1'h1; // @[BIM.scala 83:35]
  reg  if3_bim_bypassFifo_io_enq_valid_REG; // @[BIM.scala 89:37]
  wire  if3_tage_io_resp_valid;
  wire  if3_btbFifo_clock;
  wire  if3_btbFifo_reset;
  wire  if3_btbFifo_io_enq_0_ready;
  wire  if3_btbFifo_io_enq_0_valid;
  wire [38:0] if3_btbFifo_io_enq_0_bits_target;
  wire  if3_btbFifo_io_deq_0_ready;
  wire  if3_btbFifo_io_deq_0_valid;
  wire [38:0] if3_btbFifo_io_deq_0_bits_target;
  wire  if3_btbFifo_io_flush;
  wire  if3_btbFifo_fifo_clock;
  wire  if3_btbFifo_fifo_reset;
  wire  if3_btbFifo_fifo_io_enq_0_ready;
  wire  if3_btbFifo_fifo_io_enq_0_valid;
  wire [38:0] if3_btbFifo_fifo_io_enq_0_bits_target;
  wire  if3_btbFifo_fifo_io_deq_0_ready;
  wire  if3_btbFifo_fifo_io_deq_0_valid;
  wire [38:0] if3_btbFifo_fifo_io_deq_0_bits_target;
  wire  if3_btbFifo_fifo_io_flush;
  reg [38:0] if3_btbFifo_fifo_buf_0_target; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_btbFifo_fifo_buf_1_target; // @[MultiPortFifo.scala 57:20]
  reg  if3_btbFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  if3_btbFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  if3_btbFifo_fifo_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  if3_btbFifo_fifo_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] if3_btbFifo_fifo__io_enq_0_ready_T = {{1'd0}, if3_btbFifo_fifo_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  if3_btbFifo_fifo__io_enq_0_ready_T_1 = if3_btbFifo_fifo__io_enq_0_ready_T[0]; // @[MultiPortFifo.scala 64:78]
  wire  if3_btbFifo_fifo__GEN_1 = if3_btbFifo_fifo__io_enq_0_ready_T_1 ? if3_btbFifo_fifo_buf_valid_1 :
    if3_btbFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if3_btbFifo_fifo__io_deq_0_valid_T = {{1'd0}, if3_btbFifo_fifo_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  if3_btbFifo_fifo__io_deq_0_valid_T_1 = if3_btbFifo_fifo__io_deq_0_valid_T[0]; // @[MultiPortFifo.scala 65:78]
  wire  if3_btbFifo_fifo__T = if3_btbFifo_fifo_io_enq_0_ready & if3_btbFifo_fifo_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_btbFifo_fifo__GEN_4 = ~if3_btbFifo_fifo__io_enq_0_ready_T_1 | if3_btbFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_btbFifo_fifo__GEN_5 = if3_btbFifo_fifo__io_enq_0_ready_T_1 | if3_btbFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_btbFifo_fifo__GEN_6 = if3_btbFifo_fifo__T ? if3_btbFifo_fifo__GEN_4 : if3_btbFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_btbFifo_fifo__GEN_7 = if3_btbFifo_fifo__T ? if3_btbFifo_fifo__GEN_5 : if3_btbFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_btbFifo_fifo__T_1 = if3_btbFifo_fifo_io_deq_0_ready & if3_btbFifo_fifo_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_btbFifo_fifo__rd_ptr_T_2 = if3_btbFifo_fifo_rd_ptr + if3_btbFifo_fifo__T_1; // @[MultiPortFifo.scala 106:26]
  wire  if3_btbFifo_fifo__wr_ptr_T_2 = if3_btbFifo_fifo_wr_ptr + if3_btbFifo_fifo__T; // @[MultiPortFifo.scala 107:26]
  wire  if3_btbFifo_fifo__T_3 = ~if3_btbFifo_fifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_btbFifo_fifo__T_4 = if3_btbFifo_fifo_io_enq_0_valid & if3_btbFifo_fifo__T_3; // @[MultiPortFifo.scala 161:44]
  wire  if3_btbFifo_fifo__T_7 = ~if3_btbFifo_fifo__T_4; // @[MultiPortFifo.scala 161:15]
  wire  if3_btbFifo_fifo__T_9 = ~if3_btbFifo_fifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  if3_btbFifo_fifo__T_10 = ~if3_btbFifo_fifo__T_7; // @[MultiPortFifo.scala 161:13]
  wire  if3_btbFifo_fifo__T_12 = ~if3_btbFifo_fifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if3_btbFifo_fifo__T_13 = if3_btbFifo_fifo_io_deq_0_valid & if3_btbFifo_fifo__T_12; // @[MultiPortFifo.scala 164:44]
  wire  if3_btbFifo_fifo__T_16 = ~if3_btbFifo_fifo__T_13; // @[MultiPortFifo.scala 164:15]
  wire  if3_btbFifo_fifo__T_19 = ~if3_btbFifo_fifo__T_16; // @[MultiPortFifo.scala 164:13]
  wire  if3_btbFifo_rePortIn_clock;
  wire  if3_btbFifo_rePortIn_reset;
  wire  if3_btbFifo_rePortIn_io_enq_0_ready;
  wire  if3_btbFifo_rePortIn_io_enq_0_valid;
  wire [38:0] if3_btbFifo_rePortIn_io_enq_0_bits_target;
  wire  if3_btbFifo_rePortIn_io_deq_0_ready;
  wire  if3_btbFifo_rePortIn_io_deq_0_valid;
  wire [38:0] if3_btbFifo_rePortIn_io_deq_0_bits_target;
  wire  if3_btbFifo_rePortIn__T = if3_btbFifo_rePortIn_io_enq_0_ready & if3_btbFifo_rePortIn_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_btbFifo_rePortIn__T_1 = if3_btbFifo_rePortIn_io_deq_0_ready & if3_btbFifo_rePortIn_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_btbFifo_rePortIn__T_2 = if3_btbFifo_rePortIn__T == if3_btbFifo_rePortIn__T_1; // @[RePort.scala 32:45]
  wire  if3_btbFifo_rePortIn__T_4 = ~if3_btbFifo_rePortIn_reset; // @[RePort.scala 32:12]
  wire  if3_btbFifo_rePortIn__T_5 = ~if3_btbFifo_rePortIn__T_2; // @[RePort.scala 32:12]
  wire  if3_btbFifo_rePortIn__is_end_0_T = ~if3_btbFifo_rePortIn_io_enq_0_valid; // @[RePort.scala 62:21]
  wire  if3_btbFifo_rePortIn__T_6 = ~if3_btbFifo_rePortIn__is_end_0_T; // @[RePort.scala 75:11]
  wire  if3_btbFifo_zipPort_io_enq_0_ready;
  wire  if3_btbFifo_zipPort_io_enq_0_valid;
  wire [38:0] if3_btbFifo_zipPort_io_enq_0_bits_target;
  wire  if3_btbFifo_zipPort_io_enq_1_ready;
  wire  if3_btbFifo_zipPort_io_enq_1_valid;
  wire [38:0] if3_btbFifo_zipPort_io_enq_1_bits_target;
  wire  if3_btbFifo_zipPort_io_deq_0_ready;
  wire  if3_btbFifo_zipPort_io_deq_0_valid;
  wire [38:0] if3_btbFifo_zipPort_io_deq_0_bits_target;
  wire  if3_btbFifo_zipPort__T = ~if3_btbFifo_zipPort_io_enq_0_valid; // @[RePort.scala 235:24]
  wire  if3_btbFifo_zipPort__T_2 = if3_btbFifo_zipPort__T & if3_btbFifo_zipPort_io_enq_1_valid; // @[RePort.scala 235:36]
  wire  if3_btbFifo__T = if3_btbFifo_zipPort_io_enq_1_ready & if3_btbFifo_zipPort_io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  if3_btbFifo__T_2 = ~if3_btbFifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_btbFifo__T_3 = if3_btbFifo_io_enq_0_valid & if3_btbFifo__T_2; // @[MultiPortFifo.scala 161:44]
  wire  if3_btbFifo__T_6 = ~if3_btbFifo__T_3; // @[MultiPortFifo.scala 161:15]
  wire  if3_btbFifo__T_8 = ~if3_btbFifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  if3_btbFifo__T_9 = ~if3_btbFifo__T_6; // @[MultiPortFifo.scala 161:13]
  wire  if3_btbFifo__T_11 = ~if3_btbFifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if3_btbFifo__T_12 = if3_btbFifo_io_deq_0_valid & if3_btbFifo__T_11; // @[MultiPortFifo.scala 164:44]
  wire  if3_btbFifo__T_15 = ~if3_btbFifo__T_12; // @[MultiPortFifo.scala 164:15]
  wire  if3_btbFifo__T_18 = ~if3_btbFifo__T_15; // @[MultiPortFifo.scala 164:13]
  wire  if3_bimFifo_clock;
  wire  if3_bimFifo_reset;
  wire  if3_bimFifo_io_enq_0_ready;
  wire  if3_bimFifo_io_enq_0_valid;
  wire  if3_bimFifo_io_enq_0_bits_bim_p;
  wire  if3_bimFifo_io_enq_0_bits_bim_h;
  wire  if3_bimFifo_io_deq_0_ready;
  wire  if3_bimFifo_io_deq_0_valid;
  wire  if3_bimFifo_io_deq_0_bits_bim_p;
  wire  if3_bimFifo_io_deq_0_bits_bim_h;
  wire  if3_bimFifo_io_flush;
  wire  if3_bimFifo_fifo_clock;
  wire  if3_bimFifo_fifo_reset;
  wire  if3_bimFifo_fifo_io_enq_0_ready;
  wire  if3_bimFifo_fifo_io_enq_0_valid;
  wire  if3_bimFifo_fifo_io_enq_0_bits_bim_p;
  wire  if3_bimFifo_fifo_io_enq_0_bits_bim_h;
  wire  if3_bimFifo_fifo_io_deq_0_ready;
  wire  if3_bimFifo_fifo_io_deq_0_valid;
  wire  if3_bimFifo_fifo_io_deq_0_bits_bim_p;
  wire  if3_bimFifo_fifo_io_deq_0_bits_bim_h;
  wire  if3_bimFifo_fifo_io_flush;
  reg  if3_bimFifo_fifo_buf_0_bim_p; // @[MultiPortFifo.scala 57:20]
  reg  if3_bimFifo_fifo_buf_0_bim_h; // @[MultiPortFifo.scala 57:20]
  reg  if3_bimFifo_fifo_buf_1_bim_p; // @[MultiPortFifo.scala 57:20]
  reg  if3_bimFifo_fifo_buf_1_bim_h; // @[MultiPortFifo.scala 57:20]
  reg  if3_bimFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  if3_bimFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  if3_bimFifo_fifo_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  if3_bimFifo_fifo_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] if3_bimFifo_fifo__io_enq_0_ready_T = {{1'd0}, if3_bimFifo_fifo_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  if3_bimFifo_fifo__io_enq_0_ready_T_1 = if3_bimFifo_fifo__io_enq_0_ready_T[0]; // @[MultiPortFifo.scala 64:78]
  wire  if3_bimFifo_fifo__GEN_1 = if3_bimFifo_fifo__io_enq_0_ready_T_1 ? if3_bimFifo_fifo_buf_valid_1 :
    if3_bimFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if3_bimFifo_fifo__io_deq_0_valid_T = {{1'd0}, if3_bimFifo_fifo_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  if3_bimFifo_fifo__io_deq_0_valid_T_1 = if3_bimFifo_fifo__io_deq_0_valid_T[0]; // @[MultiPortFifo.scala 65:78]
  wire  if3_bimFifo_fifo__T = if3_bimFifo_fifo_io_enq_0_ready & if3_bimFifo_fifo_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_bimFifo_fifo__GEN_4 = ~if3_bimFifo_fifo__io_enq_0_ready_T_1 | if3_bimFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_bimFifo_fifo__GEN_5 = if3_bimFifo_fifo__io_enq_0_ready_T_1 | if3_bimFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_bimFifo_fifo__GEN_6 = if3_bimFifo_fifo__T ? if3_bimFifo_fifo__GEN_4 : if3_bimFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_bimFifo_fifo__GEN_7 = if3_bimFifo_fifo__T ? if3_bimFifo_fifo__GEN_5 : if3_bimFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_bimFifo_fifo__T_1 = if3_bimFifo_fifo_io_deq_0_ready & if3_bimFifo_fifo_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_bimFifo_fifo__rd_ptr_T_2 = if3_bimFifo_fifo_rd_ptr + if3_bimFifo_fifo__T_1; // @[MultiPortFifo.scala 106:26]
  wire  if3_bimFifo_fifo__wr_ptr_T_2 = if3_bimFifo_fifo_wr_ptr + if3_bimFifo_fifo__T; // @[MultiPortFifo.scala 107:26]
  wire  if3_bimFifo_fifo__T_3 = ~if3_bimFifo_fifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_bimFifo_fifo__T_4 = if3_bimFifo_fifo_io_enq_0_valid & if3_bimFifo_fifo__T_3; // @[MultiPortFifo.scala 161:44]
  wire  if3_bimFifo_fifo__T_7 = ~if3_bimFifo_fifo__T_4; // @[MultiPortFifo.scala 161:15]
  wire  if3_bimFifo_fifo__T_9 = ~if3_bimFifo_fifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  if3_bimFifo_fifo__T_10 = ~if3_bimFifo_fifo__T_7; // @[MultiPortFifo.scala 161:13]
  wire  if3_bimFifo_fifo__T_12 = ~if3_bimFifo_fifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if3_bimFifo_fifo__T_13 = if3_bimFifo_fifo_io_deq_0_valid & if3_bimFifo_fifo__T_12; // @[MultiPortFifo.scala 164:44]
  wire  if3_bimFifo_fifo__T_16 = ~if3_bimFifo_fifo__T_13; // @[MultiPortFifo.scala 164:15]
  wire  if3_bimFifo_fifo__T_19 = ~if3_bimFifo_fifo__T_16; // @[MultiPortFifo.scala 164:13]
  wire  if3_bimFifo_rePortIn_clock;
  wire  if3_bimFifo_rePortIn_reset;
  wire  if3_bimFifo_rePortIn_io_enq_0_ready;
  wire  if3_bimFifo_rePortIn_io_enq_0_valid;
  wire  if3_bimFifo_rePortIn_io_enq_0_bits_bim_p;
  wire  if3_bimFifo_rePortIn_io_enq_0_bits_bim_h;
  wire  if3_bimFifo_rePortIn_io_deq_0_ready;
  wire  if3_bimFifo_rePortIn_io_deq_0_valid;
  wire  if3_bimFifo_rePortIn_io_deq_0_bits_bim_p;
  wire  if3_bimFifo_rePortIn_io_deq_0_bits_bim_h;
  wire  if3_bimFifo_rePortIn__T = if3_bimFifo_rePortIn_io_enq_0_ready & if3_bimFifo_rePortIn_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_bimFifo_rePortIn__T_1 = if3_bimFifo_rePortIn_io_deq_0_ready & if3_bimFifo_rePortIn_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_bimFifo_rePortIn__T_2 = if3_bimFifo_rePortIn__T == if3_bimFifo_rePortIn__T_1; // @[RePort.scala 32:45]
  wire  if3_bimFifo_rePortIn__T_4 = ~if3_bimFifo_rePortIn_reset; // @[RePort.scala 32:12]
  wire  if3_bimFifo_rePortIn__T_5 = ~if3_bimFifo_rePortIn__T_2; // @[RePort.scala 32:12]
  wire  if3_bimFifo_rePortIn__is_end_0_T = ~if3_bimFifo_rePortIn_io_enq_0_valid; // @[RePort.scala 62:21]
  wire  if3_bimFifo_rePortIn__T_6 = ~if3_bimFifo_rePortIn__is_end_0_T; // @[RePort.scala 75:11]
  wire  if3_bimFifo_zipPort_io_enq_0_ready;
  wire  if3_bimFifo_zipPort_io_enq_0_valid;
  wire  if3_bimFifo_zipPort_io_enq_0_bits_bim_p;
  wire  if3_bimFifo_zipPort_io_enq_0_bits_bim_h;
  wire  if3_bimFifo_zipPort_io_enq_1_ready;
  wire  if3_bimFifo_zipPort_io_enq_1_valid;
  wire  if3_bimFifo_zipPort_io_enq_1_bits_bim_p;
  wire  if3_bimFifo_zipPort_io_enq_1_bits_bim_h;
  wire  if3_bimFifo_zipPort_io_deq_0_ready;
  wire  if3_bimFifo_zipPort_io_deq_0_valid;
  wire  if3_bimFifo_zipPort_io_deq_0_bits_bim_p;
  wire  if3_bimFifo_zipPort_io_deq_0_bits_bim_h;
  wire  if3_bimFifo_zipPort__T = ~if3_bimFifo_zipPort_io_enq_0_valid; // @[RePort.scala 235:24]
  wire  if3_bimFifo_zipPort__T_2 = if3_bimFifo_zipPort__T & if3_bimFifo_zipPort_io_enq_1_valid; // @[RePort.scala 235:36]
  wire  if3_bimFifo__T = if3_bimFifo_zipPort_io_enq_1_ready & if3_bimFifo_zipPort_io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  if3_bimFifo__T_2 = ~if3_bimFifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_bimFifo__T_3 = if3_bimFifo_io_enq_0_valid & if3_bimFifo__T_2; // @[MultiPortFifo.scala 161:44]
  wire  if3_bimFifo__T_6 = ~if3_bimFifo__T_3; // @[MultiPortFifo.scala 161:15]
  wire  if3_bimFifo__T_8 = ~if3_bimFifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  if3_bimFifo__T_9 = ~if3_bimFifo__T_6; // @[MultiPortFifo.scala 161:13]
  wire  if3_bimFifo__T_11 = ~if3_bimFifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if3_bimFifo__T_12 = if3_bimFifo_io_deq_0_valid & if3_bimFifo__T_11; // @[MultiPortFifo.scala 164:44]
  wire  if3_bimFifo__T_15 = ~if3_bimFifo__T_12; // @[MultiPortFifo.scala 164:15]
  wire  if3_bimFifo__T_18 = ~if3_bimFifo__T_15; // @[MultiPortFifo.scala 164:13]
  wire  if3_tageFifo_clock;
  wire  if3_tageFifo_reset;
  wire  if3_tageFifo_io_enq_0_valid;
  wire  if3_tageFifo_io_deq_0_ready;
  wire  if3_tageFifo_io_deq_0_valid;
  wire  if3_tageFifo_io_flush;
  wire  if3_tageFifo_fifo_clock;
  wire  if3_tageFifo_fifo_reset;
  wire  if3_tageFifo_fifo_io_enq_0_ready;
  wire  if3_tageFifo_fifo_io_enq_0_valid;
  wire  if3_tageFifo_fifo_io_deq_0_ready;
  wire  if3_tageFifo_fifo_io_deq_0_valid;
  wire  if3_tageFifo_fifo_io_flush;
  reg  if3_tageFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  if3_tageFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  if3_tageFifo_fifo_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  if3_tageFifo_fifo_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] if3_tageFifo_fifo__io_enq_0_ready_T = {{1'd0}, if3_tageFifo_fifo_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  if3_tageFifo_fifo__io_enq_0_ready_T_1 = if3_tageFifo_fifo__io_enq_0_ready_T[0]; // @[MultiPortFifo.scala 64:78]
  wire  if3_tageFifo_fifo__GEN_1 = if3_tageFifo_fifo__io_enq_0_ready_T_1 ? if3_tageFifo_fifo_buf_valid_1 :
    if3_tageFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if3_tageFifo_fifo__io_deq_0_valid_T = {{1'd0}, if3_tageFifo_fifo_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  if3_tageFifo_fifo__io_deq_0_valid_T_1 = if3_tageFifo_fifo__io_deq_0_valid_T[0]; // @[MultiPortFifo.scala 65:78]
  wire  if3_tageFifo_fifo__T = if3_tageFifo_fifo_io_enq_0_ready & if3_tageFifo_fifo_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_tageFifo_fifo__GEN_4 = ~if3_tageFifo_fifo__io_enq_0_ready_T_1 | if3_tageFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_tageFifo_fifo__GEN_5 = if3_tageFifo_fifo__io_enq_0_ready_T_1 | if3_tageFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_tageFifo_fifo__GEN_6 = if3_tageFifo_fifo__T ? if3_tageFifo_fifo__GEN_4 : if3_tageFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_tageFifo_fifo__GEN_7 = if3_tageFifo_fifo__T ? if3_tageFifo_fifo__GEN_5 : if3_tageFifo_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_tageFifo_fifo__T_1 = if3_tageFifo_fifo_io_deq_0_ready & if3_tageFifo_fifo_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_tageFifo_fifo__rd_ptr_T_2 = if3_tageFifo_fifo_rd_ptr + if3_tageFifo_fifo__T_1; // @[MultiPortFifo.scala 106:26]
  wire  if3_tageFifo_fifo__wr_ptr_T_2 = if3_tageFifo_fifo_wr_ptr + if3_tageFifo_fifo__T; // @[MultiPortFifo.scala 107:26]
  wire  if3_tageFifo_fifo__T_3 = ~if3_tageFifo_fifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_tageFifo_fifo__T_4 = if3_tageFifo_fifo_io_enq_0_valid & if3_tageFifo_fifo__T_3; // @[MultiPortFifo.scala 161:44]
  wire  if3_tageFifo_fifo__T_7 = ~if3_tageFifo_fifo__T_4; // @[MultiPortFifo.scala 161:15]
  wire  if3_tageFifo_fifo__T_9 = ~if3_tageFifo_fifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  if3_tageFifo_fifo__T_10 = ~if3_tageFifo_fifo__T_7; // @[MultiPortFifo.scala 161:13]
  wire  if3_tageFifo_fifo__T_12 = ~if3_tageFifo_fifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if3_tageFifo_fifo__T_13 = if3_tageFifo_fifo_io_deq_0_valid & if3_tageFifo_fifo__T_12; // @[MultiPortFifo.scala 164:44]
  wire  if3_tageFifo_fifo__T_16 = ~if3_tageFifo_fifo__T_13; // @[MultiPortFifo.scala 164:15]
  wire  if3_tageFifo_fifo__T_19 = ~if3_tageFifo_fifo__T_16; // @[MultiPortFifo.scala 164:13]
  wire  if3_tageFifo_rePortIn_clock;
  wire  if3_tageFifo_rePortIn_reset;
  wire  if3_tageFifo_rePortIn_io_enq_0_ready;
  wire  if3_tageFifo_rePortIn_io_enq_0_valid;
  wire  if3_tageFifo_rePortIn_io_deq_0_ready;
  wire  if3_tageFifo_rePortIn_io_deq_0_valid;
  wire  if3_tageFifo_rePortIn__T = if3_tageFifo_rePortIn_io_enq_0_ready & if3_tageFifo_rePortIn_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_tageFifo_rePortIn__T_1 = if3_tageFifo_rePortIn_io_deq_0_ready & if3_tageFifo_rePortIn_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_tageFifo_rePortIn__T_2 = if3_tageFifo_rePortIn__T == if3_tageFifo_rePortIn__T_1; // @[RePort.scala 32:45]
  wire  if3_tageFifo_rePortIn__T_4 = ~if3_tageFifo_rePortIn_reset; // @[RePort.scala 32:12]
  wire  if3_tageFifo_rePortIn__T_5 = ~if3_tageFifo_rePortIn__T_2; // @[RePort.scala 32:12]
  wire  if3_tageFifo_zipPort_io_enq_0_ready;
  wire  if3_tageFifo_zipPort_io_enq_0_valid;
  wire  if3_tageFifo_zipPort_io_enq_1_ready;
  wire  if3_tageFifo_zipPort_io_enq_1_valid;
  wire  if3_tageFifo_zipPort_io_deq_0_ready;
  wire  if3_tageFifo_zipPort_io_deq_0_valid;
  wire  if3_tageFifo_zipPort__T = ~if3_tageFifo_zipPort_io_enq_0_valid; // @[RePort.scala 235:24]
  wire  if3_tageFifo_zipPort__T_2 = if3_tageFifo_zipPort__T & if3_tageFifo_zipPort_io_enq_1_valid; // @[RePort.scala 235:36]
  wire  if3_tageFifo__T = if3_tageFifo_zipPort_io_enq_1_ready & if3_tageFifo_zipPort_io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  if3_tageFifo__T_2 = ~if3_tageFifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_tageFifo__T_3 = if3_tageFifo_io_enq_0_valid & if3_tageFifo__T_2; // @[MultiPortFifo.scala 161:44]
  wire  if3_tageFifo__T_6 = ~if3_tageFifo__T_3; // @[MultiPortFifo.scala 161:15]
  wire  if3_tageFifo__T_8 = ~if3_tageFifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  if3_tageFifo__T_9 = ~if3_tageFifo__T_6; // @[MultiPortFifo.scala 161:13]
  wire  if3_tageFifo__T_11 = ~if3_tageFifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if3_tageFifo__T_12 = if3_tageFifo_io_deq_0_valid & if3_tageFifo__T_11; // @[MultiPortFifo.scala 164:44]
  wire  if3_tageFifo__T_15 = ~if3_tageFifo__T_12; // @[MultiPortFifo.scala 164:15]
  wire  if3_tageFifo__T_18 = ~if3_tageFifo__T_15; // @[MultiPortFifo.scala 164:13]
  wire  if3_if3_resp_fifo_clock;
  wire  if3_if3_resp_fifo_reset;
  wire  if3_if3_resp_fifo_io_enq_0_ready;
  wire  if3_if3_resp_fifo_io_enq_0_valid;
  wire  if3_if3_resp_fifo_io_enq_0_bits_isRVC;
  wire [31:0] if3_if3_resp_fifo_io_enq_0_bits_instr;
  wire [38:0] if3_if3_resp_fifo_io_enq_0_bits_pc;
  wire  if3_if3_resp_fifo_io_enq_0_bits_isRedirect;
  wire [38:0] if3_if3_resp_fifo_io_enq_0_bits_target;
  wire  if3_if3_resp_fifo_io_enq_1_ready;
  wire  if3_if3_resp_fifo_io_enq_1_valid;
  wire  if3_if3_resp_fifo_io_enq_1_bits_isRVC;
  wire [31:0] if3_if3_resp_fifo_io_enq_1_bits_instr;
  wire [38:0] if3_if3_resp_fifo_io_enq_1_bits_pc;
  wire  if3_if3_resp_fifo_io_enq_1_bits_isRedirect;
  wire [38:0] if3_if3_resp_fifo_io_enq_1_bits_target;
  wire  if3_if3_resp_fifo_io_enq_2_ready;
  wire  if3_if3_resp_fifo_io_enq_2_valid;
  wire  if3_if3_resp_fifo_io_enq_2_bits_isRVC;
  wire [31:0] if3_if3_resp_fifo_io_enq_2_bits_instr;
  wire [38:0] if3_if3_resp_fifo_io_enq_2_bits_pc;
  wire  if3_if3_resp_fifo_io_enq_2_bits_isRedirect;
  wire [38:0] if3_if3_resp_fifo_io_enq_2_bits_target;
  wire  if3_if3_resp_fifo_io_enq_3_ready;
  wire  if3_if3_resp_fifo_io_enq_3_valid;
  wire  if3_if3_resp_fifo_io_enq_3_bits_isRVC;
  wire [31:0] if3_if3_resp_fifo_io_enq_3_bits_instr;
  wire [38:0] if3_if3_resp_fifo_io_enq_3_bits_pc;
  wire  if3_if3_resp_fifo_io_enq_3_bits_isRedirect;
  wire [38:0] if3_if3_resp_fifo_io_enq_3_bits_target;
  wire  if3_if3_resp_fifo_io_deq_0_ready;
  wire  if3_if3_resp_fifo_io_deq_0_valid;
  wire  if3_if3_resp_fifo_io_deq_0_bits_isRVC;
  wire [31:0] if3_if3_resp_fifo_io_deq_0_bits_instr;
  wire [38:0] if3_if3_resp_fifo_io_deq_0_bits_pc;
  wire  if3_if3_resp_fifo_io_deq_0_bits_isRedirect;
  wire [38:0] if3_if3_resp_fifo_io_deq_0_bits_target;
  wire  if3_if3_resp_fifo_io_flush;
  reg  if3_if3_resp_fifo_buf_0_isRVC; // @[MultiPortFifo.scala 57:20]
  reg [31:0] if3_if3_resp_fifo_buf_0_instr; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_if3_resp_fifo_buf_0_pc; // @[MultiPortFifo.scala 57:20]
  reg  if3_if3_resp_fifo_buf_0_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_if3_resp_fifo_buf_0_target; // @[MultiPortFifo.scala 57:20]
  reg  if3_if3_resp_fifo_buf_1_isRVC; // @[MultiPortFifo.scala 57:20]
  reg [31:0] if3_if3_resp_fifo_buf_1_instr; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_if3_resp_fifo_buf_1_pc; // @[MultiPortFifo.scala 57:20]
  reg  if3_if3_resp_fifo_buf_1_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_if3_resp_fifo_buf_1_target; // @[MultiPortFifo.scala 57:20]
  reg  if3_if3_resp_fifo_buf_2_isRVC; // @[MultiPortFifo.scala 57:20]
  reg [31:0] if3_if3_resp_fifo_buf_2_instr; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_if3_resp_fifo_buf_2_pc; // @[MultiPortFifo.scala 57:20]
  reg  if3_if3_resp_fifo_buf_2_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_if3_resp_fifo_buf_2_target; // @[MultiPortFifo.scala 57:20]
  reg  if3_if3_resp_fifo_buf_3_isRVC; // @[MultiPortFifo.scala 57:20]
  reg [31:0] if3_if3_resp_fifo_buf_3_instr; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_if3_resp_fifo_buf_3_pc; // @[MultiPortFifo.scala 57:20]
  reg  if3_if3_resp_fifo_buf_3_isRedirect; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if3_if3_resp_fifo_buf_3_target; // @[MultiPortFifo.scala 57:20]
  reg  if3_if3_resp_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  if3_if3_resp_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  if3_if3_resp_fifo_buf_valid_2; // @[MultiPortFifo.scala 58:30]
  reg  if3_if3_resp_fifo_buf_valid_3; // @[MultiPortFifo.scala 58:30]
  reg [1:0] if3_if3_resp_fifo_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg [1:0] if3_if3_resp_fifo_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [2:0] if3_if3_resp_fifo__io_enq_0_ready_T = {{1'd0}, if3_if3_resp_fifo_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire [1:0] if3_if3_resp_fifo__io_enq_0_ready_T_1 = if3_if3_resp_fifo__io_enq_0_ready_T[1:0]; // @[MultiPortFifo.scala 64:78]
  wire  if3_if3_resp_fifo__GEN_1 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_valid_1 :
    if3_if3_resp_fifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if3_if3_resp_fifo__GEN_2 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_valid_2 :
    if3_if3_resp_fifo__GEN_1; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if3_if3_resp_fifo__GEN_3 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_valid_3 :
    if3_if3_resp_fifo__GEN_2; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if3_if3_resp_fifo__io_enq_1_ready_T_1 = if3_if3_resp_fifo_wr_ptr + 2'h1; // @[MultiPortFifo.scala 64:78]
  wire  if3_if3_resp_fifo__GEN_5 = 2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_valid_1 :
    if3_if3_resp_fifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if3_if3_resp_fifo__GEN_6 = 2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_valid_2 :
    if3_if3_resp_fifo__GEN_5; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if3_if3_resp_fifo__GEN_7 = 2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_valid_3 :
    if3_if3_resp_fifo__GEN_6; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if3_if3_resp_fifo__io_enq_2_ready_T_1 = if3_if3_resp_fifo_wr_ptr + 2'h2; // @[MultiPortFifo.scala 64:78]
  wire  if3_if3_resp_fifo__GEN_9 = 2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_valid_1 :
    if3_if3_resp_fifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if3_if3_resp_fifo__GEN_10 = 2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_valid_2 :
    if3_if3_resp_fifo__GEN_9; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if3_if3_resp_fifo__GEN_11 = 2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_valid_3 :
    if3_if3_resp_fifo__GEN_10; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if3_if3_resp_fifo__io_enq_3_ready_T_1 = if3_if3_resp_fifo_wr_ptr + 2'h3; // @[MultiPortFifo.scala 64:78]
  wire  if3_if3_resp_fifo__GEN_13 = 2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_valid_1 :
    if3_if3_resp_fifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if3_if3_resp_fifo__GEN_14 = 2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_valid_2 :
    if3_if3_resp_fifo__GEN_13; // @[MultiPortFifo.scala 64:{94,94}]
  wire  if3_if3_resp_fifo__GEN_15 = 2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_valid_3 :
    if3_if3_resp_fifo__GEN_14; // @[MultiPortFifo.scala 64:{94,94}]
  wire [2:0] if3_if3_resp_fifo__io_deq_0_valid_T = {{1'd0}, if3_if3_resp_fifo_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire [1:0] if3_if3_resp_fifo__io_deq_0_valid_T_1 = if3_if3_resp_fifo__io_deq_0_valid_T[1:0]; // @[MultiPortFifo.scala 65:78]
  wire  if3_if3_resp_fifo__GEN_17 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_valid_1 :
    if3_if3_resp_fifo_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if3_if3_resp_fifo__GEN_18 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_valid_2 :
    if3_if3_resp_fifo__GEN_17; // @[MultiPortFifo.scala 65:{94,94}]
  wire  if3_if3_resp_fifo__T = if3_if3_resp_fifo_io_enq_0_ready & if3_if3_resp_fifo_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_if3_resp_fifo__GEN_20 = 2'h0 == if3_if3_resp_fifo__io_enq_0_ready_T_1 | if3_if3_resp_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_21 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 | if3_if3_resp_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_22 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 | if3_if3_resp_fifo_buf_valid_2; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_23 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 | if3_if3_resp_fifo_buf_valid_3; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_24 = if3_if3_resp_fifo__T ? if3_if3_resp_fifo__GEN_20 : if3_if3_resp_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_if3_resp_fifo__GEN_25 = if3_if3_resp_fifo__T ? if3_if3_resp_fifo__GEN_21 : if3_if3_resp_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_if3_resp_fifo__GEN_26 = if3_if3_resp_fifo__T ? if3_if3_resp_fifo__GEN_22 : if3_if3_resp_fifo_buf_valid_2; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_if3_resp_fifo__GEN_27 = if3_if3_resp_fifo__T ? if3_if3_resp_fifo__GEN_23 : if3_if3_resp_fifo_buf_valid_3; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if3_if3_resp_fifo__T_1 = if3_if3_resp_fifo_io_deq_0_ready & if3_if3_resp_fifo_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if3_if3_resp_fifo__GEN_28 = 2'h0 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_24; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_29 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_25; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_30 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_26; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_31 = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_27; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_32 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_28 : if3_if3_resp_fifo__GEN_24; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_33 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_29 : if3_if3_resp_fifo__GEN_25; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_34 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_30 : if3_if3_resp_fifo__GEN_26; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_35 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_31 : if3_if3_resp_fifo__GEN_27; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_51 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_1_isRVC :
    if3_if3_resp_fifo_buf_0_isRVC; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_61 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_1_instr
     : if3_if3_resp_fifo_buf_0_instr; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_62 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_1_pc :
    if3_if3_resp_fifo_buf_0_pc; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_64 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_1_isRedirect
     : if3_if3_resp_fifo_buf_0_isRedirect; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_65 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_1_target
     : if3_if3_resp_fifo_buf_0_target; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_66 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_2_isRVC :
    if3_if3_resp_fifo__GEN_51; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_76 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_2_instr
     : if3_if3_resp_fifo__GEN_61; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_77 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_2_pc :
    if3_if3_resp_fifo__GEN_62; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_79 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_2_isRedirect
     : if3_if3_resp_fifo__GEN_64; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_80 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_2_target
     : if3_if3_resp_fifo__GEN_65; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_81 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_3_isRVC :
    if3_if3_resp_fifo__GEN_66; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_91 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_3_instr
     : if3_if3_resp_fifo__GEN_76; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_92 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_3_pc :
    if3_if3_resp_fifo__GEN_77; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_94 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_3_isRedirect
     : if3_if3_resp_fifo__GEN_79; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_95 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo_buf_3_target
     : if3_if3_resp_fifo__GEN_80; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__buf_T_1_isRVC = if3_if3_resp_fifo__T ? if3_if3_resp_fifo_io_enq_0_bits_isRVC :
    if3_if3_resp_fifo__GEN_81; // @[MultiPortFifo.scala 101:33]
  wire [31:0] if3_if3_resp_fifo__buf_T_1_instr = if3_if3_resp_fifo__T ? if3_if3_resp_fifo_io_enq_0_bits_instr :
    if3_if3_resp_fifo__GEN_91; // @[MultiPortFifo.scala 101:33]
  wire [38:0] if3_if3_resp_fifo__buf_T_1_pc = if3_if3_resp_fifo__T ? if3_if3_resp_fifo_io_enq_0_bits_pc :
    if3_if3_resp_fifo__GEN_92; // @[MultiPortFifo.scala 101:33]
  wire  if3_if3_resp_fifo__buf_T_1_isRedirect = if3_if3_resp_fifo__T ? if3_if3_resp_fifo_io_enq_0_bits_isRedirect :
    if3_if3_resp_fifo__GEN_94; // @[MultiPortFifo.scala 101:33]
  wire [38:0] if3_if3_resp_fifo__buf_T_1_target = if3_if3_resp_fifo__T ? if3_if3_resp_fifo_io_enq_0_bits_target :
    if3_if3_resp_fifo__GEN_95; // @[MultiPortFifo.scala 101:33]
  wire  if3_if3_resp_fifo__GEN_96 = 2'h0 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo__buf_T_1_isRVC :
    if3_if3_resp_fifo_buf_0_isRVC; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if3_if3_resp_fifo__GEN_97 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo__buf_T_1_isRVC :
    if3_if3_resp_fifo_buf_1_isRVC; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if3_if3_resp_fifo__GEN_98 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo__buf_T_1_isRVC :
    if3_if3_resp_fifo_buf_2_isRVC; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if3_if3_resp_fifo__GEN_99 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo__buf_T_1_isRVC :
    if3_if3_resp_fifo_buf_3_isRVC; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [31:0] if3_if3_resp_fifo__GEN_136 = 2'h0 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_instr : if3_if3_resp_fifo_buf_0_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [31:0] if3_if3_resp_fifo__GEN_137 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_instr : if3_if3_resp_fifo_buf_1_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [31:0] if3_if3_resp_fifo__GEN_138 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_instr : if3_if3_resp_fifo_buf_2_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [31:0] if3_if3_resp_fifo__GEN_139 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_instr : if3_if3_resp_fifo_buf_3_instr; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if3_if3_resp_fifo__GEN_140 = 2'h0 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo__buf_T_1_pc
     : if3_if3_resp_fifo_buf_0_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if3_if3_resp_fifo__GEN_141 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo__buf_T_1_pc
     : if3_if3_resp_fifo_buf_1_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if3_if3_resp_fifo__GEN_142 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo__buf_T_1_pc
     : if3_if3_resp_fifo_buf_2_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if3_if3_resp_fifo__GEN_143 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ? if3_if3_resp_fifo__buf_T_1_pc
     : if3_if3_resp_fifo_buf_3_pc; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if3_if3_resp_fifo__GEN_148 = 2'h0 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_isRedirect : if3_if3_resp_fifo_buf_0_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if3_if3_resp_fifo__GEN_149 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_isRedirect : if3_if3_resp_fifo_buf_1_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if3_if3_resp_fifo__GEN_150 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_isRedirect : if3_if3_resp_fifo_buf_2_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if3_if3_resp_fifo__GEN_151 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_isRedirect : if3_if3_resp_fifo_buf_3_isRedirect; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if3_if3_resp_fifo__GEN_152 = 2'h0 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_target : if3_if3_resp_fifo_buf_0_target; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if3_if3_resp_fifo__GEN_153 = 2'h1 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_target : if3_if3_resp_fifo_buf_1_target; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if3_if3_resp_fifo__GEN_154 = 2'h2 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_target : if3_if3_resp_fifo_buf_2_target; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire [38:0] if3_if3_resp_fifo__GEN_155 = 2'h3 == if3_if3_resp_fifo__io_enq_0_ready_T_1 ?
    if3_if3_resp_fifo__buf_T_1_target : if3_if3_resp_fifo_buf_3_target; // @[MultiPortFifo.scala 101:{27,27} 57:20]
  wire  if3_if3_resp_fifo__T_2 = if3_if3_resp_fifo_io_enq_1_ready & if3_if3_resp_fifo_io_enq_1_valid; // @[Decoupled.scala 52:35]
  wire  if3_if3_resp_fifo__GEN_156 = 2'h0 == if3_if3_resp_fifo__io_enq_1_ready_T_1 | if3_if3_resp_fifo__GEN_32; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_157 = 2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1 | if3_if3_resp_fifo__GEN_33; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_158 = 2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1 | if3_if3_resp_fifo__GEN_34; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_159 = 2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1 | if3_if3_resp_fifo__GEN_35; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_160 = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo__GEN_156 : if3_if3_resp_fifo__GEN_32; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_161 = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo__GEN_157 : if3_if3_resp_fifo__GEN_33; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_162 = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo__GEN_158 : if3_if3_resp_fifo__GEN_34; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_163 = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo__GEN_159 : if3_if3_resp_fifo__GEN_35; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_164 = 2'h0 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_160; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_165 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_161; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_166 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_162; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_167 = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_163; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_168 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_164 : if3_if3_resp_fifo__GEN_160; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_169 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_165 : if3_if3_resp_fifo__GEN_161; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_170 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_166 : if3_if3_resp_fifo__GEN_162; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_171 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_167 : if3_if3_resp_fifo__GEN_163; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_187 = 2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_1_isRVC :
    if3_if3_resp_fifo_buf_0_isRVC; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_197 = 2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_1_instr
     : if3_if3_resp_fifo_buf_0_instr; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_198 = 2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_1_pc :
    if3_if3_resp_fifo_buf_0_pc; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_200 = 2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_1_isRedirect
     : if3_if3_resp_fifo_buf_0_isRedirect; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_201 = 2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ?
    if3_if3_resp_fifo_buf_1_target : if3_if3_resp_fifo_buf_0_target; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_202 = 2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_2_isRVC :
    if3_if3_resp_fifo__GEN_187; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_212 = 2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_2_instr
     : if3_if3_resp_fifo__GEN_197; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_213 = 2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_2_pc :
    if3_if3_resp_fifo__GEN_198; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_215 = 2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_2_isRedirect
     : if3_if3_resp_fifo__GEN_200; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_216 = 2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ?
    if3_if3_resp_fifo_buf_2_target : if3_if3_resp_fifo__GEN_201; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_217 = 2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_3_isRVC :
    if3_if3_resp_fifo__GEN_202; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_227 = 2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_3_instr
     : if3_if3_resp_fifo__GEN_212; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_228 = 2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_3_pc :
    if3_if3_resp_fifo__GEN_213; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_230 = 2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ? if3_if3_resp_fifo_buf_3_isRedirect
     : if3_if3_resp_fifo__GEN_215; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_231 = 2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1 ?
    if3_if3_resp_fifo_buf_3_target : if3_if3_resp_fifo__GEN_216; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__buf_T_3_isRVC = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo_io_enq_1_bits_isRVC :
    if3_if3_resp_fifo__GEN_217; // @[MultiPortFifo.scala 101:33]
  wire [31:0] if3_if3_resp_fifo__buf_T_3_instr = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo_io_enq_1_bits_instr :
    if3_if3_resp_fifo__GEN_227; // @[MultiPortFifo.scala 101:33]
  wire [38:0] if3_if3_resp_fifo__buf_T_3_pc = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo_io_enq_1_bits_pc :
    if3_if3_resp_fifo__GEN_228; // @[MultiPortFifo.scala 101:33]
  wire  if3_if3_resp_fifo__buf_T_3_isRedirect = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo_io_enq_1_bits_isRedirect :
    if3_if3_resp_fifo__GEN_230; // @[MultiPortFifo.scala 101:33]
  wire [38:0] if3_if3_resp_fifo__buf_T_3_target = if3_if3_resp_fifo__T_2 ? if3_if3_resp_fifo_io_enq_1_bits_target :
    if3_if3_resp_fifo__GEN_231; // @[MultiPortFifo.scala 101:33]
  wire  if3_if3_resp_fifo__T_4 = if3_if3_resp_fifo_io_enq_2_ready & if3_if3_resp_fifo_io_enq_2_valid; // @[Decoupled.scala 52:35]
  wire  if3_if3_resp_fifo__GEN_292 = 2'h0 == if3_if3_resp_fifo__io_enq_2_ready_T_1 | if3_if3_resp_fifo__GEN_168; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_293 = 2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1 | if3_if3_resp_fifo__GEN_169; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_294 = 2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1 | if3_if3_resp_fifo__GEN_170; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_295 = 2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1 | if3_if3_resp_fifo__GEN_171; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_296 = if3_if3_resp_fifo__T_4 ? if3_if3_resp_fifo__GEN_292 : if3_if3_resp_fifo__GEN_168; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_297 = if3_if3_resp_fifo__T_4 ? if3_if3_resp_fifo__GEN_293 : if3_if3_resp_fifo__GEN_169; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_298 = if3_if3_resp_fifo__T_4 ? if3_if3_resp_fifo__GEN_294 : if3_if3_resp_fifo__GEN_170; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_299 = if3_if3_resp_fifo__T_4 ? if3_if3_resp_fifo__GEN_295 : if3_if3_resp_fifo__GEN_171; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_300 = 2'h0 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_296; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_301 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_297; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_302 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_298; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_303 = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? 1'h0 : if3_if3_resp_fifo__GEN_299; // @[MultiPortFifo.scala 98:{57,57}]
  wire  if3_if3_resp_fifo__GEN_304 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_300 : if3_if3_resp_fifo__GEN_296; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_305 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_301 : if3_if3_resp_fifo__GEN_297; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_306 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_302 : if3_if3_resp_fifo__GEN_298; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_307 = if3_if3_resp_fifo__T_1 ? if3_if3_resp_fifo__GEN_303 : if3_if3_resp_fifo__GEN_299; // @[MultiPortFifo.scala 98:34]
  wire  if3_if3_resp_fifo__GEN_323 = 2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_1_isRVC :
    if3_if3_resp_fifo_buf_0_isRVC; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_333 = 2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_1_instr
     : if3_if3_resp_fifo_buf_0_instr; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_334 = 2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_1_pc :
    if3_if3_resp_fifo_buf_0_pc; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_336 = 2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_1_isRedirect
     : if3_if3_resp_fifo_buf_0_isRedirect; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_337 = 2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ?
    if3_if3_resp_fifo_buf_1_target : if3_if3_resp_fifo_buf_0_target; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_338 = 2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_2_isRVC :
    if3_if3_resp_fifo__GEN_323; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_348 = 2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_2_instr
     : if3_if3_resp_fifo__GEN_333; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_349 = 2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_2_pc :
    if3_if3_resp_fifo__GEN_334; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_351 = 2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_2_isRedirect
     : if3_if3_resp_fifo__GEN_336; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_352 = 2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ?
    if3_if3_resp_fifo_buf_2_target : if3_if3_resp_fifo__GEN_337; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_353 = 2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_3_isRVC :
    if3_if3_resp_fifo__GEN_338; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_363 = 2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_3_instr
     : if3_if3_resp_fifo__GEN_348; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_364 = 2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_3_pc :
    if3_if3_resp_fifo__GEN_349; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_366 = 2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ? if3_if3_resp_fifo_buf_3_isRedirect
     : if3_if3_resp_fifo__GEN_351; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_367 = 2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1 ?
    if3_if3_resp_fifo_buf_3_target : if3_if3_resp_fifo__GEN_352; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__T_6 = if3_if3_resp_fifo_io_enq_3_ready & if3_if3_resp_fifo_io_enq_3_valid; // @[Decoupled.scala 52:35]
  wire  if3_if3_resp_fifo__GEN_428 = 2'h0 == if3_if3_resp_fifo__io_enq_3_ready_T_1 | if3_if3_resp_fifo__GEN_304; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_429 = 2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1 | if3_if3_resp_fifo__GEN_305; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_430 = 2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1 | if3_if3_resp_fifo__GEN_306; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_431 = 2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1 | if3_if3_resp_fifo__GEN_307; // @[MultiPortFifo.scala 97:{57,57}]
  wire  if3_if3_resp_fifo__GEN_432 = if3_if3_resp_fifo__T_6 ? if3_if3_resp_fifo__GEN_428 : if3_if3_resp_fifo__GEN_304; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_433 = if3_if3_resp_fifo__T_6 ? if3_if3_resp_fifo__GEN_429 : if3_if3_resp_fifo__GEN_305; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_434 = if3_if3_resp_fifo__T_6 ? if3_if3_resp_fifo__GEN_430 : if3_if3_resp_fifo__GEN_306; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_435 = if3_if3_resp_fifo__T_6 ? if3_if3_resp_fifo__GEN_431 : if3_if3_resp_fifo__GEN_307; // @[MultiPortFifo.scala 97:34]
  wire  if3_if3_resp_fifo__GEN_459 = 2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_1_isRVC :
    if3_if3_resp_fifo_buf_0_isRVC; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_469 = 2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_1_instr
     : if3_if3_resp_fifo_buf_0_instr; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_470 = 2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_1_pc :
    if3_if3_resp_fifo_buf_0_pc; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_472 = 2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_1_isRedirect
     : if3_if3_resp_fifo_buf_0_isRedirect; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_473 = 2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ?
    if3_if3_resp_fifo_buf_1_target : if3_if3_resp_fifo_buf_0_target; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_474 = 2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_2_isRVC :
    if3_if3_resp_fifo__GEN_459; // @[MultiPortFifo.scala 101:{33,33}]
  wire [31:0] if3_if3_resp_fifo__GEN_484 = 2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_2_instr
     : if3_if3_resp_fifo__GEN_469; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_485 = 2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_2_pc :
    if3_if3_resp_fifo__GEN_470; // @[MultiPortFifo.scala 101:{33,33}]
  wire  if3_if3_resp_fifo__GEN_487 = 2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ? if3_if3_resp_fifo_buf_2_isRedirect
     : if3_if3_resp_fifo__GEN_472; // @[MultiPortFifo.scala 101:{33,33}]
  wire [38:0] if3_if3_resp_fifo__GEN_488 = 2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1 ?
    if3_if3_resp_fifo_buf_2_target : if3_if3_resp_fifo__GEN_473; // @[MultiPortFifo.scala 101:{33,33}]
  wire [1:0] _GEN_173 = {{1'd0}, if3_if3_resp_fifo__T_1}; // @[MultiPortFifo.scala 106:26]
  wire [1:0] if3_if3_resp_fifo__rd_ptr_T_2 = if3_if3_resp_fifo_rd_ptr + _GEN_173; // @[MultiPortFifo.scala 106:26]
  wire [1:0] if3_if3_resp_fifo__wr_ptr_T_1 = if3_if3_resp_fifo__T_2 ? 2'h2 : {{1'd0}, if3_if3_resp_fifo__T}; // @[Mux.scala 101:16]
  wire [1:0] if3_if3_resp_fifo__wr_ptr_T_2 = if3_if3_resp_fifo__T_4 ? 2'h3 : if3_if3_resp_fifo__wr_ptr_T_1; // @[Mux.scala 101:16]
  wire [2:0] if3_if3_resp_fifo__wr_ptr_T_3 = if3_if3_resp_fifo__T_6 ? 3'h4 : {{1'd0}, if3_if3_resp_fifo__wr_ptr_T_2}; // @[Mux.scala 101:16]
  wire [2:0] if3_if3_resp_fifo__wr_ptr_T_5 = if3_if3_resp_fifo__io_enq_0_ready_T + if3_if3_resp_fifo__wr_ptr_T_3; // @[MultiPortFifo.scala 107:26]
  wire [2:0] if3_if3_resp_fifo__GEN_569 = if3_if3_resp_fifo_io_flush ? 3'h0 : if3_if3_resp_fifo__wr_ptr_T_5; // @[MultiPortFifo.scala 107:16 87:23 90:16]
  wire  if3_if3_resp_fifo__GEN_645 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_1_isRVC :
    if3_if3_resp_fifo_buf_0_isRVC; // @[MultiPortFifo.scala 114:{14,14}]
  wire [31:0] if3_if3_resp_fifo__GEN_655 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_1_instr
     : if3_if3_resp_fifo_buf_0_instr; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if3_if3_resp_fifo__GEN_656 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_1_pc :
    if3_if3_resp_fifo_buf_0_pc; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if3_if3_resp_fifo__GEN_658 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_1_isRedirect
     : if3_if3_resp_fifo_buf_0_isRedirect; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if3_if3_resp_fifo__GEN_659 = 2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ?
    if3_if3_resp_fifo_buf_1_target : if3_if3_resp_fifo_buf_0_target; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if3_if3_resp_fifo__GEN_660 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_2_isRVC :
    if3_if3_resp_fifo__GEN_645; // @[MultiPortFifo.scala 114:{14,14}]
  wire [31:0] if3_if3_resp_fifo__GEN_670 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_2_instr
     : if3_if3_resp_fifo__GEN_655; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if3_if3_resp_fifo__GEN_671 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_2_pc :
    if3_if3_resp_fifo__GEN_656; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if3_if3_resp_fifo__GEN_673 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_2_isRedirect
     : if3_if3_resp_fifo__GEN_658; // @[MultiPortFifo.scala 114:{14,14}]
  wire [38:0] if3_if3_resp_fifo__GEN_674 = 2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ?
    if3_if3_resp_fifo_buf_2_target : if3_if3_resp_fifo__GEN_659; // @[MultiPortFifo.scala 114:{14,14}]
  wire  if3_if3_resp_fifo__T_9 = ~if3_if3_resp_fifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_if3_resp_fifo__T_10 = if3_if3_resp_fifo_io_enq_0_valid & if3_if3_resp_fifo__T_9; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_13 = ~if3_if3_resp_fifo__T_10; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_15 = ~if3_if3_resp_fifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_16 = ~if3_if3_resp_fifo__T_13; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_18 = ~if3_if3_resp_fifo_io_enq_1_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_if3_resp_fifo__T_27 = ~if3_if3_resp_fifo_io_enq_2_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_if3_resp_fifo__T_36 = ~if3_if3_resp_fifo_io_enq_3_valid; // @[MultiPortFifo.scala 161:63]
  wire  if3_if3_resp_fifo__T_46 = if3_if3_resp_fifo_io_enq_1_valid & if3_if3_resp_fifo__T_9; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_49 = ~if3_if3_resp_fifo__T_46; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_52 = ~if3_if3_resp_fifo__T_49; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_55 = if3_if3_resp_fifo_io_enq_1_valid & if3_if3_resp_fifo__T_18; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_58 = ~if3_if3_resp_fifo__T_55; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_61 = ~if3_if3_resp_fifo__T_58; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_82 = if3_if3_resp_fifo_io_enq_2_valid & if3_if3_resp_fifo__T_9; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_85 = ~if3_if3_resp_fifo__T_82; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_88 = ~if3_if3_resp_fifo__T_85; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_91 = if3_if3_resp_fifo_io_enq_2_valid & if3_if3_resp_fifo__T_18; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_94 = ~if3_if3_resp_fifo__T_91; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_97 = ~if3_if3_resp_fifo__T_94; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_100 = if3_if3_resp_fifo_io_enq_2_valid & if3_if3_resp_fifo__T_27; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_103 = ~if3_if3_resp_fifo__T_100; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_106 = ~if3_if3_resp_fifo__T_103; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_118 = if3_if3_resp_fifo_io_enq_3_valid & if3_if3_resp_fifo__T_9; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_121 = ~if3_if3_resp_fifo__T_118; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_124 = ~if3_if3_resp_fifo__T_121; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_127 = if3_if3_resp_fifo_io_enq_3_valid & if3_if3_resp_fifo__T_18; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_130 = ~if3_if3_resp_fifo__T_127; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_133 = ~if3_if3_resp_fifo__T_130; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_136 = if3_if3_resp_fifo_io_enq_3_valid & if3_if3_resp_fifo__T_27; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_139 = ~if3_if3_resp_fifo__T_136; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_142 = ~if3_if3_resp_fifo__T_139; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_145 = if3_if3_resp_fifo_io_enq_3_valid & if3_if3_resp_fifo__T_36; // @[MultiPortFifo.scala 161:44]
  wire  if3_if3_resp_fifo__T_148 = ~if3_if3_resp_fifo__T_145; // @[MultiPortFifo.scala 161:15]
  wire  if3_if3_resp_fifo__T_151 = ~if3_if3_resp_fifo__T_148; // @[MultiPortFifo.scala 161:13]
  wire  if3_if3_resp_fifo__T_153 = ~if3_if3_resp_fifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if3_if3_resp_fifo__T_154 = if3_if3_resp_fifo_io_deq_0_valid & if3_if3_resp_fifo__T_153; // @[MultiPortFifo.scala 164:44]
  wire  if3_if3_resp_fifo__T_157 = ~if3_if3_resp_fifo__T_154; // @[MultiPortFifo.scala 164:15]
  wire  if3_if3_resp_fifo__T_160 = ~if3_if3_resp_fifo__T_157; // @[MultiPortFifo.scala 164:13]
  wire  if3_if3_resp_fifo__T_166 = ~if3_if3_resp_fifo__T; // @[MultiPortFifo.scala 169:17]
  wire  if3_if3_resp_fifo__T_175 = ~if3_if3_resp_fifo__T_2; // @[MultiPortFifo.scala 169:17]
  wire  if3_if3_resp_fifo__T_188 = ~if3_if3_resp_fifo__T_4; // @[MultiPortFifo.scala 169:17]
  wire [2:0] _GEN_175 = if3_if3_resp_fifo_reset ? 3'h0 : if3_if3_resp_fifo__GEN_569; // @[MultiPortFifo.scala 61:{27,27}]
  reg  if3_pipeLineLock; // @[IF3.scala 54:29]
  wire  if3__predictor_ready_T = if3_btb_io_isReady & if3_bim_io_isReady; // @[IF3.scala 65:40]
  wire [1:0] if3__is_instr32_T = if3_io_if3_req_0_bits_instr[1:0]; // @[IF3.scala 81:48]
  wire  if3_is_instr32_0 = if3__is_instr32_T == 2'h3; // @[IF3.scala 81:54]
  wire [1:0] if3__is_instr32_T_1 = if3_io_if3_req_1_bits_instr[1:0]; // @[IF3.scala 81:48]
  wire  if3_is_instr32_1 = if3__is_instr32_T_1 == 2'h3; // @[IF3.scala 81:54]
  wire [1:0] if3__is_instr32_T_2 = if3_io_if3_req_2_bits_instr[1:0]; // @[IF3.scala 81:48]
  wire  if3_is_instr32_2 = if3__is_instr32_T_2 == 2'h3; // @[IF3.scala 81:54]
  wire [1:0] if3__is_instr32_T_3 = if3_io_if3_req_3_bits_instr[1:0]; // @[IF3.scala 81:48]
  wire  if3_is_instr32_3 = if3__is_instr32_T_3 == 2'h3; // @[IF3.scala 81:54]
  wire  if3__T_2 = if3_is_instr32_0 | if3_io_if3_req_0_bits_isRedirect; // @[IF3.scala 86:51]
  wire  if3__T_3 = ~if3__T_2; // @[IF3.scala 86:30]
  wire  if3__T_4 = if3_is_instr32_1 & if3__T_3; // @[IF3.scala 86:28]
  wire  if3__T_5 = if3__T_4 | if3_io_if3_req_1_bits_isRedirect; // @[IF3.scala 86:51]
  wire  if3__T_6 = ~if3__T_5; // @[IF3.scala 86:30]
  wire  if3__T_7 = if3_is_instr32_2 & if3__T_6; // @[IF3.scala 86:28]
  wire  if3__T_8 = if3__T_7 | if3_io_if3_req_2_bits_isRedirect; // @[IF3.scala 86:51]
  wire  if3__GEN_3 = if3_is_instr32_3 | if3__T_8; // @[IF3.scala 89:27 90:24]
  wire [31:0] if3__reAlign_0_bits_instr_T = {if3_io_if3_req_1_bits_instr,if3_io_if3_req_0_bits_instr}; // @[Cat.scala 33:92]
  wire [31:0] if3__reAlign_0_bits_instr_T_1 = if3_io_if3_req_1_bits_isFault ? {{16'd0}, if3_io_if3_req_1_bits_instr} :
    if3__reAlign_0_bits_instr_T; // @[IF3.scala 106:44]
  wire [15:0] if3__reAlignPreDecode_0_info16_is_jalr_T = if3_io_if3_req_1_bits_instr & 16'he07f; // @[IF3.scala 345:34]
  wire  if3__reAlignPreDecode_0_info16_is_jalr_T_1 = 16'h8002 == if3__reAlignPreDecode_0_info16_is_jalr_T; // @[IF3.scala 345:34]
  wire [4:0] if3__reAlignPreDecode_0_info16_is_jalr_T_2 = if3_io_if3_req_1_bits_instr[11:7]; // @[IF3.scala 345:75]
  wire  if3__reAlignPreDecode_0_info16_is_jalr_T_3 = if3__reAlignPreDecode_0_info16_is_jalr_T_2 != 5'h0; // @[IF3.scala 345:82]
  wire  if3__reAlignPreDecode_0_info16_is_jalr_T_4 = if3__reAlignPreDecode_0_info16_is_jalr_T_1 &
    if3__reAlignPreDecode_0_info16_is_jalr_T_3; // @[IF3.scala 345:66]
  wire [15:0] if3__reAlignPreDecode_0_info16_is_branch_T = if3_io_if3_req_1_bits_instr & 16'hc003; // @[IF3.scala 346:34]
  wire  if3__reAlignPreDecode_0_info16_is_branch_T_1 = 16'hc001 == if3__reAlignPreDecode_0_info16_is_branch_T; // @[IF3.scala 346:34]
  wire [6:0] if3__reAlignPreDecode_0_info32_is_jalr_T = if3__reAlign_0_bits_instr_T[6:0]; // @[IF3.scala 371:33]
  wire  if3__reAlignPreDecode_0_info32_is_jalr_T_1 = if3__reAlignPreDecode_0_info32_is_jalr_T == 7'h67; // @[IF3.scala 371:39]
  wire  if3__reAlignPreDecode_0_info32_is_branch_T_1 = if3__reAlignPreDecode_0_info32_is_jalr_T == 7'h63; // @[IF3.scala 372:39]
  wire [31:0] if3__reAlignPreDecode_0_info32_is_fencei_T = if3__reAlign_0_bits_instr_T & 32'h707f; // @[IF3.scala 375:35]
  wire  if3__reAlignPreDecode_0_info32_is_fencei_T_1 = 32'h100f == if3__reAlignPreDecode_0_info32_is_fencei_T; // @[IF3.scala 375:35]
  wire [31:0] if3__reAlignPreDecode_0_info32_is_sfencevma_T = if3__reAlign_0_bits_instr_T & 32'hfe007fff; // @[IF3.scala 376:38]
  wire  if3__reAlignPreDecode_0_info32_is_sfencevma_T_1 = 32'h12000073 == if3__reAlignPreDecode_0_info32_is_sfencevma_T; // @[IF3.scala 376:38]
  wire  if3__reAlignPreDecode_0_T_1_is_jalr = if3_io_if3_req_1_bits_isFault ? if3__reAlignPreDecode_0_info16_is_jalr_T_4
     : if3__reAlignPreDecode_0_info32_is_jalr_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_0_T_1_is_branch = if3_io_if3_req_1_bits_isFault ?
    if3__reAlignPreDecode_0_info16_is_branch_T_1 : if3__reAlignPreDecode_0_info32_is_branch_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_0_T_1_is_fencei = if3_io_if3_req_1_bits_isFault ? 1'h0 :
    if3__reAlignPreDecode_0_info32_is_fencei_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_0_T_1_is_sfencevma = if3_io_if3_req_1_bits_isFault ? 1'h0 :
    if3__reAlignPreDecode_0_info32_is_sfencevma_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlign_0_valid_T = if3_io_if3_req_0_ready & if3_io_if3_req_0_valid; // @[Decoupled.scala 52:35]
  wire  if3__reAlign_0_valid_T_1 = if3_io_if3_req_1_ready & if3_io_if3_req_1_valid; // @[Decoupled.scala 52:35]
  wire  if3__reAlign_0_valid_T_2 = if3__reAlign_0_valid_T & if3__reAlign_0_valid_T_1; // @[IF3.scala 112:57]
  wire  if3__reAlign_0_valid_T_3 = if3__reAlign_0_valid_T_2 & if3__predictor_ready_T; // @[IF3.scala 112:80]
  wire  if3__reAlign_0_valid_T_4 = ~if3_pipeLineLock; // @[IF3.scala 112:100]
  wire  if3__reAlign_0_valid_T_5 = if3__reAlign_0_valid_T_3 & if3__reAlign_0_valid_T_4; // @[IF3.scala 112:98]
  wire [15:0] if3__reAlignPreDecode_0_info16_is_branch_T_2 = if3_io_if3_req_0_bits_instr & 16'hc003; // @[IF3.scala 346:34]
  wire  if3__reAlignPreDecode_0_info16_is_branch_T_3 = 16'hc001 == if3__reAlignPreDecode_0_info16_is_branch_T_2; // @[IF3.scala 346:34]
  wire  if3__GEN_24 = if3_is_instr32_0 ? if3__reAlignPreDecode_0_T_1_is_branch :
    if3__reAlignPreDecode_0_info16_is_branch_T_3; // @[IF3.scala 102:31 107:31 138:31]
  wire [15:0] if3__reAlignPreDecode_0_info16_is_jalr_T_5 = if3_io_if3_req_0_bits_instr & 16'he07f; // @[IF3.scala 345:34]
  wire  if3__reAlignPreDecode_0_info16_is_jalr_T_6 = 16'h8002 == if3__reAlignPreDecode_0_info16_is_jalr_T_5; // @[IF3.scala 345:34]
  wire [4:0] if3__reAlignPreDecode_0_info16_is_jalr_T_7 = if3_io_if3_req_0_bits_instr[11:7]; // @[IF3.scala 345:75]
  wire  if3__reAlignPreDecode_0_info16_is_jalr_T_8 = if3__reAlignPreDecode_0_info16_is_jalr_T_7 != 5'h0; // @[IF3.scala 345:82]
  wire  if3__reAlignPreDecode_0_info16_is_jalr_T_9 = if3__reAlignPreDecode_0_info16_is_jalr_T_6 &
    if3__reAlignPreDecode_0_info16_is_jalr_T_8; // @[IF3.scala 345:66]
  wire  if3__GEN_23 = if3_is_instr32_0 ? if3__reAlignPreDecode_0_T_1_is_jalr :
    if3__reAlignPreDecode_0_info16_is_jalr_T_9; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__reAlign_0_ready_T = if3_combPDT_io_enq_0_ready & if3_btb_io_req_ready; // @[IF3.scala 202:53]
  wire  if3__GEN_332 = if3__GEN_23 ? if3__reAlign_0_ready_T : if3_combPDT_io_enq_0_ready; // @[IF3.scala 179:11 196:27]
  wire  if3__reAlign_0_ready_T_1 = if3_combPDT_io_enq_0_ready & if3_bim_io_req_ready; // @[IF3.scala 213:53]
  wire  if3__GEN_338 = if3__GEN_24 ? if3__reAlign_0_ready_T_1 : if3__GEN_332; // @[IF3.scala 207:27]
  wire  if3__io_if3_req_0_ready_T = if3__GEN_338 & if3__predictor_ready_T; // @[IF3.scala 113:55]
  wire  if3__io_if3_req_0_ready_T_2 = if3__io_if3_req_0_ready_T & if3__reAlign_0_valid_T_4; // @[IF3.scala 113:73]
  wire  if3__io_if3_req_0_ready_T_3 = if3__io_if3_req_0_ready_T_2 & if3_io_if3_req_1_valid; // @[IF3.scala 113:89]
  wire  if3__T_13 = if3__reAlign_0_valid_T == if3__reAlign_0_valid_T_1; // @[IF3.scala 132:37]
  wire  if3__T_15 = ~if3_reset; // @[IF3.scala 132:17]
  wire  if3__T_16 = ~if3__T_13; // @[IF3.scala 132:17]
  wire  if3__reAlign_0_valid_T_19 = if3__reAlign_0_valid_T & if3__predictor_ready_T; // @[IF3.scala 143:57]
  wire  if3__reAlign_0_valid_T_21 = if3__reAlign_0_valid_T_19 & if3__reAlign_0_valid_T_4; // @[IF3.scala 143:75]
  wire  if3__GEN_28 = if3_is_instr32_0 & if3__reAlignPreDecode_0_T_1_is_fencei; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_29 = if3_is_instr32_0 & if3__reAlignPreDecode_0_T_1_is_sfencevma; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_32 = if3_is_instr32_0 ? if3__reAlign_0_valid_T_5 : if3__reAlign_0_valid_T_21; // @[IF3.scala 102:31]
  wire  if3__GEN_34 = if3_is_instr32_0 & if3__io_if3_req_0_ready_T_2; // @[IF3.scala 102:31]
  wire  if3__T_19 = if3__reAlign_0_valid_T & if3_io_if3_req_0_bits_isRedirect; // @[IF3.scala 160:33]
  wire  if3__T_23 = ~if3__reAlign_0_valid_T_1; // @[IF3.scala 160:75]
  wire  if3__T_24 = if3_io_if3_req_0_valid & if3_io_if3_req_0_bits_isRedirect; // @[IF3.scala 161:33]
  wire  if3__T_25 = if3_io_if3_req_1_valid & if3_io_if3_req_1_bits_isRedirect; // @[IF3.scala 161:101]
  wire  if3__T_26 = ~if3__T_25; // @[IF3.scala 161:77]
  wire  if3__T_29 = ~if3__T_26; // @[IF3.scala 161:75]
  wire [31:0] if3__reAlign_1_bits_instr_T = {if3_io_if3_req_2_bits_instr,if3_io_if3_req_1_bits_instr}; // @[Cat.scala 33:92]
  wire [31:0] if3__reAlign_1_bits_instr_T_1 = if3_io_if3_req_2_bits_isFault ? {{16'd0}, if3_io_if3_req_2_bits_instr} :
    if3__reAlign_1_bits_instr_T; // @[IF3.scala 106:44]
  wire [15:0] if3__reAlignPreDecode_1_info16_is_jalr_T = if3_io_if3_req_2_bits_instr & 16'he07f; // @[IF3.scala 345:34]
  wire  if3__reAlignPreDecode_1_info16_is_jalr_T_1 = 16'h8002 == if3__reAlignPreDecode_1_info16_is_jalr_T; // @[IF3.scala 345:34]
  wire [4:0] if3__reAlignPreDecode_1_info16_is_jalr_T_2 = if3_io_if3_req_2_bits_instr[11:7]; // @[IF3.scala 345:75]
  wire  if3__reAlignPreDecode_1_info16_is_jalr_T_3 = if3__reAlignPreDecode_1_info16_is_jalr_T_2 != 5'h0; // @[IF3.scala 345:82]
  wire  if3__reAlignPreDecode_1_info16_is_jalr_T_4 = if3__reAlignPreDecode_1_info16_is_jalr_T_1 &
    if3__reAlignPreDecode_1_info16_is_jalr_T_3; // @[IF3.scala 345:66]
  wire [15:0] if3__reAlignPreDecode_1_info16_is_branch_T = if3_io_if3_req_2_bits_instr & 16'hc003; // @[IF3.scala 346:34]
  wire  if3__reAlignPreDecode_1_info16_is_branch_T_1 = 16'hc001 == if3__reAlignPreDecode_1_info16_is_branch_T; // @[IF3.scala 346:34]
  wire [6:0] if3__reAlignPreDecode_1_info32_is_jalr_T = if3__reAlign_1_bits_instr_T[6:0]; // @[IF3.scala 371:33]
  wire  if3__reAlignPreDecode_1_info32_is_jalr_T_1 = if3__reAlignPreDecode_1_info32_is_jalr_T == 7'h67; // @[IF3.scala 371:39]
  wire  if3__reAlignPreDecode_1_info32_is_branch_T_1 = if3__reAlignPreDecode_1_info32_is_jalr_T == 7'h63; // @[IF3.scala 372:39]
  wire [31:0] if3__reAlignPreDecode_1_info32_is_fencei_T = if3__reAlign_1_bits_instr_T & 32'h707f; // @[IF3.scala 375:35]
  wire  if3__reAlignPreDecode_1_info32_is_fencei_T_1 = 32'h100f == if3__reAlignPreDecode_1_info32_is_fencei_T; // @[IF3.scala 375:35]
  wire [31:0] if3__reAlignPreDecode_1_info32_is_sfencevma_T = if3__reAlign_1_bits_instr_T & 32'hfe007fff; // @[IF3.scala 376:38]
  wire  if3__reAlignPreDecode_1_info32_is_sfencevma_T_1 = 32'h12000073 == if3__reAlignPreDecode_1_info32_is_sfencevma_T; // @[IF3.scala 376:38]
  wire  if3__reAlignPreDecode_1_T_1_is_jalr = if3_io_if3_req_2_bits_isFault ? if3__reAlignPreDecode_1_info16_is_jalr_T_4
     : if3__reAlignPreDecode_1_info32_is_jalr_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_1_T_1_is_branch = if3_io_if3_req_2_bits_isFault ?
    if3__reAlignPreDecode_1_info16_is_branch_T_1 : if3__reAlignPreDecode_1_info32_is_branch_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_1_T_1_is_fencei = if3_io_if3_req_2_bits_isFault ? 1'h0 :
    if3__reAlignPreDecode_1_info32_is_fencei_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_1_T_1_is_sfencevma = if3_io_if3_req_2_bits_isFault ? 1'h0 :
    if3__reAlignPreDecode_1_info32_is_sfencevma_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlign_1_valid_T_1 = if3_io_if3_req_2_ready & if3_io_if3_req_2_valid; // @[Decoupled.scala 52:35]
  wire  if3__reAlign_1_valid_T_2 = if3__reAlign_0_valid_T_1 & if3__reAlign_1_valid_T_1; // @[IF3.scala 112:57]
  wire  if3__reAlign_1_valid_T_3 = if3__reAlign_1_valid_T_2 & if3__predictor_ready_T; // @[IF3.scala 112:80]
  wire  if3__reAlign_1_valid_T_5 = if3__reAlign_1_valid_T_3 & if3__reAlign_0_valid_T_4; // @[IF3.scala 112:98]
  wire  if3_is_lock_pipe_0 = if3__GEN_28 | if3__GEN_29; // @[frontend.scala 100:32]
  wire  if3__T_102 = ~if3__GEN_338; // @[IF3.scala 271:30]
  wire  if3__GEN_74 = if3_is_instr32_1 ? if3__reAlignPreDecode_1_T_1_is_branch :
    if3__reAlignPreDecode_0_info16_is_branch_T_1; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_92 = if3__T_3 & if3__GEN_74; // @[IF3.scala 101:33 97:25]
  wire  if3__GEN_73 = if3_is_instr32_1 ? if3__reAlignPreDecode_1_T_1_is_jalr :
    if3__reAlignPreDecode_0_info16_is_jalr_T_4; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_91 = if3__T_3 & if3__GEN_73; // @[IF3.scala 101:33 97:25]
  wire  if3__reAlign_1_ready_T = if3_combPDT_io_enq_1_ready & if3_btb_io_req_ready; // @[IF3.scala 202:53]
  wire  if3__GEN_268 = if3__GEN_23 ? if3_combPDT_io_enq_1_ready : if3__reAlign_1_ready_T; // @[IF3.scala 197:100 179:11 202:26]
  wire  if3__GEN_271 = if3__GEN_91 ? if3__GEN_268 : if3_combPDT_io_enq_1_ready; // @[IF3.scala 179:11 196:27]
  wire  if3__reAlign_1_ready_T_1 = if3_combPDT_io_enq_1_ready & if3_bim_io_req_ready; // @[IF3.scala 213:53]
  wire  if3__GEN_274 = if3__GEN_24 ? if3__GEN_271 : if3__reAlign_1_ready_T_1; // @[IF3.scala 208:103 213:26]
  wire  if3__GEN_277 = if3__GEN_92 ? if3__GEN_274 : if3__GEN_271; // @[IF3.scala 207:27]
  wire  if3__GEN_291 = if3__GEN_23 ? 1'h0 : if3__GEN_277; // @[IF3.scala 242:100 245:28]
  wire  if3__GEN_297 = if3__GEN_91 ? if3__GEN_291 : if3__GEN_277; // @[IF3.scala 241:27]
  wire  if3__GEN_303 = if3__GEN_24 ? 1'h0 : if3__GEN_297; // @[IF3.scala 252:103 255:28]
  wire  if3__GEN_309 = if3__GEN_92 ? if3__GEN_303 : if3__GEN_297; // @[IF3.scala 251:27]
  wire  if3__GEN_326 = if3__T_102 ? 1'h0 : if3__GEN_309; // @[IF3.scala 271:44 272:26]
  wire  if3__GEN_348 = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_326; // @[IF3.scala 234:29 237:26]
  wire  if3__io_if3_req_1_ready_T_9 = if3__GEN_348 & if3__predictor_ready_T; // @[IF3.scala 113:55]
  wire  if3__io_if3_req_1_ready_T_11 = if3__io_if3_req_1_ready_T_9 & if3__reAlign_0_valid_T_4; // @[IF3.scala 113:73]
  wire  if3__io_if3_req_1_ready_T_12 = if3__io_if3_req_1_ready_T_11 & if3_io_if3_req_2_valid; // @[IF3.scala 113:89]
  wire  if3__T_34 = if3__reAlign_0_valid_T_1 == if3__reAlign_1_valid_T_1; // @[IF3.scala 132:37]
  wire  if3__T_37 = ~if3__T_34; // @[IF3.scala 132:17]
  wire  if3__reAlign_1_valid_T_19 = if3__reAlign_0_valid_T_1 & if3__predictor_ready_T; // @[IF3.scala 143:57]
  wire  if3__reAlign_1_valid_T_21 = if3__reAlign_1_valid_T_19 & if3__reAlign_0_valid_T_4; // @[IF3.scala 143:75]
  wire [31:0] if3__GEN_71 = if3_is_instr32_1 ? if3__reAlign_1_bits_instr_T_1 : {{16'd0}, if3_io_if3_req_1_bits_instr}; // @[IF3.scala 102:31 106:38 137:33]
  wire  if3__GEN_77 = if3_is_instr32_1 ? if3_io_if3_req_2_bits_isFault : 1'h1; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_78 = if3_is_instr32_1 & if3__reAlignPreDecode_1_T_1_is_fencei; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_79 = if3_is_instr32_1 & if3__reAlignPreDecode_1_T_1_is_sfencevma; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_95 = if3__T_3 & if3__GEN_77; // @[IF3.scala 101:33 97:25]
  wire  if3__GEN_82 = if3_is_instr32_1 ? if3__reAlign_1_valid_T_5 : if3__reAlign_1_valid_T_21; // @[IF3.scala 102:31]
  wire  if3__GEN_83 = if3_is_instr32_1 ? if3__io_if3_req_1_ready_T_12 : if3__io_if3_req_1_ready_T_11; // @[IF3.scala 102:31]
  wire  if3__GEN_84 = if3_is_instr32_1 & if3__io_if3_req_1_ready_T_11; // @[IF3.scala 102:31]
  wire [38:0] if3__GEN_86 = if3__T_3 ? if3_io_if3_req_1_bits_pc : 39'h0; // @[IF3.scala 101:33 96:22]
  wire  if3__GEN_96 = if3__T_3 & if3__GEN_78; // @[IF3.scala 101:33 97:25]
  wire  if3__GEN_97 = if3__T_3 & if3__GEN_79; // @[IF3.scala 101:33 97:25]
  wire  if3__GEN_100 = if3__T_3 & if3__GEN_82; // @[IF3.scala 101:33 95:22]
  wire  if3__GEN_102 = if3__T_3 & if3__GEN_84; // @[IF3.scala 101:33]
  wire  if3__T_40 = if3__reAlign_0_valid_T_1 & if3_io_if3_req_1_bits_isRedirect; // @[IF3.scala 160:33]
  wire  if3__T_44 = ~if3__reAlign_1_valid_T_1; // @[IF3.scala 160:75]
  wire  if3__T_46 = if3_io_if3_req_2_valid & if3_io_if3_req_2_bits_isRedirect; // @[IF3.scala 161:101]
  wire  if3__T_47 = ~if3__T_46; // @[IF3.scala 161:77]
  wire  if3__T_50 = ~if3__T_47; // @[IF3.scala 161:75]
  wire [31:0] if3__reAlign_2_bits_instr_T = {if3_io_if3_req_3_bits_instr,if3_io_if3_req_2_bits_instr}; // @[Cat.scala 33:92]
  wire [31:0] if3__reAlign_2_bits_instr_T_1 = if3_io_if3_req_3_bits_isFault ? {{16'd0}, if3_io_if3_req_3_bits_instr} :
    if3__reAlign_2_bits_instr_T; // @[IF3.scala 106:44]
  wire [15:0] if3__reAlignPreDecode_2_info16_is_jalr_T = if3_io_if3_req_3_bits_instr & 16'he07f; // @[IF3.scala 345:34]
  wire  if3__reAlignPreDecode_2_info16_is_jalr_T_1 = 16'h8002 == if3__reAlignPreDecode_2_info16_is_jalr_T; // @[IF3.scala 345:34]
  wire [4:0] if3__reAlignPreDecode_2_info16_is_jalr_T_2 = if3_io_if3_req_3_bits_instr[11:7]; // @[IF3.scala 345:75]
  wire  if3__reAlignPreDecode_2_info16_is_jalr_T_3 = if3__reAlignPreDecode_2_info16_is_jalr_T_2 != 5'h0; // @[IF3.scala 345:82]
  wire  if3__reAlignPreDecode_2_info16_is_jalr_T_4 = if3__reAlignPreDecode_2_info16_is_jalr_T_1 &
    if3__reAlignPreDecode_2_info16_is_jalr_T_3; // @[IF3.scala 345:66]
  wire [15:0] if3__reAlignPreDecode_2_info16_is_branch_T = if3_io_if3_req_3_bits_instr & 16'hc003; // @[IF3.scala 346:34]
  wire  if3__reAlignPreDecode_2_info16_is_branch_T_1 = 16'hc001 == if3__reAlignPreDecode_2_info16_is_branch_T; // @[IF3.scala 346:34]
  wire [6:0] if3__reAlignPreDecode_2_info32_is_jalr_T = if3__reAlign_2_bits_instr_T[6:0]; // @[IF3.scala 371:33]
  wire  if3__reAlignPreDecode_2_info32_is_jalr_T_1 = if3__reAlignPreDecode_2_info32_is_jalr_T == 7'h67; // @[IF3.scala 371:39]
  wire  if3__reAlignPreDecode_2_info32_is_branch_T_1 = if3__reAlignPreDecode_2_info32_is_jalr_T == 7'h63; // @[IF3.scala 372:39]
  wire [31:0] if3__reAlignPreDecode_2_info32_is_fencei_T = if3__reAlign_2_bits_instr_T & 32'h707f; // @[IF3.scala 375:35]
  wire  if3__reAlignPreDecode_2_info32_is_fencei_T_1 = 32'h100f == if3__reAlignPreDecode_2_info32_is_fencei_T; // @[IF3.scala 375:35]
  wire [31:0] if3__reAlignPreDecode_2_info32_is_sfencevma_T = if3__reAlign_2_bits_instr_T & 32'hfe007fff; // @[IF3.scala 376:38]
  wire  if3__reAlignPreDecode_2_info32_is_sfencevma_T_1 = 32'h12000073 == if3__reAlignPreDecode_2_info32_is_sfencevma_T; // @[IF3.scala 376:38]
  wire  if3__reAlignPreDecode_2_T_1_is_jalr = if3_io_if3_req_3_bits_isFault ? if3__reAlignPreDecode_2_info16_is_jalr_T_4
     : if3__reAlignPreDecode_2_info32_is_jalr_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_2_T_1_is_branch = if3_io_if3_req_3_bits_isFault ?
    if3__reAlignPreDecode_2_info16_is_branch_T_1 : if3__reAlignPreDecode_2_info32_is_branch_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_2_T_1_is_fencei = if3_io_if3_req_3_bits_isFault ? 1'h0 :
    if3__reAlignPreDecode_2_info32_is_fencei_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlignPreDecode_2_T_1_is_sfencevma = if3_io_if3_req_3_bits_isFault ? 1'h0 :
    if3__reAlignPreDecode_2_info32_is_sfencevma_T_1; // @[IF3.scala 107:37]
  wire  if3__reAlign_2_valid_T_1 = if3_io_if3_req_3_ready & if3_io_if3_req_3_valid; // @[Decoupled.scala 52:35]
  wire  if3__reAlign_2_valid_T_2 = if3__reAlign_1_valid_T_1 & if3__reAlign_2_valid_T_1; // @[IF3.scala 112:57]
  wire  if3__reAlign_2_valid_T_3 = if3__reAlign_2_valid_T_2 & if3__predictor_ready_T; // @[IF3.scala 112:80]
  wire  if3__reAlign_2_valid_T_5 = if3__reAlign_2_valid_T_3 & if3__reAlign_0_valid_T_4; // @[IF3.scala 112:98]
  wire  if3_is_lock_pipe_1 = if3__GEN_96 | if3__GEN_97; // @[frontend.scala 100:32]
  wire  if3__T_101 = ~if3__GEN_348; // @[IF3.scala 271:30]
  wire  if3__GEN_121 = if3_is_instr32_2 ? if3__reAlignPreDecode_2_T_1_is_branch :
    if3__reAlignPreDecode_1_info16_is_branch_T_1; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_138 = if3__T_6 & if3__GEN_121; // @[IF3.scala 101:33 97:25]
  wire  if3__T_98 = if3__GEN_24 | if3__GEN_92; // @[IF3.scala 252:94]
  wire  if3__GEN_120 = if3_is_instr32_2 ? if3__reAlignPreDecode_2_T_1_is_jalr :
    if3__reAlignPreDecode_1_info16_is_jalr_T_4; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_137 = if3__T_6 & if3__GEN_120; // @[IF3.scala 101:33 97:25]
  wire  if3__T_97 = if3__GEN_23 | if3__GEN_91; // @[IF3.scala 242:92]
  wire  if3__reAlign_2_ready_T = if3_combPDT_io_enq_2_ready & if3_btb_io_req_ready; // @[IF3.scala 202:53]
  wire  if3__GEN_220 = if3__T_97 ? if3_combPDT_io_enq_2_ready : if3__reAlign_2_ready_T; // @[IF3.scala 197:100 179:11 202:26]
  wire  if3__GEN_223 = if3__GEN_137 ? if3__GEN_220 : if3_combPDT_io_enq_2_ready; // @[IF3.scala 179:11 196:27]
  wire  if3__reAlign_2_ready_T_1 = if3_combPDT_io_enq_2_ready & if3_bim_io_req_ready; // @[IF3.scala 213:53]
  wire  if3__GEN_226 = if3__T_98 ? if3__GEN_223 : if3__reAlign_2_ready_T_1; // @[IF3.scala 208:103 213:26]
  wire  if3__GEN_229 = if3__GEN_138 ? if3__GEN_226 : if3__GEN_223; // @[IF3.scala 207:27]
  wire  if3__GEN_241 = if3__T_97 ? 1'h0 : if3__GEN_229; // @[IF3.scala 242:100 245:28]
  wire  if3__GEN_245 = if3__GEN_137 ? if3__GEN_241 : if3__GEN_229; // @[IF3.scala 241:27]
  wire  if3__GEN_249 = if3__T_98 ? 1'h0 : if3__GEN_245; // @[IF3.scala 252:103 255:28]
  wire  if3__GEN_253 = if3__GEN_138 ? if3__GEN_249 : if3__GEN_245; // @[IF3.scala 251:27]
  wire  if3__GEN_264 = if3__T_102 ? 1'h0 : if3__GEN_253; // @[IF3.scala 271:44 272:26]
  wire  if3__GEN_265 = if3__T_101 ? 1'h0 : if3__GEN_264; // @[IF3.scala 271:44 272:26]
  wire  if3__GEN_287 = if3_is_lock_pipe_1 ? 1'h0 : if3__GEN_265; // @[IF3.scala 234:29 237:26]
  wire  if3__GEN_293 = if3__GEN_23 ? 1'h0 : if3__GEN_287; // @[IF3.scala 242:100 245:28]
  wire  if3__GEN_299 = if3__GEN_91 ? if3__GEN_293 : if3__GEN_287; // @[IF3.scala 241:27]
  wire  if3__GEN_305 = if3__GEN_24 ? 1'h0 : if3__GEN_299; // @[IF3.scala 252:103 255:28]
  wire  if3__GEN_311 = if3__GEN_92 ? if3__GEN_305 : if3__GEN_299; // @[IF3.scala 251:27]
  wire  if3__GEN_350 = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_311; // @[IF3.scala 234:29 237:26]
  wire  if3__io_if3_req_2_ready_T_12 = if3__GEN_350 & if3__predictor_ready_T; // @[IF3.scala 113:55]
  wire  if3__io_if3_req_2_ready_T_14 = if3__io_if3_req_2_ready_T_12 & if3__reAlign_0_valid_T_4; // @[IF3.scala 113:73]
  wire  if3__io_if3_req_2_ready_T_15 = if3__io_if3_req_2_ready_T_14 & if3_io_if3_req_3_valid; // @[IF3.scala 113:89]
  wire  if3__T_55 = if3__reAlign_1_valid_T_1 == if3__reAlign_2_valid_T_1; // @[IF3.scala 132:37]
  wire  if3__T_58 = ~if3__T_55; // @[IF3.scala 132:17]
  wire  if3__reAlign_2_valid_T_13 = if3__reAlign_1_valid_T_1 & if3__predictor_ready_T; // @[IF3.scala 143:57]
  wire  if3__reAlign_2_valid_T_15 = if3__reAlign_2_valid_T_13 & if3__reAlign_0_valid_T_4; // @[IF3.scala 143:75]
  wire [31:0] if3__GEN_118 = if3_is_instr32_2 ? if3__reAlign_2_bits_instr_T_1 : {{16'd0}, if3_io_if3_req_2_bits_instr}; // @[IF3.scala 102:31 106:38 137:33]
  wire  if3__GEN_124 = if3_is_instr32_2 ? if3_io_if3_req_3_bits_isFault : 1'h1; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_125 = if3_is_instr32_2 & if3__reAlignPreDecode_2_T_1_is_fencei; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_126 = if3_is_instr32_2 & if3__reAlignPreDecode_2_T_1_is_sfencevma; // @[IF3.scala 102:31 107:31 138:31]
  wire  if3__GEN_141 = if3__T_6 & if3__GEN_124; // @[IF3.scala 101:33 97:25]
  wire  if3__GEN_129 = if3_is_instr32_2 ? if3__reAlign_2_valid_T_5 : if3__reAlign_2_valid_T_15; // @[IF3.scala 102:31]
  wire  if3__GEN_130 = if3_is_instr32_2 ? if3__io_if3_req_2_ready_T_15 : if3__io_if3_req_2_ready_T_14; // @[IF3.scala 102:31]
  wire  if3__GEN_131 = if3_is_instr32_2 & if3__io_if3_req_2_ready_T_14; // @[IF3.scala 102:31]
  wire [38:0] if3__GEN_132 = if3__T_6 ? if3_io_if3_req_2_bits_pc : 39'h0; // @[IF3.scala 101:33 96:22]
  wire  if3__GEN_142 = if3__T_6 & if3__GEN_125; // @[IF3.scala 101:33 97:25]
  wire  if3__GEN_143 = if3__T_6 & if3__GEN_126; // @[IF3.scala 101:33 97:25]
  wire  if3__GEN_146 = if3__T_6 & if3__GEN_129; // @[IF3.scala 101:33 95:22]
  wire  if3__GEN_148 = if3__T_6 & if3__GEN_131; // @[IF3.scala 101:33]
  wire  if3__T_61 = if3__reAlign_1_valid_T_1 & if3_io_if3_req_2_bits_isRedirect; // @[IF3.scala 160:33]
  wire  if3__T_65 = ~if3__reAlign_2_valid_T_1; // @[IF3.scala 160:75]
  wire  if3__T_67 = if3_io_if3_req_3_valid & if3_io_if3_req_3_bits_isRedirect; // @[IF3.scala 161:101]
  wire  if3__T_68 = ~if3__T_67; // @[IF3.scala 161:77]
  wire  if3__T_71 = ~if3__T_68; // @[IF3.scala 161:75]
  wire  if3__T_72 = ~if3__GEN_3; // @[IF3.scala 101:13]
  wire  if3__reAlign_3_valid_T_1 = if3__reAlign_2_valid_T_1 & if3__predictor_ready_T; // @[IF3.scala 143:57]
  wire  if3__reAlign_3_valid_T_3 = if3__reAlign_3_valid_T_1 & if3__reAlign_0_valid_T_4; // @[IF3.scala 143:75]
  wire  if3_is_lock_pipe_2 = if3__GEN_142 | if3__GEN_143; // @[frontend.scala 100:32]
  wire  if3__T_93 = ~if3__GEN_350; // @[IF3.scala 271:30]
  wire  if3__GEN_157 = if3_is_instr32_3 ? 1'h0 : if3__reAlignPreDecode_2_info16_is_branch_T_1; // @[IF3.scala 102:31 97:25 138:31]
  wire  if3__GEN_173 = if3__T_72 & if3__GEN_157; // @[IF3.scala 101:33 97:25]
  wire  if3__T_88 = if3__T_98 | if3__GEN_138; // @[IF3.scala 252:94]
  wire  if3__GEN_156 = if3_is_instr32_3 ? 1'h0 : if3__reAlignPreDecode_2_info16_is_jalr_T_4; // @[IF3.scala 102:31 97:25 138:31]
  wire  if3__GEN_172 = if3__T_72 & if3__GEN_156; // @[IF3.scala 101:33 97:25]
  wire  if3__T_86 = if3__T_97 | if3__GEN_137; // @[IF3.scala 242:92]
  wire  if3__reAlign_3_ready_T = if3_combPDT_io_enq_3_ready & if3_btb_io_req_ready; // @[IF3.scala 202:53]
  wire  if3__GEN_185 = if3__T_86 ? if3_combPDT_io_enq_3_ready : if3__reAlign_3_ready_T; // @[IF3.scala 197:100 179:11 202:26]
  wire  if3__GEN_188 = if3__GEN_172 ? if3__GEN_185 : if3_combPDT_io_enq_3_ready; // @[IF3.scala 179:11 196:27]
  wire  if3__reAlign_3_ready_T_1 = if3_combPDT_io_enq_3_ready & if3_bim_io_req_ready; // @[IF3.scala 213:53]
  wire  if3__GEN_191 = if3__T_88 ? if3__GEN_188 : if3__reAlign_3_ready_T_1; // @[IF3.scala 208:103 213:26]
  wire  if3__GEN_194 = if3__GEN_173 ? if3__GEN_191 : if3__GEN_188; // @[IF3.scala 207:27]
  wire  if3__GEN_204 = if3__T_86 ? 1'h0 : if3__GEN_194; // @[IF3.scala 242:100 245:28]
  wire  if3__GEN_206 = if3__GEN_172 ? if3__GEN_204 : if3__GEN_194; // @[IF3.scala 241:27]
  wire  if3__GEN_208 = if3__T_88 ? 1'h0 : if3__GEN_206; // @[IF3.scala 252:103 255:28]
  wire  if3__GEN_210 = if3__GEN_173 ? if3__GEN_208 : if3__GEN_206; // @[IF3.scala 251:27]
  wire  if3__GEN_215 = if3__T_102 ? 1'h0 : if3__GEN_210; // @[IF3.scala 271:44 272:26]
  wire  if3__GEN_216 = if3__T_101 ? 1'h0 : if3__GEN_215; // @[IF3.scala 271:44 272:26]
  wire  if3__GEN_217 = if3__T_93 ? 1'h0 : if3__GEN_216; // @[IF3.scala 271:44 272:26]
  wire  if3__GEN_239 = if3_is_lock_pipe_2 ? 1'h0 : if3__GEN_217; // @[IF3.scala 234:29 237:26]
  wire  if3__GEN_243 = if3__T_97 ? 1'h0 : if3__GEN_239; // @[IF3.scala 242:100 245:28]
  wire  if3__GEN_247 = if3__GEN_137 ? if3__GEN_243 : if3__GEN_239; // @[IF3.scala 241:27]
  wire  if3__GEN_251 = if3__T_98 ? 1'h0 : if3__GEN_247; // @[IF3.scala 252:103 255:28]
  wire  if3__GEN_255 = if3__GEN_138 ? if3__GEN_251 : if3__GEN_247; // @[IF3.scala 251:27]
  wire  if3__GEN_289 = if3_is_lock_pipe_1 ? 1'h0 : if3__GEN_255; // @[IF3.scala 234:29 237:26]
  wire  if3__GEN_295 = if3__GEN_23 ? 1'h0 : if3__GEN_289; // @[IF3.scala 242:100 245:28]
  wire  if3__GEN_301 = if3__GEN_91 ? if3__GEN_295 : if3__GEN_289; // @[IF3.scala 241:27]
  wire  if3__GEN_307 = if3__GEN_24 ? 1'h0 : if3__GEN_301; // @[IF3.scala 252:103 255:28]
  wire  if3__GEN_313 = if3__GEN_92 ? if3__GEN_307 : if3__GEN_301; // @[IF3.scala 251:27]
  wire  if3__GEN_352 = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_313; // @[IF3.scala 234:29 237:26]
  wire  if3__io_if3_req_3_ready_T_9 = if3__GEN_352 & if3__predictor_ready_T; // @[IF3.scala 144:55]
  wire  if3__io_if3_req_3_ready_T_11 = if3__io_if3_req_3_ready_T_9 & if3__reAlign_0_valid_T_4; // @[IF3.scala 144:73]
  wire [38:0] if3__GEN_151 = if3_is_instr32_3 ? 39'h0 : if3_io_if3_req_3_bits_pc; // @[IF3.scala 102:31 96:22 134:33]
  wire [31:0] if3__GEN_154 = if3_is_instr32_3 ? 32'h0 : {{16'd0}, if3_io_if3_req_3_bits_instr}; // @[IF3.scala 102:31 96:22 137:33]
  wire  if3__GEN_160 = if3_is_instr32_3 ? 1'h0 : 1'h1; // @[IF3.scala 102:31 97:25 138:31]
  wire  if3__GEN_176 = if3__T_72 & if3__GEN_160; // @[IF3.scala 101:33 97:25]
  wire  if3__GEN_164 = if3_is_instr32_3 ? 1'h0 : if3__GEN_176; // @[IF3.scala 102:31 96:22 139:33]
  wire  if3__GEN_165 = if3_is_instr32_3 ? 1'h0 : if3__reAlign_3_valid_T_3; // @[IF3.scala 102:31 95:22]
  wire  if3__GEN_166 = if3_is_instr32_3 ? if3__GEN_148 : if3__io_if3_req_3_ready_T_11; // @[IF3.scala 102:31]
  wire [38:0] if3__GEN_167 = if3__T_72 ? if3__GEN_151 : 39'h0; // @[IF3.scala 101:33 96:22]
  wire  if3__GEN_181 = if3__T_72 & if3__GEN_165; // @[IF3.scala 101:33 95:22]
  wire  if3__T_75 = ~if3_io_if3_req_3_bits_isRedirect; // @[IF3.scala 163:44]
  wire  if3__T_78 = ~if3__T_75; // @[IF3.scala 163:42]
  wire  if3__btb_io_req_valid_T = if3_io_flush | if3_io_if4Redirect_valid; // @[IF3.scala 200:59]
  wire  if3__btb_io_req_valid_T_1 = ~if3__btb_io_req_valid_T; // @[IF3.scala 200:48]
  wire  if3__GEN_203 = if3__T_86 ? 1'h0 : if3__GEN_181; // @[IF3.scala 242:100 244:28]
  wire  if3__GEN_205 = if3__GEN_172 ? if3__GEN_203 : if3__GEN_181; // @[IF3.scala 241:27]
  wire  if3__GEN_207 = if3__T_88 ? 1'h0 : if3__GEN_205; // @[IF3.scala 252:103 254:28]
  wire  if3__GEN_209 = if3__GEN_173 ? if3__GEN_207 : if3__GEN_205; // @[IF3.scala 251:27]
  wire  if3__GEN_238 = if3_is_lock_pipe_2 ? 1'h0 : if3__GEN_209; // @[IF3.scala 234:29 236:26]
  wire  if3__GEN_242 = if3__T_97 ? 1'h0 : if3__GEN_238; // @[IF3.scala 242:100 244:28]
  wire  if3__GEN_246 = if3__GEN_137 ? if3__GEN_242 : if3__GEN_238; // @[IF3.scala 241:27]
  wire  if3__GEN_250 = if3__T_98 ? 1'h0 : if3__GEN_246; // @[IF3.scala 252:103 254:28]
  wire  if3__GEN_254 = if3__GEN_138 ? if3__GEN_250 : if3__GEN_246; // @[IF3.scala 251:27]
  wire  if3__GEN_288 = if3_is_lock_pipe_1 ? 1'h0 : if3__GEN_254; // @[IF3.scala 234:29 236:26]
  wire  if3__GEN_294 = if3__GEN_23 ? 1'h0 : if3__GEN_288; // @[IF3.scala 242:100 244:28]
  wire  if3__GEN_300 = if3__GEN_91 ? if3__GEN_294 : if3__GEN_288; // @[IF3.scala 241:27]
  wire  if3__GEN_306 = if3__GEN_24 ? 1'h0 : if3__GEN_300; // @[IF3.scala 252:103 254:28]
  wire  if3__GEN_312 = if3__GEN_92 ? if3__GEN_306 : if3__GEN_300; // @[IF3.scala 251:27]
  wire  if3__GEN_351 = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_312; // @[IF3.scala 234:29 236:26]
  wire  if3__btb_io_req_valid_T_2 = if3__GEN_351 & if3__btb_io_req_valid_T_1; // @[IF3.scala 200:46]
  wire  if3__GEN_183 = if3__T_86 ? 1'h0 : if3__btb_io_req_valid_T_2; // @[IF3.scala 197:100 185:20 200:26]
  wire [38:0] if3__GEN_184 = if3__T_86 ? 39'h0 : if3__GEN_167; // @[IF3.scala 197:100 182:22 201:28]
  wire  if3__GEN_186 = if3__GEN_172 & if3__GEN_183; // @[IF3.scala 185:20 196:27]
  wire [38:0] if3__GEN_187 = if3__GEN_172 ? if3__GEN_184 : 39'h0; // @[IF3.scala 182:22 196:27]
  wire  if3__GEN_189 = if3__T_88 ? 1'h0 : if3__btb_io_req_valid_T_2; // @[IF3.scala 208:103 186:20 211:26]
  wire [38:0] if3__GEN_190 = if3__T_88 ? 39'h0 : if3__GEN_167; // @[IF3.scala 208:103 183:22 212:28]
  wire  if3__GEN_192 = if3__GEN_173 & if3__GEN_189; // @[IF3.scala 186:20 207:27]
  wire [38:0] if3__GEN_193 = if3__GEN_173 ? if3__GEN_190 : 39'h0; // @[IF3.scala 183:22 207:27]
  wire  if3__GEN_240 = if3__T_97 ? 1'h0 : if3__GEN_146; // @[IF3.scala 242:100 244:28]
  wire  if3__GEN_244 = if3__GEN_137 ? if3__GEN_240 : if3__GEN_146; // @[IF3.scala 241:27]
  wire  if3__GEN_248 = if3__T_98 ? 1'h0 : if3__GEN_244; // @[IF3.scala 252:103 254:28]
  wire  if3__GEN_252 = if3__GEN_138 ? if3__GEN_248 : if3__GEN_244; // @[IF3.scala 251:27]
  wire  if3__GEN_286 = if3_is_lock_pipe_1 ? 1'h0 : if3__GEN_252; // @[IF3.scala 234:29 236:26]
  wire  if3__GEN_292 = if3__GEN_23 ? 1'h0 : if3__GEN_286; // @[IF3.scala 242:100 244:28]
  wire  if3__GEN_298 = if3__GEN_91 ? if3__GEN_292 : if3__GEN_286; // @[IF3.scala 241:27]
  wire  if3__GEN_304 = if3__GEN_24 ? 1'h0 : if3__GEN_298; // @[IF3.scala 252:103 254:28]
  wire  if3__GEN_310 = if3__GEN_92 ? if3__GEN_304 : if3__GEN_298; // @[IF3.scala 251:27]
  wire  if3__GEN_349 = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_310; // @[IF3.scala 234:29 236:26]
  wire  if3__btb_io_req_valid_T_5 = if3__GEN_349 & if3__btb_io_req_valid_T_1; // @[IF3.scala 200:46]
  wire  if3__GEN_218 = if3__T_97 ? if3__GEN_186 : if3__btb_io_req_valid_T_5; // @[IF3.scala 197:100 200:26]
  wire [38:0] if3__GEN_219 = if3__T_97 ? if3__GEN_187 : if3__GEN_132; // @[IF3.scala 197:100 201:28]
  wire  if3__GEN_221 = if3__GEN_137 ? if3__GEN_218 : if3__GEN_186; // @[IF3.scala 196:27]
  wire [38:0] if3__GEN_222 = if3__GEN_137 ? if3__GEN_219 : if3__GEN_187; // @[IF3.scala 196:27]
  wire  if3__GEN_224 = if3__T_98 ? if3__GEN_192 : if3__btb_io_req_valid_T_5; // @[IF3.scala 208:103 211:26]
  wire [38:0] if3__GEN_225 = if3__T_98 ? if3__GEN_193 : if3__GEN_132; // @[IF3.scala 208:103 212:28]
  wire  if3__GEN_227 = if3__GEN_138 ? if3__GEN_224 : if3__GEN_192; // @[IF3.scala 207:27]
  wire [38:0] if3__GEN_228 = if3__GEN_138 ? if3__GEN_225 : if3__GEN_193; // @[IF3.scala 207:27]
  wire  if3__GEN_290 = if3__GEN_23 ? 1'h0 : if3__GEN_100; // @[IF3.scala 242:100 244:28]
  wire  if3__GEN_296 = if3__GEN_91 ? if3__GEN_290 : if3__GEN_100; // @[IF3.scala 241:27]
  wire  if3__GEN_302 = if3__GEN_24 ? 1'h0 : if3__GEN_296; // @[IF3.scala 252:103 254:28]
  wire  if3__GEN_308 = if3__GEN_92 ? if3__GEN_302 : if3__GEN_296; // @[IF3.scala 251:27]
  wire  if3__GEN_347 = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_308; // @[IF3.scala 234:29 236:26]
  wire  if3__btb_io_req_valid_T_8 = if3__GEN_347 & if3__btb_io_req_valid_T_1; // @[IF3.scala 200:46]
  wire  if3__GEN_266 = if3__GEN_23 ? if3__GEN_221 : if3__btb_io_req_valid_T_8; // @[IF3.scala 197:100 200:26]
  wire [38:0] if3__GEN_267 = if3__GEN_23 ? if3__GEN_222 : if3__GEN_86; // @[IF3.scala 197:100 201:28]
  wire  if3__GEN_269 = if3__GEN_91 ? if3__GEN_266 : if3__GEN_221; // @[IF3.scala 196:27]
  wire [38:0] if3__GEN_270 = if3__GEN_91 ? if3__GEN_267 : if3__GEN_222; // @[IF3.scala 196:27]
  wire  if3__GEN_272 = if3__GEN_24 ? if3__GEN_227 : if3__btb_io_req_valid_T_8; // @[IF3.scala 208:103 211:26]
  wire [38:0] if3__GEN_273 = if3__GEN_24 ? if3__GEN_228 : if3__GEN_86; // @[IF3.scala 208:103 212:28]
  wire  if3__GEN_275 = if3__GEN_92 ? if3__GEN_272 : if3__GEN_227; // @[IF3.scala 207:27]
  wire [38:0] if3__GEN_276 = if3__GEN_92 ? if3__GEN_273 : if3__GEN_228; // @[IF3.scala 207:27]
  wire  if3__btb_io_req_valid_T_11 = if3__GEN_32 & if3__btb_io_req_valid_T_1; // @[IF3.scala 200:46]
  wire  if3__T_105 = if3__GEN_338 & if3__GEN_32; // @[Decoupled.scala 52:35]
  wire  if3__T_106 = if3_is_lock_pipe_0 & if3__T_105; // @[IF3.scala 329:79]
  wire  if3__T_108 = if3__GEN_348 & if3__GEN_347; // @[Decoupled.scala 52:35]
  wire  if3__T_109 = if3_is_lock_pipe_1 & if3__T_108; // @[IF3.scala 329:79]
  wire  if3__T_111 = if3__GEN_350 & if3__GEN_349; // @[Decoupled.scala 52:35]
  wire  if3__T_112 = if3_is_lock_pipe_2 & if3__T_111; // @[IF3.scala 329:79]
  wire  if3__T_116 = if3__T_106 | if3__T_109; // @[IF3.scala 329:107]
  wire  if3__T_117 = if3__T_116 | if3__T_112; // @[IF3.scala 329:107]
  wire  if3__GEN_401 = if3__T_117 | if3_pipeLineLock; // @[IF3.scala 329:{113,128} 54:29]
  wire  if4_clock;
  wire  if4_reset;
  wire  if4_io_if4_req_0_ready;
  wire  if4_io_if4_req_0_valid;
  wire  if4_io_if4_req_0_bits_isRVC;
  wire [31:0] if4_io_if4_req_0_bits_instr;
  wire [38:0] if4_io_if4_req_0_bits_pc;
  wire  if4_io_if4_req_0_bits_isRedirect;
  wire [38:0] if4_io_if4_req_0_bits_target;
  wire  if4_io_btbResp_0_ready;
  wire  if4_io_btbResp_0_valid;
  wire [38:0] if4_io_btbResp_0_bits_target;
  wire  if4_io_bimResp_0_ready;
  wire  if4_io_bimResp_0_valid;
  wire  if4_io_bimResp_0_bits_bim_p;
  wire  if4_io_bimResp_0_bits_bim_h;
  wire  if4_io_tageResp_0_ready;
  wire  if4_io_if4_resp_0_ready;
  wire  if4_io_if4_resp_0_valid;
  wire  if4_io_if4_resp_0_bits_alu_isa_lui;
  wire  if4_io_if4_resp_0_bits_alu_isa_auipc;
  wire  if4_io_if4_resp_0_bits_alu_isa_addi;
  wire  if4_io_if4_resp_0_bits_alu_isa_addiw;
  wire  if4_io_if4_resp_0_bits_alu_isa_slti;
  wire  if4_io_if4_resp_0_bits_alu_isa_sltiu;
  wire  if4_io_if4_resp_0_bits_alu_isa_xori;
  wire  if4_io_if4_resp_0_bits_alu_isa_ori;
  wire  if4_io_if4_resp_0_bits_alu_isa_andi;
  wire  if4_io_if4_resp_0_bits_alu_isa_slli;
  wire  if4_io_if4_resp_0_bits_alu_isa_slliw;
  wire  if4_io_if4_resp_0_bits_alu_isa_srli;
  wire  if4_io_if4_resp_0_bits_alu_isa_srliw;
  wire  if4_io_if4_resp_0_bits_alu_isa_srai;
  wire  if4_io_if4_resp_0_bits_alu_isa_sraiw;
  wire  if4_io_if4_resp_0_bits_alu_isa_add;
  wire  if4_io_if4_resp_0_bits_alu_isa_addw;
  wire  if4_io_if4_resp_0_bits_alu_isa_sub;
  wire  if4_io_if4_resp_0_bits_alu_isa_subw;
  wire  if4_io_if4_resp_0_bits_alu_isa_sll;
  wire  if4_io_if4_resp_0_bits_alu_isa_sllw;
  wire  if4_io_if4_resp_0_bits_alu_isa_slt;
  wire  if4_io_if4_resp_0_bits_alu_isa_sltu;
  wire  if4_io_if4_resp_0_bits_alu_isa_xor;
  wire  if4_io_if4_resp_0_bits_alu_isa_srl;
  wire  if4_io_if4_resp_0_bits_alu_isa_srlw;
  wire  if4_io_if4_resp_0_bits_alu_isa_sra;
  wire  if4_io_if4_resp_0_bits_alu_isa_sraw;
  wire  if4_io_if4_resp_0_bits_alu_isa_or;
  wire  if4_io_if4_resp_0_bits_alu_isa_and;
  wire  if4_io_if4_resp_0_bits_alu_isa_wfi;
  wire  if4_io_if4_resp_0_bits_bru_isa_jal;
  wire  if4_io_if4_resp_0_bits_bru_isa_jalr;
  wire  if4_io_if4_resp_0_bits_bru_isa_beq;
  wire  if4_io_if4_resp_0_bits_bru_isa_bne;
  wire  if4_io_if4_resp_0_bits_bru_isa_blt;
  wire  if4_io_if4_resp_0_bits_bru_isa_bge;
  wire  if4_io_if4_resp_0_bits_bru_isa_bltu;
  wire  if4_io_if4_resp_0_bits_bru_isa_bgeu;
  wire  if4_io_if4_resp_0_bits_lsu_isa_lb;
  wire  if4_io_if4_resp_0_bits_lsu_isa_lh;
  wire  if4_io_if4_resp_0_bits_lsu_isa_lw;
  wire  if4_io_if4_resp_0_bits_lsu_isa_ld;
  wire  if4_io_if4_resp_0_bits_lsu_isa_lbu;
  wire  if4_io_if4_resp_0_bits_lsu_isa_lhu;
  wire  if4_io_if4_resp_0_bits_lsu_isa_lwu;
  wire  if4_io_if4_resp_0_bits_lsu_isa_sb;
  wire  if4_io_if4_resp_0_bits_lsu_isa_sh;
  wire  if4_io_if4_resp_0_bits_lsu_isa_sw;
  wire  if4_io_if4_resp_0_bits_lsu_isa_sd;
  wire  if4_io_if4_resp_0_bits_lsu_isa_fence;
  wire  if4_io_if4_resp_0_bits_lsu_isa_fence_i;
  wire  if4_io_if4_resp_0_bits_lsu_isa_sfence_vma;
  wire  if4_io_if4_resp_0_bits_lsu_isa_lr_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_sc_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoswap_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoadd_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoxor_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoand_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoor_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amomin_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amomax_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amominu_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amomaxu_w;
  wire  if4_io_if4_resp_0_bits_lsu_isa_lr_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_sc_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoswap_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoadd_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoxor_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoand_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amoor_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amomin_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amomax_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amominu_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_amomaxu_d;
  wire  if4_io_if4_resp_0_bits_lsu_isa_flw;
  wire  if4_io_if4_resp_0_bits_lsu_isa_fsw;
  wire  if4_io_if4_resp_0_bits_lsu_isa_fld;
  wire  if4_io_if4_resp_0_bits_lsu_isa_fsd;
  wire  if4_io_if4_resp_0_bits_csr_isa_rw;
  wire  if4_io_if4_resp_0_bits_csr_isa_rs;
  wire  if4_io_if4_resp_0_bits_csr_isa_rc;
  wire  if4_io_if4_resp_0_bits_csr_isa_rwi;
  wire  if4_io_if4_resp_0_bits_csr_isa_rsi;
  wire  if4_io_if4_resp_0_bits_csr_isa_rci;
  wire  if4_io_if4_resp_0_bits_mul_isa_mul;
  wire  if4_io_if4_resp_0_bits_mul_isa_mulh;
  wire  if4_io_if4_resp_0_bits_mul_isa_mulhsu;
  wire  if4_io_if4_resp_0_bits_mul_isa_mulhu;
  wire  if4_io_if4_resp_0_bits_mul_isa_div;
  wire  if4_io_if4_resp_0_bits_mul_isa_divu;
  wire  if4_io_if4_resp_0_bits_mul_isa_rem;
  wire  if4_io_if4_resp_0_bits_mul_isa_remu;
  wire  if4_io_if4_resp_0_bits_mul_isa_mulw;
  wire  if4_io_if4_resp_0_bits_mul_isa_divw;
  wire  if4_io_if4_resp_0_bits_mul_isa_divuw;
  wire  if4_io_if4_resp_0_bits_mul_isa_remw;
  wire  if4_io_if4_resp_0_bits_mul_isa_remuw;
  wire  if4_io_if4_resp_0_bits_privil_isa_ecall;
  wire  if4_io_if4_resp_0_bits_privil_isa_ebreak;
  wire  if4_io_if4_resp_0_bits_privil_isa_mret;
  wire  if4_io_if4_resp_0_bits_privil_isa_uret;
  wire  if4_io_if4_resp_0_bits_privil_isa_sret;
  wire  if4_io_if4_resp_0_bits_privil_isa_dret;
  wire  if4_io_if4_resp_0_bits_privil_isa_hfence_vvma;
  wire  if4_io_if4_resp_0_bits_privil_isa_hfence_gvma;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlv_b;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlv_bu;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlv_h;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlv_hu;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlvx_hu;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlv_w;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlvx_wu;
  wire  if4_io_if4_resp_0_bits_privil_isa_hsv_b;
  wire  if4_io_if4_resp_0_bits_privil_isa_hsv_h;
  wire  if4_io_if4_resp_0_bits_privil_isa_hsv_w;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlv_wu;
  wire  if4_io_if4_resp_0_bits_privil_isa_hlv_d;
  wire  if4_io_if4_resp_0_bits_privil_isa_hsv_d;
  wire  if4_io_if4_resp_0_bits_privil_isa_is_access_fault;
  wire  if4_io_if4_resp_0_bits_privil_isa_is_paging_fault;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmadd_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmsub_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fnmsub_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fnmadd_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fadd_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsub_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmul_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fdiv_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsqrt_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsgnj_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsgnjn_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsgnjx_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmin_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmax_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_w_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_wu_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmv_x_w;
  wire  if4_io_if4_resp_0_bits_fpu_isa_feq_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_flt_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fle_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fclass_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_w;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_wu;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmv_w_x;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_l_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_lu_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_l;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_lu;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmadd_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmsub_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fnmsub_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fnmadd_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fadd_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsub_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmul_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fdiv_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsqrt_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsgnj_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsgnjn_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fsgnjx_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmin_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmax_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_s;
  wire  if4_io_if4_resp_0_bits_fpu_isa_feq_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_flt_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fle_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fclass_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_w_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_wu_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_w;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_wu;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_l_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_lu_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmv_x_d;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_l;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_lu;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fmv_d_x;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcsr_rw;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcsr_rs;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcsr_rc;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcsr_rwi;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcsr_rsi;
  wire  if4_io_if4_resp_0_bits_fpu_isa_fcsr_rci;
  wire  if4_io_if4_resp_0_bits_param_is_rvc;
  wire [38:0] if4_io_if4_resp_0_bits_param_pc;
  wire [63:0] if4_io_if4_resp_0_bits_param_imm;
  wire [4:0] if4_io_if4_resp_0_bits_param_raw_rs1;
  wire [4:0] if4_io_if4_resp_0_bits_param_raw_rs2;
  wire [4:0] if4_io_if4_resp_0_bits_param_raw_rd0;
  wire  if4_io_if4Redirect_valid;
  wire [38:0] if4_io_if4Redirect_bits_target;
  wire  if4_io_bftq_ready;
  wire  if4_io_bftq_valid;
  wire [38:0] if4_io_bftq_bits_pc;
  wire  if4_io_bftq_bits_bimResp_bim_p;
  wire  if4_io_bftq_bits_bimResp_bim_h;
  wire  if4_io_bftq_bits_isPredictTaken;
  wire  if4_io_jftq_ready;
  wire  if4_io_jftq_valid;
  wire [38:0] if4_io_jftq_bits_pc;
  wire [38:0] if4_io_jftq_bits_btbResp_target;
  wire [38:0] if4_io_jftq_bits_rasResp_target;
  wire  if4_io_jftq_bits_isRas;
  wire  if4_io_flush;
  wire  if4_ras_clock;
  wire  if4_ras_reset;
  wire  if4_ras_io_enq_valid;
  wire [38:0] if4_ras_io_enq_bits_target;
  wire  if4_ras_io_deq_ready;
  wire  if4_ras_io_deq_valid;
  wire [38:0] if4_ras_io_deq_bits_target;
  wire  if4_ras_io_flush;
  reg [38:0] if4_ras_buf_target [0:3]; // @[RAS.scala 43:18]
  wire  if4_ras_buf_target_io_deq_bits_MPORT_en; // @[RAS.scala 43:18]
  wire [1:0] if4_ras_buf_target_io_deq_bits_MPORT_addr; // @[RAS.scala 43:18]
  wire [38:0] if4_ras_buf_target_io_deq_bits_MPORT_data; // @[RAS.scala 43:18]
  wire [38:0] if4_ras_buf_target_MPORT_data; // @[RAS.scala 43:18]
  wire [1:0] if4_ras_buf_target_MPORT_addr; // @[RAS.scala 43:18]
  wire  if4_ras_buf_target_MPORT_mask; // @[RAS.scala 43:18]
  wire  if4_ras_buf_target_MPORT_en; // @[RAS.scala 43:18]
  wire  if4_ras_buf_target_clock;
  reg [2:0] if4_ras_btm_ptr; // @[RAS.scala 44:26]
  reg [2:0] if4_ras_top_ptr; // @[RAS.scala 45:26]
  wire [1:0] if4_ras__rd_idx_T = if4_ras_top_ptr[1:0]; // @[RAS.scala 47:25]
  wire  if4_ras_is_empty = if4_ras_btm_ptr == if4_ras_top_ptr; // @[RAS.scala 50:29]
  wire [1:0] if4_ras__is_full_T = if4_ras_btm_ptr[1:0]; // @[RAS.scala 51:29]
  wire  if4_ras__is_full_T_2 = if4_ras__is_full_T == if4_ras__rd_idx_T; // @[RAS.scala 51:39]
  wire  if4_ras__is_full_T_3 = if4_ras_btm_ptr[2]; // @[RAS.scala 51:71]
  wire  if4_ras__is_full_T_4 = if4_ras_top_ptr[2]; // @[RAS.scala 51:87]
  wire  if4_ras__is_full_T_5 = if4_ras__is_full_T_3 != if4_ras__is_full_T_4; // @[RAS.scala 51:76]
  wire  if4_ras_is_full = if4_ras__is_full_T_2 & if4_ras__is_full_T_5; // @[RAS.scala 51:61]
  wire [2:0] if4_ras__btm_ptr_T_1 = if4_ras_btm_ptr + 3'h1; // @[RAS.scala 66:30]
  wire [2:0] if4_ras__top_ptr_T_1 = if4_ras_top_ptr + 3'h1; // @[RAS.scala 68:28]
  wire  if4_ras__T = if4_ras_io_deq_ready & if4_ras_io_deq_valid; // @[Decoupled.scala 52:35]
  wire [2:0] if4_ras__top_ptr_T_3 = if4_ras_top_ptr - 3'h1; // @[RAS.scala 71:28]
  reg [38:0] if4_ras_io_deq_bits_REG_target; // @[RAS.scala 76:29]
  wire  if4_instr_fifo_clock;
  wire  if4_instr_fifo_reset;
  wire  if4_instr_fifo_io_enq_0_ready;
  wire  if4_instr_fifo_io_enq_0_valid;
  wire  if4_instr_fifo_io_deq_0_ready;
  wire  if4_instr_fifo_io_deq_0_valid;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_lui;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_auipc;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_addi;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_addiw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_slti;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_sltiu;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_xori;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_ori;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_andi;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_slli;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_slliw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_srli;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_srliw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_srai;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_sraiw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_add;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_addw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_sub;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_subw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_sll;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_sllw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_slt;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_sltu;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_xor;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_srl;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_srlw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_sra;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_sraw;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_or;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_and;
  wire  if4_instr_fifo_io_deq_0_bits_alu_isa_wfi;
  wire  if4_instr_fifo_io_deq_0_bits_bru_isa_jal;
  wire  if4_instr_fifo_io_deq_0_bits_bru_isa_jalr;
  wire  if4_instr_fifo_io_deq_0_bits_bru_isa_beq;
  wire  if4_instr_fifo_io_deq_0_bits_bru_isa_bne;
  wire  if4_instr_fifo_io_deq_0_bits_bru_isa_blt;
  wire  if4_instr_fifo_io_deq_0_bits_bru_isa_bge;
  wire  if4_instr_fifo_io_deq_0_bits_bru_isa_bltu;
  wire  if4_instr_fifo_io_deq_0_bits_bru_isa_bgeu;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_lb;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_lh;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_lw;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_ld;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_lbu;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_lhu;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_lwu;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_sb;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_sh;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_sw;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_sd;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_fence;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_fence_i;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_sfence_vma;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_lr_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_sc_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoswap_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoadd_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoxor_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoand_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoor_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amomin_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amomax_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amominu_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amomaxu_w;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_lr_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_sc_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoswap_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoadd_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoxor_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoand_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amoor_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amomin_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amomax_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amominu_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_amomaxu_d;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_flw;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_fsw;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_fld;
  wire  if4_instr_fifo_io_deq_0_bits_lsu_isa_fsd;
  wire  if4_instr_fifo_io_deq_0_bits_csr_isa_rw;
  wire  if4_instr_fifo_io_deq_0_bits_csr_isa_rs;
  wire  if4_instr_fifo_io_deq_0_bits_csr_isa_rc;
  wire  if4_instr_fifo_io_deq_0_bits_csr_isa_rwi;
  wire  if4_instr_fifo_io_deq_0_bits_csr_isa_rsi;
  wire  if4_instr_fifo_io_deq_0_bits_csr_isa_rci;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_mul;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_mulh;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_mulhsu;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_mulhu;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_div;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_divu;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_rem;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_remu;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_mulw;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_divw;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_divuw;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_remw;
  wire  if4_instr_fifo_io_deq_0_bits_mul_isa_remuw;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_ecall;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_ebreak;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_mret;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_uret;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_sret;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_dret;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hfence_vvma;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hfence_gvma;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_b;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_bu;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_h;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_hu;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlvx_hu;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_w;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlvx_wu;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_b;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_h;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_w;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_wu;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_d;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_d;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_is_access_fault;
  wire  if4_instr_fifo_io_deq_0_bits_privil_isa_is_paging_fault;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmadd_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmsub_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmsub_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmadd_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fadd_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsub_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmul_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fdiv_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsqrt_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnj_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjn_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjx_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmin_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmax_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_w_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_wu_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_x_w;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_feq_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_flt_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fle_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fclass_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_w;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_wu;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_w_x;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_l_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_lu_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_l;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_lu;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmadd_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmsub_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmsub_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmadd_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fadd_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsub_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmul_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fdiv_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsqrt_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnj_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjn_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjx_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmin_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmax_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_s;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_feq_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_flt_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fle_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fclass_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_w_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_wu_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_w;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_wu;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_l_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_lu_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_x_d;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_l;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_lu;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_d_x;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rw;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rs;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rc;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rwi;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rsi;
  wire  if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rci;
  wire  if4_instr_fifo_io_deq_0_bits_param_is_rvc;
  wire [38:0] if4_instr_fifo_io_deq_0_bits_param_pc;
  wire [63:0] if4_instr_fifo_io_deq_0_bits_param_imm;
  wire [4:0] if4_instr_fifo_io_deq_0_bits_param_raw_rs1;
  wire [4:0] if4_instr_fifo_io_deq_0_bits_param_raw_rs2;
  wire [4:0] if4_instr_fifo_io_deq_0_bits_param_raw_rd0;
  wire  if4_instr_fifo_io_flush;
  reg  if4_instr_fifo_buf_0_alu_isa_lui; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_auipc; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_addi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_addiw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_slti; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_sltiu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_xori; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_ori; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_andi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_slli; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_slliw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_srli; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_srliw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_srai; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_sraiw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_add; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_addw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_sub; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_subw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_sll; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_sllw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_slt; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_sltu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_xor; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_srl; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_srlw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_sra; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_sraw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_or; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_and; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_alu_isa_wfi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_bru_isa_jal; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_bru_isa_jalr; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_bru_isa_beq; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_bru_isa_bne; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_bru_isa_blt; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_bru_isa_bge; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_bru_isa_bltu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_bru_isa_bgeu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_lb; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_lh; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_lw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_ld; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_lbu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_lhu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_lwu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_sb; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_sh; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_sw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_sd; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_fence; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_fence_i; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_sfence_vma; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_lr_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_sc_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoswap_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoadd_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoxor_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoand_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoor_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amomin_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amomax_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amominu_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amomaxu_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_lr_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_sc_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoswap_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoadd_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoxor_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoand_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amoor_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amomin_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amomax_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amominu_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_amomaxu_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_flw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_fsw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_fld; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_lsu_isa_fsd; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_csr_isa_rw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_csr_isa_rs; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_csr_isa_rc; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_csr_isa_rwi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_csr_isa_rsi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_csr_isa_rci; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_mul; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_mulh; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_mulhsu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_mulhu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_div; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_divu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_rem; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_remu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_mulw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_divw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_divuw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_remw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_mul_isa_remuw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_ecall; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_ebreak; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_mret; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_uret; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_sret; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_dret; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hfence_vvma; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hfence_gvma; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlv_b; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlv_bu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlv_h; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlv_hu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlvx_hu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlv_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlvx_wu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hsv_b; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hsv_h; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hsv_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlv_wu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hlv_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_hsv_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_is_access_fault; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_privil_isa_is_paging_fault; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmadd_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmsub_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fnmsub_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fnmadd_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fadd_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsub_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmul_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fdiv_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsqrt_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsgnj_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsgnjn_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsgnjx_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmin_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmax_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_w_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmv_x_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_feq_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_flt_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fle_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fclass_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_wu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmv_w_x; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_l_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_l; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_lu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmadd_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmsub_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fnmsub_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fnmadd_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fadd_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsub_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmul_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fdiv_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsqrt_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsgnj_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsgnjn_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fsgnjx_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmin_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmax_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_feq_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_flt_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fle_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fclass_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_w_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_wu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_l_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmv_x_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_l; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_lu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fmv_d_x; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcsr_rw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcsr_rs; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcsr_rc; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcsr_rwi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcsr_rsi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_fpu_isa_fcsr_rci; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_0_param_is_rvc; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if4_instr_fifo_buf_0_param_pc; // @[MultiPortFifo.scala 57:20]
  reg [63:0] if4_instr_fifo_buf_0_param_imm; // @[MultiPortFifo.scala 57:20]
  reg [4:0] if4_instr_fifo_buf_0_param_raw_rs1; // @[MultiPortFifo.scala 57:20]
  reg [4:0] if4_instr_fifo_buf_0_param_raw_rs2; // @[MultiPortFifo.scala 57:20]
  reg [4:0] if4_instr_fifo_buf_0_param_raw_rd0; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_lui; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_auipc; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_addi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_addiw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_slti; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_sltiu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_xori; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_ori; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_andi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_slli; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_slliw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_srli; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_srliw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_srai; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_sraiw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_add; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_addw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_sub; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_subw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_sll; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_sllw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_slt; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_sltu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_xor; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_srl; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_srlw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_sra; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_sraw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_or; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_and; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_alu_isa_wfi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_bru_isa_jal; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_bru_isa_jalr; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_bru_isa_beq; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_bru_isa_bne; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_bru_isa_blt; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_bru_isa_bge; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_bru_isa_bltu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_bru_isa_bgeu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_lb; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_lh; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_lw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_ld; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_lbu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_lhu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_lwu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_sb; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_sh; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_sw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_sd; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_fence; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_fence_i; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_sfence_vma; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_lr_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_sc_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoswap_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoadd_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoxor_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoand_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoor_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amomin_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amomax_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amominu_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amomaxu_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_lr_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_sc_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoswap_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoadd_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoxor_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoand_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amoor_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amomin_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amomax_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amominu_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_amomaxu_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_flw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_fsw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_fld; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_lsu_isa_fsd; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_csr_isa_rw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_csr_isa_rs; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_csr_isa_rc; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_csr_isa_rwi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_csr_isa_rsi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_csr_isa_rci; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_mul; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_mulh; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_mulhsu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_mulhu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_div; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_divu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_rem; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_remu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_mulw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_divw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_divuw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_remw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_mul_isa_remuw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_ecall; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_ebreak; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_mret; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_uret; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_sret; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_dret; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hfence_vvma; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hfence_gvma; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlv_b; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlv_bu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlv_h; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlv_hu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlvx_hu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlv_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlvx_wu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hsv_b; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hsv_h; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hsv_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlv_wu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hlv_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_hsv_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_is_access_fault; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_privil_isa_is_paging_fault; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmadd_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmsub_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fnmsub_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fnmadd_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fadd_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsub_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmul_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fdiv_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsqrt_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsgnj_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsgnjn_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsgnjx_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmin_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmax_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_w_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmv_x_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_feq_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_flt_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fle_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fclass_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_wu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmv_w_x; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_l_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_l; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_lu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmadd_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmsub_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fnmsub_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fnmadd_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fadd_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsub_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmul_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fdiv_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsqrt_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsgnj_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsgnjn_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fsgnjx_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmin_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmax_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_s; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_feq_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_flt_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fle_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fclass_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_w_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_w; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_wu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_l_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmv_x_d; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_l; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_lu; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fmv_d_x; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcsr_rw; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcsr_rs; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcsr_rc; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcsr_rwi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcsr_rsi; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_fpu_isa_fcsr_rci; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_1_param_is_rvc; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if4_instr_fifo_buf_1_param_pc; // @[MultiPortFifo.scala 57:20]
  reg [63:0] if4_instr_fifo_buf_1_param_imm; // @[MultiPortFifo.scala 57:20]
  reg [4:0] if4_instr_fifo_buf_1_param_raw_rs1; // @[MultiPortFifo.scala 57:20]
  reg [4:0] if4_instr_fifo_buf_1_param_raw_rs2; // @[MultiPortFifo.scala 57:20]
  reg [4:0] if4_instr_fifo_buf_1_param_raw_rd0; // @[MultiPortFifo.scala 57:20]
  reg  if4_instr_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  if4_instr_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  if4_instr_fifo_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  if4_instr_fifo_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] if4_instr_fifo__io_enq_0_ready_T = {{1'd0}, if4_instr_fifo_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  if4_instr_fifo__io_enq_0_ready_T_1 = if4_instr_fifo__io_enq_0_ready_T[0]; // @[MultiPortFifo.scala 64:78]
  wire  if4_instr_fifo__GEN_1 = if4_instr_fifo__io_enq_0_ready_T_1 ? if4_instr_fifo_buf_valid_1 :
    if4_instr_fifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if4_instr_fifo__io_deq_0_valid_T = {{1'd0}, if4_instr_fifo_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  if4_instr_fifo__io_deq_0_valid_T_1 = if4_instr_fifo__io_deq_0_valid_T[0]; // @[MultiPortFifo.scala 65:78]
  wire  if4_instr_fifo__T = if4_instr_fifo_io_enq_0_ready & if4_instr_fifo_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_instr_fifo__GEN_4 = ~if4_instr_fifo__io_enq_0_ready_T_1 | if4_instr_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if4_instr_fifo__GEN_5 = if4_instr_fifo__io_enq_0_ready_T_1 | if4_instr_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if4_instr_fifo__GEN_6 = if4_instr_fifo__T ? if4_instr_fifo__GEN_4 : if4_instr_fifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if4_instr_fifo__GEN_7 = if4_instr_fifo__T ? if4_instr_fifo__GEN_5 : if4_instr_fifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if4_instr_fifo__T_1 = if4_instr_fifo_io_deq_0_ready & if4_instr_fifo_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_instr_fifo__rd_ptr_T_2 = if4_instr_fifo_rd_ptr + if4_instr_fifo__T_1; // @[MultiPortFifo.scala 106:26]
  wire  if4_instr_fifo__wr_ptr_T_2 = if4_instr_fifo_wr_ptr + if4_instr_fifo__T; // @[MultiPortFifo.scala 107:26]
  wire  if4_instr_fifo__T_3 = ~if4_instr_fifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if4_instr_fifo__T_4 = if4_instr_fifo_io_enq_0_valid & if4_instr_fifo__T_3; // @[MultiPortFifo.scala 161:44]
  wire  if4_instr_fifo__T_7 = ~if4_instr_fifo__T_4; // @[MultiPortFifo.scala 161:15]
  wire  if4_instr_fifo__T_9 = ~if4_instr_fifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  if4_instr_fifo__T_10 = ~if4_instr_fifo__T_7; // @[MultiPortFifo.scala 161:13]
  wire  if4_instr_fifo__T_12 = ~if4_instr_fifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if4_instr_fifo__T_13 = if4_instr_fifo_io_deq_0_valid & if4_instr_fifo__T_12; // @[MultiPortFifo.scala 164:44]
  wire  if4_instr_fifo__T_16 = ~if4_instr_fifo__T_13; // @[MultiPortFifo.scala 164:15]
  wire  if4_instr_fifo__T_19 = ~if4_instr_fifo__T_16; // @[MultiPortFifo.scala 164:13]
  wire  if4_bftq_clock;
  wire  if4_bftq_reset;
  wire  if4_bftq_io_enq_0_ready;
  wire  if4_bftq_io_enq_0_valid;
  wire [38:0] if4_bftq_io_enq_0_bits_pc;
  wire  if4_bftq_io_enq_0_bits_bimResp_bim_p;
  wire  if4_bftq_io_enq_0_bits_bimResp_bim_h;
  wire  if4_bftq_io_enq_0_bits_isPredictTaken;
  wire  if4_bftq_io_deq_0_ready;
  wire  if4_bftq_io_deq_0_valid;
  wire [38:0] if4_bftq_io_deq_0_bits_pc;
  wire  if4_bftq_io_deq_0_bits_bimResp_bim_p;
  wire  if4_bftq_io_deq_0_bits_bimResp_bim_h;
  wire  if4_bftq_io_deq_0_bits_isPredictTaken;
  wire  if4_bftq_io_flush;
  reg [38:0] if4_bftq_buf_0_pc; // @[MultiPortFifo.scala 57:20]
  reg  if4_bftq_buf_0_bimResp_bim_p; // @[MultiPortFifo.scala 57:20]
  reg  if4_bftq_buf_0_bimResp_bim_h; // @[MultiPortFifo.scala 57:20]
  reg  if4_bftq_buf_0_isPredictTaken; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if4_bftq_buf_1_pc; // @[MultiPortFifo.scala 57:20]
  reg  if4_bftq_buf_1_bimResp_bim_p; // @[MultiPortFifo.scala 57:20]
  reg  if4_bftq_buf_1_bimResp_bim_h; // @[MultiPortFifo.scala 57:20]
  reg  if4_bftq_buf_1_isPredictTaken; // @[MultiPortFifo.scala 57:20]
  reg  if4_bftq_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  if4_bftq_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  if4_bftq_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  if4_bftq_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] if4_bftq__io_enq_0_ready_T = {{1'd0}, if4_bftq_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  if4_bftq__io_enq_0_ready_T_1 = if4_bftq__io_enq_0_ready_T[0]; // @[MultiPortFifo.scala 64:78]
  wire  if4_bftq__GEN_1 = if4_bftq__io_enq_0_ready_T_1 ? if4_bftq_buf_valid_1 : if4_bftq_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if4_bftq__io_deq_0_valid_T = {{1'd0}, if4_bftq_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  if4_bftq__io_deq_0_valid_T_1 = if4_bftq__io_deq_0_valid_T[0]; // @[MultiPortFifo.scala 65:78]
  wire  if4_bftq__T = if4_bftq_io_enq_0_ready & if4_bftq_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_bftq__GEN_4 = ~if4_bftq__io_enq_0_ready_T_1 | if4_bftq_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if4_bftq__GEN_5 = if4_bftq__io_enq_0_ready_T_1 | if4_bftq_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if4_bftq__GEN_6 = if4_bftq__T ? if4_bftq__GEN_4 : if4_bftq_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if4_bftq__GEN_7 = if4_bftq__T ? if4_bftq__GEN_5 : if4_bftq_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if4_bftq__T_1 = if4_bftq_io_deq_0_ready & if4_bftq_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_bftq__rd_ptr_T_2 = if4_bftq_rd_ptr + if4_bftq__T_1; // @[MultiPortFifo.scala 106:26]
  wire  if4_bftq__wr_ptr_T_2 = if4_bftq_wr_ptr + if4_bftq__T; // @[MultiPortFifo.scala 107:26]
  wire  if4_bftq__T_3 = ~if4_bftq_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if4_bftq__T_4 = if4_bftq_io_enq_0_valid & if4_bftq__T_3; // @[MultiPortFifo.scala 161:44]
  wire  if4_bftq__T_7 = ~if4_bftq__T_4; // @[MultiPortFifo.scala 161:15]
  wire  if4_bftq__T_9 = ~if4_bftq_reset; // @[MultiPortFifo.scala 161:13]
  wire  if4_bftq__T_10 = ~if4_bftq__T_7; // @[MultiPortFifo.scala 161:13]
  wire  if4_bftq__T_12 = ~if4_bftq_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if4_bftq__T_13 = if4_bftq_io_deq_0_valid & if4_bftq__T_12; // @[MultiPortFifo.scala 164:44]
  wire  if4_bftq__T_16 = ~if4_bftq__T_13; // @[MultiPortFifo.scala 164:15]
  wire  if4_bftq__T_19 = ~if4_bftq__T_16; // @[MultiPortFifo.scala 164:13]
  wire  if4_jftq_clock;
  wire  if4_jftq_reset;
  wire  if4_jftq_io_enq_0_ready;
  wire  if4_jftq_io_enq_0_valid;
  wire [38:0] if4_jftq_io_enq_0_bits_pc;
  wire [38:0] if4_jftq_io_enq_0_bits_btbResp_target;
  wire [38:0] if4_jftq_io_enq_0_bits_rasResp_target;
  wire  if4_jftq_io_enq_0_bits_isRas;
  wire  if4_jftq_io_deq_0_ready;
  wire  if4_jftq_io_deq_0_valid;
  wire [38:0] if4_jftq_io_deq_0_bits_pc;
  wire [38:0] if4_jftq_io_deq_0_bits_btbResp_target;
  wire [38:0] if4_jftq_io_deq_0_bits_rasResp_target;
  wire  if4_jftq_io_deq_0_bits_isRas;
  wire  if4_jftq_io_flush;
  reg [38:0] if4_jftq_buf_0_pc; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if4_jftq_buf_0_btbResp_target; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if4_jftq_buf_0_rasResp_target; // @[MultiPortFifo.scala 57:20]
  reg  if4_jftq_buf_0_isRas; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if4_jftq_buf_1_pc; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if4_jftq_buf_1_btbResp_target; // @[MultiPortFifo.scala 57:20]
  reg [38:0] if4_jftq_buf_1_rasResp_target; // @[MultiPortFifo.scala 57:20]
  reg  if4_jftq_buf_1_isRas; // @[MultiPortFifo.scala 57:20]
  reg  if4_jftq_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  if4_jftq_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  if4_jftq_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  if4_jftq_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] if4_jftq__io_enq_0_ready_T = {{1'd0}, if4_jftq_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  if4_jftq__io_enq_0_ready_T_1 = if4_jftq__io_enq_0_ready_T[0]; // @[MultiPortFifo.scala 64:78]
  wire  if4_jftq__GEN_1 = if4_jftq__io_enq_0_ready_T_1 ? if4_jftq_buf_valid_1 : if4_jftq_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] if4_jftq__io_deq_0_valid_T = {{1'd0}, if4_jftq_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  if4_jftq__io_deq_0_valid_T_1 = if4_jftq__io_deq_0_valid_T[0]; // @[MultiPortFifo.scala 65:78]
  wire  if4_jftq__T = if4_jftq_io_enq_0_ready & if4_jftq_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_jftq__GEN_4 = ~if4_jftq__io_enq_0_ready_T_1 | if4_jftq_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if4_jftq__GEN_5 = if4_jftq__io_enq_0_ready_T_1 | if4_jftq_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  if4_jftq__GEN_6 = if4_jftq__T ? if4_jftq__GEN_4 : if4_jftq_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if4_jftq__GEN_7 = if4_jftq__T ? if4_jftq__GEN_5 : if4_jftq_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  if4_jftq__T_1 = if4_jftq_io_deq_0_ready & if4_jftq_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_jftq__rd_ptr_T_2 = if4_jftq_rd_ptr + if4_jftq__T_1; // @[MultiPortFifo.scala 106:26]
  wire  if4_jftq__wr_ptr_T_2 = if4_jftq_wr_ptr + if4_jftq__T; // @[MultiPortFifo.scala 107:26]
  wire  if4_jftq__T_3 = ~if4_jftq_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  if4_jftq__T_4 = if4_jftq_io_enq_0_valid & if4_jftq__T_3; // @[MultiPortFifo.scala 161:44]
  wire  if4_jftq__T_7 = ~if4_jftq__T_4; // @[MultiPortFifo.scala 161:15]
  wire  if4_jftq__T_9 = ~if4_jftq_reset; // @[MultiPortFifo.scala 161:13]
  wire  if4_jftq__T_10 = ~if4_jftq__T_7; // @[MultiPortFifo.scala 161:13]
  wire  if4_jftq__T_12 = ~if4_jftq_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  if4_jftq__T_13 = if4_jftq_io_deq_0_valid & if4_jftq__T_12; // @[MultiPortFifo.scala 164:44]
  wire  if4_jftq__T_16 = ~if4_jftq__T_13; // @[MultiPortFifo.scala 164:15]
  wire  if4_jftq__T_19 = ~if4_jftq__T_16; // @[MultiPortFifo.scala 164:13]
  wire  if4_bRePort_clock;
  wire  if4_bRePort_reset;
  wire  if4_bRePort_io_enq_0_ready;
  wire  if4_bRePort_io_enq_0_valid;
  wire [38:0] if4_bRePort_io_enq_0_bits_pc;
  wire  if4_bRePort_io_enq_0_bits_bimResp_bim_p;
  wire  if4_bRePort_io_enq_0_bits_bimResp_bim_h;
  wire  if4_bRePort_io_enq_0_bits_isPredictTaken;
  wire  if4_bRePort_io_deq_0_ready;
  wire  if4_bRePort_io_deq_0_valid;
  wire [38:0] if4_bRePort_io_deq_0_bits_pc;
  wire  if4_bRePort_io_deq_0_bits_bimResp_bim_p;
  wire  if4_bRePort_io_deq_0_bits_bimResp_bim_h;
  wire  if4_bRePort_io_deq_0_bits_isPredictTaken;
  wire  if4_bRePort__T = if4_bRePort_io_enq_0_ready & if4_bRePort_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_bRePort__T_1 = if4_bRePort_io_deq_0_ready & if4_bRePort_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_bRePort__T_2 = if4_bRePort__T == if4_bRePort__T_1; // @[RePort.scala 32:45]
  wire  if4_bRePort__T_4 = ~if4_bRePort_reset; // @[RePort.scala 32:12]
  wire  if4_bRePort__T_5 = ~if4_bRePort__T_2; // @[RePort.scala 32:12]
  wire  if4_bRePort__is_end_0_T = ~if4_bRePort_io_enq_0_valid; // @[RePort.scala 62:21]
  wire  if4_bRePort__T_6 = ~if4_bRePort__is_end_0_T; // @[RePort.scala 75:11]
  wire  if4_jRePort_clock;
  wire  if4_jRePort_reset;
  wire  if4_jRePort_io_enq_0_ready;
  wire  if4_jRePort_io_enq_0_valid;
  wire [38:0] if4_jRePort_io_enq_0_bits_pc;
  wire [38:0] if4_jRePort_io_enq_0_bits_btbResp_target;
  wire [38:0] if4_jRePort_io_enq_0_bits_rasResp_target;
  wire  if4_jRePort_io_enq_0_bits_isRas;
  wire  if4_jRePort_io_deq_0_ready;
  wire  if4_jRePort_io_deq_0_valid;
  wire [38:0] if4_jRePort_io_deq_0_bits_pc;
  wire [38:0] if4_jRePort_io_deq_0_bits_btbResp_target;
  wire [38:0] if4_jRePort_io_deq_0_bits_rasResp_target;
  wire  if4_jRePort_io_deq_0_bits_isRas;
  wire  if4_jRePort__T = if4_jRePort_io_enq_0_ready & if4_jRePort_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_jRePort__T_1 = if4_jRePort_io_deq_0_ready & if4_jRePort_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  if4_jRePort__T_2 = if4_jRePort__T == if4_jRePort__T_1; // @[RePort.scala 32:45]
  wire  if4_jRePort__T_4 = ~if4_jRePort_reset; // @[RePort.scala 32:12]
  wire  if4_jRePort__T_5 = ~if4_jRePort__T_2; // @[RePort.scala 32:12]
  wire  if4_jRePort__is_end_0_T = ~if4_jRePort_io_enq_0_valid; // @[RePort.scala 62:21]
  wire  if4_jRePort__T_6 = ~if4_jRePort__is_end_0_T; // @[RePort.scala 75:11]
  wire  if4_tageRedirect_mdl_io_enq_0_ready;
  wire [1:0] if4_tageRedirect_mdl_io_deq_0_bits_0_use;
  wire  if4_tageRedirect_mdl_io_deq_0_bits_0_is_hit;
  wire [1:0] if4_tageRedirect_mdl_io_deq_0_bits_1_use;
  wire  if4_tageRedirect_mdl_io_deq_0_bits_1_is_hit;
  wire [1:0] if4_tageRedirect_mdl_io_deq_0_bits_2_use;
  wire  if4_tageRedirect_mdl_io_deq_0_bits_2_is_hit;
  wire [1:0] if4_tageRedirect_mdl_io_deq_0_bits_3_use;
  wire  if4_tageRedirect_mdl_io_deq_0_bits_3_is_hit;
  wire [1:0] if4_tageRedirect_mdl_io_deq_0_bits_4_use;
  wire  if4_tageRedirect_mdl_io_deq_0_bits_4_is_hit;
  wire [1:0] if4_tageRedirect_mdl_io_deq_0_bits_5_use;
  wire  if4_tageRedirect_mdl_io_deq_0_bits_5_is_hit;
  wire  if4_bimRedirect_mdl_io_enq_0_ready;
  wire  if4_bimRedirect_mdl_io_enq_0_valid;
  wire  if4_bimRedirect_mdl_io_enq_0_bits_bim_p;
  wire  if4_bimRedirect_mdl_io_enq_0_bits_bim_h;
  wire  if4_bimRedirect_mdl_io_deq_0_ready;
  wire  if4_bimRedirect_mdl_io_deq_0_valid;
  wire  if4_bimRedirect_mdl_io_deq_0_bits_bim_p;
  wire  if4_bimRedirect_mdl_io_deq_0_bits_bim_h;
  wire  if4_bimRedirect_mdl_io_mapper_0;
  wire  if4_btbRedirect_mdl_io_enq_0_ready;
  wire  if4_btbRedirect_mdl_io_enq_0_valid;
  wire [38:0] if4_btbRedirect_mdl_io_enq_0_bits_target;
  wire  if4_btbRedirect_mdl_io_deq_0_ready;
  wire  if4_btbRedirect_mdl_io_deq_0_valid;
  wire [38:0] if4_btbRedirect_mdl_io_deq_0_bits_target;
  wire  if4_btbRedirect_mdl_io_mapper_0;
  wire [15:0] if4_instr_fifo_io_enq_0_bits_dec16_io_x;
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16_io_pc;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_lui;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_auipc;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addi;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addiw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slti;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sltiu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_xori;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_ori;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_andi;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slli;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slliw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srli;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srliw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srai;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sraiw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_add;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sub;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_subw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sll;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sllw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slt;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sltu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_xor;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srl;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srlw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sra;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sraw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_or;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_and;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_wfi;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_jal;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_jalr;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_beq;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bne;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_blt;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bge;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bltu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bgeu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lb;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lh;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_ld;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lbu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lhu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lwu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sb;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sh;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sd;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fence;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fence_i;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sfence_vma;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lr_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sc_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoswap_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoadd_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoxor_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoand_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoor_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomin_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomax_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amominu_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomaxu_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lr_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sc_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoswap_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoadd_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoxor_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoand_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoor_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomin_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomax_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amominu_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomaxu_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_flw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fsw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fld;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fsd;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rs;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rc;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rwi;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rsi;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rci;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mul;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulh;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulhsu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulhu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_div;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_rem;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divuw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remuw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_ecall;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_ebreak;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_mret;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_uret;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_sret;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_dret;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hfence_vvma;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hfence_gvma;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_b;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_bu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_h;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_hu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlvx_hu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlvx_wu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_b;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_h;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_wu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_is_access_fault;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_is_paging_fault;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmadd_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmsub_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmsub_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmadd_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fadd_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsub_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmul_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fdiv_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsqrt_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnj_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjn_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjx_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmin_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmax_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_w_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_wu_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_x_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_feq_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_flt_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fle_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fclass_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_wu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_w_x;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_l_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_lu_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_l;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_lu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmadd_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmsub_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmsub_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmadd_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fadd_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsub_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmul_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fdiv_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsqrt_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnj_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjn_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjx_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmin_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmax_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_feq_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_flt_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fle_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fclass_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_w_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_wu_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_wu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_l_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_lu_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_x_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_l;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_lu;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_d_x;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rw;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rs;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rc;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rwi;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rsi;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rci;
  wire  if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_is_rvc;
  wire [38:0] if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_pc;
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_imm;
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rs1;
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rs2;
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rd0;
  wire [15:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T = if4_instr_fifo_io_enq_0_bits_dec16_io_x & 16'he003
    ; // @[Decoder.scala 63:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_1 = 16'h0 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 63:24]
  wire [7:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_2 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[12:5]; // @[Decoder.scala 63:78]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_3 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_2 != 8'h0; // @[Decoder.scala 63:85]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_4 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_1 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_3; // @[Decoder.scala 63:74]
  wire [2:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_5 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[4:2]; // @[Decoder.scala 111:36]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 = {2'h1,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_5}; // @[Cat.scala 33:92]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_10 = 16'h4000 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 64:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_14 = 16'h6000 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 65:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_18 = 16'hc000 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 66:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_20 = 16'he000 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 67:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_22 = 16'h1 == if4_instr_fifo_io_enq_0_bits_dec16_io_x; // @[Decoder.scala 68:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_24 = 16'h1 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 69:24]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[11:7]
    ; // @[Decoder.scala 69:78]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 != 5'h0; // @[Decoder.scala 69:85]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_27 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_24 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 69:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_30 = 16'h2001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 70:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_33 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_30 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 70:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_36 = 16'h4001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 71:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_39 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_36 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 71:74]
  wire [15:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_41 = if4_instr_fifo_io_enq_0_bits_dec16_io_x & 16'hef83
    ; // @[Decoder.scala 72:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_42 = 16'h6101 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_41; // @[Decoder.scala 72:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_44 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 == 5'h2; // @[Decoder.scala 72:85]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_45 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_42 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_44; // @[Decoder.scala 72:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[12]; // @[Decoder.scala 72:102]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[6:2]; // @[Decoder.scala 72:109]
  wire [5:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_48 = {
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47}; // @[Cat.scala 33:92]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_49 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_48 != 6'h0; // @[Decoder.scala 72:116]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_50 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_45 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_49; // @[Decoder.scala 72:94]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_52 = 16'h6001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 73:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_54 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 != 5'h2; // @[Decoder.scala 73:85]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_55 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_52 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_54; // @[Decoder.scala 73:74]
  wire [10:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_56 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[12:2
    ]; // @[Decoder.scala 73:98]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_57 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_56 != 11'h0; // @[Decoder.scala 73:105]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_58 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_55 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_57; // @[Decoder.scala 73:94]
  wire [15:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_60 = if4_instr_fifo_io_enq_0_bits_dec16_io_x & 16'hec03
    ; // @[Decoder.scala 74:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_61 = 16'h8001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_60; // @[Decoder.scala 74:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_66 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_61 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_49; // @[Decoder.scala 74:74]
  wire [2:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_67 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[9:7]; // @[Decoder.scala 124:36]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 = {2'h1,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_67}; // @[Cat.scala 33:92]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_70 = 16'h8401 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_60; // @[Decoder.scala 75:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_75 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_70 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_49; // @[Decoder.scala 75:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_79 = 16'h8801 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_60; // @[Decoder.scala 77:24]
  wire [15:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82 = if4_instr_fifo_io_enq_0_bits_dec16_io_x & 16'hfc63
    ; // @[Decoder.scala 78:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_83 = 16'h8c01 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 78:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_87 = 16'h8c21 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 79:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_91 = 16'h8c41 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 80:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_95 = 16'h8c61 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 81:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_99 = 16'h9c01 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 82:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_103 = 16'h9c21 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 83:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_107 = 16'ha001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 84:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_109 = 16'hc001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 85:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_111 = 16'he001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 86:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_113 = 16'h2 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 87:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_116 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_113 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 87:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_120 = 16'h4002 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 89:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_123 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_120 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 89:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_126 = 16'h6002 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 90:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_129 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_126 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 90:74]
  wire [15:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_131 = if4_instr_fifo_io_enq_0_bits_dec16_io_x & 16'hf07f
    ; // @[Decoder.scala 91:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_132 = 16'h8002 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_131; // @[Decoder.scala 91:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_135 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_132 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 91:74]
  wire [15:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_136 = if4_instr_fifo_io_enq_0_bits_dec16_io_x & 16'hf003
    ; // @[Decoder.scala 92:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_137 = 16'h8002 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_136; // @[Decoder.scala 92:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_140 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_137 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 92:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_142 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47 != 5'h0; // @[Decoder.scala 92:104]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_143 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_140 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_142; // @[Decoder.scala 92:94]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_148 = 16'h9002 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_131; // @[Decoder.scala 94:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_151 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_148 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 94:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_153 = 16'h9002 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_136; // @[Decoder.scala 95:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_156 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_153 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 95:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_159 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_156 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_142; // @[Decoder.scala 95:94]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_162 = 16'hc002 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 97:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_164 = 16'he002 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 98:24]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_165 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_4 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_167 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_10 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_168 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_14 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_173 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_27 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_174 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_33 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_175 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_39 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_176 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_50 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_177 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_58 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_178 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_66 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_179 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_75 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_180 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_79 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_181 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_83 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_182 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_87 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_183 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_91 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_184 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_95 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_185 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_99 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_186 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_103 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_190 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_116 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_192 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_123 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_193 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_129 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_195 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_143 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_198 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_159 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_203 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_165 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_167; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_204 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_203 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_168; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_209 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_204 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_173; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_210 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_209 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_174; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_211 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_210 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_175; // @[Mux.scala 27:73]
  wire [4:0] _GEN_199 = {{3'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_176}; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_212 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_211 | _GEN_199; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_213 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_212 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_177; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_214 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_213 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_178; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_215 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_214 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_179; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_216 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_215 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_180; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_217 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_216 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_181; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_218 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_217 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_182; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_219 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_218 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_183; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_220 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_219 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_184; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_221 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_220 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_185; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_222 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_221 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_186; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_226 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_222 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_190; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_228 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_226 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_192; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_229 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_228 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_193; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_231 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_229 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_195; // @[Mux.scala 27:73]
  wire [4:0] _GEN_200 = {{4'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_151}; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_233 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_231 | _GEN_200; // @[Mux.scala 27:73]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_169 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_4 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_171 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_10 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_172 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_14 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_174 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_18 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_175 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_20 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_192 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_109 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_193 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_111 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_68 : 5'h0; // @[Mux.scala 27:73]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_196 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_123 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_197 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_129 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_198 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_135 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_201 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_151 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_25 : 5'h0; // @[Mux.scala 27:73]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_204 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_162 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_205 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_164 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_206 = {{3'd0},
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_169}; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_207 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_206 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_171; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_208 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_207 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_172; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_210 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_208 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_174; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_211 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_210 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_175; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_213 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_211 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_173; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_214 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_213 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_174; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_216 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_214 | _GEN_199; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_218 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_216 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_178; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_219 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_218 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_179; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_220 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_219 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_180; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_221 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_220 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_181; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_222 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_221 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_182; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_223 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_222 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_183; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_224 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_223 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_184; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_225 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_224 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_185; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_226 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_225 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_186; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_228 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_226 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_192; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_229 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_228 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_193; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_230 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_229 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_190; // @[Mux.scala 27:73]
  wire [4:0] _GEN_202 = {{3'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_196}; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_232 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_230 | _GEN_202; // @[Mux.scala 27:73]
  wire [4:0] _GEN_203 = {{3'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_197}; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_233 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_232 | _GEN_203; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_234 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_233 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_198; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_237 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_234 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_201; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_238 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_237 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_198; // @[Mux.scala 27:73]
  wire [4:0] _GEN_204 = {{3'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_204}; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_240 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_238 | _GEN_204; // @[Mux.scala 27:73]
  wire [4:0] _GEN_205 = {{3'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_205}; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_157 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_18 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_158 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_20 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_168 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_83 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_169 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_87 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_170 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_91 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_171 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_95 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_172 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_99 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_173 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_103 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_6 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_182 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_143 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_185 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_159 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_187 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_162 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_188 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_164 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_194 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_157 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_158; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_204 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_194 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_168; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_205 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_204 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_169; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_206 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_205 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_170; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_207 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_206 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_171; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_208 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_207 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_172; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_209 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_208 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_173; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_218 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_209 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_182; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_221 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_218 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_185; // @[Mux.scala 27:73]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_223 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_221 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_187; // @[Mux.scala 27:73]
  wire [3:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_5 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[10:7]; // @[Decoder.scala 48:37]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_6 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[12:11]; // @[Decoder.scala 48:46]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_7 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[5]; // @[Decoder.scala 48:56]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_8 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[6]; // @[Decoder.scala 48:62]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_9 = {54'h0,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_5,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_6,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_7,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_8,2'h0}; // @[Cat.scala 33:92]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_10 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[6:5]; // @[Decoder.scala 50:31]
  wire [2:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_11 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[12:10]; // @[Decoder.scala 50:39]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_12 = {56'h0,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_10,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_11,3'h0
    }; // @[Cat.scala 33:92]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_18 = {57'h0,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_7,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_11,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_8,2'h0}; // @[Cat.scala 33:92]
  wire [58:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_45 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46 ? 59'h7ffffffffffffff : 59'h0; // @[Bitwise.scala 77:12]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_47 = {
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_45,if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47}
    ; // @[Cat.scala 33:92]
  wire [54:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_80 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46 ? 55'h7fffffffffffff : 55'h0; // @[Bitwise.scala 77:12]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_81 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[4:3]; // @[Decoder.scala 56:43]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_83 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[2]; // @[Decoder.scala 56:57]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_85 = {
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_80,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_81,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_7,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_83,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_8,4'h0}; // @[Cat.scala 33:92]
  wire [46:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_96 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46 ? 47'h7fffffffffff : 47'h0; // @[Bitwise.scala 77:12]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_98 = {
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_96,if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_47,12'h0
    }; // @[Cat.scala 33:92]
  wire [52:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_110 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46 ? 53'h1fffffffffffff : 53'h0; // @[Bitwise.scala 77:12]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_111 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[8]; // @[Decoder.scala 58:36]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_112 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[10:9]; // @[Decoder.scala 58:42]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_114 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[7]; // @[Decoder.scala 58:57]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_116 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[11]; // @[Decoder.scala 58:69]
  wire [2:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_117 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[5:3]; // @[Decoder.scala 58:76]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_118 = {
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_110,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_111,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_112,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_8,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_114,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_83,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_116,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_117,1'h0
    }; // @[Cat.scala 33:92]
  wire [55:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_123 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46 ? 56'hffffffffffffff : 56'h0; // @[Bitwise.scala 77:12]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_126 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[11:10]; // @[Decoder.scala 59:50]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_128 = {
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_123,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_10,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_83,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_126,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_81,1'h0}; // @[Cat.scala 33:92]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_142 = {55'h0,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_5,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_10,3'h0
    }; // @[Cat.scala 33:92]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_148 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[3:2]; // @[Decoder.scala 51:33]
  wire [2:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_150 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[6:4]; // @[Decoder.scala 51:48]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_151 = {56'h0,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_148,if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_46
    ,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_150,2'h0}; // @[Cat.scala 33:92]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_163 = {55'h0,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_67,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_11,3'h0
    }; // @[Cat.scala 33:92]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_166 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[8:7]; // @[Decoder.scala 53:33]
  wire [3:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_167 = if4_instr_fifo_io_enq_0_bits_dec16_io_x[12:9]; // @[Decoder.scala 53:41]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_168 = {56'h0,
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_166,if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_167,2'h0
    }; // @[Cat.scala 33:92]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_202 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_4 ? if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_9
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_204 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_10 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_18 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_205 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_14 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_12 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_207 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_18 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_18 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_208 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_20 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_12 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_209 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_27 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_47 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_210 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_33 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_47 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_211 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_39 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_47 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_212 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_50 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_85 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_213 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_58 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_98 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_214 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_79 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_47 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_215 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_107 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_118 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_216 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_109 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_128 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_217 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_111 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_128 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_219 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_123 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_151 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_220 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_129 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_142 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_222 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_162 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_168 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_223 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_164 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_163 : 64'h0; // @[Mux.scala 27:73]
  wire [5:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_224 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_116 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_48 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_225 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_66 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_48 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_226 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_75 ?
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_48 : 6'h0; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_228 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_202 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_204; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_229 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_228 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_205; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_231 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_229 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_207; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_232 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_231 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_208; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_233 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_232 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_209; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_234 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_233 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_210; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_235 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_234 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_211; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_236 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_235 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_212; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_237 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_236 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_213; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_238 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_237 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_214; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_239 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_238 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_215; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_240 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_239 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_216; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_241 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_240 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_217; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_243 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_241 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_219; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_244 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_243 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_220; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_246 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_244 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_222; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_247 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_246 | if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_223; // @[Mux.scala 27:73]
  wire [63:0] _GEN_206 = {{58'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_224}; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_248 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_247 | _GEN_206; // @[Mux.scala 27:73]
  wire [63:0] _GEN_207 = {{58'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_225}; // @[Mux.scala 27:73]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_249 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_248 | _GEN_207; // @[Mux.scala 27:73]
  wire [63:0] _GEN_208 = {{58'd0}, if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_226}; // @[Mux.scala 27:73]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_alu_isa_addi_T_7 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_4 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_22; // @[Decoder.scala 279:42]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_alu_isa_addi_T_13 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_alu_isa_addi_T_7 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_27; // @[Decoder.scala 279:50]
  wire  if4_instr_fifo_io_enq_0_bits_dec16__info_alu_isa_addi_T_19 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_alu_isa_addi_T_13 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_39; // @[Decoder.scala 279:59]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32_io_x;
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32_io_pc;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_lui;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_auipc;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addi;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addiw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slti;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sltiu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_xori;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_ori;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_andi;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slli;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slliw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srli;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srliw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srai;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sraiw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_add;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sub;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_subw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sll;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sllw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slt;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sltu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_xor;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srl;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srlw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sra;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sraw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_or;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_and;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_wfi;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_jal;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_jalr;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_beq;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bne;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_blt;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bge;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bltu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bgeu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lb;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lh;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_ld;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lbu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lhu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lwu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sb;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sh;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sd;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fence;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fence_i;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sfence_vma;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lr_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sc_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoswap_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoadd_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoxor_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoand_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoor_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomin_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomax_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amominu_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomaxu_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lr_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sc_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoswap_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoadd_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoxor_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoand_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoor_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomin_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomax_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amominu_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomaxu_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_flw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fsw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fld;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fsd;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rs;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rc;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rwi;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rsi;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rci;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mul;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulh;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulhsu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulhu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_div;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_rem;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divuw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remuw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_ecall;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_ebreak;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_mret;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_uret;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_sret;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_dret;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hfence_vvma;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hfence_gvma;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_b;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_bu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_h;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_hu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlvx_hu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlvx_wu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_b;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_h;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_wu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_is_access_fault;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_is_paging_fault;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmadd_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmsub_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmsub_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmadd_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fadd_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsub_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmul_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fdiv_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsqrt_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnj_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjn_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjx_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmin_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmax_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_w_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_wu_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_x_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_feq_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_flt_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fle_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fclass_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_wu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_w_x;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_l_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_lu_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_l;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_lu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmadd_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmsub_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmsub_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmadd_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fadd_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsub_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmul_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fdiv_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsqrt_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnj_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjn_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjx_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmin_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmax_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_s;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_feq_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_flt_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fle_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fclass_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_w_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_wu_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_w;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_wu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_l_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_lu_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_x_d;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_l;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_lu;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_d_x;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rw;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rs;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rc;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rwi;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rsi;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rci;
  wire  if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_is_rvc;
  wire [38:0] if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_pc;
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_imm;
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rs1;
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rs2;
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rd0;
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x & 32'h707f
    ; // @[Decoder.scala 725:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T_1 = 32'h67 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 725:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lb_T_1 = 32'h3 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 733:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T = if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T_1
     | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lb_T_1; // @[Decoder.scala 514:38]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lh_T_1 = 32'h1003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 734:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_1 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lh_T_1; // @[Decoder.scala 514:56]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lw_T_1 = 32'h2003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 735:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_2 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_1
     | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lw_T_1; // @[Decoder.scala 514:74]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lbu_T_1 = 32'h4003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 737:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_3 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_2
     | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lbu_T_1; // @[Decoder.scala 514:91]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lhu_T_1 = 32'h5003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 738:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_4 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_3
     | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lhu_T_1; // @[Decoder.scala 514:110]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lwu_T_1 = 32'h6003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 739:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_5 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_4
     | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lwu_T_1; // @[Decoder.scala 514:129]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_ld_T_1 = 32'h3003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 736:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_6 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_5
     | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_ld_T_1; // @[Decoder.scala 514:148]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_addi_T_1 = 32'h13 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 694:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_7 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_6
     | if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_addi_T_1; // @[Decoder.scala 514:166]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_addiw_T_1 = 32'h1b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 695:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_8 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_7
     | if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_addiw_T_1; // @[Decoder.scala 514:186]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slti_T_1 = 32'h2013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 696:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_9 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_8
     | if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slti_T_1; // @[Decoder.scala 514:207]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_sltiu_T_1 = 32'h3013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 697:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_10 = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_9
     | if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_sltiu_T_1; // @[Decoder.scala 514:227]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_xori_T_1 = 32'h4013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 698:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_11 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_10 | if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_xori_T_1; // @[Decoder.scala 514:248]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_ori_T_1 = 32'h6013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 699:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_12 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_11 | if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_ori_T_1; // @[Decoder.scala 514:268]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_andi_T_1 = 32'h7013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 700:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_13 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_12 | if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_andi_T_1; // @[Decoder.scala 514:287]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_fence_T_1 = 32'hf ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 744:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_14 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_13 | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_fence_T_1
    ; // @[Decoder.scala 514:307]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_fence_i_T_1 = 32'h100f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 745:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_15 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_14 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_fence_i_T_1; // @[Decoder.scala 514:328]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_1 = 32'h1073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 748:37]
  wire [11:0] if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_2 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[31:20]; // @[Decoder.scala 748:92]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_3 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_2 != 12'h1; // @[Decoder.scala 748:100]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_5 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_2 != 12'h2; // @[Decoder.scala 748:119]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_6 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_3 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_5; // @[Decoder.scala 748:108]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_8 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_2 != 12'h3; // @[Decoder.scala 748:138]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_6 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_8; // @[Decoder.scala 748:127]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_10 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 748:87]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_16 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_15 | if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_10; // @[Decoder.scala 514:351]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rs_T_1 = 32'h2073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 749:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rs_T_10 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rs_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 749:87]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_17 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_16 | if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rs_T_10; // @[Decoder.scala 514:369]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rc_T_1 = 32'h3073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 750:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rc_T_10 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rc_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 750:87]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_18 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_17 | if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rc_T_10; // @[Decoder.scala 514:387]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rwi_T_1 = 32'h5073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 751:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rwi_T_10 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rwi_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 751:87]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_19 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_18 | if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rwi_T_10; // @[Decoder.scala 514:405]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rsi_T_1 = 32'h6073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 752:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rsi_T_10 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rsi_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 752:87]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_20 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_19 | if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rsi_T_10; // @[Decoder.scala 514:424]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rci_T_1 = 32'h7073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 753:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rci_T_10 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rci_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 753:87]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_21 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_20 | if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rci_T_10; // @[Decoder.scala 514:443]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_30 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[31]; // @[Decoder.scala 504:36]
  wire [51:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_32 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_30 ? 52'hfffffffffffff : 52'h0; // @[Bitwise.scala 77:12]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_34 = {
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_32,if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_2}; // @[Cat.scala 33:92]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sb_T_1 = 32'h23 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 740:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sh_T_1 = 32'h1023 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 741:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_35 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sb_T_1 | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sh_T_1; // @[Decoder.scala 515:36]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sw_T_1 = 32'h2023 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 742:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_36 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_35 | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sw_T_1; // @[Decoder.scala 515:54]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sd_T_1 = 32'h3023 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 743:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_37 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_36 | if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sd_T_1; // @[Decoder.scala 515:72]
  wire [6:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_43 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[31:25]; // @[Decoder.scala 505:44]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_44 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[11:7]; // @[Decoder.scala 505:54]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_45 = {
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_32,if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_43,
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_44}; // @[Cat.scala 33:92]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_beq_T_1 = 32'h63 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 726:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bne_T_1 = 32'h1063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 727:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_46 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_beq_T_1 | if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bne_T_1; // @[Decoder.scala 516:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_blt_T_1 = 32'h4063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 728:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_47 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_46 | if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_blt_T_1; // @[Decoder.scala 516:56]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bge_T_1 = 32'h5063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 729:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_48 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_47 | if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bge_T_1; // @[Decoder.scala 516:75]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bltu_T_1 = 32'h6063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 730:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_49 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_48 | if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bltu_T_1; // @[Decoder.scala 516:94]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bgeu_T_1 = 32'h7063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 731:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_50 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_49 | if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bgeu_T_1; // @[Decoder.scala 516:114]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_54 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[7]; // @[Decoder.scala 506:44]
  wire [5:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_55 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[30:25]; // @[Decoder.scala 506:50]
  wire [3:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_56 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[11:8]; // @[Decoder.scala 506:60]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_57 = {
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_32,if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_54,
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_55,if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_56,1'h0
    }; // @[Cat.scala 33:92]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x & 32'h7f; // @[Decoder.scala 692:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T_1 = 32'h37 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T; // @[Decoder.scala 692:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_auipc_T_1 = 32'h17 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T; // @[Decoder.scala 693:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_58 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T_1 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_auipc_T_1; // @[Decoder.scala 517:37]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_61 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [19:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_62 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[31:12]; // @[Decoder.scala 507:44]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_63 = {
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_61,if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_62,12'h0
    }; // @[Cat.scala 33:92]
  wire [43:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_66 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_30 ? 44'hfffffffffff : 44'h0; // @[Bitwise.scala 77:12]
  wire [7:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_67 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[19:12]; // @[Decoder.scala 508:44]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_68 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[20]; // @[Decoder.scala 508:54]
  wire [9:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_69 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[30:21]; // @[Decoder.scala 508:61]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_70 = {
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_66,if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_67,
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_68,if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_69,1'h0
    }; // @[Cat.scala 33:92]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x & 32'hf800707f
    ; // @[Decoder.scala 824:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T_1 = 32'h1800302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 824:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_w_T_1 = 32'h1800202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 813:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_71 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T_1 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_w_T_1; // @[riscv_isa.scala 140:20]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_d_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x & 32'hf9f0707f
    ; // @[Decoder.scala 823:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_d_T_1 = 32'h1000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_d_T; // @[Decoder.scala 823:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_w_T_1 = 32'h1000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_d_T; // @[Decoder.scala 812:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_72 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_d_T_1 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_w_T_1; // @[riscv_isa.scala 141:20]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_73 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_71 | if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_72; // @[riscv_isa.scala 146:23]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoswap_w_T_1 = 32'h800202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 814:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoadd_w_T_1 = 32'h202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 815:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_74 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoswap_w_T_1 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoadd_w_T_1; // @[riscv_isa.scala 148:15]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoxor_w_T_1 = 32'h2000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 816:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_75 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_74 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoxor_w_T_1; // @[riscv_isa.scala 148:26]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoand_w_T_1 = 32'h6000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 817:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_76 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_75 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoand_w_T_1; // @[riscv_isa.scala 148:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoor_w_T_1 = 32'h4000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 818:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_77 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_76 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoor_w_T_1; // @[riscv_isa.scala 148:48]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomin_w_T_1 = 32'h8000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 819:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_78 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_77 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomin_w_T_1; // @[riscv_isa.scala 148:58]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomax_w_T_1 = 32'ha000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 820:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_79 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_78 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomax_w_T_1; // @[riscv_isa.scala 148:69]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amominu_w_T_1 = 32'hc000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 821:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_80 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_79 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amominu_w_T_1; // @[riscv_isa.scala 148:80]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomaxu_w_T_1 = 32'he000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 822:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_81 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_80 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomaxu_w_T_1; // @[riscv_isa.scala 148:92]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoswap_d_T_1 = 32'h800302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 825:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_82 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_81 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoswap_d_T_1; // @[riscv_isa.scala 148:104]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoadd_d_T_1 = 32'h302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 826:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_83 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_82 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoadd_d_T_1; // @[riscv_isa.scala 148:116]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoxor_d_T_1 = 32'h2000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 827:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_84 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_83 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoxor_d_T_1; // @[riscv_isa.scala 148:127]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoand_d_T_1 = 32'h6000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 828:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_85 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_84 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoand_d_T_1; // @[riscv_isa.scala 148:138]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoor_d_T_1 = 32'h4000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 829:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_86 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_85 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amoor_d_T_1; // @[riscv_isa.scala 148:149]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomin_d_T_1 = 32'h8000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 830:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_87 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_86 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomin_d_T_1; // @[riscv_isa.scala 148:159]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomax_d_T_1 = 32'ha000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 831:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_88 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_87 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomax_d_T_1; // @[riscv_isa.scala 148:170]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amominu_d_T_1 = 32'hc000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 832:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_89 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_88 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amominu_d_T_1; // @[riscv_isa.scala 148:181]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomaxu_d_T_1 = 32'he000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 833:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_90 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_89 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_amomaxu_d_T_1; // @[riscv_isa.scala 148:193]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_92 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_90 | if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_71; // @[riscv_isa.scala 148:205]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_93 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_73 | if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_92; // @[Decoder.scala 519:41]
  wire [1:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_95 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[26:25]; // @[Decoder.scala 509:42]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_96 = {62'h0,
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_95}; // @[Cat.scala 33:92]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x & 32'hfc00707f
    ; // @[Decoder.scala 701:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T_1 = 32'h1013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T; // @[Decoder.scala 701:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srli_T_1 = 32'h5013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T; // @[Decoder.scala 703:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_170 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T_1 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srli_T_1; // @[Decoder.scala 521:38]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srai_T_1 = 32'h40005013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T; // @[Decoder.scala 705:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_171 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_170 | if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srai_T_1
    ; // @[Decoder.scala 521:58]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x & 32'hfe00707f
    ; // @[Decoder.scala 702:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T_1 = 32'h101b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 702:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_172 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_171 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T_1; // @[Decoder.scala 521:78]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srliw_T_1 = 32'h501b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 704:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_173 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_172 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srliw_T_1; // @[Decoder.scala 521:99]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_sraiw_T_1 = 32'h4000501b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 706:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_174 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_173 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_sraiw_T_1; // @[Decoder.scala 521:120]
  wire [5:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_176 = if4_instr_fifo_io_enq_0_bits_dec32_io_x[25:20]; // @[Decoder.scala 511:42]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_177 = {58'h0,
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_176}; // @[Cat.scala 33:92]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_178 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_174 ? if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_177
     : 64'h0; // @[Mux.scala 101:16]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_180 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_93 ? if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_96 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_178; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jal_T_1 = 32'h6f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T; // @[Decoder.scala 724:37]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_181 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jal_T_1 ? if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_70
     : if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_180; // @[Mux.scala 101:16]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_182 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_58 ? if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_63 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_181; // @[Mux.scala 101:16]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_183 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_50 ? if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_57 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_182; // @[Mux.scala 101:16]
  wire [63:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_184 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_37 ? if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_45 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_183; // @[Mux.scala 101:16]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x & 32'hfe007fff
    ; // @[Decoder.scala 810:40]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T_1 = 32'h6e004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 810:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_1 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_44; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_w_T_1 = 32'h6a004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 807:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_2 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_w_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_1; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_h_T_1 = 32'h66004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 806:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_3 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_h_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_2; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_b_T_1 = 32'h62004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 805:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_4 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_b_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_3; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hfence_gvma_T_1 = 32'h62000073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 796:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_5 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hfence_gvma_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_4; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hfence_vvma_T_1 = 32'h22000073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 795:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_6 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hfence_vvma_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_5; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_dret_T_1 = 32'h7b200073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 791:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_7 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_dret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_6; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_sret_T_1 = 32'h10200073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 790:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_8 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_sret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_7; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_uret_T_1 = 32'h200073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 789:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_9 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_uret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_8; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_mret_T_1 = 32'h30200073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 788:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_10 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_mret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_9; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_ebreak_T_1 = 32'h100073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 787:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_11 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_ebreak_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_10; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_ecall_T_1 = 32'h73 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 786:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_12 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_ecall_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_11; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_15 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sd_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_12; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_16 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sw_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_15; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_17 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sh_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_16; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_18 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sb_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_17; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_19 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bgeu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_18; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_20 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bltu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_19; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_21 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bge_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_20; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_22 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_blt_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_21; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_23 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_bne_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_22; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_24 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_beq_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_23; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_wfi_T_1 = 32'h10500073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 722:37]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x[19:15]; // @[Decoder.scala 575:37]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_1 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_dret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_2 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_mret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_1; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_3 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_sret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_2; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_4 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_uret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_3; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_5 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_ebreak_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_4; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_6 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_ecall_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_5; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_7 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jal_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_6; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_8 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_wfi_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_7; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_9 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_auipc_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_8; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x[24:20]; // @[Decoder.scala 589:37]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_1 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_10 | if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rs_T_10; // @[riscv_isa.scala 179:19]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_2 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_1 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rc_T_10; // @[riscv_isa.scala 179:24]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_3 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_2 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rwi_T_10; // @[riscv_isa.scala 179:29]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_4 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_3 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rsi_T_10; // @[riscv_isa.scala 179:35]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_5 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_4 |
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rci_T_10; // @[riscv_isa.scala 179:41]
  wire [31:0] if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T = if4_instr_fifo_io_enq_0_bits_dec32_io_x & 32'hfff0707f
    ; // @[Decoder.scala 809:40]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T_1 = 32'h6c004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 809:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_6 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_wu_T_1 = 32'h68104073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 808:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_7 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_wu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_6; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlvx_wu_T_1 = 32'h68304073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 804:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_8 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlvx_wu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_7; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_w_T_1 = 32'h68004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 803:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_9 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_w_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_8; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlvx_hu_T_1 = 32'h64304073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 802:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_10 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlvx_hu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_9; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_hu_T_1 = 32'h64104073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 801:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_11 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_hu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_10; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_h_T_1 = 32'h64004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 800:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_12 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_h_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_11; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_bu_T_1 = 32'h60104073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 799:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_13 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_bu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_12; // @[Mux.scala 101:16]
  wire  if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_b_T_1 = 32'h60004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 798:40]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_14 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_b_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_13; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_47 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_5 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_14; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_48 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_dret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_47; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_49 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_mret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_48; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_50 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_sret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_49; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_51 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_uret_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_50; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_52 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_ebreak_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_51; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_53 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_ecall_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_52; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_55 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_d_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_53; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_56 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_w_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_55; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_57 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_fence_i_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_56; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_58 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_fence_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_57; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_59 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_ld_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_58; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_60 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lwu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_59; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_61 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lhu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_60; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_62 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lbu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_61; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_63 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lw_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_62; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_64 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lh_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_63; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_65 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lb_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_64; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_66 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_65; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_67 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jal_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_66; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_68 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_wfi_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_67; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_69 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_sraiw_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_68; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_70 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srliw_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_69; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_71 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_70; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_72 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_addiw_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_71; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_73 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srai_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_72; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_74 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srli_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_73; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_75 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_74; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_76 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srai_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_75; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_77 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_srli_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_76; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_78 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_77; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_79 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_andi_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_78; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_80 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_ori_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_79; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_81 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_xori_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_80; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_82 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_sltiu_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_81; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_83 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slti_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_82; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_84 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_addi_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_83; // @[Mux.scala 101:16]
  wire [4:0] if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_85 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_auipc_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_84; // @[Mux.scala 101:16]
  wire [15:0] if4__preDecodeAgn_T = if4_io_if4_req_0_bits_instr[15:0]; // @[IF4.scala 58:85]
  wire [15:0] if4__preDecodeAgn_info16_is_jal_T = if4__preDecodeAgn_T & 16'he003; // @[IF3.scala 344:34]
  wire  if4__preDecodeAgn_info16_is_jal_T_1 = 16'ha001 == if4__preDecodeAgn_info16_is_jal_T; // @[IF3.scala 344:34]
  wire [15:0] if4__preDecodeAgn_info16_is_jalr_T = if4__preDecodeAgn_T & 16'he07f; // @[IF3.scala 345:34]
  wire  if4__preDecodeAgn_info16_is_jalr_T_1 = 16'h8002 == if4__preDecodeAgn_info16_is_jalr_T; // @[IF3.scala 345:34]
  wire [4:0] if4__preDecodeAgn_info16_is_jalr_T_2 = if4__preDecodeAgn_T[11:7]; // @[IF3.scala 345:75]
  wire  if4__preDecodeAgn_info16_is_jalr_T_3 = if4__preDecodeAgn_info16_is_jalr_T_2 != 5'h0; // @[IF3.scala 345:82]
  wire  if4__preDecodeAgn_info16_is_jalr_T_4 = if4__preDecodeAgn_info16_is_jalr_T_1 &
    if4__preDecodeAgn_info16_is_jalr_T_3; // @[IF3.scala 345:66]
  wire [15:0] if4__preDecodeAgn_info16_is_branch_T = if4__preDecodeAgn_T & 16'hc003; // @[IF3.scala 346:34]
  wire  if4__preDecodeAgn_info16_is_branch_T_1 = 16'hc001 == if4__preDecodeAgn_info16_is_branch_T; // @[IF3.scala 346:34]
  wire [15:0] if4__preDecodeAgn_info16_is_call_T = if4__preDecodeAgn_T & 16'hf07f; // @[IF3.scala 347:34]
  wire  if4__preDecodeAgn_info16_is_call_T_1 = 16'h9002 == if4__preDecodeAgn_info16_is_call_T; // @[IF3.scala 347:34]
  wire  if4__preDecodeAgn_info16_is_call_T_4 = if4__preDecodeAgn_info16_is_call_T_1 &
    if4__preDecodeAgn_info16_is_jalr_T_3; // @[IF3.scala 347:66]
  wire [15:0] if4__preDecodeAgn_info16_is_return_T = if4__preDecodeAgn_T & 16'hfdff; // @[IF3.scala 348:34]
  wire  if4__preDecodeAgn_info16_is_return_T_1 = 16'h8082 == if4__preDecodeAgn_info16_is_return_T; // @[IF3.scala 348:34]
  wire  if4__preDecodeAgn_info16_imm_T = if4__preDecodeAgn_T[12]; // @[IF3.scala 353:50]
  wire [51:0] if4__preDecodeAgn_info16_imm_T_2 = if4__preDecodeAgn_info16_imm_T ? 52'hfffffffffffff : 52'h0; // @[Bitwise.scala 77:12]
  wire  if4__preDecodeAgn_info16_imm_T_4 = if4__preDecodeAgn_T[8]; // @[IF3.scala 353:77]
  wire [1:0] if4__preDecodeAgn_info16_imm_T_5 = if4__preDecodeAgn_T[10:9]; // @[IF3.scala 353:89]
  wire  if4__preDecodeAgn_info16_imm_T_6 = if4__preDecodeAgn_T[6]; // @[IF3.scala 353:104]
  wire  if4__preDecodeAgn_info16_imm_T_7 = if4__preDecodeAgn_T[7]; // @[IF3.scala 353:116]
  wire  if4__preDecodeAgn_info16_imm_T_8 = if4__preDecodeAgn_T[2]; // @[IF3.scala 353:128]
  wire  if4__preDecodeAgn_info16_imm_T_9 = if4__preDecodeAgn_T[11]; // @[IF3.scala 353:140]
  wire [2:0] if4__preDecodeAgn_info16_imm_T_10 = if4__preDecodeAgn_T[5:3]; // @[IF3.scala 353:153]
  wire [63:0] if4__preDecodeAgn_info16_imm_T_11 = {if4__preDecodeAgn_info16_imm_T_2,if4__preDecodeAgn_info16_imm_T,
    if4__preDecodeAgn_info16_imm_T_4,if4__preDecodeAgn_info16_imm_T_5,if4__preDecodeAgn_info16_imm_T_6,
    if4__preDecodeAgn_info16_imm_T_7,if4__preDecodeAgn_info16_imm_T_8,if4__preDecodeAgn_info16_imm_T_9,
    if4__preDecodeAgn_info16_imm_T_10,1'h0}; // @[Cat.scala 33:92]
  wire [54:0] if4__preDecodeAgn_info16_imm_T_14 = if4__preDecodeAgn_info16_imm_T ? 55'h7fffffffffffff : 55'h0; // @[Bitwise.scala 77:12]
  wire [1:0] if4__preDecodeAgn_info16_imm_T_16 = if4__preDecodeAgn_T[6:5]; // @[IF3.scala 355:77]
  wire [1:0] if4__preDecodeAgn_info16_imm_T_18 = if4__preDecodeAgn_T[11:10]; // @[IF3.scala 355:103]
  wire [1:0] if4__preDecodeAgn_info16_imm_T_19 = if4__preDecodeAgn_T[4:3]; // @[IF3.scala 355:119]
  wire [63:0] if4__preDecodeAgn_info16_imm_T_20 = {if4__preDecodeAgn_info16_imm_T_14,if4__preDecodeAgn_info16_imm_T,
    if4__preDecodeAgn_info16_imm_T_16,if4__preDecodeAgn_info16_imm_T_8,if4__preDecodeAgn_info16_imm_T_18,
    if4__preDecodeAgn_info16_imm_T_19,1'h0}; // @[Cat.scala 33:92]
  wire [63:0] if4__preDecodeAgn_info16_imm_T_21 = if4__preDecodeAgn_info16_is_jal_T_1 ?
    if4__preDecodeAgn_info16_imm_T_11 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4__preDecodeAgn_info16_imm_T_23 = if4__preDecodeAgn_info16_is_branch_T_1 ?
    if4__preDecodeAgn_info16_imm_T_20 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4__preDecodeAgn_info16_imm_T_25 = if4__preDecodeAgn_info16_imm_T_21 | if4__preDecodeAgn_info16_imm_T_23; // @[Mux.scala 27:73]
  wire [6:0] if4__preDecodeAgn_info32_is_jal_T = if4_io_if4_req_0_bits_instr[6:0]; // @[IF3.scala 370:33]
  wire  if4__preDecodeAgn_info32_is_jal_T_1 = if4__preDecodeAgn_info32_is_jal_T == 7'h6f; // @[IF3.scala 370:39]
  wire  if4__preDecodeAgn_info32_is_jalr_T_1 = if4__preDecodeAgn_info32_is_jal_T == 7'h67; // @[IF3.scala 371:39]
  wire  if4__preDecodeAgn_info32_is_branch_T_1 = if4__preDecodeAgn_info32_is_jal_T == 7'h63; // @[IF3.scala 372:39]
  wire  if4__preDecodeAgn_info32_is_call_T = if4__preDecodeAgn_info32_is_jal_T_1 | if4__preDecodeAgn_info32_is_jalr_T_1; // @[IF3.scala 373:41]
  wire [4:0] if4__preDecodeAgn_info32_is_call_T_1 = if4_io_if4_req_0_bits_instr[11:7]; // @[IF3.scala 373:71]
  wire [4:0] if4__preDecodeAgn_info32_is_call_T_2 = if4__preDecodeAgn_info32_is_call_T_1 & 5'h1b; // @[IF3.scala 373:78]
  wire  if4__preDecodeAgn_info32_is_call_T_3 = 5'h1 == if4__preDecodeAgn_info32_is_call_T_2; // @[IF3.scala 373:78]
  wire  if4__preDecodeAgn_info32_is_call_T_4 = if4__preDecodeAgn_info32_is_call_T & if4__preDecodeAgn_info32_is_call_T_3
    ; // @[IF3.scala 373:60]
  wire [4:0] if4__preDecodeAgn_info32_is_return_T = if4_io_if4_req_0_bits_instr[19:15]; // @[IF3.scala 374:51]
  wire [4:0] if4__preDecodeAgn_info32_is_return_T_1 = if4__preDecodeAgn_info32_is_return_T & 5'h1b; // @[IF3.scala 374:59]
  wire  if4__preDecodeAgn_info32_is_return_T_2 = 5'h1 == if4__preDecodeAgn_info32_is_return_T_1; // @[IF3.scala 374:59]
  wire  if4__preDecodeAgn_info32_is_return_T_3 = if4__preDecodeAgn_info32_is_jalr_T_1 &
    if4__preDecodeAgn_info32_is_return_T_2; // @[IF3.scala 374:40]
  wire  if4__preDecodeAgn_info32_is_return_T_6 = if4__preDecodeAgn_info32_is_return_T !=
    if4__preDecodeAgn_info32_is_call_T_1; // @[IF3.scala 374:100]
  wire  if4__preDecodeAgn_info32_is_return_T_7 = if4__preDecodeAgn_info32_is_return_T_3 &
    if4__preDecodeAgn_info32_is_return_T_6; // @[IF3.scala 374:82]
  wire  if4__preDecodeAgn_info32_imm_T = if4_io_if4_req_0_bits_instr[31]; // @[IF3.scala 379:50]
  wire [43:0] if4__preDecodeAgn_info32_imm_T_2 = if4__preDecodeAgn_info32_imm_T ? 44'hfffffffffff : 44'h0; // @[Bitwise.scala 77:12]
  wire [7:0] if4__preDecodeAgn_info32_imm_T_3 = if4_io_if4_req_0_bits_instr[19:12]; // @[IF3.scala 379:64]
  wire  if4__preDecodeAgn_info32_imm_T_4 = if4_io_if4_req_0_bits_instr[20]; // @[IF3.scala 379:80]
  wire [9:0] if4__preDecodeAgn_info32_imm_T_5 = if4_io_if4_req_0_bits_instr[30:21]; // @[IF3.scala 379:93]
  wire [63:0] if4__preDecodeAgn_info32_imm_T_6 = {if4__preDecodeAgn_info32_imm_T_2,if4__preDecodeAgn_info32_imm_T_3,
    if4__preDecodeAgn_info32_imm_T_4,if4__preDecodeAgn_info32_imm_T_5,1'h0}; // @[Cat.scala 33:92]
  wire [51:0] if4__preDecodeAgn_info32_imm_T_9 = if4__preDecodeAgn_info32_imm_T ? 52'hfffffffffffff : 52'h0; // @[Bitwise.scala 77:12]
  wire [11:0] if4__preDecodeAgn_info32_imm_T_10 = if4_io_if4_req_0_bits_instr[31:20]; // @[IF3.scala 380:64]
  wire [63:0] if4__preDecodeAgn_info32_imm_T_11 = {if4__preDecodeAgn_info32_imm_T_9,if4__preDecodeAgn_info32_imm_T_10}; // @[Cat.scala 33:92]
  wire  if4__preDecodeAgn_info32_imm_T_15 = if4_io_if4_req_0_bits_instr[7]; // @[IF3.scala 381:64]
  wire [5:0] if4__preDecodeAgn_info32_imm_T_16 = if4_io_if4_req_0_bits_instr[30:25]; // @[IF3.scala 381:76]
  wire [3:0] if4__preDecodeAgn_info32_imm_T_17 = if4_io_if4_req_0_bits_instr[11:8]; // @[IF3.scala 381:92]
  wire [63:0] if4__preDecodeAgn_info32_imm_T_18 = {if4__preDecodeAgn_info32_imm_T_9,if4__preDecodeAgn_info32_imm_T_15,
    if4__preDecodeAgn_info32_imm_T_16,if4__preDecodeAgn_info32_imm_T_17,1'h0}; // @[Cat.scala 33:92]
  wire [63:0] if4__preDecodeAgn_info32_imm_T_19 = if4__preDecodeAgn_info32_is_jal_T_1 ? if4__preDecodeAgn_info32_imm_T_6
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4__preDecodeAgn_info32_imm_T_20 = if4__preDecodeAgn_info32_is_jalr_T_1 ?
    if4__preDecodeAgn_info32_imm_T_11 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4__preDecodeAgn_info32_imm_T_21 = if4__preDecodeAgn_info32_is_branch_T_1 ?
    if4__preDecodeAgn_info32_imm_T_18 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4__preDecodeAgn_info32_imm_T_22 = if4__preDecodeAgn_info32_imm_T_19 | if4__preDecodeAgn_info32_imm_T_20; // @[Mux.scala 27:73]
  wire [63:0] if4__preDecodeAgn_info32_imm_T_23 = if4__preDecodeAgn_info32_imm_T_22 | if4__preDecodeAgn_info32_imm_T_21; // @[Mux.scala 27:73]
  wire  if4_preDecodeAgn_0_is_jal = if4_io_if4_req_0_bits_isRVC ? if4__preDecodeAgn_info16_is_jal_T_1 :
    if4__preDecodeAgn_info32_is_jal_T_1; // @[IF4.scala 58:46]
  wire  if4_preDecodeAgn_0_is_jalr = if4_io_if4_req_0_bits_isRVC ? if4__preDecodeAgn_info16_is_jalr_T_4 :
    if4__preDecodeAgn_info32_is_jalr_T_1; // @[IF4.scala 58:46]
  wire  if4_preDecodeAgn_0_is_branch = if4_io_if4_req_0_bits_isRVC ? if4__preDecodeAgn_info16_is_branch_T_1 :
    if4__preDecodeAgn_info32_is_branch_T_1; // @[IF4.scala 58:46]
  wire  if4_preDecodeAgn_0_is_call = if4_io_if4_req_0_bits_isRVC ? if4__preDecodeAgn_info16_is_call_T_4 :
    if4__preDecodeAgn_info32_is_call_T_4; // @[IF4.scala 58:46]
  wire  if4_preDecodeAgn_0_is_return = if4_io_if4_req_0_bits_isRVC ? if4__preDecodeAgn_info16_is_return_T_1 :
    if4__preDecodeAgn_info32_is_return_T_7; // @[IF4.scala 58:46]
  wire [63:0] if4_preDecodeAgn_0_imm = if4_io_if4_req_0_bits_isRVC ? if4__preDecodeAgn_info16_imm_T_25 :
    if4__preDecodeAgn_info32_imm_T_23; // @[IF4.scala 58:46]
  wire  if4__tage_decode_isTableSel_T = if4_tageRedirect_mdl_io_deq_0_bits_0_use != 2'h0; // @[TAGE.scala 241:42]
  wire  if4_tage_decode_isTableSel_0 = if4__tage_decode_isTableSel_T & if4_tageRedirect_mdl_io_deq_0_bits_0_is_hit; // @[TAGE.scala 241:50]
  wire  if4__tage_decode_isTableSel_T_1 = if4_tageRedirect_mdl_io_deq_0_bits_1_use != 2'h0; // @[TAGE.scala 241:42]
  wire  if4_tage_decode_isTableSel_1 = if4__tage_decode_isTableSel_T_1 & if4_tageRedirect_mdl_io_deq_0_bits_1_is_hit; // @[TAGE.scala 241:50]
  wire  if4__tage_decode_isTableSel_T_2 = if4_tageRedirect_mdl_io_deq_0_bits_2_use != 2'h0; // @[TAGE.scala 241:42]
  wire  if4_tage_decode_isTableSel_2 = if4__tage_decode_isTableSel_T_2 & if4_tageRedirect_mdl_io_deq_0_bits_2_is_hit; // @[TAGE.scala 241:50]
  wire  if4__tage_decode_isTableSel_T_3 = if4_tageRedirect_mdl_io_deq_0_bits_3_use != 2'h0; // @[TAGE.scala 241:42]
  wire  if4_tage_decode_isTableSel_3 = if4__tage_decode_isTableSel_T_3 & if4_tageRedirect_mdl_io_deq_0_bits_3_is_hit; // @[TAGE.scala 241:50]
  wire  if4__tage_decode_isTableSel_T_4 = if4_tageRedirect_mdl_io_deq_0_bits_4_use != 2'h0; // @[TAGE.scala 241:42]
  wire  if4_tage_decode_isTableSel_4 = if4__tage_decode_isTableSel_T_4 & if4_tageRedirect_mdl_io_deq_0_bits_4_is_hit; // @[TAGE.scala 241:50]
  wire  if4__tage_decode_isTableSel_T_5 = if4_tageRedirect_mdl_io_deq_0_bits_5_use != 2'h0; // @[TAGE.scala 241:42]
  wire  if4_tage_decode_isTableSel_5 = if4__tage_decode_isTableSel_T_5 & if4_tageRedirect_mdl_io_deq_0_bits_5_is_hit; // @[TAGE.scala 241:50]
  wire  if4__GEN_2 = if4_tage_decode_isTableSel_1 ? 1'h0 : if4_tage_decode_isTableSel_0; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_4 = if4_tage_decode_isTableSel_2 ? 1'h0 : if4__GEN_2; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_5 = if4_tage_decode_isTableSel_2 ? 1'h0 : if4_tage_decode_isTableSel_1; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_7 = if4_tage_decode_isTableSel_3 ? 1'h0 : if4__GEN_4; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_8 = if4_tage_decode_isTableSel_3 ? 1'h0 : if4__GEN_5; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_9 = if4_tage_decode_isTableSel_3 ? 1'h0 : if4_tage_decode_isTableSel_2; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_11 = if4_tage_decode_isTableSel_4 ? 1'h0 : if4__GEN_7; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_12 = if4_tage_decode_isTableSel_4 ? 1'h0 : if4__GEN_8; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_13 = if4_tage_decode_isTableSel_4 ? 1'h0 : if4__GEN_9; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_14 = if4_tage_decode_isTableSel_4 ? 1'h0 : if4_tage_decode_isTableSel_3; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_16 = if4_tage_decode_isTableSel_5 ? 1'h0 : if4__GEN_11; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_17 = if4_tage_decode_isTableSel_5 ? 1'h0 : if4__GEN_12; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_18 = if4_tage_decode_isTableSel_5 ? 1'h0 : if4__GEN_13; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_19 = if4_tage_decode_isTableSel_5 ? 1'h0 : if4__GEN_14; // @[TAGE.scala 245:29 248:30]
  wire  if4__GEN_20 = if4_tage_decode_isTableSel_5 ? 1'h0 : if4_tage_decode_isTableSel_4; // @[TAGE.scala 245:29 248:30]
  wire  if4__tage_decode_resp_isAltpred_0_T = ~if4__GEN_16; // @[TAGE.scala 254:44]
  wire  if4__tage_decode_resp_isAltpred_0_T_1 = if4_tage_decode_isTableSel_0 & if4__tage_decode_resp_isAltpred_0_T; // @[TAGE.scala 254:42]
  wire  if4__tage_decode_resp_isAltpred_1_T = ~if4__GEN_17; // @[TAGE.scala 254:44]
  wire  if4__tage_decode_resp_isAltpred_1_T_1 = if4_tage_decode_isTableSel_1 & if4__tage_decode_resp_isAltpred_1_T; // @[TAGE.scala 254:42]
  wire  if4__tage_decode_resp_isAltpred_2_T = ~if4__GEN_18; // @[TAGE.scala 254:44]
  wire  if4__tage_decode_resp_isAltpred_2_T_1 = if4_tage_decode_isTableSel_2 & if4__tage_decode_resp_isAltpred_2_T; // @[TAGE.scala 254:42]
  wire  if4__tage_decode_resp_isAltpred_3_T = ~if4__GEN_19; // @[TAGE.scala 254:44]
  wire  if4__tage_decode_resp_isAltpred_3_T_1 = if4_tage_decode_isTableSel_3 & if4__tage_decode_resp_isAltpred_3_T; // @[TAGE.scala 254:42]
  wire  if4__tage_decode_resp_isAltpred_4_T = ~if4__GEN_20; // @[TAGE.scala 254:44]
  wire  if4__tage_decode_resp_isAltpred_4_T_1 = if4_tage_decode_isTableSel_4 & if4__tage_decode_resp_isAltpred_4_T; // @[TAGE.scala 254:42]
  wire  if4__tage_decode_resp_isAltpred_5_T = ~if4_tage_decode_isTableSel_5; // @[TAGE.scala 254:44]
  wire  if4__tage_decode_resp_isAltpred_5_T_1 = if4_tage_decode_isTableSel_5 & if4__tage_decode_resp_isAltpred_5_T; // @[TAGE.scala 254:42]
  wire  if4__tage_decode_T = if4__GEN_16 ^ if4_tage_decode_isTableSel_0; // @[TAGE.scala 262:57]
  wire  if4__tage_decode_T_1 = if4__tage_decode_resp_isAltpred_0_T_1 == if4__tage_decode_T; // @[TAGE.scala 262:33]
  wire  if4__tage_decode_T_3 = ~if4_reset; // @[TAGE.scala 262:13]
  wire  if4__tage_decode_T_4 = ~if4__tage_decode_T_1; // @[TAGE.scala 262:13]
  wire  if4__tage_decode_T_5 = if4__GEN_17 ^ if4_tage_decode_isTableSel_1; // @[TAGE.scala 262:57]
  wire  if4__tage_decode_T_6 = if4__tage_decode_resp_isAltpred_1_T_1 == if4__tage_decode_T_5; // @[TAGE.scala 262:33]
  wire  if4__tage_decode_T_9 = ~if4__tage_decode_T_6; // @[TAGE.scala 262:13]
  wire  if4__tage_decode_T_10 = if4__GEN_18 ^ if4_tage_decode_isTableSel_2; // @[TAGE.scala 262:57]
  wire  if4__tage_decode_T_11 = if4__tage_decode_resp_isAltpred_2_T_1 == if4__tage_decode_T_10; // @[TAGE.scala 262:33]
  wire  if4__tage_decode_T_14 = ~if4__tage_decode_T_11; // @[TAGE.scala 262:13]
  wire  if4__tage_decode_T_15 = if4__GEN_19 ^ if4_tage_decode_isTableSel_3; // @[TAGE.scala 262:57]
  wire  if4__tage_decode_T_16 = if4__tage_decode_resp_isAltpred_3_T_1 == if4__tage_decode_T_15; // @[TAGE.scala 262:33]
  wire  if4__tage_decode_T_19 = ~if4__tage_decode_T_16; // @[TAGE.scala 262:13]
  wire  if4__tage_decode_T_20 = if4__GEN_20 ^ if4_tage_decode_isTableSel_4; // @[TAGE.scala 262:57]
  wire  if4__tage_decode_T_21 = if4__tage_decode_resp_isAltpred_4_T_1 == if4__tage_decode_T_20; // @[TAGE.scala 262:33]
  wire  if4__tage_decode_T_24 = ~if4__tage_decode_T_21; // @[TAGE.scala 262:13]
  wire  if4__tage_decode_T_26 = ~if4__tage_decode_resp_isAltpred_5_T_1; // @[TAGE.scala 262:33]
  wire  if4__tage_decode_T_29 = ~if4__tage_decode_T_26; // @[TAGE.scala 262:13]
  wire [1:0] if4__tage_decode_T_30 = if4__GEN_17 + if4__GEN_18; // @[Bitwise.scala 51:90]
  wire [1:0] _GEN_211 = {{1'd0}, if4__GEN_16}; // @[Bitwise.scala 51:90]
  wire [2:0] if4__tage_decode_T_32 = _GEN_211 + if4__tage_decode_T_30; // @[Bitwise.scala 51:90]
  wire [1:0] if4__tage_decode_T_33 = if4__tage_decode_T_32[1:0]; // @[Bitwise.scala 51:90]
  wire [1:0] if4__tage_decode_T_34 = if4__GEN_20 + if4_tage_decode_isTableSel_5; // @[Bitwise.scala 51:90]
  wire [1:0] _GEN_212 = {{1'd0}, if4__GEN_19}; // @[Bitwise.scala 51:90]
  wire [2:0] if4__tage_decode_T_36 = _GEN_212 + if4__tage_decode_T_34; // @[Bitwise.scala 51:90]
  wire [1:0] if4__tage_decode_T_37 = if4__tage_decode_T_36[1:0]; // @[Bitwise.scala 51:90]
  wire [2:0] if4__tage_decode_T_38 = if4__tage_decode_T_33 + if4__tage_decode_T_37; // @[Bitwise.scala 51:90]
  wire  if4__tage_decode_T_40 = if4__tage_decode_T_38 <= 3'h1; // @[TAGE.scala 264:41]
  wire  if4__tage_decode_T_43 = ~if4__tage_decode_T_40; // @[TAGE.scala 264:11]
  wire  if4__isRedirect_0_T = if4_preDecodeAgn_0_is_branch & if4_bimRedirect_mdl_io_deq_0_bits_bim_p; // @[IF4.scala 123:19]
  wire  if4__isRedirect_0_T_1 = if4__isRedirect_0_T | if4_preDecodeAgn_0_is_jal; // @[IF4.scala 123:35]
  wire  if4__isRedirect_0_T_2 = if4__isRedirect_0_T_1 | if4_preDecodeAgn_0_is_jalr; // @[IF4.scala 124:15]
  wire  if4__jalr_pc_T = if4_preDecodeAgn_0_is_return & if4_ras_io_deq_valid; // @[IF4.scala 129:33]
  wire [38:0] if4__jalr_pc_T_1 = if4__jalr_pc_T ? if4_ras_io_deq_bits_target : if4_btbRedirect_mdl_io_deq_0_bits_target; // @[IF4.scala 129:18]
  wire  if4__jalr_pc_v64_T = if4__jalr_pc_T_1[38]; // @[Util.scala 47:31]
  wire [24:0] if4__jalr_pc_v64_T_2 = if4__jalr_pc_v64_T ? 25'h1ffffff : 25'h0; // @[Bitwise.scala 77:12]
  wire [63:0] if4__jalr_pc_v64_T_4 = {if4__jalr_pc_v64_T_2,if4__jalr_pc_T_1}; // @[Cat.scala 33:92]
  wire  if4__ras_io_deq_ready_T = if4_io_if4_req_0_ready & if4_io_if4_req_0_valid; // @[Decoupled.scala 52:35]
  wire [2:0] if4__ras_io_enq_bits_target_T = if4_io_if4_req_0_bits_isRVC ? 3'h2 : 3'h4; // @[IF4.scala 139:32]
  wire [38:0] _GEN_213 = {{36'd0}, if4__ras_io_enq_bits_target_T}; // @[IF4.scala 139:27]
  wire [38:0] if4__ras_io_enq_bits_target_T_2 = if4_io_if4_req_0_bits_pc + _GEN_213; // @[IF4.scala 139:27]
  wire [63:0] _GEN_214 = {{25'd0}, if4_io_if4_req_0_bits_pc}; // @[IF4.scala 146:47]
  wire [63:0] if4__redirectTarget_0_T_2 = _GEN_214 + if4_preDecodeAgn_0_imm; // @[IF4.scala 146:47]
  wire [63:0] if4__redirectTarget_0_T_5 = if4__isRedirect_0_T ? if4__redirectTarget_0_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4__redirectTarget_0_T_6 = if4_preDecodeAgn_0_is_jal ? if4__redirectTarget_0_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4__redirectTarget_0_T_7 = if4_preDecodeAgn_0_is_jalr ? if4__jalr_pc_v64_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] if4__redirectTarget_0_T_8 = if4__redirectTarget_0_T_5 | if4__redirectTarget_0_T_6; // @[Mux.scala 27:73]
  wire [63:0] if4__redirectTarget_0_T_9 = if4__redirectTarget_0_T_8 | if4__redirectTarget_0_T_7; // @[Mux.scala 27:73]
  wire  if4__isDisAgreeWithIF1_0_T = if4__isRedirect_0_T_2 != if4_io_if4_req_0_bits_isRedirect; // @[IF4.scala 168:23]
  wire  if4__isDisAgreeWithIF1_0_T_1 = if4__isRedirect_0_T_2 == if4_io_if4_req_0_bits_isRedirect; // @[IF4.scala 169:23]
  wire [63:0] _GEN_216 = {{25'd0}, if4_io_if4_req_0_bits_target}; // @[IF4.scala 169:87]
  wire  if4__isDisAgreeWithIF1_0_T_2 = _GEN_216 != if4__redirectTarget_0_T_9; // @[IF4.scala 169:87]
  wire  if4__isDisAgreeWithIF1_0_T_3 = if4__isDisAgreeWithIF1_0_T_1 & if4__isDisAgreeWithIF1_0_T_2; // @[IF4.scala 169:58]
  wire  if4__isDisAgreeWithIF1_0_T_4 = if4__isDisAgreeWithIF1_0_T | if4__isDisAgreeWithIF1_0_T_3; // @[IF4.scala 168:58]
  wire  if4__isIf4Redirect_0_T_1 = if4__ras_io_deq_ready_T & if4__isDisAgreeWithIF1_0_T_4; // @[IF4.scala 171:44]
  wire  if4__T = ~if4__isRedirect_0_T_2; // @[IF4.scala 173:11]
  wire  if4__T_1 = if4__redirectTarget_0_T_9 == 64'h0; // @[IF4.scala 173:56]
  wire  if4__T_4 = ~if4__T_1; // @[IF4.scala 173:36]
  wire  if4__T_5 = ~if4_io_if4_req_0_bits_isRedirect; // @[IF4.scala 174:33]
  wire  if4__T_6 = if4_io_if4_req_0_valid & if4__T_5; // @[IF4.scala 174:31]
  wire  if4__T_7 = if4_io_if4_req_0_bits_target == 39'h0; // @[IF4.scala 174:102]
  wire  if4__T_10 = ~if4__T_7; // @[IF4.scala 174:74]
  wire [63:0] if4__io_if4Redirect_bits_target_T_3 = if4__isRedirect_0_T_2 ? if4__redirectTarget_0_T_9 : {{25'd0},
    if4__ras_io_enq_bits_target_T_2}; // @[IF4.scala 181:31]
  wire [63:0] if4__io_if4Redirect_bits_target_T_4 = if4__isIf4Redirect_0_T_1 ? if4__io_if4Redirect_bits_target_T_3 : 64'h0
    ; // @[Mux.scala 101:16]
  wire  if4__T_11 = ~if4_btbRedirect_mdl_io_deq_0_valid; // @[IF4.scala 224:39]
  wire  if4__T_12 = if4_btbRedirect_mdl_io_deq_0_ready & if4__T_11; // @[IF4.scala 224:37]
  wire  if4__T_13 = ~if4__T_12; // @[IF4.scala 224:13]
  wire  if4__T_16 = ~if4__T_13; // @[IF4.scala 224:11]
  wire  if4__T_17 = ~if4_bimRedirect_mdl_io_deq_0_valid; // @[IF4.scala 225:39]
  wire  if4__T_18 = if4_bimRedirect_mdl_io_deq_0_ready & if4__T_17; // @[IF4.scala 225:37]
  wire  if4__T_19 = ~if4__T_18; // @[IF4.scala 225:13]
  wire  if4__T_22 = ~if4__T_19; // @[IF4.scala 225:11]
  wire  if4__io_if4_req_0_ready_T = if4_bRePort_io_enq_0_ready & if4_jRePort_io_enq_0_ready; // @[IF4.scala 254:50]
  wire  rnm_stage_clock;
  wire  rnm_stage_reset;
  wire  rnm_stage_io_rnReq_0_ready;
  wire  rnm_stage_io_rnReq_0_valid;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_lui;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_auipc;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_addi;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_addiw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_slti;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_sltiu;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_xori;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_ori;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_andi;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_slli;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_slliw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_srli;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_srliw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_srai;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_sraiw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_add;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_addw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_sub;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_subw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_sll;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_sllw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_slt;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_sltu;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_xor;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_srl;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_srlw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_sra;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_sraw;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_or;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_and;
  wire  rnm_stage_io_rnReq_0_bits_alu_isa_wfi;
  wire  rnm_stage_io_rnReq_0_bits_bru_isa_jal;
  wire  rnm_stage_io_rnReq_0_bits_bru_isa_jalr;
  wire  rnm_stage_io_rnReq_0_bits_bru_isa_beq;
  wire  rnm_stage_io_rnReq_0_bits_bru_isa_bne;
  wire  rnm_stage_io_rnReq_0_bits_bru_isa_blt;
  wire  rnm_stage_io_rnReq_0_bits_bru_isa_bge;
  wire  rnm_stage_io_rnReq_0_bits_bru_isa_bltu;
  wire  rnm_stage_io_rnReq_0_bits_bru_isa_bgeu;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_lb;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_lh;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_lw;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_ld;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_lbu;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_lhu;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_lwu;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_sb;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_sh;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_sw;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_sd;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_fence;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_fence_i;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_sfence_vma;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_lr_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_sc_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoswap_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoadd_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoxor_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoand_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoor_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amomin_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amomax_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amominu_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amomaxu_w;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_lr_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_sc_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoswap_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoadd_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoxor_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoand_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amoor_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amomin_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amomax_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amominu_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_amomaxu_d;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_flw;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_fsw;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_fld;
  wire  rnm_stage_io_rnReq_0_bits_lsu_isa_fsd;
  wire  rnm_stage_io_rnReq_0_bits_csr_isa_rw;
  wire  rnm_stage_io_rnReq_0_bits_csr_isa_rs;
  wire  rnm_stage_io_rnReq_0_bits_csr_isa_rc;
  wire  rnm_stage_io_rnReq_0_bits_csr_isa_rwi;
  wire  rnm_stage_io_rnReq_0_bits_csr_isa_rsi;
  wire  rnm_stage_io_rnReq_0_bits_csr_isa_rci;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_mul;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_mulh;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_mulhsu;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_mulhu;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_div;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_divu;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_rem;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_remu;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_mulw;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_divw;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_divuw;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_remw;
  wire  rnm_stage_io_rnReq_0_bits_mul_isa_remuw;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_ecall;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_ebreak;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_mret;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_uret;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_sret;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_dret;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hfence_vvma;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hfence_gvma;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlv_b;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlv_bu;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlv_h;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlv_hu;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlvx_hu;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlv_w;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlvx_wu;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hsv_b;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hsv_h;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hsv_w;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlv_wu;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hlv_d;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_hsv_d;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_is_access_fault;
  wire  rnm_stage_io_rnReq_0_bits_privil_isa_is_paging_fault;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_w;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_feq_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_flt_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fle_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_w;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_wu;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_w_x;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_l;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_lu;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_s;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_feq_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_flt_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fle_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_w;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_wu;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_d;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_l;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_lu;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_d_x;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rw;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rs;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rc;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rwi;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rsi;
  wire  rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rci;
  wire  rnm_stage_io_rnReq_0_bits_param_is_rvc;
  wire [38:0] rnm_stage_io_rnReq_0_bits_param_pc;
  wire [63:0] rnm_stage_io_rnReq_0_bits_param_imm;
  wire [4:0] rnm_stage_io_rnReq_0_bits_param_raw_rs1;
  wire [4:0] rnm_stage_io_rnReq_0_bits_param_raw_rs2;
  wire [4:0] rnm_stage_io_rnReq_0_bits_param_raw_rd0;
  wire  rnm_stage_io_rnRsp_0_ready;
  wire  rnm_stage_io_rnRsp_0_valid;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_lui;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_auipc;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_addi;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_addiw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_slti;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_sltiu;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_xori;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_ori;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_andi;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_slli;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_slliw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_srli;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_srliw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_srai;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_sraiw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_add;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_addw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_sub;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_subw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_sll;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_sllw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_slt;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_sltu;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_xor;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_srl;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_srlw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_sra;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_sraw;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_or;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_and;
  wire  rnm_stage_io_rnRsp_0_bits_alu_isa_wfi;
  wire  rnm_stage_io_rnRsp_0_bits_bru_isa_jal;
  wire  rnm_stage_io_rnRsp_0_bits_bru_isa_jalr;
  wire  rnm_stage_io_rnRsp_0_bits_bru_isa_beq;
  wire  rnm_stage_io_rnRsp_0_bits_bru_isa_bne;
  wire  rnm_stage_io_rnRsp_0_bits_bru_isa_blt;
  wire  rnm_stage_io_rnRsp_0_bits_bru_isa_bge;
  wire  rnm_stage_io_rnRsp_0_bits_bru_isa_bltu;
  wire  rnm_stage_io_rnRsp_0_bits_bru_isa_bgeu;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_lb;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_lh;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_lw;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_ld;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_lbu;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_lhu;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_lwu;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_sb;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_sh;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_sw;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_sd;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_fence;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_fence_i;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_sfence_vma;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_lr_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_sc_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoswap_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoadd_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoxor_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoand_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoor_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amomin_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amomax_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amominu_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amomaxu_w;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_lr_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_sc_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoswap_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoadd_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoxor_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoand_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amoor_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amomin_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amomax_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amominu_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_amomaxu_d;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_flw;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_fsw;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_fld;
  wire  rnm_stage_io_rnRsp_0_bits_lsu_isa_fsd;
  wire  rnm_stage_io_rnRsp_0_bits_csr_isa_rw;
  wire  rnm_stage_io_rnRsp_0_bits_csr_isa_rs;
  wire  rnm_stage_io_rnRsp_0_bits_csr_isa_rc;
  wire  rnm_stage_io_rnRsp_0_bits_csr_isa_rwi;
  wire  rnm_stage_io_rnRsp_0_bits_csr_isa_rsi;
  wire  rnm_stage_io_rnRsp_0_bits_csr_isa_rci;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_mul;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_mulh;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_mulhsu;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_mulhu;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_div;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_divu;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_rem;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_remu;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_mulw;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_divw;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_divuw;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_remw;
  wire  rnm_stage_io_rnRsp_0_bits_mul_isa_remuw;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmadd_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmsub_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmsub_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmadd_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fadd_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsub_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmul_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fdiv_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsqrt_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnj_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjn_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjx_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmin_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmax_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_w_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_wu_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmv_x_w;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_feq_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_flt_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fle_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fclass_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_l_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_lu_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmadd_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmsub_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmsub_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmadd_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fadd_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsub_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmul_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fdiv_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsqrt_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnj_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjn_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjx_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmin_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmax_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_s_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_d_s;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_feq_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_flt_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fle_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fclass_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_w_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_wu_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_l_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_lu_d;
  wire  rnm_stage_io_rnRsp_0_bits_fpu_isa_fmv_x_d;
  wire  rnm_stage_io_rnRsp_0_bits_param_is_rvc;
  wire [38:0] rnm_stage_io_rnRsp_0_bits_param_pc;
  wire [63:0] rnm_stage_io_rnRsp_0_bits_param_imm;
  wire [4:0] rnm_stage_io_rnRsp_0_bits_param_raw_rs1;
  wire [5:0] rnm_stage_io_rnRsp_0_bits_phy_rs1;
  wire [5:0] rnm_stage_io_rnRsp_0_bits_phy_rs2;
  wire [5:0] rnm_stage_io_rnRsp_0_bits_phy_rs3;
  wire [5:0] rnm_stage_io_rnRsp_0_bits_phy_rd0;
  wire [5:0] rnm_stage_io_xLookup_0_rsp_rs1;
  wire [5:0] rnm_stage_io_xLookup_0_rsp_rs2;
  wire [4:0] rnm_stage_io_xLookup_0_req_rs1;
  wire [4:0] rnm_stage_io_xLookup_0_req_rs2;
  wire [5:0] rnm_stage_io_fLookup_0_rsp_rs1;
  wire [5:0] rnm_stage_io_fLookup_0_rsp_rs2;
  wire [5:0] rnm_stage_io_fLookup_0_rsp_rs3;
  wire [5:0] rnm_stage_io_xRename_0_rsp_rd0;
  wire  rnm_stage_io_xRename_0_req_ready;
  wire  rnm_stage_io_xRename_0_req_valid;
  wire [4:0] rnm_stage_io_xRename_0_req_bits_rd0;
  wire [5:0] rnm_stage_io_fRename_0_rsp_rd0;
  wire  rnm_stage_io_fRename_0_req_ready;
  wire  rnm_stage_io_fRename_0_req_valid;
  wire  rnm_stage_io_rod_i_0_ready;
  wire  rnm_stage_io_rod_i_0_valid;
  wire [38:0] rnm_stage_io_rod_i_0_bits_pc;
  wire [4:0] rnm_stage_io_rod_i_0_bits_rd0_raw;
  wire [5:0] rnm_stage_io_rod_i_0_bits_rd0_phy;
  wire  rnm_stage_io_rod_i_0_bits_is_branch;
  wire  rnm_stage_io_rod_i_0_bits_is_jalr;
  wire  rnm_stage_io_rod_i_0_bits_is_lu;
  wire  rnm_stage_io_rod_i_0_bits_is_su;
  wire  rnm_stage_io_rod_i_0_bits_is_amo;
  wire  rnm_stage_io_rod_i_0_bits_is_fence_i;
  wire  rnm_stage_io_rod_i_0_bits_is_sfence_vma;
  wire  rnm_stage_io_rod_i_0_bits_is_wfi;
  wire  rnm_stage_io_rod_i_0_bits_is_csr;
  wire  rnm_stage_io_rod_i_0_bits_is_fpu;
  wire  rnm_stage_io_rod_i_0_bits_is_fcsr;
  wire  rnm_stage_io_rod_i_0_bits_is_xcmm;
  wire  rnm_stage_io_rod_i_0_bits_is_fcmm;
  wire  rnm_stage_io_rod_i_0_bits_privil_ecall;
  wire  rnm_stage_io_rod_i_0_bits_privil_ebreak;
  wire  rnm_stage_io_rod_i_0_bits_privil_mret;
  wire  rnm_stage_io_rod_i_0_bits_privil_sret;
  wire  rnm_stage_io_rod_i_0_bits_privil_dret;
  wire  rnm_stage_io_rod_i_0_bits_privil_is_access_fault;
  wire  rnm_stage_io_rod_i_0_bits_privil_is_paging_fault;
  wire  rnm_stage_io_rod_i_0_bits_is_illeage;
  wire  rnm_stage_rnRspReport_clock;
  wire  rnm_stage_rnRspReport_reset;
  wire  rnm_stage_rnRspReport_io_enq_0_ready;
  wire  rnm_stage_rnRspReport_io_enq_0_valid;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_lui;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_auipc;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addi;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addiw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slti;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sltiu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_xori;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_ori;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_andi;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slli;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slliw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srli;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srliw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srai;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sraiw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_add;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sub;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_subw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sll;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sllw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slt;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sltu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_xor;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srl;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srlw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sra;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sraw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_or;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_and;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_wfi;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_jal;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_jalr;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_beq;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bne;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_blt;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bge;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bltu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bgeu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lb;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lh;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_ld;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lbu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lhu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lwu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sb;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sh;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sd;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fence;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fence_i;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sfence_vma;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lr_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sc_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoswap_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoadd_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoxor_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoand_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoor_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomin_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomax_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amominu_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomaxu_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lr_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sc_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoswap_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoadd_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoxor_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoand_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoor_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomin_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomax_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amominu_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomaxu_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_flw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fsw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fld;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fsd;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rs;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rc;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rwi;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rsi;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rci;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mul;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulh;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulhsu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulhu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_div;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_rem;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remu;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divuw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remuw;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmadd_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmsub_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmsub_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmadd_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fadd_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsub_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmul_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fdiv_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsqrt_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnj_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjn_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjx_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmin_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmax_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_w_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_wu_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmv_x_w;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_feq_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_flt_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fle_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fclass_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_l_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_lu_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmadd_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmsub_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmsub_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmadd_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fadd_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsub_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmul_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fdiv_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsqrt_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnj_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjn_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjx_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmin_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmax_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_s_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_d_s;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_feq_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_flt_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fle_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fclass_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_w_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_wu_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_l_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_lu_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmv_x_d;
  wire  rnm_stage_rnRspReport_io_enq_0_bits_param_is_rvc;
  wire [38:0] rnm_stage_rnRspReport_io_enq_0_bits_param_pc;
  wire [63:0] rnm_stage_rnRspReport_io_enq_0_bits_param_imm;
  wire [4:0] rnm_stage_rnRspReport_io_enq_0_bits_param_raw_rs1;
  wire [5:0] rnm_stage_rnRspReport_io_enq_0_bits_phy_rs1;
  wire [5:0] rnm_stage_rnRspReport_io_enq_0_bits_phy_rs2;
  wire [5:0] rnm_stage_rnRspReport_io_enq_0_bits_phy_rs3;
  wire [5:0] rnm_stage_rnRspReport_io_enq_0_bits_phy_rd0;
  wire  rnm_stage_rnRspReport_io_deq_0_ready;
  wire  rnm_stage_rnRspReport_io_deq_0_valid;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_lui;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_auipc;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addi;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addiw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slti;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sltiu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_xori;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_ori;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_andi;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slli;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slliw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srli;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srliw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srai;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sraiw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_add;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sub;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_subw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sll;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sllw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slt;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sltu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_xor;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srl;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srlw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sra;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sraw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_or;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_and;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_wfi;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_jal;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_jalr;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_beq;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bne;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_blt;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bge;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bltu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bgeu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lb;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lh;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_ld;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lbu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lhu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lwu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sb;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sh;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sd;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fence;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fence_i;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sfence_vma;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lr_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sc_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoswap_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoadd_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoxor_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoand_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoor_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomin_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomax_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amominu_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomaxu_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lr_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sc_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoswap_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoadd_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoxor_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoand_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoor_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomin_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomax_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amominu_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomaxu_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_flw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fsw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fld;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fsd;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rs;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rc;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rwi;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rsi;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rci;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mul;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulh;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulhsu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulhu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_div;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_rem;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remu;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divuw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remuw;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmadd_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmsub_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmsub_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmadd_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fadd_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsub_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmul_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fdiv_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsqrt_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnj_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjn_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjx_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmin_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmax_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_w_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_wu_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmv_x_w;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_feq_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_flt_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fle_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fclass_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_l_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_lu_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmadd_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmsub_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmsub_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmadd_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fadd_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsub_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmul_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fdiv_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsqrt_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnj_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjn_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjx_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmin_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmax_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_s_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_d_s;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_feq_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_flt_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fle_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fclass_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_w_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_wu_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_l_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_lu_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmv_x_d;
  wire  rnm_stage_rnRspReport_io_deq_0_bits_param_is_rvc;
  wire [38:0] rnm_stage_rnRspReport_io_deq_0_bits_param_pc;
  wire [63:0] rnm_stage_rnRspReport_io_deq_0_bits_param_imm;
  wire [4:0] rnm_stage_rnRspReport_io_deq_0_bits_param_raw_rs1;
  wire [5:0] rnm_stage_rnRspReport_io_deq_0_bits_phy_rs1;
  wire [5:0] rnm_stage_rnRspReport_io_deq_0_bits_phy_rs2;
  wire [5:0] rnm_stage_rnRspReport_io_deq_0_bits_phy_rs3;
  wire [5:0] rnm_stage_rnRspReport_io_deq_0_bits_phy_rd0;
  wire  rnm_stage_rnRspReport__T = rnm_stage_rnRspReport_io_enq_0_ready & rnm_stage_rnRspReport_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  rnm_stage_rnRspReport__T_1 = rnm_stage_rnRspReport_io_deq_0_ready & rnm_stage_rnRspReport_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  rnm_stage_rnRspReport__T_2 = rnm_stage_rnRspReport__T == rnm_stage_rnRspReport__T_1; // @[RePort.scala 32:45]
  wire  rnm_stage_rnRspReport__T_4 = ~rnm_stage_rnRspReport_reset; // @[RePort.scala 32:12]
  wire  rnm_stage_rnRspReport__T_5 = ~rnm_stage_rnRspReport__T_2; // @[RePort.scala 32:12]
  wire  rnm_stage_rnRspReport__is_end_0_T = ~rnm_stage_rnRspReport_io_enq_0_valid; // @[RePort.scala 62:21]
  wire  rnm_stage_rnRspReport__T_6 = ~rnm_stage_rnRspReport__is_end_0_T; // @[RePort.scala 75:11]
  wire  rnm_stage_rnRspFifo_clock;
  wire  rnm_stage_rnRspFifo_reset;
  wire  rnm_stage_rnRspFifo_io_enq_0_ready;
  wire  rnm_stage_rnRspFifo_io_enq_0_valid;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_lui;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_auipc;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addi;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addiw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slti;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sltiu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_xori;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_ori;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_andi;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slli;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slliw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srli;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srliw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srai;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sraiw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_add;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sub;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_subw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sll;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sllw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slt;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sltu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_xor;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srl;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srlw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sra;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sraw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_or;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_and;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_wfi;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_jal;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_jalr;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_beq;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bne;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_blt;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bge;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bltu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bgeu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lb;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lh;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_ld;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lbu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lhu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lwu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sb;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sh;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sd;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fence;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fence_i;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sfence_vma;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lr_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sc_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoswap_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoadd_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoxor_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoand_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoor_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomin_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomax_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amominu_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomaxu_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lr_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sc_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoswap_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoadd_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoxor_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoand_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoor_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomin_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomax_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amominu_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomaxu_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_flw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fsw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fld;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fsd;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rs;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rc;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rwi;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rsi;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rci;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mul;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulh;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulhsu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulhu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_div;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_rem;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remu;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divuw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remuw;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmadd_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmsub_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmsub_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmadd_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fadd_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsub_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmul_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fdiv_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsqrt_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnj_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjn_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjx_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmin_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmax_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_w_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_wu_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmv_x_w;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_feq_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_flt_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fle_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fclass_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_l_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_lu_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmadd_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmsub_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmsub_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmadd_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fadd_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsub_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmul_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fdiv_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsqrt_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnj_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjn_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjx_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmin_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmax_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_s_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_d_s;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_feq_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_flt_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fle_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fclass_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_w_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_wu_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_l_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_lu_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmv_x_d;
  wire  rnm_stage_rnRspFifo_io_enq_0_bits_param_is_rvc;
  wire [38:0] rnm_stage_rnRspFifo_io_enq_0_bits_param_pc;
  wire [63:0] rnm_stage_rnRspFifo_io_enq_0_bits_param_imm;
  wire [4:0] rnm_stage_rnRspFifo_io_enq_0_bits_param_raw_rs1;
  wire [5:0] rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs1;
  wire [5:0] rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs2;
  wire [5:0] rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs3;
  wire [5:0] rnm_stage_rnRspFifo_io_enq_0_bits_phy_rd0;
  wire  rnm_stage_rnRspFifo_io_deq_0_ready;
  wire  rnm_stage_rnRspFifo_io_deq_0_valid;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_lui;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_auipc;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addi;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addiw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slti;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sltiu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_xori;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_ori;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_andi;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slli;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slliw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srli;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srliw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srai;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sraiw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_add;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sub;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_subw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sll;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sllw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slt;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sltu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_xor;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srl;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srlw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sra;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sraw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_or;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_and;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_wfi;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_jal;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_jalr;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_beq;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bne;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_blt;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bge;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bltu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bgeu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lb;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lh;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_ld;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lbu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lhu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lwu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sb;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sh;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sd;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fence;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fence_i;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sfence_vma;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lr_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sc_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoswap_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoadd_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoxor_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoand_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoor_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomin_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomax_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amominu_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomaxu_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lr_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sc_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoswap_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoadd_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoxor_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoand_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoor_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomin_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomax_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amominu_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomaxu_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_flw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fsw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fld;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fsd;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rs;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rc;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rwi;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rsi;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rci;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mul;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulh;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulhsu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulhu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_div;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_rem;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remu;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divuw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remuw;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmadd_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmsub_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmsub_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmadd_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fadd_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsub_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmul_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fdiv_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsqrt_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnj_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjn_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjx_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmin_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmax_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_w_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_wu_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmv_x_w;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_feq_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_flt_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fle_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fclass_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_l_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_lu_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmadd_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmsub_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmsub_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmadd_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fadd_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsub_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmul_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fdiv_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsqrt_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnj_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjn_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjx_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmin_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmax_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_s_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_d_s;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_feq_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_flt_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fle_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fclass_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_w_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_wu_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_l_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_lu_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmv_x_d;
  wire  rnm_stage_rnRspFifo_io_deq_0_bits_param_is_rvc;
  wire [38:0] rnm_stage_rnRspFifo_io_deq_0_bits_param_pc;
  wire [63:0] rnm_stage_rnRspFifo_io_deq_0_bits_param_imm;
  wire [4:0] rnm_stage_rnRspFifo_io_deq_0_bits_param_raw_rs1;
  wire [5:0] rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs1;
  wire [5:0] rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs2;
  wire [5:0] rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs3;
  wire [5:0] rnm_stage_rnRspFifo_io_deq_0_bits_phy_rd0;
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_lui; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_auipc; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_addi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_addiw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_slti; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_sltiu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_xori; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_ori; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_andi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_slli; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_slliw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_srli; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_srliw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_srai; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_sraiw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_add; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_addw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_sub; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_subw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_sll; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_sllw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_slt; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_sltu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_xor; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_srl; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_srlw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_sra; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_sraw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_or; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_and; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_alu_isa_wfi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_bru_isa_jal; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_bru_isa_jalr; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_bru_isa_beq; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_bru_isa_bne; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_bru_isa_blt; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_bru_isa_bge; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_bru_isa_bltu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_bru_isa_bgeu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_lb; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_lh; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_lw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_ld; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_lbu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_lhu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_lwu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_sb; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_sh; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_sw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_sd; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_fence; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_fence_i; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_sfence_vma; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_flw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_fsw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_fld; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_lsu_isa_fsd; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_csr_isa_rw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_csr_isa_rs; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_csr_isa_rc; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_csr_isa_rwi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_csr_isa_rsi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_csr_isa_rci; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_mul; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_mulh; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_mulhsu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_mulhu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_div; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_divu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_rem; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_remu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_mulw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_divw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_divuw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_remw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_mul_isa_remuw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_s_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_d_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_0_param_is_rvc; // @[MultiPortFifo.scala 57:20]
  reg [38:0] rnm_stage_rnRspFifo_buf_0_param_pc; // @[MultiPortFifo.scala 57:20]
  reg [63:0] rnm_stage_rnRspFifo_buf_0_param_imm; // @[MultiPortFifo.scala 57:20]
  reg [4:0] rnm_stage_rnRspFifo_buf_0_param_raw_rs1; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_rnRspFifo_buf_0_phy_rs1; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_rnRspFifo_buf_0_phy_rs2; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_rnRspFifo_buf_0_phy_rs3; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_rnRspFifo_buf_0_phy_rd0; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_lui; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_auipc; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_addi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_addiw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_slti; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_sltiu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_xori; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_ori; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_andi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_slli; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_slliw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_srli; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_srliw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_srai; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_sraiw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_add; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_addw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_sub; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_subw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_sll; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_sllw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_slt; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_sltu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_xor; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_srl; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_srlw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_sra; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_sraw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_or; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_and; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_alu_isa_wfi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_bru_isa_jal; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_bru_isa_jalr; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_bru_isa_beq; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_bru_isa_bne; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_bru_isa_blt; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_bru_isa_bge; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_bru_isa_bltu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_bru_isa_bgeu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_lb; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_lh; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_lw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_ld; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_lbu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_lhu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_lwu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_sb; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_sh; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_sw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_sd; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_fence; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_fence_i; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_sfence_vma; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_flw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_fsw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_fld; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_lsu_isa_fsd; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_csr_isa_rw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_csr_isa_rs; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_csr_isa_rc; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_csr_isa_rwi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_csr_isa_rsi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_csr_isa_rci; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_mul; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_mulh; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_mulhsu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_mulhu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_div; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_divu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_rem; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_remu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_mulw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_divw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_divuw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_remw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_mul_isa_remuw; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_w; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_s_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_d_s; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_d; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_1_param_is_rvc; // @[MultiPortFifo.scala 57:20]
  reg [38:0] rnm_stage_rnRspFifo_buf_1_param_pc; // @[MultiPortFifo.scala 57:20]
  reg [63:0] rnm_stage_rnRspFifo_buf_1_param_imm; // @[MultiPortFifo.scala 57:20]
  reg [4:0] rnm_stage_rnRspFifo_buf_1_param_raw_rs1; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_rnRspFifo_buf_1_phy_rs1; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_rnRspFifo_buf_1_phy_rs2; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_rnRspFifo_buf_1_phy_rs3; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_rnRspFifo_buf_1_phy_rd0; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_rnRspFifo_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  rnm_stage_rnRspFifo_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rnm_stage_rnRspFifo_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  rnm_stage_rnRspFifo_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] rnm_stage_rnRspFifo__io_enq_0_ready_T = {{1'd0}, rnm_stage_rnRspFifo_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  rnm_stage_rnRspFifo__io_enq_0_ready_T_1 = rnm_stage_rnRspFifo__io_enq_0_ready_T[0]; // @[MultiPortFifo.scala 64:78]
  wire  rnm_stage_rnRspFifo__GEN_1 = rnm_stage_rnRspFifo__io_enq_0_ready_T_1 ? rnm_stage_rnRspFifo_buf_valid_1 :
    rnm_stage_rnRspFifo_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] rnm_stage_rnRspFifo__io_deq_0_valid_T = {{1'd0}, rnm_stage_rnRspFifo_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  rnm_stage_rnRspFifo__io_deq_0_valid_T_1 = rnm_stage_rnRspFifo__io_deq_0_valid_T[0]; // @[MultiPortFifo.scala 65:78]
  wire  rnm_stage_rnRspFifo__T = rnm_stage_rnRspFifo_io_enq_0_ready & rnm_stage_rnRspFifo_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  rnm_stage_rnRspFifo__GEN_4 = ~rnm_stage_rnRspFifo__io_enq_0_ready_T_1 | rnm_stage_rnRspFifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  rnm_stage_rnRspFifo__GEN_5 = rnm_stage_rnRspFifo__io_enq_0_ready_T_1 | rnm_stage_rnRspFifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  rnm_stage_rnRspFifo__GEN_6 = rnm_stage_rnRspFifo__T ? rnm_stage_rnRspFifo__GEN_4 :
    rnm_stage_rnRspFifo_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  rnm_stage_rnRspFifo__GEN_7 = rnm_stage_rnRspFifo__T ? rnm_stage_rnRspFifo__GEN_5 :
    rnm_stage_rnRspFifo_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  rnm_stage_rnRspFifo__T_1 = rnm_stage_rnRspFifo_io_deq_0_ready & rnm_stage_rnRspFifo_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  rnm_stage_rnRspFifo__rd_ptr_T_2 = rnm_stage_rnRspFifo_rd_ptr + rnm_stage_rnRspFifo__T_1; // @[MultiPortFifo.scala 106:26]
  wire  rnm_stage_rnRspFifo__wr_ptr_T_2 = rnm_stage_rnRspFifo_wr_ptr + rnm_stage_rnRspFifo__T; // @[MultiPortFifo.scala 107:26]
  wire  rnm_stage_rnRspFifo__T_3 = ~rnm_stage_rnRspFifo_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  rnm_stage_rnRspFifo__T_4 = rnm_stage_rnRspFifo_io_enq_0_valid & rnm_stage_rnRspFifo__T_3; // @[MultiPortFifo.scala 161:44]
  wire  rnm_stage_rnRspFifo__T_7 = ~rnm_stage_rnRspFifo__T_4; // @[MultiPortFifo.scala 161:15]
  wire  rnm_stage_rnRspFifo__T_9 = ~rnm_stage_rnRspFifo_reset; // @[MultiPortFifo.scala 161:13]
  wire  rnm_stage_rnRspFifo__T_10 = ~rnm_stage_rnRspFifo__T_7; // @[MultiPortFifo.scala 161:13]
  wire  rnm_stage_rnRspFifo__T_12 = ~rnm_stage_rnRspFifo_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  rnm_stage_rnRspFifo__T_13 = rnm_stage_rnRspFifo_io_deq_0_valid & rnm_stage_rnRspFifo__T_12; // @[MultiPortFifo.scala 164:44]
  wire  rnm_stage_rnRspFifo__T_16 = ~rnm_stage_rnRspFifo__T_13; // @[MultiPortFifo.scala 164:15]
  wire  rnm_stage_rnRspFifo__T_19 = ~rnm_stage_rnRspFifo__T_16; // @[MultiPortFifo.scala 164:13]
  wire  rnm_stage_reOrder_fifo_i_clock;
  wire  rnm_stage_reOrder_fifo_i_reset;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_ready;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_valid;
  wire [38:0] rnm_stage_reOrder_fifo_i_io_enq_0_bits_pc;
  wire [4:0] rnm_stage_reOrder_fifo_i_io_enq_0_bits_rd0_raw;
  wire [5:0] rnm_stage_reOrder_fifo_i_io_enq_0_bits_rd0_phy;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_branch;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_jalr;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_lu;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_su;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_amo;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fence_i;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_sfence_vma;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_wfi;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_csr;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fpu;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fcsr;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_xcmm;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fcmm;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_ecall;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_ebreak;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_mret;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_sret;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_dret;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_is_access_fault;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_is_paging_fault;
  wire  rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_illeage;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_ready;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_valid;
  wire [38:0] rnm_stage_reOrder_fifo_i_io_deq_0_bits_pc;
  wire [4:0] rnm_stage_reOrder_fifo_i_io_deq_0_bits_rd0_raw;
  wire [5:0] rnm_stage_reOrder_fifo_i_io_deq_0_bits_rd0_phy;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_branch;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_jalr;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_lu;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_su;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_amo;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fence_i;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_sfence_vma;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_wfi;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_csr;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fpu;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fcsr;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_xcmm;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fcmm;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_ecall;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_ebreak;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_mret;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_sret;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_dret;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_is_access_fault;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_is_paging_fault;
  wire  rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_illeage;
  reg [38:0] rnm_stage_reOrder_fifo_i_buf_0_pc; // @[MultiPortFifo.scala 57:20]
  reg [4:0] rnm_stage_reOrder_fifo_i_buf_0_rd0_raw; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_reOrder_fifo_i_buf_0_rd0_phy; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_branch; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_jalr; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_lu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_su; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_amo; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_fence_i; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_sfence_vma; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_wfi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_csr; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_fpu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_fcsr; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_xcmm; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_fcmm; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_privil_ecall; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_privil_ebreak; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_privil_mret; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_privil_sret; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_privil_dret; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_privil_is_access_fault; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_privil_is_paging_fault; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_0_is_illeage; // @[MultiPortFifo.scala 57:20]
  reg [38:0] rnm_stage_reOrder_fifo_i_buf_1_pc; // @[MultiPortFifo.scala 57:20]
  reg [4:0] rnm_stage_reOrder_fifo_i_buf_1_rd0_raw; // @[MultiPortFifo.scala 57:20]
  reg [5:0] rnm_stage_reOrder_fifo_i_buf_1_rd0_phy; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_branch; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_jalr; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_lu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_su; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_amo; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_fence_i; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_sfence_vma; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_wfi; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_csr; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_fpu; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_fcsr; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_xcmm; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_fcmm; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_privil_ecall; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_privil_ebreak; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_privil_mret; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_privil_sret; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_privil_dret; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_privil_is_access_fault; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_privil_is_paging_fault; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_1_is_illeage; // @[MultiPortFifo.scala 57:20]
  reg  rnm_stage_reOrder_fifo_i_buf_valid_0; // @[MultiPortFifo.scala 58:30]
  reg  rnm_stage_reOrder_fifo_i_buf_valid_1; // @[MultiPortFifo.scala 58:30]
  reg  rnm_stage_reOrder_fifo_i_rd_ptr; // @[MultiPortFifo.scala 60:27]
  reg  rnm_stage_reOrder_fifo_i_wr_ptr; // @[MultiPortFifo.scala 61:27]
  wire [1:0] rnm_stage_reOrder_fifo_i__io_enq_0_ready_T = {{1'd0}, rnm_stage_reOrder_fifo_i_wr_ptr}; // @[MultiPortFifo.scala 64:78]
  wire  rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1 = rnm_stage_reOrder_fifo_i__io_enq_0_ready_T[0]; // @[MultiPortFifo.scala 64:78]
  wire  rnm_stage_reOrder_fifo_i__GEN_1 = rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_valid_1 : rnm_stage_reOrder_fifo_i_buf_valid_0; // @[MultiPortFifo.scala 64:{94,94}]
  wire [1:0] rnm_stage_reOrder_fifo_i__io_deq_0_valid_T = {{1'd0}, rnm_stage_reOrder_fifo_i_rd_ptr}; // @[MultiPortFifo.scala 65:78]
  wire  rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T[0]; // @[MultiPortFifo.scala 65:78]
  wire  rnm_stage_reOrder_fifo_i__T = rnm_stage_reOrder_fifo_i_io_enq_0_ready & rnm_stage_reOrder_fifo_i_io_enq_0_valid; // @[Decoupled.scala 52:35]
  wire  rnm_stage_reOrder_fifo_i__GEN_4 = ~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1 |
    rnm_stage_reOrder_fifo_i_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  rnm_stage_reOrder_fifo_i__GEN_5 = rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1 |
    rnm_stage_reOrder_fifo_i_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:{57,57}]
  wire  rnm_stage_reOrder_fifo_i__GEN_6 = rnm_stage_reOrder_fifo_i__T ? rnm_stage_reOrder_fifo_i__GEN_4 :
    rnm_stage_reOrder_fifo_i_buf_valid_0; // @[MultiPortFifo.scala 58:30 97:34]
  wire  rnm_stage_reOrder_fifo_i__GEN_7 = rnm_stage_reOrder_fifo_i__T ? rnm_stage_reOrder_fifo_i__GEN_5 :
    rnm_stage_reOrder_fifo_i_buf_valid_1; // @[MultiPortFifo.scala 58:30 97:34]
  wire  rnm_stage_reOrder_fifo_i__T_1 = rnm_stage_reOrder_fifo_i_io_deq_0_ready &
    rnm_stage_reOrder_fifo_i_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  rnm_stage_reOrder_fifo_i__rd_ptr_T_2 = rnm_stage_reOrder_fifo_i_rd_ptr + rnm_stage_reOrder_fifo_i__T_1; // @[MultiPortFifo.scala 106:26]
  wire  rnm_stage_reOrder_fifo_i__wr_ptr_T_2 = rnm_stage_reOrder_fifo_i_wr_ptr + rnm_stage_reOrder_fifo_i__T; // @[MultiPortFifo.scala 107:26]
  wire  rnm_stage_reOrder_fifo_i__T_3 = ~rnm_stage_reOrder_fifo_i_io_enq_0_valid; // @[MultiPortFifo.scala 161:63]
  wire  rnm_stage_reOrder_fifo_i__T_4 = rnm_stage_reOrder_fifo_i_io_enq_0_valid & rnm_stage_reOrder_fifo_i__T_3; // @[MultiPortFifo.scala 161:44]
  wire  rnm_stage_reOrder_fifo_i__T_7 = ~rnm_stage_reOrder_fifo_i__T_4; // @[MultiPortFifo.scala 161:15]
  wire  rnm_stage_reOrder_fifo_i__T_9 = ~rnm_stage_reOrder_fifo_i_reset; // @[MultiPortFifo.scala 161:13]
  wire  rnm_stage_reOrder_fifo_i__T_10 = ~rnm_stage_reOrder_fifo_i__T_7; // @[MultiPortFifo.scala 161:13]
  wire  rnm_stage_reOrder_fifo_i__T_12 = ~rnm_stage_reOrder_fifo_i_io_deq_0_valid; // @[MultiPortFifo.scala 164:63]
  wire  rnm_stage_reOrder_fifo_i__T_13 = rnm_stage_reOrder_fifo_i_io_deq_0_valid & rnm_stage_reOrder_fifo_i__T_12; // @[MultiPortFifo.scala 164:44]
  wire  rnm_stage_reOrder_fifo_i__T_16 = ~rnm_stage_reOrder_fifo_i__T_13; // @[MultiPortFifo.scala 164:15]
  wire  rnm_stage_reOrder_fifo_i__T_19 = ~rnm_stage_reOrder_fifo_i__T_16; // @[MultiPortFifo.scala 164:13]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T = rnm_stage_io_rnReq_0_ready & rnm_stage_io_rnReq_0_valid; // @[Decoupled.scala 52:35]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_1 = rnm_stage_io_rnReq_0_bits_privil_isa_ecall |
    rnm_stage_io_rnReq_0_bits_privil_isa_ebreak; // @[riscv_isa.scala 248:11]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_2 = rnm_stage__rnRspReport_io_enq_0_valid_T_1 |
    rnm_stage_io_rnReq_0_bits_privil_isa_mret; // @[riscv_isa.scala 248:20]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_3 = rnm_stage__rnRspReport_io_enq_0_valid_T_2 |
    rnm_stage_io_rnReq_0_bits_privil_isa_uret; // @[riscv_isa.scala 248:27]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_4 = rnm_stage__rnRspReport_io_enq_0_valid_T_3 |
    rnm_stage_io_rnReq_0_bits_privil_isa_sret; // @[riscv_isa.scala 248:34]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_5 = rnm_stage__rnRspReport_io_enq_0_valid_T_4 |
    rnm_stage_io_rnReq_0_bits_privil_isa_dret; // @[riscv_isa.scala 248:41]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_6 = rnm_stage__rnRspReport_io_enq_0_valid_T_5 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hfence_vvma; // @[riscv_isa.scala 248:48]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_7 = rnm_stage__rnRspReport_io_enq_0_valid_T_6 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hfence_gvma; // @[riscv_isa.scala 248:62]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_8 = rnm_stage__rnRspReport_io_enq_0_valid_T_7 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlv_b; // @[riscv_isa.scala 248:76]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_9 = rnm_stage__rnRspReport_io_enq_0_valid_T_8 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlv_bu; // @[riscv_isa.scala 248:84]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_10 = rnm_stage__rnRspReport_io_enq_0_valid_T_9 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlv_h; // @[riscv_isa.scala 248:93]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_11 = rnm_stage__rnRspReport_io_enq_0_valid_T_10 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlv_hu; // @[riscv_isa.scala 248:101]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_12 = rnm_stage__rnRspReport_io_enq_0_valid_T_11 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlvx_hu; // @[riscv_isa.scala 248:110]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_13 = rnm_stage__rnRspReport_io_enq_0_valid_T_12 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlv_w; // @[riscv_isa.scala 248:120]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_14 = rnm_stage__rnRspReport_io_enq_0_valid_T_13 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlvx_wu; // @[riscv_isa.scala 248:128]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_15 = rnm_stage__rnRspReport_io_enq_0_valid_T_14 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hsv_b; // @[riscv_isa.scala 248:138]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_16 = rnm_stage__rnRspReport_io_enq_0_valid_T_15 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hsv_h; // @[riscv_isa.scala 248:146]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_17 = rnm_stage__rnRspReport_io_enq_0_valid_T_16 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hsv_w; // @[riscv_isa.scala 248:154]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_18 = rnm_stage__rnRspReport_io_enq_0_valid_T_17 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlv_wu; // @[riscv_isa.scala 248:162]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_19 = rnm_stage__rnRspReport_io_enq_0_valid_T_18 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hlv_d; // @[riscv_isa.scala 248:171]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_20 = rnm_stage__rnRspReport_io_enq_0_valid_T_19 |
    rnm_stage_io_rnReq_0_bits_privil_isa_hsv_d; // @[riscv_isa.scala 248:179]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_21 = rnm_stage__rnRspReport_io_enq_0_valid_T_20 |
    rnm_stage_io_rnReq_0_bits_privil_isa_is_access_fault; // @[riscv_isa.scala 248:187]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_22 = rnm_stage__rnRspReport_io_enq_0_valid_T_21 |
    rnm_stage_io_rnReq_0_bits_privil_isa_is_paging_fault; // @[riscv_isa.scala 249:21]
  wire  rnm_stage__rnRspReport_io_enq_0_valid_T_23 = ~rnm_stage__rnRspReport_io_enq_0_valid_T_22; // @[Rename.scala 57:55]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T = rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_s |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_s; // @[riscv_isa.scala 514:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_1 = rnm_stage__rnRspReport_io_enq_0_bits_T |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_s; // @[riscv_isa.scala 514:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_2 = rnm_stage__rnRspReport_io_enq_0_bits_T_1 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_s; // @[riscv_isa.scala 514:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_3 = rnm_stage__rnRspReport_io_enq_0_bits_T_2 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_s; // @[riscv_isa.scala 514:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_4 = rnm_stage__rnRspReport_io_enq_0_bits_T_3 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_s; // @[riscv_isa.scala 514:61]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_5 = rnm_stage__rnRspReport_io_enq_0_bits_T_4 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_s; // @[riscv_isa.scala 514:73]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_6 = rnm_stage__rnRspReport_io_enq_0_bits_T_5 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_s; // @[riscv_isa.scala 514:85]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_7 = rnm_stage__rnRspReport_io_enq_0_bits_T_6 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_s; // @[riscv_isa.scala 514:97]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_8 = rnm_stage__rnRspReport_io_enq_0_bits_T_7 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_d; // @[riscv_isa.scala 514:109]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_9 = rnm_stage__rnRspReport_io_enq_0_bits_T_8 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_d; // @[riscv_isa.scala 515:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_10 = rnm_stage__rnRspReport_io_enq_0_bits_T_9 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_d; // @[riscv_isa.scala 515:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_11 = rnm_stage__rnRspReport_io_enq_0_bits_T_10 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_d; // @[riscv_isa.scala 515:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_12 = rnm_stage__rnRspReport_io_enq_0_bits_T_11 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_d; // @[riscv_isa.scala 515:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_13 = rnm_stage__rnRspReport_io_enq_0_bits_T_12 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_d; // @[riscv_isa.scala 515:61]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_14 = rnm_stage__rnRspReport_io_enq_0_bits_T_13 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_d; // @[riscv_isa.scala 515:73]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_15 = rnm_stage__rnRspReport_io_enq_0_bits_T_14 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_d; // @[riscv_isa.scala 515:85]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_16 = rnm_stage__rnRspReport_io_enq_0_bits_T_15 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_d; // @[riscv_isa.scala 515:97]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_17 = rnm_stage__rnRspReport_io_enq_0_bits_T_16 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_s; // @[riscv_isa.scala 515:109]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_18 = rnm_stage__rnRspReport_io_enq_0_bits_T_17 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_s; // @[riscv_isa.scala 516:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_19 = rnm_stage__rnRspReport_io_enq_0_bits_T_18 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_s; // @[riscv_isa.scala 516:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_20 = rnm_stage__rnRspReport_io_enq_0_bits_T_19 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_d; // @[riscv_isa.scala 516:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_21 = rnm_stage__rnRspReport_io_enq_0_bits_T_20 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_d; // @[riscv_isa.scala 516:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_22 = rnm_stage__rnRspReport_io_enq_0_bits_T_21 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_d; // @[riscv_isa.scala 516:61]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_23 = rnm_stage__rnRspReport_io_enq_0_bits_T_22 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_s; // @[riscv_isa.scala 516:73]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_24 = rnm_stage__rnRspReport_io_enq_0_bits_T_23 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_s; // @[riscv_isa.scala 517:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_25 = rnm_stage__rnRspReport_io_enq_0_bits_T_24 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_d; // @[riscv_isa.scala 517:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_26 = rnm_stage__rnRspReport_io_enq_0_bits_T_25 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_d; // @[riscv_isa.scala 517:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_27 = rnm_stage__rnRspReport_io_enq_0_bits_T_26 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_feq_s; // @[riscv_isa.scala 517:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_28 = rnm_stage__rnRspReport_io_enq_0_bits_T_27 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_flt_s; // @[riscv_isa.scala 518:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_29 = rnm_stage__rnRspReport_io_enq_0_bits_T_28 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fle_s; // @[riscv_isa.scala 518:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_30 = rnm_stage__rnRspReport_io_enq_0_bits_T_29 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_feq_d; // @[riscv_isa.scala 518:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_31 = rnm_stage__rnRspReport_io_enq_0_bits_T_30 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_flt_d; // @[riscv_isa.scala 518:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_32 = rnm_stage__rnRspReport_io_enq_0_bits_T_31 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fle_d; // @[riscv_isa.scala 518:61]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_33 = rnm_stage__rnRspReport_io_enq_0_bits_T_32 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_s; // @[riscv_isa.scala 518:73]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_34 = rnm_stage__rnRspReport_io_enq_0_bits_T_33 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_d; // @[riscv_isa.scala 519:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_35 = rnm_stage__rnRspReport_io_enq_0_bits_T_34 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_w; // @[riscv_isa.scala 519:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_36 = rnm_stage__rnRspReport_io_enq_0_bits_T_35 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_w_x; // @[riscv_isa.scala 520:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_37 = rnm_stage__rnRspReport_io_enq_0_bits_T_36 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_d; // @[riscv_isa.scala 520:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_38 = rnm_stage__rnRspReport_io_enq_0_bits_T_37 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_d_x; // @[riscv_isa.scala 520:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_39 = rnm_stage__rnRspReport_io_enq_0_bits_T_38 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_w; // @[riscv_isa.scala 520:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_40 = rnm_stage__rnRspReport_io_enq_0_bits_T_39 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_wu; // @[riscv_isa.scala 521:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_41 = rnm_stage__rnRspReport_io_enq_0_bits_T_40 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_s; // @[riscv_isa.scala 521:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_42 = rnm_stage__rnRspReport_io_enq_0_bits_T_41 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_s; // @[riscv_isa.scala 521:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_43 = rnm_stage__rnRspReport_io_enq_0_bits_T_42 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_l; // @[riscv_isa.scala 521:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_44 = rnm_stage__rnRspReport_io_enq_0_bits_T_43 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_lu; // @[riscv_isa.scala 522:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_45 = rnm_stage__rnRspReport_io_enq_0_bits_T_44 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_d; // @[riscv_isa.scala 522:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_46 = rnm_stage__rnRspReport_io_enq_0_bits_T_45 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_s; // @[riscv_isa.scala 522:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_47 = rnm_stage__rnRspReport_io_enq_0_bits_T_46 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_d; // @[riscv_isa.scala 522:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_48 = rnm_stage__rnRspReport_io_enq_0_bits_T_47 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_d; // @[riscv_isa.scala 523:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_49 = rnm_stage__rnRspReport_io_enq_0_bits_T_48 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_w; // @[riscv_isa.scala 523:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_50 = rnm_stage__rnRspReport_io_enq_0_bits_T_49 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_wu; // @[riscv_isa.scala 523:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_51 = rnm_stage__rnRspReport_io_enq_0_bits_T_50 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_d; // @[riscv_isa.scala 523:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_52 = rnm_stage__rnRspReport_io_enq_0_bits_T_51 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_d; // @[riscv_isa.scala 523:61]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_53 = rnm_stage__rnRspReport_io_enq_0_bits_T_52 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_l; // @[riscv_isa.scala 523:73]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_54 = rnm_stage__rnRspReport_io_enq_0_bits_T_53 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_lu; // @[riscv_isa.scala 524:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_55 = rnm_stage__rnRspReport_io_enq_0_bits_T_54 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_s; // @[riscv_isa.scala 524:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_56 = rnm_stage__rnRspReport_io_enq_0_bits_T_55 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_s; // @[riscv_isa.scala 524:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_57 = rnm_stage__rnRspReport_io_enq_0_bits_T_56 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rw; // @[riscv_isa.scala 524:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_58 = rnm_stage__rnRspReport_io_enq_0_bits_T_57 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rs; // @[riscv_isa.scala 525:13]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_59 = rnm_stage__rnRspReport_io_enq_0_bits_T_58 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rc; // @[riscv_isa.scala 525:25]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_60 = rnm_stage__rnRspReport_io_enq_0_bits_T_59 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rwi; // @[riscv_isa.scala 525:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_61 = rnm_stage__rnRspReport_io_enq_0_bits_T_60 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rsi; // @[riscv_isa.scala 525:49]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_62 = rnm_stage__rnRspReport_io_enq_0_bits_T_61 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rci; // @[riscv_isa.scala 525:61]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_66 = rnm_stage__rnRspReport_io_enq_0_bits_T_2 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_d; // @[riscv_isa.scala 365:43]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_67 = rnm_stage__rnRspReport_io_enq_0_bits_T_66 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_d; // @[riscv_isa.scala 366:11]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_68 = rnm_stage__rnRspReport_io_enq_0_bits_T_67 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_d; // @[riscv_isa.scala 366:21]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_69 = rnm_stage__rnRspReport_io_enq_0_bits_T_68 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_d; // @[riscv_isa.scala 366:32]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_70 = rnm_stage__rnRspReport_io_enq_0_bits_T_69 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_s; // @[riscv_isa.scala 368:29]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_71 = rnm_stage__rnRspReport_io_enq_0_bits_T_70 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_s; // @[riscv_isa.scala 369:10]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_72 = rnm_stage__rnRspReport_io_enq_0_bits_T_71 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_s; // @[riscv_isa.scala 369:19]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_73 = rnm_stage__rnRspReport_io_enq_0_bits_T_72 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_s; // @[riscv_isa.scala 369:28]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_74 = rnm_stage__rnRspReport_io_enq_0_bits_T_73 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_s; // @[riscv_isa.scala 369:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_75 = rnm_stage__rnRspReport_io_enq_0_bits_T_74 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_s; // @[riscv_isa.scala 369:47]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_76 = rnm_stage__rnRspReport_io_enq_0_bits_T_75 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_s; // @[riscv_isa.scala 370:11]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_77 = rnm_stage__rnRspReport_io_enq_0_bits_T_76 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_s; // @[riscv_isa.scala 370:22]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_78 = rnm_stage__rnRspReport_io_enq_0_bits_T_77 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_d; // @[riscv_isa.scala 370:33]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_79 = rnm_stage__rnRspReport_io_enq_0_bits_T_78 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_d; // @[riscv_isa.scala 370:43]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_80 = rnm_stage__rnRspReport_io_enq_0_bits_T_79 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_d; // @[riscv_isa.scala 370:54]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_81 = rnm_stage__rnRspReport_io_enq_0_bits_T_80 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_s; // @[riscv_isa.scala 370:65]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_82 = rnm_stage__rnRspReport_io_enq_0_bits_T_81 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_s; // @[riscv_isa.scala 371:10]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_83 = rnm_stage__rnRspReport_io_enq_0_bits_T_82 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_d; // @[riscv_isa.scala 371:19]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_84 = rnm_stage__rnRspReport_io_enq_0_bits_T_83 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_d; // @[riscv_isa.scala 371:28]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_85 = rnm_stage__rnRspReport_io_enq_0_bits_T_84 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_feq_s; // @[riscv_isa.scala 371:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_86 = rnm_stage__rnRspReport_io_enq_0_bits_T_85 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_flt_s; // @[riscv_isa.scala 372:9]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_87 = rnm_stage__rnRspReport_io_enq_0_bits_T_86 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fle_s; // @[riscv_isa.scala 372:17]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_88 = rnm_stage__rnRspReport_io_enq_0_bits_T_87 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_feq_d; // @[riscv_isa.scala 372:24]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_89 = rnm_stage__rnRspReport_io_enq_0_bits_T_88 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_flt_d; // @[riscv_isa.scala 372:32]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_90 = rnm_stage__rnRspReport_io_enq_0_bits_T_89 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fle_d; // @[riscv_isa.scala 372:40]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_91 = rnm_stage__rnRspReport_io_enq_0_bits_T_90 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_d; // @[riscv_isa.scala 372:48]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_92 = rnm_stage__rnRspReport_io_enq_0_bits_T_91 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_d; // @[riscv_isa.scala 373:10]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_93 = rnm_stage__rnRspReport_io_enq_0_bits_T_92 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_d; // @[riscv_isa.scala 373:19]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_94 = rnm_stage__rnRspReport_io_enq_0_bits_T_93 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_d; // @[riscv_isa.scala 373:28]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_95 = rnm_stage__rnRspReport_io_enq_0_bits_T_94 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_d; // @[riscv_isa.scala 373:37]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_96 = rnm_stage__rnRspReport_io_enq_0_bits_T_95 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rw; // @[riscv_isa.scala 373:47]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_97 = rnm_stage__rnRspReport_io_enq_0_bits_T_96 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rs; // @[riscv_isa.scala 374:11]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_98 = rnm_stage__rnRspReport_io_enq_0_bits_T_97 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rc; // @[riscv_isa.scala 374:21]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_99 = rnm_stage__rnRspReport_io_enq_0_bits_T_98 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rwi; // @[riscv_isa.scala 374:31]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_100 = rnm_stage__rnRspReport_io_enq_0_bits_T_99 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rsi; // @[riscv_isa.scala 374:42]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_101 = rnm_stage__rnRspReport_io_enq_0_bits_T_100 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rci; // @[riscv_isa.scala 374:53]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_102 = ~rnm_stage__rnRspReport_io_enq_0_bits_T_101; // @[Rename.scala 115:12]
  wire  rnm_stage__reg_phy_0_rs2_T_12 = rnm_stage__rnRspReport_io_enq_0_bits_T_74 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_d; // @[riscv_isa.scala 393:63]
  wire  rnm_stage__reg_phy_0_rs2_T_13 = rnm_stage__reg_phy_0_rs2_T_12 | rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_d; // @[riscv_isa.scala 394:15]
  wire  rnm_stage__reg_phy_0_rs2_T_14 = rnm_stage__reg_phy_0_rs2_T_13 | rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_d; // @[riscv_isa.scala 394:27]
  wire  rnm_stage__reg_phy_0_rs2_T_15 = rnm_stage__reg_phy_0_rs2_T_14 | rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_d; // @[riscv_isa.scala 394:39]
  wire  rnm_stage__reg_phy_0_rs2_T_16 = rnm_stage__reg_phy_0_rs2_T_15 | rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_d; // @[riscv_isa.scala 394:51]
  wire  rnm_stage__reg_phy_0_rs2_T_17 = rnm_stage__reg_phy_0_rs2_T_16 | rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_s; // @[riscv_isa.scala 394:63]
  wire  rnm_stage__reg_phy_0_rs2_T_18 = rnm_stage__reg_phy_0_rs2_T_17 | rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_s; // @[riscv_isa.scala 395:15]
  wire  rnm_stage__reg_phy_0_rs2_T_19 = rnm_stage__reg_phy_0_rs2_T_18 | rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_s; // @[riscv_isa.scala 395:27]
  wire  rnm_stage__reg_phy_0_rs2_T_20 = rnm_stage__reg_phy_0_rs2_T_19 | rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_d; // @[riscv_isa.scala 395:39]
  wire  rnm_stage__reg_phy_0_rs2_T_21 = rnm_stage__reg_phy_0_rs2_T_20 | rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_d; // @[riscv_isa.scala 396:15]
  wire  rnm_stage__reg_phy_0_rs2_T_22 = rnm_stage__reg_phy_0_rs2_T_21 | rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_d; // @[riscv_isa.scala 396:27]
  wire  rnm_stage__reg_phy_0_rs2_T_23 = rnm_stage__reg_phy_0_rs2_T_22 | rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_s; // @[riscv_isa.scala 396:39]
  wire  rnm_stage__reg_phy_0_rs2_T_24 = rnm_stage__reg_phy_0_rs2_T_23 | rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_s; // @[riscv_isa.scala 397:15]
  wire  rnm_stage__reg_phy_0_rs2_T_25 = rnm_stage__reg_phy_0_rs2_T_24 | rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_d; // @[riscv_isa.scala 397:27]
  wire  rnm_stage__reg_phy_0_rs2_T_26 = rnm_stage__reg_phy_0_rs2_T_25 | rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_d; // @[riscv_isa.scala 397:39]
  wire  rnm_stage__reg_phy_0_rs2_T_27 = rnm_stage__reg_phy_0_rs2_T_26 | rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_w; // @[riscv_isa.scala 397:51]
  wire  rnm_stage__reg_phy_0_rs2_T_28 = rnm_stage__reg_phy_0_rs2_T_27 | rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_d; // @[riscv_isa.scala 398:15]
  wire  rnm_stage__reg_phy_0_rs2_T_29 = rnm_stage__reg_phy_0_rs2_T_28 | rnm_stage_io_rnReq_0_bits_fpu_isa_feq_s; // @[riscv_isa.scala 398:27]
  wire  rnm_stage__reg_phy_0_rs2_T_30 = rnm_stage__reg_phy_0_rs2_T_29 | rnm_stage_io_rnReq_0_bits_fpu_isa_flt_s; // @[riscv_isa.scala 399:15]
  wire  rnm_stage__reg_phy_0_rs2_T_31 = rnm_stage__reg_phy_0_rs2_T_30 | rnm_stage_io_rnReq_0_bits_fpu_isa_fle_s; // @[riscv_isa.scala 399:27]
  wire  rnm_stage__reg_phy_0_rs2_T_32 = rnm_stage__reg_phy_0_rs2_T_31 | rnm_stage_io_rnReq_0_bits_fpu_isa_feq_d; // @[riscv_isa.scala 399:39]
  wire  rnm_stage__reg_phy_0_rs2_T_33 = rnm_stage__reg_phy_0_rs2_T_32 | rnm_stage_io_rnReq_0_bits_fpu_isa_flt_d; // @[riscv_isa.scala 400:15]
  wire  rnm_stage__reg_phy_0_rs2_T_34 = rnm_stage__reg_phy_0_rs2_T_33 | rnm_stage_io_rnReq_0_bits_fpu_isa_fle_d; // @[riscv_isa.scala 400:27]
  wire  rnm_stage__reg_phy_0_rs2_T_35 = rnm_stage__reg_phy_0_rs2_T_34 | rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_s; // @[riscv_isa.scala 400:39]
  wire  rnm_stage__reg_phy_0_rs2_T_36 = rnm_stage__reg_phy_0_rs2_T_35 | rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_d; // @[riscv_isa.scala 401:15]
  wire  rnm_stage__reg_phy_0_rs2_T_37 = rnm_stage__reg_phy_0_rs2_T_36 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_s; // @[riscv_isa.scala 401:27]
  wire  rnm_stage__reg_phy_0_rs2_T_38 = rnm_stage__reg_phy_0_rs2_T_37 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_s; // @[riscv_isa.scala 402:15]
  wire  rnm_stage__reg_phy_0_rs2_T_39 = rnm_stage__reg_phy_0_rs2_T_38 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_s; // @[riscv_isa.scala 402:27]
  wire  rnm_stage__reg_phy_0_rs2_T_40 = rnm_stage__reg_phy_0_rs2_T_39 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_s; // @[riscv_isa.scala 402:39]
  wire  rnm_stage__reg_phy_0_rs2_T_41 = rnm_stage__reg_phy_0_rs2_T_40 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_d; // @[riscv_isa.scala 402:51]
  wire  rnm_stage__reg_phy_0_rs2_T_42 = rnm_stage__reg_phy_0_rs2_T_41 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_d; // @[riscv_isa.scala 403:15]
  wire  rnm_stage__reg_phy_0_rs2_T_43 = rnm_stage__reg_phy_0_rs2_T_42 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_d; // @[riscv_isa.scala 403:27]
  wire  rnm_stage__reg_phy_0_rs2_T_44 = rnm_stage__reg_phy_0_rs2_T_43 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_d; // @[riscv_isa.scala 403:39]
  wire  rnm_stage__reg_phy_0_rs2_T_45 = rnm_stage__reg_phy_0_rs2_T_44 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_d; // @[riscv_isa.scala 403:51]
  wire  rnm_stage__reg_phy_0_rs2_T_46 = rnm_stage__reg_phy_0_rs2_T_45 | rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_s; // @[riscv_isa.scala 404:15]
  wire  rnm_stage__reg_phy_0_rs2_T_47 = rnm_stage_io_rnReq_0_bits_lsu_isa_fsw | rnm_stage_io_rnReq_0_bits_lsu_isa_fsd; // @[riscv_isa.scala 164:20]
  wire  rnm_stage__reg_phy_0_rs2_T_48 = rnm_stage__reg_phy_0_rs2_T_46 | rnm_stage__reg_phy_0_rs2_T_47; // @[Rename.scala 76:59]
  wire [5:0] rnm_stage__reg_phy_0_rs2_T_49 = rnm_stage__reg_phy_0_rs2_T_48 ? rnm_stage_io_fLookup_0_rsp_rs2 :
    rnm_stage_io_xLookup_0_rsp_rs2; // @[Rename.scala 76:26]
  wire [5:0] rnm_stage__GEN_0 = rnm_stage__rnRspReport_io_enq_0_bits_T_102 ? 6'h21 : rnm_stage__reg_phy_0_rs2_T_49; // @[Rename.scala 112:20 115:{37,51}]
  wire  rnm_stage__rnRspReport_io_enq_0_bits_T_110 = ~rnm_stage__rnRspReport_io_enq_0_bits_T_69; // @[Rename.scala 116:12]
  wire [5:0] rnm_stage__reg_phy_0_rs3_T_47 = rnm_stage__reg_phy_0_rs2_T_46 ? rnm_stage_io_fLookup_0_rsp_rs3 : 6'h21; // @[Rename.scala 77:26]
  wire [5:0] rnm_stage__GEN_1 = rnm_stage__rnRspReport_io_enq_0_bits_T_110 ? 6'h21 : rnm_stage__reg_phy_0_rs3_T_47; // @[Rename.scala 112:20 116:{39,53}]
  wire  rnm_stage__io_xRename_0_req_valid_T_1 = rnm_stage_io_rnReq_0_bits_lsu_isa_flw |
    rnm_stage_io_rnReq_0_bits_lsu_isa_fld; // @[riscv_isa.scala 166:20]
  wire  rnm_stage__io_xRename_0_req_valid_T_29 = rnm_stage__rnRspReport_io_enq_0_bits_T_26 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_w; // @[riscv_isa.scala 418:39]
  wire  rnm_stage__io_xRename_0_req_valid_T_30 = rnm_stage__io_xRename_0_req_valid_T_29 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_wu; // @[riscv_isa.scala 419:14]
  wire  rnm_stage__io_xRename_0_req_valid_T_31 = rnm_stage__io_xRename_0_req_valid_T_30 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_w; // @[riscv_isa.scala 419:26]
  wire  rnm_stage__io_xRename_0_req_valid_T_32 = rnm_stage__io_xRename_0_req_valid_T_31 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_wu; // @[riscv_isa.scala 419:37]
  wire  rnm_stage__io_xRename_0_req_valid_T_33 = rnm_stage__io_xRename_0_req_valid_T_32 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_l; // @[riscv_isa.scala 419:49]
  wire  rnm_stage__io_xRename_0_req_valid_T_34 = rnm_stage__io_xRename_0_req_valid_T_33 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_lu; // @[riscv_isa.scala 420:14]
  wire  rnm_stage__io_xRename_0_req_valid_T_35 = rnm_stage__io_xRename_0_req_valid_T_34 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_l; // @[riscv_isa.scala 420:26]
  wire  rnm_stage__io_xRename_0_req_valid_T_36 = rnm_stage__io_xRename_0_req_valid_T_35 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_lu; // @[riscv_isa.scala 420:37]
  wire  rnm_stage__io_xRename_0_req_valid_T_37 = rnm_stage__io_xRename_0_req_valid_T_36 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_d; // @[riscv_isa.scala 420:49]
  wire  rnm_stage__io_xRename_0_req_valid_T_38 = rnm_stage__io_xRename_0_req_valid_T_37 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_s; // @[riscv_isa.scala 421:14]
  wire  rnm_stage__io_xRename_0_req_valid_T_39 = rnm_stage__io_xRename_0_req_valid_T_38 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_w_x; // @[riscv_isa.scala 421:25]
  wire  rnm_stage__io_xRename_0_req_valid_T_40 = rnm_stage__io_xRename_0_req_valid_T_39 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_d_x; // @[riscv_isa.scala 422:13]
  wire  rnm_stage__io_xRename_0_req_valid_T_41 = rnm_stage__io_xRename_0_req_valid_T_1 |
    rnm_stage__io_xRename_0_req_valid_T_40; // @[riscv_isa.scala 794:20]
  wire  rnm_stage__io_xRename_0_req_valid_T_42 = ~rnm_stage__io_xRename_0_req_valid_T_41; // @[riscv_isa.scala 800:16]
  wire  rnm_stage__reg_phy_0_rd0_T = rnm_stage_io_fRename_0_req_ready & rnm_stage_io_fRename_0_req_valid; // @[Decoupled.scala 52:35]
  wire  rnm_stage__reg_phy_0_rd0_T_1 = rnm_stage_io_xRename_0_req_ready & rnm_stage_io_xRename_0_req_valid; // @[Decoupled.scala 52:35]
  wire [5:0] rnm_stage__reg_phy_0_rd0_T_2 = rnm_stage__reg_phy_0_rd0_T ? rnm_stage_io_fRename_0_rsp_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] rnm_stage__reg_phy_0_rd0_T_3 = rnm_stage__reg_phy_0_rd0_T_1 ? rnm_stage_io_xRename_0_rsp_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire [1:0] rnm_stage__T_2 = rnm_stage__reg_phy_0_rd0_T + rnm_stage__reg_phy_0_rd0_T_1; // @[Bitwise.scala 51:90]
  wire  rnm_stage__T_4 = rnm_stage__T_2 <= 2'h1; // @[Rename.scala 84:105]
  wire  rnm_stage__T_6 = ~rnm_stage_reset; // @[Rename.scala 84:40]
  wire  rnm_stage__T_7 = ~rnm_stage__T_4; // @[Rename.scala 84:40]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_branch_T = rnm_stage_io_rnReq_0_bits_bru_isa_beq |
    rnm_stage_io_rnReq_0_bits_bru_isa_bne; // @[riscv_isa.scala 93:23]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_branch_T_1 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_branch_T | rnm_stage_io_rnReq_0_bits_bru_isa_blt; // @[riscv_isa.scala 93:29]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_branch_T_2 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_branch_T_1 | rnm_stage_io_rnReq_0_bits_bru_isa_bge; // @[riscv_isa.scala 93:35]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_branch_T_3 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_branch_T_2 | rnm_stage_io_rnReq_0_bits_bru_isa_bltu; // @[riscv_isa.scala 93:41]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T = rnm_stage_io_rnReq_0_bits_lsu_isa_lb |
    rnm_stage_io_rnReq_0_bits_lsu_isa_lh; // @[riscv_isa.scala 143:19]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_1 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T |
    rnm_stage_io_rnReq_0_bits_lsu_isa_lw; // @[riscv_isa.scala 143:24]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_2 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_1 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_ld; // @[riscv_isa.scala 143:29]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_3 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_2 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_lbu; // @[riscv_isa.scala 143:34]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_4 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_3 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_lhu; // @[riscv_isa.scala 143:40]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_5 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_4 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_lwu; // @[riscv_isa.scala 143:46]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_6 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_5 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_flw; // @[riscv_isa.scala 143:52]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_7 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_6 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_fld; // @[riscv_isa.scala 143:59]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_8 = rnm_stage_io_rnReq_0_bits_lsu_isa_lr_d |
    rnm_stage_io_rnReq_0_bits_lsu_isa_lr_w; // @[riscv_isa.scala 141:20]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_su_T = rnm_stage_io_rnReq_0_bits_lsu_isa_sb |
    rnm_stage_io_rnReq_0_bits_lsu_isa_sh; // @[riscv_isa.scala 144:19]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_su_T_1 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_su_T |
    rnm_stage_io_rnReq_0_bits_lsu_isa_sw; // @[riscv_isa.scala 144:24]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_su_T_2 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_su_T_1 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_sd; // @[riscv_isa.scala 144:29]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_su_T_3 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_su_T_2 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_fsw; // @[riscv_isa.scala 144:34]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T = rnm_stage_io_rnReq_0_bits_lsu_isa_amoswap_w |
    rnm_stage_io_rnReq_0_bits_lsu_isa_amoadd_w; // @[riscv_isa.scala 148:15]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_1 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T |
    rnm_stage_io_rnReq_0_bits_lsu_isa_amoxor_w; // @[riscv_isa.scala 148:26]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_2 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_1
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amoand_w; // @[riscv_isa.scala 148:37]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_3 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_2
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amoor_w; // @[riscv_isa.scala 148:48]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_4 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_3
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amomin_w; // @[riscv_isa.scala 148:58]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_5 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_4
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amomax_w; // @[riscv_isa.scala 148:69]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_6 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_5
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amominu_w; // @[riscv_isa.scala 148:80]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_7 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_6
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amomaxu_w; // @[riscv_isa.scala 148:92]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_8 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_7
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amoswap_d; // @[riscv_isa.scala 148:104]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_9 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_8
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amoadd_d; // @[riscv_isa.scala 148:116]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_10 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_9
     | rnm_stage_io_rnReq_0_bits_lsu_isa_amoxor_d; // @[riscv_isa.scala 148:127]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_11 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_10 | rnm_stage_io_rnReq_0_bits_lsu_isa_amoand_d; // @[riscv_isa.scala 148:138]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_12 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_11 | rnm_stage_io_rnReq_0_bits_lsu_isa_amoor_d; // @[riscv_isa.scala 148:149]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_13 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_12 | rnm_stage_io_rnReq_0_bits_lsu_isa_amomin_d; // @[riscv_isa.scala 148:159]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_14 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_13 | rnm_stage_io_rnReq_0_bits_lsu_isa_amomax_d; // @[riscv_isa.scala 148:170]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_15 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_14 | rnm_stage_io_rnReq_0_bits_lsu_isa_amominu_d; // @[riscv_isa.scala 148:181]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_16 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_15 | rnm_stage_io_rnReq_0_bits_lsu_isa_amomaxu_d; // @[riscv_isa.scala 148:193]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_17 = rnm_stage_io_rnReq_0_bits_lsu_isa_sc_d |
    rnm_stage_io_rnReq_0_bits_lsu_isa_sc_w; // @[riscv_isa.scala 140:20]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_18 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_16 | rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_17; // @[riscv_isa.scala 148:205]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T = rnm_stage_io_rnReq_0_bits_csr_isa_rw |
    rnm_stage_io_rnReq_0_bits_csr_isa_rs; // @[riscv_isa.scala 179:19]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_1 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T |
    rnm_stage_io_rnReq_0_bits_csr_isa_rc; // @[riscv_isa.scala 179:24]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_2 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_1
     | rnm_stage_io_rnReq_0_bits_csr_isa_rwi; // @[riscv_isa.scala 179:29]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_3 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_2
     | rnm_stage_io_rnReq_0_bits_csr_isa_rsi; // @[riscv_isa.scala 179:35]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_4 = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_3
     | rnm_stage_io_rnReq_0_bits_csr_isa_rci; // @[riscv_isa.scala 179:41]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_fpu_T_63 = rnm_stage_io_rnReq_0_bits_lsu_isa_flw |
    rnm_stage_io_rnReq_0_bits_lsu_isa_fsw; // @[riscv_isa.scala 168:20]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_fpu_T_64 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_fpu_T_63 | rnm_stage_io_rnReq_0_bits_lsu_isa_fld; // @[riscv_isa.scala 168:26]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_fpu_T_65 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_fpu_T_64 | rnm_stage_io_rnReq_0_bits_lsu_isa_fsd; // @[riscv_isa.scala 168:32]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T = rnm_stage_io_rnReq_0_bits_alu_isa_lui |
    rnm_stage_io_rnReq_0_bits_alu_isa_auipc; // @[riscv_isa.scala 78:20]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_1 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T | rnm_stage_io_rnReq_0_bits_alu_isa_addi; // @[riscv_isa.scala 78:28]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_2 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_1 | rnm_stage_io_rnReq_0_bits_alu_isa_addiw; // @[riscv_isa.scala 78:35]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_3 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_2 | rnm_stage_io_rnReq_0_bits_alu_isa_slti; // @[riscv_isa.scala 78:43]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_4 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_3 | rnm_stage_io_rnReq_0_bits_alu_isa_sltiu; // @[riscv_isa.scala 78:50]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_5 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_4 | rnm_stage_io_rnReq_0_bits_alu_isa_xori; // @[riscv_isa.scala 78:58]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_6 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_5 | rnm_stage_io_rnReq_0_bits_alu_isa_ori; // @[riscv_isa.scala 78:65]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_7 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_6 | rnm_stage_io_rnReq_0_bits_alu_isa_andi; // @[riscv_isa.scala 78:71]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_8 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_7 | rnm_stage_io_rnReq_0_bits_alu_isa_slli; // @[riscv_isa.scala 78:78]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_9 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_8 | rnm_stage_io_rnReq_0_bits_alu_isa_slliw; // @[riscv_isa.scala 78:85]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_10 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_9 | rnm_stage_io_rnReq_0_bits_alu_isa_srli; // @[riscv_isa.scala 78:93]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_11 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_10 | rnm_stage_io_rnReq_0_bits_alu_isa_srliw; // @[riscv_isa.scala 78:100]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_12 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_11 | rnm_stage_io_rnReq_0_bits_alu_isa_srai; // @[riscv_isa.scala 78:108]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_13 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_12 | rnm_stage_io_rnReq_0_bits_alu_isa_sraiw; // @[riscv_isa.scala 78:115]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_14 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_13 | rnm_stage_io_rnReq_0_bits_alu_isa_add; // @[riscv_isa.scala 78:123]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_15 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_14 | rnm_stage_io_rnReq_0_bits_alu_isa_addw; // @[riscv_isa.scala 78:129]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_16 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_15 | rnm_stage_io_rnReq_0_bits_alu_isa_sub; // @[riscv_isa.scala 78:136]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_17 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_16 | rnm_stage_io_rnReq_0_bits_alu_isa_subw; // @[riscv_isa.scala 78:142]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_18 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_17 | rnm_stage_io_rnReq_0_bits_alu_isa_sll; // @[riscv_isa.scala 78:149]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_19 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_18 | rnm_stage_io_rnReq_0_bits_alu_isa_sllw; // @[riscv_isa.scala 78:155]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_20 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_19 | rnm_stage_io_rnReq_0_bits_alu_isa_slt; // @[riscv_isa.scala 78:162]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_21 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_20 | rnm_stage_io_rnReq_0_bits_alu_isa_sltu; // @[riscv_isa.scala 78:168]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_22 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_21 | rnm_stage_io_rnReq_0_bits_alu_isa_xor; // @[riscv_isa.scala 78:175]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_23 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_22 | rnm_stage_io_rnReq_0_bits_alu_isa_srl; // @[riscv_isa.scala 78:181]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_24 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_23 | rnm_stage_io_rnReq_0_bits_alu_isa_srlw; // @[riscv_isa.scala 78:187]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_25 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_24 | rnm_stage_io_rnReq_0_bits_alu_isa_sra; // @[riscv_isa.scala 78:194]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_26 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_25 | rnm_stage_io_rnReq_0_bits_alu_isa_sraw; // @[riscv_isa.scala 78:200]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_27 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_26 | rnm_stage_io_rnReq_0_bits_alu_isa_or; // @[riscv_isa.scala 78:207]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_28 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_27 | rnm_stage_io_rnReq_0_bits_alu_isa_and; // @[riscv_isa.scala 78:212]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_29 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_28 | rnm_stage_io_rnReq_0_bits_alu_isa_wfi; // @[riscv_isa.scala 78:217]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_30 = rnm_stage_io_rnReq_0_bits_bru_isa_jal |
    rnm_stage_io_rnReq_0_bits_bru_isa_jalr; // @[riscv_isa.scala 92:20]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_31 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_30 | rnm_stage_io_rnReq_0_bits_bru_isa_beq; // @[riscv_isa.scala 92:27]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_32 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_31 | rnm_stage_io_rnReq_0_bits_bru_isa_bne; // @[riscv_isa.scala 92:33]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_33 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_32 | rnm_stage_io_rnReq_0_bits_bru_isa_blt; // @[riscv_isa.scala 92:39]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_34 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_33 | rnm_stage_io_rnReq_0_bits_bru_isa_bge; // @[riscv_isa.scala 92:45]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_35 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_34 | rnm_stage_io_rnReq_0_bits_bru_isa_bltu; // @[riscv_isa.scala 92:51]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_36 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_35 | rnm_stage_io_rnReq_0_bits_bru_isa_bgeu; // @[riscv_isa.scala 92:58]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_37 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_29 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_36; // @[riscv_isa.scala 801:37]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_44 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_5 | rnm_stage_io_rnReq_0_bits_lsu_isa_sb; // @[riscv_isa.scala 145:52]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_45 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_44 | rnm_stage_io_rnReq_0_bits_lsu_isa_sh; // @[riscv_isa.scala 145:57]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_46 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_45 | rnm_stage_io_rnReq_0_bits_lsu_isa_sw; // @[riscv_isa.scala 145:62]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_47 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_46 | rnm_stage_io_rnReq_0_bits_lsu_isa_sd; // @[riscv_isa.scala 145:67]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_50 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_17 | rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_8; // @[riscv_isa.scala 146:23]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_51 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_47 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_50; // @[riscv_isa.scala 151:23]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_71 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_51 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_18; // @[riscv_isa.scala 151:33]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_75 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_71 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_fpu_T_65; // @[riscv_isa.scala 151:42]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_76 = rnm_stage_io_rnReq_0_bits_lsu_isa_fence |
    rnm_stage_io_rnReq_0_bits_lsu_isa_fence_i; // @[riscv_isa.scala 150:24]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_77 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_76 | rnm_stage_io_rnReq_0_bits_lsu_isa_sfence_vma; // @[riscv_isa.scala 150:34]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_78 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_75 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_77; // @[riscv_isa.scala 151:51]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_79 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_37 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_78; // @[riscv_isa.scala 801:54]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_85 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_79 | rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_4
    ; // @[riscv_isa.scala 801:71]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_86 = rnm_stage_io_rnReq_0_bits_mul_isa_mul |
    rnm_stage_io_rnReq_0_bits_mul_isa_mulh; // @[riscv_isa.scala 203:19]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_87 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_86 | rnm_stage_io_rnReq_0_bits_mul_isa_mulhsu; // @[riscv_isa.scala 203:26]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_88 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_87 | rnm_stage_io_rnReq_0_bits_mul_isa_mulhu; // @[riscv_isa.scala 203:35]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_89 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_88 | rnm_stage_io_rnReq_0_bits_mul_isa_mulw; // @[riscv_isa.scala 203:43]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_90 = rnm_stage_io_rnReq_0_bits_mul_isa_div |
    rnm_stage_io_rnReq_0_bits_mul_isa_divu; // @[riscv_isa.scala 204:19]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_91 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_90 | rnm_stage_io_rnReq_0_bits_mul_isa_divw; // @[riscv_isa.scala 204:26]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_92 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_91 | rnm_stage_io_rnReq_0_bits_mul_isa_divuw; // @[riscv_isa.scala 204:33]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_93 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_92 | rnm_stage_io_rnReq_0_bits_mul_isa_rem; // @[riscv_isa.scala 204:41]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_94 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_93 | rnm_stage_io_rnReq_0_bits_mul_isa_remu; // @[riscv_isa.scala 204:47]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_95 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_94 | rnm_stage_io_rnReq_0_bits_mul_isa_remw; // @[riscv_isa.scala 204:54]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_96 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_95 | rnm_stage_io_rnReq_0_bits_mul_isa_remuw; // @[riscv_isa.scala 204:61]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_97 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_89 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_96; // @[riscv_isa.scala 206:25]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_98 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_85 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_97; // @[riscv_isa.scala 801:88]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_121 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_98 | rnm_stage__rnRspReport_io_enq_0_valid_T_22; // @[riscv_isa.scala 801:108]
  wire  rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_185 =
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_121 | rnm_stage__rnRspReport_io_enq_0_bits_T_62; // @[riscv_isa.scala 801:131]
  wire  rnm_stage__io_rnReq_0_ready_T = rnm_stage_io_xRename_0_req_ready & rnm_stage_io_fRename_0_req_ready; // @[Rename.scala 91:33]
  wire  rnm_stage__io_rnReq_0_ready_T_1 = rnm_stage__io_rnReq_0_ready_T & rnm_stage_reOrder_fifo_i_io_enq_0_ready; // @[Rename.scala 91:59]
  wire  rnm_stage__T_72 = ~rnm_stage__rnRspReport_io_enq_0_bits_T_62; // @[Rename.scala 157:48]
  wire  rnm_stage__T_75 = ~rnm_stage__T_72; // @[Rename.scala 157:15]
  wire  rnm_stage__T_120 = ~rnm_stage__io_xRename_0_req_valid_T_42; // @[Rename.scala 158:15]
  wire  _GEN_222 = rnm_stage__rnRspReport_io_enq_0_valid_T & rnm_stage__T_6; // @[Rename.scala 157:15]
  wire  iss_stage_clock;
  wire  iss_stage_reset;
  wire  iss_stage_io_dptReq_0_ready;
  wire  iss_stage_io_dptReq_0_valid;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_lui;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_auipc;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_addi;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_addiw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_slti;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_sltiu;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_xori;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_ori;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_andi;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_slli;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_slliw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_srli;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_srliw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_srai;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_sraiw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_add;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_addw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_sub;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_subw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_sll;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_sllw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_slt;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_sltu;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_xor;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_srl;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_srlw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_sra;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_sraw;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_or;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_and;
  wire  iss_stage_io_dptReq_0_bits_alu_isa_wfi;
  wire  iss_stage_io_dptReq_0_bits_bru_isa_jal;
  wire  iss_stage_io_dptReq_0_bits_bru_isa_jalr;
  wire  iss_stage_io_dptReq_0_bits_bru_isa_beq;
  wire  iss_stage_io_dptReq_0_bits_bru_isa_bne;
  wire  iss_stage_io_dptReq_0_bits_bru_isa_blt;
  wire  iss_stage_io_dptReq_0_bits_bru_isa_bge;
  wire  iss_stage_io_dptReq_0_bits_bru_isa_bltu;
  wire  iss_stage_io_dptReq_0_bits_bru_isa_bgeu;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_lb;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_lh;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_lw;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_ld;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_lbu;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_lhu;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_lwu;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_sb;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_sh;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_sw;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_sd;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_fence;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_fence_i;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_sfence_vma;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_lr_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_sc_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoswap_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoadd_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoxor_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoand_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoor_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amomin_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amomax_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amominu_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amomaxu_w;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_lr_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_sc_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoswap_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoadd_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoxor_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoand_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amoor_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amomin_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amomax_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amominu_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_amomaxu_d;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_flw;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_fsw;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_fld;
  wire  iss_stage_io_dptReq_0_bits_lsu_isa_fsd;
  wire  iss_stage_io_dptReq_0_bits_csr_isa_rw;
  wire  iss_stage_io_dptReq_0_bits_csr_isa_rs;
  wire  iss_stage_io_dptReq_0_bits_csr_isa_rc;
  wire  iss_stage_io_dptReq_0_bits_csr_isa_rwi;
  wire  iss_stage_io_dptReq_0_bits_csr_isa_rsi;
  wire  iss_stage_io_dptReq_0_bits_csr_isa_rci;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_mul;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_mulh;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_mulhsu;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_mulhu;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_div;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_divu;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_rem;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_remu;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_mulw;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_divw;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_divuw;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_remw;
  wire  iss_stage_io_dptReq_0_bits_mul_isa_remuw;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmadd_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmsub_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fnmsub_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fnmadd_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fadd_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsub_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmul_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fdiv_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsqrt_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsgnj_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjn_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjx_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmin_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmax_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_w_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_wu_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmv_x_w;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_feq_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_flt_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fle_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fclass_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_l_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_lu_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmadd_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmsub_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fnmsub_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fnmadd_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fadd_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsub_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmul_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fdiv_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsqrt_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsgnj_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjn_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjx_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmin_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmax_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_s_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_d_s;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_feq_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_flt_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fle_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fclass_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_w_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_wu_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_l_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_lu_d;
  wire  iss_stage_io_dptReq_0_bits_fpu_isa_fmv_x_d;
  wire  iss_stage_io_dptReq_0_bits_param_is_rvc;
  wire [38:0] iss_stage_io_dptReq_0_bits_param_pc;
  wire [63:0] iss_stage_io_dptReq_0_bits_param_imm;
  wire [4:0] iss_stage_io_dptReq_0_bits_param_raw_rs1;
  wire [5:0] iss_stage_io_dptReq_0_bits_phy_rs1;
  wire [5:0] iss_stage_io_dptReq_0_bits_phy_rs2;
  wire [5:0] iss_stage_io_dptReq_0_bits_phy_rs3;
  wire [5:0] iss_stage_io_dptReq_0_bits_phy_rd0;
  wire  iss_stage_io_alu_iss_exe_0_ready;
  wire  iss_stage_io_alu_iss_exe_0_valid;
  wire  iss_stage_io_alu_iss_exe_0_bits_fun_add;
  wire  iss_stage_io_alu_iss_exe_0_bits_fun_slt;
  wire  iss_stage_io_alu_iss_exe_0_bits_fun_xor;
  wire  iss_stage_io_alu_iss_exe_0_bits_fun_or;
  wire  iss_stage_io_alu_iss_exe_0_bits_fun_and;
  wire  iss_stage_io_alu_iss_exe_0_bits_fun_sll;
  wire  iss_stage_io_alu_iss_exe_0_bits_fun_srl;
  wire  iss_stage_io_alu_iss_exe_0_bits_fun_sra;
  wire [5:0] iss_stage_io_alu_iss_exe_0_bits_param_rd0;
  wire  iss_stage_io_alu_iss_exe_0_bits_param_is_32w;
  wire  iss_stage_io_alu_iss_exe_0_bits_param_is_usi;
  wire [63:0] iss_stage_io_alu_iss_exe_0_bits_param_dat_op1;
  wire [63:0] iss_stage_io_alu_iss_exe_0_bits_param_dat_op2;
  wire  iss_stage_io_mul_iss_exe_0_ready;
  wire  iss_stage_io_mul_iss_exe_0_valid;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_mul;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_mulh;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_mulhsu;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_mulhu;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_div;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_divu;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_rem;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_remu;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_mulw;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_divw;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_divuw;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_remw;
  wire  iss_stage_io_mul_iss_exe_0_bits_fun_remuw;
  wire [5:0] iss_stage_io_mul_iss_exe_0_bits_param_rd0;
  wire [63:0] iss_stage_io_mul_iss_exe_0_bits_param_dat_op1;
  wire [63:0] iss_stage_io_mul_iss_exe_0_bits_param_dat_op2;
  wire  iss_stage_io_bru_iss_exe_ready;
  wire  iss_stage_io_bru_iss_exe_valid;
  wire  iss_stage_io_bru_iss_exe_bits_fun_jalr;
  wire  iss_stage_io_bru_iss_exe_bits_fun_beq;
  wire  iss_stage_io_bru_iss_exe_bits_fun_bne;
  wire  iss_stage_io_bru_iss_exe_bits_fun_blt;
  wire  iss_stage_io_bru_iss_exe_bits_fun_bge;
  wire  iss_stage_io_bru_iss_exe_bits_fun_bltu;
  wire  iss_stage_io_bru_iss_exe_bits_fun_bgeu;
  wire [5:0] iss_stage_io_bru_iss_exe_bits_param_rd0;
  wire  iss_stage_io_bru_iss_exe_bits_param_is_rvc;
  wire [63:0] iss_stage_io_bru_iss_exe_bits_param_pc;
  wire [63:0] iss_stage_io_bru_iss_exe_bits_param_imm;
  wire [63:0] iss_stage_io_bru_iss_exe_bits_param_dat_op1;
  wire [63:0] iss_stage_io_bru_iss_exe_bits_param_dat_op2;
  wire  iss_stage_io_csr_iss_exe_ready;
  wire  iss_stage_io_csr_iss_exe_valid;
  wire  iss_stage_io_csr_iss_exe_bits_fun_rw;
  wire  iss_stage_io_csr_iss_exe_bits_fun_rs;
  wire  iss_stage_io_csr_iss_exe_bits_fun_rc;
  wire [5:0] iss_stage_io_csr_iss_exe_bits_param_rd0;
  wire [63:0] iss_stage_io_csr_iss_exe_bits_param_dat_op1;
  wire [63:0] iss_stage_io_csr_iss_exe_bits_param_dat_op2;
  wire  iss_stage_io_lsu_iss_exe_ready;
  wire  iss_stage_io_lsu_iss_exe_valid;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_lb;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_lh;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_lw;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_ld;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_lbu;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_lhu;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_lwu;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_sb;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_sh;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_sw;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_sd;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_fence;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_fence_i;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_sfence_vma;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_lr_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_sc_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoswap_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoadd_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoxor_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoand_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoor_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amomin_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amomax_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amominu_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amomaxu_w;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_lr_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_sc_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoswap_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoadd_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoxor_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoand_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amoor_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amomin_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amomax_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amominu_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_amomaxu_d;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_flw;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_fsw;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_fld;
  wire  iss_stage_io_lsu_iss_exe_bits_fun_fsd;
  wire [5:0] iss_stage_io_lsu_iss_exe_bits_param_rd0;
  wire [63:0] iss_stage_io_lsu_iss_exe_bits_param_dat_op1;
  wire [63:0] iss_stage_io_lsu_iss_exe_bits_param_dat_op2;
  wire  iss_stage_io_fpu_iss_exe_0_valid;
  wire [1:0] iss_stage_io_irgLog_0;
  wire [1:0] iss_stage_io_irgLog_1;
  wire [1:0] iss_stage_io_irgLog_2;
  wire [1:0] iss_stage_io_irgLog_3;
  wire [1:0] iss_stage_io_irgLog_4;
  wire [1:0] iss_stage_io_irgLog_5;
  wire [1:0] iss_stage_io_irgLog_6;
  wire [1:0] iss_stage_io_irgLog_7;
  wire [1:0] iss_stage_io_irgLog_8;
  wire [1:0] iss_stage_io_irgLog_9;
  wire [1:0] iss_stage_io_irgLog_10;
  wire [1:0] iss_stage_io_irgLog_11;
  wire [1:0] iss_stage_io_irgLog_12;
  wire [1:0] iss_stage_io_irgLog_13;
  wire [1:0] iss_stage_io_irgLog_14;
  wire [1:0] iss_stage_io_irgLog_15;
  wire [1:0] iss_stage_io_irgLog_16;
  wire [1:0] iss_stage_io_irgLog_17;
  wire [1:0] iss_stage_io_irgLog_18;
  wire [1:0] iss_stage_io_irgLog_19;
  wire [1:0] iss_stage_io_irgLog_20;
  wire [1:0] iss_stage_io_irgLog_21;
  wire [1:0] iss_stage_io_irgLog_22;
  wire [1:0] iss_stage_io_irgLog_23;
  wire [1:0] iss_stage_io_irgLog_24;
  wire [1:0] iss_stage_io_irgLog_25;
  wire [1:0] iss_stage_io_irgLog_26;
  wire [1:0] iss_stage_io_irgLog_27;
  wire [1:0] iss_stage_io_irgLog_28;
  wire [1:0] iss_stage_io_irgLog_29;
  wire [1:0] iss_stage_io_irgLog_30;
  wire [1:0] iss_stage_io_irgLog_31;
  wire [1:0] iss_stage_io_irgLog_32;
  wire [1:0] iss_stage_io_irgLog_33;
  wire [1:0] iss_stage_io_frgLog_0;
  wire [1:0] iss_stage_io_frgLog_1;
  wire [1:0] iss_stage_io_frgLog_2;
  wire [1:0] iss_stage_io_frgLog_3;
  wire [1:0] iss_stage_io_frgLog_4;
  wire [1:0] iss_stage_io_frgLog_5;
  wire [1:0] iss_stage_io_frgLog_6;
  wire [1:0] iss_stage_io_frgLog_7;
  wire [1:0] iss_stage_io_frgLog_8;
  wire [1:0] iss_stage_io_frgLog_9;
  wire [1:0] iss_stage_io_frgLog_10;
  wire [1:0] iss_stage_io_frgLog_11;
  wire [1:0] iss_stage_io_frgLog_12;
  wire [1:0] iss_stage_io_frgLog_13;
  wire [1:0] iss_stage_io_frgLog_14;
  wire [1:0] iss_stage_io_frgLog_15;
  wire [1:0] iss_stage_io_frgLog_16;
  wire [1:0] iss_stage_io_frgLog_17;
  wire [1:0] iss_stage_io_frgLog_18;
  wire [1:0] iss_stage_io_frgLog_19;
  wire [1:0] iss_stage_io_frgLog_20;
  wire [1:0] iss_stage_io_frgLog_21;
  wire [1:0] iss_stage_io_frgLog_22;
  wire [1:0] iss_stage_io_frgLog_23;
  wire [1:0] iss_stage_io_frgLog_24;
  wire [1:0] iss_stage_io_frgLog_25;
  wire [1:0] iss_stage_io_frgLog_26;
  wire [1:0] iss_stage_io_frgLog_27;
  wire [1:0] iss_stage_io_frgLog_28;
  wire [1:0] iss_stage_io_frgLog_29;
  wire [1:0] iss_stage_io_frgLog_30;
  wire [1:0] iss_stage_io_frgLog_31;
  wire [1:0] iss_stage_io_frgLog_32;
  wire [1:0] iss_stage_io_frgLog_33;
  wire  iss_stage_io_irgReq_0_valid;
  wire [5:0] iss_stage_io_irgReq_0_bits;
  wire  iss_stage_io_irgRsp_0_valid;
  wire [5:0] iss_stage_io_irgRsp_0_bits_phy;
  wire [63:0] iss_stage_io_irgRsp_0_bits_op;
  wire  iss_stage_io_flush;
  wire  iss_stage_aluIssFifo_0_clock;
  wire  iss_stage_aluIssFifo_0_reset;
  wire  iss_stage_aluIssFifo_0_io_enq_ready;
  wire  iss_stage_aluIssFifo_0_io_enq_valid;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_fun_add;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_fun_slt;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_fun_xor;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_fun_or;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_fun_and;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_fun_sll;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_fun_srl;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_fun_sra;
  wire [5:0] iss_stage_aluIssFifo_0_io_enq_bits_param_rd0;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_param_is_32w;
  wire  iss_stage_aluIssFifo_0_io_enq_bits_param_is_usi;
  wire [63:0] iss_stage_aluIssFifo_0_io_enq_bits_param_dat_op1;
  wire [63:0] iss_stage_aluIssFifo_0_io_enq_bits_param_dat_op2;
  wire  iss_stage_aluIssFifo_0_io_deq_ready;
  wire  iss_stage_aluIssFifo_0_io_deq_valid;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_fun_add;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_fun_slt;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_fun_xor;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_fun_or;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_fun_and;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_fun_sll;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_fun_srl;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_fun_sra;
  wire [5:0] iss_stage_aluIssFifo_0_io_deq_bits_param_rd0;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_param_is_32w;
  wire  iss_stage_aluIssFifo_0_io_deq_bits_param_is_usi;
  wire [63:0] iss_stage_aluIssFifo_0_io_deq_bits_param_dat_op1;
  wire [63:0] iss_stage_aluIssFifo_0_io_deq_bits_param_dat_op2;
  reg  iss_stage_aluIssFifo_0_ram_fun_add [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_add_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_add_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_add_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_add_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_add_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_add_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_add_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_add_clock;
  reg  iss_stage_aluIssFifo_0_ram_fun_slt [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_slt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_slt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_slt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_slt_clock;
  reg  iss_stage_aluIssFifo_0_ram_fun_xor [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_xor_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_xor_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_xor_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_xor_clock;
  reg  iss_stage_aluIssFifo_0_ram_fun_or [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_or_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_or_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_or_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_or_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_or_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_or_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_or_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_or_clock;
  reg  iss_stage_aluIssFifo_0_ram_fun_and [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_and_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_and_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_and_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_and_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_and_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_and_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_and_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_and_clock;
  reg  iss_stage_aluIssFifo_0_ram_fun_sll [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sll_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sll_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sll_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sll_clock;
  reg  iss_stage_aluIssFifo_0_ram_fun_srl [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_srl_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_srl_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_srl_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_srl_clock;
  reg  iss_stage_aluIssFifo_0_ram_fun_sra [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sra_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sra_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sra_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_fun_sra_clock;
  reg [5:0] iss_stage_aluIssFifo_0_ram_param_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_aluIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_rd0_clock;
  reg  iss_stage_aluIssFifo_0_ram_param_is_32w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_32w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_32w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_32w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_32w_clock;
  reg  iss_stage_aluIssFifo_0_ram_param_is_usi [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_usi_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_usi_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_usi_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_is_usi_clock;
  reg [63:0] iss_stage_aluIssFifo_0_ram_param_dat_op1 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_aluIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op1_clock;
  reg [63:0] iss_stage_aluIssFifo_0_ram_param_dat_op2 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_aluIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_aluIssFifo_0_ram_param_dat_op2_clock;
  reg  iss_stage_aluIssFifo_0_maybe_full; // @[Decoupled.scala 278:27]
  wire  iss_stage_aluIssFifo_0__empty_T = ~iss_stage_aluIssFifo_0_maybe_full; // @[Decoupled.scala 280:28]
  wire  iss_stage_aluIssFifo_0__do_enq_T = iss_stage_aluIssFifo_0_io_enq_ready & iss_stage_aluIssFifo_0_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_aluIssFifo_0__do_deq_T = iss_stage_aluIssFifo_0_io_deq_ready & iss_stage_aluIssFifo_0_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_aluIssFifo_0__GEN_22 = iss_stage_aluIssFifo_0_io_deq_ready ? 1'h0 : iss_stage_aluIssFifo_0__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  iss_stage_aluIssFifo_0__GEN_38 = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22 :
    iss_stage_aluIssFifo_0__do_enq_T; // @[Decoupled.scala 317:17]
  wire  iss_stage_aluIssFifo_0__GEN_37 = iss_stage_aluIssFifo_0__empty_T ? 1'h0 : iss_stage_aluIssFifo_0__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  iss_stage_aluIssFifo_0__T = iss_stage_aluIssFifo_0__GEN_38 != iss_stage_aluIssFifo_0__GEN_37; // @[Decoupled.scala 295:15]
  wire  iss_stage_aluIssFifo_0__io_deq_valid_T = ~iss_stage_aluIssFifo_0__empty_T; // @[Decoupled.scala 304:19]
  wire  iss_stage_mulIssFifo_0_clock;
  wire  iss_stage_mulIssFifo_0_reset;
  wire  iss_stage_mulIssFifo_0_io_enq_ready;
  wire  iss_stage_mulIssFifo_0_io_enq_valid;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_mul;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_mulh;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_mulhsu;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_mulhu;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_div;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_divu;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_rem;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_remu;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_mulw;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_divw;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_divuw;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_remw;
  wire  iss_stage_mulIssFifo_0_io_enq_bits_fun_remuw;
  wire [5:0] iss_stage_mulIssFifo_0_io_enq_bits_param_rd0;
  wire [63:0] iss_stage_mulIssFifo_0_io_enq_bits_param_dat_op1;
  wire [63:0] iss_stage_mulIssFifo_0_io_enq_bits_param_dat_op2;
  wire  iss_stage_mulIssFifo_0_io_deq_ready;
  wire  iss_stage_mulIssFifo_0_io_deq_valid;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_mul;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_mulh;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_mulhsu;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_mulhu;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_div;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_divu;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_rem;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_remu;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_mulw;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_divw;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_divuw;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_remw;
  wire  iss_stage_mulIssFifo_0_io_deq_bits_fun_remuw;
  wire [5:0] iss_stage_mulIssFifo_0_io_deq_bits_param_rd0;
  wire [63:0] iss_stage_mulIssFifo_0_io_deq_bits_param_dat_op1;
  wire [63:0] iss_stage_mulIssFifo_0_io_deq_bits_param_dat_op2;
  reg  iss_stage_mulIssFifo_0_ram_fun_mul [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mul_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mul_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mul_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mul_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_mulh [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulh_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_mulhsu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhsu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhsu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhsu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhsu_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_mulhu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulhu_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_div [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_div_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_div_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_div_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_div_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_div_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_div_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_div_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_div_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_divu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divu_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_rem [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_rem_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_rem_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_rem_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_rem_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_remu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remu_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_mulw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_mulw_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_divw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divw_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_divuw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divuw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divuw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divuw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_divuw_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_remw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remw_clock;
  reg  iss_stage_mulIssFifo_0_ram_fun_remuw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remuw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remuw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remuw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_fun_remuw_clock;
  reg [5:0] iss_stage_mulIssFifo_0_ram_param_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_mulIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_rd0_clock;
  reg [63:0] iss_stage_mulIssFifo_0_ram_param_dat_op1 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_mulIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op1_clock;
  reg [63:0] iss_stage_mulIssFifo_0_ram_param_dat_op2 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_mulIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_mulIssFifo_0_ram_param_dat_op2_clock;
  reg  iss_stage_mulIssFifo_0_maybe_full; // @[Decoupled.scala 278:27]
  wire  iss_stage_mulIssFifo_0__empty_T = ~iss_stage_mulIssFifo_0_maybe_full; // @[Decoupled.scala 280:28]
  wire  iss_stage_mulIssFifo_0__do_enq_T = iss_stage_mulIssFifo_0_io_enq_ready & iss_stage_mulIssFifo_0_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_mulIssFifo_0__do_deq_T = iss_stage_mulIssFifo_0_io_deq_ready & iss_stage_mulIssFifo_0_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_mulIssFifo_0__GEN_25 = iss_stage_mulIssFifo_0_io_deq_ready ? 1'h0 : iss_stage_mulIssFifo_0__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  iss_stage_mulIssFifo_0__GEN_44 = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25 :
    iss_stage_mulIssFifo_0__do_enq_T; // @[Decoupled.scala 317:17]
  wire  iss_stage_mulIssFifo_0__GEN_43 = iss_stage_mulIssFifo_0__empty_T ? 1'h0 : iss_stage_mulIssFifo_0__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  iss_stage_mulIssFifo_0__T = iss_stage_mulIssFifo_0__GEN_44 != iss_stage_mulIssFifo_0__GEN_43; // @[Decoupled.scala 295:15]
  wire  iss_stage_mulIssFifo_0__io_deq_valid_T = ~iss_stage_mulIssFifo_0__empty_T; // @[Decoupled.scala 304:19]
  wire  iss_stage_bruIssFifo_clock;
  wire  iss_stage_bruIssFifo_reset;
  wire  iss_stage_bruIssFifo_io_enq_ready;
  wire  iss_stage_bruIssFifo_io_enq_valid;
  wire  iss_stage_bruIssFifo_io_enq_bits_fun_jalr;
  wire  iss_stage_bruIssFifo_io_enq_bits_fun_beq;
  wire  iss_stage_bruIssFifo_io_enq_bits_fun_bne;
  wire  iss_stage_bruIssFifo_io_enq_bits_fun_blt;
  wire  iss_stage_bruIssFifo_io_enq_bits_fun_bge;
  wire  iss_stage_bruIssFifo_io_enq_bits_fun_bltu;
  wire  iss_stage_bruIssFifo_io_enq_bits_fun_bgeu;
  wire [5:0] iss_stage_bruIssFifo_io_enq_bits_param_rd0;
  wire  iss_stage_bruIssFifo_io_enq_bits_param_is_rvc;
  wire [63:0] iss_stage_bruIssFifo_io_enq_bits_param_pc;
  wire [63:0] iss_stage_bruIssFifo_io_enq_bits_param_imm;
  wire [63:0] iss_stage_bruIssFifo_io_enq_bits_param_dat_op1;
  wire [63:0] iss_stage_bruIssFifo_io_enq_bits_param_dat_op2;
  wire  iss_stage_bruIssFifo_io_deq_ready;
  wire  iss_stage_bruIssFifo_io_deq_valid;
  wire  iss_stage_bruIssFifo_io_deq_bits_fun_jalr;
  wire  iss_stage_bruIssFifo_io_deq_bits_fun_beq;
  wire  iss_stage_bruIssFifo_io_deq_bits_fun_bne;
  wire  iss_stage_bruIssFifo_io_deq_bits_fun_blt;
  wire  iss_stage_bruIssFifo_io_deq_bits_fun_bge;
  wire  iss_stage_bruIssFifo_io_deq_bits_fun_bltu;
  wire  iss_stage_bruIssFifo_io_deq_bits_fun_bgeu;
  wire [5:0] iss_stage_bruIssFifo_io_deq_bits_param_rd0;
  wire  iss_stage_bruIssFifo_io_deq_bits_param_is_rvc;
  wire [63:0] iss_stage_bruIssFifo_io_deq_bits_param_pc;
  wire [63:0] iss_stage_bruIssFifo_io_deq_bits_param_imm;
  wire [63:0] iss_stage_bruIssFifo_io_deq_bits_param_dat_op1;
  wire [63:0] iss_stage_bruIssFifo_io_deq_bits_param_dat_op2;
  reg  iss_stage_bruIssFifo_ram_fun_jalr [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_jalr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_jalr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_jalr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_jalr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_jalr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_jalr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_jalr_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_jalr_clock;
  reg  iss_stage_bruIssFifo_ram_fun_beq [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_beq_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_beq_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_beq_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_beq_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_beq_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_beq_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_beq_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_beq_clock;
  reg  iss_stage_bruIssFifo_ram_fun_bne [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bne_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bne_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bne_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bne_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bne_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bne_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bne_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bne_clock;
  reg  iss_stage_bruIssFifo_ram_fun_blt [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_blt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_blt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_blt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_blt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_blt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_blt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_blt_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_blt_clock;
  reg  iss_stage_bruIssFifo_ram_fun_bge [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bge_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bge_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bge_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bge_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bge_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bge_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bge_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bge_clock;
  reg  iss_stage_bruIssFifo_ram_fun_bltu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bltu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bltu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bltu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bltu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bltu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bltu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bltu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bltu_clock;
  reg  iss_stage_bruIssFifo_ram_fun_bgeu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bgeu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bgeu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bgeu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_fun_bgeu_clock;
  reg [5:0] iss_stage_bruIssFifo_ram_param_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_bruIssFifo_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_bruIssFifo_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_rd0_clock;
  reg  iss_stage_bruIssFifo_ram_param_is_rvc [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_is_rvc_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_is_rvc_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_is_rvc_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_is_rvc_clock;
  reg [63:0] iss_stage_bruIssFifo_ram_param_pc [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_pc_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_pc_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_bruIssFifo_ram_param_pc_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_bruIssFifo_ram_param_pc_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_pc_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_pc_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_pc_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_pc_clock;
  reg [63:0] iss_stage_bruIssFifo_ram_param_imm [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_imm_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_imm_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_bruIssFifo_ram_param_imm_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_bruIssFifo_ram_param_imm_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_imm_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_imm_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_imm_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_imm_clock;
  reg [63:0] iss_stage_bruIssFifo_ram_param_dat_op1 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_bruIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op1_clock;
  reg [63:0] iss_stage_bruIssFifo_ram_param_dat_op2 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_bruIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_bruIssFifo_ram_param_dat_op2_clock;
  reg  iss_stage_bruIssFifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  iss_stage_bruIssFifo__empty_T = ~iss_stage_bruIssFifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  iss_stage_bruIssFifo__do_enq_T = iss_stage_bruIssFifo_io_enq_ready & iss_stage_bruIssFifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_bruIssFifo__do_deq_T = iss_stage_bruIssFifo_io_deq_ready & iss_stage_bruIssFifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_bruIssFifo__GEN_23 = iss_stage_bruIssFifo_io_deq_ready ? 1'h0 : iss_stage_bruIssFifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  iss_stage_bruIssFifo__GEN_40 = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  iss_stage_bruIssFifo__GEN_39 = iss_stage_bruIssFifo__empty_T ? 1'h0 : iss_stage_bruIssFifo__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  iss_stage_bruIssFifo__T = iss_stage_bruIssFifo__GEN_40 != iss_stage_bruIssFifo__GEN_39; // @[Decoupled.scala 295:15]
  wire  iss_stage_bruIssFifo__io_deq_valid_T = ~iss_stage_bruIssFifo__empty_T; // @[Decoupled.scala 304:19]
  wire  iss_stage_csrIssFifo_clock;
  wire  iss_stage_csrIssFifo_reset;
  wire  iss_stage_csrIssFifo_io_enq_ready;
  wire  iss_stage_csrIssFifo_io_enq_valid;
  wire  iss_stage_csrIssFifo_io_enq_bits_fun_rw;
  wire  iss_stage_csrIssFifo_io_enq_bits_fun_rs;
  wire  iss_stage_csrIssFifo_io_enq_bits_fun_rc;
  wire [5:0] iss_stage_csrIssFifo_io_enq_bits_param_rd0;
  wire [63:0] iss_stage_csrIssFifo_io_enq_bits_param_dat_op1;
  wire [63:0] iss_stage_csrIssFifo_io_enq_bits_param_dat_op2;
  wire  iss_stage_csrIssFifo_io_deq_ready;
  wire  iss_stage_csrIssFifo_io_deq_valid;
  wire  iss_stage_csrIssFifo_io_deq_bits_fun_rw;
  wire  iss_stage_csrIssFifo_io_deq_bits_fun_rs;
  wire  iss_stage_csrIssFifo_io_deq_bits_fun_rc;
  wire [5:0] iss_stage_csrIssFifo_io_deq_bits_param_rd0;
  wire [63:0] iss_stage_csrIssFifo_io_deq_bits_param_dat_op1;
  wire [63:0] iss_stage_csrIssFifo_io_deq_bits_param_dat_op2;
  reg  iss_stage_csrIssFifo_ram_fun_rw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rw_clock;
  reg  iss_stage_csrIssFifo_ram_fun_rs [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rs_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rs_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rs_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rs_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rs_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rs_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rs_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rs_clock;
  reg  iss_stage_csrIssFifo_ram_fun_rc [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rc_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rc_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rc_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rc_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rc_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rc_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rc_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_fun_rc_clock;
  reg [5:0] iss_stage_csrIssFifo_ram_param_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_csrIssFifo_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_csrIssFifo_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_rd0_clock;
  reg [63:0] iss_stage_csrIssFifo_ram_param_dat_op1 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_csrIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op1_clock;
  reg [63:0] iss_stage_csrIssFifo_ram_param_dat_op2 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_csrIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_csrIssFifo_ram_param_dat_op2_clock;
  reg  iss_stage_csrIssFifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  iss_stage_csrIssFifo__empty_T = ~iss_stage_csrIssFifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  iss_stage_csrIssFifo__do_enq_T = iss_stage_csrIssFifo_io_enq_ready & iss_stage_csrIssFifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_csrIssFifo__do_deq_T = iss_stage_csrIssFifo_io_deq_ready & iss_stage_csrIssFifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_csrIssFifo__GEN_15 = iss_stage_csrIssFifo_io_deq_ready ? 1'h0 : iss_stage_csrIssFifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  iss_stage_csrIssFifo__GEN_24 = iss_stage_csrIssFifo__empty_T ? iss_stage_csrIssFifo__GEN_15 :
    iss_stage_csrIssFifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  iss_stage_csrIssFifo__GEN_23 = iss_stage_csrIssFifo__empty_T ? 1'h0 : iss_stage_csrIssFifo__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  iss_stage_csrIssFifo__T = iss_stage_csrIssFifo__GEN_24 != iss_stage_csrIssFifo__GEN_23; // @[Decoupled.scala 295:15]
  wire  iss_stage_csrIssFifo__io_deq_valid_T = ~iss_stage_csrIssFifo__empty_T; // @[Decoupled.scala 304:19]
  wire  iss_stage_lsuIssFifo_clock;
  wire  iss_stage_lsuIssFifo_reset;
  wire  iss_stage_lsuIssFifo_io_enq_ready;
  wire  iss_stage_lsuIssFifo_io_enq_valid;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_lb;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_lh;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_lw;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_ld;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_lbu;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_lhu;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_lwu;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_sb;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_sh;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_sw;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_sd;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_fence;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_fence_i;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_sfence_vma;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_lr_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_sc_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoswap_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoadd_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoxor_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoand_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoor_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amomin_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amomax_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amominu_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amomaxu_w;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_lr_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_sc_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoswap_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoadd_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoxor_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoand_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amoor_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amomin_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amomax_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amominu_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_amomaxu_d;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_flw;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_fsw;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_fld;
  wire  iss_stage_lsuIssFifo_io_enq_bits_fun_fsd;
  wire [5:0] iss_stage_lsuIssFifo_io_enq_bits_param_rd0;
  wire [63:0] iss_stage_lsuIssFifo_io_enq_bits_param_dat_op1;
  wire [63:0] iss_stage_lsuIssFifo_io_enq_bits_param_dat_op2;
  wire  iss_stage_lsuIssFifo_io_deq_ready;
  wire  iss_stage_lsuIssFifo_io_deq_valid;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_lb;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_lh;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_lw;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_ld;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_lbu;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_lhu;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_lwu;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_sb;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_sh;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_sw;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_sd;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_fence;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_fence_i;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_sfence_vma;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_lr_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_sc_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoswap_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoadd_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoxor_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoand_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoor_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amomin_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amomax_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amominu_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amomaxu_w;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_lr_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_sc_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoswap_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoadd_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoxor_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoand_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amoor_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amomin_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amomax_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amominu_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_amomaxu_d;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_flw;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_fsw;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_fld;
  wire  iss_stage_lsuIssFifo_io_deq_bits_fun_fsd;
  wire [5:0] iss_stage_lsuIssFifo_io_deq_bits_param_rd0;
  wire [63:0] iss_stage_lsuIssFifo_io_deq_bits_param_dat_op1;
  wire [63:0] iss_stage_lsuIssFifo_io_deq_bits_param_dat_op2;
  reg  iss_stage_lsuIssFifo_ram_fun_lb [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lb_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lb_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_lh [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lh_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lh_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_lw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lw_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_ld [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_ld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_ld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_ld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_ld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_ld_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_ld_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_lbu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lbu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lbu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lbu_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_lhu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lhu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lhu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lhu_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_lwu [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lwu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lwu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lwu_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_sb [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sb_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sb_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_sh [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sh_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sh_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_sw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sw_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_sd [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sd_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sd_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_fence [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_fence_i [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_i_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_i_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_i_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fence_i_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_sfence_vma [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sfence_vma_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sfence_vma_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sfence_vma_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sfence_vma_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_lr_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_sc_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoswap_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoadd_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoxor_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoand_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoor_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amomin_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amomax_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amominu_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amomaxu_w [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_w_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_lr_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_lr_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_sc_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_sc_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoswap_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoswap_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoadd_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoadd_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoxor_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoxor_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoand_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoand_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amoor_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amoor_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amomin_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomin_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amomax_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomax_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amominu_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amominu_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_amomaxu_d [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_amomaxu_d_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_flw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_flw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_flw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_flw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_flw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_flw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_flw_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_fsw [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsw_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_fld [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fld_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fld_clock;
  reg  iss_stage_lsuIssFifo_ram_fun_fsd [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_fun_fsd_clock;
  reg [5:0] iss_stage_lsuIssFifo_ram_param_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_lsuIssFifo_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] iss_stage_lsuIssFifo_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_rd0_clock;
  reg [63:0] iss_stage_lsuIssFifo_ram_param_dat_op1 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_lsuIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op1_clock;
  reg [63:0] iss_stage_lsuIssFifo_ram_param_dat_op2 [0:0]; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_lsuIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_en; // @[Decoupled.scala 275:95]
  wire  iss_stage_lsuIssFifo_ram_param_dat_op2_clock;
  reg  iss_stage_lsuIssFifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  iss_stage_lsuIssFifo__empty_T = ~iss_stage_lsuIssFifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  iss_stage_lsuIssFifo__do_enq_T = iss_stage_lsuIssFifo_io_enq_ready & iss_stage_lsuIssFifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_lsuIssFifo__do_deq_T = iss_stage_lsuIssFifo_io_deq_ready & iss_stage_lsuIssFifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  iss_stage_lsuIssFifo__GEN_52 = iss_stage_lsuIssFifo_io_deq_ready ? 1'h0 : iss_stage_lsuIssFifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  iss_stage_lsuIssFifo__GEN_98 = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  iss_stage_lsuIssFifo__GEN_97 = iss_stage_lsuIssFifo__empty_T ? 1'h0 : iss_stage_lsuIssFifo__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  iss_stage_lsuIssFifo__T = iss_stage_lsuIssFifo__GEN_98 != iss_stage_lsuIssFifo__GEN_97; // @[Decoupled.scala 295:15]
  wire  iss_stage_lsuIssFifo__io_deq_valid_T = ~iss_stage_lsuIssFifo__empty_T; // @[Decoupled.scala 304:19]
  reg  iss_stage_bufValid_0; // @[Issue.scala 61:29]
  reg  iss_stage_bufValid_1; // @[Issue.scala 61:29]
  reg  iss_stage_bufInfo_0_alu_isa_lui; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_auipc; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_addi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_addiw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_slti; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_sltiu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_xori; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_ori; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_andi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_slli; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_slliw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_srli; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_srliw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_srai; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_sraiw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_add; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_addw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_sub; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_subw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_sll; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_sllw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_slt; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_sltu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_xor; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_srl; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_srlw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_sra; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_sraw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_or; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_and; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_alu_isa_wfi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_bru_isa_jal; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_bru_isa_jalr; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_bru_isa_beq; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_bru_isa_bne; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_bru_isa_blt; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_bru_isa_bge; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_bru_isa_bltu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_bru_isa_bgeu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_lb; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_lh; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_lw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_ld; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_lbu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_lhu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_lwu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_sb; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_sh; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_sw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_sd; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_fence; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_fence_i; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_sfence_vma; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_lr_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_sc_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoswap_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoadd_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoxor_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoand_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoor_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amomin_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amomax_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amominu_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amomaxu_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_lr_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_sc_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoswap_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoadd_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoxor_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoand_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amoor_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amomin_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amomax_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amominu_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_amomaxu_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_flw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_fsw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_fld; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_lsu_isa_fsd; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_csr_isa_rw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_csr_isa_rs; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_csr_isa_rc; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_csr_isa_rwi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_csr_isa_rsi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_csr_isa_rci; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_mul; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_mulh; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_mulhsu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_mulhu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_div; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_divu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_rem; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_remu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_mulw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_divw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_divuw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_remw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_mul_isa_remuw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_0_param_is_rvc; // @[Issue.scala 62:25]
  reg [38:0] iss_stage_bufInfo_0_param_pc; // @[Issue.scala 62:25]
  reg [63:0] iss_stage_bufInfo_0_param_imm; // @[Issue.scala 62:25]
  reg [4:0] iss_stage_bufInfo_0_param_raw_rs1; // @[Issue.scala 62:25]
  reg [5:0] iss_stage_bufInfo_0_phy_rs1; // @[Issue.scala 62:25]
  reg [5:0] iss_stage_bufInfo_0_phy_rs2; // @[Issue.scala 62:25]
  reg [5:0] iss_stage_bufInfo_0_phy_rd0; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_lui; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_auipc; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_addi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_addiw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_slti; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_sltiu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_xori; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_ori; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_andi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_slli; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_slliw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_srli; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_srliw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_srai; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_sraiw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_add; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_addw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_sub; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_subw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_sll; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_sllw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_slt; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_sltu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_xor; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_srl; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_srlw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_sra; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_sraw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_or; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_and; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_alu_isa_wfi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_bru_isa_jal; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_bru_isa_jalr; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_bru_isa_beq; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_bru_isa_bne; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_bru_isa_blt; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_bru_isa_bge; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_bru_isa_bltu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_bru_isa_bgeu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_lb; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_lh; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_lw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_ld; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_lbu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_lhu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_lwu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_sb; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_sh; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_sw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_sd; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_fence; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_fence_i; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_sfence_vma; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_lr_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_sc_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoswap_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoadd_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoxor_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoand_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoor_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amomin_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amomax_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amominu_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amomaxu_w; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_lr_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_sc_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoswap_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoadd_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoxor_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoand_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amoor_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amomin_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amomax_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amominu_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_amomaxu_d; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_flw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_fsw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_fld; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_lsu_isa_fsd; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_csr_isa_rw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_csr_isa_rs; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_csr_isa_rc; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_csr_isa_rwi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_csr_isa_rsi; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_csr_isa_rci; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_mul; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_mulh; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_mulhsu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_mulhu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_div; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_divu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_rem; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_remu; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_mulw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_divw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_divuw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_remw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_mul_isa_remuw; // @[Issue.scala 62:25]
  reg  iss_stage_bufInfo_1_param_is_rvc; // @[Issue.scala 62:25]
  reg [38:0] iss_stage_bufInfo_1_param_pc; // @[Issue.scala 62:25]
  reg [63:0] iss_stage_bufInfo_1_param_imm; // @[Issue.scala 62:25]
  reg [4:0] iss_stage_bufInfo_1_param_raw_rs1; // @[Issue.scala 62:25]
  reg [5:0] iss_stage_bufInfo_1_phy_rs1; // @[Issue.scala 62:25]
  reg [5:0] iss_stage_bufInfo_1_phy_rs2; // @[Issue.scala 62:25]
  reg [5:0] iss_stage_bufInfo_1_phy_rd0; // @[Issue.scala 62:25]
  reg  iss_stage_isOpReady_0_0; // @[Issue.scala 65:25]
  reg  iss_stage_isOpReady_0_1; // @[Issue.scala 65:25]
  reg  iss_stage_isOpReady_1_0; // @[Issue.scala 65:25]
  reg  iss_stage_isOpReady_1_1; // @[Issue.scala 65:25]
  reg [64:0] iss_stage_bufOperator_0_0; // @[Issue.scala 66:25]
  reg [64:0] iss_stage_bufOperator_0_1; // @[Issue.scala 66:25]
  reg [64:0] iss_stage_bufOperator_1_0; // @[Issue.scala 66:25]
  reg [64:0] iss_stage_bufOperator_1_1; // @[Issue.scala 66:25]
  wire  iss_stage__entrySel_T = ~iss_stage_bufValid_0; // @[Issue.scala 69:43]
  wire  iss_stage_entrySel_0 = iss_stage__entrySel_T ? 1'h0 : 1'h1; // @[Issue.scala 69:26]
  wire  iss_stage__io_dptReq_0_ready_T_1 = ~iss_stage_bufValid_1; // @[Issue.scala 78:59]
  wire  iss_stage__T = iss_stage_io_dptReq_0_ready & iss_stage_io_dptReq_0_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_224 = ~iss_stage_entrySel_0; // @[Issue.scala 82:23 89:{36,36}]
  wire  iss_stage__GEN_0 = ~iss_stage_entrySel_0 | iss_stage_bufValid_0; // @[Issue.scala 82:23 89:{36,36}]
  wire  iss_stage__GEN_1 = iss_stage_entrySel_0 | iss_stage_bufValid_1; // @[Issue.scala 82:23 89:{36,36}]
  wire  iss_stage__GEN_396 = iss_stage__T ? iss_stage__GEN_0 : iss_stage_bufValid_0; // @[Issue.scala 82:23 88:38]
  wire  iss_stage__GEN_397 = iss_stage__T ? iss_stage__GEN_1 : iss_stage_bufValid_1; // @[Issue.scala 82:23 88:38]
  wire  iss_stage__GEN_792 = iss_stage_io_flush ? 1'h0 : iss_stage__GEN_396; // @[Issue.scala 86:22 87:23]
  wire  iss_stage__GEN_793 = iss_stage_io_flush ? 1'h0 : iss_stage__GEN_397; // @[Issue.scala 86:22 87:23]
  wire  iss_stage__T_3 = iss_stage_io_dptReq_0_bits_phy_rs1 == 6'h21; // @[Issue.scala 121:39]
  wire  iss_stage__GEN_1200 = _GEN_224 | iss_stage_isOpReady_0_0; // @[Issue.scala 122:{36,36} 65:25]
  wire  iss_stage__GEN_1201 = iss_stage_entrySel_0 | iss_stage_isOpReady_1_0; // @[Issue.scala 122:{36,36} 65:25]
  wire [64:0] iss_stage__GEN_1202 = ~iss_stage_entrySel_0 ? 65'h0 : iss_stage_bufOperator_0_0; // @[Issue.scala 123:{37,37} 66:25]
  wire [64:0] iss_stage__GEN_1203 = iss_stage_entrySel_0 ? 65'h0 : iss_stage_bufOperator_1_0; // @[Issue.scala 123:{37,37} 66:25]
  wire  iss_stage__GEN_1204 = ~iss_stage_entrySel_0 ? 1'h0 : iss_stage_isOpReady_0_0; // @[Issue.scala 125:{36,36} 65:25]
  wire  iss_stage__GEN_1205 = iss_stage_entrySel_0 ? 1'h0 : iss_stage_isOpReady_1_0; // @[Issue.scala 125:{36,36} 65:25]
  wire  iss_stage__GEN_1206 = iss_stage__T_3 ? iss_stage__GEN_1200 : iss_stage__GEN_1204; // @[Issue.scala 121:58]
  wire  iss_stage__GEN_1207 = iss_stage__T_3 ? iss_stage__GEN_1201 : iss_stage__GEN_1205; // @[Issue.scala 121:58]
  wire [64:0] iss_stage__GEN_1208 = iss_stage__T_3 ? iss_stage__GEN_1202 : iss_stage_bufOperator_0_0; // @[Issue.scala 121:58 66:25]
  wire [64:0] iss_stage__GEN_1209 = iss_stage__T_3 ? iss_stage__GEN_1203 : iss_stage_bufOperator_1_0; // @[Issue.scala 121:58 66:25]
  wire  iss_stage__T_4 = iss_stage_io_dptReq_0_bits_phy_rs2 == 6'h21; // @[Issue.scala 127:39]
  wire  iss_stage__GEN_1210 = _GEN_224 | iss_stage_isOpReady_0_1; // @[Issue.scala 128:{36,36} 65:25]
  wire  iss_stage__GEN_1211 = iss_stage_entrySel_0 | iss_stage_isOpReady_1_1; // @[Issue.scala 128:{36,36} 65:25]
  wire [64:0] iss_stage__GEN_1212 = ~iss_stage_entrySel_0 ? 65'h0 : iss_stage_bufOperator_0_1; // @[Issue.scala 129:{37,37} 66:25]
  wire [64:0] iss_stage__GEN_1213 = iss_stage_entrySel_0 ? 65'h0 : iss_stage_bufOperator_1_1; // @[Issue.scala 129:{37,37} 66:25]
  wire  iss_stage__GEN_1214 = ~iss_stage_entrySel_0 ? 1'h0 : iss_stage_isOpReady_0_1; // @[Issue.scala 131:{36,36} 65:25]
  wire  iss_stage__GEN_1215 = iss_stage_entrySel_0 ? 1'h0 : iss_stage_isOpReady_1_1; // @[Issue.scala 131:{36,36} 65:25]
  wire  iss_stage__GEN_1216 = iss_stage__T_4 ? iss_stage__GEN_1210 : iss_stage__GEN_1214; // @[Issue.scala 127:58]
  wire  iss_stage__GEN_1217 = iss_stage__T_4 ? iss_stage__GEN_1211 : iss_stage__GEN_1215; // @[Issue.scala 127:58]
  wire [64:0] iss_stage__GEN_1218 = iss_stage__T_4 ? iss_stage__GEN_1212 : iss_stage_bufOperator_0_1; // @[Issue.scala 127:58 66:25]
  wire [64:0] iss_stage__GEN_1219 = iss_stage__T_4 ? iss_stage__GEN_1213 : iss_stage_bufOperator_1_1; // @[Issue.scala 127:58 66:25]
  wire  iss_stage__GEN_1230 = iss_stage__T ? iss_stage__GEN_1206 : iss_stage_isOpReady_0_0; // @[Issue.scala 120:31 65:25]
  wire  iss_stage__GEN_1231 = iss_stage__T ? iss_stage__GEN_1207 : iss_stage_isOpReady_1_0; // @[Issue.scala 120:31 65:25]
  wire [64:0] iss_stage__GEN_1232 = iss_stage__T ? iss_stage__GEN_1208 : iss_stage_bufOperator_0_0; // @[Issue.scala 120:31 66:25]
  wire [64:0] iss_stage__GEN_1233 = iss_stage__T ? iss_stage__GEN_1209 : iss_stage_bufOperator_1_0; // @[Issue.scala 120:31 66:25]
  wire  iss_stage__GEN_1234 = iss_stage__T ? iss_stage__GEN_1216 : iss_stage_isOpReady_0_1; // @[Issue.scala 120:31 65:25]
  wire  iss_stage__GEN_1235 = iss_stage__T ? iss_stage__GEN_1217 : iss_stage_isOpReady_1_1; // @[Issue.scala 120:31 65:25]
  wire [64:0] iss_stage__GEN_1236 = iss_stage__T ? iss_stage__GEN_1218 : iss_stage_bufOperator_0_1; // @[Issue.scala 120:31 66:25]
  wire [64:0] iss_stage__GEN_1237 = iss_stage__T ? iss_stage__GEN_1219 : iss_stage_bufOperator_1_1; // @[Issue.scala 120:31 66:25]
  reg  iss_stage_ageMatrixW_0_0; // @[Issue.scala 156:23]
  reg  iss_stage_ageMatrixW_0_1; // @[Issue.scala 156:23]
  reg  iss_stage_ageMatrixW_1_1; // @[Issue.scala 156:23]
  wire  iss_stage__ageMatrixR_1_0_T = ~iss_stage_ageMatrixW_0_1; // @[Issue.scala 161:27]
  wire  iss_stage__GEN_1242 = _GEN_224 | iss_stage_ageMatrixW_0_0; // @[Issue.scala 156:23 171:{44,44}]
  wire  iss_stage__GEN_1244 = _GEN_224 | iss_stage_ageMatrixW_0_1; // @[Issue.scala 156:23 171:{44,44}]
  wire  iss_stage__GEN_1245 = iss_stage_entrySel_0 | iss_stage_ageMatrixW_1_1; // @[Issue.scala 156:23 171:{44,44}]
  wire [1:0] iss_stage__GEN_1255 = 6'h1 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_1 : iss_stage_io_irgLog_0; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1256 = 6'h2 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_2 : iss_stage__GEN_1255; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1257 = 6'h3 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_3 : iss_stage__GEN_1256; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1258 = 6'h4 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_4 : iss_stage__GEN_1257; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1259 = 6'h5 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_5 : iss_stage__GEN_1258; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1260 = 6'h6 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_6 : iss_stage__GEN_1259; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1261 = 6'h7 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_7 : iss_stage__GEN_1260; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1262 = 6'h8 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_8 : iss_stage__GEN_1261; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1263 = 6'h9 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_9 : iss_stage__GEN_1262; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1264 = 6'ha == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_10 : iss_stage__GEN_1263; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1265 = 6'hb == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_11 : iss_stage__GEN_1264; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1266 = 6'hc == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_12 : iss_stage__GEN_1265; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1267 = 6'hd == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_13 : iss_stage__GEN_1266; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1268 = 6'he == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_14 : iss_stage__GEN_1267; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1269 = 6'hf == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_15 : iss_stage__GEN_1268; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1270 = 6'h10 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_16 : iss_stage__GEN_1269; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1271 = 6'h11 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_17 : iss_stage__GEN_1270; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1272 = 6'h12 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_18 : iss_stage__GEN_1271; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1273 = 6'h13 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_19 : iss_stage__GEN_1272; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1274 = 6'h14 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_20 : iss_stage__GEN_1273; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1275 = 6'h15 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_21 : iss_stage__GEN_1274; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1276 = 6'h16 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_22 : iss_stage__GEN_1275; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1277 = 6'h17 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_23 : iss_stage__GEN_1276; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1278 = 6'h18 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_24 : iss_stage__GEN_1277; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1279 = 6'h19 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_25 : iss_stage__GEN_1278; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1280 = 6'h1a == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_26 : iss_stage__GEN_1279; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1281 = 6'h1b == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_27 : iss_stage__GEN_1280; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1282 = 6'h1c == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_28 : iss_stage__GEN_1281; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1283 = 6'h1d == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_29 : iss_stage__GEN_1282; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1284 = 6'h1e == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_30 : iss_stage__GEN_1283; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1285 = 6'h1f == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_31 : iss_stage__GEN_1284; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1286 = 6'h20 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_32 : iss_stage__GEN_1285; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1287 = 6'h21 == iss_stage_bufInfo_0_phy_rs1 ? iss_stage_io_irgLog_33 : iss_stage__GEN_1286; // @[Issue.scala 217:{37,37}]
  wire  iss_stage__canIOpReq_0_0_T = iss_stage__GEN_1287 == 2'h3; // @[Issue.scala 217:37]
  wire  iss_stage__canIOpReq_0_0_T_3 = ~iss_stage_isOpReady_0_0; // @[Issue.scala 219:7]
  wire  iss_stage__canIOpReq_0_0_T_4 = iss_stage__canIOpReq_0_0_T & iss_stage__canIOpReq_0_0_T_3; // @[Issue.scala 218:23]
  wire  iss_stage__canIOpReq_0_0_T_5 = iss_stage_io_irgRsp_0_bits_phy == iss_stage_bufInfo_0_phy_rs1; // @[Issue.scala 219:69]
  wire  iss_stage__canIOpReq_0_0_T_6 = iss_stage_io_irgRsp_0_valid & iss_stage__canIOpReq_0_0_T_5; // @[Issue.scala 219:55]
  wire  iss_stage__canIOpReq_0_0_T_7 = ~iss_stage__canIOpReq_0_0_T_6; // @[Issue.scala 219:26]
  wire  iss_stage__canIOpReq_0_0_T_8 = iss_stage__canIOpReq_0_0_T_4 & iss_stage__canIOpReq_0_0_T_7; // @[Issue.scala 219:24]
  wire [1:0] iss_stage__GEN_1289 = 6'h1 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_1 : iss_stage_io_irgLog_0; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1290 = 6'h2 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_2 : iss_stage__GEN_1289; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1291 = 6'h3 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_3 : iss_stage__GEN_1290; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1292 = 6'h4 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_4 : iss_stage__GEN_1291; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1293 = 6'h5 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_5 : iss_stage__GEN_1292; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1294 = 6'h6 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_6 : iss_stage__GEN_1293; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1295 = 6'h7 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_7 : iss_stage__GEN_1294; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1296 = 6'h8 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_8 : iss_stage__GEN_1295; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1297 = 6'h9 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_9 : iss_stage__GEN_1296; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1298 = 6'ha == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_10 : iss_stage__GEN_1297; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1299 = 6'hb == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_11 : iss_stage__GEN_1298; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1300 = 6'hc == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_12 : iss_stage__GEN_1299; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1301 = 6'hd == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_13 : iss_stage__GEN_1300; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1302 = 6'he == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_14 : iss_stage__GEN_1301; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1303 = 6'hf == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_15 : iss_stage__GEN_1302; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1304 = 6'h10 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_16 : iss_stage__GEN_1303; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1305 = 6'h11 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_17 : iss_stage__GEN_1304; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1306 = 6'h12 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_18 : iss_stage__GEN_1305; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1307 = 6'h13 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_19 : iss_stage__GEN_1306; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1308 = 6'h14 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_20 : iss_stage__GEN_1307; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1309 = 6'h15 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_21 : iss_stage__GEN_1308; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1310 = 6'h16 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_22 : iss_stage__GEN_1309; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1311 = 6'h17 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_23 : iss_stage__GEN_1310; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1312 = 6'h18 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_24 : iss_stage__GEN_1311; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1313 = 6'h19 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_25 : iss_stage__GEN_1312; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1314 = 6'h1a == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_26 : iss_stage__GEN_1313; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1315 = 6'h1b == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_27 : iss_stage__GEN_1314; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1316 = 6'h1c == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_28 : iss_stage__GEN_1315; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1317 = 6'h1d == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_29 : iss_stage__GEN_1316; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1318 = 6'h1e == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_30 : iss_stage__GEN_1317; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1319 = 6'h1f == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_31 : iss_stage__GEN_1318; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1320 = 6'h20 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_32 : iss_stage__GEN_1319; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1321 = 6'h21 == iss_stage_bufInfo_0_phy_rs2 ? iss_stage_io_irgLog_33 : iss_stage__GEN_1320; // @[Issue.scala 222:{37,37}]
  wire  iss_stage__canIOpReq_0_1_T = iss_stage__GEN_1321 == 2'h3; // @[Issue.scala 222:37]
  wire  iss_stage__canIOpReq_0_1_T_3 = ~iss_stage_isOpReady_0_1; // @[Issue.scala 224:7]
  wire  iss_stage__canIOpReq_0_1_T_4 = iss_stage__canIOpReq_0_1_T & iss_stage__canIOpReq_0_1_T_3; // @[Issue.scala 223:23]
  wire  iss_stage__canIOpReq_0_1_T_5 = iss_stage_io_irgRsp_0_bits_phy == iss_stage_bufInfo_0_phy_rs2; // @[Issue.scala 224:69]
  wire  iss_stage__canIOpReq_0_1_T_6 = iss_stage_io_irgRsp_0_valid & iss_stage__canIOpReq_0_1_T_5; // @[Issue.scala 224:55]
  wire  iss_stage__canIOpReq_0_1_T_7 = ~iss_stage__canIOpReq_0_1_T_6; // @[Issue.scala 224:26]
  wire  iss_stage__canIOpReq_0_1_T_8 = iss_stage__canIOpReq_0_1_T_4 & iss_stage__canIOpReq_0_1_T_7; // @[Issue.scala 224:24]
  wire [1:0] iss_stage__GEN_1323 = 6'h1 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_1 : iss_stage_io_irgLog_0; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1324 = 6'h2 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_2 : iss_stage__GEN_1323; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1325 = 6'h3 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_3 : iss_stage__GEN_1324; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1326 = 6'h4 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_4 : iss_stage__GEN_1325; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1327 = 6'h5 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_5 : iss_stage__GEN_1326; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1328 = 6'h6 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_6 : iss_stage__GEN_1327; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1329 = 6'h7 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_7 : iss_stage__GEN_1328; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1330 = 6'h8 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_8 : iss_stage__GEN_1329; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1331 = 6'h9 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_9 : iss_stage__GEN_1330; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1332 = 6'ha == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_10 : iss_stage__GEN_1331; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1333 = 6'hb == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_11 : iss_stage__GEN_1332; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1334 = 6'hc == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_12 : iss_stage__GEN_1333; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1335 = 6'hd == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_13 : iss_stage__GEN_1334; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1336 = 6'he == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_14 : iss_stage__GEN_1335; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1337 = 6'hf == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_15 : iss_stage__GEN_1336; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1338 = 6'h10 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_16 : iss_stage__GEN_1337; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1339 = 6'h11 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_17 : iss_stage__GEN_1338; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1340 = 6'h12 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_18 : iss_stage__GEN_1339; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1341 = 6'h13 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_19 : iss_stage__GEN_1340; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1342 = 6'h14 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_20 : iss_stage__GEN_1341; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1343 = 6'h15 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_21 : iss_stage__GEN_1342; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1344 = 6'h16 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_22 : iss_stage__GEN_1343; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1345 = 6'h17 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_23 : iss_stage__GEN_1344; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1346 = 6'h18 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_24 : iss_stage__GEN_1345; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1347 = 6'h19 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_25 : iss_stage__GEN_1346; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1348 = 6'h1a == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_26 : iss_stage__GEN_1347; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1349 = 6'h1b == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_27 : iss_stage__GEN_1348; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1350 = 6'h1c == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_28 : iss_stage__GEN_1349; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1351 = 6'h1d == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_29 : iss_stage__GEN_1350; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1352 = 6'h1e == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_30 : iss_stage__GEN_1351; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1353 = 6'h1f == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_31 : iss_stage__GEN_1352; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1354 = 6'h20 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_32 : iss_stage__GEN_1353; // @[Issue.scala 217:{37,37}]
  wire [1:0] iss_stage__GEN_1355 = 6'h21 == iss_stage_bufInfo_1_phy_rs1 ? iss_stage_io_irgLog_33 : iss_stage__GEN_1354; // @[Issue.scala 217:{37,37}]
  wire  iss_stage__canIOpReq_1_0_T = iss_stage__GEN_1355 == 2'h3; // @[Issue.scala 217:37]
  wire  iss_stage__canIOpReq_1_0_T_3 = ~iss_stage_isOpReady_1_0; // @[Issue.scala 219:7]
  wire  iss_stage__canIOpReq_1_0_T_4 = iss_stage__canIOpReq_1_0_T & iss_stage__canIOpReq_1_0_T_3; // @[Issue.scala 218:23]
  wire  iss_stage__canIOpReq_1_0_T_5 = iss_stage_io_irgRsp_0_bits_phy == iss_stage_bufInfo_1_phy_rs1; // @[Issue.scala 219:69]
  wire  iss_stage__canIOpReq_1_0_T_6 = iss_stage_io_irgRsp_0_valid & iss_stage__canIOpReq_1_0_T_5; // @[Issue.scala 219:55]
  wire  iss_stage__canIOpReq_1_0_T_7 = ~iss_stage__canIOpReq_1_0_T_6; // @[Issue.scala 219:26]
  wire  iss_stage__canIOpReq_1_0_T_8 = iss_stage__canIOpReq_1_0_T_4 & iss_stage__canIOpReq_1_0_T_7; // @[Issue.scala 219:24]
  wire [1:0] iss_stage__GEN_1357 = 6'h1 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_1 : iss_stage_io_irgLog_0; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1358 = 6'h2 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_2 : iss_stage__GEN_1357; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1359 = 6'h3 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_3 : iss_stage__GEN_1358; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1360 = 6'h4 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_4 : iss_stage__GEN_1359; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1361 = 6'h5 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_5 : iss_stage__GEN_1360; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1362 = 6'h6 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_6 : iss_stage__GEN_1361; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1363 = 6'h7 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_7 : iss_stage__GEN_1362; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1364 = 6'h8 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_8 : iss_stage__GEN_1363; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1365 = 6'h9 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_9 : iss_stage__GEN_1364; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1366 = 6'ha == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_10 : iss_stage__GEN_1365; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1367 = 6'hb == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_11 : iss_stage__GEN_1366; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1368 = 6'hc == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_12 : iss_stage__GEN_1367; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1369 = 6'hd == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_13 : iss_stage__GEN_1368; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1370 = 6'he == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_14 : iss_stage__GEN_1369; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1371 = 6'hf == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_15 : iss_stage__GEN_1370; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1372 = 6'h10 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_16 : iss_stage__GEN_1371; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1373 = 6'h11 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_17 : iss_stage__GEN_1372; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1374 = 6'h12 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_18 : iss_stage__GEN_1373; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1375 = 6'h13 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_19 : iss_stage__GEN_1374; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1376 = 6'h14 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_20 : iss_stage__GEN_1375; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1377 = 6'h15 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_21 : iss_stage__GEN_1376; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1378 = 6'h16 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_22 : iss_stage__GEN_1377; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1379 = 6'h17 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_23 : iss_stage__GEN_1378; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1380 = 6'h18 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_24 : iss_stage__GEN_1379; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1381 = 6'h19 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_25 : iss_stage__GEN_1380; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1382 = 6'h1a == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_26 : iss_stage__GEN_1381; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1383 = 6'h1b == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_27 : iss_stage__GEN_1382; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1384 = 6'h1c == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_28 : iss_stage__GEN_1383; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1385 = 6'h1d == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_29 : iss_stage__GEN_1384; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1386 = 6'h1e == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_30 : iss_stage__GEN_1385; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1387 = 6'h1f == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_31 : iss_stage__GEN_1386; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1388 = 6'h20 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_32 : iss_stage__GEN_1387; // @[Issue.scala 222:{37,37}]
  wire [1:0] iss_stage__GEN_1389 = 6'h21 == iss_stage_bufInfo_1_phy_rs2 ? iss_stage_io_irgLog_33 : iss_stage__GEN_1388; // @[Issue.scala 222:{37,37}]
  wire  iss_stage__canIOpReq_1_1_T = iss_stage__GEN_1389 == 2'h3; // @[Issue.scala 222:37]
  wire  iss_stage__canIOpReq_1_1_T_3 = ~iss_stage_isOpReady_1_1; // @[Issue.scala 224:7]
  wire  iss_stage__canIOpReq_1_1_T_4 = iss_stage__canIOpReq_1_1_T & iss_stage__canIOpReq_1_1_T_3; // @[Issue.scala 223:23]
  wire  iss_stage__canIOpReq_1_1_T_5 = iss_stage_io_irgRsp_0_bits_phy == iss_stage_bufInfo_1_phy_rs2; // @[Issue.scala 224:69]
  wire  iss_stage__canIOpReq_1_1_T_6 = iss_stage_io_irgRsp_0_valid & iss_stage__canIOpReq_1_1_T_5; // @[Issue.scala 224:55]
  wire  iss_stage__canIOpReq_1_1_T_7 = ~iss_stage__canIOpReq_1_1_T_6; // @[Issue.scala 224:26]
  wire  iss_stage__canIOpReq_1_1_T_8 = iss_stage__canIOpReq_1_1_T_4 & iss_stage__canIOpReq_1_1_T_7; // @[Issue.scala 224:24]
  wire [1:0] iss_stage__GEN_1391 = 6'h1 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_1 :
    iss_stage_io_irgLog_0; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1392 = 6'h2 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_2 :
    iss_stage__GEN_1391; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1393 = 6'h3 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_3 :
    iss_stage__GEN_1392; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1394 = 6'h4 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_4 :
    iss_stage__GEN_1393; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1395 = 6'h5 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_5 :
    iss_stage__GEN_1394; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1396 = 6'h6 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_6 :
    iss_stage__GEN_1395; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1397 = 6'h7 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_7 :
    iss_stage__GEN_1396; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1398 = 6'h8 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_8 :
    iss_stage__GEN_1397; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1399 = 6'h9 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_9 :
    iss_stage__GEN_1398; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1400 = 6'ha == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_10 :
    iss_stage__GEN_1399; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1401 = 6'hb == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_11 :
    iss_stage__GEN_1400; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1402 = 6'hc == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_12 :
    iss_stage__GEN_1401; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1403 = 6'hd == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_13 :
    iss_stage__GEN_1402; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1404 = 6'he == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_14 :
    iss_stage__GEN_1403; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1405 = 6'hf == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_15 :
    iss_stage__GEN_1404; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1406 = 6'h10 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_16 :
    iss_stage__GEN_1405; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1407 = 6'h11 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_17 :
    iss_stage__GEN_1406; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1408 = 6'h12 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_18 :
    iss_stage__GEN_1407; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1409 = 6'h13 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_19 :
    iss_stage__GEN_1408; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1410 = 6'h14 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_20 :
    iss_stage__GEN_1409; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1411 = 6'h15 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_21 :
    iss_stage__GEN_1410; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1412 = 6'h16 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_22 :
    iss_stage__GEN_1411; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1413 = 6'h17 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_23 :
    iss_stage__GEN_1412; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1414 = 6'h18 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_24 :
    iss_stage__GEN_1413; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1415 = 6'h19 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_25 :
    iss_stage__GEN_1414; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1416 = 6'h1a == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_26 :
    iss_stage__GEN_1415; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1417 = 6'h1b == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_27 :
    iss_stage__GEN_1416; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1418 = 6'h1c == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_28 :
    iss_stage__GEN_1417; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1419 = 6'h1d == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_29 :
    iss_stage__GEN_1418; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1420 = 6'h1e == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_30 :
    iss_stage__GEN_1419; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1421 = 6'h1f == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_31 :
    iss_stage__GEN_1420; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1422 = 6'h20 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_32 :
    iss_stage__GEN_1421; // @[Issue.scala 232:{44,44}]
  wire [1:0] iss_stage__GEN_1423 = 6'h21 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_irgLog_33 :
    iss_stage__GEN_1422; // @[Issue.scala 232:{44,44}]
  wire  iss_stage__canIOpPostReq_0_0_T = iss_stage__GEN_1423 == 2'h3; // @[Issue.scala 232:44]
  wire  iss_stage__canIOpPostReq_0_0_T_1 = iss_stage_io_dptReq_0_bits_phy_rs1 != 6'h21; // @[Issue.scala 233:33]
  wire  iss_stage__canIOpPostReq_0_0_T_2 = iss_stage__canIOpPostReq_0_0_T & iss_stage__canIOpPostReq_0_0_T_1; // @[Issue.scala 232:56]
  wire  iss_stage__canIOpPostReq_0_0_T_3 = iss_stage_io_dptReq_0_bits_fpu_isa_fmadd_s |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmsub_s; // @[riscv_isa.scala 391:15]
  wire  iss_stage__canIOpPostReq_0_0_T_4 = iss_stage__canIOpPostReq_0_0_T_3 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fnmsub_s; // @[riscv_isa.scala 391:27]
  wire  iss_stage__canIOpPostReq_0_0_T_5 = iss_stage__canIOpPostReq_0_0_T_4 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fnmadd_s; // @[riscv_isa.scala 391:39]
  wire  iss_stage__canIOpPostReq_0_0_T_6 = iss_stage__canIOpPostReq_0_0_T_5 | iss_stage_io_dptReq_0_bits_fpu_isa_fmadd_d
    ; // @[riscv_isa.scala 391:51]
  wire  iss_stage__canIOpPostReq_0_0_T_7 = iss_stage__canIOpPostReq_0_0_T_6 | iss_stage_io_dptReq_0_bits_fpu_isa_fmsub_d
    ; // @[riscv_isa.scala 392:15]
  wire  iss_stage__canIOpPostReq_0_0_T_8 = iss_stage__canIOpPostReq_0_0_T_7 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fnmsub_d; // @[riscv_isa.scala 392:27]
  wire  iss_stage__canIOpPostReq_0_0_T_9 = iss_stage__canIOpPostReq_0_0_T_8 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fnmadd_d; // @[riscv_isa.scala 392:39]
  wire  iss_stage__canIOpPostReq_0_0_T_10 = iss_stage__canIOpPostReq_0_0_T_9 | iss_stage_io_dptReq_0_bits_fpu_isa_fadd_s
    ; // @[riscv_isa.scala 392:51]
  wire  iss_stage__canIOpPostReq_0_0_T_11 = iss_stage__canIOpPostReq_0_0_T_10 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsub_s; // @[riscv_isa.scala 393:15]
  wire  iss_stage__canIOpPostReq_0_0_T_12 = iss_stage__canIOpPostReq_0_0_T_11 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmul_s; // @[riscv_isa.scala 393:27]
  wire  iss_stage__canIOpPostReq_0_0_T_13 = iss_stage__canIOpPostReq_0_0_T_12 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fdiv_s; // @[riscv_isa.scala 393:39]
  wire  iss_stage__canIOpPostReq_0_0_T_14 = iss_stage__canIOpPostReq_0_0_T_13 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsqrt_s; // @[riscv_isa.scala 393:51]
  wire  iss_stage__canIOpPostReq_0_0_T_15 = iss_stage__canIOpPostReq_0_0_T_14 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fadd_d; // @[riscv_isa.scala 393:63]
  wire  iss_stage__canIOpPostReq_0_0_T_16 = iss_stage__canIOpPostReq_0_0_T_15 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsub_d; // @[riscv_isa.scala 394:15]
  wire  iss_stage__canIOpPostReq_0_0_T_17 = iss_stage__canIOpPostReq_0_0_T_16 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmul_d; // @[riscv_isa.scala 394:27]
  wire  iss_stage__canIOpPostReq_0_0_T_18 = iss_stage__canIOpPostReq_0_0_T_17 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fdiv_d; // @[riscv_isa.scala 394:39]
  wire  iss_stage__canIOpPostReq_0_0_T_19 = iss_stage__canIOpPostReq_0_0_T_18 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsqrt_d; // @[riscv_isa.scala 394:51]
  wire  iss_stage__canIOpPostReq_0_0_T_20 = iss_stage__canIOpPostReq_0_0_T_19 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsgnj_s; // @[riscv_isa.scala 394:63]
  wire  iss_stage__canIOpPostReq_0_0_T_21 = iss_stage__canIOpPostReq_0_0_T_20 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjn_s; // @[riscv_isa.scala 395:15]
  wire  iss_stage__canIOpPostReq_0_0_T_22 = iss_stage__canIOpPostReq_0_0_T_21 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjx_s; // @[riscv_isa.scala 395:27]
  wire  iss_stage__canIOpPostReq_0_0_T_23 = iss_stage__canIOpPostReq_0_0_T_22 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsgnj_d; // @[riscv_isa.scala 395:39]
  wire  iss_stage__canIOpPostReq_0_0_T_24 = iss_stage__canIOpPostReq_0_0_T_23 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjn_d; // @[riscv_isa.scala 396:15]
  wire  iss_stage__canIOpPostReq_0_0_T_25 = iss_stage__canIOpPostReq_0_0_T_24 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjx_d; // @[riscv_isa.scala 396:27]
  wire  iss_stage__canIOpPostReq_0_0_T_26 = iss_stage__canIOpPostReq_0_0_T_25 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmin_s; // @[riscv_isa.scala 396:39]
  wire  iss_stage__canIOpPostReq_0_0_T_27 = iss_stage__canIOpPostReq_0_0_T_26 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmax_s; // @[riscv_isa.scala 397:15]
  wire  iss_stage__canIOpPostReq_0_0_T_28 = iss_stage__canIOpPostReq_0_0_T_27 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmin_d; // @[riscv_isa.scala 397:27]
  wire  iss_stage__canIOpPostReq_0_0_T_29 = iss_stage__canIOpPostReq_0_0_T_28 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmax_d; // @[riscv_isa.scala 397:39]
  wire  iss_stage__canIOpPostReq_0_0_T_30 = iss_stage__canIOpPostReq_0_0_T_29 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmv_x_w; // @[riscv_isa.scala 397:51]
  wire  iss_stage__canIOpPostReq_0_0_T_31 = iss_stage__canIOpPostReq_0_0_T_30 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fmv_x_d; // @[riscv_isa.scala 398:15]
  wire  iss_stage__canIOpPostReq_0_0_T_32 = iss_stage__canIOpPostReq_0_0_T_31 | iss_stage_io_dptReq_0_bits_fpu_isa_feq_s
    ; // @[riscv_isa.scala 398:27]
  wire  iss_stage__canIOpPostReq_0_0_T_33 = iss_stage__canIOpPostReq_0_0_T_32 | iss_stage_io_dptReq_0_bits_fpu_isa_flt_s
    ; // @[riscv_isa.scala 399:15]
  wire  iss_stage__canIOpPostReq_0_0_T_34 = iss_stage__canIOpPostReq_0_0_T_33 | iss_stage_io_dptReq_0_bits_fpu_isa_fle_s
    ; // @[riscv_isa.scala 399:27]
  wire  iss_stage__canIOpPostReq_0_0_T_35 = iss_stage__canIOpPostReq_0_0_T_34 | iss_stage_io_dptReq_0_bits_fpu_isa_feq_d
    ; // @[riscv_isa.scala 399:39]
  wire  iss_stage__canIOpPostReq_0_0_T_36 = iss_stage__canIOpPostReq_0_0_T_35 | iss_stage_io_dptReq_0_bits_fpu_isa_flt_d
    ; // @[riscv_isa.scala 400:15]
  wire  iss_stage__canIOpPostReq_0_0_T_37 = iss_stage__canIOpPostReq_0_0_T_36 | iss_stage_io_dptReq_0_bits_fpu_isa_fle_d
    ; // @[riscv_isa.scala 400:27]
  wire  iss_stage__canIOpPostReq_0_0_T_38 = iss_stage__canIOpPostReq_0_0_T_37 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fclass_s; // @[riscv_isa.scala 400:39]
  wire  iss_stage__canIOpPostReq_0_0_T_39 = iss_stage__canIOpPostReq_0_0_T_38 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fclass_d; // @[riscv_isa.scala 401:15]
  wire  iss_stage__canIOpPostReq_0_0_T_40 = iss_stage__canIOpPostReq_0_0_T_39 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_w_s; // @[riscv_isa.scala 401:27]
  wire  iss_stage__canIOpPostReq_0_0_T_41 = iss_stage__canIOpPostReq_0_0_T_40 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_wu_s; // @[riscv_isa.scala 402:15]
  wire  iss_stage__canIOpPostReq_0_0_T_42 = iss_stage__canIOpPostReq_0_0_T_41 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_l_s; // @[riscv_isa.scala 402:27]
  wire  iss_stage__canIOpPostReq_0_0_T_43 = iss_stage__canIOpPostReq_0_0_T_42 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_lu_s; // @[riscv_isa.scala 402:39]
  wire  iss_stage__canIOpPostReq_0_0_T_44 = iss_stage__canIOpPostReq_0_0_T_43 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_w_d; // @[riscv_isa.scala 402:51]
  wire  iss_stage__canIOpPostReq_0_0_T_45 = iss_stage__canIOpPostReq_0_0_T_44 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_wu_d; // @[riscv_isa.scala 403:15]
  wire  iss_stage__canIOpPostReq_0_0_T_46 = iss_stage__canIOpPostReq_0_0_T_45 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_l_d; // @[riscv_isa.scala 403:27]
  wire  iss_stage__canIOpPostReq_0_0_T_47 = iss_stage__canIOpPostReq_0_0_T_46 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_lu_d; // @[riscv_isa.scala 403:39]
  wire  iss_stage__canIOpPostReq_0_0_T_48 = iss_stage__canIOpPostReq_0_0_T_47 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_s_d; // @[riscv_isa.scala 403:51]
  wire  iss_stage__canIOpPostReq_0_0_T_49 = iss_stage__canIOpPostReq_0_0_T_48 |
    iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_d_s; // @[riscv_isa.scala 404:15]
  wire  iss_stage__canIOpPostReq_0_0_T_50 = ~iss_stage__canIOpPostReq_0_0_T_49; // @[Issue.scala 234:7]
  wire  iss_stage__canIOpPostReq_0_0_T_51 = iss_stage__canIOpPostReq_0_0_T_2 & iss_stage__canIOpPostReq_0_0_T_50; // @[Issue.scala 233:50]
  wire [1:0] iss_stage__GEN_1425 = 6'h1 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_1 :
    iss_stage_io_irgLog_0; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1426 = 6'h2 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_2 :
    iss_stage__GEN_1425; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1427 = 6'h3 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_3 :
    iss_stage__GEN_1426; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1428 = 6'h4 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_4 :
    iss_stage__GEN_1427; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1429 = 6'h5 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_5 :
    iss_stage__GEN_1428; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1430 = 6'h6 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_6 :
    iss_stage__GEN_1429; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1431 = 6'h7 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_7 :
    iss_stage__GEN_1430; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1432 = 6'h8 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_8 :
    iss_stage__GEN_1431; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1433 = 6'h9 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_9 :
    iss_stage__GEN_1432; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1434 = 6'ha == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_10 :
    iss_stage__GEN_1433; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1435 = 6'hb == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_11 :
    iss_stage__GEN_1434; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1436 = 6'hc == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_12 :
    iss_stage__GEN_1435; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1437 = 6'hd == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_13 :
    iss_stage__GEN_1436; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1438 = 6'he == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_14 :
    iss_stage__GEN_1437; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1439 = 6'hf == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_15 :
    iss_stage__GEN_1438; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1440 = 6'h10 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_16 :
    iss_stage__GEN_1439; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1441 = 6'h11 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_17 :
    iss_stage__GEN_1440; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1442 = 6'h12 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_18 :
    iss_stage__GEN_1441; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1443 = 6'h13 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_19 :
    iss_stage__GEN_1442; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1444 = 6'h14 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_20 :
    iss_stage__GEN_1443; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1445 = 6'h15 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_21 :
    iss_stage__GEN_1444; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1446 = 6'h16 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_22 :
    iss_stage__GEN_1445; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1447 = 6'h17 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_23 :
    iss_stage__GEN_1446; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1448 = 6'h18 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_24 :
    iss_stage__GEN_1447; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1449 = 6'h19 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_25 :
    iss_stage__GEN_1448; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1450 = 6'h1a == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_26 :
    iss_stage__GEN_1449; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1451 = 6'h1b == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_27 :
    iss_stage__GEN_1450; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1452 = 6'h1c == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_28 :
    iss_stage__GEN_1451; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1453 = 6'h1d == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_29 :
    iss_stage__GEN_1452; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1454 = 6'h1e == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_30 :
    iss_stage__GEN_1453; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1455 = 6'h1f == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_31 :
    iss_stage__GEN_1454; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1456 = 6'h20 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_32 :
    iss_stage__GEN_1455; // @[Issue.scala 238:{44,44}]
  wire [1:0] iss_stage__GEN_1457 = 6'h21 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_irgLog_33 :
    iss_stage__GEN_1456; // @[Issue.scala 238:{44,44}]
  wire  iss_stage__canIOpPostReq_0_1_T = iss_stage__GEN_1457 == 2'h3; // @[Issue.scala 238:44]
  wire  iss_stage__canIOpPostReq_0_1_T_1 = iss_stage_io_dptReq_0_bits_phy_rs2 != 6'h21; // @[Issue.scala 239:33]
  wire  iss_stage__canIOpPostReq_0_1_T_2 = iss_stage__canIOpPostReq_0_1_T & iss_stage__canIOpPostReq_0_1_T_1; // @[Issue.scala 238:56]
  wire  iss_stage__canIOpPostReq_0_1_T_51 = iss_stage__canIOpPostReq_0_1_T_2 & iss_stage__canIOpPostReq_0_0_T_50; // @[Issue.scala 239:50]
  wire  iss_stage__canIOpPostReq_0_1_T_52 = iss_stage_io_dptReq_0_bits_lsu_isa_fsw |
    iss_stage_io_dptReq_0_bits_lsu_isa_fsd; // @[riscv_isa.scala 164:20]
  wire  iss_stage__canIOpPostReq_0_1_T_53 = ~iss_stage__canIOpPostReq_0_1_T_52; // @[Issue.scala 240:44]
  wire  iss_stage__canIOpPostReq_0_1_T_54 = iss_stage__canIOpPostReq_0_1_T_51 & iss_stage__canIOpPostReq_0_1_T_53; // @[Issue.scala 240:42]
  wire  iss_stage__maskCondSelIRS1_0_0_T_1 = ~iss_stage__canIOpReq_0_0_T_8; // @[Issue.scala 256:51]
  wire  iss_stage__maskCondSelIRS1_0_0_T_2 = iss_stage__entrySel_T | iss_stage__maskCondSelIRS1_0_0_T_1; // @[Issue.scala 256:49]
  wire  iss_stage__maskCondSelIRS2_0_0_T_1 = ~iss_stage__canIOpReq_0_1_T_8; // @[Issue.scala 257:51]
  wire  iss_stage__maskCondSelIRS2_0_0_T_2 = iss_stage__entrySel_T | iss_stage__maskCondSelIRS2_0_0_T_1; // @[Issue.scala 257:49]
  wire  iss_stage__maskCondSelIRS1_0_1_T_1 = ~iss_stage__canIOpReq_1_0_T_8; // @[Issue.scala 256:51]
  wire  iss_stage__maskCondSelIRS1_0_1_T_2 = iss_stage__io_dptReq_0_ready_T_1 | iss_stage__maskCondSelIRS1_0_1_T_1; // @[Issue.scala 256:49]
  wire  iss_stage__maskCondSelIRS2_0_1_T_1 = ~iss_stage__canIOpReq_1_1_T_8; // @[Issue.scala 257:51]
  wire  iss_stage__maskCondSelIRS2_0_1_T_2 = iss_stage__io_dptReq_0_ready_T_1 | iss_stage__maskCondSelIRS2_0_1_T_1; // @[Issue.scala 257:49]
  wire  iss_stage__maskCondSelIRS1_0_2_T_1 = ~iss_stage__T; // @[Issue.scala 260:45]
  wire  iss_stage__maskCondSelIRS1_0_2_T_2 = ~iss_stage__canIOpPostReq_0_0_T_51; // @[Issue.scala 260:66]
  wire  iss_stage__maskCondSelIRS1_0_2_T_3 = iss_stage__maskCondSelIRS1_0_2_T_1 | iss_stage__maskCondSelIRS1_0_2_T_2; // @[Issue.scala 260:64]
  wire  iss_stage__maskCondSelIRS2_0_2_T_2 = ~iss_stage__canIOpPostReq_0_1_T_54; // @[Issue.scala 261:66]
  wire  iss_stage__maskCondSelIRS2_0_2_T_3 = iss_stage__maskCondSelIRS1_0_2_T_1 | iss_stage__maskCondSelIRS2_0_2_T_2; // @[Issue.scala 261:64]
  wire  iss_stage__matrixOut_0_0_T = ~iss_stage__maskCondSelIRS1_0_0_T_2; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_0_T_1 = iss_stage_ageMatrixW_0_0 & iss_stage__matrixOut_0_0_T; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_0_T_2 = iss_stage__matrixOut_0_0_T_1 | iss_stage__maskCondSelIRS1_0_0_T_2; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_1_T = ~iss_stage__maskCondSelIRS1_0_1_T_2; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_1_T_1 = iss_stage_ageMatrixW_0_1 & iss_stage__matrixOut_0_1_T; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_1_T_2 = iss_stage__matrixOut_0_1_T_1 | iss_stage__maskCondSelIRS1_0_0_T_2; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_2_T = ~iss_stage__maskCondSelIRS1_0_2_T_3; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_1_0_T_1 = iss_stage__ageMatrixR_1_0_T & iss_stage__matrixOut_0_0_T; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_0_T_2 = iss_stage__matrixOut_1_0_T_1 | iss_stage__maskCondSelIRS1_0_1_T_2; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_1_T_1 = iss_stage_ageMatrixW_1_1 & iss_stage__matrixOut_0_1_T; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_1_T_2 = iss_stage__matrixOut_1_1_T_1 | iss_stage__maskCondSelIRS1_0_1_T_2; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_2_0_T_2 = iss_stage__matrixOut_0_0_T | iss_stage__maskCondSelIRS1_0_2_T_3; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_2_1_T_2 = iss_stage__matrixOut_0_1_T | iss_stage__maskCondSelIRS1_0_2_T_3; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_0_T_3 = ~iss_stage__maskCondSelIRS2_0_0_T_2; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_0_T_4 = iss_stage_ageMatrixW_0_0 & iss_stage__matrixOut_0_0_T_3; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_0_T_5 = iss_stage__matrixOut_0_0_T_4 | iss_stage__maskCondSelIRS2_0_0_T_2; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_1_T_3 = ~iss_stage__maskCondSelIRS2_0_1_T_2; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_1_T_4 = iss_stage_ageMatrixW_0_1 & iss_stage__matrixOut_0_1_T_3; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_1_T_5 = iss_stage__matrixOut_0_1_T_4 | iss_stage__maskCondSelIRS2_0_0_T_2; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_2_T_3 = ~iss_stage__maskCondSelIRS2_0_2_T_3; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_1_0_T_4 = iss_stage__ageMatrixR_1_0_T & iss_stage__matrixOut_0_0_T_3; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_0_T_5 = iss_stage__matrixOut_1_0_T_4 | iss_stage__maskCondSelIRS2_0_1_T_2; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_1_T_4 = iss_stage_ageMatrixW_1_1 & iss_stage__matrixOut_0_1_T_3; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_1_T_5 = iss_stage__matrixOut_1_1_T_4 | iss_stage__maskCondSelIRS2_0_1_T_2; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_2_0_T_5 = iss_stage__matrixOut_0_0_T_3 | iss_stage__maskCondSelIRS2_0_2_T_3; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_2_1_T_5 = iss_stage__matrixOut_0_1_T_3 | iss_stage__maskCondSelIRS2_0_2_T_3; // @[Issue.scala 200:60]
  wire  iss_stage__T_11 = iss_stage__matrixOut_0_0_T_2 & iss_stage__matrixOut_0_1_T_2; // @[Issue.scala 277:60]
  wire  iss_stage__T_12 = iss_stage__T_11 & iss_stage__maskCondSelIRS1_0_0_T_2; // @[Issue.scala 277:60]
  wire  iss_stage__T_17 = iss_stage__matrixOut_1_0_T_2 & iss_stage__matrixOut_1_1_T_2; // @[Issue.scala 277:60]
  wire  iss_stage__T_18 = iss_stage__T_17 & iss_stage__maskCondSelIRS1_0_1_T_2; // @[Issue.scala 277:60]
  wire  iss_stage__T_23 = iss_stage__matrixOut_2_0_T_2 & iss_stage__matrixOut_2_1_T_2; // @[Issue.scala 277:60]
  wire  iss_stage__T_24 = iss_stage__T_23 & iss_stage__maskCondSelIRS1_0_2_T_3; // @[Issue.scala 277:60]
  wire  iss_stage__T_26 = iss_stage__T_12 & iss_stage__T_18; // @[Issue.scala 277:32]
  wire  iss_stage__T_27 = iss_stage__T_26 & iss_stage__T_24; // @[Issue.scala 277:32]
  wire  iss_stage__T_28 = ~iss_stage__matrixOut_0_0_T_2; // @[Issue.scala 278:83]
  wire  iss_stage__T_29 = ~iss_stage__matrixOut_0_1_T_2; // @[Issue.scala 278:83]
  wire  iss_stage__T_32 = iss_stage__T_28 & iss_stage__T_29; // @[Issue.scala 278:66]
  wire  iss_stage__T_33 = iss_stage__T_32 & iss_stage__matrixOut_0_0_T; // @[Issue.scala 278:66]
  wire  iss_stage__T_34 = ~iss_stage__matrixOut_1_0_T_2; // @[Issue.scala 278:83]
  wire  iss_stage__T_35 = ~iss_stage__matrixOut_1_1_T_2; // @[Issue.scala 278:83]
  wire  iss_stage__T_38 = iss_stage__T_34 & iss_stage__T_35; // @[Issue.scala 278:66]
  wire  iss_stage__T_39 = iss_stage__T_38 & iss_stage__matrixOut_0_1_T; // @[Issue.scala 278:66]
  wire  iss_stage__T_40 = ~iss_stage__matrixOut_2_0_T_2; // @[Issue.scala 278:83]
  wire  iss_stage__T_41 = ~iss_stage__matrixOut_2_1_T_2; // @[Issue.scala 278:83]
  wire  iss_stage__T_44 = iss_stage__T_40 & iss_stage__T_41; // @[Issue.scala 278:66]
  wire  iss_stage__T_45 = iss_stage__T_44 & iss_stage__matrixOut_0_2_T; // @[Issue.scala 278:66]
  wire [1:0] iss_stage__T_46 = iss_stage__T_39 + iss_stage__T_45; // @[Bitwise.scala 51:90]
  wire [1:0] _GEN_230 = {{1'd0}, iss_stage__T_33}; // @[Bitwise.scala 51:90]
  wire [2:0] iss_stage__T_48 = _GEN_230 + iss_stage__T_46; // @[Bitwise.scala 51:90]
  wire [1:0] iss_stage__T_49 = iss_stage__T_48[1:0]; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_50 = iss_stage__T_49 == 2'h1; // @[Issue.scala 278:101]
  wire  iss_stage__T_51 = iss_stage__T_27 | iss_stage__T_50; // @[Issue.scala 277:92]
  wire  iss_stage__T_53 = ~iss_stage_reset; // @[Issue.scala 276:11]
  wire  iss_stage__T_54 = ~iss_stage__T_51; // @[Issue.scala 276:11]
  wire  iss_stage__T_59 = iss_stage__matrixOut_0_0_T_5 & iss_stage__matrixOut_0_1_T_5; // @[Issue.scala 282:60]
  wire  iss_stage__T_60 = iss_stage__T_59 & iss_stage__maskCondSelIRS2_0_0_T_2; // @[Issue.scala 282:60]
  wire  iss_stage__T_65 = iss_stage__matrixOut_1_0_T_5 & iss_stage__matrixOut_1_1_T_5; // @[Issue.scala 282:60]
  wire  iss_stage__T_66 = iss_stage__T_65 & iss_stage__maskCondSelIRS2_0_1_T_2; // @[Issue.scala 282:60]
  wire  iss_stage__T_71 = iss_stage__matrixOut_2_0_T_5 & iss_stage__matrixOut_2_1_T_5; // @[Issue.scala 282:60]
  wire  iss_stage__T_72 = iss_stage__T_71 & iss_stage__maskCondSelIRS2_0_2_T_3; // @[Issue.scala 282:60]
  wire  iss_stage__T_74 = iss_stage__T_60 & iss_stage__T_66; // @[Issue.scala 282:32]
  wire  iss_stage__T_75 = iss_stage__T_74 & iss_stage__T_72; // @[Issue.scala 282:32]
  wire  iss_stage__T_76 = ~iss_stage__matrixOut_0_0_T_5; // @[Issue.scala 283:83]
  wire  iss_stage__T_77 = ~iss_stage__matrixOut_0_1_T_5; // @[Issue.scala 283:83]
  wire  iss_stage__T_80 = iss_stage__T_76 & iss_stage__T_77; // @[Issue.scala 283:66]
  wire  iss_stage__T_81 = iss_stage__T_80 & iss_stage__matrixOut_0_0_T_3; // @[Issue.scala 283:66]
  wire  iss_stage__T_82 = ~iss_stage__matrixOut_1_0_T_5; // @[Issue.scala 283:83]
  wire  iss_stage__T_83 = ~iss_stage__matrixOut_1_1_T_5; // @[Issue.scala 283:83]
  wire  iss_stage__T_86 = iss_stage__T_82 & iss_stage__T_83; // @[Issue.scala 283:66]
  wire  iss_stage__T_87 = iss_stage__T_86 & iss_stage__matrixOut_0_1_T_3; // @[Issue.scala 283:66]
  wire  iss_stage__T_88 = ~iss_stage__matrixOut_2_0_T_5; // @[Issue.scala 283:83]
  wire  iss_stage__T_89 = ~iss_stage__matrixOut_2_1_T_5; // @[Issue.scala 283:83]
  wire  iss_stage__T_92 = iss_stage__T_88 & iss_stage__T_89; // @[Issue.scala 283:66]
  wire  iss_stage__T_93 = iss_stage__T_92 & iss_stage__matrixOut_0_2_T_3; // @[Issue.scala 283:66]
  wire [1:0] iss_stage__T_94 = iss_stage__T_87 + iss_stage__T_93; // @[Bitwise.scala 51:90]
  wire [1:0] _GEN_231 = {{1'd0}, iss_stage__T_81}; // @[Bitwise.scala 51:90]
  wire [2:0] iss_stage__T_96 = _GEN_231 + iss_stage__T_94; // @[Bitwise.scala 51:90]
  wire [1:0] iss_stage__T_97 = iss_stage__T_96[1:0]; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_98 = iss_stage__T_97 == 2'h1; // @[Issue.scala 283:101]
  wire  iss_stage__T_99 = iss_stage__T_75 | iss_stage__T_98; // @[Issue.scala 282:93]
  wire  iss_stage__T_102 = ~iss_stage__T_99; // @[Issue.scala 281:11]
  wire [5:0] iss_stage__selIRS1_0_T_18 = iss_stage__T_33 ? iss_stage_bufInfo_0_phy_rs1 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS1_0_T_19 = iss_stage__T_39 ? iss_stage_bufInfo_1_phy_rs1 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS1_0_T_20 = iss_stage__T_45 ? iss_stage_io_dptReq_0_bits_phy_rs1 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS1_0_T_21 = iss_stage__selIRS1_0_T_18 | iss_stage__selIRS1_0_T_19; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS1_0_T_22 = iss_stage__selIRS1_0_T_21 | iss_stage__selIRS1_0_T_20; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS2_0_T_18 = iss_stage__T_81 ? iss_stage_bufInfo_0_phy_rs2 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS2_0_T_19 = iss_stage__T_87 ? iss_stage_bufInfo_1_phy_rs2 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS2_0_T_20 = iss_stage__T_93 ? iss_stage_io_dptReq_0_bits_phy_rs2 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS2_0_T_21 = iss_stage__selIRS2_0_T_18 | iss_stage__selIRS2_0_T_19; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__selIRS2_0_T_22 = iss_stage__selIRS2_0_T_21 | iss_stage__selIRS2_0_T_20; // @[Mux.scala 27:73]
  wire  iss_stage__rIOpNum_0_T = ~iss_stage__T_27; // @[Issue.scala 313:28]
  wire  iss_stage__rIOpNum_0_T_1 = ~iss_stage__T_75; // @[Issue.scala 313:68]
  wire [5:0] iss_stage__rIOpNum_0_T_2 = iss_stage__rIOpNum_0_T_1 ? iss_stage__selIRS2_0_T_22 : 6'h21; // @[Issue.scala 313:66]
  wire [1:0] iss_stage__GEN_1663 = 6'h1 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_1 :
    iss_stage_io_frgLog_0; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1664 = 6'h2 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_2 :
    iss_stage__GEN_1663; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1665 = 6'h3 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_3 :
    iss_stage__GEN_1664; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1666 = 6'h4 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_4 :
    iss_stage__GEN_1665; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1667 = 6'h5 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_5 :
    iss_stage__GEN_1666; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1668 = 6'h6 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_6 :
    iss_stage__GEN_1667; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1669 = 6'h7 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_7 :
    iss_stage__GEN_1668; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1670 = 6'h8 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_8 :
    iss_stage__GEN_1669; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1671 = 6'h9 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_9 :
    iss_stage__GEN_1670; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1672 = 6'ha == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_10 :
    iss_stage__GEN_1671; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1673 = 6'hb == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_11 :
    iss_stage__GEN_1672; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1674 = 6'hc == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_12 :
    iss_stage__GEN_1673; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1675 = 6'hd == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_13 :
    iss_stage__GEN_1674; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1676 = 6'he == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_14 :
    iss_stage__GEN_1675; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1677 = 6'hf == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_15 :
    iss_stage__GEN_1676; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1678 = 6'h10 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_16 :
    iss_stage__GEN_1677; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1679 = 6'h11 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_17 :
    iss_stage__GEN_1678; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1680 = 6'h12 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_18 :
    iss_stage__GEN_1679; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1681 = 6'h13 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_19 :
    iss_stage__GEN_1680; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1682 = 6'h14 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_20 :
    iss_stage__GEN_1681; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1683 = 6'h15 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_21 :
    iss_stage__GEN_1682; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1684 = 6'h16 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_22 :
    iss_stage__GEN_1683; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1685 = 6'h17 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_23 :
    iss_stage__GEN_1684; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1686 = 6'h18 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_24 :
    iss_stage__GEN_1685; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1687 = 6'h19 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_25 :
    iss_stage__GEN_1686; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1688 = 6'h1a == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_26 :
    iss_stage__GEN_1687; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1689 = 6'h1b == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_27 :
    iss_stage__GEN_1688; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1690 = 6'h1c == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_28 :
    iss_stage__GEN_1689; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1691 = 6'h1d == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_29 :
    iss_stage__GEN_1690; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1692 = 6'h1e == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_30 :
    iss_stage__GEN_1691; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1693 = 6'h1f == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_31 :
    iss_stage__GEN_1692; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1694 = 6'h20 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_32 :
    iss_stage__GEN_1693; // @[Issue.scala 356:{44,44}]
  wire [1:0] iss_stage__GEN_1695 = 6'h21 == iss_stage_io_dptReq_0_bits_phy_rs1 ? iss_stage_io_frgLog_33 :
    iss_stage__GEN_1694; // @[Issue.scala 356:{44,44}]
  wire  iss_stage__canFOpPostReq_0_0_T = iss_stage__GEN_1695 == 2'h3; // @[Issue.scala 356:44]
  wire  iss_stage__canFOpPostReq_0_0_T_2 = iss_stage__canFOpPostReq_0_0_T & iss_stage__canIOpPostReq_0_0_T_1; // @[Issue.scala 356:56]
  wire  iss_stage__canFOpPostReq_0_0_T_50 = iss_stage__canFOpPostReq_0_0_T_2 & iss_stage__canIOpPostReq_0_0_T_49; // @[Issue.scala 357:50]
  wire [1:0] iss_stage__GEN_1697 = 6'h1 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_1 :
    iss_stage_io_frgLog_0; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1698 = 6'h2 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_2 :
    iss_stage__GEN_1697; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1699 = 6'h3 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_3 :
    iss_stage__GEN_1698; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1700 = 6'h4 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_4 :
    iss_stage__GEN_1699; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1701 = 6'h5 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_5 :
    iss_stage__GEN_1700; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1702 = 6'h6 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_6 :
    iss_stage__GEN_1701; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1703 = 6'h7 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_7 :
    iss_stage__GEN_1702; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1704 = 6'h8 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_8 :
    iss_stage__GEN_1703; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1705 = 6'h9 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_9 :
    iss_stage__GEN_1704; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1706 = 6'ha == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_10 :
    iss_stage__GEN_1705; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1707 = 6'hb == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_11 :
    iss_stage__GEN_1706; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1708 = 6'hc == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_12 :
    iss_stage__GEN_1707; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1709 = 6'hd == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_13 :
    iss_stage__GEN_1708; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1710 = 6'he == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_14 :
    iss_stage__GEN_1709; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1711 = 6'hf == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_15 :
    iss_stage__GEN_1710; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1712 = 6'h10 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_16 :
    iss_stage__GEN_1711; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1713 = 6'h11 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_17 :
    iss_stage__GEN_1712; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1714 = 6'h12 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_18 :
    iss_stage__GEN_1713; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1715 = 6'h13 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_19 :
    iss_stage__GEN_1714; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1716 = 6'h14 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_20 :
    iss_stage__GEN_1715; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1717 = 6'h15 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_21 :
    iss_stage__GEN_1716; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1718 = 6'h16 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_22 :
    iss_stage__GEN_1717; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1719 = 6'h17 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_23 :
    iss_stage__GEN_1718; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1720 = 6'h18 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_24 :
    iss_stage__GEN_1719; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1721 = 6'h19 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_25 :
    iss_stage__GEN_1720; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1722 = 6'h1a == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_26 :
    iss_stage__GEN_1721; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1723 = 6'h1b == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_27 :
    iss_stage__GEN_1722; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1724 = 6'h1c == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_28 :
    iss_stage__GEN_1723; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1725 = 6'h1d == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_29 :
    iss_stage__GEN_1724; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1726 = 6'h1e == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_30 :
    iss_stage__GEN_1725; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1727 = 6'h1f == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_31 :
    iss_stage__GEN_1726; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1728 = 6'h20 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_32 :
    iss_stage__GEN_1727; // @[Issue.scala 362:{44,44}]
  wire [1:0] iss_stage__GEN_1729 = 6'h21 == iss_stage_io_dptReq_0_bits_phy_rs2 ? iss_stage_io_frgLog_33 :
    iss_stage__GEN_1728; // @[Issue.scala 362:{44,44}]
  wire  iss_stage__canFOpPostReq_0_1_T = iss_stage__GEN_1729 == 2'h3; // @[Issue.scala 362:44]
  wire  iss_stage__canFOpPostReq_0_1_T_2 = iss_stage__canFOpPostReq_0_1_T & iss_stage__canIOpPostReq_0_1_T_1; // @[Issue.scala 362:56]
  wire  iss_stage__canFOpPostReq_0_1_T_51 = iss_stage__canIOpPostReq_0_0_T_49 | iss_stage__canIOpPostReq_0_1_T_52; // @[Issue.scala 364:41]
  wire  iss_stage__canFOpPostReq_0_1_T_52 = iss_stage__canFOpPostReq_0_1_T_2 & iss_stage__canFOpPostReq_0_1_T_51; // @[Issue.scala 363:50]
  wire [1:0] iss_stage__GEN_1731 = 6'h1 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_1 :
    iss_stage_io_frgLog_0; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1732 = 6'h2 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_2 :
    iss_stage__GEN_1731; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1733 = 6'h3 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_3 :
    iss_stage__GEN_1732; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1734 = 6'h4 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_4 :
    iss_stage__GEN_1733; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1735 = 6'h5 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_5 :
    iss_stage__GEN_1734; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1736 = 6'h6 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_6 :
    iss_stage__GEN_1735; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1737 = 6'h7 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_7 :
    iss_stage__GEN_1736; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1738 = 6'h8 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_8 :
    iss_stage__GEN_1737; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1739 = 6'h9 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_9 :
    iss_stage__GEN_1738; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1740 = 6'ha == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_10 :
    iss_stage__GEN_1739; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1741 = 6'hb == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_11 :
    iss_stage__GEN_1740; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1742 = 6'hc == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_12 :
    iss_stage__GEN_1741; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1743 = 6'hd == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_13 :
    iss_stage__GEN_1742; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1744 = 6'he == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_14 :
    iss_stage__GEN_1743; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1745 = 6'hf == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_15 :
    iss_stage__GEN_1744; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1746 = 6'h10 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_16 :
    iss_stage__GEN_1745; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1747 = 6'h11 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_17 :
    iss_stage__GEN_1746; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1748 = 6'h12 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_18 :
    iss_stage__GEN_1747; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1749 = 6'h13 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_19 :
    iss_stage__GEN_1748; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1750 = 6'h14 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_20 :
    iss_stage__GEN_1749; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1751 = 6'h15 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_21 :
    iss_stage__GEN_1750; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1752 = 6'h16 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_22 :
    iss_stage__GEN_1751; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1753 = 6'h17 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_23 :
    iss_stage__GEN_1752; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1754 = 6'h18 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_24 :
    iss_stage__GEN_1753; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1755 = 6'h19 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_25 :
    iss_stage__GEN_1754; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1756 = 6'h1a == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_26 :
    iss_stage__GEN_1755; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1757 = 6'h1b == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_27 :
    iss_stage__GEN_1756; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1758 = 6'h1c == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_28 :
    iss_stage__GEN_1757; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1759 = 6'h1d == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_29 :
    iss_stage__GEN_1758; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1760 = 6'h1e == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_30 :
    iss_stage__GEN_1759; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1761 = 6'h1f == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_31 :
    iss_stage__GEN_1760; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1762 = 6'h20 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_32 :
    iss_stage__GEN_1761; // @[Issue.scala 368:{44,44}]
  wire [1:0] iss_stage__GEN_1763 = 6'h21 == iss_stage_io_dptReq_0_bits_phy_rs3 ? iss_stage_io_frgLog_33 :
    iss_stage__GEN_1762; // @[Issue.scala 368:{44,44}]
  wire  iss_stage__canFOpPostReq_0_2_T = iss_stage__GEN_1763 == 2'h3; // @[Issue.scala 368:44]
  wire  iss_stage__canFOpPostReq_0_2_T_1 = iss_stage_io_dptReq_0_bits_phy_rs3 != 6'h21; // @[Issue.scala 369:33]
  wire  iss_stage__canFOpPostReq_0_2_T_2 = iss_stage__canFOpPostReq_0_2_T & iss_stage__canFOpPostReq_0_2_T_1; // @[Issue.scala 368:56]
  wire  iss_stage__canFOpPostReq_0_2_T_50 = iss_stage__canFOpPostReq_0_2_T_2 & iss_stage__canIOpPostReq_0_0_T_49; // @[Issue.scala 369:50]
  wire  iss_stage__maskCondSelFRS1_0_2_T_2 = ~iss_stage__canFOpPostReq_0_0_T_50; // @[Issue.scala 392:66]
  wire  iss_stage__maskCondSelFRS1_0_2_T_3 = iss_stage__maskCondSelIRS1_0_2_T_1 | iss_stage__maskCondSelFRS1_0_2_T_2; // @[Issue.scala 392:64]
  wire  iss_stage__maskCondSelFRS2_0_2_T_2 = ~iss_stage__canFOpPostReq_0_1_T_52; // @[Issue.scala 393:66]
  wire  iss_stage__maskCondSelFRS2_0_2_T_3 = iss_stage__maskCondSelIRS1_0_2_T_1 | iss_stage__maskCondSelFRS2_0_2_T_2; // @[Issue.scala 393:64]
  wire  iss_stage__maskCondSelFRS3_0_2_T_2 = ~iss_stage__canFOpPostReq_0_2_T_50; // @[Issue.scala 394:66]
  wire  iss_stage__maskCondSelFRS3_0_2_T_3 = iss_stage__maskCondSelIRS1_0_2_T_1 | iss_stage__maskCondSelFRS3_0_2_T_2; // @[Issue.scala 394:64]
  wire  iss_stage__matrixOut_0_2_T_6 = ~iss_stage__maskCondSelFRS1_0_2_T_3; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_2_T_9 = ~iss_stage__maskCondSelFRS2_0_2_T_3; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_2_T_12 = ~iss_stage__maskCondSelFRS3_0_2_T_3; // @[Issue.scala 200:46]
  wire  iss_stage__T_140 = iss_stage__matrixOut_0_2_T_6 & iss_stage__matrixOut_0_2_T_6; // @[Issue.scala 414:66]
  wire  iss_stage__T_141 = iss_stage__T_140 & iss_stage__matrixOut_0_2_T_6; // @[Issue.scala 414:66]
  wire [1:0] iss_stage__T_142 = {{1'd0}, iss_stage__T_141}; // @[Bitwise.scala 51:90]
  wire [2:0] iss_stage__T_144 = {{1'd0}, iss_stage__T_142}; // @[Bitwise.scala 51:90]
  wire [1:0] iss_stage__T_145 = iss_stage__T_144[1:0]; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_146 = iss_stage__T_145 == 2'h1; // @[Issue.scala 414:101]
  wire  iss_stage__T_147 = iss_stage__maskCondSelFRS1_0_2_T_3 | iss_stage__T_146; // @[Issue.scala 413:92]
  wire  iss_stage__T_150 = ~iss_stage__T_147; // @[Issue.scala 412:11]
  wire  iss_stage__T_188 = iss_stage__matrixOut_0_2_T_9 & iss_stage__matrixOut_0_2_T_9; // @[Issue.scala 419:66]
  wire  iss_stage__T_189 = iss_stage__T_188 & iss_stage__matrixOut_0_2_T_9; // @[Issue.scala 419:66]
  wire [1:0] iss_stage__T_190 = {{1'd0}, iss_stage__T_189}; // @[Bitwise.scala 51:90]
  wire [2:0] iss_stage__T_192 = {{1'd0}, iss_stage__T_190}; // @[Bitwise.scala 51:90]
  wire [1:0] iss_stage__T_193 = iss_stage__T_192[1:0]; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_194 = iss_stage__T_193 == 2'h1; // @[Issue.scala 419:101]
  wire  iss_stage__T_195 = iss_stage__maskCondSelFRS2_0_2_T_3 | iss_stage__T_194; // @[Issue.scala 418:93]
  wire  iss_stage__T_198 = ~iss_stage__T_195; // @[Issue.scala 417:11]
  wire  iss_stage__T_236 = iss_stage__matrixOut_0_2_T_12 & iss_stage__matrixOut_0_2_T_12; // @[Issue.scala 424:66]
  wire  iss_stage__T_237 = iss_stage__T_236 & iss_stage__matrixOut_0_2_T_12; // @[Issue.scala 424:66]
  wire [1:0] iss_stage__T_238 = {{1'd0}, iss_stage__T_237}; // @[Bitwise.scala 51:90]
  wire [2:0] iss_stage__T_240 = {{1'd0}, iss_stage__T_238}; // @[Bitwise.scala 51:90]
  wire [1:0] iss_stage__T_241 = iss_stage__T_240[1:0]; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_242 = iss_stage__T_241 == 2'h1; // @[Issue.scala 424:101]
  wire  iss_stage__T_243 = iss_stage__maskCondSelFRS3_0_2_T_3 | iss_stage__T_242; // @[Issue.scala 423:93]
  wire  iss_stage__T_246 = ~iss_stage__T_243; // @[Issue.scala 422:11]
  wire  iss_stage__T_247 = iss_stage_bufInfo_0_phy_rs1 == iss_stage_io_irgRsp_0_bits_phy; // @[Issue.scala 489:49]
  wire  iss_stage__T_248 = iss_stage_bufValid_0 & iss_stage__T_247; // @[Issue.scala 489:29]
  wire  iss_stage__GEN_1764 = iss_stage__T_248 | iss_stage__GEN_1230; // @[Issue.scala 489:98 491:32]
  wire  iss_stage__T_252 = iss_stage_bufInfo_0_phy_rs2 == iss_stage_io_irgRsp_0_bits_phy; // @[Issue.scala 489:49]
  wire  iss_stage__T_253 = iss_stage_bufValid_0 & iss_stage__T_252; // @[Issue.scala 489:29]
  wire  iss_stage__GEN_1766 = iss_stage__T_253 | iss_stage__GEN_1234; // @[Issue.scala 489:98 491:32]
  wire  iss_stage__T_257 = iss_stage_bufInfo_1_phy_rs1 == iss_stage_io_irgRsp_0_bits_phy; // @[Issue.scala 489:49]
  wire  iss_stage__T_258 = iss_stage_bufValid_1 & iss_stage__T_257; // @[Issue.scala 489:29]
  wire  iss_stage__GEN_1768 = iss_stage__T_258 | iss_stage__GEN_1231; // @[Issue.scala 489:98 491:32]
  wire  iss_stage__T_262 = iss_stage_bufInfo_1_phy_rs2 == iss_stage_io_irgRsp_0_bits_phy; // @[Issue.scala 489:49]
  wire  iss_stage__T_263 = iss_stage_bufValid_1 & iss_stage__T_262; // @[Issue.scala 489:29]
  wire  iss_stage__GEN_1770 = iss_stage__T_263 | iss_stage__GEN_1235; // @[Issue.scala 489:98 491:32]
  wire  iss_stage__postIsOpReady_0_0_T_8 = iss_stage__canIOpReq_0_0_T_6 | iss_stage_isOpReady_0_0; // @[Mux.scala 101:16]
  wire  iss_stage__postIsOpReady_0_1_T_8 = iss_stage__canIOpReq_0_1_T_6 | iss_stage_isOpReady_0_1; // @[Mux.scala 101:16]
  wire [64:0] iss_stage__postBufOperator_0_0_T_8 = iss_stage__canIOpReq_0_0_T_6 ? {{1'd0}, iss_stage_io_irgRsp_0_bits_op
    } : iss_stage_bufOperator_0_0; // @[Mux.scala 101:16]
  wire [64:0] iss_stage__postBufOperator_0_1_T_8 = iss_stage__canIOpReq_0_1_T_6 ? {{1'd0}, iss_stage_io_irgRsp_0_bits_op
    } : iss_stage_bufOperator_0_1; // @[Mux.scala 101:16]
  wire  iss_stage__postIsOpReady_1_0_T_8 = iss_stage__canIOpReq_1_0_T_6 | iss_stage_isOpReady_1_0; // @[Mux.scala 101:16]
  wire  iss_stage__postIsOpReady_1_1_T_8 = iss_stage__canIOpReq_1_1_T_6 | iss_stage_isOpReady_1_1; // @[Mux.scala 101:16]
  wire [64:0] iss_stage__postBufOperator_1_0_T_8 = iss_stage__canIOpReq_1_0_T_6 ? {{1'd0}, iss_stage_io_irgRsp_0_bits_op
    } : iss_stage_bufOperator_1_0; // @[Mux.scala 101:16]
  wire [64:0] iss_stage__postBufOperator_1_1_T_8 = iss_stage__canIOpReq_1_1_T_6 ? {{1'd0}, iss_stage_io_irgRsp_0_bits_op
    } : iss_stage_bufOperator_1_1; // @[Mux.scala 101:16]
  wire  iss_stage__aluIssInfo_res_fun_add_T = iss_stage_bufInfo_0_alu_isa_addi | iss_stage_bufInfo_0_alu_isa_addiw; // @[riscv_isa.scala 69:25]
  wire  iss_stage__aluIssInfo_res_fun_add_T_1 = iss_stage__aluIssInfo_res_fun_add_T | iss_stage_bufInfo_0_alu_isa_add; // @[riscv_isa.scala 69:33]
  wire  iss_stage__aluIssInfo_res_fun_add_T_2 = iss_stage__aluIssInfo_res_fun_add_T_1 | iss_stage_bufInfo_0_alu_isa_addw
    ; // @[riscv_isa.scala 69:39]
  wire  iss_stage__aluIssInfo_res_fun_add_T_3 = iss_stage__aluIssInfo_res_fun_add_T_2 | iss_stage_bufInfo_0_alu_isa_lui; // @[riscv_isa.scala 69:46]
  wire  iss_stage__aluIssInfo_res_fun_add_T_4 = iss_stage__aluIssInfo_res_fun_add_T_3 |
    iss_stage_bufInfo_0_alu_isa_auipc; // @[riscv_isa.scala 69:52]
  wire  iss_stage__aluIssInfo_res_fun_add_T_5 = iss_stage__aluIssInfo_res_fun_add_T_4 | iss_stage_bufInfo_0_alu_isa_sub; // @[riscv_isa.scala 69:60]
  wire  iss_stage__aluIssInfo_res_fun_add_T_6 = iss_stage__aluIssInfo_res_fun_add_T_5 | iss_stage_bufInfo_0_alu_isa_subw
    ; // @[riscv_isa.scala 69:66]
  wire  iss_stage__aluIssInfo_res_fun_add_T_7 = iss_stage__aluIssInfo_res_fun_add_T_6 | iss_stage_bufInfo_0_alu_isa_wfi; // @[riscv_isa.scala 69:73]
  wire  iss_stage__aluIssInfo_res_fun_slt_T = iss_stage_bufInfo_0_alu_isa_slti | iss_stage_bufInfo_0_alu_isa_sltiu; // @[riscv_isa.scala 70:25]
  wire  iss_stage__aluIssInfo_res_fun_slt_T_1 = iss_stage__aluIssInfo_res_fun_slt_T | iss_stage_bufInfo_0_alu_isa_slt; // @[riscv_isa.scala 70:33]
  wire  iss_stage__aluIssInfo_res_fun_slt_T_2 = iss_stage__aluIssInfo_res_fun_slt_T_1 | iss_stage_bufInfo_0_alu_isa_sltu
    ; // @[riscv_isa.scala 70:39]
  wire  iss_stage__aluIssInfo_res_fun_xor_T = iss_stage_bufInfo_0_alu_isa_xori | iss_stage_bufInfo_0_alu_isa_xor; // @[riscv_isa.scala 71:25]
  wire  iss_stage__aluIssInfo_res_fun_or_T = iss_stage_bufInfo_0_alu_isa_ori | iss_stage_bufInfo_0_alu_isa_or; // @[riscv_isa.scala 72:24]
  wire  iss_stage__aluIssInfo_res_fun_and_T = iss_stage_bufInfo_0_alu_isa_andi | iss_stage_bufInfo_0_alu_isa_and; // @[riscv_isa.scala 73:25]
  wire  iss_stage__aluIssInfo_res_fun_sll_T = iss_stage_bufInfo_0_alu_isa_slli | iss_stage_bufInfo_0_alu_isa_slliw; // @[riscv_isa.scala 74:25]
  wire  iss_stage__aluIssInfo_res_fun_sll_T_1 = iss_stage__aluIssInfo_res_fun_sll_T | iss_stage_bufInfo_0_alu_isa_sll; // @[riscv_isa.scala 74:33]
  wire  iss_stage__aluIssInfo_res_fun_sll_T_2 = iss_stage__aluIssInfo_res_fun_sll_T_1 | iss_stage_bufInfo_0_alu_isa_sllw
    ; // @[riscv_isa.scala 74:39]
  wire  iss_stage__aluIssInfo_res_fun_srl_T = iss_stage_bufInfo_0_alu_isa_srli | iss_stage_bufInfo_0_alu_isa_srliw; // @[riscv_isa.scala 75:25]
  wire  iss_stage__aluIssInfo_res_fun_srl_T_1 = iss_stage__aluIssInfo_res_fun_srl_T | iss_stage_bufInfo_0_alu_isa_srl; // @[riscv_isa.scala 75:33]
  wire  iss_stage__aluIssInfo_res_fun_srl_T_2 = iss_stage__aluIssInfo_res_fun_srl_T_1 | iss_stage_bufInfo_0_alu_isa_srlw
    ; // @[riscv_isa.scala 75:39]
  wire  iss_stage__aluIssInfo_res_fun_sra_T = iss_stage_bufInfo_0_alu_isa_srai | iss_stage_bufInfo_0_alu_isa_sraiw; // @[riscv_isa.scala 76:25]
  wire  iss_stage__aluIssInfo_res_fun_sra_T_1 = iss_stage__aluIssInfo_res_fun_sra_T | iss_stage_bufInfo_0_alu_isa_sra; // @[riscv_isa.scala 76:33]
  wire  iss_stage__aluIssInfo_res_fun_sra_T_2 = iss_stage__aluIssInfo_res_fun_sra_T_1 | iss_stage_bufInfo_0_alu_isa_sraw
    ; // @[riscv_isa.scala 76:39]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T = iss_stage_bufInfo_0_alu_isa_addiw | iss_stage_bufInfo_0_alu_isa_addw; // @[riscv_isa.scala 65:22]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_1 = iss_stage__aluIssInfo_res_param_is_32w_T |
    iss_stage_bufInfo_0_alu_isa_subw; // @[riscv_isa.scala 65:29]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_2 = iss_stage__aluIssInfo_res_param_is_32w_T_1 |
    iss_stage_bufInfo_0_alu_isa_slliw; // @[riscv_isa.scala 65:36]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_3 = iss_stage__aluIssInfo_res_param_is_32w_T_2 |
    iss_stage_bufInfo_0_alu_isa_sllw; // @[riscv_isa.scala 65:44]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_4 = iss_stage__aluIssInfo_res_param_is_32w_T_3 |
    iss_stage_bufInfo_0_alu_isa_srliw; // @[riscv_isa.scala 65:51]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_5 = iss_stage__aluIssInfo_res_param_is_32w_T_4 |
    iss_stage_bufInfo_0_alu_isa_srlw; // @[riscv_isa.scala 65:59]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_6 = iss_stage__aluIssInfo_res_param_is_32w_T_5 |
    iss_stage_bufInfo_0_alu_isa_sraiw; // @[riscv_isa.scala 65:66]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_7 = iss_stage__aluIssInfo_res_param_is_32w_T_6 |
    iss_stage_bufInfo_0_alu_isa_sraw; // @[riscv_isa.scala 65:74]
  wire  iss_stage__aluIssInfo_res_param_is_usi_T = iss_stage_bufInfo_0_alu_isa_sltiu | iss_stage_bufInfo_0_alu_isa_sltu; // @[riscv_isa.scala 66:22]
  wire  iss_stage__aluIssInfo_res_param_dat_op1_v64_T = iss_stage_bufInfo_0_param_pc[38]; // @[Util.scala 47:31]
  wire [24:0] iss_stage__aluIssInfo_res_param_dat_op1_v64_T_2 = iss_stage__aluIssInfo_res_param_dat_op1_v64_T ? 25'h1ffffff
     : 25'h0; // @[Bitwise.scala 77:12]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op1_v64_T_4 = {iss_stage__aluIssInfo_res_param_dat_op1_v64_T_2,
    iss_stage_bufInfo_0_param_pc}; // @[Cat.scala 33:92]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op1_T_1 = iss_stage_bufInfo_0_alu_isa_auipc ?
    iss_stage__aluIssInfo_res_param_dat_op1_v64_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_2 = iss_stage_bufInfo_0_alu_isa_addi ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_3 = iss_stage_bufInfo_0_alu_isa_addiw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_4 = iss_stage_bufInfo_0_alu_isa_slti ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_5 = iss_stage_bufInfo_0_alu_isa_sltiu ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_6 = iss_stage_bufInfo_0_alu_isa_xori ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_7 = iss_stage_bufInfo_0_alu_isa_ori ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_8 = iss_stage_bufInfo_0_alu_isa_andi ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_9 = iss_stage_bufInfo_0_alu_isa_slli ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_10 = iss_stage_bufInfo_0_alu_isa_slliw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_11 = iss_stage_bufInfo_0_alu_isa_srli ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_12 = iss_stage_bufInfo_0_alu_isa_srliw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_13 = iss_stage_bufInfo_0_alu_isa_srai ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_14 = iss_stage_bufInfo_0_alu_isa_sraiw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_15 = iss_stage_bufInfo_0_alu_isa_add ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_16 = iss_stage_bufInfo_0_alu_isa_addw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_17 = iss_stage_bufInfo_0_alu_isa_sub ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_18 = iss_stage_bufInfo_0_alu_isa_subw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_19 = iss_stage_bufInfo_0_alu_isa_sll ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_20 = iss_stage_bufInfo_0_alu_isa_sllw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_21 = iss_stage_bufInfo_0_alu_isa_slt ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_22 = iss_stage_bufInfo_0_alu_isa_sltu ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_23 = iss_stage_bufInfo_0_alu_isa_xor ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_24 = iss_stage_bufInfo_0_alu_isa_srl ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_25 = iss_stage_bufInfo_0_alu_isa_srlw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_26 = iss_stage_bufInfo_0_alu_isa_sra ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_27 = iss_stage_bufInfo_0_alu_isa_sraw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_28 = iss_stage_bufInfo_0_alu_isa_or ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_29 = iss_stage_bufInfo_0_alu_isa_and ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] _GEN_232 = {{1'd0}, iss_stage__aluIssInfo_res_param_dat_op1_T_1}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_32 = _GEN_232 | iss_stage__aluIssInfo_res_param_dat_op1_T_2; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_33 = iss_stage__aluIssInfo_res_param_dat_op1_T_32 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_3; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_34 = iss_stage__aluIssInfo_res_param_dat_op1_T_33 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_4; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_35 = iss_stage__aluIssInfo_res_param_dat_op1_T_34 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_5; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_36 = iss_stage__aluIssInfo_res_param_dat_op1_T_35 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_6; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_37 = iss_stage__aluIssInfo_res_param_dat_op1_T_36 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_7; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_38 = iss_stage__aluIssInfo_res_param_dat_op1_T_37 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_8; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_39 = iss_stage__aluIssInfo_res_param_dat_op1_T_38 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_9; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_40 = iss_stage__aluIssInfo_res_param_dat_op1_T_39 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_10; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_41 = iss_stage__aluIssInfo_res_param_dat_op1_T_40 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_11; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_42 = iss_stage__aluIssInfo_res_param_dat_op1_T_41 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_12; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_43 = iss_stage__aluIssInfo_res_param_dat_op1_T_42 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_13; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_44 = iss_stage__aluIssInfo_res_param_dat_op1_T_43 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_14; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_45 = iss_stage__aluIssInfo_res_param_dat_op1_T_44 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_15; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_46 = iss_stage__aluIssInfo_res_param_dat_op1_T_45 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_16; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_47 = iss_stage__aluIssInfo_res_param_dat_op1_T_46 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_17; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_48 = iss_stage__aluIssInfo_res_param_dat_op1_T_47 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_18; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_49 = iss_stage__aluIssInfo_res_param_dat_op1_T_48 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_19; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_50 = iss_stage__aluIssInfo_res_param_dat_op1_T_49 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_20; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_51 = iss_stage__aluIssInfo_res_param_dat_op1_T_50 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_21; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_52 = iss_stage__aluIssInfo_res_param_dat_op1_T_51 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_22; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_53 = iss_stage__aluIssInfo_res_param_dat_op1_T_52 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_23; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_54 = iss_stage__aluIssInfo_res_param_dat_op1_T_53 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_24; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_55 = iss_stage__aluIssInfo_res_param_dat_op1_T_54 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_25; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_56 = iss_stage__aluIssInfo_res_param_dat_op1_T_55 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_26; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_57 = iss_stage__aluIssInfo_res_param_dat_op1_T_56 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_27; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_58 = iss_stage__aluIssInfo_res_param_dat_op1_T_57 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_28; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_59 = iss_stage__aluIssInfo_res_param_dat_op1_T_58 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_29; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T = iss_stage_bufInfo_0_param_imm[5:0]; // @[Issue.scala 582:122]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_6 = ~iss_stage__postBufOperator_0_1_T_8; // @[Issue.scala 586:101]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_8 = iss_stage__aluIssInfo_res_param_dat_op2_T_6 + 65'h1; // @[Issue.scala 586:107]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_12 = iss_stage_bufInfo_0_alu_isa_lui ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_13 = iss_stage_bufInfo_0_alu_isa_auipc ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_14 = iss_stage_bufInfo_0_alu_isa_addi ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_15 = iss_stage_bufInfo_0_alu_isa_addiw ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_16 = iss_stage_bufInfo_0_alu_isa_slti ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_17 = iss_stage_bufInfo_0_alu_isa_sltiu ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_18 = iss_stage_bufInfo_0_alu_isa_xori ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_19 = iss_stage_bufInfo_0_alu_isa_ori ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_20 = iss_stage_bufInfo_0_alu_isa_andi ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_21 = iss_stage_bufInfo_0_alu_isa_slli ?
    iss_stage__aluIssInfo_res_param_dat_op2_T : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_22 = iss_stage_bufInfo_0_alu_isa_slliw ?
    iss_stage__aluIssInfo_res_param_dat_op2_T : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_23 = iss_stage_bufInfo_0_alu_isa_srli ?
    iss_stage__aluIssInfo_res_param_dat_op2_T : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_24 = iss_stage_bufInfo_0_alu_isa_srliw ?
    iss_stage__aluIssInfo_res_param_dat_op2_T : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_25 = iss_stage_bufInfo_0_alu_isa_srai ?
    iss_stage__aluIssInfo_res_param_dat_op2_T : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_26 = iss_stage_bufInfo_0_alu_isa_sraiw ?
    iss_stage__aluIssInfo_res_param_dat_op2_T : 6'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_27 = iss_stage_bufInfo_0_alu_isa_add ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_28 = iss_stage_bufInfo_0_alu_isa_addw ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_29 = iss_stage_bufInfo_0_alu_isa_sub ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_30 = iss_stage_bufInfo_0_alu_isa_subw ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_31 = iss_stage_bufInfo_0_alu_isa_sll ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_32 = iss_stage_bufInfo_0_alu_isa_sllw ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_33 = iss_stage_bufInfo_0_alu_isa_slt ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_34 = iss_stage_bufInfo_0_alu_isa_sltu ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_35 = iss_stage_bufInfo_0_alu_isa_xor ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_36 = iss_stage_bufInfo_0_alu_isa_srl ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_37 = iss_stage_bufInfo_0_alu_isa_srlw ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_38 = iss_stage_bufInfo_0_alu_isa_sra ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_39 = iss_stage_bufInfo_0_alu_isa_sraw ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_40 = iss_stage_bufInfo_0_alu_isa_or ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_41 = iss_stage_bufInfo_0_alu_isa_and ?
    iss_stage__postBufOperator_0_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_43 = iss_stage__aluIssInfo_res_param_dat_op2_T_12 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_13; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_44 = iss_stage__aluIssInfo_res_param_dat_op2_T_43 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_14; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_45 = iss_stage__aluIssInfo_res_param_dat_op2_T_44 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_15; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_46 = iss_stage__aluIssInfo_res_param_dat_op2_T_45 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_16; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_47 = iss_stage__aluIssInfo_res_param_dat_op2_T_46 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_17; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_48 = iss_stage__aluIssInfo_res_param_dat_op2_T_47 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_18; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_49 = iss_stage__aluIssInfo_res_param_dat_op2_T_48 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_19; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_50 = iss_stage__aluIssInfo_res_param_dat_op2_T_49 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_20; // @[Mux.scala 27:73]
  wire [63:0] _GEN_233 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_21}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_51 = iss_stage__aluIssInfo_res_param_dat_op2_T_50 | _GEN_233; // @[Mux.scala 27:73]
  wire [63:0] _GEN_234 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_22}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_52 = iss_stage__aluIssInfo_res_param_dat_op2_T_51 | _GEN_234; // @[Mux.scala 27:73]
  wire [63:0] _GEN_235 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_23}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_53 = iss_stage__aluIssInfo_res_param_dat_op2_T_52 | _GEN_235; // @[Mux.scala 27:73]
  wire [63:0] _GEN_236 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_24}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_54 = iss_stage__aluIssInfo_res_param_dat_op2_T_53 | _GEN_236; // @[Mux.scala 27:73]
  wire [63:0] _GEN_237 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_25}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_55 = iss_stage__aluIssInfo_res_param_dat_op2_T_54 | _GEN_237; // @[Mux.scala 27:73]
  wire [63:0] _GEN_238 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_26}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_56 = iss_stage__aluIssInfo_res_param_dat_op2_T_55 | _GEN_238; // @[Mux.scala 27:73]
  wire [64:0] _GEN_239 = {{1'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_56}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_57 = _GEN_239 | iss_stage__aluIssInfo_res_param_dat_op2_T_27; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_58 = iss_stage__aluIssInfo_res_param_dat_op2_T_57 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_28; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_59 = iss_stage__aluIssInfo_res_param_dat_op2_T_58 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_29; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_60 = iss_stage__aluIssInfo_res_param_dat_op2_T_59 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_30; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_61 = iss_stage__aluIssInfo_res_param_dat_op2_T_60 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_31; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_62 = iss_stage__aluIssInfo_res_param_dat_op2_T_61 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_32; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_63 = iss_stage__aluIssInfo_res_param_dat_op2_T_62 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_33; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_64 = iss_stage__aluIssInfo_res_param_dat_op2_T_63 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_34; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_65 = iss_stage__aluIssInfo_res_param_dat_op2_T_64 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_35; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_66 = iss_stage__aluIssInfo_res_param_dat_op2_T_65 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_36; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_67 = iss_stage__aluIssInfo_res_param_dat_op2_T_66 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_37; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_68 = iss_stage__aluIssInfo_res_param_dat_op2_T_67 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_38; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_69 = iss_stage__aluIssInfo_res_param_dat_op2_T_68 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_39; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_70 = iss_stage__aluIssInfo_res_param_dat_op2_T_69 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_40; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_71 = iss_stage__aluIssInfo_res_param_dat_op2_T_70 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_41; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssInfo_res_fun_add_T_8 = iss_stage_bufInfo_1_alu_isa_addi | iss_stage_bufInfo_1_alu_isa_addiw; // @[riscv_isa.scala 69:25]
  wire  iss_stage__aluIssInfo_res_fun_add_T_9 = iss_stage__aluIssInfo_res_fun_add_T_8 | iss_stage_bufInfo_1_alu_isa_add; // @[riscv_isa.scala 69:33]
  wire  iss_stage__aluIssInfo_res_fun_add_T_10 = iss_stage__aluIssInfo_res_fun_add_T_9 |
    iss_stage_bufInfo_1_alu_isa_addw; // @[riscv_isa.scala 69:39]
  wire  iss_stage__aluIssInfo_res_fun_add_T_11 = iss_stage__aluIssInfo_res_fun_add_T_10 |
    iss_stage_bufInfo_1_alu_isa_lui; // @[riscv_isa.scala 69:46]
  wire  iss_stage__aluIssInfo_res_fun_add_T_12 = iss_stage__aluIssInfo_res_fun_add_T_11 |
    iss_stage_bufInfo_1_alu_isa_auipc; // @[riscv_isa.scala 69:52]
  wire  iss_stage__aluIssInfo_res_fun_add_T_13 = iss_stage__aluIssInfo_res_fun_add_T_12 |
    iss_stage_bufInfo_1_alu_isa_sub; // @[riscv_isa.scala 69:60]
  wire  iss_stage__aluIssInfo_res_fun_add_T_14 = iss_stage__aluIssInfo_res_fun_add_T_13 |
    iss_stage_bufInfo_1_alu_isa_subw; // @[riscv_isa.scala 69:66]
  wire  iss_stage__aluIssInfo_res_fun_add_T_15 = iss_stage__aluIssInfo_res_fun_add_T_14 |
    iss_stage_bufInfo_1_alu_isa_wfi; // @[riscv_isa.scala 69:73]
  wire  iss_stage__aluIssInfo_res_fun_slt_T_3 = iss_stage_bufInfo_1_alu_isa_slti | iss_stage_bufInfo_1_alu_isa_sltiu; // @[riscv_isa.scala 70:25]
  wire  iss_stage__aluIssInfo_res_fun_slt_T_4 = iss_stage__aluIssInfo_res_fun_slt_T_3 | iss_stage_bufInfo_1_alu_isa_slt; // @[riscv_isa.scala 70:33]
  wire  iss_stage__aluIssInfo_res_fun_slt_T_5 = iss_stage__aluIssInfo_res_fun_slt_T_4 | iss_stage_bufInfo_1_alu_isa_sltu
    ; // @[riscv_isa.scala 70:39]
  wire  iss_stage__aluIssInfo_res_fun_xor_T_1 = iss_stage_bufInfo_1_alu_isa_xori | iss_stage_bufInfo_1_alu_isa_xor; // @[riscv_isa.scala 71:25]
  wire  iss_stage__aluIssInfo_res_fun_or_T_1 = iss_stage_bufInfo_1_alu_isa_ori | iss_stage_bufInfo_1_alu_isa_or; // @[riscv_isa.scala 72:24]
  wire  iss_stage__aluIssInfo_res_fun_and_T_1 = iss_stage_bufInfo_1_alu_isa_andi | iss_stage_bufInfo_1_alu_isa_and; // @[riscv_isa.scala 73:25]
  wire  iss_stage__aluIssInfo_res_fun_sll_T_3 = iss_stage_bufInfo_1_alu_isa_slli | iss_stage_bufInfo_1_alu_isa_slliw; // @[riscv_isa.scala 74:25]
  wire  iss_stage__aluIssInfo_res_fun_sll_T_4 = iss_stage__aluIssInfo_res_fun_sll_T_3 | iss_stage_bufInfo_1_alu_isa_sll; // @[riscv_isa.scala 74:33]
  wire  iss_stage__aluIssInfo_res_fun_sll_T_5 = iss_stage__aluIssInfo_res_fun_sll_T_4 | iss_stage_bufInfo_1_alu_isa_sllw
    ; // @[riscv_isa.scala 74:39]
  wire  iss_stage__aluIssInfo_res_fun_srl_T_3 = iss_stage_bufInfo_1_alu_isa_srli | iss_stage_bufInfo_1_alu_isa_srliw; // @[riscv_isa.scala 75:25]
  wire  iss_stage__aluIssInfo_res_fun_srl_T_4 = iss_stage__aluIssInfo_res_fun_srl_T_3 | iss_stage_bufInfo_1_alu_isa_srl; // @[riscv_isa.scala 75:33]
  wire  iss_stage__aluIssInfo_res_fun_srl_T_5 = iss_stage__aluIssInfo_res_fun_srl_T_4 | iss_stage_bufInfo_1_alu_isa_srlw
    ; // @[riscv_isa.scala 75:39]
  wire  iss_stage__aluIssInfo_res_fun_sra_T_3 = iss_stage_bufInfo_1_alu_isa_srai | iss_stage_bufInfo_1_alu_isa_sraiw; // @[riscv_isa.scala 76:25]
  wire  iss_stage__aluIssInfo_res_fun_sra_T_4 = iss_stage__aluIssInfo_res_fun_sra_T_3 | iss_stage_bufInfo_1_alu_isa_sra; // @[riscv_isa.scala 76:33]
  wire  iss_stage__aluIssInfo_res_fun_sra_T_5 = iss_stage__aluIssInfo_res_fun_sra_T_4 | iss_stage_bufInfo_1_alu_isa_sraw
    ; // @[riscv_isa.scala 76:39]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_8 = iss_stage_bufInfo_1_alu_isa_addiw |
    iss_stage_bufInfo_1_alu_isa_addw; // @[riscv_isa.scala 65:22]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_9 = iss_stage__aluIssInfo_res_param_is_32w_T_8 |
    iss_stage_bufInfo_1_alu_isa_subw; // @[riscv_isa.scala 65:29]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_10 = iss_stage__aluIssInfo_res_param_is_32w_T_9 |
    iss_stage_bufInfo_1_alu_isa_slliw; // @[riscv_isa.scala 65:36]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_11 = iss_stage__aluIssInfo_res_param_is_32w_T_10 |
    iss_stage_bufInfo_1_alu_isa_sllw; // @[riscv_isa.scala 65:44]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_12 = iss_stage__aluIssInfo_res_param_is_32w_T_11 |
    iss_stage_bufInfo_1_alu_isa_srliw; // @[riscv_isa.scala 65:51]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_13 = iss_stage__aluIssInfo_res_param_is_32w_T_12 |
    iss_stage_bufInfo_1_alu_isa_srlw; // @[riscv_isa.scala 65:59]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_14 = iss_stage__aluIssInfo_res_param_is_32w_T_13 |
    iss_stage_bufInfo_1_alu_isa_sraiw; // @[riscv_isa.scala 65:66]
  wire  iss_stage__aluIssInfo_res_param_is_32w_T_15 = iss_stage__aluIssInfo_res_param_is_32w_T_14 |
    iss_stage_bufInfo_1_alu_isa_sraw; // @[riscv_isa.scala 65:74]
  wire  iss_stage__aluIssInfo_res_param_is_usi_T_1 = iss_stage_bufInfo_1_alu_isa_sltiu |
    iss_stage_bufInfo_1_alu_isa_sltu; // @[riscv_isa.scala 66:22]
  wire  iss_stage__aluIssInfo_res_param_dat_op1_v64_T_5 = iss_stage_bufInfo_1_param_pc[38]; // @[Util.scala 47:31]
  wire [24:0] iss_stage__aluIssInfo_res_param_dat_op1_v64_T_7 = iss_stage__aluIssInfo_res_param_dat_op1_v64_T_5 ? 25'h1ffffff
     : 25'h0; // @[Bitwise.scala 77:12]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op1_v64_T_9 = {iss_stage__aluIssInfo_res_param_dat_op1_v64_T_7,
    iss_stage_bufInfo_1_param_pc}; // @[Cat.scala 33:92]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op1_T_62 = iss_stage_bufInfo_1_alu_isa_auipc ?
    iss_stage__aluIssInfo_res_param_dat_op1_v64_T_9 : 64'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_63 = iss_stage_bufInfo_1_alu_isa_addi ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_64 = iss_stage_bufInfo_1_alu_isa_addiw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_65 = iss_stage_bufInfo_1_alu_isa_slti ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_66 = iss_stage_bufInfo_1_alu_isa_sltiu ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_67 = iss_stage_bufInfo_1_alu_isa_xori ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_68 = iss_stage_bufInfo_1_alu_isa_ori ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_69 = iss_stage_bufInfo_1_alu_isa_andi ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_70 = iss_stage_bufInfo_1_alu_isa_slli ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_71 = iss_stage_bufInfo_1_alu_isa_slliw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_72 = iss_stage_bufInfo_1_alu_isa_srli ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_73 = iss_stage_bufInfo_1_alu_isa_srliw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_74 = iss_stage_bufInfo_1_alu_isa_srai ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_75 = iss_stage_bufInfo_1_alu_isa_sraiw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_76 = iss_stage_bufInfo_1_alu_isa_add ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_77 = iss_stage_bufInfo_1_alu_isa_addw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_78 = iss_stage_bufInfo_1_alu_isa_sub ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_79 = iss_stage_bufInfo_1_alu_isa_subw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_80 = iss_stage_bufInfo_1_alu_isa_sll ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_81 = iss_stage_bufInfo_1_alu_isa_sllw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_82 = iss_stage_bufInfo_1_alu_isa_slt ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_83 = iss_stage_bufInfo_1_alu_isa_sltu ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_84 = iss_stage_bufInfo_1_alu_isa_xor ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_85 = iss_stage_bufInfo_1_alu_isa_srl ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_86 = iss_stage_bufInfo_1_alu_isa_srlw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_87 = iss_stage_bufInfo_1_alu_isa_sra ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_88 = iss_stage_bufInfo_1_alu_isa_sraw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_89 = iss_stage_bufInfo_1_alu_isa_or ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_90 = iss_stage_bufInfo_1_alu_isa_and ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] _GEN_240 = {{1'd0}, iss_stage__aluIssInfo_res_param_dat_op1_T_62}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_93 = _GEN_240 | iss_stage__aluIssInfo_res_param_dat_op1_T_63; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_94 = iss_stage__aluIssInfo_res_param_dat_op1_T_93 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_64; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_95 = iss_stage__aluIssInfo_res_param_dat_op1_T_94 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_65; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_96 = iss_stage__aluIssInfo_res_param_dat_op1_T_95 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_66; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_97 = iss_stage__aluIssInfo_res_param_dat_op1_T_96 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_67; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_98 = iss_stage__aluIssInfo_res_param_dat_op1_T_97 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_68; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_99 = iss_stage__aluIssInfo_res_param_dat_op1_T_98 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_69; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_100 = iss_stage__aluIssInfo_res_param_dat_op1_T_99 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_70; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_101 = iss_stage__aluIssInfo_res_param_dat_op1_T_100 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_71; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_102 = iss_stage__aluIssInfo_res_param_dat_op1_T_101 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_72; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_103 = iss_stage__aluIssInfo_res_param_dat_op1_T_102 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_73; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_104 = iss_stage__aluIssInfo_res_param_dat_op1_T_103 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_74; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_105 = iss_stage__aluIssInfo_res_param_dat_op1_T_104 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_75; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_106 = iss_stage__aluIssInfo_res_param_dat_op1_T_105 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_76; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_107 = iss_stage__aluIssInfo_res_param_dat_op1_T_106 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_77; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_108 = iss_stage__aluIssInfo_res_param_dat_op1_T_107 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_78; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_109 = iss_stage__aluIssInfo_res_param_dat_op1_T_108 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_79; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_110 = iss_stage__aluIssInfo_res_param_dat_op1_T_109 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_80; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_111 = iss_stage__aluIssInfo_res_param_dat_op1_T_110 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_81; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_112 = iss_stage__aluIssInfo_res_param_dat_op1_T_111 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_82; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_113 = iss_stage__aluIssInfo_res_param_dat_op1_T_112 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_83; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_114 = iss_stage__aluIssInfo_res_param_dat_op1_T_113 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_84; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_115 = iss_stage__aluIssInfo_res_param_dat_op1_T_114 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_85; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_116 = iss_stage__aluIssInfo_res_param_dat_op1_T_115 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_86; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_117 = iss_stage__aluIssInfo_res_param_dat_op1_T_116 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_87; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_118 = iss_stage__aluIssInfo_res_param_dat_op1_T_117 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_88; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_119 = iss_stage__aluIssInfo_res_param_dat_op1_T_118 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_89; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op1_T_120 = iss_stage__aluIssInfo_res_param_dat_op1_T_119 |
    iss_stage__aluIssInfo_res_param_dat_op1_T_90; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_73 = iss_stage_bufInfo_1_param_imm[5:0]; // @[Issue.scala 582:122]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_79 = ~iss_stage__postBufOperator_1_1_T_8; // @[Issue.scala 586:101]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_81 = iss_stage__aluIssInfo_res_param_dat_op2_T_79 + 65'h1; // @[Issue.scala 586:107]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_85 = iss_stage_bufInfo_1_alu_isa_lui ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_86 = iss_stage_bufInfo_1_alu_isa_auipc ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_87 = iss_stage_bufInfo_1_alu_isa_addi ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_88 = iss_stage_bufInfo_1_alu_isa_addiw ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_89 = iss_stage_bufInfo_1_alu_isa_slti ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_90 = iss_stage_bufInfo_1_alu_isa_sltiu ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_91 = iss_stage_bufInfo_1_alu_isa_xori ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_92 = iss_stage_bufInfo_1_alu_isa_ori ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_93 = iss_stage_bufInfo_1_alu_isa_andi ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_94 = iss_stage_bufInfo_1_alu_isa_slli ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_73 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_95 = iss_stage_bufInfo_1_alu_isa_slliw ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_73 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_96 = iss_stage_bufInfo_1_alu_isa_srli ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_73 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_97 = iss_stage_bufInfo_1_alu_isa_srliw ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_73 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_98 = iss_stage_bufInfo_1_alu_isa_srai ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_73 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssInfo_res_param_dat_op2_T_99 = iss_stage_bufInfo_1_alu_isa_sraiw ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_73 : 6'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_100 = iss_stage_bufInfo_1_alu_isa_add ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_101 = iss_stage_bufInfo_1_alu_isa_addw ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_102 = iss_stage_bufInfo_1_alu_isa_sub ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_81 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_103 = iss_stage_bufInfo_1_alu_isa_subw ?
    iss_stage__aluIssInfo_res_param_dat_op2_T_81 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_104 = iss_stage_bufInfo_1_alu_isa_sll ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_105 = iss_stage_bufInfo_1_alu_isa_sllw ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_106 = iss_stage_bufInfo_1_alu_isa_slt ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_107 = iss_stage_bufInfo_1_alu_isa_sltu ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_108 = iss_stage_bufInfo_1_alu_isa_xor ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_109 = iss_stage_bufInfo_1_alu_isa_srl ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_110 = iss_stage_bufInfo_1_alu_isa_srlw ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_111 = iss_stage_bufInfo_1_alu_isa_sra ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_112 = iss_stage_bufInfo_1_alu_isa_sraw ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_113 = iss_stage_bufInfo_1_alu_isa_or ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_114 = iss_stage_bufInfo_1_alu_isa_and ?
    iss_stage__postBufOperator_1_1_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_116 = iss_stage__aluIssInfo_res_param_dat_op2_T_85 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_86; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_117 = iss_stage__aluIssInfo_res_param_dat_op2_T_116 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_87; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_118 = iss_stage__aluIssInfo_res_param_dat_op2_T_117 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_88; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_119 = iss_stage__aluIssInfo_res_param_dat_op2_T_118 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_89; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_120 = iss_stage__aluIssInfo_res_param_dat_op2_T_119 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_90; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_121 = iss_stage__aluIssInfo_res_param_dat_op2_T_120 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_91; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_122 = iss_stage__aluIssInfo_res_param_dat_op2_T_121 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_92; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_123 = iss_stage__aluIssInfo_res_param_dat_op2_T_122 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_93; // @[Mux.scala 27:73]
  wire [63:0] _GEN_241 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_94}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_124 = iss_stage__aluIssInfo_res_param_dat_op2_T_123 | _GEN_241; // @[Mux.scala 27:73]
  wire [63:0] _GEN_242 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_95}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_125 = iss_stage__aluIssInfo_res_param_dat_op2_T_124 | _GEN_242; // @[Mux.scala 27:73]
  wire [63:0] _GEN_243 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_96}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_126 = iss_stage__aluIssInfo_res_param_dat_op2_T_125 | _GEN_243; // @[Mux.scala 27:73]
  wire [63:0] _GEN_244 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_97}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_127 = iss_stage__aluIssInfo_res_param_dat_op2_T_126 | _GEN_244; // @[Mux.scala 27:73]
  wire [63:0] _GEN_245 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_98}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_128 = iss_stage__aluIssInfo_res_param_dat_op2_T_127 | _GEN_245; // @[Mux.scala 27:73]
  wire [63:0] _GEN_246 = {{58'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_99}; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__aluIssInfo_res_param_dat_op2_T_129 = iss_stage__aluIssInfo_res_param_dat_op2_T_128 | _GEN_246; // @[Mux.scala 27:73]
  wire [64:0] _GEN_247 = {{1'd0}, iss_stage__aluIssInfo_res_param_dat_op2_T_129}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_130 = _GEN_247 | iss_stage__aluIssInfo_res_param_dat_op2_T_100; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_131 = iss_stage__aluIssInfo_res_param_dat_op2_T_130 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_101; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_132 = iss_stage__aluIssInfo_res_param_dat_op2_T_131 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_102; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_133 = iss_stage__aluIssInfo_res_param_dat_op2_T_132 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_103; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_134 = iss_stage__aluIssInfo_res_param_dat_op2_T_133 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_104; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_135 = iss_stage__aluIssInfo_res_param_dat_op2_T_134 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_105; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_136 = iss_stage__aluIssInfo_res_param_dat_op2_T_135 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_106; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_137 = iss_stage__aluIssInfo_res_param_dat_op2_T_136 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_107; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_138 = iss_stage__aluIssInfo_res_param_dat_op2_T_137 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_108; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_139 = iss_stage__aluIssInfo_res_param_dat_op2_T_138 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_109; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_140 = iss_stage__aluIssInfo_res_param_dat_op2_T_139 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_110; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_141 = iss_stage__aluIssInfo_res_param_dat_op2_T_140 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_111; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_142 = iss_stage__aluIssInfo_res_param_dat_op2_T_141 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_112; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_143 = iss_stage__aluIssInfo_res_param_dat_op2_T_142 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_113; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__aluIssInfo_res_param_dat_op2_T_144 = iss_stage__aluIssInfo_res_param_dat_op2_T_143 |
    iss_stage__aluIssInfo_res_param_dat_op2_T_114; // @[Mux.scala 27:73]
  wire  iss_stage__maskCondAluIss_0_0_T_1 = iss_stage_bufInfo_0_alu_isa_lui | iss_stage_bufInfo_0_alu_isa_auipc; // @[riscv_isa.scala 78:20]
  wire  iss_stage__maskCondAluIss_0_0_T_2 = iss_stage__maskCondAluIss_0_0_T_1 | iss_stage_bufInfo_0_alu_isa_addi; // @[riscv_isa.scala 78:28]
  wire  iss_stage__maskCondAluIss_0_0_T_3 = iss_stage__maskCondAluIss_0_0_T_2 | iss_stage_bufInfo_0_alu_isa_addiw; // @[riscv_isa.scala 78:35]
  wire  iss_stage__maskCondAluIss_0_0_T_4 = iss_stage__maskCondAluIss_0_0_T_3 | iss_stage_bufInfo_0_alu_isa_slti; // @[riscv_isa.scala 78:43]
  wire  iss_stage__maskCondAluIss_0_0_T_5 = iss_stage__maskCondAluIss_0_0_T_4 | iss_stage_bufInfo_0_alu_isa_sltiu; // @[riscv_isa.scala 78:50]
  wire  iss_stage__maskCondAluIss_0_0_T_6 = iss_stage__maskCondAluIss_0_0_T_5 | iss_stage_bufInfo_0_alu_isa_xori; // @[riscv_isa.scala 78:58]
  wire  iss_stage__maskCondAluIss_0_0_T_7 = iss_stage__maskCondAluIss_0_0_T_6 | iss_stage_bufInfo_0_alu_isa_ori; // @[riscv_isa.scala 78:65]
  wire  iss_stage__maskCondAluIss_0_0_T_8 = iss_stage__maskCondAluIss_0_0_T_7 | iss_stage_bufInfo_0_alu_isa_andi; // @[riscv_isa.scala 78:71]
  wire  iss_stage__maskCondAluIss_0_0_T_9 = iss_stage__maskCondAluIss_0_0_T_8 | iss_stage_bufInfo_0_alu_isa_slli; // @[riscv_isa.scala 78:78]
  wire  iss_stage__maskCondAluIss_0_0_T_10 = iss_stage__maskCondAluIss_0_0_T_9 | iss_stage_bufInfo_0_alu_isa_slliw; // @[riscv_isa.scala 78:85]
  wire  iss_stage__maskCondAluIss_0_0_T_11 = iss_stage__maskCondAluIss_0_0_T_10 | iss_stage_bufInfo_0_alu_isa_srli; // @[riscv_isa.scala 78:93]
  wire  iss_stage__maskCondAluIss_0_0_T_12 = iss_stage__maskCondAluIss_0_0_T_11 | iss_stage_bufInfo_0_alu_isa_srliw; // @[riscv_isa.scala 78:100]
  wire  iss_stage__maskCondAluIss_0_0_T_13 = iss_stage__maskCondAluIss_0_0_T_12 | iss_stage_bufInfo_0_alu_isa_srai; // @[riscv_isa.scala 78:108]
  wire  iss_stage__maskCondAluIss_0_0_T_14 = iss_stage__maskCondAluIss_0_0_T_13 | iss_stage_bufInfo_0_alu_isa_sraiw; // @[riscv_isa.scala 78:115]
  wire  iss_stage__maskCondAluIss_0_0_T_15 = iss_stage__maskCondAluIss_0_0_T_14 | iss_stage_bufInfo_0_alu_isa_add; // @[riscv_isa.scala 78:123]
  wire  iss_stage__maskCondAluIss_0_0_T_16 = iss_stage__maskCondAluIss_0_0_T_15 | iss_stage_bufInfo_0_alu_isa_addw; // @[riscv_isa.scala 78:129]
  wire  iss_stage__maskCondAluIss_0_0_T_17 = iss_stage__maskCondAluIss_0_0_T_16 | iss_stage_bufInfo_0_alu_isa_sub; // @[riscv_isa.scala 78:136]
  wire  iss_stage__maskCondAluIss_0_0_T_18 = iss_stage__maskCondAluIss_0_0_T_17 | iss_stage_bufInfo_0_alu_isa_subw; // @[riscv_isa.scala 78:142]
  wire  iss_stage__maskCondAluIss_0_0_T_19 = iss_stage__maskCondAluIss_0_0_T_18 | iss_stage_bufInfo_0_alu_isa_sll; // @[riscv_isa.scala 78:149]
  wire  iss_stage__maskCondAluIss_0_0_T_20 = iss_stage__maskCondAluIss_0_0_T_19 | iss_stage_bufInfo_0_alu_isa_sllw; // @[riscv_isa.scala 78:155]
  wire  iss_stage__maskCondAluIss_0_0_T_21 = iss_stage__maskCondAluIss_0_0_T_20 | iss_stage_bufInfo_0_alu_isa_slt; // @[riscv_isa.scala 78:162]
  wire  iss_stage__maskCondAluIss_0_0_T_22 = iss_stage__maskCondAluIss_0_0_T_21 | iss_stage_bufInfo_0_alu_isa_sltu; // @[riscv_isa.scala 78:168]
  wire  iss_stage__maskCondAluIss_0_0_T_23 = iss_stage__maskCondAluIss_0_0_T_22 | iss_stage_bufInfo_0_alu_isa_xor; // @[riscv_isa.scala 78:175]
  wire  iss_stage__maskCondAluIss_0_0_T_24 = iss_stage__maskCondAluIss_0_0_T_23 | iss_stage_bufInfo_0_alu_isa_srl; // @[riscv_isa.scala 78:181]
  wire  iss_stage__maskCondAluIss_0_0_T_25 = iss_stage__maskCondAluIss_0_0_T_24 | iss_stage_bufInfo_0_alu_isa_srlw; // @[riscv_isa.scala 78:187]
  wire  iss_stage__maskCondAluIss_0_0_T_26 = iss_stage__maskCondAluIss_0_0_T_25 | iss_stage_bufInfo_0_alu_isa_sra; // @[riscv_isa.scala 78:194]
  wire  iss_stage__maskCondAluIss_0_0_T_27 = iss_stage__maskCondAluIss_0_0_T_26 | iss_stage_bufInfo_0_alu_isa_sraw; // @[riscv_isa.scala 78:200]
  wire  iss_stage__maskCondAluIss_0_0_T_28 = iss_stage__maskCondAluIss_0_0_T_27 | iss_stage_bufInfo_0_alu_isa_or; // @[riscv_isa.scala 78:207]
  wire  iss_stage__maskCondAluIss_0_0_T_29 = iss_stage__maskCondAluIss_0_0_T_28 | iss_stage_bufInfo_0_alu_isa_and; // @[riscv_isa.scala 78:212]
  wire  iss_stage__maskCondAluIss_0_0_T_30 = iss_stage__maskCondAluIss_0_0_T_29 | iss_stage_bufInfo_0_alu_isa_wfi; // @[riscv_isa.scala 78:217]
  wire  iss_stage__maskCondAluIss_0_0_T_31 = ~iss_stage__maskCondAluIss_0_0_T_30; // @[Issue.scala 617:11]
  wire  iss_stage__maskCondAluIss_0_0_T_32 = iss_stage__entrySel_T | iss_stage__maskCondAluIss_0_0_T_31; // @[Issue.scala 616:24]
  wire  iss_stage__maskCondAluIss_0_0_T_33 = iss_stage__postIsOpReady_0_0_T_8 & iss_stage__postIsOpReady_0_1_T_8; // @[Issue.scala 618:33]
  wire  iss_stage__maskCondAluIss_0_0_T_34 = ~iss_stage__maskCondAluIss_0_0_T_33; // @[Issue.scala 618:11]
  wire  iss_stage__maskCondAluIss_0_0_T_35 = iss_stage__maskCondAluIss_0_0_T_32 | iss_stage__maskCondAluIss_0_0_T_34; // @[Issue.scala 617:38]
  wire  iss_stage__maskCondAluIss_0_1_T_1 = iss_stage_bufInfo_1_alu_isa_lui | iss_stage_bufInfo_1_alu_isa_auipc; // @[riscv_isa.scala 78:20]
  wire  iss_stage__maskCondAluIss_0_1_T_2 = iss_stage__maskCondAluIss_0_1_T_1 | iss_stage_bufInfo_1_alu_isa_addi; // @[riscv_isa.scala 78:28]
  wire  iss_stage__maskCondAluIss_0_1_T_3 = iss_stage__maskCondAluIss_0_1_T_2 | iss_stage_bufInfo_1_alu_isa_addiw; // @[riscv_isa.scala 78:35]
  wire  iss_stage__maskCondAluIss_0_1_T_4 = iss_stage__maskCondAluIss_0_1_T_3 | iss_stage_bufInfo_1_alu_isa_slti; // @[riscv_isa.scala 78:43]
  wire  iss_stage__maskCondAluIss_0_1_T_5 = iss_stage__maskCondAluIss_0_1_T_4 | iss_stage_bufInfo_1_alu_isa_sltiu; // @[riscv_isa.scala 78:50]
  wire  iss_stage__maskCondAluIss_0_1_T_6 = iss_stage__maskCondAluIss_0_1_T_5 | iss_stage_bufInfo_1_alu_isa_xori; // @[riscv_isa.scala 78:58]
  wire  iss_stage__maskCondAluIss_0_1_T_7 = iss_stage__maskCondAluIss_0_1_T_6 | iss_stage_bufInfo_1_alu_isa_ori; // @[riscv_isa.scala 78:65]
  wire  iss_stage__maskCondAluIss_0_1_T_8 = iss_stage__maskCondAluIss_0_1_T_7 | iss_stage_bufInfo_1_alu_isa_andi; // @[riscv_isa.scala 78:71]
  wire  iss_stage__maskCondAluIss_0_1_T_9 = iss_stage__maskCondAluIss_0_1_T_8 | iss_stage_bufInfo_1_alu_isa_slli; // @[riscv_isa.scala 78:78]
  wire  iss_stage__maskCondAluIss_0_1_T_10 = iss_stage__maskCondAluIss_0_1_T_9 | iss_stage_bufInfo_1_alu_isa_slliw; // @[riscv_isa.scala 78:85]
  wire  iss_stage__maskCondAluIss_0_1_T_11 = iss_stage__maskCondAluIss_0_1_T_10 | iss_stage_bufInfo_1_alu_isa_srli; // @[riscv_isa.scala 78:93]
  wire  iss_stage__maskCondAluIss_0_1_T_12 = iss_stage__maskCondAluIss_0_1_T_11 | iss_stage_bufInfo_1_alu_isa_srliw; // @[riscv_isa.scala 78:100]
  wire  iss_stage__maskCondAluIss_0_1_T_13 = iss_stage__maskCondAluIss_0_1_T_12 | iss_stage_bufInfo_1_alu_isa_srai; // @[riscv_isa.scala 78:108]
  wire  iss_stage__maskCondAluIss_0_1_T_14 = iss_stage__maskCondAluIss_0_1_T_13 | iss_stage_bufInfo_1_alu_isa_sraiw; // @[riscv_isa.scala 78:115]
  wire  iss_stage__maskCondAluIss_0_1_T_15 = iss_stage__maskCondAluIss_0_1_T_14 | iss_stage_bufInfo_1_alu_isa_add; // @[riscv_isa.scala 78:123]
  wire  iss_stage__maskCondAluIss_0_1_T_16 = iss_stage__maskCondAluIss_0_1_T_15 | iss_stage_bufInfo_1_alu_isa_addw; // @[riscv_isa.scala 78:129]
  wire  iss_stage__maskCondAluIss_0_1_T_17 = iss_stage__maskCondAluIss_0_1_T_16 | iss_stage_bufInfo_1_alu_isa_sub; // @[riscv_isa.scala 78:136]
  wire  iss_stage__maskCondAluIss_0_1_T_18 = iss_stage__maskCondAluIss_0_1_T_17 | iss_stage_bufInfo_1_alu_isa_subw; // @[riscv_isa.scala 78:142]
  wire  iss_stage__maskCondAluIss_0_1_T_19 = iss_stage__maskCondAluIss_0_1_T_18 | iss_stage_bufInfo_1_alu_isa_sll; // @[riscv_isa.scala 78:149]
  wire  iss_stage__maskCondAluIss_0_1_T_20 = iss_stage__maskCondAluIss_0_1_T_19 | iss_stage_bufInfo_1_alu_isa_sllw; // @[riscv_isa.scala 78:155]
  wire  iss_stage__maskCondAluIss_0_1_T_21 = iss_stage__maskCondAluIss_0_1_T_20 | iss_stage_bufInfo_1_alu_isa_slt; // @[riscv_isa.scala 78:162]
  wire  iss_stage__maskCondAluIss_0_1_T_22 = iss_stage__maskCondAluIss_0_1_T_21 | iss_stage_bufInfo_1_alu_isa_sltu; // @[riscv_isa.scala 78:168]
  wire  iss_stage__maskCondAluIss_0_1_T_23 = iss_stage__maskCondAluIss_0_1_T_22 | iss_stage_bufInfo_1_alu_isa_xor; // @[riscv_isa.scala 78:175]
  wire  iss_stage__maskCondAluIss_0_1_T_24 = iss_stage__maskCondAluIss_0_1_T_23 | iss_stage_bufInfo_1_alu_isa_srl; // @[riscv_isa.scala 78:181]
  wire  iss_stage__maskCondAluIss_0_1_T_25 = iss_stage__maskCondAluIss_0_1_T_24 | iss_stage_bufInfo_1_alu_isa_srlw; // @[riscv_isa.scala 78:187]
  wire  iss_stage__maskCondAluIss_0_1_T_26 = iss_stage__maskCondAluIss_0_1_T_25 | iss_stage_bufInfo_1_alu_isa_sra; // @[riscv_isa.scala 78:194]
  wire  iss_stage__maskCondAluIss_0_1_T_27 = iss_stage__maskCondAluIss_0_1_T_26 | iss_stage_bufInfo_1_alu_isa_sraw; // @[riscv_isa.scala 78:200]
  wire  iss_stage__maskCondAluIss_0_1_T_28 = iss_stage__maskCondAluIss_0_1_T_27 | iss_stage_bufInfo_1_alu_isa_or; // @[riscv_isa.scala 78:207]
  wire  iss_stage__maskCondAluIss_0_1_T_29 = iss_stage__maskCondAluIss_0_1_T_28 | iss_stage_bufInfo_1_alu_isa_and; // @[riscv_isa.scala 78:212]
  wire  iss_stage__maskCondAluIss_0_1_T_30 = iss_stage__maskCondAluIss_0_1_T_29 | iss_stage_bufInfo_1_alu_isa_wfi; // @[riscv_isa.scala 78:217]
  wire  iss_stage__maskCondAluIss_0_1_T_31 = ~iss_stage__maskCondAluIss_0_1_T_30; // @[Issue.scala 617:11]
  wire  iss_stage__maskCondAluIss_0_1_T_32 = iss_stage__io_dptReq_0_ready_T_1 | iss_stage__maskCondAluIss_0_1_T_31; // @[Issue.scala 616:24]
  wire  iss_stage__maskCondAluIss_0_1_T_33 = iss_stage__postIsOpReady_1_0_T_8 & iss_stage__postIsOpReady_1_1_T_8; // @[Issue.scala 618:33]
  wire  iss_stage__maskCondAluIss_0_1_T_34 = ~iss_stage__maskCondAluIss_0_1_T_33; // @[Issue.scala 618:11]
  wire  iss_stage__maskCondAluIss_0_1_T_35 = iss_stage__maskCondAluIss_0_1_T_32 | iss_stage__maskCondAluIss_0_1_T_34; // @[Issue.scala 617:38]
  wire  iss_stage__matrixOut_0_0_T_15 = ~iss_stage__maskCondAluIss_0_0_T_35; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_0_T_16 = iss_stage_ageMatrixW_0_0 & iss_stage__matrixOut_0_0_T_15; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_0_T_17 = iss_stage__matrixOut_0_0_T_16 | iss_stage__maskCondAluIss_0_0_T_35; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_1_T_15 = ~iss_stage__maskCondAluIss_0_1_T_35; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_1_T_16 = iss_stage_ageMatrixW_0_1 & iss_stage__matrixOut_0_1_T_15; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_1_T_17 = iss_stage__matrixOut_0_1_T_16 | iss_stage__maskCondAluIss_0_0_T_35; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_0_T_16 = iss_stage__ageMatrixR_1_0_T & iss_stage__matrixOut_0_0_T_15; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_0_T_17 = iss_stage__matrixOut_1_0_T_16 | iss_stage__maskCondAluIss_0_1_T_35; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_1_T_16 = iss_stage_ageMatrixW_1_1 & iss_stage__matrixOut_0_1_T_15; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_1_T_17 = iss_stage__matrixOut_1_1_T_16 | iss_stage__maskCondAluIss_0_1_T_35; // @[Issue.scala 200:60]
  wire  iss_stage__T_294 = iss_stage__matrixOut_0_0_T_17 & iss_stage__matrixOut_0_1_T_17; // @[Issue.scala 628:59]
  wire  iss_stage__T_298 = iss_stage__matrixOut_1_0_T_17 & iss_stage__matrixOut_1_1_T_17; // @[Issue.scala 628:59]
  wire  iss_stage__T_300 = iss_stage__T_294 & iss_stage__T_298; // @[Issue.scala 628:31]
  wire  iss_stage__T_301 = ~iss_stage__matrixOut_0_0_T_17; // @[Issue.scala 629:82]
  wire  iss_stage__T_302 = ~iss_stage__matrixOut_0_1_T_17; // @[Issue.scala 629:82]
  wire  iss_stage__T_304 = iss_stage__T_301 & iss_stage__T_302; // @[Issue.scala 629:65]
  wire  iss_stage__T_305 = ~iss_stage__matrixOut_1_0_T_17; // @[Issue.scala 629:82]
  wire  iss_stage__T_306 = ~iss_stage__matrixOut_1_1_T_17; // @[Issue.scala 629:82]
  wire  iss_stage__T_308 = iss_stage__T_305 & iss_stage__T_306; // @[Issue.scala 629:65]
  wire [1:0] iss_stage__T_309 = iss_stage__T_304 + iss_stage__T_308; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_311 = iss_stage__T_309 == 2'h1; // @[Issue.scala 629:100]
  wire  iss_stage__T_312 = iss_stage__T_300 | iss_stage__T_311; // @[Issue.scala 628:92]
  wire  iss_stage__T_315 = ~iss_stage__T_312; // @[Issue.scala 627:11]
  wire  iss_stage__aluIssIdx_0_T_8 = iss_stage__T_304 ? 1'h0 : 1'h1; // @[Issue.scala 635:51]
  wire [63:0] iss_stage_aluIssInfo_0_param_dat_op2 = iss_stage__aluIssInfo_res_param_dat_op2_T_71[63:0]; // @[Issue.scala 538:19 576:23]
  wire [63:0] iss_stage__aluIssFifo_0_io_enq_bits_T_11 = iss_stage__T_304 ? iss_stage_aluIssInfo_0_param_dat_op2 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_aluIssInfo_1_param_dat_op2 = iss_stage__aluIssInfo_res_param_dat_op2_T_144[63:0]; // @[Issue.scala 538:19 576:23]
  wire [63:0] iss_stage__aluIssFifo_0_io_enq_bits_T_12 = iss_stage__T_308 ? iss_stage_aluIssInfo_1_param_dat_op2 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_aluIssInfo_0_param_dat_op1 = iss_stage__aluIssInfo_res_param_dat_op1_T_59[63:0]; // @[Issue.scala 538:19 554:23]
  wire [63:0] iss_stage__aluIssFifo_0_io_enq_bits_T_14 = iss_stage__T_304 ? iss_stage_aluIssInfo_0_param_dat_op1 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_aluIssInfo_1_param_dat_op1 = iss_stage__aluIssInfo_res_param_dat_op1_T_120[63:0]; // @[Issue.scala 538:19 554:23]
  wire [63:0] iss_stage__aluIssFifo_0_io_enq_bits_T_15 = iss_stage__T_308 ? iss_stage_aluIssInfo_1_param_dat_op1 : 64'h0
    ; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_17 = iss_stage__T_304 & iss_stage__aluIssInfo_res_param_is_usi_T; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_18 = iss_stage__T_308 & iss_stage__aluIssInfo_res_param_is_usi_T_1; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_20 = iss_stage__T_304 & iss_stage__aluIssInfo_res_param_is_32w_T_7; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_21 = iss_stage__T_308 & iss_stage__aluIssInfo_res_param_is_32w_T_15; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssFifo_0_io_enq_bits_T_23 = iss_stage__T_304 ? iss_stage_bufInfo_0_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__aluIssFifo_0_io_enq_bits_T_24 = iss_stage__T_308 ? iss_stage_bufInfo_1_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_26 = iss_stage__T_304 & iss_stage__aluIssInfo_res_fun_sra_T_2; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_27 = iss_stage__T_308 & iss_stage__aluIssInfo_res_fun_sra_T_5; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_29 = iss_stage__T_304 & iss_stage__aluIssInfo_res_fun_srl_T_2; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_30 = iss_stage__T_308 & iss_stage__aluIssInfo_res_fun_srl_T_5; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_32 = iss_stage__T_304 & iss_stage__aluIssInfo_res_fun_sll_T_2; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_33 = iss_stage__T_308 & iss_stage__aluIssInfo_res_fun_sll_T_5; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_35 = iss_stage__T_304 & iss_stage__aluIssInfo_res_fun_and_T; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_36 = iss_stage__T_308 & iss_stage__aluIssInfo_res_fun_and_T_1; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_38 = iss_stage__T_304 & iss_stage__aluIssInfo_res_fun_or_T; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_39 = iss_stage__T_308 & iss_stage__aluIssInfo_res_fun_or_T_1; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_41 = iss_stage__T_304 & iss_stage__aluIssInfo_res_fun_xor_T; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_42 = iss_stage__T_308 & iss_stage__aluIssInfo_res_fun_xor_T_1; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_44 = iss_stage__T_304 & iss_stage__aluIssInfo_res_fun_slt_T_2; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_45 = iss_stage__T_308 & iss_stage__aluIssInfo_res_fun_slt_T_5; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_47 = iss_stage__T_304 & iss_stage__aluIssInfo_res_fun_add_T_7; // @[Mux.scala 27:73]
  wire  iss_stage__aluIssFifo_0_io_enq_bits_T_48 = iss_stage__T_308 & iss_stage__aluIssInfo_res_fun_add_T_15; // @[Mux.scala 27:73]
  wire  iss_stage__T_317 = ~iss_stage__aluIssIdx_0_T_8; // @[Issue.scala 640:58]
  wire  iss_stage__T_318 = iss_stage_aluIssFifo_0__do_enq_T & iss_stage__T_317; // @[Issue.scala 640:41]
  wire  iss_stage__GEN_1804 = iss_stage__T_318 ? 1'h0 : iss_stage__GEN_792; // @[Issue.scala 640:68 641:21 75:12]
  wire  iss_stage__T_361 = iss_stage_aluIssFifo_0__do_enq_T & iss_stage__aluIssIdx_0_T_8; // @[Issue.scala 640:41]
  wire  iss_stage__GEN_1805 = iss_stage__T_361 ? 1'h0 : iss_stage__GEN_793; // @[Issue.scala 640:68 641:21 75:12]
  wire  iss_stage__maskCondMulIss_0_0_T_1 = iss_stage_bufInfo_0_mul_isa_mul | iss_stage_bufInfo_0_mul_isa_mulh; // @[riscv_isa.scala 203:19]
  wire  iss_stage__maskCondMulIss_0_0_T_2 = iss_stage__maskCondMulIss_0_0_T_1 | iss_stage_bufInfo_0_mul_isa_mulhsu; // @[riscv_isa.scala 203:26]
  wire  iss_stage__maskCondMulIss_0_0_T_3 = iss_stage__maskCondMulIss_0_0_T_2 | iss_stage_bufInfo_0_mul_isa_mulhu; // @[riscv_isa.scala 203:35]
  wire  iss_stage__maskCondMulIss_0_0_T_4 = iss_stage__maskCondMulIss_0_0_T_3 | iss_stage_bufInfo_0_mul_isa_mulw; // @[riscv_isa.scala 203:43]
  wire  iss_stage__maskCondMulIss_0_0_T_5 = iss_stage_bufInfo_0_mul_isa_div | iss_stage_bufInfo_0_mul_isa_divu; // @[riscv_isa.scala 204:19]
  wire  iss_stage__maskCondMulIss_0_0_T_6 = iss_stage__maskCondMulIss_0_0_T_5 | iss_stage_bufInfo_0_mul_isa_divw; // @[riscv_isa.scala 204:26]
  wire  iss_stage__maskCondMulIss_0_0_T_7 = iss_stage__maskCondMulIss_0_0_T_6 | iss_stage_bufInfo_0_mul_isa_divuw; // @[riscv_isa.scala 204:33]
  wire  iss_stage__maskCondMulIss_0_0_T_8 = iss_stage__maskCondMulIss_0_0_T_7 | iss_stage_bufInfo_0_mul_isa_rem; // @[riscv_isa.scala 204:41]
  wire  iss_stage__maskCondMulIss_0_0_T_9 = iss_stage__maskCondMulIss_0_0_T_8 | iss_stage_bufInfo_0_mul_isa_remu; // @[riscv_isa.scala 204:47]
  wire  iss_stage__maskCondMulIss_0_0_T_10 = iss_stage__maskCondMulIss_0_0_T_9 | iss_stage_bufInfo_0_mul_isa_remw; // @[riscv_isa.scala 204:54]
  wire  iss_stage__maskCondMulIss_0_0_T_11 = iss_stage__maskCondMulIss_0_0_T_10 | iss_stage_bufInfo_0_mul_isa_remuw; // @[riscv_isa.scala 204:61]
  wire  iss_stage__maskCondMulIss_0_0_T_12 = iss_stage__maskCondMulIss_0_0_T_4 | iss_stage__maskCondMulIss_0_0_T_11; // @[riscv_isa.scala 206:25]
  wire  iss_stage__maskCondMulIss_0_0_T_13 = ~iss_stage__maskCondMulIss_0_0_T_12; // @[Issue.scala 682:13]
  wire  iss_stage__maskCondMulIss_0_0_T_14 = iss_stage__entrySel_T | iss_stage__maskCondMulIss_0_0_T_13; // @[Issue.scala 681:26]
  wire  iss_stage__maskCondMulIss_0_0_T_17 = iss_stage__maskCondMulIss_0_0_T_14 | iss_stage__maskCondAluIss_0_0_T_34; // @[Issue.scala 682:43]
  wire  iss_stage__maskCondMulIss_0_1_T_1 = iss_stage_bufInfo_1_mul_isa_mul | iss_stage_bufInfo_1_mul_isa_mulh; // @[riscv_isa.scala 203:19]
  wire  iss_stage__maskCondMulIss_0_1_T_2 = iss_stage__maskCondMulIss_0_1_T_1 | iss_stage_bufInfo_1_mul_isa_mulhsu; // @[riscv_isa.scala 203:26]
  wire  iss_stage__maskCondMulIss_0_1_T_3 = iss_stage__maskCondMulIss_0_1_T_2 | iss_stage_bufInfo_1_mul_isa_mulhu; // @[riscv_isa.scala 203:35]
  wire  iss_stage__maskCondMulIss_0_1_T_4 = iss_stage__maskCondMulIss_0_1_T_3 | iss_stage_bufInfo_1_mul_isa_mulw; // @[riscv_isa.scala 203:43]
  wire  iss_stage__maskCondMulIss_0_1_T_5 = iss_stage_bufInfo_1_mul_isa_div | iss_stage_bufInfo_1_mul_isa_divu; // @[riscv_isa.scala 204:19]
  wire  iss_stage__maskCondMulIss_0_1_T_6 = iss_stage__maskCondMulIss_0_1_T_5 | iss_stage_bufInfo_1_mul_isa_divw; // @[riscv_isa.scala 204:26]
  wire  iss_stage__maskCondMulIss_0_1_T_7 = iss_stage__maskCondMulIss_0_1_T_6 | iss_stage_bufInfo_1_mul_isa_divuw; // @[riscv_isa.scala 204:33]
  wire  iss_stage__maskCondMulIss_0_1_T_8 = iss_stage__maskCondMulIss_0_1_T_7 | iss_stage_bufInfo_1_mul_isa_rem; // @[riscv_isa.scala 204:41]
  wire  iss_stage__maskCondMulIss_0_1_T_9 = iss_stage__maskCondMulIss_0_1_T_8 | iss_stage_bufInfo_1_mul_isa_remu; // @[riscv_isa.scala 204:47]
  wire  iss_stage__maskCondMulIss_0_1_T_10 = iss_stage__maskCondMulIss_0_1_T_9 | iss_stage_bufInfo_1_mul_isa_remw; // @[riscv_isa.scala 204:54]
  wire  iss_stage__maskCondMulIss_0_1_T_11 = iss_stage__maskCondMulIss_0_1_T_10 | iss_stage_bufInfo_1_mul_isa_remuw; // @[riscv_isa.scala 204:61]
  wire  iss_stage__maskCondMulIss_0_1_T_12 = iss_stage__maskCondMulIss_0_1_T_4 | iss_stage__maskCondMulIss_0_1_T_11; // @[riscv_isa.scala 206:25]
  wire  iss_stage__maskCondMulIss_0_1_T_13 = ~iss_stage__maskCondMulIss_0_1_T_12; // @[Issue.scala 682:13]
  wire  iss_stage__maskCondMulIss_0_1_T_14 = iss_stage__io_dptReq_0_ready_T_1 | iss_stage__maskCondMulIss_0_1_T_13; // @[Issue.scala 681:26]
  wire  iss_stage__maskCondMulIss_0_1_T_17 = iss_stage__maskCondMulIss_0_1_T_14 | iss_stage__maskCondAluIss_0_1_T_34; // @[Issue.scala 682:43]
  wire  iss_stage__matrixOut_0_0_T_18 = ~iss_stage__maskCondMulIss_0_0_T_17; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_0_T_19 = iss_stage_ageMatrixW_0_0 & iss_stage__matrixOut_0_0_T_18; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_0_T_20 = iss_stage__matrixOut_0_0_T_19 | iss_stage__maskCondMulIss_0_0_T_17; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_1_T_18 = ~iss_stage__maskCondMulIss_0_1_T_17; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_1_T_19 = iss_stage_ageMatrixW_0_1 & iss_stage__matrixOut_0_1_T_18; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_1_T_20 = iss_stage__matrixOut_0_1_T_19 | iss_stage__maskCondMulIss_0_0_T_17; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_0_T_19 = iss_stage__ageMatrixR_1_0_T & iss_stage__matrixOut_0_0_T_18; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_0_T_20 = iss_stage__matrixOut_1_0_T_19 | iss_stage__maskCondMulIss_0_1_T_17; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_1_T_19 = iss_stage_ageMatrixW_1_1 & iss_stage__matrixOut_0_1_T_18; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_1_T_20 = iss_stage__matrixOut_1_1_T_19 | iss_stage__maskCondMulIss_0_1_T_17; // @[Issue.scala 200:60]
  wire  iss_stage__T_405 = iss_stage__matrixOut_0_0_T_20 & iss_stage__matrixOut_0_1_T_20; // @[Issue.scala 693:61]
  wire  iss_stage__T_409 = iss_stage__matrixOut_1_0_T_20 & iss_stage__matrixOut_1_1_T_20; // @[Issue.scala 693:61]
  wire  iss_stage__T_411 = iss_stage__T_405 & iss_stage__T_409; // @[Issue.scala 693:33]
  wire  iss_stage__T_412 = ~iss_stage__matrixOut_0_0_T_20; // @[Issue.scala 694:84]
  wire  iss_stage__T_413 = ~iss_stage__matrixOut_0_1_T_20; // @[Issue.scala 694:84]
  wire  iss_stage__T_415 = iss_stage__T_412 & iss_stage__T_413; // @[Issue.scala 694:67]
  wire  iss_stage__T_416 = ~iss_stage__matrixOut_1_0_T_20; // @[Issue.scala 694:84]
  wire  iss_stage__T_417 = ~iss_stage__matrixOut_1_1_T_20; // @[Issue.scala 694:84]
  wire  iss_stage__T_419 = iss_stage__T_416 & iss_stage__T_417; // @[Issue.scala 694:67]
  wire [1:0] iss_stage__T_420 = iss_stage__T_415 + iss_stage__T_419; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_422 = iss_stage__T_420 == 2'h1; // @[Issue.scala 694:102]
  wire  iss_stage__T_423 = iss_stage__T_411 | iss_stage__T_422; // @[Issue.scala 693:95]
  wire  iss_stage__T_426 = ~iss_stage__T_423; // @[Issue.scala 692:13]
  wire  iss_stage__mulIssIdx_0_T_8 = iss_stage__T_415 ? 1'h0 : 1'h1; // @[Issue.scala 700:53]
  wire [63:0] iss_stage_mulIssInfo_0_param_dat_op2 = iss_stage__postBufOperator_0_1_T_8[63:0]; // @[Issue.scala 657:19 661:23]
  wire [63:0] iss_stage__mulIssFifo_0_io_enq_bits_T_11 = iss_stage__T_415 ? iss_stage_mulIssInfo_0_param_dat_op2 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_mulIssInfo_1_param_dat_op2 = iss_stage__postBufOperator_1_1_T_8[63:0]; // @[Issue.scala 657:19 661:23]
  wire [63:0] iss_stage__mulIssFifo_0_io_enq_bits_T_12 = iss_stage__T_419 ? iss_stage_mulIssInfo_1_param_dat_op2 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_mulIssInfo_0_param_dat_op1 = iss_stage__postBufOperator_0_0_T_8[63:0]; // @[Issue.scala 657:19 660:23]
  wire [63:0] iss_stage__mulIssFifo_0_io_enq_bits_T_14 = iss_stage__T_415 ? iss_stage_mulIssInfo_0_param_dat_op1 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_mulIssInfo_1_param_dat_op1 = iss_stage__postBufOperator_1_0_T_8[63:0]; // @[Issue.scala 657:19 660:23]
  wire [63:0] iss_stage__mulIssFifo_0_io_enq_bits_T_15 = iss_stage__T_419 ? iss_stage_mulIssInfo_1_param_dat_op1 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__mulIssFifo_0_io_enq_bits_T_17 = iss_stage__T_415 ? iss_stage_bufInfo_0_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__mulIssFifo_0_io_enq_bits_T_18 = iss_stage__T_419 ? iss_stage_bufInfo_1_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_20 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_remuw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_21 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_remuw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_23 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_remw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_24 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_remw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_26 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_divuw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_27 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_divuw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_29 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_divw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_30 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_divw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_32 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_mulw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_33 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_mulw; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_35 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_remu; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_36 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_remu; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_38 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_rem; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_39 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_rem; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_41 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_divu; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_42 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_divu; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_44 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_div; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_45 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_div; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_47 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_mulhu; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_48 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_mulhu; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_50 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_mulhsu; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_51 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_mulhsu; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_53 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_mulh; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_54 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_mulh; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_56 = iss_stage__T_415 & iss_stage_bufInfo_0_mul_isa_mul; // @[Mux.scala 27:73]
  wire  iss_stage__mulIssFifo_0_io_enq_bits_T_57 = iss_stage__T_419 & iss_stage_bufInfo_1_mul_isa_mul; // @[Mux.scala 27:73]
  wire  iss_stage__T_428 = ~iss_stage__mulIssIdx_0_T_8; // @[Issue.scala 705:60]
  wire  iss_stage__T_429 = iss_stage_mulIssFifo_0__do_enq_T & iss_stage__T_428; // @[Issue.scala 705:43]
  wire  iss_stage__GEN_1806 = iss_stage__T_429 ? 1'h0 : iss_stage__GEN_1804; // @[Issue.scala 705:70 706:23]
  wire  iss_stage__T_454 = iss_stage_mulIssFifo_0__do_enq_T & iss_stage__mulIssIdx_0_T_8; // @[Issue.scala 705:43]
  wire  iss_stage__GEN_1807 = iss_stage__T_454 ? 1'h0 : iss_stage__GEN_1805; // @[Issue.scala 705:70 706:23]
  wire  iss_stage__maskCondBruIss_0_T_1 = iss_stage_bufInfo_0_bru_isa_jal | iss_stage_bufInfo_0_bru_isa_jalr; // @[riscv_isa.scala 92:20]
  wire  iss_stage__maskCondBruIss_0_T_2 = iss_stage__maskCondBruIss_0_T_1 | iss_stage_bufInfo_0_bru_isa_beq; // @[riscv_isa.scala 92:27]
  wire  iss_stage__maskCondBruIss_0_T_3 = iss_stage__maskCondBruIss_0_T_2 | iss_stage_bufInfo_0_bru_isa_bne; // @[riscv_isa.scala 92:33]
  wire  iss_stage__maskCondBruIss_0_T_4 = iss_stage__maskCondBruIss_0_T_3 | iss_stage_bufInfo_0_bru_isa_blt; // @[riscv_isa.scala 92:39]
  wire  iss_stage__maskCondBruIss_0_T_5 = iss_stage__maskCondBruIss_0_T_4 | iss_stage_bufInfo_0_bru_isa_bge; // @[riscv_isa.scala 92:45]
  wire  iss_stage__maskCondBruIss_0_T_6 = iss_stage__maskCondBruIss_0_T_5 | iss_stage_bufInfo_0_bru_isa_bltu; // @[riscv_isa.scala 92:51]
  wire  iss_stage__maskCondBruIss_0_T_7 = iss_stage__maskCondBruIss_0_T_6 | iss_stage_bufInfo_0_bru_isa_bgeu; // @[riscv_isa.scala 92:58]
  wire  iss_stage__maskCondBruIss_0_T_8 = ~iss_stage__maskCondBruIss_0_T_7; // @[Issue.scala 752:7]
  wire  iss_stage__maskCondBruIss_0_T_9 = iss_stage__entrySel_T | iss_stage__maskCondBruIss_0_T_8; // @[Issue.scala 751:20]
  wire  iss_stage__maskCondBruIss_1_T_1 = iss_stage_bufInfo_1_bru_isa_jal | iss_stage_bufInfo_1_bru_isa_jalr; // @[riscv_isa.scala 92:20]
  wire  iss_stage__maskCondBruIss_1_T_2 = iss_stage__maskCondBruIss_1_T_1 | iss_stage_bufInfo_1_bru_isa_beq; // @[riscv_isa.scala 92:27]
  wire  iss_stage__maskCondBruIss_1_T_3 = iss_stage__maskCondBruIss_1_T_2 | iss_stage_bufInfo_1_bru_isa_bne; // @[riscv_isa.scala 92:33]
  wire  iss_stage__maskCondBruIss_1_T_4 = iss_stage__maskCondBruIss_1_T_3 | iss_stage_bufInfo_1_bru_isa_blt; // @[riscv_isa.scala 92:39]
  wire  iss_stage__maskCondBruIss_1_T_5 = iss_stage__maskCondBruIss_1_T_4 | iss_stage_bufInfo_1_bru_isa_bge; // @[riscv_isa.scala 92:45]
  wire  iss_stage__maskCondBruIss_1_T_6 = iss_stage__maskCondBruIss_1_T_5 | iss_stage_bufInfo_1_bru_isa_bltu; // @[riscv_isa.scala 92:51]
  wire  iss_stage__maskCondBruIss_1_T_7 = iss_stage__maskCondBruIss_1_T_6 | iss_stage_bufInfo_1_bru_isa_bgeu; // @[riscv_isa.scala 92:58]
  wire  iss_stage__maskCondBruIss_1_T_8 = ~iss_stage__maskCondBruIss_1_T_7; // @[Issue.scala 752:7]
  wire  iss_stage__maskCondBruIss_1_T_9 = iss_stage__io_dptReq_0_ready_T_1 | iss_stage__maskCondBruIss_1_T_8; // @[Issue.scala 751:20]
  wire  iss_stage__matrixOut_0_0_T_21 = ~iss_stage__maskCondBruIss_0_T_9; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_0_T_22 = iss_stage_ageMatrixW_0_0 & iss_stage__matrixOut_0_0_T_21; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_0_T_23 = iss_stage__matrixOut_0_0_T_22 | iss_stage__maskCondBruIss_0_T_9; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_1_T_21 = ~iss_stage__maskCondBruIss_1_T_9; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_1_T_22 = iss_stage_ageMatrixW_0_1 & iss_stage__matrixOut_0_1_T_21; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_1_T_23 = iss_stage__matrixOut_0_1_T_22 | iss_stage__maskCondBruIss_0_T_9; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_0_T_22 = iss_stage__ageMatrixR_1_0_T & iss_stage__matrixOut_0_0_T_21; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_0_T_23 = iss_stage__matrixOut_1_0_T_22 | iss_stage__maskCondBruIss_1_T_9; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_1_T_22 = iss_stage_ageMatrixW_1_1 & iss_stage__matrixOut_0_1_T_21; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_1_T_23 = iss_stage__matrixOut_1_1_T_22 | iss_stage__maskCondBruIss_1_T_9; // @[Issue.scala 200:60]
  wire  iss_stage__T_480 = iss_stage__matrixOut_0_0_T_23 & iss_stage__matrixOut_0_1_T_23; // @[Issue.scala 758:52]
  wire  iss_stage__T_484 = iss_stage__matrixOut_1_0_T_23 & iss_stage__matrixOut_1_1_T_23; // @[Issue.scala 758:52]
  wire  iss_stage__T_486 = iss_stage__T_480 & iss_stage__T_484; // @[Issue.scala 758:24]
  wire  iss_stage__T_487 = ~iss_stage__matrixOut_0_0_T_23; // @[Issue.scala 759:75]
  wire  iss_stage__T_488 = ~iss_stage__matrixOut_0_1_T_23; // @[Issue.scala 759:75]
  wire  iss_stage__T_490 = iss_stage__T_487 & iss_stage__T_488; // @[Issue.scala 759:58]
  wire  iss_stage__T_491 = ~iss_stage__matrixOut_1_0_T_23; // @[Issue.scala 759:75]
  wire  iss_stage__T_492 = ~iss_stage__matrixOut_1_1_T_23; // @[Issue.scala 759:75]
  wire  iss_stage__T_494 = iss_stage__T_491 & iss_stage__T_492; // @[Issue.scala 759:58]
  wire [1:0] iss_stage__T_495 = iss_stage__T_490 + iss_stage__T_494; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_497 = iss_stage__T_495 == 2'h1; // @[Issue.scala 759:92]
  wire  iss_stage__T_498 = iss_stage__T_486 | iss_stage__T_497; // @[Issue.scala 758:86]
  wire  iss_stage__T_501 = ~iss_stage__T_498; // @[Issue.scala 757:9]
  wire  iss_stage__bruIssIdx_T_8 = iss_stage__T_490 ? 1'h0 : 1'h1; // @[Issue.scala 762:39]
  wire  iss_stage__bruIssFifo_io_enq_valid_T_4 = iss_stage__T_490 & iss_stage__postIsOpReady_0_0_T_8; // @[Issue.scala 765:93]
  wire  iss_stage__bruIssFifo_io_enq_valid_T_5 = iss_stage__bruIssFifo_io_enq_valid_T_4 &
    iss_stage__postIsOpReady_0_1_T_8; // @[Issue.scala 765:115]
  wire  iss_stage__bruIssFifo_io_enq_valid_T_10 = iss_stage__T_494 & iss_stage__postIsOpReady_1_0_T_8; // @[Issue.scala 765:93]
  wire  iss_stage__bruIssFifo_io_enq_valid_T_11 = iss_stage__bruIssFifo_io_enq_valid_T_10 &
    iss_stage__postIsOpReady_1_1_T_8; // @[Issue.scala 765:115]
  wire [63:0] iss_stage__bruIssFifo_io_enq_bits_T_15 = iss_stage__bruIssFifo_io_enq_valid_T_5 ?
    iss_stage_mulIssInfo_0_param_dat_op2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__bruIssFifo_io_enq_bits_T_16 = iss_stage__bruIssFifo_io_enq_valid_T_11 ?
    iss_stage_mulIssInfo_1_param_dat_op2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__bruIssFifo_io_enq_bits_T_18 = iss_stage__bruIssFifo_io_enq_valid_T_5 ?
    iss_stage_mulIssInfo_0_param_dat_op1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__bruIssFifo_io_enq_bits_T_19 = iss_stage__bruIssFifo_io_enq_valid_T_11 ?
    iss_stage_mulIssInfo_1_param_dat_op1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__bruIssFifo_io_enq_bits_T_21 = iss_stage__bruIssFifo_io_enq_valid_T_5 ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__bruIssFifo_io_enq_bits_T_22 = iss_stage__bruIssFifo_io_enq_valid_T_11 ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__bruIssFifo_io_enq_bits_T_24 = iss_stage__bruIssFifo_io_enq_valid_T_5 ?
    iss_stage__aluIssInfo_res_param_dat_op1_v64_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__bruIssFifo_io_enq_bits_T_25 = iss_stage__bruIssFifo_io_enq_valid_T_11 ?
    iss_stage__aluIssInfo_res_param_dat_op1_v64_T_9 : 64'h0; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_27 = iss_stage__bruIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_param_is_rvc; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_28 = iss_stage__bruIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_param_is_rvc; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__bruIssFifo_io_enq_bits_T_30 = iss_stage__bruIssFifo_io_enq_valid_T_5 ?
    iss_stage_bufInfo_0_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__bruIssFifo_io_enq_bits_T_31 = iss_stage__bruIssFifo_io_enq_valid_T_11 ?
    iss_stage_bufInfo_1_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_33 = iss_stage__bruIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_bru_isa_bgeu; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_34 = iss_stage__bruIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_bru_isa_bgeu; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_36 = iss_stage__bruIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_bru_isa_bltu; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_37 = iss_stage__bruIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_bru_isa_bltu; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_39 = iss_stage__bruIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_bru_isa_bge; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_40 = iss_stage__bruIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_bru_isa_bge; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_42 = iss_stage__bruIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_bru_isa_blt; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_43 = iss_stage__bruIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_bru_isa_blt; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_45 = iss_stage__bruIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_bru_isa_bne; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_46 = iss_stage__bruIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_bru_isa_bne; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_48 = iss_stage__bruIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_bru_isa_beq; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_49 = iss_stage__bruIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_bru_isa_beq; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_51 = iss_stage__bruIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_bru_isa_jalr; // @[Mux.scala 27:73]
  wire  iss_stage__bruIssFifo_io_enq_bits_T_52 = iss_stage__bruIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_bru_isa_jalr; // @[Mux.scala 27:73]
  wire  iss_stage__T_503 = ~iss_stage__bruIssIdx_T_8; // @[Issue.scala 771:46]
  wire  iss_stage__T_504 = iss_stage_bruIssFifo__do_enq_T & iss_stage__T_503; // @[Issue.scala 771:34]
  wire  iss_stage__T_524 = iss_stage_bruIssFifo__do_enq_T & iss_stage__bruIssIdx_T_8; // @[Issue.scala 771:34]
  wire  iss_stage__csrIssInfo_res_fun_rc_T = iss_stage_bufInfo_0_csr_isa_rc | iss_stage_bufInfo_0_csr_isa_rci; // @[Issue.scala 789:44]
  wire  iss_stage__csrIssInfo_res_fun_rs_T = iss_stage_bufInfo_0_csr_isa_rs | iss_stage_bufInfo_0_csr_isa_rsi; // @[Issue.scala 790:44]
  wire  iss_stage__csrIssInfo_res_fun_rw_T = iss_stage_bufInfo_0_csr_isa_rw | iss_stage_bufInfo_0_csr_isa_rwi; // @[Issue.scala 791:44]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T = iss_stage_bufInfo_0_csr_isa_rw ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [4:0] iss_stage__csrIssInfo_res_param_dat_op1_T_1 = iss_stage_bufInfo_0_csr_isa_rwi ?
    iss_stage_bufInfo_0_param_raw_rs1 : 5'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_2 = iss_stage_bufInfo_0_csr_isa_rs ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [4:0] iss_stage__csrIssInfo_res_param_dat_op1_T_3 = iss_stage_bufInfo_0_csr_isa_rsi ?
    iss_stage_bufInfo_0_param_raw_rs1 : 5'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_4 = iss_stage_bufInfo_0_csr_isa_rc ?
    iss_stage__postBufOperator_0_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [4:0] iss_stage__csrIssInfo_res_param_dat_op1_T_5 = iss_stage_bufInfo_0_csr_isa_rci ?
    iss_stage_bufInfo_0_param_raw_rs1 : 5'h0; // @[Mux.scala 27:73]
  wire [64:0] _GEN_248 = {{60'd0}, iss_stage__csrIssInfo_res_param_dat_op1_T_1}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_6 = iss_stage__csrIssInfo_res_param_dat_op1_T | _GEN_248; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_7 = iss_stage__csrIssInfo_res_param_dat_op1_T_6 |
    iss_stage__csrIssInfo_res_param_dat_op1_T_2; // @[Mux.scala 27:73]
  wire [64:0] _GEN_249 = {{60'd0}, iss_stage__csrIssInfo_res_param_dat_op1_T_3}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_8 = iss_stage__csrIssInfo_res_param_dat_op1_T_7 | _GEN_249; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_9 = iss_stage__csrIssInfo_res_param_dat_op1_T_8 |
    iss_stage__csrIssInfo_res_param_dat_op1_T_4; // @[Mux.scala 27:73]
  wire [64:0] _GEN_250 = {{60'd0}, iss_stage__csrIssInfo_res_param_dat_op1_T_5}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_10 = iss_stage__csrIssInfo_res_param_dat_op1_T_9 | _GEN_250; // @[Mux.scala 27:73]
  wire  iss_stage__csrIssInfo_res_fun_rc_T_1 = iss_stage_bufInfo_1_csr_isa_rc | iss_stage_bufInfo_1_csr_isa_rci; // @[Issue.scala 789:44]
  wire  iss_stage__csrIssInfo_res_fun_rs_T_1 = iss_stage_bufInfo_1_csr_isa_rs | iss_stage_bufInfo_1_csr_isa_rsi; // @[Issue.scala 790:44]
  wire  iss_stage__csrIssInfo_res_fun_rw_T_1 = iss_stage_bufInfo_1_csr_isa_rw | iss_stage_bufInfo_1_csr_isa_rwi; // @[Issue.scala 791:44]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_11 = iss_stage_bufInfo_1_csr_isa_rw ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [4:0] iss_stage__csrIssInfo_res_param_dat_op1_T_12 = iss_stage_bufInfo_1_csr_isa_rwi ?
    iss_stage_bufInfo_1_param_raw_rs1 : 5'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_13 = iss_stage_bufInfo_1_csr_isa_rs ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [4:0] iss_stage__csrIssInfo_res_param_dat_op1_T_14 = iss_stage_bufInfo_1_csr_isa_rsi ?
    iss_stage_bufInfo_1_param_raw_rs1 : 5'h0; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_15 = iss_stage_bufInfo_1_csr_isa_rc ?
    iss_stage__postBufOperator_1_0_T_8 : 65'h0; // @[Mux.scala 27:73]
  wire [4:0] iss_stage__csrIssInfo_res_param_dat_op1_T_16 = iss_stage_bufInfo_1_csr_isa_rci ?
    iss_stage_bufInfo_1_param_raw_rs1 : 5'h0; // @[Mux.scala 27:73]
  wire [64:0] _GEN_251 = {{60'd0}, iss_stage__csrIssInfo_res_param_dat_op1_T_12}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_17 = iss_stage__csrIssInfo_res_param_dat_op1_T_11 | _GEN_251; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_18 = iss_stage__csrIssInfo_res_param_dat_op1_T_17 |
    iss_stage__csrIssInfo_res_param_dat_op1_T_13; // @[Mux.scala 27:73]
  wire [64:0] _GEN_252 = {{60'd0}, iss_stage__csrIssInfo_res_param_dat_op1_T_14}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_19 = iss_stage__csrIssInfo_res_param_dat_op1_T_18 | _GEN_252; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_20 = iss_stage__csrIssInfo_res_param_dat_op1_T_19 |
    iss_stage__csrIssInfo_res_param_dat_op1_T_15; // @[Mux.scala 27:73]
  wire [64:0] _GEN_253 = {{60'd0}, iss_stage__csrIssInfo_res_param_dat_op1_T_16}; // @[Mux.scala 27:73]
  wire [64:0] iss_stage__csrIssInfo_res_param_dat_op1_T_21 = iss_stage__csrIssInfo_res_param_dat_op1_T_20 | _GEN_253; // @[Mux.scala 27:73]
  wire  iss_stage__maskCondCsrIss_0_T_1 = iss_stage_bufInfo_0_csr_isa_rw | iss_stage_bufInfo_0_csr_isa_rs; // @[riscv_isa.scala 179:19]
  wire  iss_stage__maskCondCsrIss_0_T_2 = iss_stage__maskCondCsrIss_0_T_1 | iss_stage_bufInfo_0_csr_isa_rc; // @[riscv_isa.scala 179:24]
  wire  iss_stage__maskCondCsrIss_0_T_3 = iss_stage__maskCondCsrIss_0_T_2 | iss_stage_bufInfo_0_csr_isa_rwi; // @[riscv_isa.scala 179:29]
  wire  iss_stage__maskCondCsrIss_0_T_4 = iss_stage__maskCondCsrIss_0_T_3 | iss_stage_bufInfo_0_csr_isa_rsi; // @[riscv_isa.scala 179:35]
  wire  iss_stage__maskCondCsrIss_0_T_5 = iss_stage__maskCondCsrIss_0_T_4 | iss_stage_bufInfo_0_csr_isa_rci; // @[riscv_isa.scala 179:41]
  wire  iss_stage__maskCondCsrIss_0_T_6 = ~iss_stage__maskCondCsrIss_0_T_5; // @[Issue.scala 818:7]
  wire  iss_stage__maskCondCsrIss_0_T_7 = iss_stage__entrySel_T | iss_stage__maskCondCsrIss_0_T_6; // @[Issue.scala 817:20]
  wire  iss_stage__maskCondCsrIss_1_T_1 = iss_stage_bufInfo_1_csr_isa_rw | iss_stage_bufInfo_1_csr_isa_rs; // @[riscv_isa.scala 179:19]
  wire  iss_stage__maskCondCsrIss_1_T_2 = iss_stage__maskCondCsrIss_1_T_1 | iss_stage_bufInfo_1_csr_isa_rc; // @[riscv_isa.scala 179:24]
  wire  iss_stage__maskCondCsrIss_1_T_3 = iss_stage__maskCondCsrIss_1_T_2 | iss_stage_bufInfo_1_csr_isa_rwi; // @[riscv_isa.scala 179:29]
  wire  iss_stage__maskCondCsrIss_1_T_4 = iss_stage__maskCondCsrIss_1_T_3 | iss_stage_bufInfo_1_csr_isa_rsi; // @[riscv_isa.scala 179:35]
  wire  iss_stage__maskCondCsrIss_1_T_5 = iss_stage__maskCondCsrIss_1_T_4 | iss_stage_bufInfo_1_csr_isa_rci; // @[riscv_isa.scala 179:41]
  wire  iss_stage__maskCondCsrIss_1_T_6 = ~iss_stage__maskCondCsrIss_1_T_5; // @[Issue.scala 818:7]
  wire  iss_stage__maskCondCsrIss_1_T_7 = iss_stage__io_dptReq_0_ready_T_1 | iss_stage__maskCondCsrIss_1_T_6; // @[Issue.scala 817:20]
  wire  iss_stage__matrixOut_0_0_T_24 = ~iss_stage__maskCondCsrIss_0_T_7; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_0_T_25 = iss_stage_ageMatrixW_0_0 & iss_stage__matrixOut_0_0_T_24; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_0_T_26 = iss_stage__matrixOut_0_0_T_25 | iss_stage__maskCondCsrIss_0_T_7; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_1_T_24 = ~iss_stage__maskCondCsrIss_1_T_7; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_1_T_25 = iss_stage_ageMatrixW_0_1 & iss_stage__matrixOut_0_1_T_24; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_1_T_26 = iss_stage__matrixOut_0_1_T_25 | iss_stage__maskCondCsrIss_0_T_7; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_0_T_25 = iss_stage__ageMatrixR_1_0_T & iss_stage__matrixOut_0_0_T_24; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_0_T_26 = iss_stage__matrixOut_1_0_T_25 | iss_stage__maskCondCsrIss_1_T_7; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_1_T_25 = iss_stage_ageMatrixW_1_1 & iss_stage__matrixOut_0_1_T_24; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_1_T_26 = iss_stage__matrixOut_1_1_T_25 | iss_stage__maskCondCsrIss_1_T_7; // @[Issue.scala 200:60]
  wire  iss_stage__T_545 = iss_stage__matrixOut_0_0_T_26 & iss_stage__matrixOut_0_1_T_26; // @[Issue.scala 824:52]
  wire  iss_stage__T_549 = iss_stage__matrixOut_1_0_T_26 & iss_stage__matrixOut_1_1_T_26; // @[Issue.scala 824:52]
  wire  iss_stage__T_551 = iss_stage__T_545 & iss_stage__T_549; // @[Issue.scala 824:24]
  wire  iss_stage__T_552 = ~iss_stage__matrixOut_0_0_T_26; // @[Issue.scala 825:75]
  wire  iss_stage__T_553 = ~iss_stage__matrixOut_0_1_T_26; // @[Issue.scala 825:75]
  wire  iss_stage__T_555 = iss_stage__T_552 & iss_stage__T_553; // @[Issue.scala 825:58]
  wire  iss_stage__T_556 = ~iss_stage__matrixOut_1_0_T_26; // @[Issue.scala 825:75]
  wire  iss_stage__T_557 = ~iss_stage__matrixOut_1_1_T_26; // @[Issue.scala 825:75]
  wire  iss_stage__T_559 = iss_stage__T_556 & iss_stage__T_557; // @[Issue.scala 825:58]
  wire [1:0] iss_stage__T_560 = iss_stage__T_555 + iss_stage__T_559; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_562 = iss_stage__T_560 == 2'h1; // @[Issue.scala 825:92]
  wire  iss_stage__T_563 = iss_stage__T_551 | iss_stage__T_562; // @[Issue.scala 824:86]
  wire  iss_stage__T_566 = ~iss_stage__T_563; // @[Issue.scala 823:9]
  wire  iss_stage__csrIssIdx_T_8 = iss_stage__T_555 ? 1'h0 : 1'h1; // @[Issue.scala 828:39]
  wire  iss_stage__csrIssFifo_io_enq_valid_T_4 = iss_stage__T_555 & iss_stage__postIsOpReady_0_0_T_8; // @[Issue.scala 831:93]
  wire  iss_stage__csrIssFifo_io_enq_valid_T_5 = iss_stage__csrIssFifo_io_enq_valid_T_4 &
    iss_stage__postIsOpReady_0_1_T_8; // @[Issue.scala 831:115]
  wire  iss_stage__csrIssFifo_io_enq_valid_T_10 = iss_stage__T_559 & iss_stage__postIsOpReady_1_0_T_8; // @[Issue.scala 831:93]
  wire  iss_stage__csrIssFifo_io_enq_valid_T_11 = iss_stage__csrIssFifo_io_enq_valid_T_10 &
    iss_stage__postIsOpReady_1_1_T_8; // @[Issue.scala 831:115]
  wire [63:0] iss_stage__csrIssFifo_io_enq_bits_T_15 = iss_stage__csrIssFifo_io_enq_valid_T_5 ?
    iss_stage_bufInfo_0_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage__csrIssFifo_io_enq_bits_T_16 = iss_stage__csrIssFifo_io_enq_valid_T_11 ?
    iss_stage_bufInfo_1_param_imm : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_csrIssInfo_0_param_dat_op1 = iss_stage__csrIssInfo_res_param_dat_op1_T_10[63:0]; // @[Issue.scala 787:19 793:23]
  wire [63:0] iss_stage__csrIssFifo_io_enq_bits_T_18 = iss_stage__csrIssFifo_io_enq_valid_T_5 ?
    iss_stage_csrIssInfo_0_param_dat_op1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_csrIssInfo_1_param_dat_op1 = iss_stage__csrIssInfo_res_param_dat_op1_T_21[63:0]; // @[Issue.scala 787:19 793:23]
  wire [63:0] iss_stage__csrIssFifo_io_enq_bits_T_19 = iss_stage__csrIssFifo_io_enq_valid_T_11 ?
    iss_stage_csrIssInfo_1_param_dat_op1 : 64'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__csrIssFifo_io_enq_bits_T_21 = iss_stage__csrIssFifo_io_enq_valid_T_5 ?
    iss_stage_bufInfo_0_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__csrIssFifo_io_enq_bits_T_22 = iss_stage__csrIssFifo_io_enq_valid_T_11 ?
    iss_stage_bufInfo_1_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire  iss_stage__csrIssFifo_io_enq_bits_T_24 = iss_stage__csrIssFifo_io_enq_valid_T_5 &
    iss_stage__csrIssInfo_res_fun_rc_T; // @[Mux.scala 27:73]
  wire  iss_stage__csrIssFifo_io_enq_bits_T_25 = iss_stage__csrIssFifo_io_enq_valid_T_11 &
    iss_stage__csrIssInfo_res_fun_rc_T_1; // @[Mux.scala 27:73]
  wire  iss_stage__csrIssFifo_io_enq_bits_T_27 = iss_stage__csrIssFifo_io_enq_valid_T_5 &
    iss_stage__csrIssInfo_res_fun_rs_T; // @[Mux.scala 27:73]
  wire  iss_stage__csrIssFifo_io_enq_bits_T_28 = iss_stage__csrIssFifo_io_enq_valid_T_11 &
    iss_stage__csrIssInfo_res_fun_rs_T_1; // @[Mux.scala 27:73]
  wire  iss_stage__csrIssFifo_io_enq_bits_T_30 = iss_stage__csrIssFifo_io_enq_valid_T_5 &
    iss_stage__csrIssInfo_res_fun_rw_T; // @[Mux.scala 27:73]
  wire  iss_stage__csrIssFifo_io_enq_bits_T_31 = iss_stage__csrIssFifo_io_enq_valid_T_11 &
    iss_stage__csrIssInfo_res_fun_rw_T_1; // @[Mux.scala 27:73]
  wire  iss_stage__T_568 = ~iss_stage__csrIssIdx_T_8; // @[Issue.scala 837:46]
  wire  iss_stage__T_569 = iss_stage_csrIssFifo__do_enq_T & iss_stage__T_568; // @[Issue.scala 837:34]
  wire  iss_stage__T_587 = iss_stage_csrIssFifo__do_enq_T & iss_stage__csrIssIdx_T_8; // @[Issue.scala 837:34]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T = iss_stage_bufInfo_0_lsu_isa_sc_d | iss_stage_bufInfo_0_lsu_isa_sc_w; // @[riscv_isa.scala 140:20]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_1 = iss_stage_bufInfo_0_lsu_isa_lr_d |
    iss_stage_bufInfo_0_lsu_isa_lr_w; // @[riscv_isa.scala 141:20]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_2 = iss_stage__lsuIssInfo_res_param_dat_op1_T |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_1; // @[riscv_isa.scala 146:23]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_3 = iss_stage_bufInfo_0_lsu_isa_amoswap_w |
    iss_stage_bufInfo_0_lsu_isa_amoadd_w; // @[riscv_isa.scala 148:15]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_4 = iss_stage__lsuIssInfo_res_param_dat_op1_T_3 |
    iss_stage_bufInfo_0_lsu_isa_amoxor_w; // @[riscv_isa.scala 148:26]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_5 = iss_stage__lsuIssInfo_res_param_dat_op1_T_4 |
    iss_stage_bufInfo_0_lsu_isa_amoand_w; // @[riscv_isa.scala 148:37]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_6 = iss_stage__lsuIssInfo_res_param_dat_op1_T_5 |
    iss_stage_bufInfo_0_lsu_isa_amoor_w; // @[riscv_isa.scala 148:48]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_7 = iss_stage__lsuIssInfo_res_param_dat_op1_T_6 |
    iss_stage_bufInfo_0_lsu_isa_amomin_w; // @[riscv_isa.scala 148:58]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_8 = iss_stage__lsuIssInfo_res_param_dat_op1_T_7 |
    iss_stage_bufInfo_0_lsu_isa_amomax_w; // @[riscv_isa.scala 148:69]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_9 = iss_stage__lsuIssInfo_res_param_dat_op1_T_8 |
    iss_stage_bufInfo_0_lsu_isa_amominu_w; // @[riscv_isa.scala 148:80]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_10 = iss_stage__lsuIssInfo_res_param_dat_op1_T_9 |
    iss_stage_bufInfo_0_lsu_isa_amomaxu_w; // @[riscv_isa.scala 148:92]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_11 = iss_stage__lsuIssInfo_res_param_dat_op1_T_10 |
    iss_stage_bufInfo_0_lsu_isa_amoswap_d; // @[riscv_isa.scala 148:104]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_12 = iss_stage__lsuIssInfo_res_param_dat_op1_T_11 |
    iss_stage_bufInfo_0_lsu_isa_amoadd_d; // @[riscv_isa.scala 148:116]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_13 = iss_stage__lsuIssInfo_res_param_dat_op1_T_12 |
    iss_stage_bufInfo_0_lsu_isa_amoxor_d; // @[riscv_isa.scala 148:127]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_14 = iss_stage__lsuIssInfo_res_param_dat_op1_T_13 |
    iss_stage_bufInfo_0_lsu_isa_amoand_d; // @[riscv_isa.scala 148:138]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_15 = iss_stage__lsuIssInfo_res_param_dat_op1_T_14 |
    iss_stage_bufInfo_0_lsu_isa_amoor_d; // @[riscv_isa.scala 148:149]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_16 = iss_stage__lsuIssInfo_res_param_dat_op1_T_15 |
    iss_stage_bufInfo_0_lsu_isa_amomin_d; // @[riscv_isa.scala 148:159]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_17 = iss_stage__lsuIssInfo_res_param_dat_op1_T_16 |
    iss_stage_bufInfo_0_lsu_isa_amomax_d; // @[riscv_isa.scala 148:170]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_18 = iss_stage__lsuIssInfo_res_param_dat_op1_T_17 |
    iss_stage_bufInfo_0_lsu_isa_amominu_d; // @[riscv_isa.scala 148:181]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_19 = iss_stage__lsuIssInfo_res_param_dat_op1_T_18 |
    iss_stage_bufInfo_0_lsu_isa_amomaxu_d; // @[riscv_isa.scala 148:193]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_21 = iss_stage__lsuIssInfo_res_param_dat_op1_T_19 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T; // @[riscv_isa.scala 148:205]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_22 = iss_stage__lsuIssInfo_res_param_dat_op1_T_2 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_21; // @[Issue.scala 857:42]
  wire [64:0] iss_stage__lsuIssInfo_res_param_dat_op1_T_23 = iss_stage__canIOpReq_0_0_T_6 ? {{1'd0},
    iss_stage_io_irgRsp_0_bits_op} : iss_stage_bufOperator_0_0; // @[Issue.scala 857:125]
  wire [63:0] iss_stage__lsuIssInfo_res_param_dat_op1_T_24 = iss_stage_bufInfo_0_param_imm; // @[Issue.scala 857:163]
  wire [64:0] _GEN_254 = {{1{iss_stage__lsuIssInfo_res_param_dat_op1_T_24[63]}},
    iss_stage__lsuIssInfo_res_param_dat_op1_T_24}; // @[Issue.scala 857:132]
  wire [64:0] iss_stage__lsuIssInfo_res_param_dat_op1_T_28 = $signed(iss_stage__lsuIssInfo_res_param_dat_op1_T_23) +
    $signed(_GEN_254); // @[Issue.scala 857:173]
  wire [64:0] iss_stage__lsuIssInfo_res_param_dat_op1_T_29 = iss_stage__lsuIssInfo_res_param_dat_op1_T_22 ?
    iss_stage__postBufOperator_0_0_T_8 : iss_stage__lsuIssInfo_res_param_dat_op1_T_28; // @[Issue.scala 857:10]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_T = iss_stage_bufInfo_0_lsu_isa_fsw | iss_stage_bufInfo_0_lsu_isa_fsd; // @[riscv_isa.scala 164:20]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T = iss_stage__postBufOperator_0_1_T_8[31]; // @[Fpu.scala 143:14]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_1 = iss_stage__postBufOperator_0_1_T_8[52]; // @[Fpu.scala 144:14]
  wire [30:0] iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_2 = iss_stage__postBufOperator_0_1_T_8[30:0]; // @[Fpu.scala 145:14]
  wire [32:0] iss_stage_lsuIssInfo_res_param_dat_op2_unswizzled = {iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T,
    iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_1,iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_2}; // @[Cat.scala 33:92]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_sign = iss_stage_lsuIssInfo_res_param_dat_op2_unswizzled[32]; // @[Fpu.scala 59:17]
  wire [22:0] iss_stage_lsuIssInfo_res_param_dat_op2_fractIn = iss_stage_lsuIssInfo_res_param_dat_op2_unswizzled[22:0]; // @[Fpu.scala 60:20]
  wire [8:0] iss_stage_lsuIssInfo_res_param_dat_op2_expIn = iss_stage_lsuIssInfo_res_param_dat_op2_unswizzled[31:23]; // @[Fpu.scala 61:18]
  wire [2:0] iss_stage_lsuIssInfo_res_param_dat_op2_expOut_expCode = iss_stage_lsuIssInfo_res_param_dat_op2_expIn[8:6]; // @[Fpu.scala 64:26]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_expOut_T = iss_stage_lsuIssInfo_res_param_dat_op2_expOut_expCode == 3'h0
    ; // @[Fpu.scala 66:19]
  wire [11:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp = iss_stage__postBufOperator_0_1_T_8[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire [2:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isZero_T =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala 51:29]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isZero =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire [1:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial_T =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala 52:29]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial_T == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:41]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T_1 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial &
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala 55:33]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_1 = ~
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala 56:36]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_2 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial &
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala 56:33]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sign_T = iss_stage__postBufOperator_0_1_T_8[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sExp_T = {1'b0,$signed(
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T = ~
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
  wire [51:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_1 = iss_stage__postBufOperator_0_1_T_8[
    51:0]; // @[rawFloatFromRecFN.scala 60:51]
  wire [53:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_2 = {1'h0,
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T,
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_1}; // @[Cat.scala 33:92]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_isSubnormal = $signed(
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sExp_T) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormShiftDist_T =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sExp_T[5:0]; // @[fNFromRecFN.scala 51:51]
  wire [5:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_denormShiftDist = 6'h1 -
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormShiftDist_T; // @[fNFromRecFN.scala 51:39]
  wire [52:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_T =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_2[53:1]; // @[fNFromRecFN.scala 52:38]
  wire [52:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_T_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_T >>
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [51:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_denormFract =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sExp_T[10:0]; // @[fNFromRecFN.scala 57:27]
  wire [10:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_2 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_3 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_isSubnormal ? 11'h0 :
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_4 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T_1 |
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_2; // @[fNFromRecFN.scala 59:44]
  wire [10:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_6 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_4 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_expOut =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_3 |
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [51:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_T =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_2[51:0]; // @[fNFromRecFN.scala 63:52]
  wire [51:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_T_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_2 ? 52'h0 :
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_T; // @[fNFromRecFN.scala 63:20]
  wire [51:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_fractOut =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_isSubnormal ?
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_denormFract :
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [63:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded = {
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sign_T,
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_expOut,iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_fractOut}; // @[Cat.scala 33:92]
  wire [1:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial_T =
    iss_stage_lsuIssInfo_res_param_dat_op2_expIn[8:7]; // @[rawFloatFromRecFN.scala 52:29]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial_T == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T =
    iss_stage_lsuIssInfo_res_param_dat_op2_expIn[6]; // @[rawFloatFromRecFN.scala 55:41]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T_1 =
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial &
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala 55:33]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_1 = ~
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala 56:36]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_2 =
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial &
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sExp_T = {1'b0,$signed(
    iss_stage_lsuIssInfo_res_param_dat_op2_expIn)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T = ~
    iss_stage__lsuIssInfo_res_param_dat_op2_expOut_T; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T_2 = {1'h0,
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T,iss_stage_lsuIssInfo_res_param_dat_op2_fractIn
    }; // @[Cat.scala 33:92]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_isSubnormal = $signed(
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sExp_T) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormShiftDist_T =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sExp_T[4:0]; // @[fNFromRecFN.scala 51:51]
  wire [4:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormShiftDist = 5'h1 -
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormShiftDist_T; // @[fNFromRecFN.scala 51:39]
  wire [23:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_T =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T_2[24:1]; // @[fNFromRecFN.scala 52:38]
  wire [23:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_T_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_T >>
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala 52:42]
  wire [22:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sExp_T[7:0]; // @[fNFromRecFN.scala 57:27]
  wire [7:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_2 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_3 =
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_isSubnormal ? 8'h0 :
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala 55:16]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_4 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T_1 |
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_2; // @[fNFromRecFN.scala 59:44]
  wire [7:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_6 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_3 |
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_6; // @[fNFromRecFN.scala 59:15]
  wire [22:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_T =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T_2[22:0]; // @[fNFromRecFN.scala 63:52]
  wire [22:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_T_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_2 ? 23'h0 :
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_T; // @[fNFromRecFN.scala 63:20]
  wire [22:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut =
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_isSubnormal ?
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract :
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala 61:16]
  wire [31:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded = {iss_stage_lsuIssInfo_res_param_dat_op2_sign,
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut,
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut}; // @[Cat.scala 33:92]
  wire [31:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_8 = iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded[63:32]; // @[Fpu.scala 243:21]
  wire [2:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_9 = iss_stage__postBufOperator_0_1_T_8[63:61]; // @[Fpu.scala 34:25]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_T_10 = &iss_stage__lsuIssInfo_res_param_dat_op2_T_9; // @[Fpu.scala 34:56]
  wire [31:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_11 = iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded[31:0]; // @[Fpu.scala 243:81]
  wire [31:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_12 = iss_stage__lsuIssInfo_res_param_dat_op2_T_10 ?
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded : iss_stage__lsuIssInfo_res_param_dat_op2_T_11; // @[Fpu.scala 243:44]
  wire [63:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_13 = {iss_stage__lsuIssInfo_res_param_dat_op2_T_8,
    iss_stage__lsuIssInfo_res_param_dat_op2_T_12}; // @[Cat.scala 33:92]
  wire [64:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_14 = iss_stage__lsuIssInfo_res_param_dat_op2_T ? {{1'd0},
    iss_stage__lsuIssInfo_res_param_dat_op2_T_13} : iss_stage__postBufOperator_0_1_T_8; // @[Issue.scala 859:10]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_30 = iss_stage_bufInfo_1_lsu_isa_sc_d |
    iss_stage_bufInfo_1_lsu_isa_sc_w; // @[riscv_isa.scala 140:20]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_31 = iss_stage_bufInfo_1_lsu_isa_lr_d |
    iss_stage_bufInfo_1_lsu_isa_lr_w; // @[riscv_isa.scala 141:20]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_32 = iss_stage__lsuIssInfo_res_param_dat_op1_T_30 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_31; // @[riscv_isa.scala 146:23]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_33 = iss_stage_bufInfo_1_lsu_isa_amoswap_w |
    iss_stage_bufInfo_1_lsu_isa_amoadd_w; // @[riscv_isa.scala 148:15]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_34 = iss_stage__lsuIssInfo_res_param_dat_op1_T_33 |
    iss_stage_bufInfo_1_lsu_isa_amoxor_w; // @[riscv_isa.scala 148:26]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_35 = iss_stage__lsuIssInfo_res_param_dat_op1_T_34 |
    iss_stage_bufInfo_1_lsu_isa_amoand_w; // @[riscv_isa.scala 148:37]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_36 = iss_stage__lsuIssInfo_res_param_dat_op1_T_35 |
    iss_stage_bufInfo_1_lsu_isa_amoor_w; // @[riscv_isa.scala 148:48]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_37 = iss_stage__lsuIssInfo_res_param_dat_op1_T_36 |
    iss_stage_bufInfo_1_lsu_isa_amomin_w; // @[riscv_isa.scala 148:58]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_38 = iss_stage__lsuIssInfo_res_param_dat_op1_T_37 |
    iss_stage_bufInfo_1_lsu_isa_amomax_w; // @[riscv_isa.scala 148:69]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_39 = iss_stage__lsuIssInfo_res_param_dat_op1_T_38 |
    iss_stage_bufInfo_1_lsu_isa_amominu_w; // @[riscv_isa.scala 148:80]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_40 = iss_stage__lsuIssInfo_res_param_dat_op1_T_39 |
    iss_stage_bufInfo_1_lsu_isa_amomaxu_w; // @[riscv_isa.scala 148:92]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_41 = iss_stage__lsuIssInfo_res_param_dat_op1_T_40 |
    iss_stage_bufInfo_1_lsu_isa_amoswap_d; // @[riscv_isa.scala 148:104]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_42 = iss_stage__lsuIssInfo_res_param_dat_op1_T_41 |
    iss_stage_bufInfo_1_lsu_isa_amoadd_d; // @[riscv_isa.scala 148:116]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_43 = iss_stage__lsuIssInfo_res_param_dat_op1_T_42 |
    iss_stage_bufInfo_1_lsu_isa_amoxor_d; // @[riscv_isa.scala 148:127]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_44 = iss_stage__lsuIssInfo_res_param_dat_op1_T_43 |
    iss_stage_bufInfo_1_lsu_isa_amoand_d; // @[riscv_isa.scala 148:138]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_45 = iss_stage__lsuIssInfo_res_param_dat_op1_T_44 |
    iss_stage_bufInfo_1_lsu_isa_amoor_d; // @[riscv_isa.scala 148:149]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_46 = iss_stage__lsuIssInfo_res_param_dat_op1_T_45 |
    iss_stage_bufInfo_1_lsu_isa_amomin_d; // @[riscv_isa.scala 148:159]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_47 = iss_stage__lsuIssInfo_res_param_dat_op1_T_46 |
    iss_stage_bufInfo_1_lsu_isa_amomax_d; // @[riscv_isa.scala 148:170]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_48 = iss_stage__lsuIssInfo_res_param_dat_op1_T_47 |
    iss_stage_bufInfo_1_lsu_isa_amominu_d; // @[riscv_isa.scala 148:181]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_49 = iss_stage__lsuIssInfo_res_param_dat_op1_T_48 |
    iss_stage_bufInfo_1_lsu_isa_amomaxu_d; // @[riscv_isa.scala 148:193]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_51 = iss_stage__lsuIssInfo_res_param_dat_op1_T_49 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_30; // @[riscv_isa.scala 148:205]
  wire  iss_stage__lsuIssInfo_res_param_dat_op1_T_52 = iss_stage__lsuIssInfo_res_param_dat_op1_T_32 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_51; // @[Issue.scala 857:42]
  wire [64:0] iss_stage__lsuIssInfo_res_param_dat_op1_T_53 = iss_stage__canIOpReq_1_0_T_6 ? {{1'd0},
    iss_stage_io_irgRsp_0_bits_op} : iss_stage_bufOperator_1_0; // @[Issue.scala 857:125]
  wire [63:0] iss_stage__lsuIssInfo_res_param_dat_op1_T_54 = iss_stage_bufInfo_1_param_imm; // @[Issue.scala 857:163]
  wire [64:0] _GEN_256 = {{1{iss_stage__lsuIssInfo_res_param_dat_op1_T_54[63]}},
    iss_stage__lsuIssInfo_res_param_dat_op1_T_54}; // @[Issue.scala 857:132]
  wire [64:0] iss_stage__lsuIssInfo_res_param_dat_op1_T_58 = $signed(iss_stage__lsuIssInfo_res_param_dat_op1_T_53) +
    $signed(_GEN_256); // @[Issue.scala 857:173]
  wire [64:0] iss_stage__lsuIssInfo_res_param_dat_op1_T_59 = iss_stage__lsuIssInfo_res_param_dat_op1_T_52 ?
    iss_stage__postBufOperator_1_0_T_8 : iss_stage__lsuIssInfo_res_param_dat_op1_T_58; // @[Issue.scala 857:10]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_T_15 = iss_stage_bufInfo_1_lsu_isa_fsw | iss_stage_bufInfo_1_lsu_isa_fsd
    ; // @[riscv_isa.scala 164:20]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_3 = iss_stage__postBufOperator_1_1_T_8[31]; // @[Fpu.scala 143:14]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_4 = iss_stage__postBufOperator_1_1_T_8[52]; // @[Fpu.scala 144:14]
  wire [30:0] iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_5 = iss_stage__postBufOperator_1_1_T_8[30:0]; // @[Fpu.scala 145:14]
  wire [32:0] iss_stage_lsuIssInfo_res_param_dat_op2_unswizzled_1 = {
    iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_3,iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_4,
    iss_stage__lsuIssInfo_res_param_dat_op2_unswizzled_T_5}; // @[Cat.scala 33:92]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_sign_1 = iss_stage_lsuIssInfo_res_param_dat_op2_unswizzled_1[32]; // @[Fpu.scala 59:17]
  wire [22:0] iss_stage_lsuIssInfo_res_param_dat_op2_fractIn_1 = iss_stage_lsuIssInfo_res_param_dat_op2_unswizzled_1[22:
    0]; // @[Fpu.scala 60:20]
  wire [8:0] iss_stage_lsuIssInfo_res_param_dat_op2_expIn_1 = iss_stage_lsuIssInfo_res_param_dat_op2_unswizzled_1[31:23]
    ; // @[Fpu.scala 61:18]
  wire [2:0] iss_stage_lsuIssInfo_res_param_dat_op2_expOut_expCode_1 = iss_stage_lsuIssInfo_res_param_dat_op2_expIn_1[8:
    6]; // @[Fpu.scala 64:26]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_expOut_T_6 = iss_stage_lsuIssInfo_res_param_dat_op2_expOut_expCode_1 == 3'h0
    ; // @[Fpu.scala 66:19]
  wire [11:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp_1 = iss_stage__postBufOperator_1_1_T_8[63:52]; // @[rawFloatFromRecFN.scala 50:21]
  wire [2:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isZero_T_1 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala 51:29]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isZero_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
  wire [1:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial_T_1 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala 52:29]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial_T_1 == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T_2 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala 55:41]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T_3 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial_1 &
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala 55:33]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_4 = ~
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala 56:36]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_5 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isSpecial_1 &
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala 56:33]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sign_T_1 = iss_stage__postBufOperator_1_1_T_8[64]; // @[rawFloatFromRecFN.scala 58:25]
  wire [12:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sExp_T_1 = {1'b0,$signed(
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_exp_1)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_3 = ~
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala 60:39]
  wire [51:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_4 = iss_stage__postBufOperator_1_1_T_8[
    51:0]; // @[rawFloatFromRecFN.scala 60:51]
  wire [53:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_5 = {1'h0,
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_3,
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_4}; // @[Cat.scala 33:92]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_isSubnormal_1 = $signed(
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sExp_T_1) < 13'sh402; // @[fNFromRecFN.scala 50:39]
  wire [5:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormShiftDist_T_2 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sExp_T_1[5:0]; // @[fNFromRecFN.scala 51:51]
  wire [5:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_denormShiftDist_1 = 6'h1 -
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormShiftDist_T_2; // @[fNFromRecFN.scala 51:39]
  wire [52:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_T_2 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_5[53:1]; // @[fNFromRecFN.scala 52:38]
  wire [52:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_T_3 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_T_2 >>
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala 52:42]
  wire [51:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala 52:60]
  wire [10:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_7 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sExp_T_1[10:0]; // @[fNFromRecFN.scala 57:27]
  wire [10:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_9 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_7 - 11'h401; // @[fNFromRecFN.scala 57:45]
  wire [10:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_10 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_isSubnormal_1 ? 11'h0 :
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_9; // @[fNFromRecFN.scala 55:16]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_11 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isNaN_T_3 |
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_5; // @[fNFromRecFN.scala 59:44]
  wire [10:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_13 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_11 ? 11'h7ff : 11'h0; // @[Bitwise.scala 77:12]
  wire [10:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_expOut_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_10 |
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_expOut_T_13; // @[fNFromRecFN.scala 59:15]
  wire [51:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_T_2 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sig_T_5[51:0]; // @[fNFromRecFN.scala 63:52]
  wire [51:0] iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_T_3 =
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_isInf_T_5 ? 52'h0 :
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_T_2; // @[fNFromRecFN.scala 63:20]
  wire [51:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_1 =
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_isSubnormal_1 ?
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_denormFract_1 :
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala 61:16]
  wire [63:0] iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_1 = {
    iss_stage__lsuIssInfo_res_param_dat_op2_unrecoded_rawIn_out_sign_T_1,
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_expOut_1,
    iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_fractOut_1}; // @[Cat.scala 33:92]
  wire [1:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial_T_1 =
    iss_stage_lsuIssInfo_res_param_dat_op2_expIn_1[8:7]; // @[rawFloatFromRecFN.scala 52:29]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial_T_1 == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T_2 =
    iss_stage_lsuIssInfo_res_param_dat_op2_expIn_1[6]; // @[rawFloatFromRecFN.scala 55:41]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T_3 =
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial_1 &
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala 55:33]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_4 = ~
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala 56:36]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_5 =
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_isSpecial_1 &
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala 56:33]
  wire [9:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sExp_T_1 = {1'b0,$signed(
    iss_stage_lsuIssInfo_res_param_dat_op2_expIn_1)}; // @[rawFloatFromRecFN.scala 59:27]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T_3 = ~
    iss_stage__lsuIssInfo_res_param_dat_op2_expOut_T_6; // @[rawFloatFromRecFN.scala 60:39]
  wire [24:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0,
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T_3,
    iss_stage_lsuIssInfo_res_param_dat_op2_fractIn_1}; // @[Cat.scala 33:92]
  wire  iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_isSubnormal_1 = $signed(
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sExp_T_1) < 10'sh82; // @[fNFromRecFN.scala 50:39]
  wire [4:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormShiftDist_T_2 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sExp_T_1[4:0]; // @[fNFromRecFN.scala 51:51]
  wire [4:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormShiftDist_1 = 5'h1 -
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormShiftDist_T_2; // @[fNFromRecFN.scala 51:39]
  wire [23:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_T_2 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T_5[24:1]; // @[fNFromRecFN.scala 52:38]
  wire [23:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_T_3 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_T_2 >>
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala 52:42]
  wire [22:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala 52:60]
  wire [7:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_7 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sExp_T_1[7:0]; // @[fNFromRecFN.scala 57:27]
  wire [7:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_9 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_7 - 8'h81; // @[fNFromRecFN.scala 57:45]
  wire [7:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_10 =
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_isSubnormal_1 ? 8'h0 :
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_9; // @[fNFromRecFN.scala 55:16]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_11 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isNaN_T_3 |
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_5; // @[fNFromRecFN.scala 59:44]
  wire [7:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_13 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_11 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_1 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_10 |
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_T_13; // @[fNFromRecFN.scala 59:15]
  wire [22:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_T_2 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_sig_T_5[22:0]; // @[fNFromRecFN.scala 63:52]
  wire [22:0] iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_T_3 =
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_rawIn_out_isInf_T_5 ? 23'h0 :
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_T_2; // @[fNFromRecFN.scala 63:20]
  wire [22:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_1 =
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_isSubnormal_1 ?
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_denormFract_1 :
    iss_stage__lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala 61:16]
  wire [31:0] iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_1 = {iss_stage_lsuIssInfo_res_param_dat_op2_sign_1,
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_expOut_1,
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_fractOut_1}; // @[Cat.scala 33:92]
  wire [31:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_23 = iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_1[63:32]; // @[Fpu.scala 243:21]
  wire [2:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_24 = iss_stage__postBufOperator_1_1_T_8[63:61]; // @[Fpu.scala 34:25]
  wire  iss_stage__lsuIssInfo_res_param_dat_op2_T_25 = &iss_stage__lsuIssInfo_res_param_dat_op2_T_24; // @[Fpu.scala 34:56]
  wire [31:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_26 = iss_stage_lsuIssInfo_res_param_dat_op2_unrecoded_1[31:0]; // @[Fpu.scala 243:81]
  wire [31:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_27 = iss_stage__lsuIssInfo_res_param_dat_op2_T_25 ?
    iss_stage_lsuIssInfo_res_param_dat_op2_prevUnrecoded_1 : iss_stage__lsuIssInfo_res_param_dat_op2_T_26; // @[Fpu.scala 243:44]
  wire [63:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_28 = {iss_stage__lsuIssInfo_res_param_dat_op2_T_23,
    iss_stage__lsuIssInfo_res_param_dat_op2_T_27}; // @[Cat.scala 33:92]
  wire [64:0] iss_stage__lsuIssInfo_res_param_dat_op2_T_29 = iss_stage__lsuIssInfo_res_param_dat_op2_T_15 ? {{1'd0},
    iss_stage__lsuIssInfo_res_param_dat_op2_T_28} : iss_stage__postBufOperator_1_1_T_8; // @[Issue.scala 859:10]
  wire  iss_stage__maskCondLsuIss_0_T_1 = iss_stage_bufInfo_0_lsu_isa_lb | iss_stage_bufInfo_0_lsu_isa_lh; // @[riscv_isa.scala 145:19]
  wire  iss_stage__maskCondLsuIss_0_T_2 = iss_stage__maskCondLsuIss_0_T_1 | iss_stage_bufInfo_0_lsu_isa_lw; // @[riscv_isa.scala 145:24]
  wire  iss_stage__maskCondLsuIss_0_T_3 = iss_stage__maskCondLsuIss_0_T_2 | iss_stage_bufInfo_0_lsu_isa_ld; // @[riscv_isa.scala 145:29]
  wire  iss_stage__maskCondLsuIss_0_T_4 = iss_stage__maskCondLsuIss_0_T_3 | iss_stage_bufInfo_0_lsu_isa_lbu; // @[riscv_isa.scala 145:34]
  wire  iss_stage__maskCondLsuIss_0_T_5 = iss_stage__maskCondLsuIss_0_T_4 | iss_stage_bufInfo_0_lsu_isa_lhu; // @[riscv_isa.scala 145:40]
  wire  iss_stage__maskCondLsuIss_0_T_6 = iss_stage__maskCondLsuIss_0_T_5 | iss_stage_bufInfo_0_lsu_isa_lwu; // @[riscv_isa.scala 145:46]
  wire  iss_stage__maskCondLsuIss_0_T_7 = iss_stage__maskCondLsuIss_0_T_6 | iss_stage_bufInfo_0_lsu_isa_sb; // @[riscv_isa.scala 145:52]
  wire  iss_stage__maskCondLsuIss_0_T_8 = iss_stage__maskCondLsuIss_0_T_7 | iss_stage_bufInfo_0_lsu_isa_sh; // @[riscv_isa.scala 145:57]
  wire  iss_stage__maskCondLsuIss_0_T_9 = iss_stage__maskCondLsuIss_0_T_8 | iss_stage_bufInfo_0_lsu_isa_sw; // @[riscv_isa.scala 145:62]
  wire  iss_stage__maskCondLsuIss_0_T_10 = iss_stage__maskCondLsuIss_0_T_9 | iss_stage_bufInfo_0_lsu_isa_sd; // @[riscv_isa.scala 145:67]
  wire  iss_stage__maskCondLsuIss_0_T_14 = iss_stage__maskCondLsuIss_0_T_10 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_2; // @[riscv_isa.scala 151:23]
  wire  iss_stage__maskCondLsuIss_0_T_34 = iss_stage__maskCondLsuIss_0_T_14 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_21; // @[riscv_isa.scala 151:33]
  wire  iss_stage__maskCondLsuIss_0_T_35 = iss_stage_bufInfo_0_lsu_isa_flw | iss_stage_bufInfo_0_lsu_isa_fsw; // @[riscv_isa.scala 149:20]
  wire  iss_stage__maskCondLsuIss_0_T_36 = iss_stage__maskCondLsuIss_0_T_35 | iss_stage_bufInfo_0_lsu_isa_fld; // @[riscv_isa.scala 149:26]
  wire  iss_stage__maskCondLsuIss_0_T_37 = iss_stage__maskCondLsuIss_0_T_36 | iss_stage_bufInfo_0_lsu_isa_fsd; // @[riscv_isa.scala 149:32]
  wire  iss_stage__maskCondLsuIss_0_T_38 = iss_stage__maskCondLsuIss_0_T_34 | iss_stage__maskCondLsuIss_0_T_37; // @[riscv_isa.scala 151:42]
  wire  iss_stage__maskCondLsuIss_0_T_39 = iss_stage_bufInfo_0_lsu_isa_fence | iss_stage_bufInfo_0_lsu_isa_fence_i; // @[riscv_isa.scala 150:24]
  wire  iss_stage__maskCondLsuIss_0_T_40 = iss_stage__maskCondLsuIss_0_T_39 | iss_stage_bufInfo_0_lsu_isa_sfence_vma; // @[riscv_isa.scala 150:34]
  wire  iss_stage__maskCondLsuIss_0_T_41 = iss_stage__maskCondLsuIss_0_T_38 | iss_stage__maskCondLsuIss_0_T_40; // @[riscv_isa.scala 151:51]
  wire  iss_stage__maskCondLsuIss_0_T_42 = ~iss_stage__maskCondLsuIss_0_T_41; // @[Issue.scala 881:7]
  wire  iss_stage__maskCondLsuIss_0_T_43 = iss_stage__entrySel_T | iss_stage__maskCondLsuIss_0_T_42; // @[Issue.scala 880:20]
  wire  iss_stage__maskCondLsuIss_1_T_1 = iss_stage_bufInfo_1_lsu_isa_lb | iss_stage_bufInfo_1_lsu_isa_lh; // @[riscv_isa.scala 145:19]
  wire  iss_stage__maskCondLsuIss_1_T_2 = iss_stage__maskCondLsuIss_1_T_1 | iss_stage_bufInfo_1_lsu_isa_lw; // @[riscv_isa.scala 145:24]
  wire  iss_stage__maskCondLsuIss_1_T_3 = iss_stage__maskCondLsuIss_1_T_2 | iss_stage_bufInfo_1_lsu_isa_ld; // @[riscv_isa.scala 145:29]
  wire  iss_stage__maskCondLsuIss_1_T_4 = iss_stage__maskCondLsuIss_1_T_3 | iss_stage_bufInfo_1_lsu_isa_lbu; // @[riscv_isa.scala 145:34]
  wire  iss_stage__maskCondLsuIss_1_T_5 = iss_stage__maskCondLsuIss_1_T_4 | iss_stage_bufInfo_1_lsu_isa_lhu; // @[riscv_isa.scala 145:40]
  wire  iss_stage__maskCondLsuIss_1_T_6 = iss_stage__maskCondLsuIss_1_T_5 | iss_stage_bufInfo_1_lsu_isa_lwu; // @[riscv_isa.scala 145:46]
  wire  iss_stage__maskCondLsuIss_1_T_7 = iss_stage__maskCondLsuIss_1_T_6 | iss_stage_bufInfo_1_lsu_isa_sb; // @[riscv_isa.scala 145:52]
  wire  iss_stage__maskCondLsuIss_1_T_8 = iss_stage__maskCondLsuIss_1_T_7 | iss_stage_bufInfo_1_lsu_isa_sh; // @[riscv_isa.scala 145:57]
  wire  iss_stage__maskCondLsuIss_1_T_9 = iss_stage__maskCondLsuIss_1_T_8 | iss_stage_bufInfo_1_lsu_isa_sw; // @[riscv_isa.scala 145:62]
  wire  iss_stage__maskCondLsuIss_1_T_10 = iss_stage__maskCondLsuIss_1_T_9 | iss_stage_bufInfo_1_lsu_isa_sd; // @[riscv_isa.scala 145:67]
  wire  iss_stage__maskCondLsuIss_1_T_14 = iss_stage__maskCondLsuIss_1_T_10 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_32; // @[riscv_isa.scala 151:23]
  wire  iss_stage__maskCondLsuIss_1_T_34 = iss_stage__maskCondLsuIss_1_T_14 |
    iss_stage__lsuIssInfo_res_param_dat_op1_T_51; // @[riscv_isa.scala 151:33]
  wire  iss_stage__maskCondLsuIss_1_T_35 = iss_stage_bufInfo_1_lsu_isa_flw | iss_stage_bufInfo_1_lsu_isa_fsw; // @[riscv_isa.scala 149:20]
  wire  iss_stage__maskCondLsuIss_1_T_36 = iss_stage__maskCondLsuIss_1_T_35 | iss_stage_bufInfo_1_lsu_isa_fld; // @[riscv_isa.scala 149:26]
  wire  iss_stage__maskCondLsuIss_1_T_37 = iss_stage__maskCondLsuIss_1_T_36 | iss_stage_bufInfo_1_lsu_isa_fsd; // @[riscv_isa.scala 149:32]
  wire  iss_stage__maskCondLsuIss_1_T_38 = iss_stage__maskCondLsuIss_1_T_34 | iss_stage__maskCondLsuIss_1_T_37; // @[riscv_isa.scala 151:42]
  wire  iss_stage__maskCondLsuIss_1_T_39 = iss_stage_bufInfo_1_lsu_isa_fence | iss_stage_bufInfo_1_lsu_isa_fence_i; // @[riscv_isa.scala 150:24]
  wire  iss_stage__maskCondLsuIss_1_T_40 = iss_stage__maskCondLsuIss_1_T_39 | iss_stage_bufInfo_1_lsu_isa_sfence_vma; // @[riscv_isa.scala 150:34]
  wire  iss_stage__maskCondLsuIss_1_T_41 = iss_stage__maskCondLsuIss_1_T_38 | iss_stage__maskCondLsuIss_1_T_40; // @[riscv_isa.scala 151:51]
  wire  iss_stage__maskCondLsuIss_1_T_42 = ~iss_stage__maskCondLsuIss_1_T_41; // @[Issue.scala 881:7]
  wire  iss_stage__maskCondLsuIss_1_T_43 = iss_stage__io_dptReq_0_ready_T_1 | iss_stage__maskCondLsuIss_1_T_42; // @[Issue.scala 880:20]
  wire  iss_stage__matrixOut_0_0_T_27 = ~iss_stage__maskCondLsuIss_0_T_43; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_0_T_28 = iss_stage_ageMatrixW_0_0 & iss_stage__matrixOut_0_0_T_27; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_0_T_29 = iss_stage__matrixOut_0_0_T_28 | iss_stage__maskCondLsuIss_0_T_43; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_0_1_T_27 = ~iss_stage__maskCondLsuIss_1_T_43; // @[Issue.scala 200:46]
  wire  iss_stage__matrixOut_0_1_T_28 = iss_stage_ageMatrixW_0_1 & iss_stage__matrixOut_0_1_T_27; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_0_1_T_29 = iss_stage__matrixOut_0_1_T_28 | iss_stage__maskCondLsuIss_0_T_43; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_0_T_28 = iss_stage__ageMatrixR_1_0_T & iss_stage__matrixOut_0_0_T_27; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_0_T_29 = iss_stage__matrixOut_1_0_T_28 | iss_stage__maskCondLsuIss_1_T_43; // @[Issue.scala 200:60]
  wire  iss_stage__matrixOut_1_1_T_28 = iss_stage_ageMatrixW_1_1 & iss_stage__matrixOut_0_1_T_27; // @[Issue.scala 200:44]
  wire  iss_stage__matrixOut_1_1_T_29 = iss_stage__matrixOut_1_1_T_28 | iss_stage__maskCondLsuIss_1_T_43; // @[Issue.scala 200:60]
  wire  iss_stage__T_606 = iss_stage__matrixOut_0_0_T_29 & iss_stage__matrixOut_0_1_T_29; // @[Issue.scala 887:52]
  wire  iss_stage__T_610 = iss_stage__matrixOut_1_0_T_29 & iss_stage__matrixOut_1_1_T_29; // @[Issue.scala 887:52]
  wire  iss_stage__T_612 = iss_stage__T_606 & iss_stage__T_610; // @[Issue.scala 887:24]
  wire  iss_stage__T_613 = ~iss_stage__matrixOut_0_0_T_29; // @[Issue.scala 888:75]
  wire  iss_stage__T_614 = ~iss_stage__matrixOut_0_1_T_29; // @[Issue.scala 888:75]
  wire  iss_stage__T_616 = iss_stage__T_613 & iss_stage__T_614; // @[Issue.scala 888:58]
  wire  iss_stage__T_617 = ~iss_stage__matrixOut_1_0_T_29; // @[Issue.scala 888:75]
  wire  iss_stage__T_618 = ~iss_stage__matrixOut_1_1_T_29; // @[Issue.scala 888:75]
  wire  iss_stage__T_620 = iss_stage__T_617 & iss_stage__T_618; // @[Issue.scala 888:58]
  wire [1:0] iss_stage__T_621 = iss_stage__T_616 + iss_stage__T_620; // @[Bitwise.scala 51:90]
  wire  iss_stage__T_623 = iss_stage__T_621 == 2'h1; // @[Issue.scala 888:92]
  wire  iss_stage__T_624 = iss_stage__T_612 | iss_stage__T_623; // @[Issue.scala 887:86]
  wire  iss_stage__T_627 = ~iss_stage__T_624; // @[Issue.scala 886:9]
  wire  iss_stage__lsuIssIdx_T_8 = iss_stage__T_616 ? 1'h0 : 1'h1; // @[Issue.scala 891:39]
  wire  iss_stage__lsuIssFifo_io_enq_valid_T_4 = iss_stage__T_616 & iss_stage__postIsOpReady_0_0_T_8; // @[Issue.scala 894:93]
  wire  iss_stage__lsuIssFifo_io_enq_valid_T_5 = iss_stage__lsuIssFifo_io_enq_valid_T_4 &
    iss_stage__postIsOpReady_0_1_T_8; // @[Issue.scala 894:115]
  wire  iss_stage__lsuIssFifo_io_enq_valid_T_10 = iss_stage__T_620 & iss_stage__postIsOpReady_1_0_T_8; // @[Issue.scala 894:93]
  wire  iss_stage__lsuIssFifo_io_enq_valid_T_11 = iss_stage__lsuIssFifo_io_enq_valid_T_10 &
    iss_stage__postIsOpReady_1_1_T_8; // @[Issue.scala 894:115]
  wire [63:0] iss_stage_lsuIssInfo_0_param_dat_op2 = iss_stage__lsuIssInfo_res_param_dat_op2_T_14[63:0]; // @[Issue.scala 852:19 858:23]
  wire [63:0] iss_stage__lsuIssFifo_io_enq_bits_T_15 = iss_stage__lsuIssFifo_io_enq_valid_T_5 ?
    iss_stage_lsuIssInfo_0_param_dat_op2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_lsuIssInfo_1_param_dat_op2 = iss_stage__lsuIssInfo_res_param_dat_op2_T_29[63:0]; // @[Issue.scala 852:19 858:23]
  wire [63:0] iss_stage__lsuIssFifo_io_enq_bits_T_16 = iss_stage__lsuIssFifo_io_enq_valid_T_11 ?
    iss_stage_lsuIssInfo_1_param_dat_op2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_lsuIssInfo_0_param_dat_op1 = iss_stage__lsuIssInfo_res_param_dat_op1_T_29[63:0]; // @[Issue.scala 852:19 856:23]
  wire [63:0] iss_stage__lsuIssFifo_io_enq_bits_T_18 = iss_stage__lsuIssFifo_io_enq_valid_T_5 ?
    iss_stage_lsuIssInfo_0_param_dat_op1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] iss_stage_lsuIssInfo_1_param_dat_op1 = iss_stage__lsuIssInfo_res_param_dat_op1_T_59[63:0]; // @[Issue.scala 852:19 856:23]
  wire [63:0] iss_stage__lsuIssFifo_io_enq_bits_T_19 = iss_stage__lsuIssFifo_io_enq_valid_T_11 ?
    iss_stage_lsuIssInfo_1_param_dat_op1 : 64'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__lsuIssFifo_io_enq_bits_T_21 = iss_stage__lsuIssFifo_io_enq_valid_T_5 ?
    iss_stage_bufInfo_0_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] iss_stage__lsuIssFifo_io_enq_bits_T_22 = iss_stage__lsuIssFifo_io_enq_valid_T_11 ?
    iss_stage_bufInfo_1_phy_rd0 : 6'h0; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_24 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_fsd; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_25 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_fsd; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_27 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_fld; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_28 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_fld; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_30 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_fsw; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_31 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_fsw; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_33 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_flw; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_34 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_flw; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_36 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amomaxu_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_37 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amomaxu_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_39 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amominu_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_40 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amominu_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_42 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amomax_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_43 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amomax_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_45 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amomin_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_46 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amomin_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_48 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoor_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_49 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoor_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_51 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoand_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_52 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoand_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_54 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoxor_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_55 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoxor_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_57 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoadd_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_58 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoadd_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_60 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoswap_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_61 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoswap_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_63 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_sc_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_64 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_sc_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_66 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_lr_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_67 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_lr_d; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_69 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amomaxu_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_70 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amomaxu_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_72 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amominu_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_73 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amominu_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_75 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amomax_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_76 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amomax_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_78 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amomin_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_79 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amomin_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_81 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoor_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_82 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoor_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_84 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoand_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_85 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoand_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_87 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoxor_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_88 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoxor_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_90 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoadd_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_91 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoadd_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_93 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_amoswap_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_94 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_amoswap_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_96 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_sc_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_97 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_sc_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_99 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_lr_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_100 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_lr_w; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_102 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_sfence_vma; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_103 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_sfence_vma; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_105 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_fence_i; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_106 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_fence_i; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_108 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_fence; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_109 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_fence; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_111 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_sd; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_112 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_sd; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_114 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_sw; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_115 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_sw; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_117 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_sh; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_118 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_sh; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_120 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_sb; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_121 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_sb; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_123 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_lwu; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_124 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_lwu; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_126 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_lhu; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_127 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_lhu; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_129 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_lbu; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_130 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_lbu; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_132 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_ld; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_133 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_ld; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_135 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_lw; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_136 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_lw; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_138 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_lh; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_139 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_lh; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_141 = iss_stage__lsuIssFifo_io_enq_valid_T_5 &
    iss_stage_bufInfo_0_lsu_isa_lb; // @[Mux.scala 27:73]
  wire  iss_stage__lsuIssFifo_io_enq_bits_T_142 = iss_stage__lsuIssFifo_io_enq_valid_T_11 &
    iss_stage_bufInfo_1_lsu_isa_lb; // @[Mux.scala 27:73]
  wire  iss_stage__T_629 = ~iss_stage__lsuIssIdx_T_8; // @[Issue.scala 900:46]
  wire  iss_stage__T_630 = iss_stage_lsuIssFifo__do_enq_T & iss_stage__T_629; // @[Issue.scala 900:34]
  wire  iss_stage__T_684 = iss_stage_lsuIssFifo__do_enq_T & iss_stage__lsuIssIdx_T_8; // @[Issue.scala 900:34]
  wire  _GEN_258 = iss_stage__T_318 & iss_stage__T_53; // @[Issue.scala 642:15]
  wire  _GEN_261 = iss_stage__T_361 & iss_stage__T_53; // @[Issue.scala 642:15]
  wire  _GEN_264 = iss_stage__T_429 & iss_stage__T_53; // @[Issue.scala 707:17]
  wire  _GEN_267 = iss_stage__T_454 & iss_stage__T_53; // @[Issue.scala 707:17]
  wire  _GEN_270 = iss_stage__T_504 & iss_stage__T_53; // @[Issue.scala 773:13]
  wire  _GEN_273 = iss_stage__T_524 & iss_stage__T_53; // @[Issue.scala 773:13]
  wire  _GEN_276 = iss_stage__T_569 & iss_stage__T_53; // @[Issue.scala 839:13]
  wire  _GEN_279 = iss_stage__T_587 & iss_stage__T_53; // @[Issue.scala 839:13]
  wire  _GEN_282 = iss_stage__T_630 & iss_stage__T_53; // @[Issue.scala 902:13]
  wire  _GEN_285 = iss_stage__T_684 & iss_stage__T_53; // @[Issue.scala 902:13]
  wire  exe_stage_clock;
  wire  exe_stage_reset;
  wire  exe_stage_io_alu_iss_exe_0_ready;
  wire  exe_stage_io_alu_iss_exe_0_valid;
  wire  exe_stage_io_alu_iss_exe_0_bits_fun_add;
  wire  exe_stage_io_alu_iss_exe_0_bits_fun_slt;
  wire  exe_stage_io_alu_iss_exe_0_bits_fun_xor;
  wire  exe_stage_io_alu_iss_exe_0_bits_fun_or;
  wire  exe_stage_io_alu_iss_exe_0_bits_fun_and;
  wire  exe_stage_io_alu_iss_exe_0_bits_fun_sll;
  wire  exe_stage_io_alu_iss_exe_0_bits_fun_srl;
  wire  exe_stage_io_alu_iss_exe_0_bits_fun_sra;
  wire [5:0] exe_stage_io_alu_iss_exe_0_bits_param_rd0;
  wire  exe_stage_io_alu_iss_exe_0_bits_param_is_32w;
  wire  exe_stage_io_alu_iss_exe_0_bits_param_is_usi;
  wire [63:0] exe_stage_io_alu_iss_exe_0_bits_param_dat_op1;
  wire [63:0] exe_stage_io_alu_iss_exe_0_bits_param_dat_op2;
  wire  exe_stage_io_alu_exe_iwb_0_ready;
  wire  exe_stage_io_alu_exe_iwb_0_valid;
  wire [5:0] exe_stage_io_alu_exe_iwb_0_bits_rd0;
  wire [63:0] exe_stage_io_alu_exe_iwb_0_bits_res;
  wire  exe_stage_io_bru_iss_exe_ready;
  wire  exe_stage_io_bru_iss_exe_valid;
  wire  exe_stage_io_bru_iss_exe_bits_fun_jalr;
  wire  exe_stage_io_bru_iss_exe_bits_fun_beq;
  wire  exe_stage_io_bru_iss_exe_bits_fun_bne;
  wire  exe_stage_io_bru_iss_exe_bits_fun_blt;
  wire  exe_stage_io_bru_iss_exe_bits_fun_bge;
  wire  exe_stage_io_bru_iss_exe_bits_fun_bltu;
  wire  exe_stage_io_bru_iss_exe_bits_fun_bgeu;
  wire [5:0] exe_stage_io_bru_iss_exe_bits_param_rd0;
  wire  exe_stage_io_bru_iss_exe_bits_param_is_rvc;
  wire [63:0] exe_stage_io_bru_iss_exe_bits_param_pc;
  wire [63:0] exe_stage_io_bru_iss_exe_bits_param_imm;
  wire [63:0] exe_stage_io_bru_iss_exe_bits_param_dat_op1;
  wire [63:0] exe_stage_io_bru_iss_exe_bits_param_dat_op2;
  wire  exe_stage_io_bru_exe_iwb_ready;
  wire  exe_stage_io_bru_exe_iwb_valid;
  wire [5:0] exe_stage_io_bru_exe_iwb_bits_rd0;
  wire [63:0] exe_stage_io_bru_exe_iwb_bits_res;
  wire  exe_stage_io_csr_iss_exe_ready;
  wire  exe_stage_io_csr_iss_exe_valid;
  wire  exe_stage_io_csr_iss_exe_bits_fun_rw;
  wire  exe_stage_io_csr_iss_exe_bits_fun_rs;
  wire  exe_stage_io_csr_iss_exe_bits_fun_rc;
  wire [5:0] exe_stage_io_csr_iss_exe_bits_param_rd0;
  wire [63:0] exe_stage_io_csr_iss_exe_bits_param_dat_op1;
  wire [63:0] exe_stage_io_csr_iss_exe_bits_param_dat_op2;
  wire  exe_stage_io_csr_exe_iwb_ready;
  wire  exe_stage_io_csr_exe_iwb_valid;
  wire [5:0] exe_stage_io_csr_exe_iwb_bits_rd0;
  wire [63:0] exe_stage_io_csr_exe_iwb_bits_res;
  wire  exe_stage_io_lsu_iss_exe_ready;
  wire  exe_stage_io_lsu_iss_exe_valid;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_lb;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_lh;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_lw;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_ld;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_lbu;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_lhu;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_lwu;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_sb;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_sh;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_sw;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_sd;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_fence;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_fence_i;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_sfence_vma;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_lr_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_sc_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoswap_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoadd_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoxor_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoand_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoor_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amomin_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amomax_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amominu_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amomaxu_w;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_lr_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_sc_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoswap_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoadd_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoxor_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoand_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amoor_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amomin_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amomax_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amominu_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_amomaxu_d;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_flw;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_fsw;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_fld;
  wire  exe_stage_io_lsu_iss_exe_bits_fun_fsd;
  wire [5:0] exe_stage_io_lsu_iss_exe_bits_param_rd0;
  wire [63:0] exe_stage_io_lsu_iss_exe_bits_param_dat_op1;
  wire [63:0] exe_stage_io_lsu_iss_exe_bits_param_dat_op2;
  wire  exe_stage_io_lsu_exe_iwb_ready;
  wire  exe_stage_io_lsu_exe_iwb_valid;
  wire [5:0] exe_stage_io_lsu_exe_iwb_bits_rd0;
  wire [63:0] exe_stage_io_lsu_exe_iwb_bits_res;
  wire  exe_stage_io_lsu_exe_fwb_ready;
  wire  exe_stage_io_lsu_exe_fwb_valid;
  wire  exe_stage_io_mul_iss_exe_0_ready;
  wire  exe_stage_io_mul_iss_exe_0_valid;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_mul;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_mulh;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_mulhsu;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_mulhu;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_div;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_divu;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_rem;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_remu;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_mulw;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_divw;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_divuw;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_remw;
  wire  exe_stage_io_mul_iss_exe_0_bits_fun_remuw;
  wire [5:0] exe_stage_io_mul_iss_exe_0_bits_param_rd0;
  wire [63:0] exe_stage_io_mul_iss_exe_0_bits_param_dat_op1;
  wire [63:0] exe_stage_io_mul_iss_exe_0_bits_param_dat_op2;
  wire  exe_stage_io_mul_exe_iwb_0_ready;
  wire  exe_stage_io_mul_exe_iwb_0_valid;
  wire [5:0] exe_stage_io_mul_exe_iwb_0_bits_rd0;
  wire [63:0] exe_stage_io_mul_exe_iwb_0_bits_res;
  wire  exe_stage_io_fpu_iss_exe_0_valid;
  wire  exe_stage_io_fpu_exe_iwb_0_valid;
  wire [5:0] exe_stage_io_fpu_exe_iwb_0_bits_rd0;
  wire [63:0] exe_stage_io_fpu_exe_iwb_0_bits_res;
  wire  exe_stage_io_fpu_exe_fwb_0_valid;
  wire  exe_stage_io_fcsr_cmm_op_0_valid;
  wire [11:0] exe_stage_io_fcsr_cmm_op_0_bits_addr;
  wire [63:0] exe_stage_io_fcsr_cmm_op_0_bits_dat_i;
  wire  exe_stage_io_fcsr_cmm_op_0_bits_op_rw;
  wire  exe_stage_io_fcsr_cmm_op_0_bits_op_rs;
  wire  exe_stage_io_fcsr_cmm_op_0_bits_op_rc;
  wire  exe_stage_io_bftq_ready;
  wire  exe_stage_io_bftq_valid;
  wire [38:0] exe_stage_io_bftq_bits_pc;
  wire  exe_stage_io_bftq_bits_bimResp_bim_p;
  wire  exe_stage_io_bftq_bits_bimResp_bim_h;
  wire  exe_stage_io_bftq_bits_isPredictTaken;
  wire  exe_stage_io_jftq_ready;
  wire  exe_stage_io_jftq_valid;
  wire [38:0] exe_stage_io_jftq_bits_pc;
  wire [38:0] exe_stage_io_jftq_bits_btbResp_target;
  wire [38:0] exe_stage_io_jftq_bits_rasResp_target;
  wire  exe_stage_io_jftq_bits_isRas;
  wire  exe_stage_io_bctq_ready;
  wire  exe_stage_io_bctq_valid;
  wire  exe_stage_io_bctq_bits_isPredictTaken;
  wire  exe_stage_io_bctq_bits_isFinalTaken;
  wire [63:0] exe_stage_io_bctq_bits_finalTarget;
  wire  exe_stage_io_jctq_ready;
  wire  exe_stage_io_jctq_valid;
  wire [38:0] exe_stage_io_jctq_bits_btbResp_target;
  wire [38:0] exe_stage_io_jctq_bits_rasResp_target;
  wire  exe_stage_io_jctq_bits_isRas;
  wire [63:0] exe_stage_io_jctq_bits_finalTarget;
  wire  exe_stage_io_bcmm_update_valid;
  wire [38:0] exe_stage_io_bcmm_update_bits_pc;
  wire  exe_stage_io_bcmm_update_bits_bimResp_bim_p;
  wire  exe_stage_io_bcmm_update_bits_bimResp_bim_h;
  wire  exe_stage_io_bcmm_update_bits_isFinalTaken;
  wire  exe_stage_io_jcmm_update_valid;
  wire [38:0] exe_stage_io_jcmm_update_bits_pc;
  wire [63:0] exe_stage_io_jcmm_update_bits_finalTarget;
  wire  exe_stage_io_csr_addr_valid;
  wire [11:0] exe_stage_io_csr_addr_bits;
  wire  exe_stage_io_csr_data_valid;
  wire [63:0] exe_stage_io_csr_data_bits;
  wire  exe_stage_io_csr_cmm_op_ready;
  wire  exe_stage_io_csr_cmm_op_valid;
  wire [11:0] exe_stage_io_csr_cmm_op_bits_addr;
  wire [63:0] exe_stage_io_csr_cmm_op_bits_dat_i;
  wire  exe_stage_io_csr_cmm_op_bits_op_rw;
  wire  exe_stage_io_csr_cmm_op_bits_op_rs;
  wire  exe_stage_io_csr_cmm_op_bits_op_rc;
  wire  exe_stage_io_lsu_mmu_ready;
  wire  exe_stage_io_lsu_mmu_valid;
  wire  exe_stage_io_lsu_mmu_bits_is_X;
  wire  exe_stage_io_lsu_mmu_bits_is_W;
  wire  exe_stage_io_lsu_mmu_bits_is_R;
  wire [63:0] exe_stage_io_lsu_mmu_bits_vaddr;
  wire  exe_stage_io_mmu_lsu_ready;
  wire  exe_stage_io_mmu_lsu_valid;
  wire [63:0] exe_stage_io_mmu_lsu_bits_paddr;
  wire  exe_stage_io_mmu_lsu_bits_is_paging_fault;
  wire  exe_stage_io_mmu_lsu_bits_is_access_fault;
  wire  exe_stage_io_cmm_lsu_is_amo_pending;
  wire  exe_stage_io_cmm_lsu_is_store_commit_0;
  wire  exe_stage_io_lsu_cmm_is_access_fault;
  wire  exe_stage_io_lsu_cmm_is_paging_fault;
  wire  exe_stage_io_lsu_cmm_is_misAlign;
  wire [63:0] exe_stage_io_lsu_cmm_trap_addr;
  wire  exe_stage_io_missUnit_dcache_acquire_ready;
  wire  exe_stage_io_missUnit_dcache_acquire_valid;
  wire [2:0] exe_stage_io_missUnit_dcache_acquire_bits_opcode;
  wire [2:0] exe_stage_io_missUnit_dcache_acquire_bits_param;
  wire [2:0] exe_stage_io_missUnit_dcache_acquire_bits_size;
  wire  exe_stage_io_missUnit_dcache_acquire_bits_source;
  wire [31:0] exe_stage_io_missUnit_dcache_acquire_bits_address;
  wire [7:0] exe_stage_io_missUnit_dcache_acquire_bits_mask;
  wire [63:0] exe_stage_io_missUnit_dcache_acquire_bits_data;
  wire  exe_stage_io_missUnit_dcache_acquire_bits_corrupt;
  wire  exe_stage_io_missUnit_dcache_grant_ready;
  wire  exe_stage_io_missUnit_dcache_grant_valid;
  wire [2:0] exe_stage_io_missUnit_dcache_grant_bits_opcode;
  wire [2:0] exe_stage_io_missUnit_dcache_grant_bits_size;
  wire  exe_stage_io_missUnit_dcache_grant_bits_source;
  wire [4:0] exe_stage_io_missUnit_dcache_grant_bits_sink;
  wire [63:0] exe_stage_io_missUnit_dcache_grant_bits_data;
  wire  exe_stage_io_missUnit_dcache_grantAck_ready;
  wire  exe_stage_io_missUnit_dcache_grantAck_valid;
  wire [4:0] exe_stage_io_missUnit_dcache_grantAck_bits_sink;
  wire  exe_stage_io_probeUnit_dcache_probe_ready;
  wire  exe_stage_io_probeUnit_dcache_probe_valid;
  wire [31:0] exe_stage_io_probeUnit_dcache_probe_bits_address;
  wire  exe_stage_io_writeBackUnit_dcache_release_ready;
  wire  exe_stage_io_writeBackUnit_dcache_release_valid;
  wire [2:0] exe_stage_io_writeBackUnit_dcache_release_bits_opcode;
  wire [2:0] exe_stage_io_writeBackUnit_dcache_release_bits_param;
  wire [2:0] exe_stage_io_writeBackUnit_dcache_release_bits_size;
  wire  exe_stage_io_writeBackUnit_dcache_release_bits_source;
  wire [31:0] exe_stage_io_writeBackUnit_dcache_release_bits_address;
  wire [63:0] exe_stage_io_writeBackUnit_dcache_release_bits_data;
  wire  exe_stage_io_writeBackUnit_dcache_release_bits_corrupt;
  wire  exe_stage_io_writeBackUnit_dcache_grant_ready;
  wire  exe_stage_io_writeBackUnit_dcache_grant_valid;
  wire  exe_stage_io_writeBackUnit_dcache_grant_bits_source;
  wire  exe_stage_io_system_getPut_ready;
  wire  exe_stage_io_system_getPut_valid;
  wire [2:0] exe_stage_io_system_getPut_bits_opcode;
  wire [2:0] exe_stage_io_system_getPut_bits_param;
  wire [1:0] exe_stage_io_system_getPut_bits_size;
  wire  exe_stage_io_system_getPut_bits_source;
  wire [31:0] exe_stage_io_system_getPut_bits_address;
  wire [7:0] exe_stage_io_system_getPut_bits_mask;
  wire [63:0] exe_stage_io_system_getPut_bits_data;
  wire  exe_stage_io_system_getPut_bits_corrupt;
  wire  exe_stage_io_system_access_ready;
  wire  exe_stage_io_system_access_valid;
  wire [2:0] exe_stage_io_system_access_bits_opcode;
  wire [63:0] exe_stage_io_system_access_bits_data;
  wire  exe_stage_io_periph_getPut_ready;
  wire  exe_stage_io_periph_getPut_valid;
  wire [2:0] exe_stage_io_periph_getPut_bits_opcode;
  wire [2:0] exe_stage_io_periph_getPut_bits_param;
  wire [1:0] exe_stage_io_periph_getPut_bits_size;
  wire  exe_stage_io_periph_getPut_bits_source;
  wire [31:0] exe_stage_io_periph_getPut_bits_address;
  wire [7:0] exe_stage_io_periph_getPut_bits_mask;
  wire [63:0] exe_stage_io_periph_getPut_bits_data;
  wire  exe_stage_io_periph_getPut_bits_corrupt;
  wire  exe_stage_io_periph_access_ready;
  wire  exe_stage_io_periph_access_valid;
  wire [2:0] exe_stage_io_periph_access_bits_opcode;
  wire [63:0] exe_stage_io_periph_access_bits_data;
  wire  exe_stage_io_flush;
  wire  exe_stage_alu_0_clock;
  wire  exe_stage_alu_0_reset;
  wire  exe_stage_alu_0_io_alu_iss_exe_ready;
  wire  exe_stage_alu_0_io_alu_iss_exe_valid;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_fun_add;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_fun_slt;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_fun_xor;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_fun_or;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_fun_and;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_fun_sll;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_fun_srl;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_fun_sra;
  wire [5:0] exe_stage_alu_0_io_alu_iss_exe_bits_param_rd0;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_param_is_32w;
  wire  exe_stage_alu_0_io_alu_iss_exe_bits_param_is_usi;
  wire [63:0] exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1;
  wire [63:0] exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2;
  wire  exe_stage_alu_0_io_alu_exe_iwb_ready;
  wire  exe_stage_alu_0_io_alu_exe_iwb_valid;
  wire [5:0] exe_stage_alu_0_io_alu_exe_iwb_bits_rd0;
  wire [63:0] exe_stage_alu_0_io_alu_exe_iwb_bits_res;
  wire  exe_stage_alu_0_io_flush;
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_clock;
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_reset;
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_ready;
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_valid;
  wire [5:0] exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_bits_rd0;
  wire [63:0] exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_bits_res;
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_ready;
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_valid;
  wire [5:0] exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_bits_rd0;
  wire [63:0] exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_bits_res;
  reg [5:0] exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_clock;
  reg [63:0] exe_stage_alu_0_alu_exe_iwb_fifo_ram_res [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_clock;
  reg  exe_stage_alu_0_alu_exe_iwb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo__empty_T = ~exe_stage_alu_0_alu_exe_iwb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo__do_enq_T = exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_ready &
    exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo__do_deq_T = exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_ready &
    exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_alu_0_alu_exe_iwb_fifo__T = exe_stage_alu_0_alu_exe_iwb_fifo__do_enq_T !=
    exe_stage_alu_0_alu_exe_iwb_fifo__do_deq_T; // @[Decoupled.scala 295:15]
  wire [63:0] exe_stage_alu_0_adder_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1 +
    exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2; // @[Alu.scala 52:23]
  wire  exe_stage_alu_0__adder_res_32w_T = exe_stage_alu_0_adder_res[31]; // @[Alu.scala 49:43]
  wire [31:0] exe_stage_alu_0__adder_res_32w_T_2 = exe_stage_alu_0__adder_res_32w_T ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [31:0] exe_stage_alu_0__adder_res_32w_T_3 = exe_stage_alu_0_adder_res[31:0]; // @[Alu.scala 49:53]
  wire [63:0] exe_stage_alu_0_adder_res_32w = {exe_stage_alu_0__adder_res_32w_T_2,exe_stage_alu_0__adder_res_32w_T_3}; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_alu_0_alu_add_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_is_32w ?
    exe_stage_alu_0_adder_res_32w : exe_stage_alu_0_adder_res; // @[Alu.scala 54:24]
  wire  exe_stage_alu_0__slt_sign_res_T_2 = $signed(exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1) < $signed(
    exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2); // @[Alu.scala 56:38]
  wire  exe_stage_alu_0__slt_unsi_res_T = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1 <
    exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2; // @[Alu.scala 57:31]
  wire  exe_stage_alu_0_alu_slt_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_is_usi ? exe_stage_alu_0__slt_unsi_res_T
     : exe_stage_alu_0__slt_sign_res_T_2; // @[Alu.scala 59:24]
  wire [63:0] exe_stage_alu_0_alu_xor_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1 ^
    exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2; // @[Alu.scala 61:25]
  wire [63:0] exe_stage_alu_0_alu_or_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1 |
    exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2; // @[Alu.scala 62:25]
  wire [63:0] exe_stage_alu_0_alu_and_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1 &
    exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2; // @[Alu.scala 63:25]
  wire [4:0] exe_stage_alu_0__shift_op2_T = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2[4:0]; // @[Alu.scala 67:34]
  wire [5:0] exe_stage_alu_0__shift_op2_T_1 = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2[5:0]; // @[Alu.scala 67:44]
  wire [5:0] exe_stage_alu_0_shift_op2 = exe_stage_alu_0_io_alu_iss_exe_bits_param_is_32w ? {{1'd0},
    exe_stage_alu_0__shift_op2_T} : exe_stage_alu_0__shift_op2_T_1; // @[Alu.scala 67:22]
  wire [126:0] _GEN_755 = {{63'd0}, exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1}; // @[Alu.scala 69:48]
  wire [126:0] exe_stage_alu_0__alu_sll_res_T = _GEN_755 << exe_stage_alu_0_shift_op2; // @[Alu.scala 69:48]
  wire  exe_stage_alu_0__alu_sll_res_T_1 = exe_stage_alu_0__alu_sll_res_T[31]; // @[Alu.scala 49:43]
  wire [31:0] exe_stage_alu_0__alu_sll_res_T_3 = exe_stage_alu_0__alu_sll_res_T_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [31:0] exe_stage_alu_0__alu_sll_res_T_4 = exe_stage_alu_0__alu_sll_res_T[31:0]; // @[Alu.scala 49:53]
  wire [63:0] exe_stage_alu_0__alu_sll_res_T_5 = {exe_stage_alu_0__alu_sll_res_T_3,exe_stage_alu_0__alu_sll_res_T_4}; // @[Cat.scala 33:92]
  wire [126:0] exe_stage_alu_0_alu_sll_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_is_32w ? {{63'd0},
    exe_stage_alu_0__alu_sll_res_T_5} : exe_stage_alu_0__alu_sll_res_T; // @[Alu.scala 69:25]
  wire [31:0] exe_stage_alu_0__alu_srl_res_T = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1[31:0]; // @[Alu.scala 71:46]
  wire [31:0] exe_stage_alu_0__alu_srl_res_T_1 = exe_stage_alu_0__alu_srl_res_T >> exe_stage_alu_0_shift_op2; // @[Alu.scala 71:53]
  wire  exe_stage_alu_0__alu_srl_res_T_2 = exe_stage_alu_0__alu_srl_res_T_1[31]; // @[Alu.scala 49:43]
  wire [31:0] exe_stage_alu_0__alu_srl_res_T_4 = exe_stage_alu_0__alu_srl_res_T_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [63:0] exe_stage_alu_0__alu_srl_res_T_6 = {exe_stage_alu_0__alu_srl_res_T_4,exe_stage_alu_0__alu_srl_res_T_1}; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_alu_0__alu_srl_res_T_7 = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1 >>
    exe_stage_alu_0_shift_op2; // @[Alu.scala 71:72]
  wire [63:0] exe_stage_alu_0_alu_srl_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_is_32w ?
    exe_stage_alu_0__alu_srl_res_T_6 : exe_stage_alu_0__alu_srl_res_T_7; // @[Alu.scala 71:25]
  wire  exe_stage_alu_0__sra_op1_128w_T = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1[31]; // @[Alu.scala 73:52]
  wire [95:0] exe_stage_alu_0__sra_op1_128w_T_2 = exe_stage_alu_0__sra_op1_128w_T ? 96'hffffffffffffffffffffffff : 96'h0
    ; // @[Bitwise.scala 77:12]
  wire [127:0] exe_stage_alu_0__sra_op1_128w_T_4 = {exe_stage_alu_0__sra_op1_128w_T_2,exe_stage_alu_0__alu_srl_res_T}; // @[Cat.scala 33:92]
  wire  exe_stage_alu_0__sra_op1_128w_T_5 = exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1[63]; // @[Alu.scala 73:89]
  wire [63:0] exe_stage_alu_0__sra_op1_128w_T_7 = exe_stage_alu_0__sra_op1_128w_T_5 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 77:12]
  wire [127:0] exe_stage_alu_0__sra_op1_128w_T_9 = {exe_stage_alu_0__sra_op1_128w_T_7,
    exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1}; // @[Cat.scala 33:92]
  wire [127:0] exe_stage_alu_0_sra_op1_128w = exe_stage_alu_0_io_alu_iss_exe_bits_param_is_32w ?
    exe_stage_alu_0__sra_op1_128w_T_4 : exe_stage_alu_0__sra_op1_128w_T_9; // @[Alu.scala 73:25]
  wire [127:0] exe_stage_alu_0__alu_sra_res_T = exe_stage_alu_0_sra_op1_128w >> exe_stage_alu_0_shift_op2; // @[Alu.scala 74:56]
  wire  exe_stage_alu_0__alu_sra_res_T_1 = exe_stage_alu_0__alu_sra_res_T[31]; // @[Alu.scala 49:43]
  wire [31:0] exe_stage_alu_0__alu_sra_res_T_3 = exe_stage_alu_0__alu_sra_res_T_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [31:0] exe_stage_alu_0__alu_sra_res_T_4 = exe_stage_alu_0__alu_sra_res_T[31:0]; // @[Alu.scala 49:53]
  wire [63:0] exe_stage_alu_0__alu_sra_res_T_5 = {exe_stage_alu_0__alu_sra_res_T_3,exe_stage_alu_0__alu_sra_res_T_4}; // @[Cat.scala 33:92]
  wire [127:0] exe_stage_alu_0_alu_sra_res = exe_stage_alu_0_io_alu_iss_exe_bits_param_is_32w ? {{64'd0},
    exe_stage_alu_0__alu_sra_res_T_5} : exe_stage_alu_0__alu_sra_res_T; // @[Alu.scala 74:25]
  wire [127:0] exe_stage_alu_0__res_T = exe_stage_alu_0_io_alu_iss_exe_bits_fun_sra ? exe_stage_alu_0_alu_sra_res : 128'h0
    ; // @[Mux.scala 101:16]
  wire [127:0] exe_stage_alu_0__res_T_1 = exe_stage_alu_0_io_alu_iss_exe_bits_fun_srl ? {{64'd0},
    exe_stage_alu_0_alu_srl_res} : exe_stage_alu_0__res_T; // @[Mux.scala 101:16]
  wire [127:0] exe_stage_alu_0__res_T_2 = exe_stage_alu_0_io_alu_iss_exe_bits_fun_sll ? {{1'd0},
    exe_stage_alu_0_alu_sll_res} : exe_stage_alu_0__res_T_1; // @[Mux.scala 101:16]
  wire [127:0] exe_stage_alu_0__res_T_3 = exe_stage_alu_0_io_alu_iss_exe_bits_fun_and ? {{64'd0},
    exe_stage_alu_0_alu_and_res} : exe_stage_alu_0__res_T_2; // @[Mux.scala 101:16]
  wire [127:0] exe_stage_alu_0__res_T_4 = exe_stage_alu_0_io_alu_iss_exe_bits_fun_or ? {{64'd0},
    exe_stage_alu_0_alu_or_res} : exe_stage_alu_0__res_T_3; // @[Mux.scala 101:16]
  wire [127:0] exe_stage_alu_0__res_T_5 = exe_stage_alu_0_io_alu_iss_exe_bits_fun_xor ? {{64'd0},
    exe_stage_alu_0_alu_xor_res} : exe_stage_alu_0__res_T_4; // @[Mux.scala 101:16]
  wire [127:0] exe_stage_alu_0__res_T_6 = exe_stage_alu_0_io_alu_iss_exe_bits_fun_slt ? {{127'd0},
    exe_stage_alu_0_alu_slt_res} : exe_stage_alu_0__res_T_5; // @[Mux.scala 101:16]
  wire [127:0] exe_stage_alu_0_res = exe_stage_alu_0_io_alu_iss_exe_bits_fun_add ? {{64'd0}, exe_stage_alu_0_alu_add_res
    } : exe_stage_alu_0__res_T_6; // @[Mux.scala 101:16]
  wire  exe_stage_bru_clock;
  wire  exe_stage_bru_reset;
  wire  exe_stage_bru_io_bru_iss_exe_ready;
  wire  exe_stage_bru_io_bru_iss_exe_valid;
  wire  exe_stage_bru_io_bru_iss_exe_bits_fun_jalr;
  wire  exe_stage_bru_io_bru_iss_exe_bits_fun_beq;
  wire  exe_stage_bru_io_bru_iss_exe_bits_fun_bne;
  wire  exe_stage_bru_io_bru_iss_exe_bits_fun_blt;
  wire  exe_stage_bru_io_bru_iss_exe_bits_fun_bge;
  wire  exe_stage_bru_io_bru_iss_exe_bits_fun_bltu;
  wire  exe_stage_bru_io_bru_iss_exe_bits_fun_bgeu;
  wire [5:0] exe_stage_bru_io_bru_iss_exe_bits_param_rd0;
  wire  exe_stage_bru_io_bru_iss_exe_bits_param_is_rvc;
  wire [63:0] exe_stage_bru_io_bru_iss_exe_bits_param_pc;
  wire [63:0] exe_stage_bru_io_bru_iss_exe_bits_param_imm;
  wire [63:0] exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1;
  wire [63:0] exe_stage_bru_io_bru_iss_exe_bits_param_dat_op2;
  wire  exe_stage_bru_io_bru_exe_iwb_ready;
  wire  exe_stage_bru_io_bru_exe_iwb_valid;
  wire [5:0] exe_stage_bru_io_bru_exe_iwb_bits_rd0;
  wire [63:0] exe_stage_bru_io_bru_exe_iwb_bits_res;
  wire  exe_stage_bru_io_bftq_ready;
  wire  exe_stage_bru_io_bftq_valid;
  wire [38:0] exe_stage_bru_io_bftq_bits_pc;
  wire  exe_stage_bru_io_bftq_bits_bimResp_bim_p;
  wire  exe_stage_bru_io_bftq_bits_bimResp_bim_h;
  wire  exe_stage_bru_io_bftq_bits_isPredictTaken;
  wire  exe_stage_bru_io_jftq_ready;
  wire  exe_stage_bru_io_jftq_valid;
  wire [38:0] exe_stage_bru_io_jftq_bits_pc;
  wire [38:0] exe_stage_bru_io_jftq_bits_btbResp_target;
  wire [38:0] exe_stage_bru_io_jftq_bits_rasResp_target;
  wire  exe_stage_bru_io_jftq_bits_isRas;
  wire  exe_stage_bru_io_bctq_ready;
  wire  exe_stage_bru_io_bctq_valid;
  wire [38:0] exe_stage_bru_io_bctq_bits_pc;
  wire  exe_stage_bru_io_bctq_bits_bimResp_bim_p;
  wire  exe_stage_bru_io_bctq_bits_bimResp_bim_h;
  wire  exe_stage_bru_io_bctq_bits_isPredictTaken;
  wire  exe_stage_bru_io_bctq_bits_isFinalTaken;
  wire [63:0] exe_stage_bru_io_bctq_bits_finalTarget;
  wire  exe_stage_bru_io_jctq_ready;
  wire  exe_stage_bru_io_jctq_valid;
  wire [38:0] exe_stage_bru_io_jctq_bits_pc;
  wire [38:0] exe_stage_bru_io_jctq_bits_btbResp_target;
  wire [38:0] exe_stage_bru_io_jctq_bits_rasResp_target;
  wire  exe_stage_bru_io_jctq_bits_isRas;
  wire [63:0] exe_stage_bru_io_jctq_bits_finalTarget;
  wire  exe_stage_bru_io_bcmm_update_valid;
  wire [38:0] exe_stage_bru_io_bcmm_update_bits_pc;
  wire  exe_stage_bru_io_bcmm_update_bits_bimResp_bim_p;
  wire  exe_stage_bru_io_bcmm_update_bits_bimResp_bim_h;
  wire  exe_stage_bru_io_bcmm_update_bits_isFinalTaken;
  wire  exe_stage_bru_io_jcmm_update_valid;
  wire [38:0] exe_stage_bru_io_jcmm_update_bits_pc;
  wire [63:0] exe_stage_bru_io_jcmm_update_bits_finalTarget;
  wire  exe_stage_bru_io_flush;
  wire  exe_stage_bru_bru_exe_iwb_fifo_clock;
  wire  exe_stage_bru_bru_exe_iwb_fifo_reset;
  wire  exe_stage_bru_bru_exe_iwb_fifo_io_enq_ready;
  wire  exe_stage_bru_bru_exe_iwb_fifo_io_enq_valid;
  wire [5:0] exe_stage_bru_bru_exe_iwb_fifo_io_enq_bits_rd0;
  wire [63:0] exe_stage_bru_bru_exe_iwb_fifo_io_enq_bits_res;
  wire  exe_stage_bru_bru_exe_iwb_fifo_io_deq_ready;
  wire  exe_stage_bru_bru_exe_iwb_fifo_io_deq_valid;
  wire [5:0] exe_stage_bru_bru_exe_iwb_fifo_io_deq_bits_rd0;
  wire [63:0] exe_stage_bru_bru_exe_iwb_fifo_io_deq_bits_res;
  reg [5:0] exe_stage_bru_bru_exe_iwb_fifo_ram_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_clock;
  reg [63:0] exe_stage_bru_bru_exe_iwb_fifo_ram_res [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_bru_bru_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bru_exe_iwb_fifo_ram_res_clock;
  reg  exe_stage_bru_bru_exe_iwb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_bru_bru_exe_iwb_fifo__empty_T = ~exe_stage_bru_bru_exe_iwb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_bru_bru_exe_iwb_fifo__do_enq_T = exe_stage_bru_bru_exe_iwb_fifo_io_enq_ready &
    exe_stage_bru_bru_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru_bru_exe_iwb_fifo__do_deq_T = exe_stage_bru_bru_exe_iwb_fifo_io_deq_ready &
    exe_stage_bru_bru_exe_iwb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru_bru_exe_iwb_fifo__T = exe_stage_bru_bru_exe_iwb_fifo__do_enq_T !=
    exe_stage_bru_bru_exe_iwb_fifo__do_deq_T; // @[Decoupled.scala 295:15]
  wire  exe_stage_bru_bctq_clock;
  wire  exe_stage_bru_bctq_reset;
  wire  exe_stage_bru_bctq_io_enq_ready;
  wire  exe_stage_bru_bctq_io_enq_valid;
  wire [38:0] exe_stage_bru_bctq_io_enq_bits_pc;
  wire  exe_stage_bru_bctq_io_enq_bits_bimResp_bim_p;
  wire  exe_stage_bru_bctq_io_enq_bits_bimResp_bim_h;
  wire  exe_stage_bru_bctq_io_enq_bits_isPredictTaken;
  wire  exe_stage_bru_bctq_io_enq_bits_isFinalTaken;
  wire [63:0] exe_stage_bru_bctq_io_enq_bits_finalTarget;
  wire  exe_stage_bru_bctq_io_deq_ready;
  wire  exe_stage_bru_bctq_io_deq_valid;
  wire [38:0] exe_stage_bru_bctq_io_deq_bits_pc;
  wire  exe_stage_bru_bctq_io_deq_bits_bimResp_bim_p;
  wire  exe_stage_bru_bctq_io_deq_bits_bimResp_bim_h;
  wire  exe_stage_bru_bctq_io_deq_bits_isPredictTaken;
  wire  exe_stage_bru_bctq_io_deq_bits_isFinalTaken;
  wire [63:0] exe_stage_bru_bctq_io_deq_bits_finalTarget;
  reg [38:0] exe_stage_bru_bctq_ram_pc [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_pc_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_pc_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [38:0] exe_stage_bru_bctq_ram_pc_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [38:0] exe_stage_bru_bctq_ram_pc_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_pc_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_pc_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_pc_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_pc_clock;
  reg  exe_stage_bru_bctq_ram_bimResp_bim_p [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_p_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_p_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_p_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_p_clock;
  reg  exe_stage_bru_bctq_ram_bimResp_bim_h [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_h_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_h_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_h_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_bimResp_bim_h_clock;
  reg  exe_stage_bru_bctq_ram_isPredictTaken [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isPredictTaken_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isPredictTaken_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isPredictTaken_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isPredictTaken_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isPredictTaken_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isPredictTaken_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isPredictTaken_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isPredictTaken_clock;
  reg  exe_stage_bru_bctq_ram_isFinalTaken [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isFinalTaken_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isFinalTaken_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isFinalTaken_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isFinalTaken_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isFinalTaken_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isFinalTaken_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isFinalTaken_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_isFinalTaken_clock;
  reg [63:0] exe_stage_bru_bctq_ram_finalTarget [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_finalTarget_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_finalTarget_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_bru_bctq_ram_finalTarget_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_bru_bctq_ram_finalTarget_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_finalTarget_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_finalTarget_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_finalTarget_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_bctq_ram_finalTarget_clock;
  reg  exe_stage_bru_bctq_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_bru_bctq__empty_T = ~exe_stage_bru_bctq_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_bru_bctq__do_enq_T = exe_stage_bru_bctq_io_enq_ready & exe_stage_bru_bctq_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru_bctq__do_deq_T = exe_stage_bru_bctq_io_deq_ready & exe_stage_bru_bctq_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru_bctq__T = exe_stage_bru_bctq__do_enq_T != exe_stage_bru_bctq__do_deq_T; // @[Decoupled.scala 295:15]
  wire  exe_stage_bru_jctq_clock;
  wire  exe_stage_bru_jctq_reset;
  wire  exe_stage_bru_jctq_io_enq_ready;
  wire  exe_stage_bru_jctq_io_enq_valid;
  wire [38:0] exe_stage_bru_jctq_io_enq_bits_pc;
  wire [38:0] exe_stage_bru_jctq_io_enq_bits_btbResp_target;
  wire [38:0] exe_stage_bru_jctq_io_enq_bits_rasResp_target;
  wire  exe_stage_bru_jctq_io_enq_bits_isRas;
  wire [63:0] exe_stage_bru_jctq_io_enq_bits_finalTarget;
  wire  exe_stage_bru_jctq_io_deq_ready;
  wire  exe_stage_bru_jctq_io_deq_valid;
  wire [38:0] exe_stage_bru_jctq_io_deq_bits_pc;
  wire [38:0] exe_stage_bru_jctq_io_deq_bits_btbResp_target;
  wire [38:0] exe_stage_bru_jctq_io_deq_bits_rasResp_target;
  wire  exe_stage_bru_jctq_io_deq_bits_isRas;
  wire [63:0] exe_stage_bru_jctq_io_deq_bits_finalTarget;
  reg [38:0] exe_stage_bru_jctq_ram_pc [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_pc_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_pc_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [38:0] exe_stage_bru_jctq_ram_pc_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [38:0] exe_stage_bru_jctq_ram_pc_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_pc_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_pc_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_pc_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_pc_clock;
  reg [38:0] exe_stage_bru_jctq_ram_btbResp_target [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_btbResp_target_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_btbResp_target_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [38:0] exe_stage_bru_jctq_ram_btbResp_target_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [38:0] exe_stage_bru_jctq_ram_btbResp_target_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_btbResp_target_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_btbResp_target_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_btbResp_target_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_btbResp_target_clock;
  reg [38:0] exe_stage_bru_jctq_ram_rasResp_target [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_rasResp_target_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_rasResp_target_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [38:0] exe_stage_bru_jctq_ram_rasResp_target_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [38:0] exe_stage_bru_jctq_ram_rasResp_target_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_rasResp_target_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_rasResp_target_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_rasResp_target_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_rasResp_target_clock;
  reg  exe_stage_bru_jctq_ram_isRas [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_isRas_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_isRas_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_isRas_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_isRas_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_isRas_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_isRas_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_isRas_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_isRas_clock;
  reg [63:0] exe_stage_bru_jctq_ram_finalTarget [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_finalTarget_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_finalTarget_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_bru_jctq_ram_finalTarget_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_bru_jctq_ram_finalTarget_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_finalTarget_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_finalTarget_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_finalTarget_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_bru_jctq_ram_finalTarget_clock;
  reg  exe_stage_bru_jctq_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_bru_jctq__empty_T = ~exe_stage_bru_jctq_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_bru_jctq__do_enq_T = exe_stage_bru_jctq_io_enq_ready & exe_stage_bru_jctq_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru_jctq__do_deq_T = exe_stage_bru_jctq_io_deq_ready & exe_stage_bru_jctq_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru_jctq__T = exe_stage_bru_jctq__do_enq_T != exe_stage_bru_jctq__do_deq_T; // @[Decoupled.scala 295:15]
  reg  exe_stage_bru_misPredict_locker; // @[Bru.scala 50:34]
  wire  exe_stage_bru__is_branchTaken_T = exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1 ==
    exe_stage_bru_io_bru_iss_exe_bits_param_dat_op2; // @[Bru.scala 62:42]
  wire  exe_stage_bru__is_branchTaken_T_1 = exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1 !=
    exe_stage_bru_io_bru_iss_exe_bits_param_dat_op2; // @[Bru.scala 63:42]
  wire  exe_stage_bru__is_branchTaken_T_4 = $signed(exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1) < $signed(
    exe_stage_bru_io_bru_iss_exe_bits_param_dat_op2); // @[Bru.scala 64:49]
  wire  exe_stage_bru__is_branchTaken_T_7 = $signed(exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1) >= $signed(
    exe_stage_bru_io_bru_iss_exe_bits_param_dat_op2); // @[Bru.scala 65:49]
  wire  exe_stage_bru__is_branchTaken_T_8 = exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1 <
    exe_stage_bru_io_bru_iss_exe_bits_param_dat_op2; // @[Bru.scala 66:42]
  wire  exe_stage_bru__is_branchTaken_T_9 = exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1 >=
    exe_stage_bru_io_bru_iss_exe_bits_param_dat_op2; // @[Bru.scala 67:42]
  wire  exe_stage_bru__is_branchTaken_T_10 = exe_stage_bru_io_bru_iss_exe_bits_fun_beq & exe_stage_bru__is_branchTaken_T
    ; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_11 = exe_stage_bru_io_bru_iss_exe_bits_fun_bne &
    exe_stage_bru__is_branchTaken_T_1; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_12 = exe_stage_bru_io_bru_iss_exe_bits_fun_blt &
    exe_stage_bru__is_branchTaken_T_4; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_13 = exe_stage_bru_io_bru_iss_exe_bits_fun_bge &
    exe_stage_bru__is_branchTaken_T_7; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_14 = exe_stage_bru_io_bru_iss_exe_bits_fun_bltu &
    exe_stage_bru__is_branchTaken_T_8; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_15 = exe_stage_bru_io_bru_iss_exe_bits_fun_bgeu &
    exe_stage_bru__is_branchTaken_T_9; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_16 = exe_stage_bru__is_branchTaken_T_10 | exe_stage_bru__is_branchTaken_T_11; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_17 = exe_stage_bru__is_branchTaken_T_16 | exe_stage_bru__is_branchTaken_T_12; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_18 = exe_stage_bru__is_branchTaken_T_17 | exe_stage_bru__is_branchTaken_T_13; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_19 = exe_stage_bru__is_branchTaken_T_18 | exe_stage_bru__is_branchTaken_T_14; // @[Mux.scala 27:73]
  wire  exe_stage_bru__is_branchTaken_T_20 = exe_stage_bru__is_branchTaken_T_19 | exe_stage_bru__is_branchTaken_T_15; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_bru__bctq_io_enq_bits_finalTarget_T_1 = exe_stage_bru_io_bru_iss_exe_bits_param_pc +
    exe_stage_bru_io_bru_iss_exe_bits_param_imm; // @[Bru.scala 72:61]
  wire [2:0] exe_stage_bru__bctq_io_enq_bits_finalTarget_T_2 = exe_stage_bru_io_bru_iss_exe_bits_param_is_rvc ? 3'h2 : 3'h4
    ; // @[Bru.scala 72:78]
  wire [63:0] _GEN_288 = {{61'd0}, exe_stage_bru__bctq_io_enq_bits_finalTarget_T_2}; // @[Bru.scala 72:73]
  wire [63:0] exe_stage_bru__bctq_io_enq_bits_finalTarget_T_4 = exe_stage_bru_io_bru_iss_exe_bits_param_pc + _GEN_288; // @[Bru.scala 72:73]
  wire [63:0] exe_stage_bru__jctq_io_enq_bits_finalTarget_T_1 = exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1 +
    exe_stage_bru_io_bru_iss_exe_bits_param_imm; // @[Bru.scala 79:40]
  wire [62:0] exe_stage_bru__jctq_io_enq_bits_finalTarget_T_2 = exe_stage_bru__jctq_io_enq_bits_finalTarget_T_1[63:1]; // @[Bru.scala 79:47]
  wire  exe_stage_bru__io_bcmm_update_bits_T = exe_stage_bru_io_bctq_ready & exe_stage_bru_io_bctq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru__io_jcmm_update_bits_T = exe_stage_bru_io_jctq_ready & exe_stage_bru_io_jctq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru__T_1 = exe_stage_bru_bctq_io_enq_bits_isPredictTaken !=
    exe_stage_bru_bctq_io_enq_bits_isFinalTaken; // @[frontend.scala 245:37]
  wire  exe_stage_bru__T_2 = exe_stage_bru_bctq__do_enq_T & exe_stage_bru__T_1; // @[Bru.scala 97:34]
  wire [63:0] _GEN_289 = {{25'd0}, exe_stage_bru_jctq_io_enq_bits_rasResp_target}; // @[frontend.scala 250:48]
  wire  exe_stage_bru__T_4 = _GEN_289 != exe_stage_bru_jctq_io_enq_bits_finalTarget; // @[frontend.scala 250:48]
  wire [63:0] _GEN_290 = {{25'd0}, exe_stage_bru_jctq_io_enq_bits_btbResp_target}; // @[frontend.scala 250:80]
  wire  exe_stage_bru__T_5 = _GEN_290 != exe_stage_bru_jctq_io_enq_bits_finalTarget; // @[frontend.scala 250:80]
  wire  exe_stage_bru__T_6 = exe_stage_bru_jctq_io_enq_bits_isRas ? exe_stage_bru__T_4 : exe_stage_bru__T_5; // @[frontend.scala 250:25]
  wire  exe_stage_bru__T_7 = exe_stage_bru_jctq__do_enq_T & exe_stage_bru__T_6; // @[Bru.scala 97:87]
  wire  exe_stage_bru__T_8 = exe_stage_bru__T_2 | exe_stage_bru__T_7; // @[Bru.scala 97:67]
  wire  exe_stage_bru__GEN_0 = exe_stage_bru__T_8 | exe_stage_bru_misPredict_locker; // @[Bru.scala 97:122 98:23 50:34]
  wire  exe_stage_bru__io_bru_iss_exe_ready_T = exe_stage_bru_bru_exe_iwb_fifo_io_enq_ready &
    exe_stage_bru_bctq_io_enq_ready; // @[Bru.scala 110:57]
  wire  exe_stage_bru__io_bru_iss_exe_ready_T_1 = exe_stage_bru__io_bru_iss_exe_ready_T &
    exe_stage_bru_jctq_io_enq_ready; // @[Bru.scala 110:77]
  wire  exe_stage_bru__io_bru_iss_exe_ready_T_2 = ~exe_stage_bru_misPredict_locker; // @[Bru.scala 110:99]
  wire  exe_stage_bru__io_bftq_ready_T = exe_stage_bru_io_bru_iss_exe_ready & exe_stage_bru_io_bru_iss_exe_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru__io_bftq_ready_T_1 = exe_stage_bru_io_bru_iss_exe_bits_fun_beq |
    exe_stage_bru_io_bru_iss_exe_bits_fun_bne; // @[riscv_isa.scala 93:23]
  wire  exe_stage_bru__io_bftq_ready_T_2 = exe_stage_bru__io_bftq_ready_T_1 | exe_stage_bru_io_bru_iss_exe_bits_fun_blt; // @[riscv_isa.scala 93:29]
  wire  exe_stage_bru__io_bftq_ready_T_3 = exe_stage_bru__io_bftq_ready_T_2 | exe_stage_bru_io_bru_iss_exe_bits_fun_bge; // @[riscv_isa.scala 93:35]
  wire  exe_stage_bru__io_bftq_ready_T_4 = exe_stage_bru__io_bftq_ready_T_3 | exe_stage_bru_io_bru_iss_exe_bits_fun_bltu
    ; // @[riscv_isa.scala 93:41]
  wire  exe_stage_bru__io_bftq_ready_T_5 = exe_stage_bru__io_bftq_ready_T_4 | exe_stage_bru_io_bru_iss_exe_bits_fun_bgeu
    ; // @[riscv_isa.scala 93:48]
  wire  exe_stage_bru__io_bftq_ready_T_6 = exe_stage_bru__io_bftq_ready_T & exe_stage_bru__io_bftq_ready_T_5; // @[Bru.scala 112:40]
  wire  exe_stage_bru__io_jftq_ready_T_1 = exe_stage_bru__io_bftq_ready_T & exe_stage_bru_io_bru_iss_exe_bits_fun_jalr; // @[Bru.scala 113:40]
  wire  exe_stage_bru__T_12 = exe_stage_bru_jctq__do_enq_T == exe_stage_bru__io_jftq_ready_T_1; // @[Bru.scala 124:28]
  wire  exe_stage_bru__T_14 = ~exe_stage_bru_reset; // @[Bru.scala 124:9]
  wire  exe_stage_bru__T_15 = ~exe_stage_bru__T_12; // @[Bru.scala 124:9]
  wire  exe_stage_bru__T_16 = exe_stage_bru_io_jftq_ready & exe_stage_bru_io_jftq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru__T_18 = exe_stage_bru__T_16 == exe_stage_bru_jctq__do_enq_T; // @[Bru.scala 125:24]
  wire  exe_stage_bru__T_21 = ~exe_stage_bru__T_18; // @[Bru.scala 125:9]
  wire  exe_stage_bru__T_30 = exe_stage_bru_bctq__do_enq_T == exe_stage_bru__io_bftq_ready_T_6; // @[Bru.scala 126:28]
  wire  exe_stage_bru__T_33 = ~exe_stage_bru__T_30; // @[Bru.scala 126:9]
  wire  exe_stage_bru__T_34 = exe_stage_bru_io_bftq_ready & exe_stage_bru_io_bftq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_bru__T_36 = exe_stage_bru__T_34 == exe_stage_bru_bctq__do_enq_T; // @[Bru.scala 127:24]
  wire  exe_stage_bru__T_39 = ~exe_stage_bru__T_36; // @[Bru.scala 127:9]
  wire  exe_stage_bru__T_42 = exe_stage_bru__io_bftq_ready_T == exe_stage_bru_bru_exe_iwb_fifo__do_enq_T; // @[Bru.scala 128:31]
  wire  exe_stage_bru__T_45 = ~exe_stage_bru__T_42; // @[Bru.scala 128:9]
  wire  exe_stage_lsu_clock;
  wire  exe_stage_lsu_reset;
  wire  exe_stage_lsu_io_lsu_iss_exe_ready;
  wire  exe_stage_lsu_io_lsu_iss_exe_valid;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_lb;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_lh;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_lw;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_ld;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_lbu;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_lhu;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_lwu;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_sb;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_sh;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_sw;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_sd;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_fence;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_fence_i;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_sfence_vma;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_flw;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsw;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_fld;
  wire  exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsd;
  wire [5:0] exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0;
  wire [63:0] exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op1;
  wire [63:0] exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op2;
  wire  exe_stage_lsu_io_lsu_exe_iwb_ready;
  wire  exe_stage_lsu_io_lsu_exe_iwb_valid;
  wire [5:0] exe_stage_lsu_io_lsu_exe_iwb_bits_rd0;
  wire [63:0] exe_stage_lsu_io_lsu_exe_iwb_bits_res;
  wire  exe_stage_lsu_io_lsu_exe_fwb_ready;
  wire  exe_stage_lsu_io_lsu_exe_fwb_valid;
  wire  exe_stage_lsu_io_cmm_lsu_is_amo_pending;
  wire  exe_stage_lsu_io_cmm_lsu_is_store_commit_0;
  wire  exe_stage_lsu_io_lsu_cmm_is_access_fault;
  wire  exe_stage_lsu_io_lsu_cmm_is_paging_fault;
  wire  exe_stage_lsu_io_lsu_cmm_is_misAlign;
  wire [63:0] exe_stage_lsu_io_lsu_cmm_trap_addr;
  wire  exe_stage_lsu_io_lsu_mmu_ready;
  wire  exe_stage_lsu_io_lsu_mmu_valid;
  wire  exe_stage_lsu_io_lsu_mmu_bits_is_X;
  wire  exe_stage_lsu_io_lsu_mmu_bits_is_W;
  wire  exe_stage_lsu_io_lsu_mmu_bits_is_R;
  wire [63:0] exe_stage_lsu_io_lsu_mmu_bits_vaddr;
  wire  exe_stage_lsu_io_mmu_lsu_ready;
  wire  exe_stage_lsu_io_mmu_lsu_valid;
  wire [63:0] exe_stage_lsu_io_mmu_lsu_bits_paddr;
  wire  exe_stage_lsu_io_mmu_lsu_bits_is_paging_fault;
  wire  exe_stage_lsu_io_mmu_lsu_bits_is_access_fault;
  wire  exe_stage_lsu_io_missUnit_dcache_acquire_ready;
  wire  exe_stage_lsu_io_missUnit_dcache_acquire_valid;
  wire [2:0] exe_stage_lsu_io_missUnit_dcache_acquire_bits_opcode;
  wire [2:0] exe_stage_lsu_io_missUnit_dcache_acquire_bits_param;
  wire [2:0] exe_stage_lsu_io_missUnit_dcache_acquire_bits_size;
  wire  exe_stage_lsu_io_missUnit_dcache_acquire_bits_source;
  wire [31:0] exe_stage_lsu_io_missUnit_dcache_acquire_bits_address;
  wire [7:0] exe_stage_lsu_io_missUnit_dcache_acquire_bits_mask;
  wire [63:0] exe_stage_lsu_io_missUnit_dcache_acquire_bits_data;
  wire  exe_stage_lsu_io_missUnit_dcache_acquire_bits_corrupt;
  wire  exe_stage_lsu_io_missUnit_dcache_grant_ready;
  wire  exe_stage_lsu_io_missUnit_dcache_grant_valid;
  wire [2:0] exe_stage_lsu_io_missUnit_dcache_grant_bits_opcode;
  wire [2:0] exe_stage_lsu_io_missUnit_dcache_grant_bits_size;
  wire  exe_stage_lsu_io_missUnit_dcache_grant_bits_source;
  wire [4:0] exe_stage_lsu_io_missUnit_dcache_grant_bits_sink;
  wire [63:0] exe_stage_lsu_io_missUnit_dcache_grant_bits_data;
  wire  exe_stage_lsu_io_missUnit_dcache_grantAck_ready;
  wire  exe_stage_lsu_io_missUnit_dcache_grantAck_valid;
  wire [4:0] exe_stage_lsu_io_missUnit_dcache_grantAck_bits_sink;
  wire  exe_stage_lsu_io_probeUnit_dcache_probe_ready;
  wire  exe_stage_lsu_io_probeUnit_dcache_probe_valid;
  wire [31:0] exe_stage_lsu_io_probeUnit_dcache_probe_bits_address;
  wire  exe_stage_lsu_io_writeBackUnit_dcache_release_ready;
  wire  exe_stage_lsu_io_writeBackUnit_dcache_release_valid;
  wire [2:0] exe_stage_lsu_io_writeBackUnit_dcache_release_bits_opcode;
  wire [2:0] exe_stage_lsu_io_writeBackUnit_dcache_release_bits_param;
  wire [2:0] exe_stage_lsu_io_writeBackUnit_dcache_release_bits_size;
  wire  exe_stage_lsu_io_writeBackUnit_dcache_release_bits_source;
  wire [31:0] exe_stage_lsu_io_writeBackUnit_dcache_release_bits_address;
  wire [63:0] exe_stage_lsu_io_writeBackUnit_dcache_release_bits_data;
  wire  exe_stage_lsu_io_writeBackUnit_dcache_release_bits_corrupt;
  wire  exe_stage_lsu_io_writeBackUnit_dcache_grant_ready;
  wire  exe_stage_lsu_io_writeBackUnit_dcache_grant_valid;
  wire  exe_stage_lsu_io_writeBackUnit_dcache_grant_bits_source;
  wire  exe_stage_lsu_io_system_getPut_ready;
  wire  exe_stage_lsu_io_system_getPut_valid;
  wire [2:0] exe_stage_lsu_io_system_getPut_bits_opcode;
  wire [2:0] exe_stage_lsu_io_system_getPut_bits_param;
  wire [1:0] exe_stage_lsu_io_system_getPut_bits_size;
  wire  exe_stage_lsu_io_system_getPut_bits_source;
  wire [31:0] exe_stage_lsu_io_system_getPut_bits_address;
  wire [7:0] exe_stage_lsu_io_system_getPut_bits_mask;
  wire [63:0] exe_stage_lsu_io_system_getPut_bits_data;
  wire  exe_stage_lsu_io_system_getPut_bits_corrupt;
  wire  exe_stage_lsu_io_system_access_ready;
  wire  exe_stage_lsu_io_system_access_valid;
  wire [2:0] exe_stage_lsu_io_system_access_bits_opcode;
  wire [63:0] exe_stage_lsu_io_system_access_bits_data;
  wire  exe_stage_lsu_io_periph_getPut_ready;
  wire  exe_stage_lsu_io_periph_getPut_valid;
  wire [2:0] exe_stage_lsu_io_periph_getPut_bits_opcode;
  wire [2:0] exe_stage_lsu_io_periph_getPut_bits_param;
  wire [1:0] exe_stage_lsu_io_periph_getPut_bits_size;
  wire  exe_stage_lsu_io_periph_getPut_bits_source;
  wire [31:0] exe_stage_lsu_io_periph_getPut_bits_address;
  wire [7:0] exe_stage_lsu_io_periph_getPut_bits_mask;
  wire [63:0] exe_stage_lsu_io_periph_getPut_bits_data;
  wire  exe_stage_lsu_io_periph_getPut_bits_corrupt;
  wire  exe_stage_lsu_io_periph_access_ready;
  wire  exe_stage_lsu_io_periph_access_valid;
  wire [2:0] exe_stage_lsu_io_periph_access_bits_opcode;
  wire [63:0] exe_stage_lsu_io_periph_access_bits_data;
  wire  exe_stage_lsu_io_flush;
  wire  exe_stage_lsu_stQueue_clock;
  wire  exe_stage_lsu_stQueue_reset;
  wire  exe_stage_lsu_stQueue_io_enq_ready;
  wire  exe_stage_lsu_stQueue_io_enq_valid;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_lb;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_lh;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_lw;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_ld;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_lbu;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_lhu;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_lwu;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_sb;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_sh;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_sw;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_sd;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_lr_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_sc_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoand_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoor_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amomin_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amomax_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amominu_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_lr_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_sc_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoand_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amoor_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amomin_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amomax_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amominu_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_flw;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_fsw;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_fld;
  wire  exe_stage_lsu_stQueue_io_enq_bits_fun_fsd;
  wire [5:0] exe_stage_lsu_stQueue_io_enq_bits_param_rd0;
  wire [63:0] exe_stage_lsu_stQueue_io_enq_bits_param_dat_op1;
  wire [63:0] exe_stage_lsu_stQueue_io_enq_bits_param_dat_op2;
  wire  exe_stage_lsu_stQueue_io_deq_ready;
  wire  exe_stage_lsu_stQueue_io_deq_valid;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_lb;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_lh;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_lw;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_ld;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_lbu;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_lhu;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_lwu;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_sb;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_sh;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_sw;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_sd;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_lr_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_sc_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoand_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoor_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amomin_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amomax_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amominu_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_lr_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_sc_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoand_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amoor_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amomin_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amomax_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amominu_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_flw;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_fsw;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_fld;
  wire  exe_stage_lsu_stQueue_io_deq_bits_fun_fsd;
  wire [5:0] exe_stage_lsu_stQueue_io_deq_bits_param_rd0;
  wire [63:0] exe_stage_lsu_stQueue_io_deq_bits_param_dat_op1;
  wire [63:0] exe_stage_lsu_stQueue_io_deq_bits_param_dat_op2;
  wire  exe_stage_lsu_stQueue_io_cmm_lsu_is_amo_pending;
  wire  exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0;
  wire  exe_stage_lsu_stQueue_io_is_empty;
  wire  exe_stage_lsu_stQueue_io_overlapReq_valid;
  wire [31:0] exe_stage_lsu_stQueue_io_overlapReq_bits_paddr;
  wire  exe_stage_lsu_stQueue_io_overlapResp_valid;
  wire [63:0] exe_stage_lsu_stQueue_io_overlapResp_bits_wdata;
  wire [7:0] exe_stage_lsu_stQueue_io_overlapResp_bits_wstrb;
  wire  exe_stage_lsu_stQueue_io_flush;
  reg  exe_stage_lsu_stQueue_buff_0_fun_lb; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_lh; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_lw; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_ld; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_lbu; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_lhu; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_lwu; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_sb; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_sh; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_sw; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_sd; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_lr_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_sc_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoswap_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoadd_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoxor_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoand_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoor_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amomin_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amomax_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amominu_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_lr_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_sc_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoswap_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoadd_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoxor_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoand_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amoor_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amomin_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amomax_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amominu_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_flw; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_fsw; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_fld; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_0_fun_fsd; // @[Store_queue.scala 54:21]
  reg [5:0] exe_stage_lsu_stQueue_buff_0_param_rd0; // @[Store_queue.scala 54:21]
  reg [63:0] exe_stage_lsu_stQueue_buff_0_param_dat_op1; // @[Store_queue.scala 54:21]
  reg [63:0] exe_stage_lsu_stQueue_buff_0_param_dat_op2; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_lb; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_lh; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_lw; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_ld; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_lbu; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_lhu; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_lwu; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_sb; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_sh; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_sw; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_sd; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_lr_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_sc_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoswap_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoadd_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoxor_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoand_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoor_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amomin_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amomax_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amominu_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_lr_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_sc_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoswap_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoadd_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoxor_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoand_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amoor_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amomin_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amomax_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amominu_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_flw; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_fsw; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_fld; // @[Store_queue.scala 54:21]
  reg  exe_stage_lsu_stQueue_buff_1_fun_fsd; // @[Store_queue.scala 54:21]
  reg [5:0] exe_stage_lsu_stQueue_buff_1_param_rd0; // @[Store_queue.scala 54:21]
  reg [63:0] exe_stage_lsu_stQueue_buff_1_param_dat_op1; // @[Store_queue.scala 54:21]
  reg [63:0] exe_stage_lsu_stQueue_buff_1_param_dat_op2; // @[Store_queue.scala 54:21]
  reg [1:0] exe_stage_lsu_stQueue_cm_ptr_reg; // @[Store_queue.scala 56:27]
  reg [1:0] exe_stage_lsu_stQueue_wr_ptr_reg; // @[Store_queue.scala 57:27]
  reg [1:0] exe_stage_lsu_stQueue_rd_ptr_reg; // @[Store_queue.scala 58:27]
  wire  exe_stage_lsu_stQueue_wr_ptr = exe_stage_lsu_stQueue_wr_ptr_reg[0]; // @[Store_queue.scala 61:26]
  wire  exe_stage_lsu_stQueue_rd_ptr = exe_stage_lsu_stQueue_rd_ptr_reg[0]; // @[Store_queue.scala 62:26]
  wire  exe_stage_lsu_stQueue__full_T = exe_stage_lsu_stQueue_wr_ptr_reg[1]; // @[Store_queue.scala 64:25]
  wire  exe_stage_lsu_stQueue__full_T_1 = exe_stage_lsu_stQueue_rd_ptr_reg[1]; // @[Store_queue.scala 64:46]
  wire  exe_stage_lsu_stQueue__full_T_2 = exe_stage_lsu_stQueue__full_T != exe_stage_lsu_stQueue__full_T_1; // @[Store_queue.scala 64:32]
  wire  exe_stage_lsu_stQueue__full_T_5 = exe_stage_lsu_stQueue_wr_ptr == exe_stage_lsu_stQueue_rd_ptr; // @[Store_queue.scala 64:78]
  wire  exe_stage_lsu_stQueue_full = exe_stage_lsu_stQueue__full_T_2 & exe_stage_lsu_stQueue__full_T_5; // @[Store_queue.scala 64:54]
  wire  exe_stage_lsu_stQueue_emty = exe_stage_lsu_stQueue_cm_ptr_reg == exe_stage_lsu_stQueue_rd_ptr_reg; // @[Store_queue.scala 65:25]
  reg  exe_stage_lsu_stQueue_is_amo; // @[Store_queue.scala 69:23]
  reg  exe_stage_lsu_stQueue_is_amo_pre; // @[Store_queue.scala 76:29]
  wire  exe_stage_lsu_stQueue__is_amo_pos_T = ~exe_stage_lsu_stQueue_is_amo_pre; // @[Store_queue.scala 77:50]
  wire  exe_stage_lsu_stQueue_is_amo_pos = exe_stage_lsu_stQueue_io_cmm_lsu_is_amo_pending &
    exe_stage_lsu_stQueue__is_amo_pos_T; // @[Store_queue.scala 77:48]
  wire  exe_stage_lsu_stQueue__T = ~exe_stage_lsu_stQueue_io_is_empty; // @[Store_queue.scala 82:26]
  wire  exe_stage_lsu_stQueue__T_1 = exe_stage_lsu_stQueue_is_amo & exe_stage_lsu_stQueue__T; // @[Store_queue.scala 82:24]
  wire  exe_stage_lsu_stQueue__GEN_0 = exe_stage_lsu_stQueue__T_1 ? 1'h0 : exe_stage_lsu_stQueue_is_amo; // @[Store_queue.scala 82:40 83:14 69:23]
  wire  exe_stage_lsu_stQueue__GEN_1 = exe_stage_lsu_stQueue_is_amo_pos | exe_stage_lsu_stQueue__GEN_0; // @[Store_queue.scala 80:31 81:14]
  wire  exe_stage_lsu_stQueue__GEN_47 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lb :
    exe_stage_lsu_stQueue_buff_0_fun_lb; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_48 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lh :
    exe_stage_lsu_stQueue_buff_0_fun_lh; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_49 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lw :
    exe_stage_lsu_stQueue_buff_0_fun_lw; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_50 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_ld :
    exe_stage_lsu_stQueue_buff_0_fun_ld; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_51 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lbu :
    exe_stage_lsu_stQueue_buff_0_fun_lbu; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_52 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lhu :
    exe_stage_lsu_stQueue_buff_0_fun_lhu; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_53 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lwu :
    exe_stage_lsu_stQueue_buff_0_fun_lwu; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_54 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sb :
    exe_stage_lsu_stQueue_buff_0_fun_sb; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_55 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sh :
    exe_stage_lsu_stQueue_buff_0_fun_sh; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_56 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sw :
    exe_stage_lsu_stQueue_buff_0_fun_sw; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_57 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sd :
    exe_stage_lsu_stQueue_buff_0_fun_sd; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_61 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lr_w :
    exe_stage_lsu_stQueue_buff_0_fun_lr_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_62 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sc_w :
    exe_stage_lsu_stQueue_buff_0_fun_sc_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_63 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoswap_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoswap_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_64 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoadd_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoadd_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_65 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoxor_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoxor_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_66 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoand_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoand_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_67 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoor_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoor_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_68 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomin_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomin_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_69 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomax_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomax_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_70 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amominu_w :
    exe_stage_lsu_stQueue_buff_0_fun_amominu_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_71 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_72 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lr_d :
    exe_stage_lsu_stQueue_buff_0_fun_lr_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_73 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sc_d :
    exe_stage_lsu_stQueue_buff_0_fun_sc_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_74 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoswap_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoswap_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_75 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoadd_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoadd_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_76 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoxor_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoxor_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_77 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoand_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoand_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_78 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoor_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoor_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_79 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomin_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomin_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_80 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomax_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomax_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_81 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amominu_d :
    exe_stage_lsu_stQueue_buff_0_fun_amominu_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_82 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_83 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_flw :
    exe_stage_lsu_stQueue_buff_0_fun_flw; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_84 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_fsw :
    exe_stage_lsu_stQueue_buff_0_fun_fsw; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_85 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_fld :
    exe_stage_lsu_stQueue_buff_0_fun_fld; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__GEN_86 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_fun_fsd :
    exe_stage_lsu_stQueue_buff_0_fun_fsd; // @[Store_queue.scala 92:{21,21}]
  wire [5:0] exe_stage_lsu_stQueue__GEN_87 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_param_rd0 :
    exe_stage_lsu_stQueue_buff_0_param_rd0; // @[Store_queue.scala 92:{21,21}]
  wire [63:0] exe_stage_lsu_stQueue__GEN_88 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_param_dat_op1
     : exe_stage_lsu_stQueue_buff_0_param_dat_op1; // @[Store_queue.scala 92:{21,21}]
  wire [63:0] exe_stage_lsu_stQueue__GEN_89 = exe_stage_lsu_stQueue_rd_ptr ? exe_stage_lsu_stQueue_buff_1_param_dat_op2
     : exe_stage_lsu_stQueue_buff_0_param_dat_op2; // @[Store_queue.scala 92:{21,21}]
  wire  exe_stage_lsu_stQueue__T_4 = exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 | exe_stage_lsu_stQueue__T_1; // @[Store_queue.scala 100:31]
  wire [1:0] exe_stage_lsu_stQueue__wr_ptr_reg_T_1 = exe_stage_lsu_stQueue_cm_ptr_reg + 2'h1; // @[Store_queue.scala 100:86]
  wire  exe_stage_lsu_stQueue__T_5 = exe_stage_lsu_stQueue_io_enq_ready & exe_stage_lsu_stQueue_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_stQueue__GEN_92 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lb :
    exe_stage_lsu_stQueue_buff_0_fun_lb; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_93 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lb :
    exe_stage_lsu_stQueue_buff_1_fun_lb; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_94 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lh :
    exe_stage_lsu_stQueue_buff_0_fun_lh; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_95 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lh :
    exe_stage_lsu_stQueue_buff_1_fun_lh; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_96 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lw :
    exe_stage_lsu_stQueue_buff_0_fun_lw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_97 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lw :
    exe_stage_lsu_stQueue_buff_1_fun_lw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_98 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_ld :
    exe_stage_lsu_stQueue_buff_0_fun_ld; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_99 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_ld :
    exe_stage_lsu_stQueue_buff_1_fun_ld; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_100 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lbu :
    exe_stage_lsu_stQueue_buff_0_fun_lbu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_101 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lbu :
    exe_stage_lsu_stQueue_buff_1_fun_lbu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_102 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lhu :
    exe_stage_lsu_stQueue_buff_0_fun_lhu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_103 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lhu :
    exe_stage_lsu_stQueue_buff_1_fun_lhu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_104 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lwu :
    exe_stage_lsu_stQueue_buff_0_fun_lwu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_105 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lwu :
    exe_stage_lsu_stQueue_buff_1_fun_lwu; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_106 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sb :
    exe_stage_lsu_stQueue_buff_0_fun_sb; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_107 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sb :
    exe_stage_lsu_stQueue_buff_1_fun_sb; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_108 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sh :
    exe_stage_lsu_stQueue_buff_0_fun_sh; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_109 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sh :
    exe_stage_lsu_stQueue_buff_1_fun_sh; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_110 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sw :
    exe_stage_lsu_stQueue_buff_0_fun_sw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_111 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sw :
    exe_stage_lsu_stQueue_buff_1_fun_sw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_112 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sd :
    exe_stage_lsu_stQueue_buff_0_fun_sd; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_113 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sd :
    exe_stage_lsu_stQueue_buff_1_fun_sd; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_120 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lr_w :
    exe_stage_lsu_stQueue_buff_0_fun_lr_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_121 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lr_w :
    exe_stage_lsu_stQueue_buff_1_fun_lr_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_122 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sc_w :
    exe_stage_lsu_stQueue_buff_0_fun_sc_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_123 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sc_w :
    exe_stage_lsu_stQueue_buff_1_fun_sc_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_124 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoswap_w
     : exe_stage_lsu_stQueue_buff_0_fun_amoswap_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_125 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoswap_w
     : exe_stage_lsu_stQueue_buff_1_fun_amoswap_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_126 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoadd_w
     : exe_stage_lsu_stQueue_buff_0_fun_amoadd_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_127 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoadd_w
     : exe_stage_lsu_stQueue_buff_1_fun_amoadd_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_128 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoxor_w
     : exe_stage_lsu_stQueue_buff_0_fun_amoxor_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_129 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoxor_w
     : exe_stage_lsu_stQueue_buff_1_fun_amoxor_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_130 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoand_w
     : exe_stage_lsu_stQueue_buff_0_fun_amoand_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_131 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoand_w
     : exe_stage_lsu_stQueue_buff_1_fun_amoand_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_132 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoor_w
     : exe_stage_lsu_stQueue_buff_0_fun_amoor_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_133 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoor_w :
    exe_stage_lsu_stQueue_buff_1_fun_amoor_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_134 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomin_w
     : exe_stage_lsu_stQueue_buff_0_fun_amomin_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_135 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomin_w
     : exe_stage_lsu_stQueue_buff_1_fun_amomin_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_136 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomax_w
     : exe_stage_lsu_stQueue_buff_0_fun_amomax_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_137 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomax_w
     : exe_stage_lsu_stQueue_buff_1_fun_amomax_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_138 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amominu_w
     : exe_stage_lsu_stQueue_buff_0_fun_amominu_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_139 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amominu_w
     : exe_stage_lsu_stQueue_buff_1_fun_amominu_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_140 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomaxu_w
     : exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_141 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomaxu_w
     : exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_142 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lr_d :
    exe_stage_lsu_stQueue_buff_0_fun_lr_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_143 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_lr_d :
    exe_stage_lsu_stQueue_buff_1_fun_lr_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_144 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sc_d :
    exe_stage_lsu_stQueue_buff_0_fun_sc_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_145 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_sc_d :
    exe_stage_lsu_stQueue_buff_1_fun_sc_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_146 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoswap_d
     : exe_stage_lsu_stQueue_buff_0_fun_amoswap_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_147 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoswap_d
     : exe_stage_lsu_stQueue_buff_1_fun_amoswap_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_148 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoadd_d
     : exe_stage_lsu_stQueue_buff_0_fun_amoadd_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_149 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoadd_d
     : exe_stage_lsu_stQueue_buff_1_fun_amoadd_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_150 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoxor_d
     : exe_stage_lsu_stQueue_buff_0_fun_amoxor_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_151 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoxor_d
     : exe_stage_lsu_stQueue_buff_1_fun_amoxor_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_152 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoand_d
     : exe_stage_lsu_stQueue_buff_0_fun_amoand_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_153 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoand_d
     : exe_stage_lsu_stQueue_buff_1_fun_amoand_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_154 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoor_d
     : exe_stage_lsu_stQueue_buff_0_fun_amoor_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_155 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amoor_d :
    exe_stage_lsu_stQueue_buff_1_fun_amoor_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_156 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomin_d
     : exe_stage_lsu_stQueue_buff_0_fun_amomin_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_157 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomin_d
     : exe_stage_lsu_stQueue_buff_1_fun_amomin_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_158 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomax_d
     : exe_stage_lsu_stQueue_buff_0_fun_amomax_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_159 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomax_d
     : exe_stage_lsu_stQueue_buff_1_fun_amomax_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_160 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amominu_d
     : exe_stage_lsu_stQueue_buff_0_fun_amominu_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_161 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amominu_d
     : exe_stage_lsu_stQueue_buff_1_fun_amominu_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_162 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomaxu_d
     : exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_163 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_amomaxu_d
     : exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_164 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_flw :
    exe_stage_lsu_stQueue_buff_0_fun_flw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_165 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_flw :
    exe_stage_lsu_stQueue_buff_1_fun_flw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_166 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_fsw :
    exe_stage_lsu_stQueue_buff_0_fun_fsw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_167 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_fsw :
    exe_stage_lsu_stQueue_buff_1_fun_fsw; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_168 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_fld :
    exe_stage_lsu_stQueue_buff_0_fun_fld; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_169 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_fld :
    exe_stage_lsu_stQueue_buff_1_fun_fld; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_170 = ~exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_fsd :
    exe_stage_lsu_stQueue_buff_0_fun_fsd; // @[Store_queue.scala 107:{18,18} 54:21]
  wire  exe_stage_lsu_stQueue__GEN_171 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_fun_fsd :
    exe_stage_lsu_stQueue_buff_1_fun_fsd; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [5:0] exe_stage_lsu_stQueue__GEN_172 = ~exe_stage_lsu_stQueue_wr_ptr ?
    exe_stage_lsu_stQueue_io_enq_bits_param_rd0 : exe_stage_lsu_stQueue_buff_0_param_rd0; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [5:0] exe_stage_lsu_stQueue__GEN_173 = exe_stage_lsu_stQueue_wr_ptr ? exe_stage_lsu_stQueue_io_enq_bits_param_rd0
     : exe_stage_lsu_stQueue_buff_1_param_rd0; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_174 = ~exe_stage_lsu_stQueue_wr_ptr ?
    exe_stage_lsu_stQueue_io_enq_bits_param_dat_op1 : exe_stage_lsu_stQueue_buff_0_param_dat_op1; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_175 = exe_stage_lsu_stQueue_wr_ptr ?
    exe_stage_lsu_stQueue_io_enq_bits_param_dat_op1 : exe_stage_lsu_stQueue_buff_1_param_dat_op1; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_176 = ~exe_stage_lsu_stQueue_wr_ptr ?
    exe_stage_lsu_stQueue_io_enq_bits_param_dat_op2 : exe_stage_lsu_stQueue_buff_0_param_dat_op2; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_177 = exe_stage_lsu_stQueue_wr_ptr ?
    exe_stage_lsu_stQueue_io_enq_bits_param_dat_op2 : exe_stage_lsu_stQueue_buff_1_param_dat_op2; // @[Store_queue.scala 107:{18,18} 54:21]
  wire [1:0] exe_stage_lsu_stQueue__wr_ptr_reg_T_3 = exe_stage_lsu_stQueue_wr_ptr_reg + 2'h1; // @[Store_queue.scala 108:30]
  wire  exe_stage_lsu_stQueue__GEN_180 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_92 :
    exe_stage_lsu_stQueue_buff_0_fun_lb; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_181 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_93 :
    exe_stage_lsu_stQueue_buff_1_fun_lb; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_182 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_94 :
    exe_stage_lsu_stQueue_buff_0_fun_lh; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_183 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_95 :
    exe_stage_lsu_stQueue_buff_1_fun_lh; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_184 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_96 :
    exe_stage_lsu_stQueue_buff_0_fun_lw; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_185 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_97 :
    exe_stage_lsu_stQueue_buff_1_fun_lw; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_186 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_98 :
    exe_stage_lsu_stQueue_buff_0_fun_ld; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_187 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_99 :
    exe_stage_lsu_stQueue_buff_1_fun_ld; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_188 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_100 :
    exe_stage_lsu_stQueue_buff_0_fun_lbu; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_189 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_101 :
    exe_stage_lsu_stQueue_buff_1_fun_lbu; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_190 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_102 :
    exe_stage_lsu_stQueue_buff_0_fun_lhu; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_191 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_103 :
    exe_stage_lsu_stQueue_buff_1_fun_lhu; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_192 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_104 :
    exe_stage_lsu_stQueue_buff_0_fun_lwu; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_193 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_105 :
    exe_stage_lsu_stQueue_buff_1_fun_lwu; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_194 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_106 :
    exe_stage_lsu_stQueue_buff_0_fun_sb; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_195 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_107 :
    exe_stage_lsu_stQueue_buff_1_fun_sb; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_196 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_108 :
    exe_stage_lsu_stQueue_buff_0_fun_sh; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_197 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_109 :
    exe_stage_lsu_stQueue_buff_1_fun_sh; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_198 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_110 :
    exe_stage_lsu_stQueue_buff_0_fun_sw; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_199 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_111 :
    exe_stage_lsu_stQueue_buff_1_fun_sw; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_200 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_112 :
    exe_stage_lsu_stQueue_buff_0_fun_sd; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_201 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_113 :
    exe_stage_lsu_stQueue_buff_1_fun_sd; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_208 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_120 :
    exe_stage_lsu_stQueue_buff_0_fun_lr_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_209 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_121 :
    exe_stage_lsu_stQueue_buff_1_fun_lr_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_210 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_122 :
    exe_stage_lsu_stQueue_buff_0_fun_sc_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_211 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_123 :
    exe_stage_lsu_stQueue_buff_1_fun_sc_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_212 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_124 :
    exe_stage_lsu_stQueue_buff_0_fun_amoswap_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_213 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_125 :
    exe_stage_lsu_stQueue_buff_1_fun_amoswap_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_214 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_126 :
    exe_stage_lsu_stQueue_buff_0_fun_amoadd_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_215 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_127 :
    exe_stage_lsu_stQueue_buff_1_fun_amoadd_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_216 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_128 :
    exe_stage_lsu_stQueue_buff_0_fun_amoxor_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_217 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_129 :
    exe_stage_lsu_stQueue_buff_1_fun_amoxor_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_218 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_130 :
    exe_stage_lsu_stQueue_buff_0_fun_amoand_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_219 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_131 :
    exe_stage_lsu_stQueue_buff_1_fun_amoand_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_220 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_132 :
    exe_stage_lsu_stQueue_buff_0_fun_amoor_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_221 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_133 :
    exe_stage_lsu_stQueue_buff_1_fun_amoor_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_222 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_134 :
    exe_stage_lsu_stQueue_buff_0_fun_amomin_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_223 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_135 :
    exe_stage_lsu_stQueue_buff_1_fun_amomin_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_224 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_136 :
    exe_stage_lsu_stQueue_buff_0_fun_amomax_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_225 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_137 :
    exe_stage_lsu_stQueue_buff_1_fun_amomax_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_226 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_138 :
    exe_stage_lsu_stQueue_buff_0_fun_amominu_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_227 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_139 :
    exe_stage_lsu_stQueue_buff_1_fun_amominu_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_228 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_140 :
    exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_229 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_141 :
    exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_230 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_142 :
    exe_stage_lsu_stQueue_buff_0_fun_lr_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_231 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_143 :
    exe_stage_lsu_stQueue_buff_1_fun_lr_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_232 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_144 :
    exe_stage_lsu_stQueue_buff_0_fun_sc_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_233 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_145 :
    exe_stage_lsu_stQueue_buff_1_fun_sc_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_234 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_146 :
    exe_stage_lsu_stQueue_buff_0_fun_amoswap_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_235 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_147 :
    exe_stage_lsu_stQueue_buff_1_fun_amoswap_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_236 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_148 :
    exe_stage_lsu_stQueue_buff_0_fun_amoadd_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_237 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_149 :
    exe_stage_lsu_stQueue_buff_1_fun_amoadd_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_238 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_150 :
    exe_stage_lsu_stQueue_buff_0_fun_amoxor_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_239 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_151 :
    exe_stage_lsu_stQueue_buff_1_fun_amoxor_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_240 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_152 :
    exe_stage_lsu_stQueue_buff_0_fun_amoand_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_241 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_153 :
    exe_stage_lsu_stQueue_buff_1_fun_amoand_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_242 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_154 :
    exe_stage_lsu_stQueue_buff_0_fun_amoor_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_243 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_155 :
    exe_stage_lsu_stQueue_buff_1_fun_amoor_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_244 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_156 :
    exe_stage_lsu_stQueue_buff_0_fun_amomin_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_245 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_157 :
    exe_stage_lsu_stQueue_buff_1_fun_amomin_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_246 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_158 :
    exe_stage_lsu_stQueue_buff_0_fun_amomax_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_247 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_159 :
    exe_stage_lsu_stQueue_buff_1_fun_amomax_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_248 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_160 :
    exe_stage_lsu_stQueue_buff_0_fun_amominu_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_249 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_161 :
    exe_stage_lsu_stQueue_buff_1_fun_amominu_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_250 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_162 :
    exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_251 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_163 :
    exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_252 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_164 :
    exe_stage_lsu_stQueue_buff_0_fun_flw; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_253 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_165 :
    exe_stage_lsu_stQueue_buff_1_fun_flw; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_254 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_166 :
    exe_stage_lsu_stQueue_buff_0_fun_fsw; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_255 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_167 :
    exe_stage_lsu_stQueue_buff_1_fun_fsw; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_256 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_168 :
    exe_stage_lsu_stQueue_buff_0_fun_fld; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_257 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_169 :
    exe_stage_lsu_stQueue_buff_1_fun_fld; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_258 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_170 :
    exe_stage_lsu_stQueue_buff_0_fun_fsd; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_259 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_171 :
    exe_stage_lsu_stQueue_buff_1_fun_fsd; // @[Store_queue.scala 106:30 54:21]
  wire [5:0] exe_stage_lsu_stQueue__GEN_260 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_172 :
    exe_stage_lsu_stQueue_buff_0_param_rd0; // @[Store_queue.scala 106:30 54:21]
  wire [5:0] exe_stage_lsu_stQueue__GEN_261 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_173 :
    exe_stage_lsu_stQueue_buff_1_param_rd0; // @[Store_queue.scala 106:30 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_262 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_174 :
    exe_stage_lsu_stQueue_buff_0_param_dat_op1; // @[Store_queue.scala 106:30 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_263 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_175 :
    exe_stage_lsu_stQueue_buff_1_param_dat_op1; // @[Store_queue.scala 106:30 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_264 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_176 :
    exe_stage_lsu_stQueue_buff_0_param_dat_op2; // @[Store_queue.scala 106:30 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_265 = exe_stage_lsu_stQueue__T_5 ? exe_stage_lsu_stQueue__GEN_177 :
    exe_stage_lsu_stQueue_buff_1_param_dat_op2; // @[Store_queue.scala 106:30 54:21]
  wire  exe_stage_lsu_stQueue__GEN_270 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_lb :
    exe_stage_lsu_stQueue__GEN_180; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_271 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_lb :
    exe_stage_lsu_stQueue__GEN_181; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_272 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_lh :
    exe_stage_lsu_stQueue__GEN_182; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_273 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_lh :
    exe_stage_lsu_stQueue__GEN_183; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_274 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_lw :
    exe_stage_lsu_stQueue__GEN_184; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_275 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_lw :
    exe_stage_lsu_stQueue__GEN_185; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_276 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_ld :
    exe_stage_lsu_stQueue__GEN_186; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_277 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_ld :
    exe_stage_lsu_stQueue__GEN_187; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_278 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_lbu :
    exe_stage_lsu_stQueue__GEN_188; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_279 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_lbu :
    exe_stage_lsu_stQueue__GEN_189; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_280 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_lhu :
    exe_stage_lsu_stQueue__GEN_190; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_281 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_lhu :
    exe_stage_lsu_stQueue__GEN_191; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_282 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_lwu :
    exe_stage_lsu_stQueue__GEN_192; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_283 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_lwu :
    exe_stage_lsu_stQueue__GEN_193; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_284 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_sb :
    exe_stage_lsu_stQueue__GEN_194; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_285 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_sb :
    exe_stage_lsu_stQueue__GEN_195; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_286 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_sh :
    exe_stage_lsu_stQueue__GEN_196; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_287 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_sh :
    exe_stage_lsu_stQueue__GEN_197; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_288 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_sw :
    exe_stage_lsu_stQueue__GEN_198; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_289 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_sw :
    exe_stage_lsu_stQueue__GEN_199; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_290 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_sd :
    exe_stage_lsu_stQueue__GEN_200; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_291 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_sd :
    exe_stage_lsu_stQueue__GEN_201; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_298 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_lr_w :
    exe_stage_lsu_stQueue__GEN_208; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_299 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_lr_w :
    exe_stage_lsu_stQueue__GEN_209; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_300 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_sc_w :
    exe_stage_lsu_stQueue__GEN_210; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_301 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_sc_w :
    exe_stage_lsu_stQueue__GEN_211; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_302 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoswap_w :
    exe_stage_lsu_stQueue__GEN_212; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_303 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoswap_w :
    exe_stage_lsu_stQueue__GEN_213; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_304 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoadd_w :
    exe_stage_lsu_stQueue__GEN_214; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_305 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoadd_w :
    exe_stage_lsu_stQueue__GEN_215; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_306 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoxor_w :
    exe_stage_lsu_stQueue__GEN_216; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_307 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoxor_w :
    exe_stage_lsu_stQueue__GEN_217; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_308 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoand_w :
    exe_stage_lsu_stQueue__GEN_218; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_309 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoand_w :
    exe_stage_lsu_stQueue__GEN_219; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_310 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoor_w :
    exe_stage_lsu_stQueue__GEN_220; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_311 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoor_w :
    exe_stage_lsu_stQueue__GEN_221; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_312 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amomin_w :
    exe_stage_lsu_stQueue__GEN_222; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_313 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amomin_w :
    exe_stage_lsu_stQueue__GEN_223; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_314 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amomax_w :
    exe_stage_lsu_stQueue__GEN_224; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_315 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amomax_w :
    exe_stage_lsu_stQueue__GEN_225; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_316 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amominu_w :
    exe_stage_lsu_stQueue__GEN_226; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_317 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amominu_w :
    exe_stage_lsu_stQueue__GEN_227; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_318 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w :
    exe_stage_lsu_stQueue__GEN_228; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_319 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w :
    exe_stage_lsu_stQueue__GEN_229; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_320 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_lr_d :
    exe_stage_lsu_stQueue__GEN_230; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_321 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_lr_d :
    exe_stage_lsu_stQueue__GEN_231; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_322 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_sc_d :
    exe_stage_lsu_stQueue__GEN_232; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_323 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_sc_d :
    exe_stage_lsu_stQueue__GEN_233; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_324 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoswap_d :
    exe_stage_lsu_stQueue__GEN_234; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_325 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoswap_d :
    exe_stage_lsu_stQueue__GEN_235; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_326 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoadd_d :
    exe_stage_lsu_stQueue__GEN_236; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_327 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoadd_d :
    exe_stage_lsu_stQueue__GEN_237; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_328 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoxor_d :
    exe_stage_lsu_stQueue__GEN_238; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_329 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoxor_d :
    exe_stage_lsu_stQueue__GEN_239; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_330 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoand_d :
    exe_stage_lsu_stQueue__GEN_240; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_331 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoand_d :
    exe_stage_lsu_stQueue__GEN_241; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_332 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amoor_d :
    exe_stage_lsu_stQueue__GEN_242; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_333 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amoor_d :
    exe_stage_lsu_stQueue__GEN_243; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_334 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amomin_d :
    exe_stage_lsu_stQueue__GEN_244; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_335 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amomin_d :
    exe_stage_lsu_stQueue__GEN_245; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_336 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amomax_d :
    exe_stage_lsu_stQueue__GEN_246; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_337 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amomax_d :
    exe_stage_lsu_stQueue__GEN_247; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_338 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amominu_d :
    exe_stage_lsu_stQueue__GEN_248; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_339 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amominu_d :
    exe_stage_lsu_stQueue__GEN_249; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_340 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d :
    exe_stage_lsu_stQueue__GEN_250; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_341 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d :
    exe_stage_lsu_stQueue__GEN_251; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_342 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_flw :
    exe_stage_lsu_stQueue__GEN_252; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_343 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_flw :
    exe_stage_lsu_stQueue__GEN_253; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_344 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_fsw :
    exe_stage_lsu_stQueue__GEN_254; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_345 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_fsw :
    exe_stage_lsu_stQueue__GEN_255; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_346 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_fld :
    exe_stage_lsu_stQueue__GEN_256; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_347 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_fld :
    exe_stage_lsu_stQueue__GEN_257; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_348 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_fun_fsd :
    exe_stage_lsu_stQueue__GEN_258; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__GEN_349 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_fun_fsd :
    exe_stage_lsu_stQueue__GEN_259; // @[Store_queue.scala 94:20 54:21]
  wire [5:0] exe_stage_lsu_stQueue__GEN_350 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_0_param_rd0 :
    exe_stage_lsu_stQueue__GEN_260; // @[Store_queue.scala 94:20 54:21]
  wire [5:0] exe_stage_lsu_stQueue__GEN_351 = exe_stage_lsu_stQueue_io_flush ? exe_stage_lsu_stQueue_buff_1_param_rd0 :
    exe_stage_lsu_stQueue__GEN_261; // @[Store_queue.scala 94:20 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_352 = exe_stage_lsu_stQueue_io_flush ?
    exe_stage_lsu_stQueue_buff_0_param_dat_op1 : exe_stage_lsu_stQueue__GEN_262; // @[Store_queue.scala 94:20 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_353 = exe_stage_lsu_stQueue_io_flush ?
    exe_stage_lsu_stQueue_buff_1_param_dat_op1 : exe_stage_lsu_stQueue__GEN_263; // @[Store_queue.scala 94:20 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_354 = exe_stage_lsu_stQueue_io_flush ?
    exe_stage_lsu_stQueue_buff_0_param_dat_op2 : exe_stage_lsu_stQueue__GEN_264; // @[Store_queue.scala 94:20 54:21]
  wire [63:0] exe_stage_lsu_stQueue__GEN_355 = exe_stage_lsu_stQueue_io_flush ?
    exe_stage_lsu_stQueue_buff_1_param_dat_op2 : exe_stage_lsu_stQueue__GEN_265; // @[Store_queue.scala 94:20 54:21]
  wire  exe_stage_lsu_stQueue__T_6 = exe_stage_lsu_stQueue_io_deq_ready & exe_stage_lsu_stQueue_io_deq_valid; // @[Decoupled.scala 52:35]
  wire [1:0] exe_stage_lsu_stQueue__rd_ptr_reg_T_1 = exe_stage_lsu_stQueue_rd_ptr_reg + 2'h1; // @[Store_queue.scala 112:30]
  wire  exe_stage_lsu_stQueue__T_7 = ~exe_stage_lsu_stQueue_is_amo; // @[Store_queue.scala 129:15]
  wire  exe_stage_lsu_stQueue__T_9 = ~exe_stage_lsu_stQueue_reset; // @[Store_queue.scala 129:13]
  wire  exe_stage_lsu_stQueue__T_10 = ~exe_stage_lsu_stQueue__T_7; // @[Store_queue.scala 129:13]
  wire  exe_stage_lsu_stQueue__T_11 = exe_stage_lsu_stQueue_cm_ptr_reg != exe_stage_lsu_stQueue_wr_ptr_reg; // @[Store_queue.scala 130:26]
  wire  exe_stage_lsu_stQueue__T_14 = ~exe_stage_lsu_stQueue__T_11; // @[Store_queue.scala 130:13]
  wire  exe_stage_lsu_stQueue__T_19 = exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 & exe_stage_lsu_stQueue__T_1; // @[Store_queue.scala 133:37]
  wire  exe_stage_lsu_stQueue__T_20 = ~exe_stage_lsu_stQueue__T_19; // @[Store_queue.scala 133:15]
  wire  exe_stage_lsu_stQueue__T_23 = ~exe_stage_lsu_stQueue__T_20; // @[Store_queue.scala 133:13]
  wire  exe_stage_lsu_stQueue__io_is_empty_T = exe_stage_lsu_stQueue_cm_ptr_reg == exe_stage_lsu_stQueue_wr_ptr_reg; // @[Store_queue.scala 141:32]
  wire  exe_stage_lsu_stQueue__T_30 = exe_stage_lsu_stQueue__full_T_1 != exe_stage_lsu_stQueue__full_T; // @[Store_queue.scala 148:28]
  wire  exe_stage_lsu_stQueue__T_31 = exe_stage_lsu_stQueue_rd_ptr >= exe_stage_lsu_stQueue_wr_ptr; // @[Store_queue.scala 149:22]
  wire  exe_stage_lsu_stQueue__T_34 = ~exe_stage_lsu_stQueue__T_31; // @[Store_queue.scala 149:13]
  wire [2:0] exe_stage_lsu_stQueue__ro_ptr_T = {{1'd0}, exe_stage_lsu_stQueue_rd_ptr_reg}; // @[Store_queue.scala 151:34]
  wire [1:0] exe_stage_lsu_stQueue__ro_ptr_T_1 = exe_stage_lsu_stQueue__ro_ptr_T[1:0]; // @[Store_queue.scala 151:34]
  wire  exe_stage_lsu_stQueue_ro_ptr = exe_stage_lsu_stQueue__ro_ptr_T_1[0]; // @[Store_queue.scala 151:40]
  wire  exe_stage_lsu_stQueue__T_35 = exe_stage_lsu_stQueue_ro_ptr >= exe_stage_lsu_stQueue_rd_ptr; // @[Store_queue.scala 152:23]
  wire  exe_stage_lsu_stQueue__T_36 = exe_stage_lsu_stQueue_ro_ptr < exe_stage_lsu_stQueue_wr_ptr; // @[Store_queue.scala 152:43]
  wire  exe_stage_lsu_stQueue__T_37 = exe_stage_lsu_stQueue__T_35 | exe_stage_lsu_stQueue__T_36; // @[Store_queue.scala 152:33]
  wire [63:0] exe_stage_lsu_stQueue__GEN_538 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_param_dat_op1
     : exe_stage_lsu_stQueue_buff_0_param_dat_op1; // @[Store_queue.scala 152:{83,83}]
  wire [28:0] exe_stage_lsu_stQueue__T_38 = exe_stage_lsu_stQueue__GEN_538[31:3]; // @[Store_queue.scala 152:83]
  wire [28:0] exe_stage_lsu_stQueue__T_39 = exe_stage_lsu_stQueue_io_overlapReq_bits_paddr[31:3]; // @[Store_queue.scala 152:122]
  wire  exe_stage_lsu_stQueue__T_40 = exe_stage_lsu_stQueue__T_38 == exe_stage_lsu_stQueue__T_39; // @[Store_queue.scala 152:94]
  wire  exe_stage_lsu_stQueue__T_41 = exe_stage_lsu_stQueue__T_37 & exe_stage_lsu_stQueue__T_40; // @[Store_queue.scala 152:53]
  wire  exe_stage_lsu_stQueue__GEN_540 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lb :
    exe_stage_lsu_stQueue_buff_0_fun_lb; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_542 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lh :
    exe_stage_lsu_stQueue_buff_0_fun_lh; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_544 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lw :
    exe_stage_lsu_stQueue_buff_0_fun_lw; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_546 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_ld :
    exe_stage_lsu_stQueue_buff_0_fun_ld; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_548 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lbu :
    exe_stage_lsu_stQueue_buff_0_fun_lbu; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_550 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lhu :
    exe_stage_lsu_stQueue_buff_0_fun_lhu; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_552 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lwu :
    exe_stage_lsu_stQueue_buff_0_fun_lwu; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_554 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sb :
    exe_stage_lsu_stQueue_buff_0_fun_sb; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_556 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sh :
    exe_stage_lsu_stQueue_buff_0_fun_sh; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_558 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sw :
    exe_stage_lsu_stQueue_buff_0_fun_sw; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_560 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sd :
    exe_stage_lsu_stQueue_buff_0_fun_sd; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_568 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lr_w :
    exe_stage_lsu_stQueue_buff_0_fun_lr_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_570 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sc_w :
    exe_stage_lsu_stQueue_buff_0_fun_sc_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_572 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoswap_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoswap_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_574 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoadd_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoadd_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_576 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoxor_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoxor_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_578 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoand_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoand_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_580 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoor_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoor_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_582 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomin_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomin_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_584 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomax_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomax_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_586 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amominu_w :
    exe_stage_lsu_stQueue_buff_0_fun_amominu_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_588 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_590 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_lr_d :
    exe_stage_lsu_stQueue_buff_0_fun_lr_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_592 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_sc_d :
    exe_stage_lsu_stQueue_buff_0_fun_sc_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_594 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoswap_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoswap_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_596 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoadd_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoadd_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_598 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoxor_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoxor_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_600 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoand_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoand_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_602 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amoor_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoor_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_604 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomin_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomin_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_606 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomax_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomax_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_608 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amominu_d :
    exe_stage_lsu_stQueue_buff_0_fun_amominu_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_610 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_612 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_flw :
    exe_stage_lsu_stQueue_buff_0_fun_flw; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_614 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_fsw :
    exe_stage_lsu_stQueue_buff_0_fun_fsw; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_616 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_fld :
    exe_stage_lsu_stQueue_buff_0_fun_fld; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_618 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_fun_fsd :
    exe_stage_lsu_stQueue_buff_0_fun_fsd; // @[Store_queue.scala 153:{27,27}]
  wire [63:0] exe_stage_lsu_stQueue__GEN_622 = exe_stage_lsu_stQueue_ro_ptr ? exe_stage_lsu_stQueue_buff_1_param_dat_op2
     : exe_stage_lsu_stQueue_buff_0_param_dat_op2; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__T_42 = exe_stage_lsu_stQueue__GEN_572 | exe_stage_lsu_stQueue__GEN_574; // @[riscv_isa.scala 148:15]
  wire  exe_stage_lsu_stQueue__T_43 = exe_stage_lsu_stQueue__T_42 | exe_stage_lsu_stQueue__GEN_576; // @[riscv_isa.scala 148:26]
  wire  exe_stage_lsu_stQueue__T_44 = exe_stage_lsu_stQueue__T_43 | exe_stage_lsu_stQueue__GEN_578; // @[riscv_isa.scala 148:37]
  wire  exe_stage_lsu_stQueue__T_45 = exe_stage_lsu_stQueue__T_44 | exe_stage_lsu_stQueue__GEN_580; // @[riscv_isa.scala 148:48]
  wire  exe_stage_lsu_stQueue__T_46 = exe_stage_lsu_stQueue__T_45 | exe_stage_lsu_stQueue__GEN_582; // @[riscv_isa.scala 148:58]
  wire  exe_stage_lsu_stQueue__T_47 = exe_stage_lsu_stQueue__T_46 | exe_stage_lsu_stQueue__GEN_584; // @[riscv_isa.scala 148:69]
  wire  exe_stage_lsu_stQueue__T_48 = exe_stage_lsu_stQueue__T_47 | exe_stage_lsu_stQueue__GEN_586; // @[riscv_isa.scala 148:80]
  wire  exe_stage_lsu_stQueue__T_49 = exe_stage_lsu_stQueue__T_48 | exe_stage_lsu_stQueue__GEN_588; // @[riscv_isa.scala 148:92]
  wire  exe_stage_lsu_stQueue__T_50 = exe_stage_lsu_stQueue__T_49 | exe_stage_lsu_stQueue__GEN_594; // @[riscv_isa.scala 148:104]
  wire  exe_stage_lsu_stQueue__T_51 = exe_stage_lsu_stQueue__T_50 | exe_stage_lsu_stQueue__GEN_596; // @[riscv_isa.scala 148:116]
  wire  exe_stage_lsu_stQueue__T_52 = exe_stage_lsu_stQueue__T_51 | exe_stage_lsu_stQueue__GEN_598; // @[riscv_isa.scala 148:127]
  wire  exe_stage_lsu_stQueue__T_53 = exe_stage_lsu_stQueue__T_52 | exe_stage_lsu_stQueue__GEN_600; // @[riscv_isa.scala 148:138]
  wire  exe_stage_lsu_stQueue__T_54 = exe_stage_lsu_stQueue__T_53 | exe_stage_lsu_stQueue__GEN_602; // @[riscv_isa.scala 148:149]
  wire  exe_stage_lsu_stQueue__T_55 = exe_stage_lsu_stQueue__T_54 | exe_stage_lsu_stQueue__GEN_604; // @[riscv_isa.scala 148:159]
  wire  exe_stage_lsu_stQueue__T_56 = exe_stage_lsu_stQueue__T_55 | exe_stage_lsu_stQueue__GEN_606; // @[riscv_isa.scala 148:170]
  wire  exe_stage_lsu_stQueue__T_57 = exe_stage_lsu_stQueue__T_56 | exe_stage_lsu_stQueue__GEN_608; // @[riscv_isa.scala 148:181]
  wire  exe_stage_lsu_stQueue__T_58 = exe_stage_lsu_stQueue__T_57 | exe_stage_lsu_stQueue__GEN_610; // @[riscv_isa.scala 148:193]
  wire  exe_stage_lsu_stQueue__T_59 = exe_stage_lsu_stQueue__GEN_592 | exe_stage_lsu_stQueue__GEN_570; // @[riscv_isa.scala 140:20]
  wire  exe_stage_lsu_stQueue__T_60 = exe_stage_lsu_stQueue__T_58 | exe_stage_lsu_stQueue__T_59; // @[riscv_isa.scala 148:205]
  wire  exe_stage_lsu_stQueue__GEN_625 = exe_stage_lsu_stQueue__T_60 ? 1'h0 : exe_stage_lsu_stQueue_io_overlapReq_valid; // @[Store_queue.scala 146:26 155:{43,66}]
  wire  exe_stage_lsu_stQueue__GEN_626 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_540; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_627 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_542; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_628 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_544; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_629 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_546; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_630 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_548; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_631 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_550; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_632 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_552; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_633 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_554; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_634 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_556; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_635 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_558; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_636 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_560; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_640 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_568; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_641 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_570; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_642 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_572; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_643 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_574; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_644 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_576; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_645 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_578; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_646 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_580; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_647 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_582; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_648 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_584; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_649 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_586; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_650 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_588; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_651 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_590; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_652 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_592; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_653 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_594; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_654 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_596; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_655 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_598; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_656 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_600; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_657 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_602; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_658 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_604; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_659 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_606; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_660 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_608; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_661 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_610; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_662 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_612; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_663 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_614; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_664 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_616; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_665 = exe_stage_lsu_stQueue__T_41 & exe_stage_lsu_stQueue__GEN_618; // @[Store_queue.scala 152:136 153:27 158:27]
  wire [63:0] exe_stage_lsu_stQueue__GEN_667 = exe_stage_lsu_stQueue__T_41 ? exe_stage_lsu_stQueue__GEN_538 : 64'h0; // @[Store_queue.scala 152:136 153:27 158:27]
  wire [63:0] exe_stage_lsu_stQueue__GEN_668 = exe_stage_lsu_stQueue__T_41 ? exe_stage_lsu_stQueue__GEN_622 : 64'h0; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_670 = exe_stage_lsu_stQueue__T_41 ? exe_stage_lsu_stQueue__GEN_625 :
    exe_stage_lsu_stQueue_io_overlapReq_valid; // @[Store_queue.scala 152:136 146:26]
  wire  exe_stage_lsu_stQueue_ro_ptr_1 = exe_stage_lsu_stQueue__rd_ptr_reg_T_1[0]; // @[Store_queue.scala 151:40]
  wire  exe_stage_lsu_stQueue__T_61 = exe_stage_lsu_stQueue_ro_ptr_1 >= exe_stage_lsu_stQueue_rd_ptr; // @[Store_queue.scala 152:23]
  wire  exe_stage_lsu_stQueue__T_62 = exe_stage_lsu_stQueue_ro_ptr_1 < exe_stage_lsu_stQueue_wr_ptr; // @[Store_queue.scala 152:43]
  wire  exe_stage_lsu_stQueue__T_63 = exe_stage_lsu_stQueue__T_61 | exe_stage_lsu_stQueue__T_62; // @[Store_queue.scala 152:33]
  wire [63:0] exe_stage_lsu_stQueue__GEN_672 = exe_stage_lsu_stQueue_ro_ptr_1 ?
    exe_stage_lsu_stQueue_buff_1_param_dat_op1 : exe_stage_lsu_stQueue_buff_0_param_dat_op1; // @[Store_queue.scala 152:{83,83}]
  wire [28:0] exe_stage_lsu_stQueue__T_64 = exe_stage_lsu_stQueue__GEN_672[31:3]; // @[Store_queue.scala 152:83]
  wire  exe_stage_lsu_stQueue__T_66 = exe_stage_lsu_stQueue__T_64 == exe_stage_lsu_stQueue__T_39; // @[Store_queue.scala 152:94]
  wire  exe_stage_lsu_stQueue__T_67 = exe_stage_lsu_stQueue__T_63 & exe_stage_lsu_stQueue__T_66; // @[Store_queue.scala 152:53]
  wire  exe_stage_lsu_stQueue__GEN_674 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_lb :
    exe_stage_lsu_stQueue_buff_0_fun_lb; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_676 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_lh :
    exe_stage_lsu_stQueue_buff_0_fun_lh; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_678 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_lw :
    exe_stage_lsu_stQueue_buff_0_fun_lw; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_680 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_ld :
    exe_stage_lsu_stQueue_buff_0_fun_ld; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_682 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_lbu :
    exe_stage_lsu_stQueue_buff_0_fun_lbu; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_684 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_lhu :
    exe_stage_lsu_stQueue_buff_0_fun_lhu; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_686 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_lwu :
    exe_stage_lsu_stQueue_buff_0_fun_lwu; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_688 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_sb :
    exe_stage_lsu_stQueue_buff_0_fun_sb; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_690 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_sh :
    exe_stage_lsu_stQueue_buff_0_fun_sh; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_692 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_sw :
    exe_stage_lsu_stQueue_buff_0_fun_sw; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_694 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_sd :
    exe_stage_lsu_stQueue_buff_0_fun_sd; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_702 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_lr_w :
    exe_stage_lsu_stQueue_buff_0_fun_lr_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_704 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_sc_w :
    exe_stage_lsu_stQueue_buff_0_fun_sc_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_706 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoswap_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoswap_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_708 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoadd_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoadd_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_710 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoxor_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoxor_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_712 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoand_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoand_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_714 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoor_w :
    exe_stage_lsu_stQueue_buff_0_fun_amoor_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_716 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amomin_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomin_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_718 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amomax_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomax_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_720 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amominu_w :
    exe_stage_lsu_stQueue_buff_0_fun_amominu_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_722 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w :
    exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_724 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_lr_d :
    exe_stage_lsu_stQueue_buff_0_fun_lr_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_726 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_sc_d :
    exe_stage_lsu_stQueue_buff_0_fun_sc_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_728 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoswap_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoswap_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_730 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoadd_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoadd_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_732 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoxor_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoxor_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_734 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoand_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoand_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_736 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amoor_d :
    exe_stage_lsu_stQueue_buff_0_fun_amoor_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_738 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amomin_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomin_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_740 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amomax_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomax_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_742 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amominu_d :
    exe_stage_lsu_stQueue_buff_0_fun_amominu_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_744 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d :
    exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_746 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_flw :
    exe_stage_lsu_stQueue_buff_0_fun_flw; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_748 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_fsw :
    exe_stage_lsu_stQueue_buff_0_fun_fsw; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_750 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_fld :
    exe_stage_lsu_stQueue_buff_0_fun_fld; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__GEN_752 = exe_stage_lsu_stQueue_ro_ptr_1 ? exe_stage_lsu_stQueue_buff_1_fun_fsd :
    exe_stage_lsu_stQueue_buff_0_fun_fsd; // @[Store_queue.scala 153:{27,27}]
  wire [63:0] exe_stage_lsu_stQueue__GEN_756 = exe_stage_lsu_stQueue_ro_ptr_1 ?
    exe_stage_lsu_stQueue_buff_1_param_dat_op2 : exe_stage_lsu_stQueue_buff_0_param_dat_op2; // @[Store_queue.scala 153:{27,27}]
  wire  exe_stage_lsu_stQueue__T_68 = exe_stage_lsu_stQueue__GEN_706 | exe_stage_lsu_stQueue__GEN_708; // @[riscv_isa.scala 148:15]
  wire  exe_stage_lsu_stQueue__T_69 = exe_stage_lsu_stQueue__T_68 | exe_stage_lsu_stQueue__GEN_710; // @[riscv_isa.scala 148:26]
  wire  exe_stage_lsu_stQueue__T_70 = exe_stage_lsu_stQueue__T_69 | exe_stage_lsu_stQueue__GEN_712; // @[riscv_isa.scala 148:37]
  wire  exe_stage_lsu_stQueue__T_71 = exe_stage_lsu_stQueue__T_70 | exe_stage_lsu_stQueue__GEN_714; // @[riscv_isa.scala 148:48]
  wire  exe_stage_lsu_stQueue__T_72 = exe_stage_lsu_stQueue__T_71 | exe_stage_lsu_stQueue__GEN_716; // @[riscv_isa.scala 148:58]
  wire  exe_stage_lsu_stQueue__T_73 = exe_stage_lsu_stQueue__T_72 | exe_stage_lsu_stQueue__GEN_718; // @[riscv_isa.scala 148:69]
  wire  exe_stage_lsu_stQueue__T_74 = exe_stage_lsu_stQueue__T_73 | exe_stage_lsu_stQueue__GEN_720; // @[riscv_isa.scala 148:80]
  wire  exe_stage_lsu_stQueue__T_75 = exe_stage_lsu_stQueue__T_74 | exe_stage_lsu_stQueue__GEN_722; // @[riscv_isa.scala 148:92]
  wire  exe_stage_lsu_stQueue__T_76 = exe_stage_lsu_stQueue__T_75 | exe_stage_lsu_stQueue__GEN_728; // @[riscv_isa.scala 148:104]
  wire  exe_stage_lsu_stQueue__T_77 = exe_stage_lsu_stQueue__T_76 | exe_stage_lsu_stQueue__GEN_730; // @[riscv_isa.scala 148:116]
  wire  exe_stage_lsu_stQueue__T_78 = exe_stage_lsu_stQueue__T_77 | exe_stage_lsu_stQueue__GEN_732; // @[riscv_isa.scala 148:127]
  wire  exe_stage_lsu_stQueue__T_79 = exe_stage_lsu_stQueue__T_78 | exe_stage_lsu_stQueue__GEN_734; // @[riscv_isa.scala 148:138]
  wire  exe_stage_lsu_stQueue__T_80 = exe_stage_lsu_stQueue__T_79 | exe_stage_lsu_stQueue__GEN_736; // @[riscv_isa.scala 148:149]
  wire  exe_stage_lsu_stQueue__T_81 = exe_stage_lsu_stQueue__T_80 | exe_stage_lsu_stQueue__GEN_738; // @[riscv_isa.scala 148:159]
  wire  exe_stage_lsu_stQueue__T_82 = exe_stage_lsu_stQueue__T_81 | exe_stage_lsu_stQueue__GEN_740; // @[riscv_isa.scala 148:170]
  wire  exe_stage_lsu_stQueue__T_83 = exe_stage_lsu_stQueue__T_82 | exe_stage_lsu_stQueue__GEN_742; // @[riscv_isa.scala 148:181]
  wire  exe_stage_lsu_stQueue__T_84 = exe_stage_lsu_stQueue__T_83 | exe_stage_lsu_stQueue__GEN_744; // @[riscv_isa.scala 148:193]
  wire  exe_stage_lsu_stQueue__T_85 = exe_stage_lsu_stQueue__GEN_726 | exe_stage_lsu_stQueue__GEN_704; // @[riscv_isa.scala 140:20]
  wire  exe_stage_lsu_stQueue__T_86 = exe_stage_lsu_stQueue__T_84 | exe_stage_lsu_stQueue__T_85; // @[riscv_isa.scala 148:205]
  wire  exe_stage_lsu_stQueue__GEN_759 = exe_stage_lsu_stQueue__T_86 ? 1'h0 : exe_stage_lsu_stQueue__GEN_670; // @[Store_queue.scala 155:{43,66}]
  wire  exe_stage_lsu_stQueue__GEN_760 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_674; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_761 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_676; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_762 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_678; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_763 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_680; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_764 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_682; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_765 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_684; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_766 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_686; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_767 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_688; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_768 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_690; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_769 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_692; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_770 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_694; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_774 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_702; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_775 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_704; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_776 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_706; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_777 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_708; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_778 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_710; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_779 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_712; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_780 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_714; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_781 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_716; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_782 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_718; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_783 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_720; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_784 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_722; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_785 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_724; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_786 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_726; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_787 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_728; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_788 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_730; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_789 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_732; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_790 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_734; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_791 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_736; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_792 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_738; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_793 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_740; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_794 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_742; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_795 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_744; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_796 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_746; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_797 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_748; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_798 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_750; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_799 = exe_stage_lsu_stQueue__T_67 & exe_stage_lsu_stQueue__GEN_752; // @[Store_queue.scala 152:136 153:27 158:27]
  wire [63:0] exe_stage_lsu_stQueue__GEN_801 = exe_stage_lsu_stQueue__T_67 ? exe_stage_lsu_stQueue__GEN_672 : 64'h0; // @[Store_queue.scala 152:136 153:27 158:27]
  wire [63:0] exe_stage_lsu_stQueue__GEN_802 = exe_stage_lsu_stQueue__T_67 ? exe_stage_lsu_stQueue__GEN_756 : 64'h0; // @[Store_queue.scala 152:136 153:27 158:27]
  wire  exe_stage_lsu_stQueue__GEN_804 = exe_stage_lsu_stQueue__T_67 ? exe_stage_lsu_stQueue__GEN_759 :
    exe_stage_lsu_stQueue__GEN_670; // @[Store_queue.scala 152:136]
  wire  exe_stage_lsu_stQueue__T_87 = exe_stage_lsu_stQueue_rd_ptr <= exe_stage_lsu_stQueue_wr_ptr; // @[Store_queue.scala 162:22]
  wire  exe_stage_lsu_stQueue__T_90 = ~exe_stage_lsu_stQueue__T_87; // @[Store_queue.scala 162:13]
  wire  exe_stage_lsu_stQueue__T_93 = exe_stage_lsu_stQueue__T_35 & exe_stage_lsu_stQueue__T_36; // @[Store_queue.scala 165:32]
  wire  exe_stage_lsu_stQueue__T_97 = exe_stage_lsu_stQueue__T_93 & exe_stage_lsu_stQueue__T_40; // @[Store_queue.scala 165:51]
  wire  exe_stage_lsu_stQueue__GEN_894 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_540; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_895 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_542; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_896 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_544; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_897 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_546; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_898 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_548; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_899 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_550; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_900 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_552; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_901 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_554; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_902 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_556; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_903 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_558; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_904 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_560; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_908 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_568; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_909 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_570; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_910 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_572; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_911 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_574; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_912 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_576; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_913 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_578; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_914 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_580; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_915 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_582; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_916 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_584; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_917 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_586; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_918 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_588; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_919 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_590; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_920 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_592; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_921 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_594; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_922 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_596; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_923 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_598; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_924 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_600; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_925 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_602; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_926 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_604; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_927 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_606; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_928 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_608; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_929 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_610; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_930 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_612; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_931 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_614; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_932 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_616; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_933 = exe_stage_lsu_stQueue__T_97 & exe_stage_lsu_stQueue__GEN_618; // @[Store_queue.scala 165:134 166:27 171:27]
  wire [63:0] exe_stage_lsu_stQueue__GEN_935 = exe_stage_lsu_stQueue__T_97 ? exe_stage_lsu_stQueue__GEN_538 : 64'h0; // @[Store_queue.scala 165:134 166:27 171:27]
  wire [63:0] exe_stage_lsu_stQueue__GEN_936 = exe_stage_lsu_stQueue__T_97 ? exe_stage_lsu_stQueue__GEN_622 : 64'h0; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_938 = exe_stage_lsu_stQueue__T_97 ? exe_stage_lsu_stQueue__GEN_625 :
    exe_stage_lsu_stQueue_io_overlapReq_valid; // @[Store_queue.scala 165:134 146:26]
  wire  exe_stage_lsu_stQueue__T_119 = exe_stage_lsu_stQueue__T_61 & exe_stage_lsu_stQueue__T_62; // @[Store_queue.scala 165:32]
  wire  exe_stage_lsu_stQueue__T_123 = exe_stage_lsu_stQueue__T_119 & exe_stage_lsu_stQueue__T_66; // @[Store_queue.scala 165:51]
  wire  exe_stage_lsu_stQueue__GEN_1027 = exe_stage_lsu_stQueue__T_86 ? 1'h0 : exe_stage_lsu_stQueue__GEN_938; // @[Store_queue.scala 168:{43,66}]
  wire  exe_stage_lsu_stQueue__GEN_1028 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_674; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1029 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_676; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1030 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_678; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1031 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_680; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1032 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_682; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1033 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_684; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1034 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_686; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1035 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_688; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1036 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_690; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1037 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_692; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1038 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_694; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1042 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_702; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1043 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_704; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1044 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_706; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1045 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_708; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1046 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_710; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1047 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_712; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1048 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_714; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1049 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_716; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1050 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_718; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1051 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_720; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1052 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_722; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1053 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_724; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1054 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_726; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1055 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_728; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1056 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_730; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1057 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_732; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1058 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_734; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1059 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_736; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1060 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_738; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1061 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_740; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1062 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_742; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1063 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_744; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1064 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_746; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1065 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_748; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1066 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_750; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1067 = exe_stage_lsu_stQueue__T_123 & exe_stage_lsu_stQueue__GEN_752; // @[Store_queue.scala 165:134 166:27 171:27]
  wire [63:0] exe_stage_lsu_stQueue__GEN_1069 = exe_stage_lsu_stQueue__T_123 ? exe_stage_lsu_stQueue__GEN_672 : 64'h0; // @[Store_queue.scala 165:134 166:27 171:27]
  wire [63:0] exe_stage_lsu_stQueue__GEN_1070 = exe_stage_lsu_stQueue__T_123 ? exe_stage_lsu_stQueue__GEN_756 : 64'h0; // @[Store_queue.scala 165:134 166:27 171:27]
  wire  exe_stage_lsu_stQueue__GEN_1072 = exe_stage_lsu_stQueue__T_123 ? exe_stage_lsu_stQueue__GEN_1027 :
    exe_stage_lsu_stQueue__GEN_938; // @[Store_queue.scala 165:134]
  wire  exe_stage_lsu_stQueue__GEN_1073 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_626 :
    exe_stage_lsu_stQueue__GEN_894; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1074 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_627 :
    exe_stage_lsu_stQueue__GEN_895; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1075 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_628 :
    exe_stage_lsu_stQueue__GEN_896; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1076 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_629 :
    exe_stage_lsu_stQueue__GEN_897; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1077 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_630 :
    exe_stage_lsu_stQueue__GEN_898; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1078 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_631 :
    exe_stage_lsu_stQueue__GEN_899; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1079 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_632 :
    exe_stage_lsu_stQueue__GEN_900; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1080 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_633 :
    exe_stage_lsu_stQueue__GEN_901; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1081 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_634 :
    exe_stage_lsu_stQueue__GEN_902; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1082 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_635 :
    exe_stage_lsu_stQueue__GEN_903; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1083 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_636 :
    exe_stage_lsu_stQueue__GEN_904; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1087 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_640 :
    exe_stage_lsu_stQueue__GEN_908; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1088 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_641 :
    exe_stage_lsu_stQueue__GEN_909; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1089 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_642 :
    exe_stage_lsu_stQueue__GEN_910; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1090 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_643 :
    exe_stage_lsu_stQueue__GEN_911; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1091 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_644 :
    exe_stage_lsu_stQueue__GEN_912; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1092 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_645 :
    exe_stage_lsu_stQueue__GEN_913; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1093 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_646 :
    exe_stage_lsu_stQueue__GEN_914; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1094 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_647 :
    exe_stage_lsu_stQueue__GEN_915; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1095 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_648 :
    exe_stage_lsu_stQueue__GEN_916; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1096 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_649 :
    exe_stage_lsu_stQueue__GEN_917; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1097 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_650 :
    exe_stage_lsu_stQueue__GEN_918; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1098 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_651 :
    exe_stage_lsu_stQueue__GEN_919; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1099 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_652 :
    exe_stage_lsu_stQueue__GEN_920; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1100 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_653 :
    exe_stage_lsu_stQueue__GEN_921; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1101 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_654 :
    exe_stage_lsu_stQueue__GEN_922; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1102 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_655 :
    exe_stage_lsu_stQueue__GEN_923; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1103 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_656 :
    exe_stage_lsu_stQueue__GEN_924; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1104 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_657 :
    exe_stage_lsu_stQueue__GEN_925; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1105 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_658 :
    exe_stage_lsu_stQueue__GEN_926; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1106 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_659 :
    exe_stage_lsu_stQueue__GEN_927; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1107 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_660 :
    exe_stage_lsu_stQueue__GEN_928; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1108 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_661 :
    exe_stage_lsu_stQueue__GEN_929; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1109 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_662 :
    exe_stage_lsu_stQueue__GEN_930; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1110 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_663 :
    exe_stage_lsu_stQueue__GEN_931; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1111 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_664 :
    exe_stage_lsu_stQueue__GEN_932; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1112 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_665 :
    exe_stage_lsu_stQueue__GEN_933; // @[Store_queue.scala 148:51]
  wire [63:0] exe_stage_lsu_stQueue__GEN_1114 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_667 :
    exe_stage_lsu_stQueue__GEN_935; // @[Store_queue.scala 148:51]
  wire [63:0] exe_stage_lsu_stQueue__GEN_1115 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_668 :
    exe_stage_lsu_stQueue__GEN_936; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1118 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_760 :
    exe_stage_lsu_stQueue__GEN_1028; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1119 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_761 :
    exe_stage_lsu_stQueue__GEN_1029; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1120 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_762 :
    exe_stage_lsu_stQueue__GEN_1030; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1121 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_763 :
    exe_stage_lsu_stQueue__GEN_1031; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1122 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_764 :
    exe_stage_lsu_stQueue__GEN_1032; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1123 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_765 :
    exe_stage_lsu_stQueue__GEN_1033; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1124 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_766 :
    exe_stage_lsu_stQueue__GEN_1034; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1125 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_767 :
    exe_stage_lsu_stQueue__GEN_1035; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1126 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_768 :
    exe_stage_lsu_stQueue__GEN_1036; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1127 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_769 :
    exe_stage_lsu_stQueue__GEN_1037; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1128 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_770 :
    exe_stage_lsu_stQueue__GEN_1038; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1132 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_774 :
    exe_stage_lsu_stQueue__GEN_1042; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1133 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_775 :
    exe_stage_lsu_stQueue__GEN_1043; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1134 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_776 :
    exe_stage_lsu_stQueue__GEN_1044; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1135 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_777 :
    exe_stage_lsu_stQueue__GEN_1045; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1136 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_778 :
    exe_stage_lsu_stQueue__GEN_1046; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1137 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_779 :
    exe_stage_lsu_stQueue__GEN_1047; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1138 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_780 :
    exe_stage_lsu_stQueue__GEN_1048; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1139 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_781 :
    exe_stage_lsu_stQueue__GEN_1049; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1140 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_782 :
    exe_stage_lsu_stQueue__GEN_1050; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1141 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_783 :
    exe_stage_lsu_stQueue__GEN_1051; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1142 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_784 :
    exe_stage_lsu_stQueue__GEN_1052; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1143 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_785 :
    exe_stage_lsu_stQueue__GEN_1053; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1144 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_786 :
    exe_stage_lsu_stQueue__GEN_1054; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1145 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_787 :
    exe_stage_lsu_stQueue__GEN_1055; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1146 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_788 :
    exe_stage_lsu_stQueue__GEN_1056; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1147 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_789 :
    exe_stage_lsu_stQueue__GEN_1057; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1148 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_790 :
    exe_stage_lsu_stQueue__GEN_1058; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1149 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_791 :
    exe_stage_lsu_stQueue__GEN_1059; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1150 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_792 :
    exe_stage_lsu_stQueue__GEN_1060; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1151 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_793 :
    exe_stage_lsu_stQueue__GEN_1061; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1152 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_794 :
    exe_stage_lsu_stQueue__GEN_1062; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1153 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_795 :
    exe_stage_lsu_stQueue__GEN_1063; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1154 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_796 :
    exe_stage_lsu_stQueue__GEN_1064; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1155 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_797 :
    exe_stage_lsu_stQueue__GEN_1065; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1156 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_798 :
    exe_stage_lsu_stQueue__GEN_1066; // @[Store_queue.scala 148:51]
  wire  exe_stage_lsu_stQueue__GEN_1157 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_799 :
    exe_stage_lsu_stQueue__GEN_1067; // @[Store_queue.scala 148:51]
  wire [63:0] exe_stage_lsu_stQueue__GEN_1159 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_801 :
    exe_stage_lsu_stQueue__GEN_1069; // @[Store_queue.scala 148:51]
  wire [63:0] exe_stage_lsu_stQueue__GEN_1160 = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_802 :
    exe_stage_lsu_stQueue__GEN_1070; // @[Store_queue.scala 148:51]
  wire [2:0] exe_stage_lsu_stQueue__res_T = exe_stage_lsu_stQueue__GEN_1114[2:0]; // @[riscv_isa.scala 907:38]
  wire [5:0] exe_stage_lsu_stQueue__res_T_1 = {exe_stage_lsu_stQueue__res_T, 3'h0}; // @[riscv_isa.scala 907:61]
  wire [126:0] _GEN_762 = {{63'd0}, exe_stage_lsu_stQueue__GEN_1115}; // @[riscv_isa.scala 907:28]
  wire [126:0] exe_stage_lsu_stQueue__res_T_2 = _GEN_762 << exe_stage_lsu_stQueue__res_T_1; // @[riscv_isa.scala 907:28]
  wire  exe_stage_lsu_stQueue__wstrb_T = exe_stage_lsu_stQueue__GEN_1073 | exe_stage_lsu_stQueue__GEN_1077; // @[riscv_isa.scala 153:20]
  wire  exe_stage_lsu_stQueue__wstrb_T_1 = exe_stage_lsu_stQueue__wstrb_T | exe_stage_lsu_stQueue__GEN_1080; // @[riscv_isa.scala 153:26]
  wire  exe_stage_lsu_stQueue__wstrb_T_2 = exe_stage_lsu_stQueue__GEN_1074 | exe_stage_lsu_stQueue__GEN_1078; // @[riscv_isa.scala 154:20]
  wire  exe_stage_lsu_stQueue__wstrb_T_3 = exe_stage_lsu_stQueue__wstrb_T_2 | exe_stage_lsu_stQueue__GEN_1081; // @[riscv_isa.scala 154:26]
  wire  exe_stage_lsu_stQueue__wstrb_T_4 = exe_stage_lsu_stQueue__GEN_1075 | exe_stage_lsu_stQueue__GEN_1079; // @[riscv_isa.scala 155:20]
  wire  exe_stage_lsu_stQueue__wstrb_T_5 = exe_stage_lsu_stQueue__wstrb_T_4 | exe_stage_lsu_stQueue__GEN_1082; // @[riscv_isa.scala 155:26]
  wire  exe_stage_lsu_stQueue__wstrb_T_6 = exe_stage_lsu_stQueue__wstrb_T_5 | exe_stage_lsu_stQueue__GEN_1089; // @[riscv_isa.scala 155:31]
  wire  exe_stage_lsu_stQueue__wstrb_T_7 = exe_stage_lsu_stQueue__wstrb_T_6 | exe_stage_lsu_stQueue__GEN_1090; // @[riscv_isa.scala 155:43]
  wire  exe_stage_lsu_stQueue__wstrb_T_8 = exe_stage_lsu_stQueue__wstrb_T_7 | exe_stage_lsu_stQueue__GEN_1091; // @[riscv_isa.scala 155:54]
  wire  exe_stage_lsu_stQueue__wstrb_T_9 = exe_stage_lsu_stQueue__wstrb_T_8 | exe_stage_lsu_stQueue__GEN_1092; // @[riscv_isa.scala 155:65]
  wire  exe_stage_lsu_stQueue__wstrb_T_10 = exe_stage_lsu_stQueue__wstrb_T_9 | exe_stage_lsu_stQueue__GEN_1093; // @[riscv_isa.scala 155:76]
  wire  exe_stage_lsu_stQueue__wstrb_T_11 = exe_stage_lsu_stQueue__wstrb_T_10 | exe_stage_lsu_stQueue__GEN_1094; // @[riscv_isa.scala 155:86]
  wire  exe_stage_lsu_stQueue__wstrb_T_12 = exe_stage_lsu_stQueue__wstrb_T_11 | exe_stage_lsu_stQueue__GEN_1095; // @[riscv_isa.scala 155:97]
  wire  exe_stage_lsu_stQueue__wstrb_T_13 = exe_stage_lsu_stQueue__wstrb_T_12 | exe_stage_lsu_stQueue__GEN_1096; // @[riscv_isa.scala 155:108]
  wire  exe_stage_lsu_stQueue__wstrb_T_14 = exe_stage_lsu_stQueue__wstrb_T_13 | exe_stage_lsu_stQueue__GEN_1097; // @[riscv_isa.scala 155:120]
  wire  exe_stage_lsu_stQueue__wstrb_T_15 = exe_stage_lsu_stQueue__wstrb_T_14 | exe_stage_lsu_stQueue__GEN_1109; // @[riscv_isa.scala 155:132]
  wire  exe_stage_lsu_stQueue__wstrb_T_16 = exe_stage_lsu_stQueue__wstrb_T_15 | exe_stage_lsu_stQueue__GEN_1110; // @[riscv_isa.scala 155:138]
  wire  exe_stage_lsu_stQueue__wstrb_T_17 = exe_stage_lsu_stQueue__wstrb_T_16 | exe_stage_lsu_stQueue__GEN_1087; // @[riscv_isa.scala 155:144]
  wire  exe_stage_lsu_stQueue__wstrb_T_18 = exe_stage_lsu_stQueue__wstrb_T_17 | exe_stage_lsu_stQueue__GEN_1088; // @[riscv_isa.scala 155:151]
  wire  exe_stage_lsu_stQueue__wstrb_T_19 = exe_stage_lsu_stQueue__GEN_1076 | exe_stage_lsu_stQueue__GEN_1098; // @[riscv_isa.scala 156:20]
  wire  exe_stage_lsu_stQueue__wstrb_T_20 = exe_stage_lsu_stQueue__wstrb_T_19 | exe_stage_lsu_stQueue__GEN_1111; // @[riscv_isa.scala 156:27]
  wire  exe_stage_lsu_stQueue__wstrb_T_21 = exe_stage_lsu_stQueue__wstrb_T_20 | exe_stage_lsu_stQueue__GEN_1083; // @[riscv_isa.scala 156:33]
  wire  exe_stage_lsu_stQueue__wstrb_T_22 = exe_stage_lsu_stQueue__wstrb_T_21 | exe_stage_lsu_stQueue__GEN_1099; // @[riscv_isa.scala 156:38]
  wire  exe_stage_lsu_stQueue__wstrb_T_23 = exe_stage_lsu_stQueue__wstrb_T_22 | exe_stage_lsu_stQueue__GEN_1112; // @[riscv_isa.scala 156:45]
  wire  exe_stage_lsu_stQueue__wstrb_T_24 = exe_stage_lsu_stQueue__wstrb_T_23 | exe_stage_lsu_stQueue__GEN_1100; // @[riscv_isa.scala 156:51]
  wire  exe_stage_lsu_stQueue__wstrb_T_25 = exe_stage_lsu_stQueue__wstrb_T_24 | exe_stage_lsu_stQueue__GEN_1101; // @[riscv_isa.scala 156:63]
  wire  exe_stage_lsu_stQueue__wstrb_T_26 = exe_stage_lsu_stQueue__wstrb_T_25 | exe_stage_lsu_stQueue__GEN_1102; // @[riscv_isa.scala 156:74]
  wire  exe_stage_lsu_stQueue__wstrb_T_27 = exe_stage_lsu_stQueue__wstrb_T_26 | exe_stage_lsu_stQueue__GEN_1103; // @[riscv_isa.scala 156:85]
  wire  exe_stage_lsu_stQueue__wstrb_T_28 = exe_stage_lsu_stQueue__wstrb_T_27 | exe_stage_lsu_stQueue__GEN_1104; // @[riscv_isa.scala 156:96]
  wire  exe_stage_lsu_stQueue__wstrb_T_29 = exe_stage_lsu_stQueue__wstrb_T_28 | exe_stage_lsu_stQueue__GEN_1105; // @[riscv_isa.scala 156:106]
  wire  exe_stage_lsu_stQueue__wstrb_T_30 = exe_stage_lsu_stQueue__wstrb_T_29 | exe_stage_lsu_stQueue__GEN_1106; // @[riscv_isa.scala 156:117]
  wire  exe_stage_lsu_stQueue__wstrb_T_31 = exe_stage_lsu_stQueue__wstrb_T_30 | exe_stage_lsu_stQueue__GEN_1107; // @[riscv_isa.scala 156:128]
  wire  exe_stage_lsu_stQueue__wstrb_T_32 = exe_stage_lsu_stQueue__wstrb_T_31 | exe_stage_lsu_stQueue__GEN_1108; // @[riscv_isa.scala 156:140]
  wire [1:0] exe_stage_lsu_stQueue__wstrb_T_34 = exe_stage_lsu_stQueue__wstrb_T_3 ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_stQueue__wstrb_T_35 = exe_stage_lsu_stQueue__wstrb_T_18 ? 4'hf : 4'h0; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_stQueue__wstrb_T_36 = exe_stage_lsu_stQueue__wstrb_T_32 ? 8'hff : 8'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_292 = {{1'd0}, exe_stage_lsu_stQueue__wstrb_T_1}; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_stQueue__wstrb_T_37 = _GEN_292 | exe_stage_lsu_stQueue__wstrb_T_34; // @[Mux.scala 27:73]
  wire [3:0] _GEN_293 = {{2'd0}, exe_stage_lsu_stQueue__wstrb_T_37}; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_stQueue__wstrb_T_38 = _GEN_293 | exe_stage_lsu_stQueue__wstrb_T_35; // @[Mux.scala 27:73]
  wire [7:0] _GEN_294 = {{4'd0}, exe_stage_lsu_stQueue__wstrb_T_38}; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_stQueue__wstrb_T_39 = _GEN_294 | exe_stage_lsu_stQueue__wstrb_T_36; // @[Mux.scala 27:73]
  wire [14:0] _GEN_763 = {{7'd0}, exe_stage_lsu_stQueue__wstrb_T_39}; // @[riscv_isa.scala 916:10]
  wire [14:0] exe_stage_lsu_stQueue__wstrb_T_41 = _GEN_763 << exe_stage_lsu_stQueue__res_T; // @[riscv_isa.scala 916:10]
  wire [7:0] exe_stage_lsu_stQueue_wstrb = exe_stage_lsu_stQueue__wstrb_T_41[7:0]; // @[riscv_isa.scala 912:21 913:11]
  wire  exe_stage_lsu_stQueue__wmask_T = exe_stage_lsu_stQueue_wstrb[0]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_1 = exe_stage_lsu_stQueue_wstrb[1]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_2 = exe_stage_lsu_stQueue_wstrb[2]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_3 = exe_stage_lsu_stQueue_wstrb[3]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_4 = exe_stage_lsu_stQueue_wstrb[4]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_5 = exe_stage_lsu_stQueue_wstrb[5]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_6 = exe_stage_lsu_stQueue_wstrb[6]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_7 = exe_stage_lsu_stQueue_wstrb[7]; // @[Util.scala 41:14]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_9 = exe_stage_lsu_stQueue__wmask_T ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_11 = exe_stage_lsu_stQueue__wmask_T_1 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_13 = exe_stage_lsu_stQueue__wmask_T_2 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_15 = exe_stage_lsu_stQueue__wmask_T_3 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_17 = exe_stage_lsu_stQueue__wmask_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_19 = exe_stage_lsu_stQueue__wmask_T_5 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_21 = exe_stage_lsu_stQueue__wmask_T_6 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_23 = exe_stage_lsu_stQueue__wmask_T_7 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [63:0] exe_stage_lsu_stQueue_wmask = {exe_stage_lsu_stQueue__wmask_T_23,exe_stage_lsu_stQueue__wmask_T_21,
    exe_stage_lsu_stQueue__wmask_T_19,exe_stage_lsu_stQueue__wmask_T_17,exe_stage_lsu_stQueue__wmask_T_15,
    exe_stage_lsu_stQueue__wmask_T_13,exe_stage_lsu_stQueue__wmask_T_11,exe_stage_lsu_stQueue__wmask_T_9}; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_lsu_stQueue_res = exe_stage_lsu_stQueue__res_T_2[63:0]; // @[riscv_isa.scala 906:21 907:11]
  wire [63:0] exe_stage_lsu_stQueue__new_data_T_2 = exe_stage_lsu_stQueue_res & exe_stage_lsu_stQueue_wmask; // @[Util.scala 108:44]
  wire [2:0] exe_stage_lsu_stQueue__res_T_3 = exe_stage_lsu_stQueue__GEN_1159[2:0]; // @[riscv_isa.scala 907:38]
  wire [5:0] exe_stage_lsu_stQueue__res_T_4 = {exe_stage_lsu_stQueue__res_T_3, 3'h0}; // @[riscv_isa.scala 907:61]
  wire [126:0] _GEN_764 = {{63'd0}, exe_stage_lsu_stQueue__GEN_1160}; // @[riscv_isa.scala 907:28]
  wire [126:0] exe_stage_lsu_stQueue__res_T_5 = _GEN_764 << exe_stage_lsu_stQueue__res_T_4; // @[riscv_isa.scala 907:28]
  wire  exe_stage_lsu_stQueue__wstrb_T_42 = exe_stage_lsu_stQueue__GEN_1118 | exe_stage_lsu_stQueue__GEN_1122; // @[riscv_isa.scala 153:20]
  wire  exe_stage_lsu_stQueue__wstrb_T_43 = exe_stage_lsu_stQueue__wstrb_T_42 | exe_stage_lsu_stQueue__GEN_1125; // @[riscv_isa.scala 153:26]
  wire  exe_stage_lsu_stQueue__wstrb_T_44 = exe_stage_lsu_stQueue__GEN_1119 | exe_stage_lsu_stQueue__GEN_1123; // @[riscv_isa.scala 154:20]
  wire  exe_stage_lsu_stQueue__wstrb_T_45 = exe_stage_lsu_stQueue__wstrb_T_44 | exe_stage_lsu_stQueue__GEN_1126; // @[riscv_isa.scala 154:26]
  wire  exe_stage_lsu_stQueue__wstrb_T_46 = exe_stage_lsu_stQueue__GEN_1120 | exe_stage_lsu_stQueue__GEN_1124; // @[riscv_isa.scala 155:20]
  wire  exe_stage_lsu_stQueue__wstrb_T_47 = exe_stage_lsu_stQueue__wstrb_T_46 | exe_stage_lsu_stQueue__GEN_1127; // @[riscv_isa.scala 155:26]
  wire  exe_stage_lsu_stQueue__wstrb_T_48 = exe_stage_lsu_stQueue__wstrb_T_47 | exe_stage_lsu_stQueue__GEN_1134; // @[riscv_isa.scala 155:31]
  wire  exe_stage_lsu_stQueue__wstrb_T_49 = exe_stage_lsu_stQueue__wstrb_T_48 | exe_stage_lsu_stQueue__GEN_1135; // @[riscv_isa.scala 155:43]
  wire  exe_stage_lsu_stQueue__wstrb_T_50 = exe_stage_lsu_stQueue__wstrb_T_49 | exe_stage_lsu_stQueue__GEN_1136; // @[riscv_isa.scala 155:54]
  wire  exe_stage_lsu_stQueue__wstrb_T_51 = exe_stage_lsu_stQueue__wstrb_T_50 | exe_stage_lsu_stQueue__GEN_1137; // @[riscv_isa.scala 155:65]
  wire  exe_stage_lsu_stQueue__wstrb_T_52 = exe_stage_lsu_stQueue__wstrb_T_51 | exe_stage_lsu_stQueue__GEN_1138; // @[riscv_isa.scala 155:76]
  wire  exe_stage_lsu_stQueue__wstrb_T_53 = exe_stage_lsu_stQueue__wstrb_T_52 | exe_stage_lsu_stQueue__GEN_1139; // @[riscv_isa.scala 155:86]
  wire  exe_stage_lsu_stQueue__wstrb_T_54 = exe_stage_lsu_stQueue__wstrb_T_53 | exe_stage_lsu_stQueue__GEN_1140; // @[riscv_isa.scala 155:97]
  wire  exe_stage_lsu_stQueue__wstrb_T_55 = exe_stage_lsu_stQueue__wstrb_T_54 | exe_stage_lsu_stQueue__GEN_1141; // @[riscv_isa.scala 155:108]
  wire  exe_stage_lsu_stQueue__wstrb_T_56 = exe_stage_lsu_stQueue__wstrb_T_55 | exe_stage_lsu_stQueue__GEN_1142; // @[riscv_isa.scala 155:120]
  wire  exe_stage_lsu_stQueue__wstrb_T_57 = exe_stage_lsu_stQueue__wstrb_T_56 | exe_stage_lsu_stQueue__GEN_1154; // @[riscv_isa.scala 155:132]
  wire  exe_stage_lsu_stQueue__wstrb_T_58 = exe_stage_lsu_stQueue__wstrb_T_57 | exe_stage_lsu_stQueue__GEN_1155; // @[riscv_isa.scala 155:138]
  wire  exe_stage_lsu_stQueue__wstrb_T_59 = exe_stage_lsu_stQueue__wstrb_T_58 | exe_stage_lsu_stQueue__GEN_1132; // @[riscv_isa.scala 155:144]
  wire  exe_stage_lsu_stQueue__wstrb_T_60 = exe_stage_lsu_stQueue__wstrb_T_59 | exe_stage_lsu_stQueue__GEN_1133; // @[riscv_isa.scala 155:151]
  wire  exe_stage_lsu_stQueue__wstrb_T_61 = exe_stage_lsu_stQueue__GEN_1121 | exe_stage_lsu_stQueue__GEN_1143; // @[riscv_isa.scala 156:20]
  wire  exe_stage_lsu_stQueue__wstrb_T_62 = exe_stage_lsu_stQueue__wstrb_T_61 | exe_stage_lsu_stQueue__GEN_1156; // @[riscv_isa.scala 156:27]
  wire  exe_stage_lsu_stQueue__wstrb_T_63 = exe_stage_lsu_stQueue__wstrb_T_62 | exe_stage_lsu_stQueue__GEN_1128; // @[riscv_isa.scala 156:33]
  wire  exe_stage_lsu_stQueue__wstrb_T_64 = exe_stage_lsu_stQueue__wstrb_T_63 | exe_stage_lsu_stQueue__GEN_1144; // @[riscv_isa.scala 156:38]
  wire  exe_stage_lsu_stQueue__wstrb_T_65 = exe_stage_lsu_stQueue__wstrb_T_64 | exe_stage_lsu_stQueue__GEN_1157; // @[riscv_isa.scala 156:45]
  wire  exe_stage_lsu_stQueue__wstrb_T_66 = exe_stage_lsu_stQueue__wstrb_T_65 | exe_stage_lsu_stQueue__GEN_1145; // @[riscv_isa.scala 156:51]
  wire  exe_stage_lsu_stQueue__wstrb_T_67 = exe_stage_lsu_stQueue__wstrb_T_66 | exe_stage_lsu_stQueue__GEN_1146; // @[riscv_isa.scala 156:63]
  wire  exe_stage_lsu_stQueue__wstrb_T_68 = exe_stage_lsu_stQueue__wstrb_T_67 | exe_stage_lsu_stQueue__GEN_1147; // @[riscv_isa.scala 156:74]
  wire  exe_stage_lsu_stQueue__wstrb_T_69 = exe_stage_lsu_stQueue__wstrb_T_68 | exe_stage_lsu_stQueue__GEN_1148; // @[riscv_isa.scala 156:85]
  wire  exe_stage_lsu_stQueue__wstrb_T_70 = exe_stage_lsu_stQueue__wstrb_T_69 | exe_stage_lsu_stQueue__GEN_1149; // @[riscv_isa.scala 156:96]
  wire  exe_stage_lsu_stQueue__wstrb_T_71 = exe_stage_lsu_stQueue__wstrb_T_70 | exe_stage_lsu_stQueue__GEN_1150; // @[riscv_isa.scala 156:106]
  wire  exe_stage_lsu_stQueue__wstrb_T_72 = exe_stage_lsu_stQueue__wstrb_T_71 | exe_stage_lsu_stQueue__GEN_1151; // @[riscv_isa.scala 156:117]
  wire  exe_stage_lsu_stQueue__wstrb_T_73 = exe_stage_lsu_stQueue__wstrb_T_72 | exe_stage_lsu_stQueue__GEN_1152; // @[riscv_isa.scala 156:128]
  wire  exe_stage_lsu_stQueue__wstrb_T_74 = exe_stage_lsu_stQueue__wstrb_T_73 | exe_stage_lsu_stQueue__GEN_1153; // @[riscv_isa.scala 156:140]
  wire [1:0] exe_stage_lsu_stQueue__wstrb_T_76 = exe_stage_lsu_stQueue__wstrb_T_45 ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_stQueue__wstrb_T_77 = exe_stage_lsu_stQueue__wstrb_T_60 ? 4'hf : 4'h0; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_stQueue__wstrb_T_78 = exe_stage_lsu_stQueue__wstrb_T_74 ? 8'hff : 8'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_295 = {{1'd0}, exe_stage_lsu_stQueue__wstrb_T_43}; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_stQueue__wstrb_T_79 = _GEN_295 | exe_stage_lsu_stQueue__wstrb_T_76; // @[Mux.scala 27:73]
  wire [3:0] _GEN_296 = {{2'd0}, exe_stage_lsu_stQueue__wstrb_T_79}; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_stQueue__wstrb_T_80 = _GEN_296 | exe_stage_lsu_stQueue__wstrb_T_77; // @[Mux.scala 27:73]
  wire [7:0] _GEN_297 = {{4'd0}, exe_stage_lsu_stQueue__wstrb_T_80}; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_stQueue__wstrb_T_81 = _GEN_297 | exe_stage_lsu_stQueue__wstrb_T_78; // @[Mux.scala 27:73]
  wire [14:0] _GEN_765 = {{7'd0}, exe_stage_lsu_stQueue__wstrb_T_81}; // @[riscv_isa.scala 916:10]
  wire [14:0] exe_stage_lsu_stQueue__wstrb_T_83 = _GEN_765 << exe_stage_lsu_stQueue__res_T_3; // @[riscv_isa.scala 916:10]
  wire [7:0] exe_stage_lsu_stQueue_wstrb_2 = exe_stage_lsu_stQueue__wstrb_T_83[7:0]; // @[riscv_isa.scala 912:21 913:11]
  wire  exe_stage_lsu_stQueue__wmask_T_24 = exe_stage_lsu_stQueue_wstrb_2[0]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_25 = exe_stage_lsu_stQueue_wstrb_2[1]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_26 = exe_stage_lsu_stQueue_wstrb_2[2]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_27 = exe_stage_lsu_stQueue_wstrb_2[3]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_28 = exe_stage_lsu_stQueue_wstrb_2[4]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_29 = exe_stage_lsu_stQueue_wstrb_2[5]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_30 = exe_stage_lsu_stQueue_wstrb_2[6]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_stQueue__wmask_T_31 = exe_stage_lsu_stQueue_wstrb_2[7]; // @[Util.scala 41:14]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_33 = exe_stage_lsu_stQueue__wmask_T_24 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_35 = exe_stage_lsu_stQueue__wmask_T_25 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_37 = exe_stage_lsu_stQueue__wmask_T_26 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_39 = exe_stage_lsu_stQueue__wmask_T_27 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_41 = exe_stage_lsu_stQueue__wmask_T_28 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_43 = exe_stage_lsu_stQueue__wmask_T_29 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_45 = exe_stage_lsu_stQueue__wmask_T_30 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_stQueue__wmask_T_47 = exe_stage_lsu_stQueue__wmask_T_31 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [63:0] exe_stage_lsu_stQueue_wmask_1 = {exe_stage_lsu_stQueue__wmask_T_47,exe_stage_lsu_stQueue__wmask_T_45,
    exe_stage_lsu_stQueue__wmask_T_43,exe_stage_lsu_stQueue__wmask_T_41,exe_stage_lsu_stQueue__wmask_T_39,
    exe_stage_lsu_stQueue__wmask_T_37,exe_stage_lsu_stQueue__wmask_T_35,exe_stage_lsu_stQueue__wmask_T_33}; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_lsu_stQueue__new_data_T_3 = ~exe_stage_lsu_stQueue_wmask_1; // @[Util.scala 108:27]
  wire [63:0] exe_stage_lsu_stQueue__new_data_T_4 = exe_stage_lsu_stQueue__new_data_T_2 &
    exe_stage_lsu_stQueue__new_data_T_3; // @[Util.scala 108:25]
  wire [63:0] exe_stage_lsu_stQueue_res_1 = exe_stage_lsu_stQueue__res_T_5[63:0]; // @[riscv_isa.scala 906:21 907:11]
  wire [63:0] exe_stage_lsu_stQueue__new_data_T_5 = exe_stage_lsu_stQueue_res_1 & exe_stage_lsu_stQueue_wmask_1; // @[Util.scala 108:44]
  wire  _GEN_298 = exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 & exe_stage_lsu_stQueue__T_9; // @[Store_queue.scala 129:13]
  wire  _GEN_301 = ~exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 & exe_stage_lsu_stQueue__T_1; // @[Store_queue.scala 133:13]
  wire  _GEN_302 = ~exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 & exe_stage_lsu_stQueue__T_1 &
    exe_stage_lsu_stQueue__T_9; // @[Store_queue.scala 133:13]
  wire  exe_stage_lsu_ls_arb_io_in_0_ready;
  wire  exe_stage_lsu_ls_arb_io_in_0_valid;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_lb;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_lh;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_lw;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_ld;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_lbu;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_lhu;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_lwu;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_sb;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_sh;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_sw;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_sd;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_lr_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_sc_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoswap_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoadd_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoxor_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoand_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoor_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomin_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomax_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amominu_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_lr_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_sc_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoswap_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoadd_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoxor_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoand_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoor_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomin_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomax_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amominu_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_flw;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_fsw;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_fld;
  wire  exe_stage_lsu_ls_arb_io_in_0_bits_fun_fsd;
  wire [5:0] exe_stage_lsu_ls_arb_io_in_0_bits_param_rd0;
  wire [63:0] exe_stage_lsu_ls_arb_io_in_0_bits_param_dat_op1;
  wire [63:0] exe_stage_lsu_ls_arb_io_in_0_bits_param_dat_op2;
  wire  exe_stage_lsu_ls_arb_io_in_1_ready;
  wire  exe_stage_lsu_ls_arb_io_in_1_valid;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_lb;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_lh;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_lw;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_ld;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_lbu;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_lhu;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_lwu;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_sb;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_sh;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_sw;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_sd;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_lr_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_sc_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoswap_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoadd_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoxor_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoand_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoor_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomin_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomax_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amominu_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_lr_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_sc_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoswap_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoadd_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoxor_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoand_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoor_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomin_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomax_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amominu_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_flw;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_fsw;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_fld;
  wire  exe_stage_lsu_ls_arb_io_in_1_bits_fun_fsd;
  wire [5:0] exe_stage_lsu_ls_arb_io_in_1_bits_param_rd0;
  wire [63:0] exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op1;
  wire [63:0] exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op2;
  wire  exe_stage_lsu_ls_arb_io_out_ready;
  wire  exe_stage_lsu_ls_arb_io_out_valid;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_lb;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_lh;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_lw;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_ld;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_lbu;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_lhu;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_lwu;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_sb;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_sh;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_sw;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_sd;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_lr_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_sc_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_lr_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_sc_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_flw;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_fsw;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_fld;
  wire  exe_stage_lsu_ls_arb_io_out_bits_fun_fsd;
  wire [5:0] exe_stage_lsu_ls_arb_io_out_bits_param_rd0;
  wire [63:0] exe_stage_lsu_ls_arb_io_out_bits_param_dat_op1;
  wire [63:0] exe_stage_lsu_ls_arb_io_out_bits_param_dat_op2;
  wire  exe_stage_lsu_ls_arb_grant_1 = ~exe_stage_lsu_ls_arb_io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  exe_stage_lsu_ls_arb__io_out_valid_T = ~exe_stage_lsu_ls_arb_grant_1; // @[Arbiter.scala 147:19]
  wire  exe_stage_lsu_system_clock;
  wire  exe_stage_lsu_system_reset;
  wire  exe_stage_lsu_system_io_enq_ready;
  wire  exe_stage_lsu_system_io_enq_valid;
  wire  exe_stage_lsu_system_io_enq_bits_fun_lb;
  wire  exe_stage_lsu_system_io_enq_bits_fun_lh;
  wire  exe_stage_lsu_system_io_enq_bits_fun_lw;
  wire  exe_stage_lsu_system_io_enq_bits_fun_ld;
  wire  exe_stage_lsu_system_io_enq_bits_fun_lbu;
  wire  exe_stage_lsu_system_io_enq_bits_fun_lhu;
  wire  exe_stage_lsu_system_io_enq_bits_fun_lwu;
  wire  exe_stage_lsu_system_io_enq_bits_fun_sb;
  wire  exe_stage_lsu_system_io_enq_bits_fun_sh;
  wire  exe_stage_lsu_system_io_enq_bits_fun_sw;
  wire  exe_stage_lsu_system_io_enq_bits_fun_sd;
  wire  exe_stage_lsu_system_io_enq_bits_fun_lr_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_sc_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoand_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoor_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amomin_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amomax_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amominu_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_system_io_enq_bits_fun_lr_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_sc_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoand_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amoor_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amomin_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amomax_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amominu_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_system_io_enq_bits_fun_flw;
  wire  exe_stage_lsu_system_io_enq_bits_fun_fsw;
  wire  exe_stage_lsu_system_io_enq_bits_fun_fld;
  wire  exe_stage_lsu_system_io_enq_bits_fun_fsd;
  wire  exe_stage_lsu_system_io_deq_ready;
  wire  exe_stage_lsu_system_io_deq_valid;
  wire [5:0] exe_stage_lsu_system_io_deq_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_system_io_deq_bits_wb_res;
  wire  exe_stage_lsu_system_io_deq_bits_is_load_amo;
  wire  exe_stage_lsu_system_io_deq_bits_is_flw;
  wire  exe_stage_lsu_system_io_deq_bits_is_fld;
  wire  exe_stage_lsu_system_io_is_empty;
  wire  exe_stage_lsu_system_io_getPut_ready;
  wire  exe_stage_lsu_system_io_getPut_valid;
  wire [2:0] exe_stage_lsu_system_io_getPut_bits_opcode;
  wire [2:0] exe_stage_lsu_system_io_getPut_bits_param;
  wire [1:0] exe_stage_lsu_system_io_getPut_bits_size;
  wire  exe_stage_lsu_system_io_getPut_bits_source;
  wire [31:0] exe_stage_lsu_system_io_getPut_bits_address;
  wire [7:0] exe_stage_lsu_system_io_getPut_bits_mask;
  wire [63:0] exe_stage_lsu_system_io_getPut_bits_data;
  wire  exe_stage_lsu_system_io_getPut_bits_corrupt;
  wire  exe_stage_lsu_system_io_access_ready;
  wire  exe_stage_lsu_system_io_access_valid;
  wire [2:0] exe_stage_lsu_system_io_access_bits_opcode;
  wire [63:0] exe_stage_lsu_system_io_access_bits_data;
  reg  exe_stage_lsu_system_is_busy; // @[IO_Lsu.scala 45:27]
  reg  exe_stage_lsu_system_isTransing; // @[IO_Lsu.scala 46:27]
  reg  exe_stage_lsu_system_pending_fun_lb; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_lh; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_lw; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_ld; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_lbu; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_lhu; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_lwu; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_sb; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_sh; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_sw; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_sd; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_lr_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_sc_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoswap_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoadd_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoxor_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoand_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoor_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amomin_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amomax_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amominu_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amomaxu_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_lr_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_sc_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoswap_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoadd_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoxor_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoand_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amoor_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amomin_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amomax_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amominu_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_amomaxu_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_flw; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_fsw; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_fld; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_system_pending_fun_fsd; // @[IO_Lsu.scala 47:20]
  reg [5:0] exe_stage_lsu_system_pending_param_rd0; // @[IO_Lsu.scala 47:20]
  reg [63:0] exe_stage_lsu_system_pending_param_dat_op1; // @[IO_Lsu.scala 47:20]
  reg [63:0] exe_stage_lsu_system_pending_param_dat_op2; // @[IO_Lsu.scala 47:20]
  wire  exe_stage_lsu_system__io_is_empty_T = ~exe_stage_lsu_system_is_busy; // @[IO_Lsu.scala 49:18]
  wire  exe_stage_lsu_system__io_getPut_valid_T = ~exe_stage_lsu_system_isTransing; // @[IO_Lsu.scala 51:32]
  wire  exe_stage_lsu_system__T = exe_stage_lsu_system_pending_fun_lb | exe_stage_lsu_system_pending_fun_lh; // @[riscv_isa.scala 143:19]
  wire  exe_stage_lsu_system__T_1 = exe_stage_lsu_system__T | exe_stage_lsu_system_pending_fun_lw; // @[riscv_isa.scala 143:24]
  wire  exe_stage_lsu_system__T_2 = exe_stage_lsu_system__T_1 | exe_stage_lsu_system_pending_fun_ld; // @[riscv_isa.scala 143:29]
  wire  exe_stage_lsu_system__T_3 = exe_stage_lsu_system__T_2 | exe_stage_lsu_system_pending_fun_lbu; // @[riscv_isa.scala 143:34]
  wire  exe_stage_lsu_system__T_4 = exe_stage_lsu_system__T_3 | exe_stage_lsu_system_pending_fun_lhu; // @[riscv_isa.scala 143:40]
  wire  exe_stage_lsu_system__T_5 = exe_stage_lsu_system__T_4 | exe_stage_lsu_system_pending_fun_lwu; // @[riscv_isa.scala 143:46]
  wire  exe_stage_lsu_system__T_6 = exe_stage_lsu_system__T_5 | exe_stage_lsu_system_pending_fun_flw; // @[riscv_isa.scala 143:52]
  wire  exe_stage_lsu_system__T_7 = exe_stage_lsu_system__T_6 | exe_stage_lsu_system_pending_fun_fld; // @[riscv_isa.scala 143:59]
  wire  exe_stage_lsu_system__T_8 = exe_stage_lsu_system_pending_fun_lr_d | exe_stage_lsu_system_pending_fun_lr_w; // @[riscv_isa.scala 141:20]
  wire  exe_stage_lsu_system__T_9 = exe_stage_lsu_system__T_7 | exe_stage_lsu_system__T_8; // @[riscv_isa.scala 143:65]
  wire  exe_stage_lsu_system__T_11 = ~exe_stage_lsu_system__T_8; // @[IO_Lsu.scala 55:31]
  wire  exe_stage_lsu_system__T_12 = exe_stage_lsu_system__T_9 & exe_stage_lsu_system__T_11; // @[IO_Lsu.scala 55:29]
  wire [63:0] exe_stage_lsu_system__io_getPut_bits_T = {{3'd0}, exe_stage_lsu_system_pending_param_dat_op1[63:3]}; // @[IO_Lsu.scala 59:39]
  wire [66:0] exe_stage_lsu_system__io_getPut_bits_T_1 = {exe_stage_lsu_system__io_getPut_bits_T, 3'h0}; // @[IO_Lsu.scala 59:59]
  wire  exe_stage_lsu_system__T_13 = exe_stage_lsu_system_pending_fun_sb | exe_stage_lsu_system_pending_fun_sh; // @[riscv_isa.scala 144:19]
  wire  exe_stage_lsu_system__T_14 = exe_stage_lsu_system__T_13 | exe_stage_lsu_system_pending_fun_sw; // @[riscv_isa.scala 144:24]
  wire  exe_stage_lsu_system__T_15 = exe_stage_lsu_system__T_14 | exe_stage_lsu_system_pending_fun_sd; // @[riscv_isa.scala 144:29]
  wire  exe_stage_lsu_system__T_16 = exe_stage_lsu_system__T_15 | exe_stage_lsu_system_pending_fun_fsw; // @[riscv_isa.scala 144:34]
  wire  exe_stage_lsu_system__T_17 = exe_stage_lsu_system__T_16 | exe_stage_lsu_system_pending_fun_fsd; // @[riscv_isa.scala 144:40]
  wire  exe_stage_lsu_system__T_18 = exe_stage_lsu_system_pending_fun_sc_d | exe_stage_lsu_system_pending_fun_sc_w; // @[riscv_isa.scala 140:20]
  wire  exe_stage_lsu_system__T_19 = ~exe_stage_lsu_system__T_18; // @[IO_Lsu.scala 62:40]
  wire  exe_stage_lsu_system__T_20 = exe_stage_lsu_system__T_17 & exe_stage_lsu_system__T_19; // @[IO_Lsu.scala 62:38]
  wire [2:0] exe_stage_lsu_system__io_getPut_bits_res_T = exe_stage_lsu_system_pending_param_dat_op1[2:0]; // @[riscv_isa.scala 907:38]
  wire [5:0] exe_stage_lsu_system__io_getPut_bits_res_T_1 = {exe_stage_lsu_system__io_getPut_bits_res_T, 3'h0}; // @[riscv_isa.scala 907:61]
  wire [126:0] _GEN_778 = {{63'd0}, exe_stage_lsu_system_pending_param_dat_op2}; // @[riscv_isa.scala 907:28]
  wire [126:0] exe_stage_lsu_system__io_getPut_bits_res_T_2 = _GEN_778 << exe_stage_lsu_system__io_getPut_bits_res_T_1; // @[riscv_isa.scala 907:28]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T = exe_stage_lsu_system_pending_fun_lb |
    exe_stage_lsu_system_pending_fun_lbu; // @[riscv_isa.scala 153:20]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_1 = exe_stage_lsu_system__io_getPut_bits_wstrb_T |
    exe_stage_lsu_system_pending_fun_sb; // @[riscv_isa.scala 153:26]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_2 = exe_stage_lsu_system_pending_fun_lh |
    exe_stage_lsu_system_pending_fun_lhu; // @[riscv_isa.scala 154:20]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_3 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_2 |
    exe_stage_lsu_system_pending_fun_sh; // @[riscv_isa.scala 154:26]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_4 = exe_stage_lsu_system_pending_fun_lw |
    exe_stage_lsu_system_pending_fun_lwu; // @[riscv_isa.scala 155:20]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_5 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_4 |
    exe_stage_lsu_system_pending_fun_sw; // @[riscv_isa.scala 155:26]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_6 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_5 |
    exe_stage_lsu_system_pending_fun_amoswap_w; // @[riscv_isa.scala 155:31]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_7 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_6 |
    exe_stage_lsu_system_pending_fun_amoadd_w; // @[riscv_isa.scala 155:43]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_8 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_7 |
    exe_stage_lsu_system_pending_fun_amoxor_w; // @[riscv_isa.scala 155:54]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_9 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_8 |
    exe_stage_lsu_system_pending_fun_amoand_w; // @[riscv_isa.scala 155:65]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_10 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_9 |
    exe_stage_lsu_system_pending_fun_amoor_w; // @[riscv_isa.scala 155:76]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_11 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_10 |
    exe_stage_lsu_system_pending_fun_amomin_w; // @[riscv_isa.scala 155:86]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_12 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_11 |
    exe_stage_lsu_system_pending_fun_amomax_w; // @[riscv_isa.scala 155:97]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_13 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_12 |
    exe_stage_lsu_system_pending_fun_amominu_w; // @[riscv_isa.scala 155:108]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_14 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_13 |
    exe_stage_lsu_system_pending_fun_amomaxu_w; // @[riscv_isa.scala 155:120]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_15 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_14 |
    exe_stage_lsu_system_pending_fun_flw; // @[riscv_isa.scala 155:132]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_16 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_15 |
    exe_stage_lsu_system_pending_fun_fsw; // @[riscv_isa.scala 155:138]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_17 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_16 |
    exe_stage_lsu_system_pending_fun_lr_w; // @[riscv_isa.scala 155:144]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_18 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_17 |
    exe_stage_lsu_system_pending_fun_sc_w; // @[riscv_isa.scala 155:151]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_19 = exe_stage_lsu_system_pending_fun_ld |
    exe_stage_lsu_system_pending_fun_lr_d; // @[riscv_isa.scala 156:20]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_20 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_19 |
    exe_stage_lsu_system_pending_fun_fld; // @[riscv_isa.scala 156:27]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_21 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_20 |
    exe_stage_lsu_system_pending_fun_sd; // @[riscv_isa.scala 156:33]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_22 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_21 |
    exe_stage_lsu_system_pending_fun_sc_d; // @[riscv_isa.scala 156:38]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_23 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_22 |
    exe_stage_lsu_system_pending_fun_fsd; // @[riscv_isa.scala 156:45]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_24 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_23 |
    exe_stage_lsu_system_pending_fun_amoswap_d; // @[riscv_isa.scala 156:51]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_25 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_24 |
    exe_stage_lsu_system_pending_fun_amoadd_d; // @[riscv_isa.scala 156:63]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_26 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_25 |
    exe_stage_lsu_system_pending_fun_amoxor_d; // @[riscv_isa.scala 156:74]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_27 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_26 |
    exe_stage_lsu_system_pending_fun_amoand_d; // @[riscv_isa.scala 156:85]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_28 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_27 |
    exe_stage_lsu_system_pending_fun_amoor_d; // @[riscv_isa.scala 156:96]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_29 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_28 |
    exe_stage_lsu_system_pending_fun_amomin_d; // @[riscv_isa.scala 156:106]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_30 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_29 |
    exe_stage_lsu_system_pending_fun_amomax_d; // @[riscv_isa.scala 156:117]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_31 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_30 |
    exe_stage_lsu_system_pending_fun_amominu_d; // @[riscv_isa.scala 156:128]
  wire  exe_stage_lsu_system__io_getPut_bits_wstrb_T_32 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_31 |
    exe_stage_lsu_system_pending_fun_amomaxu_d; // @[riscv_isa.scala 156:140]
  wire [1:0] exe_stage_lsu_system__io_getPut_bits_wstrb_T_34 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_3 ? 2'h3 : 2'h0
    ; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_system__io_getPut_bits_wstrb_T_35 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_18 ? 4'hf : 4'h0
    ; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_system__io_getPut_bits_wstrb_T_36 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_32 ? 8'hff
     : 8'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_316 = {{1'd0}, exe_stage_lsu_system__io_getPut_bits_wstrb_T_1}; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_system__io_getPut_bits_wstrb_T_37 = _GEN_316 |
    exe_stage_lsu_system__io_getPut_bits_wstrb_T_34; // @[Mux.scala 27:73]
  wire [3:0] _GEN_317 = {{2'd0}, exe_stage_lsu_system__io_getPut_bits_wstrb_T_37}; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_system__io_getPut_bits_wstrb_T_38 = _GEN_317 |
    exe_stage_lsu_system__io_getPut_bits_wstrb_T_35; // @[Mux.scala 27:73]
  wire [7:0] _GEN_318 = {{4'd0}, exe_stage_lsu_system__io_getPut_bits_wstrb_T_38}; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_system__io_getPut_bits_wstrb_T_39 = _GEN_318 |
    exe_stage_lsu_system__io_getPut_bits_wstrb_T_36; // @[Mux.scala 27:73]
  wire [14:0] _GEN_779 = {{7'd0}, exe_stage_lsu_system__io_getPut_bits_wstrb_T_39}; // @[riscv_isa.scala 916:10]
  wire [14:0] exe_stage_lsu_system__io_getPut_bits_wstrb_T_41 = _GEN_779 << exe_stage_lsu_system__io_getPut_bits_res_T; // @[riscv_isa.scala 916:10]
  wire  exe_stage_lsu_system__T_22 = ~exe_stage_lsu_system_reset; // @[IO_Lsu.scala 73:15]
  wire [31:0] exe_stage_lsu_system_io_getPut_bits_a_1_address = exe_stage_lsu_system__io_getPut_bits_T_1[31:0]; // @[Edges.scala 483:17 488:15]
  wire [7:0] exe_stage_lsu_system_io_getPut_bits_wstrb = exe_stage_lsu_system__io_getPut_bits_wstrb_T_41[7:0]; // @[riscv_isa.scala 912:21 913:11]
  wire [63:0] exe_stage_lsu_system_io_getPut_bits_res = exe_stage_lsu_system__io_getPut_bits_res_T_2[63:0]; // @[riscv_isa.scala 906:21 907:11]
  wire  exe_stage_lsu_system__T_24 = exe_stage_lsu_system_io_enq_ready & exe_stage_lsu_system_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_system__T_28 = ~exe_stage_lsu_system__io_is_empty_T; // @[IO_Lsu.scala 85:11]
  wire  exe_stage_lsu_system__T_32 = ~exe_stage_lsu_system__io_getPut_valid_T; // @[IO_Lsu.scala 86:11]
  wire  exe_stage_lsu_system__T_33 = exe_stage_lsu_system_io_getPut_ready & exe_stage_lsu_system_io_getPut_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_system__T_34 = exe_stage_lsu_system_io_access_ready & exe_stage_lsu_system_io_access_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_system__T_35 = exe_stage_lsu_system__T_33 & exe_stage_lsu_system__T_34; // @[IO_Lsu.scala 89:31]
  wire  exe_stage_lsu_system__GEN_24 = exe_stage_lsu_system__T_34 ? 1'h0 : exe_stage_lsu_system_is_busy; // @[IO_Lsu.scala 96:32 98:13 45:27]
  wire  exe_stage_lsu_system__GEN_25 = exe_stage_lsu_system__T_34 ? 1'h0 : exe_stage_lsu_system_isTransing; // @[IO_Lsu.scala 96:32 99:16 46:27]
  wire  exe_stage_lsu_system__GEN_26 = exe_stage_lsu_system__T_33 | exe_stage_lsu_system__GEN_25; // @[IO_Lsu.scala 93:33 95:16]
  wire  exe_stage_lsu_system__GEN_27 = exe_stage_lsu_system__T_33 ? exe_stage_lsu_system_is_busy :
    exe_stage_lsu_system__GEN_24; // @[IO_Lsu.scala 45:27 93:33]
  wire  exe_stage_lsu_system__GEN_28 = exe_stage_lsu_system__T_35 ? 1'h0 : exe_stage_lsu_system__GEN_27; // @[IO_Lsu.scala 89:50 90:13]
  wire  exe_stage_lsu_system__GEN_74 = exe_stage_lsu_system__T_24 | exe_stage_lsu_system__GEN_28; // @[IO_Lsu.scala 84:23 88:13]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_align_align_data_T_4 =
    exe_stage_lsu_system_io_access_bits_data >> exe_stage_lsu_system__io_getPut_bits_res_T_1; // @[Util.scala 147:26]
  wire  exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_2 = exe_stage_lsu_system_pending_fun_lbu |
    exe_stage_lsu_system_pending_fun_lhu; // @[riscv_isa.scala 158:20]
  wire  exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_3 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_2 | exe_stage_lsu_system_pending_fun_lwu; // @[riscv_isa.scala 158:26]
  wire  exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_4 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_align_align_data_T_4[7]; // @[Util.scala 120:90]
  wire  exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_5 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_4; // @[Util.scala 120:71]
  wire [55:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_7 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_5 ? 56'hffffffffffffff : 56'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_8 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_align_align_data_T_4[7:0]; // @[Util.scala 120:104]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_9 = {
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_7,exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_8}; // @[Cat.scala 33:92]
  wire  exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_14 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_align_align_data_T_4[15]; // @[Util.scala 121:90]
  wire  exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_15 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_14; // @[Util.scala 121:71]
  wire [47:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_17 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_15 ? 48'hffffffffffff : 48'h0; // @[Bitwise.scala 77:12]
  wire [15:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_18 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_align_align_data_T_4[15:0]; // @[Util.scala 121:104]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_19 = {
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_17,exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_18}
    ; // @[Cat.scala 33:92]
  wire  exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_37 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_align_align_data_T_4[31]; // @[Util.scala 122:90]
  wire  exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_38 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_37; // @[Util.scala 122:71]
  wire [31:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_40 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_38 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [31:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_41 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_align_align_data_T_4[31:0]; // @[Util.scala 122:104]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_42 = {
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_40,exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_41}
    ; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_57 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_1
     ? exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_9 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_58 = exe_stage_lsu_system__io_getPut_bits_wstrb_T_3
     ? exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_19 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_59 =
    exe_stage_lsu_system__io_getPut_bits_wstrb_T_18 ? exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_42 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_60 =
    exe_stage_lsu_system__io_getPut_bits_wstrb_T_32 ?
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_align_align_data_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_61 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_57 |
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_58; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_62 =
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_61 |
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_59; // @[Mux.scala 27:73]
  wire  _GEN_327 = exe_stage_lsu_system__T_24 & exe_stage_lsu_system__T_22; // @[IO_Lsu.scala 85:11]
  wire  _GEN_329 = ~exe_stage_lsu_system__T_24; // @[IO_Lsu.scala 92:11]
  wire  _GEN_333 = _GEN_329 & ~exe_stage_lsu_system__T_35; // @[IO_Lsu.scala 94:11]
  wire  exe_stage_lsu_periph_clock;
  wire  exe_stage_lsu_periph_reset;
  wire  exe_stage_lsu_periph_io_enq_ready;
  wire  exe_stage_lsu_periph_io_enq_valid;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_lb;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_lh;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_lw;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_ld;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_lbu;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_lhu;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_lwu;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_sb;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_sh;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_sw;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_sd;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_lr_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_sc_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoand_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoor_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amomin_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amomax_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amominu_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_lr_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_sc_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoand_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amoor_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amomin_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amomax_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amominu_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_flw;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_fsw;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_fld;
  wire  exe_stage_lsu_periph_io_enq_bits_fun_fsd;
  wire  exe_stage_lsu_periph_io_deq_ready;
  wire  exe_stage_lsu_periph_io_deq_valid;
  wire [5:0] exe_stage_lsu_periph_io_deq_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_periph_io_deq_bits_wb_res;
  wire  exe_stage_lsu_periph_io_deq_bits_is_load_amo;
  wire  exe_stage_lsu_periph_io_deq_bits_is_flw;
  wire  exe_stage_lsu_periph_io_deq_bits_is_fld;
  wire  exe_stage_lsu_periph_io_is_empty;
  wire  exe_stage_lsu_periph_io_getPut_ready;
  wire  exe_stage_lsu_periph_io_getPut_valid;
  wire [2:0] exe_stage_lsu_periph_io_getPut_bits_opcode;
  wire [2:0] exe_stage_lsu_periph_io_getPut_bits_param;
  wire [1:0] exe_stage_lsu_periph_io_getPut_bits_size;
  wire  exe_stage_lsu_periph_io_getPut_bits_source;
  wire [31:0] exe_stage_lsu_periph_io_getPut_bits_address;
  wire [7:0] exe_stage_lsu_periph_io_getPut_bits_mask;
  wire [63:0] exe_stage_lsu_periph_io_getPut_bits_data;
  wire  exe_stage_lsu_periph_io_getPut_bits_corrupt;
  wire  exe_stage_lsu_periph_io_access_ready;
  wire  exe_stage_lsu_periph_io_access_valid;
  wire [2:0] exe_stage_lsu_periph_io_access_bits_opcode;
  wire [63:0] exe_stage_lsu_periph_io_access_bits_data;
  reg  exe_stage_lsu_periph_is_busy; // @[IO_Lsu.scala 45:27]
  reg  exe_stage_lsu_periph_isTransing; // @[IO_Lsu.scala 46:27]
  reg  exe_stage_lsu_periph_pending_fun_lb; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_lh; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_lw; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_ld; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_lbu; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_lhu; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_lwu; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_sb; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_sh; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_sw; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_sd; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_lr_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_sc_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoswap_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoadd_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoxor_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoand_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoor_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amomin_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amomax_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amominu_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amomaxu_w; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_lr_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_sc_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoswap_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoadd_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoxor_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoand_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amoor_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amomin_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amomax_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amominu_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_amomaxu_d; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_flw; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_fsw; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_fld; // @[IO_Lsu.scala 47:20]
  reg  exe_stage_lsu_periph_pending_fun_fsd; // @[IO_Lsu.scala 47:20]
  reg [5:0] exe_stage_lsu_periph_pending_param_rd0; // @[IO_Lsu.scala 47:20]
  reg [63:0] exe_stage_lsu_periph_pending_param_dat_op1; // @[IO_Lsu.scala 47:20]
  reg [63:0] exe_stage_lsu_periph_pending_param_dat_op2; // @[IO_Lsu.scala 47:20]
  wire  exe_stage_lsu_periph__io_is_empty_T = ~exe_stage_lsu_periph_is_busy; // @[IO_Lsu.scala 49:18]
  wire  exe_stage_lsu_periph__io_getPut_valid_T = ~exe_stage_lsu_periph_isTransing; // @[IO_Lsu.scala 51:32]
  wire  exe_stage_lsu_periph__T = exe_stage_lsu_periph_pending_fun_lb | exe_stage_lsu_periph_pending_fun_lh; // @[riscv_isa.scala 143:19]
  wire  exe_stage_lsu_periph__T_1 = exe_stage_lsu_periph__T | exe_stage_lsu_periph_pending_fun_lw; // @[riscv_isa.scala 143:24]
  wire  exe_stage_lsu_periph__T_2 = exe_stage_lsu_periph__T_1 | exe_stage_lsu_periph_pending_fun_ld; // @[riscv_isa.scala 143:29]
  wire  exe_stage_lsu_periph__T_3 = exe_stage_lsu_periph__T_2 | exe_stage_lsu_periph_pending_fun_lbu; // @[riscv_isa.scala 143:34]
  wire  exe_stage_lsu_periph__T_4 = exe_stage_lsu_periph__T_3 | exe_stage_lsu_periph_pending_fun_lhu; // @[riscv_isa.scala 143:40]
  wire  exe_stage_lsu_periph__T_5 = exe_stage_lsu_periph__T_4 | exe_stage_lsu_periph_pending_fun_lwu; // @[riscv_isa.scala 143:46]
  wire  exe_stage_lsu_periph__T_6 = exe_stage_lsu_periph__T_5 | exe_stage_lsu_periph_pending_fun_flw; // @[riscv_isa.scala 143:52]
  wire  exe_stage_lsu_periph__T_7 = exe_stage_lsu_periph__T_6 | exe_stage_lsu_periph_pending_fun_fld; // @[riscv_isa.scala 143:59]
  wire  exe_stage_lsu_periph__T_8 = exe_stage_lsu_periph_pending_fun_lr_d | exe_stage_lsu_periph_pending_fun_lr_w; // @[riscv_isa.scala 141:20]
  wire  exe_stage_lsu_periph__T_9 = exe_stage_lsu_periph__T_7 | exe_stage_lsu_periph__T_8; // @[riscv_isa.scala 143:65]
  wire  exe_stage_lsu_periph__T_11 = ~exe_stage_lsu_periph__T_8; // @[IO_Lsu.scala 55:31]
  wire  exe_stage_lsu_periph__T_12 = exe_stage_lsu_periph__T_9 & exe_stage_lsu_periph__T_11; // @[IO_Lsu.scala 55:29]
  wire [63:0] exe_stage_lsu_periph__io_getPut_bits_T = {{3'd0}, exe_stage_lsu_periph_pending_param_dat_op1[63:3]}; // @[IO_Lsu.scala 59:39]
  wire [66:0] exe_stage_lsu_periph__io_getPut_bits_T_1 = {exe_stage_lsu_periph__io_getPut_bits_T, 3'h0}; // @[IO_Lsu.scala 59:59]
  wire  exe_stage_lsu_periph__T_13 = exe_stage_lsu_periph_pending_fun_sb | exe_stage_lsu_periph_pending_fun_sh; // @[riscv_isa.scala 144:19]
  wire  exe_stage_lsu_periph__T_14 = exe_stage_lsu_periph__T_13 | exe_stage_lsu_periph_pending_fun_sw; // @[riscv_isa.scala 144:24]
  wire  exe_stage_lsu_periph__T_15 = exe_stage_lsu_periph__T_14 | exe_stage_lsu_periph_pending_fun_sd; // @[riscv_isa.scala 144:29]
  wire  exe_stage_lsu_periph__T_16 = exe_stage_lsu_periph__T_15 | exe_stage_lsu_periph_pending_fun_fsw; // @[riscv_isa.scala 144:34]
  wire  exe_stage_lsu_periph__T_17 = exe_stage_lsu_periph__T_16 | exe_stage_lsu_periph_pending_fun_fsd; // @[riscv_isa.scala 144:40]
  wire  exe_stage_lsu_periph__T_18 = exe_stage_lsu_periph_pending_fun_sc_d | exe_stage_lsu_periph_pending_fun_sc_w; // @[riscv_isa.scala 140:20]
  wire  exe_stage_lsu_periph__T_19 = ~exe_stage_lsu_periph__T_18; // @[IO_Lsu.scala 62:40]
  wire  exe_stage_lsu_periph__T_20 = exe_stage_lsu_periph__T_17 & exe_stage_lsu_periph__T_19; // @[IO_Lsu.scala 62:38]
  wire [2:0] exe_stage_lsu_periph__io_getPut_bits_res_T = exe_stage_lsu_periph_pending_param_dat_op1[2:0]; // @[riscv_isa.scala 907:38]
  wire [5:0] exe_stage_lsu_periph__io_getPut_bits_res_T_1 = {exe_stage_lsu_periph__io_getPut_bits_res_T, 3'h0}; // @[riscv_isa.scala 907:61]
  wire [126:0] _GEN_790 = {{63'd0}, exe_stage_lsu_periph_pending_param_dat_op2}; // @[riscv_isa.scala 907:28]
  wire [126:0] exe_stage_lsu_periph__io_getPut_bits_res_T_2 = _GEN_790 << exe_stage_lsu_periph__io_getPut_bits_res_T_1; // @[riscv_isa.scala 907:28]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T = exe_stage_lsu_periph_pending_fun_lb |
    exe_stage_lsu_periph_pending_fun_lbu; // @[riscv_isa.scala 153:20]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_1 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T |
    exe_stage_lsu_periph_pending_fun_sb; // @[riscv_isa.scala 153:26]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_2 = exe_stage_lsu_periph_pending_fun_lh |
    exe_stage_lsu_periph_pending_fun_lhu; // @[riscv_isa.scala 154:20]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_3 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_2 |
    exe_stage_lsu_periph_pending_fun_sh; // @[riscv_isa.scala 154:26]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_4 = exe_stage_lsu_periph_pending_fun_lw |
    exe_stage_lsu_periph_pending_fun_lwu; // @[riscv_isa.scala 155:20]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_5 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_4 |
    exe_stage_lsu_periph_pending_fun_sw; // @[riscv_isa.scala 155:26]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_6 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_5 |
    exe_stage_lsu_periph_pending_fun_amoswap_w; // @[riscv_isa.scala 155:31]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_7 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_6 |
    exe_stage_lsu_periph_pending_fun_amoadd_w; // @[riscv_isa.scala 155:43]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_8 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_7 |
    exe_stage_lsu_periph_pending_fun_amoxor_w; // @[riscv_isa.scala 155:54]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_9 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_8 |
    exe_stage_lsu_periph_pending_fun_amoand_w; // @[riscv_isa.scala 155:65]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_10 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_9 |
    exe_stage_lsu_periph_pending_fun_amoor_w; // @[riscv_isa.scala 155:76]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_11 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_10 |
    exe_stage_lsu_periph_pending_fun_amomin_w; // @[riscv_isa.scala 155:86]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_12 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_11 |
    exe_stage_lsu_periph_pending_fun_amomax_w; // @[riscv_isa.scala 155:97]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_13 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_12 |
    exe_stage_lsu_periph_pending_fun_amominu_w; // @[riscv_isa.scala 155:108]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_14 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_13 |
    exe_stage_lsu_periph_pending_fun_amomaxu_w; // @[riscv_isa.scala 155:120]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_15 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_14 |
    exe_stage_lsu_periph_pending_fun_flw; // @[riscv_isa.scala 155:132]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_16 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_15 |
    exe_stage_lsu_periph_pending_fun_fsw; // @[riscv_isa.scala 155:138]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_17 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_16 |
    exe_stage_lsu_periph_pending_fun_lr_w; // @[riscv_isa.scala 155:144]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_18 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_17 |
    exe_stage_lsu_periph_pending_fun_sc_w; // @[riscv_isa.scala 155:151]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_19 = exe_stage_lsu_periph_pending_fun_ld |
    exe_stage_lsu_periph_pending_fun_lr_d; // @[riscv_isa.scala 156:20]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_20 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_19 |
    exe_stage_lsu_periph_pending_fun_fld; // @[riscv_isa.scala 156:27]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_21 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_20 |
    exe_stage_lsu_periph_pending_fun_sd; // @[riscv_isa.scala 156:33]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_22 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_21 |
    exe_stage_lsu_periph_pending_fun_sc_d; // @[riscv_isa.scala 156:38]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_23 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_22 |
    exe_stage_lsu_periph_pending_fun_fsd; // @[riscv_isa.scala 156:45]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_24 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_23 |
    exe_stage_lsu_periph_pending_fun_amoswap_d; // @[riscv_isa.scala 156:51]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_25 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_24 |
    exe_stage_lsu_periph_pending_fun_amoadd_d; // @[riscv_isa.scala 156:63]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_26 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_25 |
    exe_stage_lsu_periph_pending_fun_amoxor_d; // @[riscv_isa.scala 156:74]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_27 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_26 |
    exe_stage_lsu_periph_pending_fun_amoand_d; // @[riscv_isa.scala 156:85]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_28 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_27 |
    exe_stage_lsu_periph_pending_fun_amoor_d; // @[riscv_isa.scala 156:96]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_29 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_28 |
    exe_stage_lsu_periph_pending_fun_amomin_d; // @[riscv_isa.scala 156:106]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_30 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_29 |
    exe_stage_lsu_periph_pending_fun_amomax_d; // @[riscv_isa.scala 156:117]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_31 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_30 |
    exe_stage_lsu_periph_pending_fun_amominu_d; // @[riscv_isa.scala 156:128]
  wire  exe_stage_lsu_periph__io_getPut_bits_wstrb_T_32 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_31 |
    exe_stage_lsu_periph_pending_fun_amomaxu_d; // @[riscv_isa.scala 156:140]
  wire [1:0] exe_stage_lsu_periph__io_getPut_bits_wstrb_T_34 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_3 ? 2'h3 : 2'h0
    ; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_periph__io_getPut_bits_wstrb_T_35 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_18 ? 4'hf : 4'h0
    ; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_periph__io_getPut_bits_wstrb_T_36 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_32 ? 8'hff
     : 8'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_355 = {{1'd0}, exe_stage_lsu_periph__io_getPut_bits_wstrb_T_1}; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_periph__io_getPut_bits_wstrb_T_37 = _GEN_355 |
    exe_stage_lsu_periph__io_getPut_bits_wstrb_T_34; // @[Mux.scala 27:73]
  wire [3:0] _GEN_356 = {{2'd0}, exe_stage_lsu_periph__io_getPut_bits_wstrb_T_37}; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_periph__io_getPut_bits_wstrb_T_38 = _GEN_356 |
    exe_stage_lsu_periph__io_getPut_bits_wstrb_T_35; // @[Mux.scala 27:73]
  wire [7:0] _GEN_357 = {{4'd0}, exe_stage_lsu_periph__io_getPut_bits_wstrb_T_38}; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_periph__io_getPut_bits_wstrb_T_39 = _GEN_357 |
    exe_stage_lsu_periph__io_getPut_bits_wstrb_T_36; // @[Mux.scala 27:73]
  wire [14:0] _GEN_791 = {{7'd0}, exe_stage_lsu_periph__io_getPut_bits_wstrb_T_39}; // @[riscv_isa.scala 916:10]
  wire [14:0] exe_stage_lsu_periph__io_getPut_bits_wstrb_T_41 = _GEN_791 << exe_stage_lsu_periph__io_getPut_bits_res_T; // @[riscv_isa.scala 916:10]
  wire  exe_stage_lsu_periph__T_22 = ~exe_stage_lsu_periph_reset; // @[IO_Lsu.scala 73:15]
  wire [31:0] exe_stage_lsu_periph_io_getPut_bits_a_1_address = exe_stage_lsu_periph__io_getPut_bits_T_1[31:0]; // @[Edges.scala 483:17 488:15]
  wire [7:0] exe_stage_lsu_periph_io_getPut_bits_wstrb = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_41[7:0]; // @[riscv_isa.scala 912:21 913:11]
  wire [63:0] exe_stage_lsu_periph_io_getPut_bits_res = exe_stage_lsu_periph__io_getPut_bits_res_T_2[63:0]; // @[riscv_isa.scala 906:21 907:11]
  wire  exe_stage_lsu_periph__T_24 = exe_stage_lsu_periph_io_enq_ready & exe_stage_lsu_periph_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_periph__T_28 = ~exe_stage_lsu_periph__io_is_empty_T; // @[IO_Lsu.scala 85:11]
  wire  exe_stage_lsu_periph__T_32 = ~exe_stage_lsu_periph__io_getPut_valid_T; // @[IO_Lsu.scala 86:11]
  wire  exe_stage_lsu_periph__T_33 = exe_stage_lsu_periph_io_getPut_ready & exe_stage_lsu_periph_io_getPut_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_periph__T_34 = exe_stage_lsu_periph_io_access_ready & exe_stage_lsu_periph_io_access_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_periph__T_35 = exe_stage_lsu_periph__T_33 & exe_stage_lsu_periph__T_34; // @[IO_Lsu.scala 89:31]
  wire  exe_stage_lsu_periph__GEN_24 = exe_stage_lsu_periph__T_34 ? 1'h0 : exe_stage_lsu_periph_is_busy; // @[IO_Lsu.scala 96:32 98:13 45:27]
  wire  exe_stage_lsu_periph__GEN_25 = exe_stage_lsu_periph__T_34 ? 1'h0 : exe_stage_lsu_periph_isTransing; // @[IO_Lsu.scala 96:32 99:16 46:27]
  wire  exe_stage_lsu_periph__GEN_26 = exe_stage_lsu_periph__T_33 | exe_stage_lsu_periph__GEN_25; // @[IO_Lsu.scala 93:33 95:16]
  wire  exe_stage_lsu_periph__GEN_27 = exe_stage_lsu_periph__T_33 ? exe_stage_lsu_periph_is_busy :
    exe_stage_lsu_periph__GEN_24; // @[IO_Lsu.scala 45:27 93:33]
  wire  exe_stage_lsu_periph__GEN_28 = exe_stage_lsu_periph__T_35 ? 1'h0 : exe_stage_lsu_periph__GEN_27; // @[IO_Lsu.scala 89:50 90:13]
  wire  exe_stage_lsu_periph__GEN_74 = exe_stage_lsu_periph__T_24 | exe_stage_lsu_periph__GEN_28; // @[IO_Lsu.scala 84:23 88:13]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_align_align_data_T_4 =
    exe_stage_lsu_periph_io_access_bits_data >> exe_stage_lsu_periph__io_getPut_bits_res_T_1; // @[Util.scala 147:26]
  wire  exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_2 = exe_stage_lsu_periph_pending_fun_lbu |
    exe_stage_lsu_periph_pending_fun_lhu; // @[riscv_isa.scala 158:20]
  wire  exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_3 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_2 | exe_stage_lsu_periph_pending_fun_lwu; // @[riscv_isa.scala 158:26]
  wire  exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_4 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_align_align_data_T_4[7]; // @[Util.scala 120:90]
  wire  exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_5 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_4; // @[Util.scala 120:71]
  wire [55:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_7 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_5 ? 56'hffffffffffffff : 56'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_8 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_align_align_data_T_4[7:0]; // @[Util.scala 120:104]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_9 = {
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_7,exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_8}; // @[Cat.scala 33:92]
  wire  exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_14 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_align_align_data_T_4[15]; // @[Util.scala 121:90]
  wire  exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_15 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_14; // @[Util.scala 121:71]
  wire [47:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_17 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_15 ? 48'hffffffffffff : 48'h0; // @[Bitwise.scala 77:12]
  wire [15:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_18 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_align_align_data_T_4[15:0]; // @[Util.scala 121:104]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_19 = {
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_17,exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_18}
    ; // @[Cat.scala 33:92]
  wire  exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_37 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_align_align_data_T_4[31]; // @[Util.scala 122:90]
  wire  exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_38 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_37; // @[Util.scala 122:71]
  wire [31:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_40 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_38 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [31:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_41 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_align_align_data_T_4[31:0]; // @[Util.scala 122:104]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_42 = {
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_40,exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_41}
    ; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_57 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_1
     ? exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_9 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_58 = exe_stage_lsu_periph__io_getPut_bits_wstrb_T_3
     ? exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_19 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_59 =
    exe_stage_lsu_periph__io_getPut_bits_wstrb_T_18 ? exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_42 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_60 =
    exe_stage_lsu_periph__io_getPut_bits_wstrb_T_32 ?
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_align_align_data_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_61 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_57 |
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_58; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_62 =
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_61 |
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_59; // @[Mux.scala 27:73]
  wire  _GEN_366 = exe_stage_lsu_periph__T_24 & exe_stage_lsu_periph__T_22; // @[IO_Lsu.scala 85:11]
  wire  _GEN_368 = ~exe_stage_lsu_periph__T_24; // @[IO_Lsu.scala 92:11]
  wire  _GEN_372 = _GEN_368 & ~exe_stage_lsu_periph__T_35; // @[IO_Lsu.scala 94:11]
  wire  exe_stage_lsu_cache_0_clock;
  wire  exe_stage_lsu_cache_0_reset;
  wire  exe_stage_lsu_cache_0_io_enq_ready;
  wire  exe_stage_lsu_cache_0_io_enq_valid;
  wire [31:0] exe_stage_lsu_cache_0_io_enq_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_io_enq_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_io_enq_bits_wstrb;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_io_enq_bits_fun_fsd;
  wire [5:0] exe_stage_lsu_cache_0_io_enq_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_io_deq_ready;
  wire  exe_stage_lsu_cache_0_io_deq_valid;
  wire  exe_stage_lsu_cache_0_io_deq_bits_chkIdx;
  wire [5:0] exe_stage_lsu_cache_0_io_deq_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_cache_0_io_deq_bits_wb_res;
  wire  exe_stage_lsu_cache_0_io_deq_bits_is_load_amo;
  wire  exe_stage_lsu_cache_0_io_deq_bits_is_flw;
  wire  exe_stage_lsu_cache_0_io_deq_bits_is_fld;
  wire  exe_stage_lsu_cache_0_io_is_empty;
  wire  exe_stage_lsu_cache_0_io_flush;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_ready;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_valid;
  wire [2:0] exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_opcode;
  wire [2:0] exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_param;
  wire [2:0] exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_size;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_source;
  wire [31:0] exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_address;
  wire [7:0] exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_mask;
  wire [63:0] exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_data;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_corrupt;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_grant_ready;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_grant_valid;
  wire [2:0] exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_opcode;
  wire [2:0] exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_size;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_source;
  wire [4:0] exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_sink;
  wire [63:0] exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_data;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_ready;
  wire  exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_valid;
  wire [4:0] exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_bits_sink;
  wire  exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_ready;
  wire  exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_valid;
  wire [31:0] exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_bits_address;
  wire  exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_ready;
  wire  exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_valid;
  wire [2:0] exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_opcode;
  wire [2:0] exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_param;
  wire [2:0] exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_size;
  wire  exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_source;
  wire [31:0] exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_address;
  wire [63:0] exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_data;
  wire  exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_corrupt;
  wire  exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_ready;
  wire  exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_valid;
  wire  exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_bits_source;
  wire  exe_stage_lsu_cache_0_missUnit_clock;
  wire  exe_stage_lsu_cache_0_missUnit_reset;
  wire  exe_stage_lsu_cache_0_missUnit_io_req_valid;
  wire [31:0] exe_stage_lsu_cache_0_missUnit_io_req_bits_paddr;
  wire  exe_stage_lsu_cache_0_missUnit_io_rsp_ready;
  wire  exe_stage_lsu_cache_0_missUnit_io_rsp_valid;
  wire [31:0] exe_stage_lsu_cache_0_missUnit_io_rsp_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_missUnit_io_rsp_bits_wdata;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_acquire_ready;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_acquire_valid;
  wire [2:0] exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_opcode;
  wire [2:0] exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_param;
  wire [2:0] exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_size;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_source;
  wire [31:0] exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_address;
  wire [7:0] exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_mask;
  wire [63:0] exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_data;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_corrupt;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_grant_ready;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_grant_valid;
  wire [2:0] exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_opcode;
  wire [2:0] exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_size;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_source;
  wire [4:0] exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_sink;
  wire [63:0] exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_data;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_ready;
  wire  exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_valid;
  wire [4:0] exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_bits_sink;
  wire  exe_stage_lsu_cache_0_missUnit_io_miss_ban;
  wire  exe_stage_lsu_cache_0_missUnit_io_release_ban;
  reg [31:0] exe_stage_lsu_cache_0_missUnit_miss_queue_0_paddr; // @[MissUnit.scala 56:27]
  reg [31:0] exe_stage_lsu_cache_0_missUnit_miss_queue_1_paddr; // @[MissUnit.scala 56:27]
  reg  exe_stage_lsu_cache_0_missUnit_miss_valid_0; // @[MissUnit.scala 59:27]
  reg  exe_stage_lsu_cache_0_missUnit_miss_valid_1; // @[MissUnit.scala 59:27]
  reg [63:0] exe_stage_lsu_cache_0_missUnit_miss_rsp_0; // @[MissUnit.scala 62:25]
  reg [63:0] exe_stage_lsu_cache_0_missUnit_miss_rsp_1; // @[MissUnit.scala 62:25]
  reg [2:0] exe_stage_lsu_cache_0_missUnit_mshr_state_qout; // @[MissUnit.scala 65:32]
  wire  exe_stage_lsu_cache_0_missUnit__T = exe_stage_lsu_cache_0_missUnit_io_cache_grant_ready &
    exe_stage_lsu_cache_0_missUnit_io_cache_grant_valid; // @[Decoupled.scala 52:35]
  wire [10:0] exe_stage_lsu_cache_0_missUnit__beats1_decode_T_1 = 11'hf <<
    exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_size; // @[package.scala 234:77]
  wire [3:0] exe_stage_lsu_cache_0_missUnit__beats1_decode_T_2 = exe_stage_lsu_cache_0_missUnit__beats1_decode_T_1[3:0]; // @[package.scala 234:82]
  wire [3:0] exe_stage_lsu_cache_0_missUnit__beats1_decode_T_3 = ~exe_stage_lsu_cache_0_missUnit__beats1_decode_T_2; // @[package.scala 234:46]
  wire  exe_stage_lsu_cache_0_missUnit_beats1_decode = exe_stage_lsu_cache_0_missUnit__beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  exe_stage_lsu_cache_0_missUnit_beats1_opdata = exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  exe_stage_lsu_cache_0_missUnit_beats1 = exe_stage_lsu_cache_0_missUnit_beats1_opdata &
    exe_stage_lsu_cache_0_missUnit_beats1_decode; // @[Edges.scala 220:14]
  reg  exe_stage_lsu_cache_0_missUnit_counter; // @[Edges.scala 228:27]
  wire  exe_stage_lsu_cache_0_missUnit_counter1 = exe_stage_lsu_cache_0_missUnit_counter - 1'h1; // @[Edges.scala 229:28]
  wire  exe_stage_lsu_cache_0_missUnit_first = ~exe_stage_lsu_cache_0_missUnit_counter; // @[Edges.scala 230:25]
  wire  exe_stage_lsu_cache_0_missUnit__last_T_1 = ~exe_stage_lsu_cache_0_missUnit_beats1; // @[Edges.scala 231:47]
  wire  exe_stage_lsu_cache_0_missUnit_last = exe_stage_lsu_cache_0_missUnit_counter |
    exe_stage_lsu_cache_0_missUnit__last_T_1; // @[Edges.scala 231:37]
  wire  exe_stage_lsu_cache_0_missUnit_is_trans_done = exe_stage_lsu_cache_0_missUnit_last &
    exe_stage_lsu_cache_0_missUnit__T; // @[Edges.scala 232:22]
  wire  exe_stage_lsu_cache_0_missUnit__count_T = ~exe_stage_lsu_cache_0_missUnit_counter1; // @[Edges.scala 233:27]
  wire  exe_stage_lsu_cache_0_missUnit_transCnt = exe_stage_lsu_cache_0_missUnit_beats1 &
    exe_stage_lsu_cache_0_missUnit__count_T; // @[Edges.scala 233:25]
  wire  exe_stage_lsu_cache_0_missUnit_acquire_sel_sel = exe_stage_lsu_cache_0_missUnit_miss_valid_0 ? 1'h0 : 1'h1; // @[MissUnit.scala 75:36]
  wire  exe_stage_lsu_cache_0_missUnit__acquire_sel_T = exe_stage_lsu_cache_0_missUnit_mshr_state_qout == 3'h0; // @[MissUnit.scala 76:26]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_4 = exe_stage_lsu_cache_0_missUnit_miss_valid_0 |
    exe_stage_lsu_cache_0_missUnit_miss_valid_1; // @[MissUnit.scala 103:59]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_5 = ~exe_stage_lsu_cache_0_missUnit_io_miss_ban; // @[MissUnit.scala 103:70]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_6 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_4 &
    exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_5; // @[MissUnit.scala 103:68]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_16 = exe_stage_lsu_cache_0_missUnit__acquire_sel_T &
    exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_6; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_8 = exe_stage_lsu_cache_0_missUnit_mshr_state_qout == 3'h1; // @[MissUnit.scala 104:24]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_9 = exe_stage_lsu_cache_0_missUnit_io_cache_acquire_ready &
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_valid; // @[Decoupled.scala 52:35]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_10 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_9
     ? 2'h2 : 2'h1; // @[MissUnit.scala 104:39]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_17 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_8
     ? exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_10 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_392 = {{1'd0}, exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_16}; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_20 = _GEN_392 |
    exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_17; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_11 = exe_stage_lsu_cache_0_missUnit_mshr_state_qout == 3'h2; // @[MissUnit.scala 105:24]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_12 = exe_stage_lsu_cache_0_missUnit_is_trans_done ? 2'h3
     : 2'h2; // @[MissUnit.scala 105:39]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_18 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_11
     ? exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_12 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_21 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_20
     | exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_18; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_13 = exe_stage_lsu_cache_0_missUnit_mshr_state_qout == 3'h3; // @[MissUnit.scala 106:24]
  wire  exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_14 = exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_ready &
    exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_valid; // @[Decoupled.scala 52:35]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_15 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_14
     ? 2'h0 : 2'h3; // @[MissUnit.scala 106:39]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_19 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_13
     ? exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_15 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_22 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_21
     | exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_19; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_missUnit_mshr_state_dnxt = {{1'd0},
    exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_22}; // @[MissUnit.scala 101:19 64:29]
  wire  exe_stage_lsu_cache_0_missUnit__acquire_sel_T_2 = exe_stage_lsu_cache_0_missUnit_mshr_state_dnxt == 3'h1; // @[MissUnit.scala 76:97]
  wire  exe_stage_lsu_cache_0_missUnit__acquire_sel_T_3 = exe_stage_lsu_cache_0_missUnit__acquire_sel_T &
    exe_stage_lsu_cache_0_missUnit__acquire_sel_T_2; // @[MissUnit.scala 76:79]
  reg  exe_stage_lsu_cache_0_missUnit_acquire_sel_r; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_missUnit_acquire_sel = exe_stage_lsu_cache_0_missUnit__acquire_sel_T ?
    exe_stage_lsu_cache_0_missUnit_acquire_sel_sel : exe_stage_lsu_cache_0_missUnit_acquire_sel_r; // @[MissUnit.scala 76:8]
  reg  exe_stage_lsu_cache_0_missUnit_cache_acquire_vaild; // @[MissUnit.scala 81:37]
  reg  exe_stage_lsu_cache_0_missUnit_cache_grantAck_valid; // @[MissUnit.scala 87:37]
  reg  exe_stage_lsu_cache_0_missUnit_rsp_valid; // @[MissUnit.scala 90:26]
  reg [4:0] exe_stage_lsu_cache_0_missUnit_cache_grant_reg_sink; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_missUnit__T_3 = exe_stage_lsu_cache_0_missUnit__T &
    exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_source; // @[MissUnit.scala 93:33]
  wire  exe_stage_lsu_cache_0_missUnit__T_4 = ~exe_stage_lsu_cache_0_missUnit__T_3; // @[MissUnit.scala 93:11]
  wire  exe_stage_lsu_cache_0_missUnit__T_6 = ~exe_stage_lsu_cache_0_missUnit_reset; // @[MissUnit.scala 93:9]
  wire  exe_stage_lsu_cache_0_missUnit__T_7 = ~exe_stage_lsu_cache_0_missUnit__T_4; // @[MissUnit.scala 93:9]
  wire  exe_stage_lsu_cache_0_missUnit__T_15 = ~exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_8; // @[MissUnit.scala 113:11]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_10 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_9 ? 1'h0 :
    exe_stage_lsu_cache_0_missUnit_cache_acquire_vaild; // @[MissUnit.scala 111:40 112:25 81:37]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_11 = exe_stage_lsu_cache_0_missUnit__acquire_sel_T_3 |
    exe_stage_lsu_cache_0_missUnit__GEN_10; // @[MissUnit.scala 109:61 110:25]
  wire [31:0] exe_stage_lsu_cache_0_missUnit__GEN_13 = exe_stage_lsu_cache_0_missUnit_acquire_sel ?
    exe_stage_lsu_cache_0_missUnit_miss_queue_1_paddr : exe_stage_lsu_cache_0_missUnit_miss_queue_0_paddr; // @[MissUnit.scala 130:{49,49}]
  wire [38:0] _GEN_393 = {{7'd0}, exe_stage_lsu_cache_0_missUnit__GEN_13}; // @[MissUnit.scala 130:49]
  wire [38:0] exe_stage_lsu_cache_0_missUnit__io_cache_acquire_bits_T_1 = _GEN_393 & 39'hffffffff0; // @[MissUnit.scala 130:49]
  wire  exe_stage_lsu_cache_0_missUnit__T_20 = ~exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_11; // @[MissUnit.scala 142:11]
  wire  exe_stage_lsu_cache_0_missUnit__T_21 = exe_stage_lsu_cache_0_missUnit_mshr_state_dnxt == 3'h3; // @[MissUnit.scala 145:25]
  wire  exe_stage_lsu_cache_0_missUnit__T_23 = exe_stage_lsu_cache_0_missUnit__T_21 &
    exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_11; // @[MissUnit.scala 145:33]
  wire  exe_stage_lsu_cache_0_missUnit__T_24 = exe_stage_lsu_cache_0_missUnit_io_rsp_ready &
    exe_stage_lsu_cache_0_missUnit_io_rsp_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_missUnit__T_28 = ~exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_13; // @[MissUnit.scala 150:11]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_18 = ~exe_stage_lsu_cache_0_missUnit_acquire_sel ? 1'h0 :
    exe_stage_lsu_cache_0_missUnit_miss_valid_0; // @[MissUnit.scala 153:{31,31} 59:27]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_19 = exe_stage_lsu_cache_0_missUnit_acquire_sel ? 1'h0 :
    exe_stage_lsu_cache_0_missUnit_miss_valid_1; // @[MissUnit.scala 153:{31,31} 59:27]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_20 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_14 ? 1'h0 :
    exe_stage_lsu_cache_0_missUnit_cache_grantAck_valid; // @[MissUnit.scala 151:41 152:26 87:37]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_21 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_14 ?
    exe_stage_lsu_cache_0_missUnit__GEN_18 : exe_stage_lsu_cache_0_missUnit_miss_valid_0; // @[MissUnit.scala 151:41 59:27]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_22 = exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_14 ?
    exe_stage_lsu_cache_0_missUnit__GEN_19 : exe_stage_lsu_cache_0_missUnit_miss_valid_1; // @[MissUnit.scala 151:41 59:27]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_23 = exe_stage_lsu_cache_0_missUnit__T_24 ? 1'h0 :
    exe_stage_lsu_cache_0_missUnit_rsp_valid; // @[MissUnit.scala 147:28 148:15 90:26]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_24 = exe_stage_lsu_cache_0_missUnit__T_24 |
    exe_stage_lsu_cache_0_missUnit__GEN_20; // @[MissUnit.scala 147:28 149:26]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_25 = exe_stage_lsu_cache_0_missUnit__T_24 ?
    exe_stage_lsu_cache_0_missUnit_miss_valid_0 : exe_stage_lsu_cache_0_missUnit__GEN_21; // @[MissUnit.scala 147:28 59:27]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_26 = exe_stage_lsu_cache_0_missUnit__T_24 ?
    exe_stage_lsu_cache_0_missUnit_miss_valid_1 : exe_stage_lsu_cache_0_missUnit__GEN_22; // @[MissUnit.scala 147:28 59:27]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_27 = exe_stage_lsu_cache_0_missUnit__T_23 |
    exe_stage_lsu_cache_0_missUnit__GEN_23; // @[MissUnit.scala 145:61 146:15]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_29 = exe_stage_lsu_cache_0_missUnit__T_23 ?
    exe_stage_lsu_cache_0_missUnit_miss_valid_0 : exe_stage_lsu_cache_0_missUnit__GEN_25; // @[MissUnit.scala 145:61 59:27]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_30 = exe_stage_lsu_cache_0_missUnit__T_23 ?
    exe_stage_lsu_cache_0_missUnit_miss_valid_1 : exe_stage_lsu_cache_0_missUnit__GEN_26; // @[MissUnit.scala 145:61 59:27]
  wire  exe_stage_lsu_cache_0_missUnit__io_release_ban_T = exe_stage_lsu_cache_0_missUnit_mshr_state_dnxt == 3'h2; // @[MissUnit.scala 161:37]
  wire  exe_stage_lsu_cache_0_missUnit_is_missQueue_full = exe_stage_lsu_cache_0_missUnit_miss_valid_0 &
    exe_stage_lsu_cache_0_missUnit_miss_valid_1; // @[MissUnit.scala 167:44]
  wire  exe_stage_lsu_cache_0_missUnit__load_sel_T = ~exe_stage_lsu_cache_0_missUnit_miss_valid_0; // @[MissUnit.scala 170:56]
  wire  exe_stage_lsu_cache_0_missUnit_load_sel = exe_stage_lsu_cache_0_missUnit__load_sel_T ? 1'h0 : 1'h1; // @[MissUnit.scala 170:39]
  wire  exe_stage_lsu_cache_0_missUnit__is_merge_T = exe_stage_lsu_cache_0_missUnit_miss_queue_0_paddr ==
    exe_stage_lsu_cache_0_missUnit_io_req_bits_paddr; // @[MissUnit.scala 178:28]
  wire  exe_stage_lsu_cache_0_missUnit__is_merge_T_2 = exe_stage_lsu_cache_0_missUnit__is_merge_T &
    exe_stage_lsu_cache_0_missUnit_miss_valid_0; // @[MissUnit.scala 178:51]
  wire  exe_stage_lsu_cache_0_missUnit__is_merge_T_3 = exe_stage_lsu_cache_0_missUnit_miss_queue_1_paddr ==
    exe_stage_lsu_cache_0_missUnit_io_req_bits_paddr; // @[MissUnit.scala 178:28]
  wire  exe_stage_lsu_cache_0_missUnit__is_merge_T_5 = exe_stage_lsu_cache_0_missUnit__is_merge_T_3 &
    exe_stage_lsu_cache_0_missUnit_miss_valid_1; // @[MissUnit.scala 178:51]
  wire  exe_stage_lsu_cache_0_missUnit_is_merge = exe_stage_lsu_cache_0_missUnit__is_merge_T_2 |
    exe_stage_lsu_cache_0_missUnit__is_merge_T_5; // @[MissUnit.scala 180:13]
  wire  exe_stage_lsu_cache_0_missUnit__T_34 = ~exe_stage_lsu_cache_0_missUnit_is_merge; // @[MissUnit.scala 184:11]
  wire  exe_stage_lsu_cache_0_missUnit__T_35 = ~exe_stage_lsu_cache_0_missUnit_is_missQueue_full; // @[MissUnit.scala 184:23]
  wire  exe_stage_lsu_cache_0_missUnit__T_36 = exe_stage_lsu_cache_0_missUnit__T_34 &
    exe_stage_lsu_cache_0_missUnit__T_35; // @[MissUnit.scala 184:21]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_33 = ~exe_stage_lsu_cache_0_missUnit_load_sel |
    exe_stage_lsu_cache_0_missUnit__GEN_29; // @[MissUnit.scala 186:{28,28}]
  wire  exe_stage_lsu_cache_0_missUnit__GEN_34 = exe_stage_lsu_cache_0_missUnit_load_sel |
    exe_stage_lsu_cache_0_missUnit__GEN_30; // @[MissUnit.scala 186:{28,28}]
  wire  exe_stage_lsu_cache_0_missUnit__T_38 = ~exe_stage_lsu_cache_0_missUnit_miss_valid_1; // @[MissUnit.scala 194:40]
  wire  exe_stage_lsu_cache_0_missUnit__T_40 = exe_stage_lsu_cache_0_missUnit__load_sel_T |
    exe_stage_lsu_cache_0_missUnit__T_38; // @[MissUnit.scala 194:24]
  wire  exe_stage_lsu_cache_0_missUnit__T_48 = exe_stage_lsu_cache_0_missUnit__T_40 |
    exe_stage_lsu_cache_0_missUnit_is_merge; // @[MissUnit.scala 194:54]
  wire  exe_stage_lsu_cache_0_missUnit__T_51 = ~exe_stage_lsu_cache_0_missUnit__T_48; // @[MissUnit.scala 193:11]
  wire  _GEN_401 = ~exe_stage_lsu_cache_0_missUnit__T_23; // @[MissUnit.scala 150:11]
  wire  exe_stage_lsu_cache_0_probeUnit_clock;
  wire  exe_stage_lsu_cache_0_probeUnit_reset;
  wire  exe_stage_lsu_cache_0_probeUnit_io_cache_probe_ready;
  wire  exe_stage_lsu_cache_0_probeUnit_io_cache_probe_valid;
  wire [31:0] exe_stage_lsu_cache_0_probeUnit_io_cache_probe_bits_address;
  wire  exe_stage_lsu_cache_0_probeUnit_io_req_ready;
  wire  exe_stage_lsu_cache_0_probeUnit_io_req_valid;
  wire [31:0] exe_stage_lsu_cache_0_probeUnit_io_req_bits_paddr;
  wire  exe_stage_lsu_cache_0_probeUnit_io_probeBan;
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_clock;
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_reset;
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_ready;
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_valid;
  wire [31:0] exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_bits;
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_ready;
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_valid;
  wire [31:0] exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_bits;
  reg [31:0] exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_clock;
  reg  exe_stage_lsu_cache_0_probeUnit_probe_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo__empty_T = ~exe_stage_lsu_cache_0_probeUnit_probe_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo__do_enq_T = exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_ready
     & exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo__do_deq_T = exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_ready
     & exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_probeUnit_probe_fifo__T = exe_stage_lsu_cache_0_probeUnit_probe_fifo__do_enq_T !=
    exe_stage_lsu_cache_0_probeUnit_probe_fifo__do_deq_T; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_cache_0_probeUnit__io_req_valid_T = ~exe_stage_lsu_cache_0_probeUnit_io_probeBan; // @[ProbeUnit.scala 54:45]
  wire  exe_stage_lsu_cache_0_writeBackUnit_clock;
  wire  exe_stage_lsu_cache_0_writeBackUnit_reset;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_valid;
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_data;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_releaseData;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_release;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_probe;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_probeData;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_ready;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_valid;
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_opcode;
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_param;
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_size;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_source;
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_address;
  wire [63:0] exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_data;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_corrupt;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_ready;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_valid;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_bits_source;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_release_ban;
  wire  exe_stage_lsu_cache_0_writeBackUnit_io_miss_ban;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_reset;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_ready;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_valid;
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_data;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_releaseData;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_release;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_probe;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_probeData;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_ready;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_valid;
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_data;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_releaseData;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_release;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probe;
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData;
  reg [31:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_clock;
  reg [127:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [127:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [127:0] exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_clock;
  reg  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_clock;
  reg  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_clock;
  reg  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_clock;
  reg  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_clock;
  reg  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value; // @[Counter.scala 61:40]
  reg  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value; // @[Counter.scala 61:40]
  reg  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ptr_match =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value ==
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__empty_T = ~exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ptr_match &
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__empty_T; // @[Decoupled.scala 280:25]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_full = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ptr_match &
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_maybe_full; // @[Decoupled.scala 281:24]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_ready
     & exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_deq_T = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_ready
     & exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__value_T_1 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value + 1'h1; // @[Counter.scala 77:24]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_17 = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_ready
     ? 1'h0 : exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_25 = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ?
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_17 : exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__value_T_3 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value + 1'h1; // @[Counter.scala 77:24]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_24 = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? 1'h0
     : exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__T = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_25 !=
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_24; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__io_deq_valid_T = ~exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty
    ; // @[Decoupled.scala 304:19]
  reg [1:0] exe_stage_lsu_cache_0_writeBackUnit_wb_state_qout; // @[wrtieBackUnit.scala 70:30]
  wire  exe_stage_lsu_cache_0_writeBackUnit__is_release_done_T =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_ready &
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_valid; // @[Decoupled.scala 52:35]
  wire [10:0] exe_stage_lsu_cache_0_writeBackUnit__is_release_done_beats1_decode_T_1 = 11'hf <<
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_size; // @[package.scala 234:77]
  wire [3:0] exe_stage_lsu_cache_0_writeBackUnit__is_release_done_beats1_decode_T_2 =
    exe_stage_lsu_cache_0_writeBackUnit__is_release_done_beats1_decode_T_1[3:0]; // @[package.scala 234:82]
  wire [3:0] exe_stage_lsu_cache_0_writeBackUnit__is_release_done_beats1_decode_T_3 = ~
    exe_stage_lsu_cache_0_writeBackUnit__is_release_done_beats1_decode_T_2; // @[package.scala 234:46]
  wire  exe_stage_lsu_cache_0_writeBackUnit_is_release_done_beats1_decode =
    exe_stage_lsu_cache_0_writeBackUnit__is_release_done_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  exe_stage_lsu_cache_0_writeBackUnit_is_release_done_beats1_opdata =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_opcode[0]; // @[Edges.scala 101:36]
  wire  exe_stage_lsu_cache_0_writeBackUnit_is_release_done_beats1 =
    exe_stage_lsu_cache_0_writeBackUnit_is_release_done_beats1_opdata &
    exe_stage_lsu_cache_0_writeBackUnit_is_release_done_beats1_decode; // @[Edges.scala 220:14]
  reg  exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter; // @[Edges.scala 228:27]
  wire  exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter1 =
    exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter - 1'h1; // @[Edges.scala 229:28]
  wire  exe_stage_lsu_cache_0_writeBackUnit_is_release_done_first = ~
    exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter; // @[Edges.scala 230:25]
  wire  exe_stage_lsu_cache_0_writeBackUnit__is_release_done_last_T_1 = ~
    exe_stage_lsu_cache_0_writeBackUnit_is_release_done_beats1; // @[Edges.scala 231:47]
  wire  exe_stage_lsu_cache_0_writeBackUnit_is_release_done_last =
    exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter |
    exe_stage_lsu_cache_0_writeBackUnit__is_release_done_last_T_1; // @[Edges.scala 231:37]
  wire  exe_stage_lsu_cache_0_writeBackUnit_is_release_done = exe_stage_lsu_cache_0_writeBackUnit_is_release_done_last
     & exe_stage_lsu_cache_0_writeBackUnit__is_release_done_T; // @[Edges.scala 232:22]
  reg  exe_stage_lsu_cache_0_writeBackUnit_cache_release_valid; // @[wrtieBackUnit.scala 76:36]
  reg  exe_stage_lsu_cache_0_writeBackUnit_cache_grant_ready; // @[wrtieBackUnit.scala 79:36]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T = exe_stage_lsu_cache_0_writeBackUnit_wb_state_qout == 2'h0
    ; // @[wrtieBackUnit.scala 87:22]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_1 = ~exe_stage_lsu_cache_0_writeBackUnit_io_release_ban; // @[wrtieBackUnit.scala 89:12]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_2 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_release |
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_releaseData; // @[wrtieBackUnit.scala 89:63]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_3 = exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_1
     & exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_2; // @[wrtieBackUnit.scala 89:28]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_4 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probe |
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData; // @[wrtieBackUnit.scala 90:42]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_5 = exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_3
     | exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_4; // @[wrtieBackUnit.scala 89:103]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_6 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_valid & exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_5; // @[wrtieBackUnit.scala 88:30]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_8 = exe_stage_lsu_cache_0_writeBackUnit_wb_state_qout == 2'h1
    ; // @[wrtieBackUnit.scala 93:22]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_9 = ~exe_stage_lsu_cache_0_writeBackUnit_is_release_done; // @[wrtieBackUnit.scala 94:13]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_10 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData |
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probe; // @[wrtieBackUnit.scala 95:49]
  wire [1:0] exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_11 =
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_10 ? 2'h0 : 2'h2; // @[wrtieBackUnit.scala 95:14]
  wire [1:0] exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_12 =
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_9 ? 2'h1 :
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_11; // @[wrtieBackUnit.scala 94:12]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_13 = exe_stage_lsu_cache_0_writeBackUnit_wb_state_qout == 2'h2
    ; // @[wrtieBackUnit.scala 96:22]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_14 =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_ready & exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_valid; // @[Decoupled.scala 52:35]
  wire [1:0] exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_15 =
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_14 ? 2'h0 : 2'h2; // @[wrtieBackUnit.scala 96:37]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_16 = exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T
     & exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_6; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_17 =
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_8 ? exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_12 : 2'h0
    ; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_18 =
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_13 ? exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_15 : 2'h0
    ; // @[Mux.scala 27:73]
  wire [1:0] _GEN_416 = {{1'd0}, exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_16}; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_19 = _GEN_416 |
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_17; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_20 =
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_19 | exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_18; // @[Mux.scala 27:73]
  reg  exe_stage_lsu_cache_0_writeBackUnit_beatCnt; // @[wrtieBackUnit.scala 100:24]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_1 = exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_20 == 2'h1; // @[wrtieBackUnit.scala 101:47]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_2 = exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T &
    exe_stage_lsu_cache_0_writeBackUnit__T_1; // @[wrtieBackUnit.scala 101:31]
  wire  exe_stage_lsu_cache_0_writeBackUnit__beatCnt_T_1 = exe_stage_lsu_cache_0_writeBackUnit_beatCnt + 1'h1; // @[wrtieBackUnit.scala 102:59]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_6 = ~exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_valid; // @[wrtieBackUnit.scala 106:16]
  wire  exe_stage_lsu_cache_0_writeBackUnit__GEN_3 = exe_stage_lsu_cache_0_writeBackUnit__T_6 |
    exe_stage_lsu_cache_0_writeBackUnit_cache_release_valid; // @[wrtieBackUnit.scala 106:{42,64} 76:36]
  wire [38:0] _GEN_417 = {{7'd0}, exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_paddr}; // @[wrtieBackUnit.scala 123:45]
  wire [38:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_info_probe_T_1 = _GEN_417 & 39'hffffffff0; // @[wrtieBackUnit.scala 123:45]
  wire [6:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_info_probeData_T_2 = {
    exe_stage_lsu_cache_0_writeBackUnit_beatCnt, 6'h0}; // @[wrtieBackUnit.scala 133:51]
  wire [127:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_info_probeData_T_3 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_data >>
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_info_probeData_T_2; // @[wrtieBackUnit.scala 133:39]
  wire [63:0] exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_info_probeData_data =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_info_probeData_T_3[63:0]; // @[Edges.scala 422:17 428:15]
  wire [63:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_8 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData ?
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_info_probeData_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_10 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_releaseData ?
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_info_probeData_data : 64'h0; // @[Mux.scala 27:73]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_info_probe_address =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_info_probe_T_1[31:0]; // @[Edges.scala 407:17 412:15]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_14 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probe ?
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_info_probe_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_15 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData ?
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_info_probe_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_16 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_release ?
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_info_probe_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_17 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_releaseData ?
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_info_probe_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_18 =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_14 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_15; // @[Mux.scala 27:73]
  wire [31:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_19 =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_18 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_16; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_28 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probe ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_29 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_30 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_release ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_31 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_releaseData ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_32 =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_28 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_29; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_33 =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_32 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_30; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_35 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probe ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_36 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_37 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_release ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_38 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_releaseData ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_39 =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_35 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_36; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_40 =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_39 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_37; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_43 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData ? 3'h5 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_44 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_release ? 3'h6 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_45 =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_releaseData ? 3'h7 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_46 =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_28 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_43; // @[Mux.scala 27:73]
  wire [2:0] exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_47 =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_46 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_44; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_7 = ~exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_ready; // @[wrtieBackUnit.scala 160:32]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_8 = exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_valid &
    exe_stage_lsu_cache_0_writeBackUnit__T_7; // @[wrtieBackUnit.scala 160:30]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_11 = ~exe_stage_lsu_cache_0_writeBackUnit_reset; // @[wrtieBackUnit.scala 162:11]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_12 = ~exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_13; // @[wrtieBackUnit.scala 162:11]
  wire  exe_stage_lsu_cache_0_writeBackUnit__GEN_6 = exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_ready ? 1'h0 :
    exe_stage_lsu_cache_0_writeBackUnit_cache_grant_ready; // @[wrtieBackUnit.scala 163:39 164:23 79:36]
  wire  exe_stage_lsu_cache_0_writeBackUnit__GEN_7 = exe_stage_lsu_cache_0_writeBackUnit__T_8 |
    exe_stage_lsu_cache_0_writeBackUnit__GEN_6; // @[wrtieBackUnit.scala 160:56 161:23]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_19 = exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_14 &
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_bits_source; // @[wrtieBackUnit.scala 167:33]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_20 = ~exe_stage_lsu_cache_0_writeBackUnit__T_19; // @[wrtieBackUnit.scala 167:11]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_23 = ~exe_stage_lsu_cache_0_writeBackUnit__T_20; // @[wrtieBackUnit.scala 167:9]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_fifo_io_deq_ready_T = exe_stage_lsu_cache_0_writeBackUnit_wb_state_qout
     != 2'h0; // @[wrtieBackUnit.scala 169:19]
  wire  exe_stage_lsu_cache_0_writeBackUnit__wb_fifo_io_deq_ready_T_1 =
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_20 == 2'h0; // @[wrtieBackUnit.scala 169:43]
  wire  exe_stage_lsu_cache_0_writeBackUnit__io_miss_ban_T_2 = exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_8 |
    exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_13; // @[wrtieBackUnit.scala 171:40]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_24 = ~exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_ready; // @[wrtieBackUnit.scala 175:9]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_25 = ~exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_valid; // @[wrtieBackUnit.scala 176:12]
  wire  exe_stage_lsu_cache_0_writeBackUnit__T_28 = ~exe_stage_lsu_cache_0_writeBackUnit__T_25; // @[wrtieBackUnit.scala 176:11]
  wire  exe_stage_lsu_cache_0_lsEntry_clock;
  wire  exe_stage_lsu_cache_0_lsEntry_reset;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_ready;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_valid;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_lsEntry_io_enq_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_lsEntry_io_enq_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_lsEntry_io_enq_bits_wstrb;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_lsEntry_io_enq_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_ready;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_valid;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_lsEntry_io_deq_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_lsEntry_io_deq_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_lsEntry_io_deq_bits_wstrb;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_lsEntry_io_deq_bits_rd_rd0;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_clock;
  reg [31:0] exe_stage_lsu_cache_0_lsEntry_ram_paddr [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_paddr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_paddr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] exe_stage_lsu_cache_0_lsEntry_ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_paddr_clock;
  reg [127:0] exe_stage_lsu_cache_0_lsEntry_ram_wdata [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wdata_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wdata_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [127:0] exe_stage_lsu_cache_0_lsEntry_ram_wdata_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [127:0] exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wdata_clock;
  reg [15:0] exe_stage_lsu_cache_0_lsEntry_ram_wstrb [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wstrb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wstrb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [15:0] exe_stage_lsu_cache_0_lsEntry_ram_wstrb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [15:0] exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_wstrb_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_clock;
  reg [5:0] exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0 [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_clock;
  reg  exe_stage_lsu_cache_0_lsEntry_enq_ptr_value; // @[Counter.scala 61:40]
  reg  exe_stage_lsu_cache_0_lsEntry_deq_ptr_value; // @[Counter.scala 61:40]
  reg  exe_stage_lsu_cache_0_lsEntry_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_cache_0_lsEntry_ptr_match = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value ==
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  exe_stage_lsu_cache_0_lsEntry__empty_T = ~exe_stage_lsu_cache_0_lsEntry_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_cache_0_lsEntry_empty = exe_stage_lsu_cache_0_lsEntry_ptr_match &
    exe_stage_lsu_cache_0_lsEntry__empty_T; // @[Decoupled.scala 280:25]
  wire  exe_stage_lsu_cache_0_lsEntry_full = exe_stage_lsu_cache_0_lsEntry_ptr_match &
    exe_stage_lsu_cache_0_lsEntry_maybe_full; // @[Decoupled.scala 281:24]
  wire  exe_stage_lsu_cache_0_lsEntry__do_enq_T = exe_stage_lsu_cache_0_lsEntry_io_enq_ready &
    exe_stage_lsu_cache_0_lsEntry_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_lsEntry__do_deq_T = exe_stage_lsu_cache_0_lsEntry_io_deq_ready &
    exe_stage_lsu_cache_0_lsEntry_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_lsEntry__value_T_1 = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value + 1'h1; // @[Counter.scala 77:24]
  wire  exe_stage_lsu_cache_0_lsEntry__GEN_59 = exe_stage_lsu_cache_0_lsEntry_io_deq_ready ? 1'h0 :
    exe_stage_lsu_cache_0_lsEntry__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  exe_stage_lsu_cache_0_lsEntry__GEN_109 = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T; // @[Decoupled.scala 317:17]
  wire  exe_stage_lsu_cache_0_lsEntry__value_T_3 = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value + 1'h1; // @[Counter.scala 77:24]
  wire  exe_stage_lsu_cache_0_lsEntry__GEN_108 = exe_stage_lsu_cache_0_lsEntry_empty ? 1'h0 :
    exe_stage_lsu_cache_0_lsEntry__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  exe_stage_lsu_cache_0_lsEntry__T = exe_stage_lsu_cache_0_lsEntry__GEN_109 !=
    exe_stage_lsu_cache_0_lsEntry__GEN_108; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_cache_0_lsEntry__io_deq_valid_T = ~exe_stage_lsu_cache_0_lsEntry_empty; // @[Decoupled.scala 304:19]
  wire  exe_stage_lsu_cache_0_rtn_fifo_clock;
  wire  exe_stage_lsu_cache_0_rtn_fifo_reset;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_enq_ready;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_enq_valid;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_chkIdx;
  wire [5:0] exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_wb_res;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_load_amo;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_flw;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_fld;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_deq_ready;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_deq_valid;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_chkIdx;
  wire [5:0] exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_wb_res;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_load_amo;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_flw;
  wire  exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_fld;
  reg  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_clock;
  reg [5:0] exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0 [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_clock;
  reg [63:0] exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_clock;
  reg  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_clock;
  reg  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_clock;
  reg  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld [0:1]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_clock;
  reg  exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value; // @[Counter.scala 61:40]
  reg  exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value; // @[Counter.scala 61:40]
  reg  exe_stage_lsu_cache_0_rtn_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_cache_0_rtn_fifo_ptr_match = exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value ==
    exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  exe_stage_lsu_cache_0_rtn_fifo__empty_T = ~exe_stage_lsu_cache_0_rtn_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_cache_0_rtn_fifo_empty = exe_stage_lsu_cache_0_rtn_fifo_ptr_match &
    exe_stage_lsu_cache_0_rtn_fifo__empty_T; // @[Decoupled.scala 280:25]
  wire  exe_stage_lsu_cache_0_rtn_fifo_full = exe_stage_lsu_cache_0_rtn_fifo_ptr_match &
    exe_stage_lsu_cache_0_rtn_fifo_maybe_full; // @[Decoupled.scala 281:24]
  wire  exe_stage_lsu_cache_0_rtn_fifo__do_enq_T = exe_stage_lsu_cache_0_rtn_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_rtn_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_rtn_fifo__do_deq_T = exe_stage_lsu_cache_0_rtn_fifo_io_deq_ready &
    exe_stage_lsu_cache_0_rtn_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_rtn_fifo__value_T_1 = exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value + 1'h1; // @[Counter.scala 77:24]
  wire  exe_stage_lsu_cache_0_rtn_fifo__GEN_17 = exe_stage_lsu_cache_0_rtn_fifo_io_deq_ready ? 1'h0 :
    exe_stage_lsu_cache_0_rtn_fifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  exe_stage_lsu_cache_0_rtn_fifo__GEN_25 = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo__GEN_17 : exe_stage_lsu_cache_0_rtn_fifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  exe_stage_lsu_cache_0_rtn_fifo__value_T_3 = exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value + 1'h1; // @[Counter.scala 77:24]
  wire  exe_stage_lsu_cache_0_rtn_fifo__GEN_24 = exe_stage_lsu_cache_0_rtn_fifo_empty ? 1'h0 :
    exe_stage_lsu_cache_0_rtn_fifo__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  exe_stage_lsu_cache_0_rtn_fifo__T = exe_stage_lsu_cache_0_rtn_fifo__GEN_25 !=
    exe_stage_lsu_cache_0_rtn_fifo__GEN_24; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_cache_0_rtn_fifo__io_deq_valid_T = ~exe_stage_lsu_cache_0_rtn_fifo_empty; // @[Decoupled.scala 304:19]
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_ready;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_valid;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_op_arb_io_in_0_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_op_arb_io_in_0_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_op_arb_io_in_0_bits_wstrb;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_op_arb_io_in_0_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_ready;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_valid;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_op_arb_io_in_1_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_op_arb_io_in_1_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_op_arb_io_in_1_bits_wstrb;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fsd;
  wire [5:0] exe_stage_lsu_cache_0_op_arb_io_in_1_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_ready;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_valid;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_op_arb_io_out_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_op_arb_io_out_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_op_arb_io_out_bits_wstrb;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_op_arb_io_out_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_op_arb_grant_1 = ~exe_stage_lsu_cache_0_op_arb_io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  exe_stage_lsu_cache_0_op_arb__io_out_valid_T = ~exe_stage_lsu_cache_0_op_arb_grant_1; // @[Arbiter.scala 147:19]
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_0_ready;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_0_valid;
  wire [31:0] exe_stage_lsu_cache_0_rd_arb_io_in_0_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_rd_arb_io_in_0_bits_wdata;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_1_ready;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_1_valid;
  wire [31:0] exe_stage_lsu_cache_0_rd_arb_io_in_1_bits_paddr;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_ready;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_valid;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_wstrb;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_ready;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_valid;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_rd_arb_io_out_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_rd_arb_io_out_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_rd_arb_io_out_bits_wstrb;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_rd_arb_io_out_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_1 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_chkIdx; // @[Arbiter.scala 136:15 138:26 140:19]
  wire [31:0] exe_stage_lsu_cache_0_rd_arb__GEN_2 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ?
    exe_stage_lsu_cache_0_rd_arb_io_in_1_bits_paddr : exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_paddr; // @[Arbiter.scala 136:15 138:26 140:19]
  wire [127:0] exe_stage_lsu_cache_0_rd_arb__GEN_3 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 128'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_wdata; // @[Arbiter.scala 136:15 138:26 140:19]
  wire [15:0] exe_stage_lsu_cache_0_rd_arb__GEN_4 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 16'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_wstrb; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_5 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lb; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_6 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lh; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_7 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_8 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_ld; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_9 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lbu; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_10 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lhu; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_11 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lwu; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_12 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sb; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_13 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sh; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_14 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_15 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sd; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_19 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lr_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_20 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sc_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_21 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoswap_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_22 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoadd_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_23 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoxor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_24 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoand_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_25 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_26 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomin_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_27 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomax_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_28 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amominu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_29 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomaxu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_30 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lr_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_31 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sc_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_32 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoswap_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_33 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoadd_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_34 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoxor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_35 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoand_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_36 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_37 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomin_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_38 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomax_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_39 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amominu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_40 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomaxu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_41 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_flw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_42 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fsw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_43 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fld; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_44 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fsd; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_45 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid |
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_probe; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_46 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_grant; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__GEN_47 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_preft; // @[Arbiter.scala 136:15 138:26 140:19]
  wire [5:0] exe_stage_lsu_cache_0_rd_arb__GEN_48 = exe_stage_lsu_cache_0_rd_arb_io_in_1_valid ? 6'h0 :
    exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_rd_rd0; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_cache_0_rd_arb__grant_T = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid |
    exe_stage_lsu_cache_0_rd_arb_io_in_1_valid; // @[Arbiter.scala 45:68]
  wire  exe_stage_lsu_cache_0_rd_arb_grant_1 = ~exe_stage_lsu_cache_0_rd_arb_io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  exe_stage_lsu_cache_0_rd_arb_grant_2 = ~exe_stage_lsu_cache_0_rd_arb__grant_T; // @[Arbiter.scala 45:78]
  wire  exe_stage_lsu_cache_0_rd_arb__io_out_valid_T = ~exe_stage_lsu_cache_0_rd_arb_grant_2; // @[Arbiter.scala 147:19]
  wire  exe_stage_lsu_cache_0_reload_fifo_clock;
  wire  exe_stage_lsu_cache_0_reload_fifo_reset;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_ready;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_wstrb;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_ready;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_valid;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_wstrb;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_rd_rd0;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_clock;
  reg [31:0] exe_stage_lsu_cache_0_reload_fifo_ram_paddr [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_paddr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_paddr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] exe_stage_lsu_cache_0_reload_fifo_ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_paddr_clock;
  reg [127:0] exe_stage_lsu_cache_0_reload_fifo_ram_wdata [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wdata_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wdata_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [127:0] exe_stage_lsu_cache_0_reload_fifo_ram_wdata_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [127:0] exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wdata_clock;
  reg [15:0] exe_stage_lsu_cache_0_reload_fifo_ram_wstrb [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [15:0] exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [15:0] exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_clock;
  reg [5:0] exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_clock;
  reg  exe_stage_lsu_cache_0_reload_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_cache_0_reload_fifo__empty_T = ~exe_stage_lsu_cache_0_reload_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_cache_0_reload_fifo__do_enq_T = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_reload_fifo__do_deq_T = exe_stage_lsu_cache_0_reload_fifo_io_deq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_reload_fifo__T = exe_stage_lsu_cache_0_reload_fifo__do_enq_T !=
    exe_stage_lsu_cache_0_reload_fifo__do_deq_T; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_cache_0_stage_clock;
  wire  exe_stage_lsu_cache_0_stage_reset;
  wire  exe_stage_lsu_cache_0_stage_io_enq_ready;
  wire  exe_stage_lsu_cache_0_stage_io_enq_valid;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_stage_io_enq_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_stage_io_enq_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_stage_io_enq_bits_wstrb;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_stage_io_enq_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_stage_io_enq_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_stage_io_reload_valid;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_chkIdx;
  wire [31:0] exe_stage_lsu_cache_0_stage_io_reload_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_stage_io_reload_bits_wdata;
  wire [15:0] exe_stage_lsu_cache_0_stage_io_reload_bits_wstrb;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lb;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lh;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lw;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_ld;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lbu;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lhu;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lwu;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sb;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sh;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sw;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sd;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lr_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sc_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoswap_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoadd_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoxor_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoand_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoor_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomin_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomax_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amominu_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomaxu_w;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lr_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sc_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoswap_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoadd_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoxor_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoand_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoor_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomin_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomax_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amominu_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomaxu_d;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_flw;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fsw;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fld;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fsd;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_probe;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_grant;
  wire  exe_stage_lsu_cache_0_stage_io_reload_bits_fun_preft;
  wire [5:0] exe_stage_lsu_cache_0_stage_io_reload_bits_rd_rd0;
  wire  exe_stage_lsu_cache_0_stage_io_deq_valid;
  wire  exe_stage_lsu_cache_0_stage_io_deq_bits_chkIdx;
  wire [5:0] exe_stage_lsu_cache_0_stage_io_deq_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_cache_0_stage_io_deq_bits_wb_res;
  wire  exe_stage_lsu_cache_0_stage_io_deq_bits_is_load_amo;
  wire  exe_stage_lsu_cache_0_stage_io_deq_bits_is_flw;
  wire  exe_stage_lsu_cache_0_stage_io_deq_bits_is_fld;
  wire  exe_stage_lsu_cache_0_stage_io_missUnit_req_valid;
  wire [31:0] exe_stage_lsu_cache_0_stage_io_missUnit_req_bits_paddr;
  wire  exe_stage_lsu_cache_0_stage_io_wb_req_valid;
  wire [31:0] exe_stage_lsu_cache_0_stage_io_wb_req_bits_paddr;
  wire [127:0] exe_stage_lsu_cache_0_stage_io_wb_req_bits_data;
  wire  exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_releaseData;
  wire  exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_release;
  wire  exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_probe;
  wire  exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_probeData;
  wire  exe_stage_lsu_cache_0_stage_io_isCacheEmpty;
  wire  exe_stage_lsu_cache_0_stage_io_flush;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_0;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_1;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_2;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_3;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_4;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_5;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_6;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_7;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_8;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_9;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_10;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_11;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_12;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_13;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_14;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_15;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_0;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_1;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_2;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_3;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_4;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_5;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_6;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_7;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_8;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_9;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_10;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_11;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_12;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_13;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_14;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_15;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_0;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_1;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_2;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_3;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_4;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_5;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_6;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_7;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_8;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_9;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_10;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_11;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_12;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_13;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_14;
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_15;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_addr_pipe_0;
  reg [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15 [0:1]; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_addr; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_data; // @[CacheRAM.scala 46:27]
  wire [7:0] exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_data; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_addr; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_mask; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_en; // @[CacheRAM.scala 46:27]
  wire  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_clock;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_addr_pipe_0;
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_clock;
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_io_addrr;
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_io_addrw;
  wire [26:0] exe_stage_lsu_cache_0_stage_tagRAM_0_io_dataw;
  wire [26:0] exe_stage_lsu_cache_0_stage_tagRAM_0_io_datar;
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_io_enw;
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_io_enr;
  reg [26:0] exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem [0:1]; // @[CacheRAM.scala 152:27]
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_en; // @[CacheRAM.scala 152:27]
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_addr; // @[CacheRAM.scala 152:27]
  wire [26:0] exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_data; // @[CacheRAM.scala 152:27]
  wire [26:0] exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_data; // @[CacheRAM.scala 152:27]
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_addr; // @[CacheRAM.scala 152:27]
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_mask; // @[CacheRAM.scala 152:27]
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_en; // @[CacheRAM.scala 152:27]
  wire  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_clock;
  reg  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_en_pipe_0;
  reg  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_addr_pipe_0;
  wire  exe_stage_lsu_cache_0_stage__pipeStage1Valid_T = exe_stage_lsu_cache_0_stage_io_enq_ready &
    exe_stage_lsu_cache_0_stage_io_enq_valid; // @[Decoupled.scala 52:35]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Valid; // @[DcacheStage.scala 71:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_chkIdx; // @[DcacheStage.scala 72:32]
  reg [31:0] exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr; // @[DcacheStage.scala 72:32]
  reg [127:0] exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata; // @[DcacheStage.scala 72:32]
  reg [15:0] exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lb; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lh; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lw; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_ld; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lbu; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lhu; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lwu; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sb; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sh; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sw; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sd; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_w; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_d; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_flw; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsw; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fld; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsd; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_probe; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_preft; // @[DcacheStage.scala 72:32]
  reg [5:0] exe_stage_lsu_cache_0_stage_pipeStage1Bits_rd_rd0; // @[DcacheStage.scala 72:32]
  reg  exe_stage_lsu_cache_0_stage_isTagBypass; // @[Reg.scala 19:16]
  reg [26:0] exe_stage_lsu_cache_0_stage_tagBypassData; // @[Reg.scala 19:16]
  wire [26:0] exe_stage_lsu_cache_0_stage__tagInfoR_0_T = exe_stage_lsu_cache_0_stage_isTagBypass ?
    exe_stage_lsu_cache_0_stage_tagBypassData : exe_stage_lsu_cache_0_stage_tagRAM_0_io_datar; // @[DcacheStage.scala 127:31]
  wire [26:0] exe_stage_lsu_cache_0_stage__tagInfoW_T = exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[31:5]; // @[Dcache.scala 73:21]
  wire  exe_stage_lsu_cache_0_stage__res_T = exe_stage_lsu_cache_0_stage__tagInfoR_0_T ==
    exe_stage_lsu_cache_0_stage__tagInfoW_T; // @[DcacheStage.scala 241:59]
  wire  exe_stage_lsu_cache_0_stage__addrSelW_T = exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[4]; // @[Dcache.scala 74:21]
  reg  exe_stage_lsu_cache_0_stage_isCBValid_1_0; // @[DcacheStage.scala 84:26]
  reg  exe_stage_lsu_cache_0_stage_isCBValid_0_0; // @[DcacheStage.scala 84:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_72 = exe_stage_lsu_cache_0_stage__addrSelW_T ?
    exe_stage_lsu_cache_0_stage_isCBValid_1_0 : exe_stage_lsu_cache_0_stage_isCBValid_0_0; // @[DcacheStage.scala 241:{73,73}]
  wire  exe_stage_lsu_cache_0_stage_res_0 = exe_stage_lsu_cache_0_stage__res_T & exe_stage_lsu_cache_0_stage__GEN_72; // @[DcacheStage.scala 241:73]
  wire  exe_stage_lsu_cache_0_stage_isHit = |exe_stage_lsu_cache_0_stage_res_0; // @[DcacheStage.scala 77:30]
  reg  exe_stage_lsu_cache_0_stage_isCBDirty_0_0; // @[DcacheStage.scala 86:26]
  reg  exe_stage_lsu_cache_0_stage_isCBDirty_1_0; // @[DcacheStage.scala 86:26]
  wire  exe_stage_lsu_cache_0_stage__addrSelR_T = exe_stage_lsu_cache_0_stage_io_enq_bits_paddr[4]; // @[Dcache.scala 74:21]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_2 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_w |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_w; // @[riscv_isa.scala 148:15]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_3 = exe_stage_lsu_cache_0_stage__datEnW_0_T_2 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_w; // @[riscv_isa.scala 148:26]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_4 = exe_stage_lsu_cache_0_stage__datEnW_0_T_3 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_w; // @[riscv_isa.scala 148:37]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_5 = exe_stage_lsu_cache_0_stage__datEnW_0_T_4 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_w; // @[riscv_isa.scala 148:48]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_6 = exe_stage_lsu_cache_0_stage__datEnW_0_T_5 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_w; // @[riscv_isa.scala 148:58]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_7 = exe_stage_lsu_cache_0_stage__datEnW_0_T_6 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_w; // @[riscv_isa.scala 148:69]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_8 = exe_stage_lsu_cache_0_stage__datEnW_0_T_7 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_w; // @[riscv_isa.scala 148:80]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_9 = exe_stage_lsu_cache_0_stage__datEnW_0_T_8 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_w; // @[riscv_isa.scala 148:92]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_10 = exe_stage_lsu_cache_0_stage__datEnW_0_T_9 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_d; // @[riscv_isa.scala 148:104]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_11 = exe_stage_lsu_cache_0_stage__datEnW_0_T_10 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_d; // @[riscv_isa.scala 148:116]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_12 = exe_stage_lsu_cache_0_stage__datEnW_0_T_11 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_d; // @[riscv_isa.scala 148:127]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_13 = exe_stage_lsu_cache_0_stage__datEnW_0_T_12 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_d; // @[riscv_isa.scala 148:138]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_14 = exe_stage_lsu_cache_0_stage__datEnW_0_T_13 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_d; // @[riscv_isa.scala 148:149]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_15 = exe_stage_lsu_cache_0_stage__datEnW_0_T_14 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_d; // @[riscv_isa.scala 148:159]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_16 = exe_stage_lsu_cache_0_stage__datEnW_0_T_15 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_d; // @[riscv_isa.scala 148:170]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_17 = exe_stage_lsu_cache_0_stage__datEnW_0_T_16 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_d; // @[riscv_isa.scala 148:181]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_18 = exe_stage_lsu_cache_0_stage__datEnW_0_T_17 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_d; // @[riscv_isa.scala 148:193]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_19 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_d |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_w; // @[riscv_isa.scala 140:20]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_20 = exe_stage_lsu_cache_0_stage__datEnW_0_T_18 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_19; // @[riscv_isa.scala 148:205]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_21 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sb |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sh; // @[riscv_isa.scala 144:19]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_22 = exe_stage_lsu_cache_0_stage__datEnW_0_T_21 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sw; // @[riscv_isa.scala 144:24]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_23 = exe_stage_lsu_cache_0_stage__datEnW_0_T_22 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sd; // @[riscv_isa.scala 144:29]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_24 = exe_stage_lsu_cache_0_stage__datEnW_0_T_23 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsw; // @[riscv_isa.scala 144:34]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_25 = exe_stage_lsu_cache_0_stage__datEnW_0_T_24 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsd; // @[riscv_isa.scala 144:40]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_26 = exe_stage_lsu_cache_0_stage__datEnW_0_T_20 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_25; // @[Dcache.scala 54:26]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_28 = exe_stage_lsu_cache_0_stage__datEnW_0_T_26 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_19; // @[Dcache.scala 54:34]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_29 = exe_stage_lsu_cache_0_stage__datEnW_0_T_28 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant; // @[Dcache.scala 54:42]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_30 = exe_stage_lsu_cache_0_stage_pipeStage1Valid &
    exe_stage_lsu_cache_0_stage__datEnW_0_T_29; // @[DcacheStage.scala 100:41]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_50 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lb |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lh; // @[riscv_isa.scala 143:19]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_51 = exe_stage_lsu_cache_0_stage__datEnW_0_T_50 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lw; // @[riscv_isa.scala 143:24]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_52 = exe_stage_lsu_cache_0_stage__datEnW_0_T_51 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_ld; // @[riscv_isa.scala 143:29]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_53 = exe_stage_lsu_cache_0_stage__datEnW_0_T_52 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lbu; // @[riscv_isa.scala 143:34]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_54 = exe_stage_lsu_cache_0_stage__datEnW_0_T_53 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lhu; // @[riscv_isa.scala 143:40]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_55 = exe_stage_lsu_cache_0_stage__datEnW_0_T_54 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lwu; // @[riscv_isa.scala 143:46]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_56 = exe_stage_lsu_cache_0_stage__datEnW_0_T_55 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_flw; // @[riscv_isa.scala 143:52]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_57 = exe_stage_lsu_cache_0_stage__datEnW_0_T_56 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fld; // @[riscv_isa.scala 143:59]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_58 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_d |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_w; // @[riscv_isa.scala 141:20]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_59 = exe_stage_lsu_cache_0_stage__datEnW_0_T_57 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_58; // @[riscv_isa.scala 143:65]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_60 = exe_stage_lsu_cache_0_stage__datEnW_0_T_20 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_59; // @[Dcache.scala 50:27]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_66 = exe_stage_lsu_cache_0_stage__datEnW_0_T_60 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_25; // @[Dcache.scala 50:35]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_68 = exe_stage_lsu_cache_0_stage__datEnW_0_T_66 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_58; // @[Dcache.scala 50:43]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_70 = exe_stage_lsu_cache_0_stage__datEnW_0_T_68 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_19; // @[Dcache.scala 50:51]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_71 = exe_stage_lsu_cache_0_stage__datEnW_0_T_70 &
    exe_stage_lsu_cache_0_stage_isHit; // @[DcacheStage.scala 103:40]
  reg  exe_stage_lsu_cache_0_stage_is_pending_lr; // @[DcacheStage.scala 147:30]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T = ~exe_stage_lsu_cache_0_stage_is_pending_lr; // @[DcacheStage.scala 151:5]
  reg  exe_stage_lsu_cache_0_stage_is_lr_64_32n; // @[DcacheStage.scala 148:29]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_1 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lw |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lwu; // @[riscv_isa.scala 155:20]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_2 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_1 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sw; // @[riscv_isa.scala 155:26]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_3 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_2 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_w; // @[riscv_isa.scala 155:31]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_4 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_3 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_w; // @[riscv_isa.scala 155:43]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_5 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_4 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_w; // @[riscv_isa.scala 155:54]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_6 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_5 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_w; // @[riscv_isa.scala 155:65]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_7 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_6 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_w; // @[riscv_isa.scala 155:76]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_8 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_7 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_w; // @[riscv_isa.scala 155:86]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_9 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_8 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_w; // @[riscv_isa.scala 155:97]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_10 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_9 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_w; // @[riscv_isa.scala 155:108]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_11 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_10 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_w; // @[riscv_isa.scala 155:120]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_12 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_11 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_flw; // @[riscv_isa.scala 155:132]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_13 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_12 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsw; // @[riscv_isa.scala 155:138]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_14 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_13 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_w; // @[riscv_isa.scala 155:144]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_15 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_14 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_w; // @[riscv_isa.scala 155:151]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_16 = exe_stage_lsu_cache_0_stage_is_lr_64_32n &
    exe_stage_lsu_cache_0_stage__is_sc_fail_T_15; // @[DcacheStage.scala 152:20]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_17 = exe_stage_lsu_cache_0_stage__is_sc_fail_T |
    exe_stage_lsu_cache_0_stage__is_sc_fail_T_16; // @[DcacheStage.scala 151:20]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_18 = ~exe_stage_lsu_cache_0_stage_is_lr_64_32n; // @[DcacheStage.scala 153:6]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_19 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_ld |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_d; // @[riscv_isa.scala 156:20]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_20 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_19 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fld; // @[riscv_isa.scala 156:27]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_21 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_20 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sd; // @[riscv_isa.scala 156:33]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_22 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_21 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_d; // @[riscv_isa.scala 156:38]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_23 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_22 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsd; // @[riscv_isa.scala 156:45]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_24 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_23 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_d; // @[riscv_isa.scala 156:51]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_25 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_24 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_d; // @[riscv_isa.scala 156:63]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_26 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_25 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_d; // @[riscv_isa.scala 156:74]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_27 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_26 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_d; // @[riscv_isa.scala 156:85]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_28 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_27 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_d; // @[riscv_isa.scala 156:96]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_29 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_28 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_d; // @[riscv_isa.scala 156:106]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_30 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_29 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_d; // @[riscv_isa.scala 156:117]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_31 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_30 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_d; // @[riscv_isa.scala 156:128]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_32 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_31 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_d; // @[riscv_isa.scala 156:140]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_33 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_18 &
    exe_stage_lsu_cache_0_stage__is_sc_fail_T_32; // @[DcacheStage.scala 153:20]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_34 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_17 |
    exe_stage_lsu_cache_0_stage__is_sc_fail_T_33; // @[DcacheStage.scala 152:50]
  reg [31:0] exe_stage_lsu_cache_0_stage_lr_addr; // @[DcacheStage.scala 149:20]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_35 = exe_stage_lsu_cache_0_stage_lr_addr !=
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr; // @[DcacheStage.scala 154:13]
  wire  exe_stage_lsu_cache_0_stage__is_sc_fail_T_36 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_34 |
    exe_stage_lsu_cache_0_stage__is_sc_fail_T_35; // @[DcacheStage.scala 153:50]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_73 = ~exe_stage_lsu_cache_0_stage__is_sc_fail_T_36; // @[DcacheStage.scala 103:81]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_74 = exe_stage_lsu_cache_0_stage__datEnW_0_T_19 ?
    exe_stage_lsu_cache_0_stage__datEnW_0_T_73 : 1'h1; // @[DcacheStage.scala 103:53]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_75 = exe_stage_lsu_cache_0_stage__datEnW_0_T_71 &
    exe_stage_lsu_cache_0_stage__datEnW_0_T_74; // @[DcacheStage.scala 103:48]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_76 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_75; // @[DcacheStage.scala 102:38]
  wire  exe_stage_lsu_cache_0_stage__datEnW_0_T_77 = exe_stage_lsu_cache_0_stage__datEnW_0_T_30 &
    exe_stage_lsu_cache_0_stage__datEnW_0_T_76; // @[DcacheStage.scala 101:35]
  wire  exe_stage_lsu_cache_0_stage__tagEnW_0_T_2 = exe_stage_lsu_cache_0_stage_pipeStage1Valid &
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant; // @[DcacheStage.scala 106:52]
  wire [15:0] exe_stage_lsu_cache_0_stage__T_41 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant ? 16'hffff : 16'h0
    ; // @[Mux.scala 27:73]
  wire [15:0] exe_stage_lsu_cache_0_stage__T_42 = exe_stage_lsu_cache_0_stage__datEnW_0_T_70 ?
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb : 16'h0; // @[Mux.scala 27:73]
  wire [15:0] exe_stage_lsu_cache_0_stage__T_43 = exe_stage_lsu_cache_0_stage__T_41 | exe_stage_lsu_cache_0_stage__T_42; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__T_44 = exe_stage_lsu_cache_0_stage__T_43[0]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_45 = exe_stage_lsu_cache_0_stage__T_43[1]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_46 = exe_stage_lsu_cache_0_stage__T_43[2]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_47 = exe_stage_lsu_cache_0_stage__T_43[3]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_48 = exe_stage_lsu_cache_0_stage__T_43[4]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_49 = exe_stage_lsu_cache_0_stage__T_43[5]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_50 = exe_stage_lsu_cache_0_stage__T_43[6]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_51 = exe_stage_lsu_cache_0_stage__T_43[7]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_52 = exe_stage_lsu_cache_0_stage__T_43[8]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_53 = exe_stage_lsu_cache_0_stage__T_43[9]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_54 = exe_stage_lsu_cache_0_stage__T_43[10]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_55 = exe_stage_lsu_cache_0_stage__T_43[11]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_56 = exe_stage_lsu_cache_0_stage__T_43[12]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_57 = exe_stage_lsu_cache_0_stage__T_43[13]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_58 = exe_stage_lsu_cache_0_stage__T_43[14]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__T_59 = exe_stage_lsu_cache_0_stage__T_43[15]; // @[DcacheStage.scala 113:8]
  wire  exe_stage_lsu_cache_0_stage__isTagBypass_T = exe_stage_lsu_cache_0_stage__addrSelR_T ==
    exe_stage_lsu_cache_0_stage__addrSelW_T; // @[DcacheStage.scala 117:58]
  wire  exe_stage_lsu_cache_0_stage__isTagBypass_T_1 = exe_stage_lsu_cache_0_stage__tagEnW_0_T_2 &
    exe_stage_lsu_cache_0_stage__isTagBypass_T; // @[DcacheStage.scala 117:46]
  wire  exe_stage_lsu_cache_0_stage__tagBypassData_T_1 = exe_stage_lsu_cache_0_stage__pipeStage1Valid_T &
    exe_stage_lsu_cache_0_stage__tagEnW_0_T_2; // @[DcacheStage.scala 118:58]
  wire  exe_stage_lsu_cache_0_stage__tagBypassData_T_3 = exe_stage_lsu_cache_0_stage__tagBypassData_T_1 &
    exe_stage_lsu_cache_0_stage__isTagBypass_T; // @[DcacheStage.scala 118:70]
  wire  exe_stage_lsu_cache_0_stage__isDatBypass_T_1 = exe_stage_lsu_cache_0_stage__datEnW_0_T_77 &
    exe_stage_lsu_cache_0_stage__isTagBypass_T; // @[DcacheStage.scala 119:46]
  reg  exe_stage_lsu_cache_0_stage_isDatBypass; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__datBypassData_T_1 = exe_stage_lsu_cache_0_stage__pipeStage1Valid_T &
    exe_stage_lsu_cache_0_stage__datEnW_0_T_77; // @[DcacheStage.scala 120:58]
  wire  exe_stage_lsu_cache_0_stage__datBypassData_T_3 = exe_stage_lsu_cache_0_stage__datBypassData_T_1 &
    exe_stage_lsu_cache_0_stage__isTagBypass_T; // @[DcacheStage.scala 120:70]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_0; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_1; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_2; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_3; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_4; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_5; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_6; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_7; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_8; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_9; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_10; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_11; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_12; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_13; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_14; // @[Reg.scala 19:16]
  reg [7:0] exe_stage_lsu_cache_0_stage_datBypassData_15; // @[Reg.scala 19:16]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_44 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant ?
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_45 = exe_stage_lsu_cache_0_stage__datEnW_0_T_25 ?
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_61 = exe_stage_lsu_cache_0_stage__dataW_T_44 |
    exe_stage_lsu_cache_0_stage__dataW_T_45; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_46 = exe_stage_lsu_cache_0_stage__datEnW_0_T_19 ?
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_62 = exe_stage_lsu_cache_0_stage__dataW_T_61 |
    exe_stage_lsu_cache_0_stage__dataW_T_46; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__dataW_T_6 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_w |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_d; // @[DcacheStage.scala 202:37]
  wire [3:0] exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[3:0]; // @[Util.scala 147:35]
  wire  exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_1 =
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T[3]; // @[Util.scala 147:52]
  wire [3:0] exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_2 = {
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_1, 3'h0}; // @[Util.scala 147:62]
  wire [6:0] exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3 = {
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_2, 3'h0}; // @[Util.scala 147:72]
  wire [127:0] exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_4 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata >> exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 147:26]
  wire [63:0] exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data =
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_4[63:0]; // @[Util.scala 145:26 147:18]
  wire [190:0] _GEN_820 = {{127'd0}, exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_4 = _GEN_820 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data = exe_stage_lsu_cache_0_stage__dataW_align_data_T_4[127:0]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_47 = exe_stage_lsu_cache_0_stage__dataW_T_6 ?
    exe_stage_lsu_cache_0_stage_dataW_align_data : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_63 = exe_stage_lsu_cache_0_stage__dataW_T_62 |
    exe_stage_lsu_cache_0_stage__dataW_T_47; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__high_sel_T = exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[2]; // @[DcacheStage.scala 186:39]
  wire [31:0] exe_stage_lsu_cache_0_stage__dataW_T_7 = exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data[63:32]; // @[DcacheStage.scala 203:139]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_8 = {exe_stage_lsu_cache_0_stage__dataW_T_7, 32'h0}; // @[DcacheStage.scala 203:145]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_9 = exe_stage_lsu_cache_0_stage__high_sel_T ?
    exe_stage_lsu_cache_0_stage__dataW_T_8 : exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data; // @[DcacheStage.scala 203:111]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_15; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_90 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_15; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_91 = exe_stage_lsu_cache_0_stage__T_90 ?
    exe_stage_lsu_cache_0_stage_datBypassData_15 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_15; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_14; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_88 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_14; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_89 = exe_stage_lsu_cache_0_stage__T_88 ?
    exe_stage_lsu_cache_0_stage_datBypassData_14 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_14; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_13; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_86 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_13; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_87 = exe_stage_lsu_cache_0_stage__T_86 ?
    exe_stage_lsu_cache_0_stage_datBypassData_13 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_13; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_12; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_84 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_12; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_85 = exe_stage_lsu_cache_0_stage__T_84 ?
    exe_stage_lsu_cache_0_stage_datBypassData_12 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_12; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_11; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_82 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_11; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_83 = exe_stage_lsu_cache_0_stage__T_82 ?
    exe_stage_lsu_cache_0_stage_datBypassData_11 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_11; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_10; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_80 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_10; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_81 = exe_stage_lsu_cache_0_stage__T_80 ?
    exe_stage_lsu_cache_0_stage_datBypassData_10 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_10; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_9; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_78 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_9; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_79 = exe_stage_lsu_cache_0_stage__T_78 ?
    exe_stage_lsu_cache_0_stage_datBypassData_9 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_9; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_8; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_76 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_8; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_77 = exe_stage_lsu_cache_0_stage__T_76 ?
    exe_stage_lsu_cache_0_stage_datBypassData_8 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_8; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_7; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_74 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_7; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_75 = exe_stage_lsu_cache_0_stage__T_74 ?
    exe_stage_lsu_cache_0_stage_datBypassData_7 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_7; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_6; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_72 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_6; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_73 = exe_stage_lsu_cache_0_stage__T_72 ?
    exe_stage_lsu_cache_0_stage_datBypassData_6 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_6; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_5; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_70 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_5; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_71 = exe_stage_lsu_cache_0_stage__T_70 ?
    exe_stage_lsu_cache_0_stage_datBypassData_5 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_5; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_4; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_68 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_4; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_69 = exe_stage_lsu_cache_0_stage__T_68 ?
    exe_stage_lsu_cache_0_stage_datBypassData_4 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_4; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_3; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_66 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_3; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_67 = exe_stage_lsu_cache_0_stage__T_66 ?
    exe_stage_lsu_cache_0_stage_datBypassData_3 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_3; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_2; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_64 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_2; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_65 = exe_stage_lsu_cache_0_stage__T_64 ?
    exe_stage_lsu_cache_0_stage_datBypassData_2 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_2; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_1; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_62 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_1; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_63 = exe_stage_lsu_cache_0_stage__T_62 ?
    exe_stage_lsu_cache_0_stage_datBypassData_1 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_1; // @[DcacheStage.scala 136:65]
  reg  exe_stage_lsu_cache_0_stage_datBypassWM_0; // @[Reg.scala 19:16]
  wire  exe_stage_lsu_cache_0_stage__T_60 = exe_stage_lsu_cache_0_stage_isDatBypass &
    exe_stage_lsu_cache_0_stage_datBypassWM_0; // @[DcacheStage.scala 136:78]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_61 = exe_stage_lsu_cache_0_stage__T_60 ?
    exe_stage_lsu_cache_0_stage_datBypassData_0 : exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_0; // @[DcacheStage.scala 136:65]
  wire [63:0] exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_lo = {exe_stage_lsu_cache_0_stage__T_75,
    exe_stage_lsu_cache_0_stage__T_73,exe_stage_lsu_cache_0_stage__T_71,exe_stage_lsu_cache_0_stage__T_69,
    exe_stage_lsu_cache_0_stage__T_67,exe_stage_lsu_cache_0_stage__T_65,exe_stage_lsu_cache_0_stage__T_63,
    exe_stage_lsu_cache_0_stage__T_61}; // @[Cat.scala 33:92]
  wire [127:0] exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_T = {exe_stage_lsu_cache_0_stage__T_91,
    exe_stage_lsu_cache_0_stage__T_89,exe_stage_lsu_cache_0_stage__T_87,exe_stage_lsu_cache_0_stage__T_85,
    exe_stage_lsu_cache_0_stage__T_83,exe_stage_lsu_cache_0_stage__T_81,exe_stage_lsu_cache_0_stage__T_79,
    exe_stage_lsu_cache_0_stage__T_77,exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_lo}; // @[Cat.scala 33:92]
  wire [127:0] exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_align_data_T_4 =
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_T >> exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 147:26]
  wire [63:0] exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data =
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_align_data_T_4[63:0]; // @[Util.scala 145:26 147:18]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_11 = exe_stage_lsu_cache_0_stage__dataW_T_9 +
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 203:170]
  wire [190:0] _GEN_821 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_11}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_9 = _GEN_821 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_1 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_9[127:0]
    ; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_48 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_w ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_1 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_64 = exe_stage_lsu_cache_0_stage__dataW_T_63 |
    exe_stage_lsu_cache_0_stage__dataW_T_48; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_13 = exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data +
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 204:124]
  wire [190:0] _GEN_822 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_13}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_14 = _GEN_822 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_2 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_14[127:0
    ]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_49 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_d ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_2 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_65 = exe_stage_lsu_cache_0_stage__dataW_T_64 |
    exe_stage_lsu_cache_0_stage__dataW_T_49; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__dataW_T_14 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_w |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_d; // @[DcacheStage.scala 205:37]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_15 = exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data ^
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 205:124]
  wire [190:0] _GEN_823 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_15}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_19 = _GEN_823 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_3 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_19[127:0
    ]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_50 = exe_stage_lsu_cache_0_stage__dataW_T_14 ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_3 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_66 = exe_stage_lsu_cache_0_stage__dataW_T_65 |
    exe_stage_lsu_cache_0_stage__dataW_T_50; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__dataW_T_16 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_w |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_d; // @[DcacheStage.scala 206:37]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_17 = exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data &
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 206:124]
  wire [190:0] _GEN_824 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_17}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_24 = _GEN_824 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_4 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_24[127:0
    ]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_51 = exe_stage_lsu_cache_0_stage__dataW_T_16 ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_4 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_67 = exe_stage_lsu_cache_0_stage__dataW_T_66 |
    exe_stage_lsu_cache_0_stage__dataW_T_51; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__dataW_T_18 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_w |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_d; // @[DcacheStage.scala 207:37]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_19 = exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data |
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 207:124]
  wire [190:0] _GEN_825 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_19}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_29 = _GEN_825 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_5 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_29[127:0
    ]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_52 = exe_stage_lsu_cache_0_stage__dataW_T_18 ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_5 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_68 = exe_stage_lsu_cache_0_stage__dataW_T_67 |
    exe_stage_lsu_cache_0_stage__dataW_T_52; // @[Mux.scala 27:73]
  wire [31:0] exe_stage_lsu_cache_0_stage__cmp_a_sel_T = exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data[63:32]; // @[DcacheStage.scala 193:49]
  wire [31:0] exe_stage_lsu_cache_0_stage__cmp_a_sel_T_1 = exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data[31:0]
    ; // @[DcacheStage.scala 193:74]
  wire [31:0] exe_stage_lsu_cache_0_stage_cmp_a_sel = exe_stage_lsu_cache_0_stage__high_sel_T ?
    exe_stage_lsu_cache_0_stage__cmp_a_sel_T : exe_stage_lsu_cache_0_stage__cmp_a_sel_T_1; // @[DcacheStage.scala 193:22]
  wire [31:0] exe_stage_lsu_cache_0_stage__dataW_T_20 = exe_stage_lsu_cache_0_stage__high_sel_T ?
    exe_stage_lsu_cache_0_stage__cmp_a_sel_T : exe_stage_lsu_cache_0_stage__cmp_a_sel_T_1; // @[DcacheStage.scala 210:89]
  wire [31:0] exe_stage_lsu_cache_0_stage__cmp_b_sel_T = exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data[63:32]; // @[DcacheStage.scala 194:49]
  wire [31:0] exe_stage_lsu_cache_0_stage__cmp_b_sel_T_1 = exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data[31:0]
    ; // @[DcacheStage.scala 194:74]
  wire [31:0] exe_stage_lsu_cache_0_stage_cmp_b_sel = exe_stage_lsu_cache_0_stage__high_sel_T ?
    exe_stage_lsu_cache_0_stage__cmp_b_sel_T : exe_stage_lsu_cache_0_stage__cmp_b_sel_T_1; // @[DcacheStage.scala 194:22]
  wire [31:0] exe_stage_lsu_cache_0_stage__dataW_T_21 = exe_stage_lsu_cache_0_stage__high_sel_T ?
    exe_stage_lsu_cache_0_stage__cmp_b_sel_T : exe_stage_lsu_cache_0_stage__cmp_b_sel_T_1; // @[DcacheStage.scala 210:115]
  wire  exe_stage_lsu_cache_0_stage__dataW_T_22 = $signed(exe_stage_lsu_cache_0_stage__dataW_T_20) < $signed(
    exe_stage_lsu_cache_0_stage__dataW_T_21); // @[DcacheStage.scala 210:103]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_23 = exe_stage_lsu_cache_0_stage__dataW_T_22 ?
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data : exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 210:78]
  wire [190:0] _GEN_826 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_23}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_34 = _GEN_826 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_6 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_34[127:0
    ]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_53 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_w ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_6 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_69 = exe_stage_lsu_cache_0_stage__dataW_T_68 |
    exe_stage_lsu_cache_0_stage__dataW_T_53; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_24 = exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_4[63:
    0]; // @[DcacheStage.scala 211:96]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_25 = exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_align_data_T_4[63:
    0]; // @[DcacheStage.scala 211:122]
  wire  exe_stage_lsu_cache_0_stage__dataW_T_26 = $signed(exe_stage_lsu_cache_0_stage__dataW_T_24) < $signed(
    exe_stage_lsu_cache_0_stage__dataW_T_25); // @[DcacheStage.scala 211:103]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_27 = exe_stage_lsu_cache_0_stage__dataW_T_26 ?
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data : exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 211:78]
  wire [190:0] _GEN_827 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_27}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_39 = _GEN_827 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_7 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_39[127:0
    ]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_54 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_d ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_7 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_70 = exe_stage_lsu_cache_0_stage__dataW_T_69 |
    exe_stage_lsu_cache_0_stage__dataW_T_54; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_31 = exe_stage_lsu_cache_0_stage__dataW_T_22 ?
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data : exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data; // @[DcacheStage.scala 212:78]
  wire [190:0] _GEN_828 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_31}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_44 = _GEN_828 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_8 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_44[127:0
    ]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_55 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_w ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_8 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_71 = exe_stage_lsu_cache_0_stage__dataW_T_70 |
    exe_stage_lsu_cache_0_stage__dataW_T_55; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_35 = exe_stage_lsu_cache_0_stage__dataW_T_26 ?
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data : exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data; // @[DcacheStage.scala 213:78]
  wire [190:0] _GEN_829 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_35}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_49 = _GEN_829 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_9 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_49[127:0
    ]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_56 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_d ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_9 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_72 = exe_stage_lsu_cache_0_stage__dataW_T_71 |
    exe_stage_lsu_cache_0_stage__dataW_T_56; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__dataW_T_36 = exe_stage_lsu_cache_0_stage_cmp_a_sel <
    exe_stage_lsu_cache_0_stage_cmp_b_sel; // @[DcacheStage.scala 214:103]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_37 = exe_stage_lsu_cache_0_stage__dataW_T_36 ?
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data : exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 214:78]
  wire [190:0] _GEN_830 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_37}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_54 = _GEN_830 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_10 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_54[127:
    0]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_57 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_w ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_10 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_73 = exe_stage_lsu_cache_0_stage__dataW_T_72 |
    exe_stage_lsu_cache_0_stage__dataW_T_57; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__dataW_T_38 = exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data <
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 215:103]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_39 = exe_stage_lsu_cache_0_stage__dataW_T_38 ?
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data : exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data; // @[DcacheStage.scala 215:78]
  wire [190:0] _GEN_831 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_39}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_59 = _GEN_831 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_11 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_59[127:
    0]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_58 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_d ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_11 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_74 = exe_stage_lsu_cache_0_stage__dataW_T_73 |
    exe_stage_lsu_cache_0_stage__dataW_T_58; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_41 = exe_stage_lsu_cache_0_stage__dataW_T_36 ?
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data : exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data; // @[DcacheStage.scala 216:78]
  wire [190:0] _GEN_832 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_41}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_64 = _GEN_832 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_12 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_64[127:
    0]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_59 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_w ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_12 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_75 = exe_stage_lsu_cache_0_stage__dataW_T_74 |
    exe_stage_lsu_cache_0_stage__dataW_T_59; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__dataW_T_43 = exe_stage_lsu_cache_0_stage__dataW_T_38 ?
    exe_stage_lsu_cache_0_stage_amo_reAlign_64_b_align_data : exe_stage_lsu_cache_0_stage_amo_reAlign_64_a_align_data; // @[DcacheStage.scala 217:78]
  wire [190:0] _GEN_833 = {{127'd0}, exe_stage_lsu_cache_0_stage__dataW_T_43}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu_cache_0_stage__dataW_align_data_T_69 = _GEN_833 <<
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 149:26]
  wire [127:0] exe_stage_lsu_cache_0_stage_dataW_align_data_13 = exe_stage_lsu_cache_0_stage__dataW_align_data_T_69[127:
    0]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_60 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_d ?
    exe_stage_lsu_cache_0_stage_dataW_align_data_13 : 128'h0; // @[Mux.scala 27:73]
  wire [127:0] exe_stage_lsu_cache_0_stage__dataW_T_76 = exe_stage_lsu_cache_0_stage__dataW_T_75 |
    exe_stage_lsu_cache_0_stage__dataW_T_60; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_205 = exe_stage_lsu_cache_0_stage__dataW_T_76[7:0]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_206 = exe_stage_lsu_cache_0_stage__dataW_T_76[15:8]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_207 = exe_stage_lsu_cache_0_stage__dataW_T_76[23:16]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_208 = exe_stage_lsu_cache_0_stage__dataW_T_76[31:24]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_209 = exe_stage_lsu_cache_0_stage__dataW_T_76[39:32]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_210 = exe_stage_lsu_cache_0_stage__dataW_T_76[47:40]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_211 = exe_stage_lsu_cache_0_stage__dataW_T_76[55:48]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_212 = exe_stage_lsu_cache_0_stage__dataW_T_76[63:56]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_213 = exe_stage_lsu_cache_0_stage__dataW_T_76[71:64]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_214 = exe_stage_lsu_cache_0_stage__dataW_T_76[79:72]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_215 = exe_stage_lsu_cache_0_stage__dataW_T_76[87:80]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_216 = exe_stage_lsu_cache_0_stage__dataW_T_76[95:88]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_217 = exe_stage_lsu_cache_0_stage__dataW_T_76[103:96]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_218 = exe_stage_lsu_cache_0_stage__dataW_T_76[111:104]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_219 = exe_stage_lsu_cache_0_stage__dataW_T_76[119:112]; // @[DcacheStage.scala 222:60]
  wire [7:0] exe_stage_lsu_cache_0_stage__T_220 = exe_stage_lsu_cache_0_stage__dataW_T_76[127:120]; // @[DcacheStage.scala 222:60]
  reg  exe_stage_lsu_cache_0_stage_killTrans; // @[DcacheStage.scala 146:26]
  wire  exe_stage_lsu_cache_0_stage__T_92 = exe_stage_lsu_cache_0_stage_io_flush | exe_stage_lsu_cache_0_stage_killTrans
    ; // @[DcacheStage.scala 157:18]
  wire  exe_stage_lsu_cache_0_stage__T_133 = exe_stage_lsu_cache_0_stage_pipeStage1Valid &
    exe_stage_lsu_cache_0_stage__datEnW_0_T_70; // @[DcacheStage.scala 159:32]
  wire  exe_stage_lsu_cache_0_stage__T_134 = exe_stage_lsu_cache_0_stage__T_133 & exe_stage_lsu_cache_0_stage_isHit; // @[DcacheStage.scala 159:63]
  wire  exe_stage_lsu_cache_0_stage__T_165 = exe_stage_lsu_cache_0_stage__is_sc_fail_T_32 |
    exe_stage_lsu_cache_0_stage__is_sc_fail_T_15; // @[DcacheStage.scala 164:42]
  wire  exe_stage_lsu_cache_0_stage__T_167 = ~exe_stage_lsu_cache_0_stage_reset; // @[DcacheStage.scala 164:13]
  wire  exe_stage_lsu_cache_0_stage__T_168 = ~exe_stage_lsu_cache_0_stage__T_165; // @[DcacheStage.scala 164:13]
  wire  exe_stage_lsu_cache_0_stage__T_196 = exe_stage_lsu_cache_0_stage__datEnW_0_T_19 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_58; // @[riscv_isa.scala 146:23]
  wire  exe_stage_lsu_cache_0_stage__T_197 = ~exe_stage_lsu_cache_0_stage__T_196; // @[DcacheStage.scala 167:75]
  wire  exe_stage_lsu_cache_0_stage__T_198 = exe_stage_lsu_cache_0_stage__datEnW_0_T_20 &
    exe_stage_lsu_cache_0_stage__T_197; // @[DcacheStage.scala 167:73]
  wire  exe_stage_lsu_cache_0_stage__T_199 = exe_stage_lsu_cache_0_stage__datEnW_0_T_25 |
    exe_stage_lsu_cache_0_stage__T_198; // @[DcacheStage.scala 167:44]
  wire [26:0] exe_stage_lsu_cache_0_stage__T_200 = exe_stage_lsu_cache_0_stage_lr_addr[31:5]; // @[DcacheStage.scala 168:33]
  wire  exe_stage_lsu_cache_0_stage__T_201 = exe_stage_lsu_cache_0_stage__tagInfoW_T ==
    exe_stage_lsu_cache_0_stage__T_200; // @[DcacheStage.scala 168:22]
  wire  exe_stage_lsu_cache_0_stage__GEN_35 = exe_stage_lsu_cache_0_stage__T_201 ? 1'h0 :
    exe_stage_lsu_cache_0_stage_is_pending_lr; // @[DcacheStage.scala 168:55 169:23 147:30]
  wire  exe_stage_lsu_cache_0_stage__GEN_36 = exe_stage_lsu_cache_0_stage__T_199 ? exe_stage_lsu_cache_0_stage__GEN_35
     : exe_stage_lsu_cache_0_stage_is_pending_lr; // @[DcacheStage.scala 167:107 147:30]
  wire  exe_stage_lsu_cache_0_stage__GEN_37 = exe_stage_lsu_cache_0_stage__datEnW_0_T_19 ? 1'h0 :
    exe_stage_lsu_cache_0_stage__GEN_36; // @[DcacheStage.scala 165:45 166:21]
  wire  exe_stage_lsu_cache_0_stage__GEN_38 = exe_stage_lsu_cache_0_stage__datEnW_0_T_58 |
    exe_stage_lsu_cache_0_stage__GEN_37; // @[DcacheStage.scala 160:38 161:21]
  wire  exe_stage_lsu_cache_0_stage__T_202 = exe_stage_lsu_cache_0_stage_pipeStage1Valid &
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_probe; // @[DcacheStage.scala 172:32]
  wire  exe_stage_lsu_cache_0_stage__GEN_49 = exe_stage_lsu_cache_0_stage_io_isCacheEmpty ? 1'h0 :
    exe_stage_lsu_cache_0_stage_killTrans; // @[DcacheStage.scala 180:34 181:15 146:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_50 = exe_stage_lsu_cache_0_stage_io_flush | exe_stage_lsu_cache_0_stage__GEN_49
    ; // @[DcacheStage.scala 178:20 179:15]
  wire  _GEN_428 = ~exe_stage_lsu_cache_0_stage__addrSelW_T; // @[DcacheStage.scala 228:{34,34} 84:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_51 = ~exe_stage_lsu_cache_0_stage__addrSelW_T |
    exe_stage_lsu_cache_0_stage_isCBValid_0_0; // @[DcacheStage.scala 228:{34,34} 84:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_52 = exe_stage_lsu_cache_0_stage__addrSelW_T |
    exe_stage_lsu_cache_0_stage_isCBValid_1_0; // @[DcacheStage.scala 228:{34,34} 84:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_53 = ~exe_stage_lsu_cache_0_stage__addrSelW_T ? 1'h0 :
    exe_stage_lsu_cache_0_stage_isCBDirty_0_0; // @[DcacheStage.scala 229:{34,34} 86:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_54 = exe_stage_lsu_cache_0_stage__addrSelW_T ? 1'h0 :
    exe_stage_lsu_cache_0_stage_isCBDirty_1_0; // @[DcacheStage.scala 229:{34,34} 86:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_55 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant ?
    exe_stage_lsu_cache_0_stage__GEN_51 : exe_stage_lsu_cache_0_stage_isCBValid_0_0; // @[DcacheStage.scala 227:38 84:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_56 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant ?
    exe_stage_lsu_cache_0_stage__GEN_52 : exe_stage_lsu_cache_0_stage_isCBValid_1_0; // @[DcacheStage.scala 227:38 84:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_57 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant ?
    exe_stage_lsu_cache_0_stage__GEN_53 : exe_stage_lsu_cache_0_stage_isCBDirty_0_0; // @[DcacheStage.scala 227:38 86:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_58 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant ?
    exe_stage_lsu_cache_0_stage__GEN_54 : exe_stage_lsu_cache_0_stage_isCBDirty_1_0; // @[DcacheStage.scala 227:38 86:26]
  wire  exe_stage_lsu_cache_0_stage__GEN_59 = _GEN_428 | exe_stage_lsu_cache_0_stage__GEN_57; // @[DcacheStage.scala 232:{34,34}]
  wire  exe_stage_lsu_cache_0_stage__GEN_60 = exe_stage_lsu_cache_0_stage__addrSelW_T |
    exe_stage_lsu_cache_0_stage__GEN_58; // @[DcacheStage.scala 232:{34,34}]
  wire  exe_stage_lsu_cache_0_stage__T_248 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_probe &
    exe_stage_lsu_cache_0_stage_isHit; // @[DcacheStage.scala 235:36]
  wire  exe_stage_lsu_cache_0_stage__T_253 = ~exe_stage_lsu_cache_0_stage_isHit; // @[DcacheStage.scala 283:46]
  reg  exe_stage_lsu_cache_0_stage_missUnitReqValid; // @[DcacheStage.scala 291:33]
  reg [31:0] exe_stage_lsu_cache_0_stage_missUnitReqPaddr; // @[DcacheStage.scala 292:29]
  wire  exe_stage_lsu_cache_0_stage__T_296 = exe_stage_lsu_cache_0_stage__datEnW_0_T_70 |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_preft; // @[DcacheStage.scala 297:58]
  wire  exe_stage_lsu_cache_0_stage__T_297 = exe_stage_lsu_cache_0_stage_pipeStage1Valid &
    exe_stage_lsu_cache_0_stage__T_296; // @[DcacheStage.scala 297:25]
  wire  exe_stage_lsu_cache_0_stage__T_299 = exe_stage_lsu_cache_0_stage__T_297 & exe_stage_lsu_cache_0_stage__T_253; // @[DcacheStage.scala 297:87]
  wire [31:0] exe_stage_lsu_cache_0_stage__missUnitReqPaddr_T = {{4'd0},
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[31:4]}; // @[DcacheStage.scala 299:46]
  wire [35:0] _GEN_431 = {exe_stage_lsu_cache_0_stage__missUnitReqPaddr_T, 4'h0}; // @[DcacheStage.scala 299:60]
  wire [38:0] exe_stage_lsu_cache_0_stage__missUnitReqPaddr_T_1 = {{3'd0}, _GEN_431}; // @[DcacheStage.scala 299:60]
  wire [38:0] exe_stage_lsu_cache_0_stage__GEN_74 = exe_stage_lsu_cache_0_stage__T_299 ?
    exe_stage_lsu_cache_0_stage__missUnitReqPaddr_T_1 : {{7'd0}, exe_stage_lsu_cache_0_stage_missUnitReqPaddr}; // @[DcacheStage.scala 297:102 299:22 292:29]
  reg  exe_stage_lsu_cache_0_stage_wbReqValid; // @[DcacheStage.scala 307:27]
  reg [31:0] exe_stage_lsu_cache_0_stage_wbReqPaddr; // @[DcacheStage.scala 308:23]
  reg [127:0] exe_stage_lsu_cache_0_stage_wbReqData; // @[DcacheStage.scala 309:23]
  reg  exe_stage_lsu_cache_0_stage_wbReqisData; // @[DcacheStage.scala 310:24]
  reg  exe_stage_lsu_cache_0_stage_isPb; // @[DcacheStage.scala 311:24]
  wire  exe_stage_lsu_cache_0_stage__io_wb_req_bits_is_releaseData_T = ~exe_stage_lsu_cache_0_stage_isPb; // @[DcacheStage.scala 317:51]
  wire  exe_stage_lsu_cache_0_stage__io_wb_req_bits_is_release_T = ~exe_stage_lsu_cache_0_stage_wbReqisData; // @[DcacheStage.scala 318:36]
  wire  exe_stage_lsu_cache_0_stage__T_300 = ~exe_stage_lsu_cache_0_stage__GEN_72; // @[DcacheStage.scala 322:85]
  wire  exe_stage_lsu_cache_0_stage__T_302 = ~exe_stage_lsu_cache_0_stage__T_300; // @[DcacheStage.scala 322:56]
  wire  exe_stage_lsu_cache_0_stage__T_303 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant &
    exe_stage_lsu_cache_0_stage__T_302; // @[DcacheStage.scala 322:54]
  wire  exe_stage_lsu_cache_0_stage__T_304 = exe_stage_lsu_cache_0_stage_pipeStage1Valid &
    exe_stage_lsu_cache_0_stage__T_303; // @[DcacheStage.scala 322:25]
  wire [31:0] exe_stage_lsu_cache_0_stage__wbReqPaddr_T = {exe_stage_lsu_cache_0_stage__tagInfoR_0_T,
    exe_stage_lsu_cache_0_stage__addrSelW_T,4'h0}; // @[Cat.scala 33:92]
  wire  exe_stage_lsu_cache_0_stage__GEN_76 = exe_stage_lsu_cache_0_stage__addrSelW_T ?
    exe_stage_lsu_cache_0_stage_isCBDirty_1_0 : exe_stage_lsu_cache_0_stage_isCBDirty_0_0; // @[DcacheStage.scala 326:{17,17}]
  wire  exe_stage_lsu_cache_0_stage__wbReqisData_T = exe_stage_lsu_cache_0_stage__GEN_76 &
    exe_stage_lsu_cache_0_stage_isHit; // @[DcacheStage.scala 332:47]
  wire [38:0] exe_stage_lsu_cache_0_stage__GEN_78 = exe_stage_lsu_cache_0_stage__T_202 ?
    exe_stage_lsu_cache_0_stage__missUnitReqPaddr_T_1 : {{7'd0}, exe_stage_lsu_cache_0_stage_wbReqPaddr}; // @[DcacheStage.scala 328:60 330:17 308:23]
  wire  exe_stage_lsu_cache_0_stage__GEN_81 = exe_stage_lsu_cache_0_stage__T_202 | exe_stage_lsu_cache_0_stage_isPb; // @[DcacheStage.scala 328:60 333:17 311:24]
  wire  exe_stage_lsu_cache_0_stage__GEN_82 = exe_stage_lsu_cache_0_stage__T_304 | exe_stage_lsu_cache_0_stage__T_202; // @[DcacheStage.scala 322:99 323:17]
  wire [38:0] exe_stage_lsu_cache_0_stage__GEN_83 = exe_stage_lsu_cache_0_stage__T_304 ? {{7'd0},
    exe_stage_lsu_cache_0_stage__wbReqPaddr_T} : exe_stage_lsu_cache_0_stage__GEN_78; // @[DcacheStage.scala 322:99 324:17]
  reg  exe_stage_lsu_cache_0_stage_reloadValid; // @[DcacheStage.scala 347:28]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_chkIdx; // @[DcacheStage.scala 348:24]
  reg [31:0] exe_stage_lsu_cache_0_stage_reloadBits_paddr; // @[DcacheStage.scala 348:24]
  reg [127:0] exe_stage_lsu_cache_0_stage_reloadBits_wdata; // @[DcacheStage.scala 348:24]
  reg [15:0] exe_stage_lsu_cache_0_stage_reloadBits_wstrb; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_lb; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_lh; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_lw; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_ld; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_lbu; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_lhu; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_lwu; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_sb; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_sh; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_sw; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_sd; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_lr_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_sc_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoswap_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoadd_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoxor_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoand_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoor_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomin_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomax_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amominu_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomaxu_w; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_lr_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_sc_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoswap_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoadd_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoxor_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoand_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoor_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomin_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomax_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amominu_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomaxu_d; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_flw; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_fsw; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_fld; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_fsd; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_probe; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_grant; // @[DcacheStage.scala 348:24]
  reg  exe_stage_lsu_cache_0_stage_reloadBits_fun_preft; // @[DcacheStage.scala 348:24]
  reg [5:0] exe_stage_lsu_cache_0_stage_reloadBits_rd_rd0; // @[DcacheStage.scala 348:24]
  wire  exe_stage_lsu_cache_0_stage__T_348 = exe_stage_lsu_cache_0_stage__T_133 & exe_stage_lsu_cache_0_stage__T_253; // @[DcacheStage.scala 350:56]
  reg  exe_stage_lsu_cache_0_stage_deqValid; // @[DcacheStage.scala 362:25]
  reg  exe_stage_lsu_cache_0_stage_deqBits_chkIdx; // @[DcacheStage.scala 363:21]
  reg [5:0] exe_stage_lsu_cache_0_stage_deqBits_wb_rd0; // @[DcacheStage.scala 363:21]
  reg [63:0] exe_stage_lsu_cache_0_stage_deqBits_wb_res; // @[DcacheStage.scala 363:21]
  reg  exe_stage_lsu_cache_0_stage_deqBits_is_load_amo; // @[DcacheStage.scala 363:21]
  reg  exe_stage_lsu_cache_0_stage_deqBits_is_flw; // @[DcacheStage.scala 363:21]
  reg  exe_stage_lsu_cache_0_stage_deqBits_is_fld; // @[DcacheStage.scala 363:21]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[0]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_1 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[1]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_2 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[2]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_3 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[3]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_4 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[4]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_5 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[5]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_6 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[6]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_7 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[7]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_8 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[8]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_9 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[9]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_10 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[10]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_11 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[11]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_12 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[12]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_13 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[13]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_14 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[14]; // @[Util.scala 41:14]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_15 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb[15]; // @[Util.scala 41:14]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_17 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_19 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_1 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_21 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_2 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_23 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_3 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_25 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_27 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_5 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_29 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_6 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_31 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_7 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_33 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_8 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_35 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_9 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_37 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_10 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_39 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_11 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_41 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_12 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_43 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_13 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_45 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_14 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_47 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_15 ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [63:0] exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_wmask_lo = {
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_31,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_29,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_27,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_25,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_23,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_21,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_19,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_17}; // @[Cat.scala 33:92]
  wire [127:0] exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_wmask = {
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_47,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_45,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_43,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_41,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_39,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_37,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_35,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_wmask_T_33,
    exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_wmask_lo}; // @[Cat.scala 33:92]
  wire [127:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_new_data_T = ~
    exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_wmask; // @[Util.scala 108:27]
  wire [127:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_new_data_T_1 =
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_T & exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_new_data_T
    ; // @[Util.scala 108:25]
  wire [127:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_new_data_T_2 =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata & exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_wmask; // @[Util.scala 108:44]
  wire [127:0] exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_new_data =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_new_data_T_1 |
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_new_data_T_2; // @[Util.scala 108:35]
  wire [127:0] exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_overlap_data =
    exe_stage_lsu_cache_0_stage__datEnW_0_T_59 ? exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_new_data :
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_T; // @[DcacheStage.scala 380:31]
  wire [127:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_res_align_data_T_4 =
    exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_overlap_data >>
    exe_stage_lsu_cache_0_stage__amo_reAlign_64_a_align_data_T_3; // @[Util.scala 147:26]
  wire [2:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T =
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[2:0]; // @[Util.scala 147:35]
  wire [5:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_3 = {
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T, 3'h0}; // @[Util.scala 147:72]
  wire [63:0] exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_res_align_data =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_pre_res_align_data_T_4[63:0]; // @[Util.scala 145:26 147:18]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_4 =
    exe_stage_lsu_cache_0_stage_deqBits_wb_res_res_pre_pre_res_align_data >>
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_3; // @[Util.scala 147:26]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lb |
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lbu; // @[riscv_isa.scala 153:20]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_1 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T | exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sb; // @[riscv_isa.scala 153:26]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_2 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lbu
     | exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lhu; // @[riscv_isa.scala 158:20]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_3 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_2 | exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lwu; // @[riscv_isa.scala 158:26]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_4 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_4[7]; // @[Util.scala 120:90]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_5 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_4; // @[Util.scala 120:71]
  wire [55:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_7 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_5 ? 56'hffffffffffffff : 56'h0; // @[Bitwise.scala 77:12]
  wire [7:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_8 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_4[7:0]; // @[Util.scala 120:104]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_9 = {
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_7,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_8}; // @[Cat.scala 33:92]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_10 = exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lh
     | exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lhu; // @[riscv_isa.scala 154:20]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_11 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_10 | exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sh; // @[riscv_isa.scala 154:26]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_14 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_4[15]; // @[Util.scala 121:90]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_15 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_14; // @[Util.scala 121:71]
  wire [47:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_17 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_15 ? 48'hffffffffffff : 48'h0; // @[Bitwise.scala 77:12]
  wire [15:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_18 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_4[15:0]; // @[Util.scala 121:104]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_19 = {
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_17,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_18}; // @[Cat.scala 33:92]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_37 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_4[31]; // @[Util.scala 122:90]
  wire  exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_38 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_3 ? 1'h0 :
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_37; // @[Util.scala 122:71]
  wire [31:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_40 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_38 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [31:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_41 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_4[31:0]; // @[Util.scala 122:104]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_42 = {
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_40,
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_41}; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_57 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_1 ?
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_9 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_58 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_11 ?
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_19 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_59 =
    exe_stage_lsu_cache_0_stage__is_sc_fail_T_15 ? exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_42 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_60 =
    exe_stage_lsu_cache_0_stage__is_sc_fail_T_32 ?
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_align_align_data_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_61 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_57 |
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_58; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_62 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_61 |
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_59; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_63 =
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_62 |
    exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_60; // @[Mux.scala 27:73]
  wire  exe_stage_lsu_cache_0_stage__deqBits_is_load_amo_T_31 = exe_stage_lsu_cache_0_stage__datEnW_0_T_60 |
    exe_stage_lsu_cache_0_stage__datEnW_0_T_58; // @[Dcache.scala 56:31]
  reg [31:0] exe_stage_lsu_cache_0_sbBuff_0_paddr; // @[Dcache.scala 138:23]
  reg [31:0] exe_stage_lsu_cache_0_sbBuff_1_paddr; // @[Dcache.scala 138:23]
  reg  exe_stage_lsu_cache_0_sbValid_0; // @[Dcache.scala 139:24]
  reg  exe_stage_lsu_cache_0_sbValid_1; // @[Dcache.scala 139:24]
  wire [28:0] exe_stage_lsu_cache_0__isHazard_T = exe_stage_lsu_cache_0_sbBuff_0_paddr[31:3]; // @[Dcache.scala 142:51]
  wire [28:0] exe_stage_lsu_cache_0__isHazard_T_1 = exe_stage_lsu_cache_0_io_enq_bits_paddr[31:3]; // @[Dcache.scala 142:83]
  wire  exe_stage_lsu_cache_0__isHazard_T_2 = exe_stage_lsu_cache_0__isHazard_T == exe_stage_lsu_cache_0__isHazard_T_1; // @[Dcache.scala 142:62]
  wire [28:0] exe_stage_lsu_cache_0__isHazard_T_3 = exe_stage_lsu_cache_0_sbBuff_1_paddr[31:3]; // @[Dcache.scala 142:51]
  wire  exe_stage_lsu_cache_0__isHazard_T_5 = exe_stage_lsu_cache_0__isHazard_T_3 == exe_stage_lsu_cache_0__isHazard_T_1
    ; // @[Dcache.scala 142:62]
  wire  exe_stage_lsu_cache_0_isHazard = exe_stage_lsu_cache_0__isHazard_T_2 | exe_stage_lsu_cache_0__isHazard_T_5; // @[Dcache.scala 142:106]
  wire  exe_stage_lsu_cache_0__sbIdx_T = ~exe_stage_lsu_cache_0_sbValid_0; // @[Dcache.scala 143:50]
  wire  exe_stage_lsu_cache_0_sbIdx = exe_stage_lsu_cache_0__sbIdx_T ? 1'h0 : 1'h1; // @[Dcache.scala 143:33]
  wire  exe_stage_lsu_cache_0__sbEnqReady_T_1 = ~exe_stage_lsu_cache_0_sbValid_1; // @[Dcache.scala 147:36]
  wire  exe_stage_lsu_cache_0__sbEnqReady_T_3 = exe_stage_lsu_cache_0__sbIdx_T | exe_stage_lsu_cache_0__sbEnqReady_T_1; // @[Dcache.scala 147:19]
  wire  exe_stage_lsu_cache_0__sbEnqReady_T_4 = ~exe_stage_lsu_cache_0_isHazard; // @[Dcache.scala 148:5]
  wire  exe_stage_lsu_cache_0_sbEnqReady = exe_stage_lsu_cache_0__sbEnqReady_T_3 & exe_stage_lsu_cache_0__sbEnqReady_T_4
    ; // @[Dcache.scala 147:51]
  wire  exe_stage_lsu_cache_0__T = exe_stage_lsu_cache_0_io_enq_ready & exe_stage_lsu_cache_0_io_enq_valid; // @[Decoupled.scala 52:35]
  wire [31:0] exe_stage_lsu_cache_0__GEN_2 = ~exe_stage_lsu_cache_0_sbIdx ? exe_stage_lsu_cache_0_io_enq_bits_paddr :
    exe_stage_lsu_cache_0_sbBuff_0_paddr; // @[Dcache.scala 151:{20,20} 138:23]
  wire [31:0] exe_stage_lsu_cache_0__GEN_3 = exe_stage_lsu_cache_0_sbIdx ? exe_stage_lsu_cache_0_io_enq_bits_paddr :
    exe_stage_lsu_cache_0_sbBuff_1_paddr; // @[Dcache.scala 151:{20,20} 138:23]
  wire  exe_stage_lsu_cache_0__GEN_96 = ~exe_stage_lsu_cache_0_sbIdx | exe_stage_lsu_cache_0_sbValid_0; // @[Dcache.scala 152:{20,20} 139:24]
  wire  exe_stage_lsu_cache_0__GEN_97 = exe_stage_lsu_cache_0_sbIdx | exe_stage_lsu_cache_0_sbValid_1; // @[Dcache.scala 152:{20,20} 139:24]
  wire [31:0] exe_stage_lsu_cache_0__GEN_100 = exe_stage_lsu_cache_0__T ? exe_stage_lsu_cache_0__GEN_2 :
    exe_stage_lsu_cache_0_sbBuff_0_paddr; // @[Dcache.scala 138:23 150:23]
  wire [31:0] exe_stage_lsu_cache_0__GEN_101 = exe_stage_lsu_cache_0__T ? exe_stage_lsu_cache_0__GEN_3 :
    exe_stage_lsu_cache_0_sbBuff_1_paddr; // @[Dcache.scala 138:23 150:23]
  wire  exe_stage_lsu_cache_0__GEN_194 = exe_stage_lsu_cache_0__T ? exe_stage_lsu_cache_0__GEN_96 :
    exe_stage_lsu_cache_0_sbValid_0; // @[Dcache.scala 150:23 139:24]
  wire  exe_stage_lsu_cache_0__GEN_195 = exe_stage_lsu_cache_0__T ? exe_stage_lsu_cache_0__GEN_97 :
    exe_stage_lsu_cache_0_sbValid_1; // @[Dcache.scala 150:23 139:24]
  wire  exe_stage_lsu_cache_0__T_1 = exe_stage_lsu_cache_0_io_deq_ready & exe_stage_lsu_cache_0_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_cache_0_isSBEmpty = exe_stage_lsu_cache_0__sbIdx_T & exe_stage_lsu_cache_0__sbEnqReady_T_1; // @[Dcache.scala 160:33]
  wire  exe_stage_lsu_cache_0__T_3 = ~exe_stage_lsu_cache_0_isSBEmpty; // @[Dcache.scala 161:32]
  wire  exe_stage_lsu_cache_0__T_5 = ~exe_stage_lsu_cache_0_reset; // @[Dcache.scala 161:31]
  wire  exe_stage_lsu_cache_0__T_6 = ~exe_stage_lsu_cache_0__T_3; // @[Dcache.scala 161:31]
  wire  exe_stage_lsu_cache_0__T_9 = exe_stage_lsu_cache_0_sbBuff_1_paddr == exe_stage_lsu_cache_0_sbBuff_0_paddr; // @[Dcache.scala 168:64]
  wire [1:0] exe_stage_lsu_cache_0__T_10 = 1'h1 + exe_stage_lsu_cache_0__T_9; // @[Dcache.scala 168:27]
  wire  exe_stage_lsu_cache_0__T_12 = exe_stage_lsu_cache_0__T_10 == 2'h1; // @[Dcache.scala 168:87]
  wire  exe_stage_lsu_cache_0__T_15 = ~exe_stage_lsu_cache_0__T_12; // @[Dcache.scala 168:13]
  wire  exe_stage_lsu_cache_0__T_17 = exe_stage_lsu_cache_0_sbBuff_0_paddr == exe_stage_lsu_cache_0_sbBuff_1_paddr; // @[Dcache.scala 168:64]
  wire [1:0] exe_stage_lsu_cache_0__T_19 = exe_stage_lsu_cache_0__T_17 + 1'h1; // @[Dcache.scala 168:27]
  wire  exe_stage_lsu_cache_0__T_21 = exe_stage_lsu_cache_0__T_19 == 2'h1; // @[Dcache.scala 168:87]
  wire  exe_stage_lsu_cache_0__T_24 = ~exe_stage_lsu_cache_0__T_21; // @[Dcache.scala 168:13]
  wire  exe_stage_lsu_cache_0__T_27 = ~exe_stage_lsu_cache_0_reload_fifo_io_enq_ready; // @[Dcache.scala 281:41]
  wire  exe_stage_lsu_cache_0__T_30 = ~exe_stage_lsu_cache_0_rtn_fifo_io_enq_ready; // @[Dcache.scala 282:38]
  wire  exe_stage_lsu_lu_wb_arb_io_in_0_ready;
  wire  exe_stage_lsu_lu_wb_arb_io_in_0_valid;
  wire [5:0] exe_stage_lsu_lu_wb_arb_io_in_0_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_lu_wb_arb_io_in_0_bits_wb_res;
  wire  exe_stage_lsu_lu_wb_arb_io_in_0_bits_is_flw;
  wire  exe_stage_lsu_lu_wb_arb_io_in_0_bits_is_fld;
  wire  exe_stage_lsu_lu_wb_arb_io_in_1_ready;
  wire  exe_stage_lsu_lu_wb_arb_io_in_1_valid;
  wire [5:0] exe_stage_lsu_lu_wb_arb_io_in_1_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_lu_wb_arb_io_in_1_bits_wb_res;
  wire  exe_stage_lsu_lu_wb_arb_io_in_1_bits_is_flw;
  wire  exe_stage_lsu_lu_wb_arb_io_in_1_bits_is_fld;
  wire  exe_stage_lsu_lu_wb_arb_io_in_2_ready;
  wire  exe_stage_lsu_lu_wb_arb_io_in_2_valid;
  wire [5:0] exe_stage_lsu_lu_wb_arb_io_in_2_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_lu_wb_arb_io_in_2_bits_wb_res;
  wire  exe_stage_lsu_lu_wb_arb_io_in_2_bits_is_flw;
  wire  exe_stage_lsu_lu_wb_arb_io_in_2_bits_is_fld;
  wire  exe_stage_lsu_lu_wb_arb_io_out_ready;
  wire  exe_stage_lsu_lu_wb_arb_io_out_valid;
  wire [5:0] exe_stage_lsu_lu_wb_arb_io_out_bits_wb_rd0;
  wire [63:0] exe_stage_lsu_lu_wb_arb_io_out_bits_wb_res;
  wire  exe_stage_lsu_lu_wb_arb_io_out_bits_is_flw;
  wire  exe_stage_lsu_lu_wb_arb_io_out_bits_is_fld;
  wire [5:0] exe_stage_lsu_lu_wb_arb__GEN_2 = exe_stage_lsu_lu_wb_arb_io_in_1_valid ?
    exe_stage_lsu_lu_wb_arb_io_in_1_bits_wb_rd0 : exe_stage_lsu_lu_wb_arb_io_in_2_bits_wb_rd0; // @[Arbiter.scala 136:15 138:26 140:19]
  wire [63:0] exe_stage_lsu_lu_wb_arb__GEN_3 = exe_stage_lsu_lu_wb_arb_io_in_1_valid ?
    exe_stage_lsu_lu_wb_arb_io_in_1_bits_wb_res : exe_stage_lsu_lu_wb_arb_io_in_2_bits_wb_res; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_lu_wb_arb__GEN_5 = exe_stage_lsu_lu_wb_arb_io_in_1_valid ?
    exe_stage_lsu_lu_wb_arb_io_in_1_bits_is_flw : exe_stage_lsu_lu_wb_arb_io_in_2_bits_is_flw; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_lu_wb_arb__GEN_6 = exe_stage_lsu_lu_wb_arb_io_in_1_valid ?
    exe_stage_lsu_lu_wb_arb_io_in_1_bits_is_fld : exe_stage_lsu_lu_wb_arb_io_in_2_bits_is_fld; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_lu_wb_arb__grant_T = exe_stage_lsu_lu_wb_arb_io_in_0_valid | exe_stage_lsu_lu_wb_arb_io_in_1_valid
    ; // @[Arbiter.scala 45:68]
  wire  exe_stage_lsu_lu_wb_arb_grant_1 = ~exe_stage_lsu_lu_wb_arb_io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  exe_stage_lsu_lu_wb_arb_grant_2 = ~exe_stage_lsu_lu_wb_arb__grant_T; // @[Arbiter.scala 45:78]
  wire  exe_stage_lsu_lu_wb_arb__io_out_valid_T = ~exe_stage_lsu_lu_wb_arb_grant_2; // @[Arbiter.scala 147:19]
  wire  exe_stage_lsu_lu_wb_fifo_clock;
  wire  exe_stage_lsu_lu_wb_fifo_reset;
  wire  exe_stage_lsu_lu_wb_fifo_io_enq_ready;
  wire  exe_stage_lsu_lu_wb_fifo_io_enq_valid;
  wire [5:0] exe_stage_lsu_lu_wb_fifo_io_enq_bits_rd0;
  wire [63:0] exe_stage_lsu_lu_wb_fifo_io_enq_bits_res;
  wire  exe_stage_lsu_lu_wb_fifo_io_deq_ready;
  wire  exe_stage_lsu_lu_wb_fifo_io_deq_valid;
  wire [5:0] exe_stage_lsu_lu_wb_fifo_io_deq_bits_rd0;
  wire [63:0] exe_stage_lsu_lu_wb_fifo_io_deq_bits_res;
  reg [5:0] exe_stage_lsu_lu_wb_fifo_ram_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_lu_wb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_rd0_clock;
  reg [63:0] exe_stage_lsu_lu_wb_fifo_ram_res [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_res_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_res_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_lsu_lu_wb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_lu_wb_fifo_ram_res_clock;
  reg  exe_stage_lsu_lu_wb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_lu_wb_fifo__empty_T = ~exe_stage_lsu_lu_wb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_lu_wb_fifo__do_enq_T = exe_stage_lsu_lu_wb_fifo_io_enq_ready &
    exe_stage_lsu_lu_wb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_lu_wb_fifo__do_deq_T = exe_stage_lsu_lu_wb_fifo_io_deq_ready &
    exe_stage_lsu_lu_wb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_lu_wb_fifo__GEN_10 = exe_stage_lsu_lu_wb_fifo_io_deq_ready ? 1'h0 :
    exe_stage_lsu_lu_wb_fifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  exe_stage_lsu_lu_wb_fifo__GEN_14 = exe_stage_lsu_lu_wb_fifo__empty_T ? exe_stage_lsu_lu_wb_fifo__GEN_10 :
    exe_stage_lsu_lu_wb_fifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  exe_stage_lsu_lu_wb_fifo__GEN_13 = exe_stage_lsu_lu_wb_fifo__empty_T ? 1'h0 : exe_stage_lsu_lu_wb_fifo__do_deq_T
    ; // @[Decoupled.scala 317:17 319:14]
  wire  exe_stage_lsu_lu_wb_fifo__T = exe_stage_lsu_lu_wb_fifo__GEN_14 != exe_stage_lsu_lu_wb_fifo__GEN_13; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_lu_wb_fifo__io_deq_valid_T = ~exe_stage_lsu_lu_wb_fifo__empty_T; // @[Decoupled.scala 304:19]
  wire  exe_stage_lsu_flu_wb_fifo_clock;
  wire  exe_stage_lsu_flu_wb_fifo_reset;
  wire  exe_stage_lsu_flu_wb_fifo_io_enq_ready;
  wire  exe_stage_lsu_flu_wb_fifo_io_enq_valid;
  wire  exe_stage_lsu_flu_wb_fifo_io_deq_ready;
  wire  exe_stage_lsu_flu_wb_fifo_io_deq_valid;
  reg  exe_stage_lsu_flu_wb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_flu_wb_fifo__empty_T = ~exe_stage_lsu_flu_wb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_flu_wb_fifo__do_enq_T = exe_stage_lsu_flu_wb_fifo_io_enq_ready &
    exe_stage_lsu_flu_wb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_flu_wb_fifo__do_deq_T = exe_stage_lsu_flu_wb_fifo_io_deq_ready &
    exe_stage_lsu_flu_wb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_flu_wb_fifo__GEN_10 = exe_stage_lsu_flu_wb_fifo_io_deq_ready ? 1'h0 :
    exe_stage_lsu_flu_wb_fifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  exe_stage_lsu_flu_wb_fifo__GEN_14 = exe_stage_lsu_flu_wb_fifo__empty_T ? exe_stage_lsu_flu_wb_fifo__GEN_10 :
    exe_stage_lsu_flu_wb_fifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  exe_stage_lsu_flu_wb_fifo__GEN_13 = exe_stage_lsu_flu_wb_fifo__empty_T ? 1'h0 :
    exe_stage_lsu_flu_wb_fifo__do_deq_T; // @[Decoupled.scala 317:17 319:14]
  wire  exe_stage_lsu_flu_wb_fifo__T = exe_stage_lsu_flu_wb_fifo__GEN_14 != exe_stage_lsu_flu_wb_fifo__GEN_13; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_flu_wb_fifo__io_deq_valid_T = ~exe_stage_lsu_flu_wb_fifo__empty_T; // @[Decoupled.scala 304:19]
  wire  exe_stage_lsu_su_wb_fifo_clock;
  wire  exe_stage_lsu_su_wb_fifo_reset;
  wire  exe_stage_lsu_su_wb_fifo_io_enq_ready;
  wire  exe_stage_lsu_su_wb_fifo_io_enq_valid;
  wire [5:0] exe_stage_lsu_su_wb_fifo_io_enq_bits_rd0;
  wire  exe_stage_lsu_su_wb_fifo_io_deq_ready;
  wire  exe_stage_lsu_su_wb_fifo_io_deq_valid;
  wire [5:0] exe_stage_lsu_su_wb_fifo_io_deq_bits_rd0;
  wire [63:0] exe_stage_lsu_su_wb_fifo_io_deq_bits_res;
  reg [5:0] exe_stage_lsu_su_wb_fifo_ram_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_su_wb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_rd0_clock;
  reg [63:0] exe_stage_lsu_su_wb_fifo_ram_res [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_res_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_res_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_lsu_su_wb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_lsu_su_wb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_res_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_res_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_res_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_su_wb_fifo_ram_res_clock;
  reg  exe_stage_lsu_su_wb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_su_wb_fifo__empty_T = ~exe_stage_lsu_su_wb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_su_wb_fifo__do_enq_T = exe_stage_lsu_su_wb_fifo_io_enq_ready &
    exe_stage_lsu_su_wb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_su_wb_fifo__do_deq_T = exe_stage_lsu_su_wb_fifo_io_deq_ready &
    exe_stage_lsu_su_wb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_su_wb_fifo__GEN_10 = exe_stage_lsu_su_wb_fifo_io_deq_ready ? 1'h0 :
    exe_stage_lsu_su_wb_fifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  exe_stage_lsu_su_wb_fifo__GEN_14 = exe_stage_lsu_su_wb_fifo__empty_T ? exe_stage_lsu_su_wb_fifo__GEN_10 :
    exe_stage_lsu_su_wb_fifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  exe_stage_lsu_su_wb_fifo__GEN_13 = exe_stage_lsu_su_wb_fifo__empty_T ? 1'h0 : exe_stage_lsu_su_wb_fifo__do_deq_T
    ; // @[Decoupled.scala 317:17 319:14]
  wire  exe_stage_lsu_su_wb_fifo__T = exe_stage_lsu_su_wb_fifo__GEN_14 != exe_stage_lsu_su_wb_fifo__GEN_13; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_su_wb_fifo__io_deq_valid_T = ~exe_stage_lsu_su_wb_fifo__empty_T; // @[Decoupled.scala 304:19]
  wire  exe_stage_lsu_fe_wb_fifo_clock;
  wire  exe_stage_lsu_fe_wb_fifo_reset;
  wire  exe_stage_lsu_fe_wb_fifo_io_enq_ready;
  wire  exe_stage_lsu_fe_wb_fifo_io_enq_valid;
  wire [5:0] exe_stage_lsu_fe_wb_fifo_io_enq_bits_rd0;
  wire  exe_stage_lsu_fe_wb_fifo_io_deq_ready;
  wire  exe_stage_lsu_fe_wb_fifo_io_deq_valid;
  wire [5:0] exe_stage_lsu_fe_wb_fifo_io_deq_bits_rd0;
  wire [63:0] exe_stage_lsu_fe_wb_fifo_io_deq_bits_res;
  reg [5:0] exe_stage_lsu_fe_wb_fifo_ram_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_fe_wb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_rd0_clock;
  reg [63:0] exe_stage_lsu_fe_wb_fifo_ram_res [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_res_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_res_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_lsu_fe_wb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_lsu_fe_wb_fifo_ram_res_clock;
  reg  exe_stage_lsu_fe_wb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_lsu_fe_wb_fifo__empty_T = ~exe_stage_lsu_fe_wb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_lsu_fe_wb_fifo__do_enq_T = exe_stage_lsu_fe_wb_fifo_io_enq_ready &
    exe_stage_lsu_fe_wb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_fe_wb_fifo__do_deq_T = exe_stage_lsu_fe_wb_fifo_io_deq_ready &
    exe_stage_lsu_fe_wb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu_fe_wb_fifo__GEN_10 = exe_stage_lsu_fe_wb_fifo_io_deq_ready ? 1'h0 :
    exe_stage_lsu_fe_wb_fifo__do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  exe_stage_lsu_fe_wb_fifo__GEN_14 = exe_stage_lsu_fe_wb_fifo__empty_T ? exe_stage_lsu_fe_wb_fifo__GEN_10 :
    exe_stage_lsu_fe_wb_fifo__do_enq_T; // @[Decoupled.scala 317:17]
  wire  exe_stage_lsu_fe_wb_fifo__GEN_13 = exe_stage_lsu_fe_wb_fifo__empty_T ? 1'h0 : exe_stage_lsu_fe_wb_fifo__do_deq_T
    ; // @[Decoupled.scala 317:17 319:14]
  wire  exe_stage_lsu_fe_wb_fifo__T = exe_stage_lsu_fe_wb_fifo__GEN_14 != exe_stage_lsu_fe_wb_fifo__GEN_13; // @[Decoupled.scala 295:15]
  wire  exe_stage_lsu_fe_wb_fifo__io_deq_valid_T = ~exe_stage_lsu_fe_wb_fifo__empty_T; // @[Decoupled.scala 304:19]
  wire  exe_stage_lsu_rtn_arb_io_in_0_ready;
  wire  exe_stage_lsu_rtn_arb_io_in_0_valid;
  wire [5:0] exe_stage_lsu_rtn_arb_io_in_0_bits_rd0;
  wire [63:0] exe_stage_lsu_rtn_arb_io_in_0_bits_res;
  wire  exe_stage_lsu_rtn_arb_io_in_1_ready;
  wire  exe_stage_lsu_rtn_arb_io_in_1_valid;
  wire [5:0] exe_stage_lsu_rtn_arb_io_in_1_bits_rd0;
  wire [63:0] exe_stage_lsu_rtn_arb_io_in_1_bits_res;
  wire  exe_stage_lsu_rtn_arb_io_in_2_ready;
  wire  exe_stage_lsu_rtn_arb_io_in_2_valid;
  wire [5:0] exe_stage_lsu_rtn_arb_io_in_2_bits_rd0;
  wire [63:0] exe_stage_lsu_rtn_arb_io_in_2_bits_res;
  wire  exe_stage_lsu_rtn_arb_io_out_ready;
  wire  exe_stage_lsu_rtn_arb_io_out_valid;
  wire [5:0] exe_stage_lsu_rtn_arb_io_out_bits_rd0;
  wire [63:0] exe_stage_lsu_rtn_arb_io_out_bits_res;
  wire [5:0] exe_stage_lsu_rtn_arb__GEN_1 = exe_stage_lsu_rtn_arb_io_in_1_valid ? exe_stage_lsu_rtn_arb_io_in_1_bits_rd0
     : exe_stage_lsu_rtn_arb_io_in_2_bits_rd0; // @[Arbiter.scala 136:15 138:26 140:19]
  wire [63:0] exe_stage_lsu_rtn_arb__GEN_2 = exe_stage_lsu_rtn_arb_io_in_1_valid ?
    exe_stage_lsu_rtn_arb_io_in_1_bits_res : exe_stage_lsu_rtn_arb_io_in_2_bits_res; // @[Arbiter.scala 136:15 138:26 140:19]
  wire  exe_stage_lsu_rtn_arb__grant_T = exe_stage_lsu_rtn_arb_io_in_0_valid | exe_stage_lsu_rtn_arb_io_in_1_valid; // @[Arbiter.scala 45:68]
  wire  exe_stage_lsu_rtn_arb_grant_1 = ~exe_stage_lsu_rtn_arb_io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  exe_stage_lsu_rtn_arb_grant_2 = ~exe_stage_lsu_rtn_arb__grant_T; // @[Arbiter.scala 45:78]
  wire  exe_stage_lsu_rtn_arb__io_out_valid_T = ~exe_stage_lsu_rtn_arb_grant_2; // @[Arbiter.scala 147:19]
  wire  exe_stage_lsu_acquireArb_io_in_0_ready;
  wire  exe_stage_lsu_acquireArb_io_in_0_valid;
  wire [2:0] exe_stage_lsu_acquireArb_io_in_0_bits_opcode;
  wire [2:0] exe_stage_lsu_acquireArb_io_in_0_bits_param;
  wire [2:0] exe_stage_lsu_acquireArb_io_in_0_bits_size;
  wire  exe_stage_lsu_acquireArb_io_in_0_bits_source;
  wire [31:0] exe_stage_lsu_acquireArb_io_in_0_bits_address;
  wire [7:0] exe_stage_lsu_acquireArb_io_in_0_bits_mask;
  wire [63:0] exe_stage_lsu_acquireArb_io_in_0_bits_data;
  wire  exe_stage_lsu_acquireArb_io_in_0_bits_corrupt;
  wire  exe_stage_lsu_acquireArb_io_out_ready;
  wire  exe_stage_lsu_acquireArb_io_out_valid;
  wire [2:0] exe_stage_lsu_acquireArb_io_out_bits_opcode;
  wire [2:0] exe_stage_lsu_acquireArb_io_out_bits_param;
  wire [2:0] exe_stage_lsu_acquireArb_io_out_bits_size;
  wire  exe_stage_lsu_acquireArb_io_out_bits_source;
  wire [31:0] exe_stage_lsu_acquireArb_io_out_bits_address;
  wire [7:0] exe_stage_lsu_acquireArb_io_out_bits_mask;
  wire [63:0] exe_stage_lsu_acquireArb_io_out_bits_data;
  wire  exe_stage_lsu_acquireArb_io_out_bits_corrupt;
  wire  exe_stage_lsu_grantAckArb_io_in_0_ready;
  wire  exe_stage_lsu_grantAckArb_io_in_0_valid;
  wire [4:0] exe_stage_lsu_grantAckArb_io_in_0_bits_sink;
  wire  exe_stage_lsu_grantAckArb_io_out_ready;
  wire  exe_stage_lsu_grantAckArb_io_out_valid;
  wire [4:0] exe_stage_lsu_grantAckArb_io_out_bits_sink;
  wire  exe_stage_lsu_releaseArb_io_in_0_ready;
  wire  exe_stage_lsu_releaseArb_io_in_0_valid;
  wire [2:0] exe_stage_lsu_releaseArb_io_in_0_bits_opcode;
  wire [2:0] exe_stage_lsu_releaseArb_io_in_0_bits_param;
  wire [2:0] exe_stage_lsu_releaseArb_io_in_0_bits_size;
  wire  exe_stage_lsu_releaseArb_io_in_0_bits_source;
  wire [31:0] exe_stage_lsu_releaseArb_io_in_0_bits_address;
  wire [63:0] exe_stage_lsu_releaseArb_io_in_0_bits_data;
  wire  exe_stage_lsu_releaseArb_io_in_0_bits_corrupt;
  wire  exe_stage_lsu_releaseArb_io_out_ready;
  wire  exe_stage_lsu_releaseArb_io_out_valid;
  wire [2:0] exe_stage_lsu_releaseArb_io_out_bits_opcode;
  wire [2:0] exe_stage_lsu_releaseArb_io_out_bits_param;
  wire [2:0] exe_stage_lsu_releaseArb_io_out_bits_size;
  wire  exe_stage_lsu_releaseArb_io_out_bits_source;
  wire [31:0] exe_stage_lsu_releaseArb_io_out_bits_address;
  wire [63:0] exe_stage_lsu_releaseArb_io_out_bits_data;
  wire  exe_stage_lsu_releaseArb_io_out_bits_corrupt;
  reg  exe_stage_lsu_trans_kill; // @[Lsu.scala 73:27]
  wire  exe_stage_lsu__addrTransIO_valid_T = exe_stage_lsu_io_mmu_lsu_bits_is_access_fault |
    exe_stage_lsu_io_mmu_lsu_bits_is_paging_fault; // @[MMU.scala 77:34]
  wire  exe_stage_lsu__addrTransIO_valid_T_1 = ~exe_stage_lsu__addrTransIO_valid_T; // @[Lsu.scala 136:43]
  wire  exe_stage_lsu__addrTransIO_valid_T_2 = exe_stage_lsu_io_mmu_lsu_valid & exe_stage_lsu__addrTransIO_valid_T_1; // @[Lsu.scala 136:41]
  wire  exe_stage_lsu__addrTransIO_valid_T_3 = exe_stage_lsu_io_lsu_iss_exe_bits_fun_lh |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_lhu; // @[riscv_isa.scala 154:20]
  wire  exe_stage_lsu__addrTransIO_valid_T_4 = exe_stage_lsu__addrTransIO_valid_T_3 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_sh; // @[riscv_isa.scala 154:26]
  wire  exe_stage_lsu__addrTransIO_valid_T_5 = exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op1[0]; // @[riscv_isa.scala 898:36]
  wire  exe_stage_lsu__addrTransIO_valid_T_7 = exe_stage_lsu_io_lsu_iss_exe_bits_fun_lw |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_lwu; // @[riscv_isa.scala 155:20]
  wire  exe_stage_lsu__addrTransIO_valid_T_8 = exe_stage_lsu__addrTransIO_valid_T_7 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_sw; // @[riscv_isa.scala 155:26]
  wire  exe_stage_lsu__addrTransIO_valid_T_9 = exe_stage_lsu__addrTransIO_valid_T_8 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_w; // @[riscv_isa.scala 155:31]
  wire  exe_stage_lsu__addrTransIO_valid_T_10 = exe_stage_lsu__addrTransIO_valid_T_9 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_w; // @[riscv_isa.scala 155:43]
  wire  exe_stage_lsu__addrTransIO_valid_T_11 = exe_stage_lsu__addrTransIO_valid_T_10 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_w; // @[riscv_isa.scala 155:54]
  wire  exe_stage_lsu__addrTransIO_valid_T_12 = exe_stage_lsu__addrTransIO_valid_T_11 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_w; // @[riscv_isa.scala 155:65]
  wire  exe_stage_lsu__addrTransIO_valid_T_13 = exe_stage_lsu__addrTransIO_valid_T_12 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_w; // @[riscv_isa.scala 155:76]
  wire  exe_stage_lsu__addrTransIO_valid_T_14 = exe_stage_lsu__addrTransIO_valid_T_13 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_w; // @[riscv_isa.scala 155:86]
  wire  exe_stage_lsu__addrTransIO_valid_T_15 = exe_stage_lsu__addrTransIO_valid_T_14 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_w; // @[riscv_isa.scala 155:97]
  wire  exe_stage_lsu__addrTransIO_valid_T_16 = exe_stage_lsu__addrTransIO_valid_T_15 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_w; // @[riscv_isa.scala 155:108]
  wire  exe_stage_lsu__addrTransIO_valid_T_17 = exe_stage_lsu__addrTransIO_valid_T_16 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_w; // @[riscv_isa.scala 155:120]
  wire  exe_stage_lsu__addrTransIO_valid_T_18 = exe_stage_lsu__addrTransIO_valid_T_17 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_flw; // @[riscv_isa.scala 155:132]
  wire  exe_stage_lsu__addrTransIO_valid_T_19 = exe_stage_lsu__addrTransIO_valid_T_18 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsw; // @[riscv_isa.scala 155:138]
  wire  exe_stage_lsu__addrTransIO_valid_T_20 = exe_stage_lsu__addrTransIO_valid_T_19 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_w; // @[riscv_isa.scala 155:144]
  wire  exe_stage_lsu__addrTransIO_valid_T_21 = exe_stage_lsu__addrTransIO_valid_T_20 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_w; // @[riscv_isa.scala 155:151]
  wire [1:0] exe_stage_lsu__addrTransIO_valid_T_22 = exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op1[1:0]; // @[riscv_isa.scala 899:36]
  wire  exe_stage_lsu__addrTransIO_valid_T_23 = exe_stage_lsu__addrTransIO_valid_T_22 != 2'h0; // @[riscv_isa.scala 899:42]
  wire  exe_stage_lsu__addrTransIO_valid_T_24 = exe_stage_lsu_io_lsu_iss_exe_bits_fun_ld |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_d; // @[riscv_isa.scala 156:20]
  wire  exe_stage_lsu__addrTransIO_valid_T_25 = exe_stage_lsu__addrTransIO_valid_T_24 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_fld; // @[riscv_isa.scala 156:27]
  wire  exe_stage_lsu__addrTransIO_valid_T_26 = exe_stage_lsu__addrTransIO_valid_T_25 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_sd; // @[riscv_isa.scala 156:33]
  wire  exe_stage_lsu__addrTransIO_valid_T_27 = exe_stage_lsu__addrTransIO_valid_T_26 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_d; // @[riscv_isa.scala 156:38]
  wire  exe_stage_lsu__addrTransIO_valid_T_28 = exe_stage_lsu__addrTransIO_valid_T_27 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsd; // @[riscv_isa.scala 156:45]
  wire  exe_stage_lsu__addrTransIO_valid_T_29 = exe_stage_lsu__addrTransIO_valid_T_28 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_d; // @[riscv_isa.scala 156:51]
  wire  exe_stage_lsu__addrTransIO_valid_T_30 = exe_stage_lsu__addrTransIO_valid_T_29 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_d; // @[riscv_isa.scala 156:63]
  wire  exe_stage_lsu__addrTransIO_valid_T_31 = exe_stage_lsu__addrTransIO_valid_T_30 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_d; // @[riscv_isa.scala 156:74]
  wire  exe_stage_lsu__addrTransIO_valid_T_32 = exe_stage_lsu__addrTransIO_valid_T_31 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_d; // @[riscv_isa.scala 156:85]
  wire  exe_stage_lsu__addrTransIO_valid_T_33 = exe_stage_lsu__addrTransIO_valid_T_32 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_d; // @[riscv_isa.scala 156:96]
  wire  exe_stage_lsu__addrTransIO_valid_T_34 = exe_stage_lsu__addrTransIO_valid_T_33 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_d; // @[riscv_isa.scala 156:106]
  wire  exe_stage_lsu__addrTransIO_valid_T_35 = exe_stage_lsu__addrTransIO_valid_T_34 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_d; // @[riscv_isa.scala 156:117]
  wire  exe_stage_lsu__addrTransIO_valid_T_36 = exe_stage_lsu__addrTransIO_valid_T_35 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_d; // @[riscv_isa.scala 156:128]
  wire  exe_stage_lsu__addrTransIO_valid_T_37 = exe_stage_lsu__addrTransIO_valid_T_36 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_d; // @[riscv_isa.scala 156:140]
  wire [2:0] exe_stage_lsu__addrTransIO_valid_T_38 = exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op1[2:0]; // @[riscv_isa.scala 900:36]
  wire  exe_stage_lsu__addrTransIO_valid_T_39 = exe_stage_lsu__addrTransIO_valid_T_38 != 3'h0; // @[riscv_isa.scala 900:42]
  wire  exe_stage_lsu__addrTransIO_valid_T_40 = exe_stage_lsu__addrTransIO_valid_T_4 &
    exe_stage_lsu__addrTransIO_valid_T_5; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__addrTransIO_valid_T_41 = exe_stage_lsu__addrTransIO_valid_T_21 &
    exe_stage_lsu__addrTransIO_valid_T_23; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__addrTransIO_valid_T_42 = exe_stage_lsu__addrTransIO_valid_T_37 &
    exe_stage_lsu__addrTransIO_valid_T_39; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__addrTransIO_valid_T_43 = exe_stage_lsu__addrTransIO_valid_T_40 |
    exe_stage_lsu__addrTransIO_valid_T_41; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__addrTransIO_valid_T_44 = exe_stage_lsu__addrTransIO_valid_T_43 |
    exe_stage_lsu__addrTransIO_valid_T_42; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__addrTransIO_valid_T_45 = ~exe_stage_lsu__addrTransIO_valid_T_44; // @[Lsu.scala 136:71]
  wire  exe_stage_lsu__addrTransIO_valid_T_46 = exe_stage_lsu__addrTransIO_valid_T_2 &
    exe_stage_lsu__addrTransIO_valid_T_45; // @[Lsu.scala 136:69]
  wire  exe_stage_lsu__addrTransIO_valid_T_47 = exe_stage_lsu_io_lsu_iss_exe_bits_fun_fence |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_fence_i; // @[riscv_isa.scala 150:24]
  wire  exe_stage_lsu__addrTransIO_valid_T_48 = exe_stage_lsu__addrTransIO_valid_T_47 |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_sfence_vma; // @[riscv_isa.scala 150:34]
  wire  exe_stage_lsu__addrTransIO_valid_T_49 = exe_stage_lsu_trans_kill | exe_stage_lsu__addrTransIO_valid_T_48; // @[Lsu.scala 136:119]
  wire  exe_stage_lsu__addrTransIO_valid_T_50 = ~exe_stage_lsu__addrTransIO_valid_T_49; // @[Lsu.scala 136:106]
  wire  exe_stage_lsu__addrTransIO_valid_T_51 = exe_stage_lsu__addrTransIO_valid_T_46 &
    exe_stage_lsu__addrTransIO_valid_T_50; // @[Lsu.scala 136:104]
  wire  exe_stage_lsu__T_15 = exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_w |
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_w; // @[riscv_isa.scala 148:15]
  wire  exe_stage_lsu__T_16 = exe_stage_lsu__T_15 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_w; // @[riscv_isa.scala 148:26]
  wire  exe_stage_lsu__T_17 = exe_stage_lsu__T_16 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_w; // @[riscv_isa.scala 148:37]
  wire  exe_stage_lsu__T_18 = exe_stage_lsu__T_17 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_w; // @[riscv_isa.scala 148:48]
  wire  exe_stage_lsu__T_19 = exe_stage_lsu__T_18 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_w; // @[riscv_isa.scala 148:58]
  wire  exe_stage_lsu__T_20 = exe_stage_lsu__T_19 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_w; // @[riscv_isa.scala 148:69]
  wire  exe_stage_lsu__T_21 = exe_stage_lsu__T_20 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_w; // @[riscv_isa.scala 148:80]
  wire  exe_stage_lsu__T_22 = exe_stage_lsu__T_21 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_w; // @[riscv_isa.scala 148:92]
  wire  exe_stage_lsu__T_23 = exe_stage_lsu__T_22 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_d; // @[riscv_isa.scala 148:104]
  wire  exe_stage_lsu__T_24 = exe_stage_lsu__T_23 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_d; // @[riscv_isa.scala 148:116]
  wire  exe_stage_lsu__T_25 = exe_stage_lsu__T_24 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_d; // @[riscv_isa.scala 148:127]
  wire  exe_stage_lsu__T_26 = exe_stage_lsu__T_25 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_d; // @[riscv_isa.scala 148:138]
  wire  exe_stage_lsu__T_27 = exe_stage_lsu__T_26 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_d; // @[riscv_isa.scala 148:149]
  wire  exe_stage_lsu__T_28 = exe_stage_lsu__T_27 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_d; // @[riscv_isa.scala 148:159]
  wire  exe_stage_lsu__T_29 = exe_stage_lsu__T_28 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_d; // @[riscv_isa.scala 148:170]
  wire  exe_stage_lsu__T_30 = exe_stage_lsu__T_29 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_d; // @[riscv_isa.scala 148:181]
  wire  exe_stage_lsu__T_31 = exe_stage_lsu__T_30 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_d; // @[riscv_isa.scala 148:193]
  wire  exe_stage_lsu__T_32 = exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_d | exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_w; // @[riscv_isa.scala 140:20]
  wire  exe_stage_lsu__T_33 = exe_stage_lsu__T_31 | exe_stage_lsu__T_32; // @[riscv_isa.scala 148:205]
  wire  exe_stage_lsu__T_10 = exe_stage_lsu_io_lsu_iss_exe_bits_fun_sb | exe_stage_lsu_io_lsu_iss_exe_bits_fun_sh; // @[riscv_isa.scala 144:19]
  wire  exe_stage_lsu__T_11 = exe_stage_lsu__T_10 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_sw; // @[riscv_isa.scala 144:24]
  wire  exe_stage_lsu__T_12 = exe_stage_lsu__T_11 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_sd; // @[riscv_isa.scala 144:29]
  wire  exe_stage_lsu__T_13 = exe_stage_lsu__T_12 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsw; // @[riscv_isa.scala 144:34]
  wire  exe_stage_lsu__T_14 = exe_stage_lsu__T_13 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsd; // @[riscv_isa.scala 144:40]
  wire  exe_stage_lsu__opStIO_ready_T = exe_stage_lsu_su_wb_fifo_io_enq_ready & exe_stage_lsu_stQueue_io_enq_ready; // @[Lsu.scala 462:43]
  wire  exe_stage_lsu__T = exe_stage_lsu_io_lsu_iss_exe_bits_fun_lb | exe_stage_lsu_io_lsu_iss_exe_bits_fun_lh; // @[riscv_isa.scala 143:19]
  wire  exe_stage_lsu__T_1 = exe_stage_lsu__T | exe_stage_lsu_io_lsu_iss_exe_bits_fun_lw; // @[riscv_isa.scala 143:24]
  wire  exe_stage_lsu__T_2 = exe_stage_lsu__T_1 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_ld; // @[riscv_isa.scala 143:29]
  wire  exe_stage_lsu__T_3 = exe_stage_lsu__T_2 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_lbu; // @[riscv_isa.scala 143:34]
  wire  exe_stage_lsu__T_4 = exe_stage_lsu__T_3 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_lhu; // @[riscv_isa.scala 143:40]
  wire  exe_stage_lsu__T_5 = exe_stage_lsu__T_4 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_lwu; // @[riscv_isa.scala 143:46]
  wire  exe_stage_lsu__T_6 = exe_stage_lsu__T_5 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_flw; // @[riscv_isa.scala 143:52]
  wire  exe_stage_lsu__T_7 = exe_stage_lsu__T_6 | exe_stage_lsu_io_lsu_iss_exe_bits_fun_fld; // @[riscv_isa.scala 143:59]
  wire  exe_stage_lsu__T_8 = exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_d | exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_w; // @[riscv_isa.scala 141:20]
  wire  exe_stage_lsu__T_9 = exe_stage_lsu__T_7 | exe_stage_lsu__T_8; // @[riscv_isa.scala 143:65]
  wire  exe_stage_lsu__opLdIO_ready_T = exe_stage_lsu_ls_arb_io_in_0_ready & exe_stage_lsu_stQueue_io_overlapResp_valid; // @[Lsu.scala 213:41]
  wire  exe_stage_lsu__GEN_45 = exe_stage_lsu__T_9 & exe_stage_lsu__opLdIO_ready_T; // @[Lsu.scala 160:21 162:38 165:23]
  wire  exe_stage_lsu__GEN_91 = exe_stage_lsu__T_14 ? exe_stage_lsu__opStIO_ready_T : exe_stage_lsu__GEN_45; // @[Lsu.scala 171:38 174:23]
  wire  exe_stage_lsu__GEN_137 = exe_stage_lsu__T_33 ? exe_stage_lsu_stQueue_io_enq_ready : exe_stage_lsu__GEN_91; // @[Lsu.scala 180:39 183:23]
  wire  exe_stage_lsu__io_mmu_lsu_ready_T_2 = exe_stage_lsu__GEN_137 & exe_stage_lsu__addrTransIO_valid_T_1; // @[Lsu.scala 139:41]
  wire  exe_stage_lsu__io_mmu_lsu_ready_T_46 = exe_stage_lsu__io_mmu_lsu_ready_T_2 &
    exe_stage_lsu__addrTransIO_valid_T_45; // @[Lsu.scala 139:69]
  wire  exe_stage_lsu__io_lsu_mmu_valid_T_2 = ~exe_stage_lsu__addrTransIO_valid_T_48; // @[Lsu.scala 141:46]
  wire  exe_stage_lsu__io_lsu_mmu_bits_is_R_T_11 = exe_stage_lsu__T_9 | exe_stage_lsu__T_8; // @[riscv_isa.scala 161:20]
  wire  exe_stage_lsu__io_lsu_mmu_bits_is_W_T_6 = exe_stage_lsu__T_14 | exe_stage_lsu__T_32; // @[riscv_isa.scala 162:20]
  wire  exe_stage_lsu__io_lsu_iss_exe_ready_T_3 = exe_stage_lsu__io_lsu_mmu_valid_T_2 & exe_stage_lsu_io_lsu_mmu_ready; // @[Lsu.scala 147:41]
  wire  exe_stage_lsu__io_lsu_iss_exe_ready_T_7 = exe_stage_lsu__addrTransIO_valid_T_48 &
    exe_stage_lsu_fe_wb_fifo__do_enq_T; // @[Lsu.scala 148:41]
  wire  exe_stage_lsu__GEN_0 = exe_stage_lsu__T_9 & exe_stage_lsu__addrTransIO_valid_T_51; // @[Lsu.scala 162:38 163:23 167:18]
  wire [63:0] exe_stage_lsu__GEN_42 = exe_stage_lsu__T_9 ? exe_stage_lsu_io_mmu_lsu_bits_paddr : 64'h0; // @[Lsu.scala 162:38 164:23 168:18]
  wire  exe_stage_lsu__GEN_46 = exe_stage_lsu__T_14 & exe_stage_lsu__addrTransIO_valid_T_51; // @[Lsu.scala 171:38 172:23 176:18]
  wire  exe_stage_lsu__GEN_47 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lb; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_48 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lh; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_49 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lw; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_50 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_ld; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_51 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lbu; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_52 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lhu; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_53 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lwu; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_54 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sb; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_55 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sh; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_56 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sw; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_57 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sd; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_61 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_62 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_63 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_64 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_65 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_66 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_67 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_68 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_69 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_70 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_71 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_72 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_73 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_74 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_75 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_76 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_77 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_78 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_79 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_80 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_81 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_82 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_83 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_flw; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_84 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsw; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_85 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fld; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_86 = exe_stage_lsu__T_14 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsd; // @[Lsu.scala 171:38 173:23 177:18]
  wire [5:0] exe_stage_lsu__GEN_87 = exe_stage_lsu__T_14 ? exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0 : 6'h0; // @[Lsu.scala 171:38 173:23 177:18]
  wire [63:0] exe_stage_lsu__GEN_88 = exe_stage_lsu__T_14 ? exe_stage_lsu_io_mmu_lsu_bits_paddr : 64'h0; // @[Lsu.scala 171:38 173:23 177:18]
  wire [63:0] exe_stage_lsu__GEN_89 = exe_stage_lsu__T_14 ? exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op2 : 64'h0; // @[Lsu.scala 171:38 173:23 177:18]
  wire  exe_stage_lsu__GEN_92 = exe_stage_lsu__T_33 & exe_stage_lsu__addrTransIO_valid_T_51; // @[Lsu.scala 180:39 181:23 185:18]
  wire  exe_stage_lsu__GEN_93 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lb; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_94 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lh; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_95 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lw; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_96 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_ld; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_97 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lbu; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_98 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lhu; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_99 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lwu; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_100 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sb; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_101 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sh; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_102 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sw; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_103 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sd; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_107 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_108 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_109 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_110 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_111 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_112 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_113 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_114 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_115 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_116 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_117 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_118 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_119 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_120 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_121 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_122 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_123 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_124 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_125 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_126 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_127 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_128 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_129 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_flw; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_130 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsw; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_131 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fld; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__GEN_132 = exe_stage_lsu__T_33 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsd; // @[Lsu.scala 180:39 182:23 186:18]
  wire [5:0] exe_stage_lsu__GEN_133 = exe_stage_lsu__T_33 ? exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0 : 6'h0; // @[Lsu.scala 180:39 182:23 186:18]
  wire [63:0] exe_stage_lsu__GEN_134 = exe_stage_lsu__T_33 ? exe_stage_lsu_io_mmu_lsu_bits_paddr : 64'h0; // @[Lsu.scala 180:39 182:23 186:18]
  wire [63:0] exe_stage_lsu__GEN_135 = exe_stage_lsu__T_33 ? exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op2 : 64'h0; // @[Lsu.scala 180:39 182:23 186:18]
  wire  exe_stage_lsu__stQueue_io_enq_valid_T = exe_stage_lsu__opStIO_ready_T & exe_stage_lsu__GEN_46; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu__stQueue_io_enq_valid_T_1 = exe_stage_lsu_stQueue_io_enq_ready & exe_stage_lsu__GEN_92; // @[Decoupled.scala 52:35]
  wire [63:0] exe_stage_lsu__stQueue_io_enq_bits_T_5 = exe_stage_lsu__stQueue_io_enq_valid_T ? exe_stage_lsu__GEN_89 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu__stQueue_io_enq_bits_T_6 = exe_stage_lsu__stQueue_io_enq_valid_T_1 ? exe_stage_lsu__GEN_135
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu__stQueue_io_enq_bits_T_8 = exe_stage_lsu__stQueue_io_enq_valid_T ? exe_stage_lsu__GEN_88 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_lsu__stQueue_io_enq_bits_T_9 = exe_stage_lsu__stQueue_io_enq_valid_T_1 ? exe_stage_lsu__GEN_134
     : 64'h0; // @[Mux.scala 27:73]
  wire [5:0] exe_stage_lsu__stQueue_io_enq_bits_T_11 = exe_stage_lsu__stQueue_io_enq_valid_T ? exe_stage_lsu__GEN_87 : 6'h0
    ; // @[Mux.scala 27:73]
  wire [5:0] exe_stage_lsu__stQueue_io_enq_bits_T_12 = exe_stage_lsu__stQueue_io_enq_valid_T_1 ? exe_stage_lsu__GEN_133
     : 6'h0; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_14 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_86; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_15 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_132; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_17 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_85; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_18 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_131; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_20 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_84; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_21 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_130; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_23 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_83; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_24 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_129; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_26 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_82; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_27 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_128; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_29 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_81; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_30 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_127; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_32 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_80; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_33 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_126; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_35 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_79; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_36 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_125; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_38 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_78; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_39 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_124; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_41 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_77; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_42 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_123; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_44 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_76; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_45 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_122; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_47 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_75; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_48 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_121; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_50 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_74; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_51 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_120; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_53 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_73; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_54 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_119; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_56 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_72; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_57 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_118; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_59 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_71; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_60 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_117; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_62 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_70; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_63 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_116; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_65 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_69; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_66 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_115; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_68 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_68; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_69 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_114; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_71 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_67; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_72 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_113; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_74 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_66; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_75 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_112; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_77 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_65; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_78 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_111; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_80 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_64; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_81 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_110; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_83 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_63; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_84 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_109; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_86 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_62; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_87 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_108; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_89 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_61; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_90 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_107; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_101 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_57; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_102 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_103; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_104 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_56; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_105 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_102; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_107 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_55; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_108 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_101; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_110 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_54; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_111 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_100; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_113 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_53; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_114 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_99; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_116 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_52; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_117 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_98; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_119 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_51; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_120 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_97; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_122 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_50; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_123 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_96; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_125 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_49; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_126 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_95; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_128 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_48; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_129 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_94; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_131 = exe_stage_lsu__stQueue_io_enq_valid_T & exe_stage_lsu__GEN_47; // @[Mux.scala 27:73]
  wire  exe_stage_lsu__stQueue_io_enq_bits_T_132 = exe_stage_lsu__stQueue_io_enq_valid_T_1 & exe_stage_lsu__GEN_93; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu_psel = exe_stage_lsu_ls_arb_io_out_bits_param_dat_op1[31:28]; // @[Lsu.scala 222:46]
  wire  exe_stage_lsu__sel_T = exe_stage_lsu_psel[3]; // @[Lsu.scala 223:22]
  wire  exe_stage_lsu__sel_T_1 = exe_stage_lsu_psel[2]; // @[Lsu.scala 223:41]
  wire [1:0] exe_stage_lsu__sel_T_2 = exe_stage_lsu__sel_T_1 ? 2'h1 : 2'h2; // @[Lsu.scala 223:35]
  wire [1:0] exe_stage_lsu_sel = exe_stage_lsu__sel_T ? 2'h0 : exe_stage_lsu__sel_T_2; // @[Lsu.scala 223:16]
  wire  exe_stage_lsu__T_34 = exe_stage_lsu_sel == 2'h2; // @[Lsu.scala 228:13]
  wire  exe_stage_lsu__GEN_183 = exe_stage_lsu__T_34 & exe_stage_lsu_periph_io_enq_ready; // @[Lsu.scala 226:23 228:23 231:26]
  wire  exe_stage_lsu__T_35 = exe_stage_lsu_sel == 2'h1; // @[Lsu.scala 237:13]
  wire  exe_stage_lsu__GEN_229 = exe_stage_lsu__T_35 ? exe_stage_lsu_system_io_enq_ready : exe_stage_lsu__GEN_183; // @[Lsu.scala 237:23 240:26]
  wire  exe_stage_lsu__T_36 = exe_stage_lsu_sel == 2'h0; // @[Lsu.scala 246:13]
  wire  exe_stage_lsu__GEN_231 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lb; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_232 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lh; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_233 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lw; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_234 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_ld; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_235 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lbu; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_236 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lhu; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_237 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lwu; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_238 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sb; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_239 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sh; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_240 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sw; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_241 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sd; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_245 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lr_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_246 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sc_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_247 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_248 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_249 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_250 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_251 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_252 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_253 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_254 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_255 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_w; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_256 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lr_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_257 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sc_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_258 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_259 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_260 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_261 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_262 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_263 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_264 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_265 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_266 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_d; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_267 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_flw; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_268 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_fsw; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_269 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_fld; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__GEN_270 = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_fsd; // @[Lsu.scala 246:23 248:26 252:26]
  wire [63:0] exe_stage_lsu__GEN_272 = exe_stage_lsu__T_36 ? exe_stage_lsu_ls_arb_io_out_bits_param_dat_op1 : 64'h0; // @[Lsu.scala 246:23 248:26 252:26]
  wire [63:0] exe_stage_lsu__GEN_273 = exe_stage_lsu__T_36 ? exe_stage_lsu_ls_arb_io_out_bits_param_dat_op2 : 64'h0; // @[Lsu.scala 246:23 248:26 252:26]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T = exe_stage_lsu__GEN_231 | exe_stage_lsu__GEN_232; // @[riscv_isa.scala 143:19]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_1 = exe_stage_lsu__CacheMuxBits_res_wdata_T | exe_stage_lsu__GEN_233; // @[riscv_isa.scala 143:24]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_2 = exe_stage_lsu__CacheMuxBits_res_wdata_T_1 | exe_stage_lsu__GEN_234; // @[riscv_isa.scala 143:29]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_3 = exe_stage_lsu__CacheMuxBits_res_wdata_T_2 | exe_stage_lsu__GEN_235; // @[riscv_isa.scala 143:34]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_4 = exe_stage_lsu__CacheMuxBits_res_wdata_T_3 | exe_stage_lsu__GEN_236; // @[riscv_isa.scala 143:40]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_5 = exe_stage_lsu__CacheMuxBits_res_wdata_T_4 | exe_stage_lsu__GEN_237; // @[riscv_isa.scala 143:46]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_6 = exe_stage_lsu__CacheMuxBits_res_wdata_T_5 | exe_stage_lsu__GEN_267; // @[riscv_isa.scala 143:52]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_7 = exe_stage_lsu__CacheMuxBits_res_wdata_T_6 | exe_stage_lsu__GEN_269; // @[riscv_isa.scala 143:59]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_8 = exe_stage_lsu__GEN_256 | exe_stage_lsu__GEN_245; // @[riscv_isa.scala 141:20]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_T_9 = exe_stage_lsu__CacheMuxBits_res_wdata_T_7 |
    exe_stage_lsu__CacheMuxBits_res_wdata_T_8; // @[riscv_isa.scala 143:65]
  wire [3:0] exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T = exe_stage_lsu_stQueue_io_overlapReq_bits_paddr[3:0]; // @[Util.scala 149:35]
  wire  exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_1 = exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T[3]; // @[Util.scala 149:50]
  wire [3:0] exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_2 = {
    exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_1, 3'h0}; // @[Util.scala 149:62]
  wire [6:0] exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_3 = {
    exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_2, 3'h0}; // @[Util.scala 149:74]
  wire [190:0] _GEN_848 = {{127'd0}, exe_stage_lsu_stQueue_io_overlapResp_bits_wdata}; // @[Util.scala 149:26]
  wire [190:0] exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_4 = _GEN_848 <<
    exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_3; // @[Util.scala 149:26]
  wire [3:0] exe_stage_lsu__CacheMuxBits_res_wdata_res_T = exe_stage_lsu__GEN_272[3:0]; // @[riscv_isa.scala 907:38]
  wire [6:0] exe_stage_lsu__CacheMuxBits_res_wdata_res_T_1 = {exe_stage_lsu__CacheMuxBits_res_wdata_res_T, 3'h0}; // @[riscv_isa.scala 907:61]
  wire [190:0] _GEN_849 = {{127'd0}, exe_stage_lsu__GEN_273}; // @[riscv_isa.scala 907:28]
  wire [190:0] exe_stage_lsu__CacheMuxBits_res_wdata_res_T_2 = _GEN_849 << exe_stage_lsu__CacheMuxBits_res_wdata_res_T_1
    ; // @[riscv_isa.scala 907:28]
  wire [127:0] exe_stage_lsu_CacheMuxBits_res_wdata_align_data = exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_4[
    127:0]; // @[Util.scala 145:26 149:18]
  wire [127:0] exe_stage_lsu_CacheMuxBits_res_wdata_res = exe_stage_lsu__CacheMuxBits_res_wdata_res_T_2[127:0]; // @[riscv_isa.scala 906:21 907:11]
  wire [22:0] _GEN_850 = {{15'd0}, exe_stage_lsu_stQueue_io_overlapResp_bits_wstrb}; // @[Util.scala 169:26]
  wire [22:0] exe_stage_lsu__CacheMuxBits_res_wstrb_align_strb_T_3 = _GEN_850 <<
    exe_stage_lsu__CacheMuxBits_res_wdata_align_data_T_2; // @[Util.scala 169:26]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T = exe_stage_lsu__GEN_231 | exe_stage_lsu__GEN_235; // @[riscv_isa.scala 153:20]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_1 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T |
    exe_stage_lsu__GEN_238; // @[riscv_isa.scala 153:26]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_2 = exe_stage_lsu__GEN_232 | exe_stage_lsu__GEN_236; // @[riscv_isa.scala 154:20]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_3 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_2 |
    exe_stage_lsu__GEN_239; // @[riscv_isa.scala 154:26]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_4 = exe_stage_lsu__GEN_233 | exe_stage_lsu__GEN_237; // @[riscv_isa.scala 155:20]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_5 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_4 |
    exe_stage_lsu__GEN_240; // @[riscv_isa.scala 155:26]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_6 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_5 |
    exe_stage_lsu__GEN_247; // @[riscv_isa.scala 155:31]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_7 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_6 |
    exe_stage_lsu__GEN_248; // @[riscv_isa.scala 155:43]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_8 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_7 |
    exe_stage_lsu__GEN_249; // @[riscv_isa.scala 155:54]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_9 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_8 |
    exe_stage_lsu__GEN_250; // @[riscv_isa.scala 155:65]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_10 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_9 |
    exe_stage_lsu__GEN_251; // @[riscv_isa.scala 155:76]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_11 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_10 |
    exe_stage_lsu__GEN_252; // @[riscv_isa.scala 155:86]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_12 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_11 |
    exe_stage_lsu__GEN_253; // @[riscv_isa.scala 155:97]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_13 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_12 |
    exe_stage_lsu__GEN_254; // @[riscv_isa.scala 155:108]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_14 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_13 |
    exe_stage_lsu__GEN_255; // @[riscv_isa.scala 155:120]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_15 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_14 |
    exe_stage_lsu__GEN_267; // @[riscv_isa.scala 155:132]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_16 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_15 |
    exe_stage_lsu__GEN_268; // @[riscv_isa.scala 155:138]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_17 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_16 |
    exe_stage_lsu__GEN_245; // @[riscv_isa.scala 155:144]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_18 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_17 |
    exe_stage_lsu__GEN_246; // @[riscv_isa.scala 155:151]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_19 = exe_stage_lsu__GEN_234 | exe_stage_lsu__GEN_256; // @[riscv_isa.scala 156:20]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_20 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_19 |
    exe_stage_lsu__GEN_269; // @[riscv_isa.scala 156:27]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_21 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_20 |
    exe_stage_lsu__GEN_241; // @[riscv_isa.scala 156:33]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_22 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_21 |
    exe_stage_lsu__GEN_257; // @[riscv_isa.scala 156:38]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_23 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_22 |
    exe_stage_lsu__GEN_270; // @[riscv_isa.scala 156:45]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_24 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_23 |
    exe_stage_lsu__GEN_258; // @[riscv_isa.scala 156:51]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_25 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_24 |
    exe_stage_lsu__GEN_259; // @[riscv_isa.scala 156:63]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_26 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_25 |
    exe_stage_lsu__GEN_260; // @[riscv_isa.scala 156:74]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_27 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_26 |
    exe_stage_lsu__GEN_261; // @[riscv_isa.scala 156:85]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_28 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_27 |
    exe_stage_lsu__GEN_262; // @[riscv_isa.scala 156:96]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_29 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_28 |
    exe_stage_lsu__GEN_263; // @[riscv_isa.scala 156:106]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_30 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_29 |
    exe_stage_lsu__GEN_264; // @[riscv_isa.scala 156:117]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_31 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_30 |
    exe_stage_lsu__GEN_265; // @[riscv_isa.scala 156:128]
  wire  exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_32 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_31 |
    exe_stage_lsu__GEN_266; // @[riscv_isa.scala 156:140]
  wire [1:0] exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_34 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_3 ? 2'h3
     : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_35 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_18 ? 4'hf
     : 4'h0; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_36 = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_32 ? 8'hff
     : 8'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_449 = {{1'd0}, exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_1}; // @[Mux.scala 27:73]
  wire [1:0] exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_37 = _GEN_449 |
    exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_34; // @[Mux.scala 27:73]
  wire [3:0] _GEN_450 = {{2'd0}, exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_37}; // @[Mux.scala 27:73]
  wire [3:0] exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_38 = _GEN_450 |
    exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_35; // @[Mux.scala 27:73]
  wire [7:0] _GEN_451 = {{4'd0}, exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_38}; // @[Mux.scala 27:73]
  wire [7:0] exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_39 = _GEN_451 |
    exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_36; // @[Mux.scala 27:73]
  wire [22:0] _GEN_851 = {{15'd0}, exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_39}; // @[riscv_isa.scala 916:10]
  wire [22:0] exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_41 = _GEN_851 << exe_stage_lsu__CacheMuxBits_res_wdata_res_T
    ; // @[riscv_isa.scala 916:10]
  wire [15:0] exe_stage_lsu_CacheMuxBits_res_wstrb_align_strb = exe_stage_lsu__CacheMuxBits_res_wstrb_align_strb_T_3[15:
    0]; // @[Util.scala 165:26 169:18]
  wire [15:0] exe_stage_lsu_CacheMuxBits_res_wstrb_wstrb = exe_stage_lsu__CacheMuxBits_res_wstrb_wstrb_T_41[15:0]; // @[riscv_isa.scala 912:21 913:11]
  wire  exe_stage_lsu__T_38 = ~exe_stage_lsu_io_missUnit_dcache_grant_bits_source; // @[Lsu.scala 307:54]
  wire  exe_stage_lsu__T_40 = ~exe_stage_lsu_io_writeBackUnit_dcache_grant_bits_source; // @[Lsu.scala 317:59]
  reg  exe_stage_lsu_is_chnc_busy_0; // @[Lsu.scala 325:33]
  wire  exe_stage_lsu__is_release_done_T = exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_ready &
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_valid; // @[Decoupled.scala 52:35]
  wire [10:0] exe_stage_lsu__is_release_done_beats1_decode_T_1 = 11'hf <<
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_size; // @[package.scala 234:77]
  wire [3:0] exe_stage_lsu__is_release_done_beats1_decode_T_2 = exe_stage_lsu__is_release_done_beats1_decode_T_1[3:0]; // @[package.scala 234:82]
  wire [3:0] exe_stage_lsu__is_release_done_beats1_decode_T_3 = ~exe_stage_lsu__is_release_done_beats1_decode_T_2; // @[package.scala 234:46]
  wire  exe_stage_lsu_is_release_done_beats1_decode = exe_stage_lsu__is_release_done_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  exe_stage_lsu_is_release_done_beats1_opdata = exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_opcode[
    0]; // @[Edges.scala 101:36]
  wire  exe_stage_lsu_is_release_done_beats1 = exe_stage_lsu_is_release_done_beats1_opdata &
    exe_stage_lsu_is_release_done_beats1_decode; // @[Edges.scala 220:14]
  reg  exe_stage_lsu_is_release_done_counter; // @[Edges.scala 228:27]
  wire  exe_stage_lsu_is_release_done_counter1 = exe_stage_lsu_is_release_done_counter - 1'h1; // @[Edges.scala 229:28]
  wire  exe_stage_lsu_is_release_done_first = ~exe_stage_lsu_is_release_done_counter; // @[Edges.scala 230:25]
  wire  exe_stage_lsu__is_release_done_last_T_1 = ~exe_stage_lsu_is_release_done_beats1; // @[Edges.scala 231:47]
  wire  exe_stage_lsu_is_release_done_last = exe_stage_lsu_is_release_done_counter |
    exe_stage_lsu__is_release_done_last_T_1; // @[Edges.scala 231:37]
  wire  exe_stage_lsu_is_release_done_0 = exe_stage_lsu_is_release_done_last & exe_stage_lsu__is_release_done_T; // @[Edges.scala 232:22]
  wire  exe_stage_lsu__T_42 = ~exe_stage_lsu_is_chnc_busy_0; // @[Lsu.scala 334:48]
  wire [2:0] exe_stage_lsu__GEN_358 = exe_stage_lsu_is_chnc_busy_0 ?
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_opcode : 3'h0; // @[Lsu.scala 287:46 339:{47,85}]
  wire [2:0] exe_stage_lsu__GEN_359 = exe_stage_lsu_is_chnc_busy_0 ?
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_param : 3'h0; // @[Lsu.scala 287:46 339:{47,85}]
  wire [2:0] exe_stage_lsu__GEN_360 = exe_stage_lsu_is_chnc_busy_0 ?
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_size : 3'h0; // @[Lsu.scala 287:46 339:{47,85}]
  wire  exe_stage_lsu__GEN_361 = exe_stage_lsu_is_chnc_busy_0 &
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_source; // @[Lsu.scala 287:46 339:{47,85}]
  wire [31:0] exe_stage_lsu__GEN_362 = exe_stage_lsu_is_chnc_busy_0 ?
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_address : 32'h0; // @[Lsu.scala 287:46 339:{47,85}]
  wire [63:0] exe_stage_lsu__GEN_363 = exe_stage_lsu_is_chnc_busy_0 ?
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_data : 64'h0; // @[Lsu.scala 287:46 339:{47,85}]
  wire  exe_stage_lsu__GEN_364 = exe_stage_lsu_is_chnc_busy_0 &
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_corrupt; // @[Lsu.scala 287:46 339:{47,85}]
  wire  exe_stage_lsu__GEN_365 = exe_stage_lsu_is_chnc_busy_0 &
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_valid; // @[Lsu.scala 286:47 339:{47,85}]
  wire  exe_stage_lsu__GEN_366 = exe_stage_lsu_is_chnc_busy_0 ? exe_stage_lsu_io_writeBackUnit_dcache_release_ready :
    exe_stage_lsu_releaseArb_io_in_0_ready; // @[Lsu.scala 332:29 339:{47,85}]
  wire  exe_stage_lsu__T_47 = ~exe_stage_lsu_reset; // @[Lsu.scala 342:13]
  wire  exe_stage_lsu__is_empty_T_2 = exe_stage_lsu_stQueue_io_is_empty & exe_stage_lsu_cache_0_io_is_empty; // @[Lsu.scala 536:25]
  wire  exe_stage_lsu__is_empty_T_3 = exe_stage_lsu__is_empty_T_2 & exe_stage_lsu_system_io_is_empty; // @[Lsu.scala 537:79]
  wire  exe_stage_lsu__is_empty_T_4 = exe_stage_lsu__is_empty_T_3 & exe_stage_lsu_periph_io_is_empty; // @[Lsu.scala 538:24]
  wire  exe_stage_lsu__is_empty_T_5 = ~exe_stage_lsu_su_wb_fifo_io_deq_valid; // @[Lsu.scala 540:5]
  wire  exe_stage_lsu__is_empty_T_6 = exe_stage_lsu__is_empty_T_4 & exe_stage_lsu__is_empty_T_5; // @[Lsu.scala 539:24]
  wire  exe_stage_lsu__is_empty_T_7 = ~exe_stage_lsu_lu_wb_fifo_io_deq_valid; // @[Lsu.scala 541:5]
  wire  exe_stage_lsu__is_empty_T_8 = exe_stage_lsu__is_empty_T_6 & exe_stage_lsu__is_empty_T_7; // @[Lsu.scala 540:30]
  wire  exe_stage_lsu__GEN_377 = exe_stage_lsu__is_empty_T_8 ? 1'h0 : exe_stage_lsu_trans_kill; // @[Lsu.scala 412:{25,38} 73:27]
  wire  exe_stage_lsu__GEN_378 = exe_stage_lsu_io_flush | exe_stage_lsu__GEN_377; // @[Lsu.scala 411:{20,33}]
  wire  exe_stage_lsu__cache_0_io_deq_ready_T = ~exe_stage_lsu_cache_0_io_deq_bits_is_load_amo; // @[Lsu.scala 421:57]
  wire  exe_stage_lsu__T_50 = exe_stage_lsu_lu_wb_arb_io_in_0_ready & exe_stage_lsu_lu_wb_arb_io_in_0_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu__T_51 = exe_stage_lsu_cache_0__T_1 == exe_stage_lsu__T_50; // @[Lsu.scala 422:76]
  wire  exe_stage_lsu__T_54 = ~exe_stage_lsu__T_51; // @[Lsu.scala 422:54]
  wire  exe_stage_lsu__system_io_deq_ready_T = ~exe_stage_lsu_system_io_deq_bits_is_load_amo; // @[Lsu.scala 427:54]
  wire  exe_stage_lsu__T_55 = exe_stage_lsu_system_io_deq_ready & exe_stage_lsu_system_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu__T_56 = exe_stage_lsu_lu_wb_arb_io_in_1_ready & exe_stage_lsu_lu_wb_arb_io_in_1_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu__T_57 = exe_stage_lsu__T_55 == exe_stage_lsu__T_56; // @[Lsu.scala 428:70]
  wire  exe_stage_lsu__T_60 = ~exe_stage_lsu__T_57; // @[Lsu.scala 428:50]
  wire  exe_stage_lsu__periph_io_deq_ready_T = ~exe_stage_lsu_periph_io_deq_bits_is_load_amo; // @[Lsu.scala 432:56]
  wire  exe_stage_lsu__T_61 = exe_stage_lsu_periph_io_deq_ready & exe_stage_lsu_periph_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu__T_62 = exe_stage_lsu_lu_wb_arb_io_in_2_ready & exe_stage_lsu_lu_wb_arb_io_in_2_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_lsu__T_63 = exe_stage_lsu__T_61 == exe_stage_lsu__T_62; // @[Lsu.scala 433:70]
  wire  exe_stage_lsu__T_66 = ~exe_stage_lsu__T_63; // @[Lsu.scala 433:50]
  wire  exe_stage_lsu__lu_wb_fifo_io_enq_valid_T = exe_stage_lsu_lu_wb_arb_io_out_bits_is_flw |
    exe_stage_lsu_lu_wb_arb_io_out_bits_is_fld; // @[Dcache.scala 88:23]
  wire  exe_stage_lsu__lu_wb_fifo_io_enq_valid_T_1 = ~exe_stage_lsu__lu_wb_fifo_io_enq_valid_T; // @[Dcache.scala 87:16]
  wire  exe_stage_lsu__lu_wb_fifo_io_enq_valid_T_2 = exe_stage_lsu_lu_wb_arb_io_out_valid &
    exe_stage_lsu__lu_wb_fifo_io_enq_valid_T_1; // @[Lsu.scala 437:53]
  wire  exe_stage_lsu__lu_wb_fifo_io_enq_valid_T_3 = ~exe_stage_lsu_trans_kill; // @[Lsu.scala 437:87]
  wire  exe_stage_lsu__flu_wb_fifo_io_enq_valid_T_1 = exe_stage_lsu_lu_wb_arb_io_out_valid &
    exe_stage_lsu__lu_wb_fifo_io_enq_valid_T; // @[Lsu.scala 443:54]
  wire  exe_stage_lsu__lu_wb_arb_io_out_ready_T = exe_stage_lsu_lu_wb_fifo_io_enq_ready &
    exe_stage_lsu_flu_wb_fifo_io_enq_ready; // @[Lsu.scala 454:54]
  wire  exe_stage_lsu__fe_wb_fifo_io_enq_valid_T_2 = exe_stage_lsu__is_empty_T_8 & exe_stage_lsu__addrTransIO_valid_T_48
    ; // @[Lsu.scala 467:39]
  reg  exe_stage_lsu_isAccessFaultReg; // @[Lsu.scala 485:33]
  reg  exe_stage_lsu_isPagingFault; // @[Lsu.scala 486:33]
  reg  exe_stage_lsu_isMisAlign; // @[Lsu.scala 487:27]
  reg [63:0] exe_stage_lsu_trapAddrReg; // @[Lsu.scala 488:24]
  wire  exe_stage_lsu__T_67 = exe_stage_lsu_io_mmu_lsu_valid & exe_stage_lsu__is_empty_T_8; // @[Lsu.scala 494:33]
  wire  exe_stage_csr_clock;
  wire  exe_stage_csr_reset;
  wire  exe_stage_csr_io_csr_iss_exe_ready;
  wire  exe_stage_csr_io_csr_iss_exe_valid;
  wire  exe_stage_csr_io_csr_iss_exe_bits_fun_rw;
  wire  exe_stage_csr_io_csr_iss_exe_bits_fun_rs;
  wire  exe_stage_csr_io_csr_iss_exe_bits_fun_rc;
  wire [5:0] exe_stage_csr_io_csr_iss_exe_bits_param_rd0;
  wire [63:0] exe_stage_csr_io_csr_iss_exe_bits_param_dat_op1;
  wire [63:0] exe_stage_csr_io_csr_iss_exe_bits_param_dat_op2;
  wire  exe_stage_csr_io_csr_exe_iwb_ready;
  wire  exe_stage_csr_io_csr_exe_iwb_valid;
  wire [5:0] exe_stage_csr_io_csr_exe_iwb_bits_rd0;
  wire [63:0] exe_stage_csr_io_csr_exe_iwb_bits_res;
  wire  exe_stage_csr_io_csr_addr_valid;
  wire [11:0] exe_stage_csr_io_csr_addr_bits;
  wire  exe_stage_csr_io_csr_data_valid;
  wire [63:0] exe_stage_csr_io_csr_data_bits;
  wire  exe_stage_csr_io_csr_cmm_op_ready;
  wire  exe_stage_csr_io_csr_cmm_op_valid;
  wire [11:0] exe_stage_csr_io_csr_cmm_op_bits_addr;
  wire [63:0] exe_stage_csr_io_csr_cmm_op_bits_dat_i;
  wire  exe_stage_csr_io_csr_cmm_op_bits_op_rw;
  wire  exe_stage_csr_io_csr_cmm_op_bits_op_rs;
  wire  exe_stage_csr_io_csr_cmm_op_bits_op_rc;
  wire  exe_stage_csr_io_flush;
  wire  exe_stage_csr_csr_exe_iwb_fifo_clock;
  wire  exe_stage_csr_csr_exe_iwb_fifo_reset;
  wire  exe_stage_csr_csr_exe_iwb_fifo_io_enq_ready;
  wire  exe_stage_csr_csr_exe_iwb_fifo_io_enq_valid;
  wire [5:0] exe_stage_csr_csr_exe_iwb_fifo_io_enq_bits_rd0;
  wire [63:0] exe_stage_csr_csr_exe_iwb_fifo_io_enq_bits_res;
  wire  exe_stage_csr_csr_exe_iwb_fifo_io_deq_ready;
  wire  exe_stage_csr_csr_exe_iwb_fifo_io_deq_valid;
  wire [5:0] exe_stage_csr_csr_exe_iwb_fifo_io_deq_bits_rd0;
  wire [63:0] exe_stage_csr_csr_exe_iwb_fifo_io_deq_bits_res;
  reg [5:0] exe_stage_csr_csr_exe_iwb_fifo_ram_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_clock;
  reg [63:0] exe_stage_csr_csr_exe_iwb_fifo_ram_res [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_csr_csr_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_exe_iwb_fifo_ram_res_clock;
  reg  exe_stage_csr_csr_exe_iwb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_csr_csr_exe_iwb_fifo__empty_T = ~exe_stage_csr_csr_exe_iwb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_csr_csr_exe_iwb_fifo__do_enq_T = exe_stage_csr_csr_exe_iwb_fifo_io_enq_ready &
    exe_stage_csr_csr_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_csr_csr_exe_iwb_fifo__do_deq_T = exe_stage_csr_csr_exe_iwb_fifo_io_deq_ready &
    exe_stage_csr_csr_exe_iwb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_csr_csr_exe_iwb_fifo__T = exe_stage_csr_csr_exe_iwb_fifo__do_enq_T !=
    exe_stage_csr_csr_exe_iwb_fifo__do_deq_T; // @[Decoupled.scala 295:15]
  wire  exe_stage_csr_csr_op_fifo_clock;
  wire  exe_stage_csr_csr_op_fifo_reset;
  wire  exe_stage_csr_csr_op_fifo_io_enq_ready;
  wire  exe_stage_csr_csr_op_fifo_io_enq_valid;
  wire [11:0] exe_stage_csr_csr_op_fifo_io_enq_bits_addr;
  wire [63:0] exe_stage_csr_csr_op_fifo_io_enq_bits_dat_i;
  wire  exe_stage_csr_csr_op_fifo_io_enq_bits_op_rw;
  wire  exe_stage_csr_csr_op_fifo_io_enq_bits_op_rs;
  wire  exe_stage_csr_csr_op_fifo_io_enq_bits_op_rc;
  wire  exe_stage_csr_csr_op_fifo_io_deq_ready;
  wire  exe_stage_csr_csr_op_fifo_io_deq_valid;
  wire [11:0] exe_stage_csr_csr_op_fifo_io_deq_bits_addr;
  wire [63:0] exe_stage_csr_csr_op_fifo_io_deq_bits_dat_i;
  wire  exe_stage_csr_csr_op_fifo_io_deq_bits_op_rw;
  wire  exe_stage_csr_csr_op_fifo_io_deq_bits_op_rs;
  wire  exe_stage_csr_csr_op_fifo_io_deq_bits_op_rc;
  reg [11:0] exe_stage_csr_csr_op_fifo_ram_addr [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_addr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_addr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [11:0] exe_stage_csr_csr_op_fifo_ram_addr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [11:0] exe_stage_csr_csr_op_fifo_ram_addr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_addr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_addr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_addr_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_addr_clock;
  reg [63:0] exe_stage_csr_csr_op_fifo_ram_dat_i [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_dat_i_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_dat_i_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_csr_csr_op_fifo_ram_dat_i_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_dat_i_clock;
  reg  exe_stage_csr_csr_op_fifo_ram_op_rw [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rw_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rw_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rw_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rw_clock;
  reg  exe_stage_csr_csr_op_fifo_ram_op_rs [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rs_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rs_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rs_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rs_clock;
  reg  exe_stage_csr_csr_op_fifo_ram_op_rc [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rc_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rc_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rc_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_csr_csr_op_fifo_ram_op_rc_clock;
  reg  exe_stage_csr_csr_op_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_csr_csr_op_fifo__empty_T = ~exe_stage_csr_csr_op_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_csr_csr_op_fifo__do_enq_T = exe_stage_csr_csr_op_fifo_io_enq_ready &
    exe_stage_csr_csr_op_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_csr_csr_op_fifo__do_deq_T = exe_stage_csr_csr_op_fifo_io_deq_ready &
    exe_stage_csr_csr_op_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_csr_csr_op_fifo__T = exe_stage_csr_csr_op_fifo__do_enq_T != exe_stage_csr_csr_op_fifo__do_deq_T; // @[Decoupled.scala 295:15]
  wire  exe_stage_csr__dontWrite_T = exe_stage_csr_io_csr_iss_exe_bits_param_dat_op1 == 64'h0; // @[Csr.scala 60:24]
  wire  exe_stage_csr__dontWrite_T_1 = exe_stage_csr_io_csr_iss_exe_bits_fun_rs |
    exe_stage_csr_io_csr_iss_exe_bits_fun_rc; // @[Csr.scala 60:40]
  wire  exe_stage_csr_dontWrite = exe_stage_csr__dontWrite_T & exe_stage_csr__dontWrite_T_1; // @[Csr.scala 60:33]
  wire  exe_stage_csr__csr_op_fifo_io_enq_bits_op_rw_T = ~exe_stage_csr_dontWrite; // @[Csr.scala 64:41]
  wire  exe_stage_csr__csr_exe_iwb_fifo_io_enq_valid_T = exe_stage_csr_io_csr_iss_exe_valid &
    exe_stage_csr_csr_op_fifo_io_enq_ready; // @[Csr.scala 74:57]
  wire  exe_stage_mulDiv_0_clock;
  wire  exe_stage_mulDiv_0_reset;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_ready;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_valid;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mul;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulh;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulhsu;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulhu;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_div;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divu;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_rem;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remu;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divw;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divuw;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remw;
  wire  exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remuw;
  wire [5:0] exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_rd0;
  wire [63:0] exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op1;
  wire [63:0] exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op2;
  wire  exe_stage_mulDiv_0_io_mul_exe_iwb_ready;
  wire  exe_stage_mulDiv_0_io_mul_exe_iwb_valid;
  wire [5:0] exe_stage_mulDiv_0_io_mul_exe_iwb_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_io_mul_exe_iwb_bits_res;
  wire  exe_stage_mulDiv_0_io_flush;
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_clock;
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_reset;
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_ready;
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_valid;
  wire [5:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_bits_res;
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_ready;
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_valid;
  wire [5:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_bits_res;
  reg [5:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0 [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [5:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_clock;
  reg [63:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res [0:0]; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_en; // @[Decoupled.scala 275:95]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_clock;
  reg  exe_stage_mulDiv_0_mul_exe_iwb_fifo_maybe_full; // @[Decoupled.scala 278:27]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo__empty_T = ~exe_stage_mulDiv_0_mul_exe_iwb_fifo_maybe_full; // @[Decoupled.scala 280:28]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo__do_enq_T = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_ready &
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo__do_deq_T = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_ready &
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_mulDiv_0_mul_exe_iwb_fifo__T = exe_stage_mulDiv_0_mul_exe_iwb_fifo__do_enq_T !=
    exe_stage_mulDiv_0_mul_exe_iwb_fifo__do_deq_T; // @[Decoupled.scala 295:15]
  wire  exe_stage_mulDiv_0_multiplier_io_enq_ready;
  wire  exe_stage_mulDiv_0_multiplier_io_enq_valid;
  wire  exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mul;
  wire  exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulh;
  wire  exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulhsu;
  wire  exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulhu;
  wire  exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulw;
  wire [5:0] exe_stage_mulDiv_0_multiplier_io_enq_bits_param_rd0;
  wire  exe_stage_mulDiv_0_multiplier_io_deq_ready;
  wire  exe_stage_mulDiv_0_multiplier_io_deq_valid;
  wire  exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mul;
  wire  exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulh;
  wire  exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulhsu;
  wire  exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulhu;
  wire  exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulw;
  wire [5:0] exe_stage_mulDiv_0_multiplier_io_deq_bits_param_rd0;
  wire [64:0] exe_stage_mulDiv_0_multiplier_io_op1;
  wire [64:0] exe_stage_mulDiv_0_multiplier_io_op2;
  wire [129:0] exe_stage_mulDiv_0_multiplier_io_res;
  wire  exe_stage_mulDiv_0_dividor_clock;
  wire  exe_stage_mulDiv_0_dividor_reset;
  wire  exe_stage_mulDiv_0_dividor_io_enq_ready;
  wire  exe_stage_mulDiv_0_dividor_io_enq_valid;
  wire  exe_stage_mulDiv_0_dividor_io_enq_bits_fun_div;
  wire  exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divu;
  wire  exe_stage_mulDiv_0_dividor_io_enq_bits_fun_rem;
  wire  exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remu;
  wire  exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divw;
  wire  exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divuw;
  wire  exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remw;
  wire  exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remuw;
  wire [5:0] exe_stage_mulDiv_0_dividor_io_enq_bits_param_rd0;
  wire [63:0] exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1;
  wire [63:0] exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2;
  wire  exe_stage_mulDiv_0_dividor_io_deq_ready;
  wire  exe_stage_mulDiv_0_dividor_io_deq_valid;
  wire [5:0] exe_stage_mulDiv_0_dividor_io_deq_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_dividor_io_deq_bits_res;
  wire  exe_stage_mulDiv_0_dividor_io_flush;
  wire  exe_stage_mulDiv_0_dividor_algDivider_clock;
  wire  exe_stage_mulDiv_0_dividor_algDivider_reset;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_ready;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_valid;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_div;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divu;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_rem;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remu;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divw;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divuw;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remw;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remuw;
  wire [5:0] exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_rd0;
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_dat_op1;
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_dat_op2;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_ready;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_valid;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_div;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divu;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_rem;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remu;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divw;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divuw;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remw;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remuw;
  wire [5:0] exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_rd0;
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_dat_op1;
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_dat_op2;
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider_io_op1;
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider_io_quo;
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider_io_rem;
  wire  exe_stage_mulDiv_0_dividor_algDivider_io_flush;
  reg  exe_stage_mulDiv_0_dividor_algDivider_isDivBusy; // @[Mul.scala 582:26]
  reg [6:0] exe_stage_mulDiv_0_dividor_algDivider_cnt; // @[Mul.scala 584:20]
  wire  exe_stage_mulDiv_0_dividor_algDivider__T = exe_stage_mulDiv_0_dividor_algDivider_io_enq_ready &
    exe_stage_mulDiv_0_dividor_algDivider_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_mulDiv_0_dividor_algDivider__T_1 = exe_stage_mulDiv_0_dividor_algDivider__T |
    exe_stage_mulDiv_0_dividor_algDivider_io_flush; // @[Mul.scala 585:21]
  wire  exe_stage_mulDiv_0_dividor_algDivider__T_2 = exe_stage_mulDiv_0_dividor_algDivider_cnt != 7'h40; // @[Mul.scala 587:32]
  wire  exe_stage_mulDiv_0_dividor_algDivider__T_3 = exe_stage_mulDiv_0_dividor_algDivider_isDivBusy &
    exe_stage_mulDiv_0_dividor_algDivider__T_2; // @[Mul.scala 587:26]
  wire [6:0] exe_stage_mulDiv_0_dividor_algDivider__cnt_T_1 = exe_stage_mulDiv_0_dividor_algDivider_cnt + 7'h1; // @[Mul.scala 588:16]
  wire  exe_stage_mulDiv_0_dividor_algDivider__T_4 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_ready &
    exe_stage_mulDiv_0_dividor_algDivider_io_deq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_mulDiv_0_dividor_algDivider__T_5 = exe_stage_mulDiv_0_dividor_algDivider__T_4 |
    exe_stage_mulDiv_0_dividor_algDivider_io_flush; // @[Mul.scala 596:21]
  wire  exe_stage_mulDiv_0_dividor_algDivider__GEN_2 = exe_stage_mulDiv_0_dividor_algDivider__T |
    exe_stage_mulDiv_0_dividor_algDivider_isDivBusy; // @[Mul.scala 598:30 599:15 582:26]
  reg [127:0] exe_stage_mulDiv_0_dividor_algDivider_dividend; // @[Mul.scala 604:21]
  reg [63:0] exe_stage_mulDiv_0_dividor_algDivider_divisor; // @[Mul.scala 605:20]
  wire [128:0] exe_stage_mulDiv_0_dividor_algDivider_dividend_shift = {exe_stage_mulDiv_0_dividor_algDivider_dividend
    , 1'h0}; // @[Mul.scala 607:33]
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider__div_cmp_T = exe_stage_mulDiv_0_dividor_algDivider_dividend_shift[
    127:64]; // @[Mul.scala 608:32]
  wire  exe_stage_mulDiv_0_dividor_algDivider_div_cmp = exe_stage_mulDiv_0_dividor_algDivider__div_cmp_T >=
    exe_stage_mulDiv_0_dividor_algDivider_divisor; // @[Mul.scala 608:41]
  wire [63:0] exe_stage_mulDiv_0_dividor_algDivider__divided_T_2 = exe_stage_mulDiv_0_dividor_algDivider__div_cmp_T -
    exe_stage_mulDiv_0_dividor_algDivider_divisor; // @[Mul.scala 612:35]
  wire [62:0] exe_stage_mulDiv_0_dividor_algDivider__divided_T_3 = exe_stage_mulDiv_0_dividor_algDivider_dividend_shift[
    63:1]; // @[Mul.scala 612:61]
  wire [127:0] exe_stage_mulDiv_0_dividor_algDivider__divided_T_4 = {exe_stage_mulDiv_0_dividor_algDivider__divided_T_2,
    exe_stage_mulDiv_0_dividor_algDivider__divided_T_3,1'h1}; // @[Cat.scala 33:92]
  wire [128:0] exe_stage_mulDiv_0_dividor_algDivider_divided = exe_stage_mulDiv_0_dividor_algDivider_div_cmp ? {{1'd0},
    exe_stage_mulDiv_0_dividor_algDivider__divided_T_4} : exe_stage_mulDiv_0_dividor_algDivider_dividend_shift; // @[Mul.scala 610:8]
  wire [128:0] exe_stage_mulDiv_0_dividor_algDivider__GEN_4 = exe_stage_mulDiv_0_dividor_algDivider__T ? {{65'd0},
    exe_stage_mulDiv_0_dividor_algDivider_io_op1} : exe_stage_mulDiv_0_dividor_algDivider_divided; // @[Mul.scala 616:23 617:14 621:14]
  reg  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_div; // @[Reg.scala 19:16]
  reg  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divu; // @[Reg.scala 19:16]
  reg  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_rem; // @[Reg.scala 19:16]
  reg  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remu; // @[Reg.scala 19:16]
  reg  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divw; // @[Reg.scala 19:16]
  reg  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divuw; // @[Reg.scala 19:16]
  reg  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remw; // @[Reg.scala 19:16]
  reg  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remuw; // @[Reg.scala 19:16]
  reg [5:0] exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_rd0; // @[Reg.scala 19:16]
  reg [63:0] exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_dat_op1; // @[Reg.scala 19:16]
  reg [63:0] exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_dat_op2; // @[Reg.scala 19:16]
  wire  exe_stage_mulDiv_0_dividor_algDivider__divFinish_T = exe_stage_mulDiv_0_dividor_algDivider_cnt == 7'h40; // @[Mul.scala 626:36]
  wire  exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_ready;
  wire  exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_valid;
  wire [5:0] exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_bits_res;
  wire  exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_ready;
  wire  exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_valid;
  wire [5:0] exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_bits_res;
  wire  exe_stage_mulDiv_0_dividor_divRtnArb_io_out_ready;
  wire  exe_stage_mulDiv_0_dividor_divRtnArb_io_out_valid;
  wire [5:0] exe_stage_mulDiv_0_dividor_divRtnArb_io_out_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_dividor_divRtnArb_io_out_bits_res;
  wire  exe_stage_mulDiv_0_dividor_divRtnArb_grant_1 = ~exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  exe_stage_mulDiv_0_dividor_divRtnArb__io_out_valid_T = ~exe_stage_mulDiv_0_dividor_divRtnArb_grant_1; // @[Arbiter.scala 147:19]
  wire  exe_stage_mulDiv_0_dividor__T = exe_stage_mulDiv_0_dividor_io_enq_ready &
    exe_stage_mulDiv_0_dividor_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  exe_stage_mulDiv_0_dividor__T_1 = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_div |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divu; // @[riscv_isa.scala 204:19]
  wire  exe_stage_mulDiv_0_dividor__T_2 = exe_stage_mulDiv_0_dividor__T_1 |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divw; // @[riscv_isa.scala 204:26]
  wire  exe_stage_mulDiv_0_dividor__T_3 = exe_stage_mulDiv_0_dividor__T_2 |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divuw; // @[riscv_isa.scala 204:33]
  wire  exe_stage_mulDiv_0_dividor__T_4 = exe_stage_mulDiv_0_dividor__T_3 |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_rem; // @[riscv_isa.scala 204:41]
  wire  exe_stage_mulDiv_0_dividor__T_5 = exe_stage_mulDiv_0_dividor__T_4 |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remu; // @[riscv_isa.scala 204:47]
  wire  exe_stage_mulDiv_0_dividor__T_6 = exe_stage_mulDiv_0_dividor__T_5 |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remw; // @[riscv_isa.scala 204:54]
  wire  exe_stage_mulDiv_0_dividor__T_7 = exe_stage_mulDiv_0_dividor__T_6 |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remuw; // @[riscv_isa.scala 204:61]
  wire  exe_stage_mulDiv_0_dividor__T_9 = ~exe_stage_mulDiv_0_dividor_reset; // @[Mul.scala 430:31]
  wire  exe_stage_mulDiv_0_dividor__T_10 = ~exe_stage_mulDiv_0_dividor__T_7; // @[Mul.scala 430:31]
  wire  exe_stage_mulDiv_0_dividor__is32wPre_T = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divw |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divuw; // @[riscv_isa.scala 199:23]
  wire  exe_stage_mulDiv_0_dividor__is32wPre_T_1 = exe_stage_mulDiv_0_dividor__is32wPre_T |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remw; // @[riscv_isa.scala 199:31]
  wire  exe_stage_mulDiv_0_dividor_is32wPre = exe_stage_mulDiv_0_dividor__is32wPre_T_1 |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remuw; // @[riscv_isa.scala 199:39]
  wire  exe_stage_mulDiv_0_dividor__isUsiPre_T = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divu |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remu; // @[riscv_isa.scala 200:23]
  wire  exe_stage_mulDiv_0_dividor__isUsiPre_T_1 = exe_stage_mulDiv_0_dividor__isUsiPre_T |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divuw; // @[riscv_isa.scala 200:31]
  wire  exe_stage_mulDiv_0_dividor_isUsiPre = exe_stage_mulDiv_0_dividor__isUsiPre_T_1 |
    exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remuw; // @[riscv_isa.scala 200:39]
  wire [31:0] exe_stage_mulDiv_0_dividor__dividend_load_T = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1[31:0]; // @[Mul.scala 449:29]
  wire [63:0] exe_stage_mulDiv_0_dividor__dividend_load_T_1 = exe_stage_mulDiv_0_dividor_is32wPre ? {{32'd0},
    exe_stage_mulDiv_0_dividor__dividend_load_T} : exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1; // @[Mul.scala 449:12]
  wire  exe_stage_mulDiv_0_dividor__dividend_load_T_2 = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1[31]; // @[Mul.scala 452:37]
  wire [31:0] exe_stage_mulDiv_0_dividor__dividend_load_T_4 = ~exe_stage_mulDiv_0_dividor__dividend_load_T; // @[Mul.scala 452:44]
  wire [31:0] exe_stage_mulDiv_0_dividor__dividend_load_T_6 = exe_stage_mulDiv_0_dividor__dividend_load_T_4 + 32'h1; // @[Mul.scala 452:58]
  wire [31:0] exe_stage_mulDiv_0_dividor__dividend_load_T_8 = exe_stage_mulDiv_0_dividor__dividend_load_T_2 ?
    exe_stage_mulDiv_0_dividor__dividend_load_T_6 : exe_stage_mulDiv_0_dividor__dividend_load_T; // @[Mul.scala 452:30]
  wire [63:0] exe_stage_mulDiv_0_dividor__dividend_load_T_9 = {32'h0,exe_stage_mulDiv_0_dividor__dividend_load_T_8}; // @[Cat.scala 33:92]
  wire  exe_stage_mulDiv_0_dividor__dividend_load_T_10 = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1[63]; // @[Mul.scala 453:22]
  wire [63:0] exe_stage_mulDiv_0_dividor__dividend_load_T_11 = ~exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1; // @[Mul.scala 453:29]
  wire [63:0] exe_stage_mulDiv_0_dividor__dividend_load_T_13 = exe_stage_mulDiv_0_dividor__dividend_load_T_11 + 64'h1; // @[Mul.scala 453:37]
  wire [63:0] exe_stage_mulDiv_0_dividor__dividend_load_T_14 = exe_stage_mulDiv_0_dividor__dividend_load_T_10 ?
    exe_stage_mulDiv_0_dividor__dividend_load_T_13 : exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1; // @[Mul.scala 453:14]
  wire [63:0] exe_stage_mulDiv_0_dividor__dividend_load_T_15 = exe_stage_mulDiv_0_dividor_is32wPre ?
    exe_stage_mulDiv_0_dividor__dividend_load_T_9 : exe_stage_mulDiv_0_dividor__dividend_load_T_14; // @[Mul.scala 450:12]
  wire [31:0] exe_stage_mulDiv_0_dividor__divisor_load_T = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2[31:0]; // @[Mul.scala 461:27]
  wire  exe_stage_mulDiv_0_dividor__divisor_load_T_3 = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2[31]; // @[Mul.scala 464:39]
  wire [31:0] exe_stage_mulDiv_0_dividor__divisor_load_T_5 = ~exe_stage_mulDiv_0_dividor__divisor_load_T; // @[Mul.scala 464:46]
  wire [31:0] exe_stage_mulDiv_0_dividor__divisor_load_T_7 = exe_stage_mulDiv_0_dividor__divisor_load_T_5 + 32'h1; // @[Mul.scala 464:60]
  wire [31:0] exe_stage_mulDiv_0_dividor__divisor_load_T_9 = exe_stage_mulDiv_0_dividor__divisor_load_T_3 ?
    exe_stage_mulDiv_0_dividor__divisor_load_T_7 : exe_stage_mulDiv_0_dividor__divisor_load_T; // @[Mul.scala 464:32]
  wire [63:0] exe_stage_mulDiv_0_dividor__divisor_load_T_10 = {32'h0,exe_stage_mulDiv_0_dividor__divisor_load_T_9}; // @[Cat.scala 33:92]
  wire  exe_stage_mulDiv_0_dividor__divisor_load_T_11 = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2[63]; // @[Mul.scala 465:20]
  wire [63:0] exe_stage_mulDiv_0_dividor__divisor_load_T_12 = ~exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2; // @[Mul.scala 465:27]
  wire [63:0] exe_stage_mulDiv_0_dividor__divisor_load_T_14 = exe_stage_mulDiv_0_dividor__divisor_load_T_12 + 64'h1; // @[Mul.scala 465:35]
  wire  exe_stage_mulDiv_0_dividor_isDivByZero = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2 == 64'h0; // @[Mul.scala 480:29]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T = ~exe_stage_mulDiv_0_dividor_isUsiPre; // @[Mul.scala 481:23]
  wire [30:0] exe_stage_mulDiv_0_dividor__isDivOverflow_T_3 = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1[30:0]
    ; // @[Mul.scala 483:58]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_4 = exe_stage_mulDiv_0_dividor__isDivOverflow_T_3 == 31'h0; // @[Mul.scala 483:65]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_5 = exe_stage_mulDiv_0_dividor__dividend_load_T_2 &
    exe_stage_mulDiv_0_dividor__isDivOverflow_T_4; // @[Mul.scala 483:49]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_6 = exe_stage_mulDiv_0_dividor_is32wPre &
    exe_stage_mulDiv_0_dividor__isDivOverflow_T_5; // @[Mul.scala 483:28]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_8 = &exe_stage_mulDiv_0_dividor__divisor_load_T; // @[Mul.scala 483:92]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_10 = exe_stage_mulDiv_0_dividor__isDivOverflow_T_6 &
    exe_stage_mulDiv_0_dividor__isDivOverflow_T_8; // @[Mul.scala 483:76]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_11 = ~exe_stage_mulDiv_0_dividor_is32wPre; // @[Mul.scala 485:18]
  wire [62:0] exe_stage_mulDiv_0_dividor__isDivOverflow_T_14 = exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1[62:0
    ]; // @[Mul.scala 485:58]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_15 = exe_stage_mulDiv_0_dividor__isDivOverflow_T_14 == 63'h0; // @[Mul.scala 485:65]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_16 = exe_stage_mulDiv_0_dividor__dividend_load_T_10 &
    exe_stage_mulDiv_0_dividor__isDivOverflow_T_15; // @[Mul.scala 485:49]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_17 = exe_stage_mulDiv_0_dividor__isDivOverflow_T_11 &
    exe_stage_mulDiv_0_dividor__isDivOverflow_T_16; // @[Mul.scala 485:28]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_19 = &exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2; // @[Mul.scala 485:92]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_21 = exe_stage_mulDiv_0_dividor__isDivOverflow_T_17 &
    exe_stage_mulDiv_0_dividor__isDivOverflow_T_19; // @[Mul.scala 485:76]
  wire  exe_stage_mulDiv_0_dividor__isDivOverflow_T_22 = exe_stage_mulDiv_0_dividor__isDivOverflow_T_10 |
    exe_stage_mulDiv_0_dividor__isDivOverflow_T_21; // @[Mul.scala 484:17]
  wire  exe_stage_mulDiv_0_dividor_isDivOverflow = exe_stage_mulDiv_0_dividor__isDivOverflow_T &
    exe_stage_mulDiv_0_dividor__isDivOverflow_T_22; // @[Mul.scala 481:33]
  wire  exe_stage_mulDiv_0_dividor_divBypass = exe_stage_mulDiv_0_dividor_isDivByZero |
    exe_stage_mulDiv_0_dividor_isDivOverflow; // @[Mul.scala 487:31]
  wire  exe_stage_mulDiv_0_dividor__remaDZRes_T_1 = exe_stage_mulDiv_0_dividor__dividend_load_T[31]; // @[Util.scala 29:36]
  wire [31:0] exe_stage_mulDiv_0_dividor__remaDZRes_T_3 = exe_stage_mulDiv_0_dividor__remaDZRes_T_1 ? 32'hffffffff : 32'h0
    ; // @[Bitwise.scala 77:12]
  wire [63:0] exe_stage_mulDiv_0_dividor__remaDZRes_T_4 = {exe_stage_mulDiv_0_dividor__remaDZRes_T_3,
    exe_stage_mulDiv_0_dividor__dividend_load_T}; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_mulDiv_0_dividor_remaDZRes = exe_stage_mulDiv_0_dividor_is32wPre ?
    exe_stage_mulDiv_0_dividor__remaDZRes_T_4 : exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1; // @[Mul.scala 490:22]
  wire [63:0] exe_stage_mulDiv_0_dividor_quotOFRes = exe_stage_mulDiv_0_dividor_is32wPre ? 64'hffffffff80000000 : 64'h8000000000000000
    ; // @[Mul.scala 491:22]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassQuo_T = exe_stage_mulDiv_0_dividor_isDivByZero ? 64'hffffffffffffffff : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassQuo_T_1 = exe_stage_mulDiv_0_dividor_isDivOverflow ?
    exe_stage_mulDiv_0_dividor_quotOFRes : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassQuo_T_2 = exe_stage_mulDiv_0_dividor__byPassQuo_T |
    exe_stage_mulDiv_0_dividor__byPassQuo_T_1; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRem_T = exe_stage_mulDiv_0_dividor_isDivByZero ?
    exe_stage_mulDiv_0_dividor_remaDZRes : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_div ?
    exe_stage_mulDiv_0_dividor__byPassQuo_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_1 = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divu ?
    exe_stage_mulDiv_0_dividor__byPassQuo_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_2 = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divw ?
    exe_stage_mulDiv_0_dividor__byPassQuo_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_3 = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divuw ?
    exe_stage_mulDiv_0_dividor__byPassQuo_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_4 = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remw ?
    exe_stage_mulDiv_0_dividor__byPassRem_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_5 = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remuw ?
    exe_stage_mulDiv_0_dividor__byPassRem_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_6 = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_rem ?
    exe_stage_mulDiv_0_dividor__byPassRem_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_7 = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remu ?
    exe_stage_mulDiv_0_dividor__byPassRem_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_8 = exe_stage_mulDiv_0_dividor__byPassRes_T |
    exe_stage_mulDiv_0_dividor__byPassRes_T_1; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_9 = exe_stage_mulDiv_0_dividor__byPassRes_T_8 |
    exe_stage_mulDiv_0_dividor__byPassRes_T_2; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_10 = exe_stage_mulDiv_0_dividor__byPassRes_T_9 |
    exe_stage_mulDiv_0_dividor__byPassRes_T_3; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_11 = exe_stage_mulDiv_0_dividor__byPassRes_T_10 |
    exe_stage_mulDiv_0_dividor__byPassRes_T_4; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_12 = exe_stage_mulDiv_0_dividor__byPassRes_T_11 |
    exe_stage_mulDiv_0_dividor__byPassRes_T_5; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__byPassRes_T_13 = exe_stage_mulDiv_0_dividor__byPassRes_T_12 |
    exe_stage_mulDiv_0_dividor__byPassRes_T_6; // @[Mux.scala 27:73]
  wire  exe_stage_mulDiv_0_dividor__algDivider_io_enq_valid_T = ~exe_stage_mulDiv_0_dividor_divBypass; // @[Mul.scala 509:47]
  wire  exe_stage_mulDiv_0_dividor__is32wPost_T = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divw |
    exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divuw; // @[riscv_isa.scala 199:23]
  wire  exe_stage_mulDiv_0_dividor__is32wPost_T_1 = exe_stage_mulDiv_0_dividor__is32wPost_T |
    exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remw; // @[riscv_isa.scala 199:31]
  wire  exe_stage_mulDiv_0_dividor_is32wPost = exe_stage_mulDiv_0_dividor__is32wPost_T_1 |
    exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remuw; // @[riscv_isa.scala 199:39]
  wire  exe_stage_mulDiv_0_dividor__isUsiPost_T = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divu |
    exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remu; // @[riscv_isa.scala 200:23]
  wire  exe_stage_mulDiv_0_dividor__isUsiPost_T_1 = exe_stage_mulDiv_0_dividor__isUsiPost_T |
    exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divuw; // @[riscv_isa.scala 200:31]
  wire  exe_stage_mulDiv_0_dividor_isUsiPost = exe_stage_mulDiv_0_dividor__isUsiPost_T_1 |
    exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remuw; // @[riscv_isa.scala 200:39]
  wire  exe_stage_mulDiv_0_dividor__dividend_sign_T = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_dat_op1[31
    ]; // @[Mul.scala 525:69]
  wire  exe_stage_mulDiv_0_dividor__dividend_sign_T_2 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_dat_op1[
    63]; // @[Mul.scala 525:89]
  wire  exe_stage_mulDiv_0_dividor__dividend_sign_T_4 = exe_stage_mulDiv_0_dividor_is32wPost ?
    exe_stage_mulDiv_0_dividor__dividend_sign_T : exe_stage_mulDiv_0_dividor__dividend_sign_T_2; // @[Mul.scala 525:50]
  wire  exe_stage_mulDiv_0_dividor_dividend_sign = exe_stage_mulDiv_0_dividor_isUsiPost ? 1'h0 :
    exe_stage_mulDiv_0_dividor__dividend_sign_T_4; // @[Mul.scala 525:26]
  wire  exe_stage_mulDiv_0_dividor__divisor_sign_T = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_dat_op2[31]
    ; // @[Mul.scala 526:69]
  wire  exe_stage_mulDiv_0_dividor__divisor_sign_T_2 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_dat_op2[
    63]; // @[Mul.scala 526:89]
  wire  exe_stage_mulDiv_0_dividor__divisor_sign_T_4 = exe_stage_mulDiv_0_dividor_is32wPost ?
    exe_stage_mulDiv_0_dividor__divisor_sign_T : exe_stage_mulDiv_0_dividor__divisor_sign_T_2; // @[Mul.scala 526:50]
  wire  exe_stage_mulDiv_0_dividor_divisor_sign = exe_stage_mulDiv_0_dividor_isUsiPost ? 1'h0 :
    exe_stage_mulDiv_0_dividor__divisor_sign_T_4; // @[Mul.scala 526:26]
  wire  exe_stage_mulDiv_0_dividor__quot_sign_corrcet_T = exe_stage_mulDiv_0_dividor_dividend_sign ^
    exe_stage_mulDiv_0_dividor_divisor_sign; // @[Mul.scala 529:22]
  wire [63:0] exe_stage_mulDiv_0_dividor__quot_sign_corrcet_T_1 = ~exe_stage_mulDiv_0_dividor_algDivider_io_quo; // @[Mul.scala 529:37]
  wire [63:0] exe_stage_mulDiv_0_dividor__quot_sign_corrcet_T_3 = exe_stage_mulDiv_0_dividor__quot_sign_corrcet_T_1 + 64'h1
    ; // @[Mul.scala 529:56]
  wire [63:0] exe_stage_mulDiv_0_dividor_quot_sign_corrcet = exe_stage_mulDiv_0_dividor__quot_sign_corrcet_T ?
    exe_stage_mulDiv_0_dividor__quot_sign_corrcet_T_3 : exe_stage_mulDiv_0_dividor_algDivider_io_quo; // @[Mul.scala 529:8]
  wire [63:0] exe_stage_mulDiv_0_dividor__rema_sign_corrcet_T = ~exe_stage_mulDiv_0_dividor_algDivider_io_rem; // @[Mul.scala 532:24]
  wire [63:0] exe_stage_mulDiv_0_dividor__rema_sign_corrcet_T_2 = exe_stage_mulDiv_0_dividor__rema_sign_corrcet_T + 64'h1
    ; // @[Mul.scala 532:43]
  wire [63:0] exe_stage_mulDiv_0_dividor_rema_sign_corrcet = exe_stage_mulDiv_0_dividor_dividend_sign ?
    exe_stage_mulDiv_0_dividor__rema_sign_corrcet_T_2 : exe_stage_mulDiv_0_dividor_algDivider_io_rem; // @[Mul.scala 532:8]
  wire [31:0] exe_stage_mulDiv_0_dividor__divRes_T = exe_stage_mulDiv_0_dividor_quot_sign_corrcet[31:0]; // @[Mul.scala 540:67]
  wire  exe_stage_mulDiv_0_dividor__divRes_T_1 = exe_stage_mulDiv_0_dividor__divRes_T[31]; // @[Util.scala 29:36]
  wire [31:0] exe_stage_mulDiv_0_dividor__divRes_T_3 = exe_stage_mulDiv_0_dividor__divRes_T_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_4 = {exe_stage_mulDiv_0_dividor__divRes_T_3,
    exe_stage_mulDiv_0_dividor__divRes_T}; // @[Cat.scala 33:92]
  wire [31:0] exe_stage_mulDiv_0_dividor__divRes_T_10 = exe_stage_mulDiv_0_dividor_rema_sign_corrcet[31:0]; // @[Mul.scala 542:67]
  wire  exe_stage_mulDiv_0_dividor__divRes_T_11 = exe_stage_mulDiv_0_dividor__divRes_T_10[31]; // @[Util.scala 29:36]
  wire [31:0] exe_stage_mulDiv_0_dividor__divRes_T_13 = exe_stage_mulDiv_0_dividor__divRes_T_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_14 = {exe_stage_mulDiv_0_dividor__divRes_T_13,
    exe_stage_mulDiv_0_dividor__divRes_T_10}; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_20 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_div ?
    exe_stage_mulDiv_0_dividor_quot_sign_corrcet : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_21 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divu ?
    exe_stage_mulDiv_0_dividor_quot_sign_corrcet : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_22 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_rem ?
    exe_stage_mulDiv_0_dividor_rema_sign_corrcet : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_23 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remu ?
    exe_stage_mulDiv_0_dividor_rema_sign_corrcet : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_24 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divw ?
    exe_stage_mulDiv_0_dividor__divRes_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_25 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divuw ?
    exe_stage_mulDiv_0_dividor__divRes_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_26 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remw ?
    exe_stage_mulDiv_0_dividor__divRes_T_14 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_27 = exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remuw ?
    exe_stage_mulDiv_0_dividor__divRes_T_14 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_28 = exe_stage_mulDiv_0_dividor__divRes_T_20 |
    exe_stage_mulDiv_0_dividor__divRes_T_21; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_29 = exe_stage_mulDiv_0_dividor__divRes_T_28 |
    exe_stage_mulDiv_0_dividor__divRes_T_22; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_30 = exe_stage_mulDiv_0_dividor__divRes_T_29 |
    exe_stage_mulDiv_0_dividor__divRes_T_23; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_31 = exe_stage_mulDiv_0_dividor__divRes_T_30 |
    exe_stage_mulDiv_0_dividor__divRes_T_24; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_32 = exe_stage_mulDiv_0_dividor__divRes_T_31 |
    exe_stage_mulDiv_0_dividor__divRes_T_25; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0_dividor__divRes_T_33 = exe_stage_mulDiv_0_dividor__divRes_T_32 |
    exe_stage_mulDiv_0_dividor__divRes_T_26; // @[Mux.scala 27:73]
  wire  exe_stage_mulDiv_0_iwbArb_io_in_0_ready;
  wire  exe_stage_mulDiv_0_iwbArb_io_in_0_valid;
  wire [5:0] exe_stage_mulDiv_0_iwbArb_io_in_0_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_iwbArb_io_in_0_bits_res;
  wire  exe_stage_mulDiv_0_iwbArb_io_in_1_ready;
  wire  exe_stage_mulDiv_0_iwbArb_io_in_1_valid;
  wire [5:0] exe_stage_mulDiv_0_iwbArb_io_in_1_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_iwbArb_io_in_1_bits_res;
  wire  exe_stage_mulDiv_0_iwbArb_io_out_ready;
  wire  exe_stage_mulDiv_0_iwbArb_io_out_valid;
  wire [5:0] exe_stage_mulDiv_0_iwbArb_io_out_bits_rd0;
  wire [63:0] exe_stage_mulDiv_0_iwbArb_io_out_bits_res;
  wire  exe_stage_mulDiv_0_iwbArb_grant_1 = ~exe_stage_mulDiv_0_iwbArb_io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  exe_stage_mulDiv_0_iwbArb__io_out_valid_T = ~exe_stage_mulDiv_0_iwbArb_grant_1; // @[Arbiter.scala 147:19]
  wire  exe_stage_mulDiv_0__mul_op1_sign_T = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mul |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulh; // @[Mul.scala 52:37]
  wire  exe_stage_mulDiv_0__mul_op1_sign_T_1 = exe_stage_mulDiv_0__mul_op1_sign_T |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulhsu; // @[Mul.scala 52:68]
  wire  exe_stage_mulDiv_0__mul_op1_sign_T_2 = exe_stage_mulDiv_0__mul_op1_sign_T_1 |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw; // @[Mul.scala 52:101]
  wire  exe_stage_mulDiv_0__mul_op1_sign_T_3 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op1[31]; // @[Mul.scala 53:74]
  wire  exe_stage_mulDiv_0__mul_op1_sign_T_4 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op1[63]; // @[Mul.scala 53:113]
  wire  exe_stage_mulDiv_0__mul_op1_sign_T_5 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw ?
    exe_stage_mulDiv_0__mul_op1_sign_T_3 : exe_stage_mulDiv_0__mul_op1_sign_T_4; // @[Mul.scala 53:10]
  wire  exe_stage_mulDiv_0_mul_op1_sign = exe_stage_mulDiv_0__mul_op1_sign_T_2 & exe_stage_mulDiv_0__mul_op1_sign_T_5; // @[Mul.scala 51:8]
  wire  exe_stage_mulDiv_0__mul_op2_sign_T_1 = exe_stage_mulDiv_0__mul_op1_sign_T |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw; // @[Mul.scala 59:67]
  wire  exe_stage_mulDiv_0__mul_op2_sign_T_2 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op2[31]; // @[Mul.scala 60:74]
  wire  exe_stage_mulDiv_0__mul_op2_sign_T_3 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op2[63]; // @[Mul.scala 60:113]
  wire  exe_stage_mulDiv_0__mul_op2_sign_T_4 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw ?
    exe_stage_mulDiv_0__mul_op2_sign_T_2 : exe_stage_mulDiv_0__mul_op2_sign_T_3; // @[Mul.scala 60:10]
  wire  exe_stage_mulDiv_0_mul_op2_sign = exe_stage_mulDiv_0__mul_op2_sign_T_1 & exe_stage_mulDiv_0__mul_op2_sign_T_4; // @[Mul.scala 58:8]
  wire [32:0] exe_stage_mulDiv_0__mul_op1_T_1 = exe_stage_mulDiv_0_mul_op1_sign ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 77:12]
  wire [31:0] exe_stage_mulDiv_0__mul_op1_T_2 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op1[31:0]; // @[Mul.scala 67:68]
  wire [64:0] exe_stage_mulDiv_0__mul_op1_T_3 = {exe_stage_mulDiv_0__mul_op1_T_1,exe_stage_mulDiv_0__mul_op1_T_2}; // @[Cat.scala 33:92]
  wire [64:0] exe_stage_mulDiv_0__mul_op1_T_4 = {exe_stage_mulDiv_0_mul_op1_sign,
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op1}; // @[Cat.scala 33:92]
  wire [32:0] exe_stage_mulDiv_0__mul_op2_T_1 = exe_stage_mulDiv_0_mul_op2_sign ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 77:12]
  wire [31:0] exe_stage_mulDiv_0__mul_op2_T_2 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op2[31:0]; // @[Mul.scala 74:68]
  wire [64:0] exe_stage_mulDiv_0__mul_op2_T_3 = {exe_stage_mulDiv_0__mul_op2_T_1,exe_stage_mulDiv_0__mul_op2_T_2}; // @[Cat.scala 33:92]
  wire [64:0] exe_stage_mulDiv_0__mul_op2_T_4 = {exe_stage_mulDiv_0_mul_op2_sign,
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op2}; // @[Cat.scala 33:92]
  wire  exe_stage_mulDiv_0__multiplier_io_enq_valid_T_2 = exe_stage_mulDiv_0__mul_op1_sign_T_1 |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulhu; // @[riscv_isa.scala 203:35]
  wire  exe_stage_mulDiv_0__multiplier_io_enq_valid_T_3 = exe_stage_mulDiv_0__multiplier_io_enq_valid_T_2 |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw; // @[riscv_isa.scala 203:43]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T = exe_stage_mulDiv_0_multiplier_io_res[63:0]; // @[Mul.scala 92:59]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_1 = exe_stage_mulDiv_0_multiplier_io_res[127:64]; // @[Mul.scala 93:59]
  wire [31:0] exe_stage_mulDiv_0__mulRes_T_4 = exe_stage_mulDiv_0_multiplier_io_res[31:0]; // @[Mul.scala 96:67]
  wire  exe_stage_mulDiv_0__mulRes_T_5 = exe_stage_mulDiv_0__mulRes_T_4[31]; // @[Util.scala 29:36]
  wire [31:0] exe_stage_mulDiv_0__mulRes_T_7 = exe_stage_mulDiv_0__mulRes_T_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_8 = {exe_stage_mulDiv_0__mulRes_T_7,exe_stage_mulDiv_0__mulRes_T_4}; // @[Cat.scala 33:92]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_9 = exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mul ?
    exe_stage_mulDiv_0__mulRes_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_10 = exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulh ?
    exe_stage_mulDiv_0__mulRes_T_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_11 = exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulhsu ?
    exe_stage_mulDiv_0__mulRes_T_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_12 = exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulhu ?
    exe_stage_mulDiv_0__mulRes_T_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_13 = exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulw ?
    exe_stage_mulDiv_0__mulRes_T_8 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_14 = exe_stage_mulDiv_0__mulRes_T_9 | exe_stage_mulDiv_0__mulRes_T_10; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_15 = exe_stage_mulDiv_0__mulRes_T_14 | exe_stage_mulDiv_0__mulRes_T_11; // @[Mux.scala 27:73]
  wire [63:0] exe_stage_mulDiv_0__mulRes_T_16 = exe_stage_mulDiv_0__mulRes_T_15 | exe_stage_mulDiv_0__mulRes_T_12; // @[Mux.scala 27:73]
  wire  exe_stage_mulDiv_0__dividor_io_enq_valid_T = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_div |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divu; // @[riscv_isa.scala 204:19]
  wire  exe_stage_mulDiv_0__dividor_io_enq_valid_T_1 = exe_stage_mulDiv_0__dividor_io_enq_valid_T |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divw; // @[riscv_isa.scala 204:26]
  wire  exe_stage_mulDiv_0__dividor_io_enq_valid_T_2 = exe_stage_mulDiv_0__dividor_io_enq_valid_T_1 |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divuw; // @[riscv_isa.scala 204:33]
  wire  exe_stage_mulDiv_0__dividor_io_enq_valid_T_3 = exe_stage_mulDiv_0__dividor_io_enq_valid_T_2 |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_rem; // @[riscv_isa.scala 204:41]
  wire  exe_stage_mulDiv_0__dividor_io_enq_valid_T_4 = exe_stage_mulDiv_0__dividor_io_enq_valid_T_3 |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remu; // @[riscv_isa.scala 204:47]
  wire  exe_stage_mulDiv_0__dividor_io_enq_valid_T_5 = exe_stage_mulDiv_0__dividor_io_enq_valid_T_4 |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remw; // @[riscv_isa.scala 204:54]
  wire  exe_stage_mulDiv_0__dividor_io_enq_valid_T_6 = exe_stage_mulDiv_0__dividor_io_enq_valid_T_5 |
    exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remuw; // @[riscv_isa.scala 204:61]
  wire  exe_stage_fpu_0_clock;
  wire  exe_stage_fpu_0_reset;
  wire  exe_stage_fpu_0_io_fpu_iss_exe_valid;
  wire  exe_stage_fpu_0_io_fpu_exe_iwb_valid;
  wire [5:0] exe_stage_fpu_0_io_fpu_exe_iwb_bits_rd0;
  wire [64:0] exe_stage_fpu_0_io_fpu_exe_iwb_bits_res;
  wire  exe_stage_fpu_0_io_fpu_exe_fwb_valid;
  wire  exe_stage_fpu_0_io_fcsr_cmm_op_0_valid;
  wire [11:0] exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_addr;
  wire [63:0] exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_dat_i;
  wire  exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rw;
  wire  exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rs;
  wire  exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rc;
  wire  exe_stage_fpu_0__T = ~exe_stage_fpu_0_io_fpu_iss_exe_valid; // @[FAlu.scala 282:11]
  wire  exe_stage_fpu_0__T_2 = ~exe_stage_fpu_0_reset; // @[FAlu.scala 282:9]
  wire  exe_stage_fpu_0__T_3 = ~exe_stage_fpu_0__T; // @[FAlu.scala 282:9]
  wire  iwb_stage_clock;
  wire  iwb_stage_reset;
  wire [5:0] iwb_stage_io_xLookup_0_rsp_rs1;
  wire [5:0] iwb_stage_io_xLookup_0_rsp_rs2;
  wire [4:0] iwb_stage_io_xLookup_0_req_rs1;
  wire [4:0] iwb_stage_io_xLookup_0_req_rs2;
  wire [5:0] iwb_stage_io_fLookup_0_rsp_rs1;
  wire [5:0] iwb_stage_io_fLookup_0_rsp_rs2;
  wire [5:0] iwb_stage_io_fLookup_0_rsp_rs3;
  wire [5:0] iwb_stage_io_xRename_0_rsp_rd0;
  wire  iwb_stage_io_xRename_0_req_ready;
  wire  iwb_stage_io_xRename_0_req_valid;
  wire [4:0] iwb_stage_io_xRename_0_req_bits_rd0;
  wire [5:0] iwb_stage_io_fRename_0_rsp_rd0;
  wire  iwb_stage_io_fRename_0_req_ready;
  wire [1:0] iwb_stage_io_irgLog_0;
  wire [1:0] iwb_stage_io_irgLog_1;
  wire [1:0] iwb_stage_io_irgLog_2;
  wire [1:0] iwb_stage_io_irgLog_3;
  wire [1:0] iwb_stage_io_irgLog_4;
  wire [1:0] iwb_stage_io_irgLog_5;
  wire [1:0] iwb_stage_io_irgLog_6;
  wire [1:0] iwb_stage_io_irgLog_7;
  wire [1:0] iwb_stage_io_irgLog_8;
  wire [1:0] iwb_stage_io_irgLog_9;
  wire [1:0] iwb_stage_io_irgLog_10;
  wire [1:0] iwb_stage_io_irgLog_11;
  wire [1:0] iwb_stage_io_irgLog_12;
  wire [1:0] iwb_stage_io_irgLog_13;
  wire [1:0] iwb_stage_io_irgLog_14;
  wire [1:0] iwb_stage_io_irgLog_15;
  wire [1:0] iwb_stage_io_irgLog_16;
  wire [1:0] iwb_stage_io_irgLog_17;
  wire [1:0] iwb_stage_io_irgLog_18;
  wire [1:0] iwb_stage_io_irgLog_19;
  wire [1:0] iwb_stage_io_irgLog_20;
  wire [1:0] iwb_stage_io_irgLog_21;
  wire [1:0] iwb_stage_io_irgLog_22;
  wire [1:0] iwb_stage_io_irgLog_23;
  wire [1:0] iwb_stage_io_irgLog_24;
  wire [1:0] iwb_stage_io_irgLog_25;
  wire [1:0] iwb_stage_io_irgLog_26;
  wire [1:0] iwb_stage_io_irgLog_27;
  wire [1:0] iwb_stage_io_irgLog_28;
  wire [1:0] iwb_stage_io_irgLog_29;
  wire [1:0] iwb_stage_io_irgLog_30;
  wire [1:0] iwb_stage_io_irgLog_31;
  wire [1:0] iwb_stage_io_irgLog_32;
  wire [1:0] iwb_stage_io_irgLog_33;
  wire [1:0] iwb_stage_io_frgLog_0;
  wire [1:0] iwb_stage_io_frgLog_1;
  wire [1:0] iwb_stage_io_frgLog_2;
  wire [1:0] iwb_stage_io_frgLog_3;
  wire [1:0] iwb_stage_io_frgLog_4;
  wire [1:0] iwb_stage_io_frgLog_5;
  wire [1:0] iwb_stage_io_frgLog_6;
  wire [1:0] iwb_stage_io_frgLog_7;
  wire [1:0] iwb_stage_io_frgLog_8;
  wire [1:0] iwb_stage_io_frgLog_9;
  wire [1:0] iwb_stage_io_frgLog_10;
  wire [1:0] iwb_stage_io_frgLog_11;
  wire [1:0] iwb_stage_io_frgLog_12;
  wire [1:0] iwb_stage_io_frgLog_13;
  wire [1:0] iwb_stage_io_frgLog_14;
  wire [1:0] iwb_stage_io_frgLog_15;
  wire [1:0] iwb_stage_io_frgLog_16;
  wire [1:0] iwb_stage_io_frgLog_17;
  wire [1:0] iwb_stage_io_frgLog_18;
  wire [1:0] iwb_stage_io_frgLog_19;
  wire [1:0] iwb_stage_io_frgLog_20;
  wire [1:0] iwb_stage_io_frgLog_21;
  wire [1:0] iwb_stage_io_frgLog_22;
  wire [1:0] iwb_stage_io_frgLog_23;
  wire [1:0] iwb_stage_io_frgLog_24;
  wire [1:0] iwb_stage_io_frgLog_25;
  wire [1:0] iwb_stage_io_frgLog_26;
  wire [1:0] iwb_stage_io_frgLog_27;
  wire [1:0] iwb_stage_io_frgLog_28;
  wire [1:0] iwb_stage_io_frgLog_29;
  wire [1:0] iwb_stage_io_frgLog_30;
  wire [1:0] iwb_stage_io_frgLog_31;
  wire [1:0] iwb_stage_io_frgLog_32;
  wire [1:0] iwb_stage_io_frgLog_33;
  wire  iwb_stage_io_irgReq_0_valid;
  wire [5:0] iwb_stage_io_irgReq_0_bits;
  wire  iwb_stage_io_irgRsp_0_valid;
  wire [5:0] iwb_stage_io_irgRsp_0_bits_phy;
  wire [63:0] iwb_stage_io_irgRsp_0_bits_op;
  wire  iwb_stage_io_alu_iWriteBack_0_ready;
  wire  iwb_stage_io_alu_iWriteBack_0_valid;
  wire [5:0] iwb_stage_io_alu_iWriteBack_0_bits_rd0;
  wire [63:0] iwb_stage_io_alu_iWriteBack_0_bits_res;
  wire  iwb_stage_io_bru_iWriteBack_ready;
  wire  iwb_stage_io_bru_iWriteBack_valid;
  wire [5:0] iwb_stage_io_bru_iWriteBack_bits_rd0;
  wire [63:0] iwb_stage_io_bru_iWriteBack_bits_res;
  wire  iwb_stage_io_csr_iWriteBack_ready;
  wire  iwb_stage_io_csr_iWriteBack_valid;
  wire [5:0] iwb_stage_io_csr_iWriteBack_bits_rd0;
  wire [63:0] iwb_stage_io_csr_iWriteBack_bits_res;
  wire  iwb_stage_io_mem_iWriteBack_ready;
  wire  iwb_stage_io_mem_iWriteBack_valid;
  wire [5:0] iwb_stage_io_mem_iWriteBack_bits_rd0;
  wire [63:0] iwb_stage_io_mem_iWriteBack_bits_res;
  wire  iwb_stage_io_mul_iWriteBack_0_ready;
  wire  iwb_stage_io_mul_iWriteBack_0_valid;
  wire [5:0] iwb_stage_io_mul_iWriteBack_0_bits_rd0;
  wire [63:0] iwb_stage_io_mul_iWriteBack_0_bits_res;
  wire  iwb_stage_io_fpu_iWriteBack_0_valid;
  wire [5:0] iwb_stage_io_fpu_iWriteBack_0_bits_rd0;
  wire [63:0] iwb_stage_io_fpu_iWriteBack_0_bits_res;
  wire  iwb_stage_io_mem_fWriteBack_ready;
  wire  iwb_stage_io_mem_fWriteBack_valid;
  wire  iwb_stage_io_fpu_fWriteBack_0_valid;
  wire  iwb_stage_io_commit_0_is_comfirm;
  wire  iwb_stage_io_commit_0_is_MisPredict;
  wire  iwb_stage_io_commit_0_is_abort;
  wire [4:0] iwb_stage_io_commit_0_raw;
  wire [5:0] iwb_stage_io_commit_0_phy;
  wire  iwb_stage_io_commit_0_toX;
  wire  iwb_stage_io_commit_0_toF;
  wire  iwb_stage_io_commit_0_is_writeback;
  wire  iwb_stage_iReg_clock;
  wire  iwb_stage_iReg_reset;
  wire [5:0] iwb_stage_iReg_io_lookup_0_rsp_rs1;
  wire [5:0] iwb_stage_iReg_io_lookup_0_rsp_rs2;
  wire [4:0] iwb_stage_iReg_io_lookup_0_req_rs1;
  wire [4:0] iwb_stage_iReg_io_lookup_0_req_rs2;
  wire [5:0] iwb_stage_iReg_io_rename_0_rsp_rd0;
  wire  iwb_stage_iReg_io_rename_0_req_ready;
  wire  iwb_stage_iReg_io_rename_0_req_valid;
  wire [4:0] iwb_stage_iReg_io_rename_0_req_bits_rd0;
  wire [1:0] iwb_stage_iReg_io_rgLog_0;
  wire [1:0] iwb_stage_iReg_io_rgLog_1;
  wire [1:0] iwb_stage_iReg_io_rgLog_2;
  wire [1:0] iwb_stage_iReg_io_rgLog_3;
  wire [1:0] iwb_stage_iReg_io_rgLog_4;
  wire [1:0] iwb_stage_iReg_io_rgLog_5;
  wire [1:0] iwb_stage_iReg_io_rgLog_6;
  wire [1:0] iwb_stage_iReg_io_rgLog_7;
  wire [1:0] iwb_stage_iReg_io_rgLog_8;
  wire [1:0] iwb_stage_iReg_io_rgLog_9;
  wire [1:0] iwb_stage_iReg_io_rgLog_10;
  wire [1:0] iwb_stage_iReg_io_rgLog_11;
  wire [1:0] iwb_stage_iReg_io_rgLog_12;
  wire [1:0] iwb_stage_iReg_io_rgLog_13;
  wire [1:0] iwb_stage_iReg_io_rgLog_14;
  wire [1:0] iwb_stage_iReg_io_rgLog_15;
  wire [1:0] iwb_stage_iReg_io_rgLog_16;
  wire [1:0] iwb_stage_iReg_io_rgLog_17;
  wire [1:0] iwb_stage_iReg_io_rgLog_18;
  wire [1:0] iwb_stage_iReg_io_rgLog_19;
  wire [1:0] iwb_stage_iReg_io_rgLog_20;
  wire [1:0] iwb_stage_iReg_io_rgLog_21;
  wire [1:0] iwb_stage_iReg_io_rgLog_22;
  wire [1:0] iwb_stage_iReg_io_rgLog_23;
  wire [1:0] iwb_stage_iReg_io_rgLog_24;
  wire [1:0] iwb_stage_iReg_io_rgLog_25;
  wire [1:0] iwb_stage_iReg_io_rgLog_26;
  wire [1:0] iwb_stage_iReg_io_rgLog_27;
  wire [1:0] iwb_stage_iReg_io_rgLog_28;
  wire [1:0] iwb_stage_iReg_io_rgLog_29;
  wire [1:0] iwb_stage_iReg_io_rgLog_30;
  wire [1:0] iwb_stage_iReg_io_rgLog_31;
  wire [1:0] iwb_stage_iReg_io_rgLog_32;
  wire [1:0] iwb_stage_iReg_io_rgLog_33;
  wire  iwb_stage_iReg_io_rgReq_0_valid;
  wire [5:0] iwb_stage_iReg_io_rgReq_0_bits;
  wire  iwb_stage_iReg_io_rgRsp_0_valid;
  wire [5:0] iwb_stage_iReg_io_rgRsp_0_bits_phy;
  wire [63:0] iwb_stage_iReg_io_rgRsp_0_bits_op;
  wire  iwb_stage_iReg_io_exe_writeBack_0_ready;
  wire  iwb_stage_iReg_io_exe_writeBack_0_valid;
  wire [5:0] iwb_stage_iReg_io_exe_writeBack_0_bits_rd0;
  wire [63:0] iwb_stage_iReg_io_exe_writeBack_0_bits_res;
  wire  iwb_stage_iReg_io_commit_0_is_comfirm;
  wire  iwb_stage_iReg_io_commit_0_is_MisPredict;
  wire  iwb_stage_iReg_io_commit_0_is_abort;
  wire [4:0] iwb_stage_iReg_io_commit_0_raw;
  wire [5:0] iwb_stage_iReg_io_commit_0_phy;
  wire  iwb_stage_iReg_io_commit_0_is_writeback;
  reg [1:0] iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_1; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_2; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_3; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_4; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_5; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_6; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_7; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_8; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_9; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_10; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_11; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_12; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_13; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_14; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_15; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_16; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_17; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_18; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_19; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_20; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_21; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_22; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_23; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_24; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_25; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_26; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_27; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_28; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_29; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_30; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_31; // @[Regfiles.scala 101:12]
  reg [1:0] iwb_stage_iReg_log_reg_32; // @[Regfiles.scala 101:12]
  reg [63:0] iwb_stage_iReg_files_reg_0; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_1; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_2; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_3; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_4; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_5; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_6; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_7; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_8; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_9; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_10; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_11; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_12; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_13; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_14; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_15; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_16; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_17; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_18; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_19; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_20; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_21; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_22; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_23; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_24; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_25; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_26; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_27; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_28; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_29; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_30; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_31; // @[Regfiles.scala 114:26]
  reg [63:0] iwb_stage_iReg_files_reg_32; // @[Regfiles.scala 114:26]
  reg [5:0] iwb_stage_iReg_rename_ptr_0; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_1; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_2; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_3; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_4; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_5; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_6; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_7; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_8; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_9; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_10; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_11; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_12; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_13; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_14; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_15; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_16; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_17; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_18; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_19; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_20; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_21; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_22; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_23; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_24; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_25; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_26; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_27; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_28; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_29; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_30; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_rename_ptr_31; // @[Regfiles.scala 125:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_0; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_1; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_2; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_3; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_4; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_5; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_6; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_7; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_8; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_9; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_10; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_11; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_12; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_13; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_14; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_15; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_16; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_17; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_18; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_19; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_20; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_21; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_22; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_23; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_24; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_25; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_26; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_27; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_28; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_29; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_30; // @[Regfiles.scala 130:27]
  reg [5:0] iwb_stage_iReg_archit_ptr_31; // @[Regfiles.scala 130:27]
  wire  iwb_stage_iReg__T_1 = iwb_stage_iReg_log_reg_32 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1089 = iwb_stage_iReg__T_1 ? 6'h20 : 6'h0; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_2 = iwb_stage_iReg_log_reg_31 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1090 = iwb_stage_iReg__T_2 ? 6'h1f : iwb_stage_iReg__GEN_1089; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_3 = iwb_stage_iReg_log_reg_30 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1091 = iwb_stage_iReg__T_3 ? 6'h1e : iwb_stage_iReg__GEN_1090; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_4 = iwb_stage_iReg_log_reg_29 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1092 = iwb_stage_iReg__T_4 ? 6'h1d : iwb_stage_iReg__GEN_1091; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_5 = iwb_stage_iReg_log_reg_28 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1093 = iwb_stage_iReg__T_5 ? 6'h1c : iwb_stage_iReg__GEN_1092; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_6 = iwb_stage_iReg_log_reg_27 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1094 = iwb_stage_iReg__T_6 ? 6'h1b : iwb_stage_iReg__GEN_1093; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_7 = iwb_stage_iReg_log_reg_26 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1095 = iwb_stage_iReg__T_7 ? 6'h1a : iwb_stage_iReg__GEN_1094; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_8 = iwb_stage_iReg_log_reg_25 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1096 = iwb_stage_iReg__T_8 ? 6'h19 : iwb_stage_iReg__GEN_1095; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_9 = iwb_stage_iReg_log_reg_24 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1097 = iwb_stage_iReg__T_9 ? 6'h18 : iwb_stage_iReg__GEN_1096; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_10 = iwb_stage_iReg_log_reg_23 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1098 = iwb_stage_iReg__T_10 ? 6'h17 : iwb_stage_iReg__GEN_1097; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_11 = iwb_stage_iReg_log_reg_22 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1099 = iwb_stage_iReg__T_11 ? 6'h16 : iwb_stage_iReg__GEN_1098; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_12 = iwb_stage_iReg_log_reg_21 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1100 = iwb_stage_iReg__T_12 ? 6'h15 : iwb_stage_iReg__GEN_1099; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_13 = iwb_stage_iReg_log_reg_20 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1101 = iwb_stage_iReg__T_13 ? 6'h14 : iwb_stage_iReg__GEN_1100; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_14 = iwb_stage_iReg_log_reg_19 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1102 = iwb_stage_iReg__T_14 ? 6'h13 : iwb_stage_iReg__GEN_1101; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_15 = iwb_stage_iReg_log_reg_18 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1103 = iwb_stage_iReg__T_15 ? 6'h12 : iwb_stage_iReg__GEN_1102; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_16 = iwb_stage_iReg_log_reg_17 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1104 = iwb_stage_iReg__T_16 ? 6'h11 : iwb_stage_iReg__GEN_1103; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_17 = iwb_stage_iReg_log_reg_16 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1105 = iwb_stage_iReg__T_17 ? 6'h10 : iwb_stage_iReg__GEN_1104; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_18 = iwb_stage_iReg_log_reg_15 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1106 = iwb_stage_iReg__T_18 ? 6'hf : iwb_stage_iReg__GEN_1105; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_19 = iwb_stage_iReg_log_reg_14 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1107 = iwb_stage_iReg__T_19 ? 6'he : iwb_stage_iReg__GEN_1106; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_20 = iwb_stage_iReg_log_reg_13 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1108 = iwb_stage_iReg__T_20 ? 6'hd : iwb_stage_iReg__GEN_1107; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_21 = iwb_stage_iReg_log_reg_12 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1109 = iwb_stage_iReg__T_21 ? 6'hc : iwb_stage_iReg__GEN_1108; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_22 = iwb_stage_iReg_log_reg_11 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1110 = iwb_stage_iReg__T_22 ? 6'hb : iwb_stage_iReg__GEN_1109; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_23 = iwb_stage_iReg_log_reg_10 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1111 = iwb_stage_iReg__T_23 ? 6'ha : iwb_stage_iReg__GEN_1110; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_24 = iwb_stage_iReg_log_reg_9 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1112 = iwb_stage_iReg__T_24 ? 6'h9 : iwb_stage_iReg__GEN_1111; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_25 = iwb_stage_iReg_log_reg_8 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1113 = iwb_stage_iReg__T_25 ? 6'h8 : iwb_stage_iReg__GEN_1112; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_26 = iwb_stage_iReg_log_reg_7 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1114 = iwb_stage_iReg__T_26 ? 6'h7 : iwb_stage_iReg__GEN_1113; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_27 = iwb_stage_iReg_log_reg_6 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1115 = iwb_stage_iReg__T_27 ? 6'h6 : iwb_stage_iReg__GEN_1114; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_28 = iwb_stage_iReg_log_reg_5 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1116 = iwb_stage_iReg__T_28 ? 6'h5 : iwb_stage_iReg__GEN_1115; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_29 = iwb_stage_iReg_log_reg_4 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1117 = iwb_stage_iReg__T_29 ? 6'h4 : iwb_stage_iReg__GEN_1116; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_30 = iwb_stage_iReg_log_reg_3 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1118 = iwb_stage_iReg__T_30 ? 6'h3 : iwb_stage_iReg__GEN_1117; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_31 = iwb_stage_iReg_log_reg_2 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1119 = iwb_stage_iReg__T_31 ? 6'h2 : iwb_stage_iReg__GEN_1118; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_32 = iwb_stage_iReg_log_reg_1 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1120 = iwb_stage_iReg__T_32 ? 6'h1 : iwb_stage_iReg__GEN_1119; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_33 = iwb_stage_iReg_log_reg_0 == 2'h0; // @[Regfiles.scala 150:36]
  wire [5:0] iwb_stage_iReg__GEN_1121 = iwb_stage_iReg__T_33 ? 6'h0 : iwb_stage_iReg__GEN_1120; // @[Regfiles.scala 150:{46,62}]
  wire  iwb_stage_iReg__T_34 = iwb_stage_iReg_io_rename_0_req_ready & iwb_stage_iReg_io_rename_0_req_valid; // @[Decoupled.scala 52:35]
  wire [1:0] iwb_stage_iReg__GEN_1123 = 6'h1 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1124 = 6'h2 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_1123; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1125 = 6'h3 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_1124; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1126 = 6'h4 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_1125; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1127 = 6'h5 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_1126; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1128 = 6'h6 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_1127; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1129 = 6'h7 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_1128; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1130 = 6'h8 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_1129; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1131 = 6'h9 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_1130; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1132 = 6'ha == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_1131; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1133 = 6'hb == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_1132; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1134 = 6'hc == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_1133; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1135 = 6'hd == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_1134; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1136 = 6'he == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_1135; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1137 = 6'hf == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_1136; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1138 = 6'h10 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_1137; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1139 = 6'h11 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_1138; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1140 = 6'h12 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_1139; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1141 = 6'h13 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_1140; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1142 = 6'h14 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_1141; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1143 = 6'h15 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_1142; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1144 = 6'h16 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_1143; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1145 = 6'h17 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_1144; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1146 = 6'h18 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_1145; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1147 = 6'h19 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_1146; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1148 = 6'h1a == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_1147; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1149 = 6'h1b == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_1148; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1150 = 6'h1c == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_1149; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1151 = 6'h1d == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_1150; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1152 = 6'h1e == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_1151; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1153 = 6'h1f == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_1152; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1154 = 6'h20 == iwb_stage_iReg__GEN_1121 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_1153; // @[Regfiles.scala 160:{34,34}]
  wire [1:0] iwb_stage_iReg__GEN_1155 = 6'h21 == iwb_stage_iReg__GEN_1121 ? 2'h3 : iwb_stage_iReg__GEN_1154; // @[Regfiles.scala 160:{34,34}]
  wire  iwb_stage_iReg__T_35 = iwb_stage_iReg__GEN_1155 == 2'h0; // @[Regfiles.scala 160:34]
  wire  iwb_stage_iReg__T_37 = ~iwb_stage_iReg_reset; // @[Regfiles.scala 160:13]
  wire  iwb_stage_iReg__T_38 = ~iwb_stage_iReg__T_35; // @[Regfiles.scala 160:13]
  wire [1:0] iwb_stage_iReg__GEN_1156 = 6'h0 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1157 = 6'h1 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_1; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1158 = 6'h2 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_2; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1159 = 6'h3 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_3; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1160 = 6'h4 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_4; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1161 = 6'h5 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_5; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1162 = 6'h6 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_6; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1163 = 6'h7 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_7; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1164 = 6'h8 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_8; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1165 = 6'h9 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_9; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1166 = 6'ha == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_10; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1167 = 6'hb == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_11; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1168 = 6'hc == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_12; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1169 = 6'hd == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_13; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1170 = 6'he == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_14; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1171 = 6'hf == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_15; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1172 = 6'h10 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_16; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1173 = 6'h11 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_17; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1174 = 6'h12 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_18; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1175 = 6'h13 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_19; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1176 = 6'h14 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_20; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1177 = 6'h15 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_21; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1178 = 6'h16 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_22; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1179 = 6'h17 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_23; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1180 = 6'h18 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_24; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1181 = 6'h19 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_25; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1182 = 6'h1a == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_26; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1183 = 6'h1b == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_27; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1184 = 6'h1c == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_28; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1185 = 6'h1d == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_29; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1186 = 6'h1e == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_30; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1187 = 6'h1f == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_31; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1188 = 6'h20 == iwb_stage_iReg__GEN_1121 ? 2'h1 : iwb_stage_iReg_log_reg_32; // @[Regfiles.scala 101:12 161:{30,30}]
  wire [1:0] iwb_stage_iReg__GEN_1221 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1156 : iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1222 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1157 : iwb_stage_iReg_log_reg_1; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1223 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1158 : iwb_stage_iReg_log_reg_2; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1224 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1159 : iwb_stage_iReg_log_reg_3; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1225 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1160 : iwb_stage_iReg_log_reg_4; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1226 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1161 : iwb_stage_iReg_log_reg_5; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1227 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1162 : iwb_stage_iReg_log_reg_6; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1228 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1163 : iwb_stage_iReg_log_reg_7; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1229 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1164 : iwb_stage_iReg_log_reg_8; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1230 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1165 : iwb_stage_iReg_log_reg_9; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1231 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1166 : iwb_stage_iReg_log_reg_10; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1232 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1167 : iwb_stage_iReg_log_reg_11; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1233 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1168 : iwb_stage_iReg_log_reg_12; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1234 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1169 : iwb_stage_iReg_log_reg_13; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1235 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1170 : iwb_stage_iReg_log_reg_14; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1236 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1171 : iwb_stage_iReg_log_reg_15; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1237 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1172 : iwb_stage_iReg_log_reg_16; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1238 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1173 : iwb_stage_iReg_log_reg_17; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1239 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1174 : iwb_stage_iReg_log_reg_18; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1240 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1175 : iwb_stage_iReg_log_reg_19; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1241 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1176 : iwb_stage_iReg_log_reg_20; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1242 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1177 : iwb_stage_iReg_log_reg_21; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1243 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1178 : iwb_stage_iReg_log_reg_22; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1244 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1179 : iwb_stage_iReg_log_reg_23; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1245 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1180 : iwb_stage_iReg_log_reg_24; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1246 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1181 : iwb_stage_iReg_log_reg_25; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1247 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1182 : iwb_stage_iReg_log_reg_26; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1248 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1183 : iwb_stage_iReg_log_reg_27; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1249 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1184 : iwb_stage_iReg_log_reg_28; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1250 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1185 : iwb_stage_iReg_log_reg_29; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1251 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1186 : iwb_stage_iReg_log_reg_30; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1252 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1187 : iwb_stage_iReg_log_reg_31; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__GEN_1253 = iwb_stage_iReg__T_34 ? iwb_stage_iReg__GEN_1188 : iwb_stage_iReg_log_reg_32; // @[Regfiles.scala 101:12 158:35]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_34 = iwb_stage_iReg__T_33 + iwb_stage_iReg__T_32; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_36 = iwb_stage_iReg__T_31 + iwb_stage_iReg__T_30; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_38 = iwb_stage_iReg__io_rename_0_req_ready_T_34 +
    iwb_stage_iReg__io_rename_0_req_ready_T_36; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_40 = iwb_stage_iReg__T_29 + iwb_stage_iReg__T_28; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_42 = iwb_stage_iReg__T_27 + iwb_stage_iReg__T_26; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_44 = iwb_stage_iReg__io_rename_0_req_ready_T_40 +
    iwb_stage_iReg__io_rename_0_req_ready_T_42; // @[Regfiles.scala 165:40]
  wire [3:0] iwb_stage_iReg__io_rename_0_req_ready_T_46 = iwb_stage_iReg__io_rename_0_req_ready_T_38 +
    iwb_stage_iReg__io_rename_0_req_ready_T_44; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_48 = iwb_stage_iReg__T_25 + iwb_stage_iReg__T_24; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_50 = iwb_stage_iReg__T_23 + iwb_stage_iReg__T_22; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_52 = iwb_stage_iReg__io_rename_0_req_ready_T_48 +
    iwb_stage_iReg__io_rename_0_req_ready_T_50; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_54 = iwb_stage_iReg__T_21 + iwb_stage_iReg__T_20; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_56 = iwb_stage_iReg__T_18 + iwb_stage_iReg__T_17; // @[Regfiles.scala 165:40]
  wire [1:0] _GEN_456 = {{1'd0}, iwb_stage_iReg__T_19}; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_58 = _GEN_456 + iwb_stage_iReg__io_rename_0_req_ready_T_56; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_59 = iwb_stage_iReg__io_rename_0_req_ready_T_58[1:0]; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_60 = iwb_stage_iReg__io_rename_0_req_ready_T_54 +
    iwb_stage_iReg__io_rename_0_req_ready_T_59; // @[Regfiles.scala 165:40]
  wire [3:0] iwb_stage_iReg__io_rename_0_req_ready_T_62 = iwb_stage_iReg__io_rename_0_req_ready_T_52 +
    iwb_stage_iReg__io_rename_0_req_ready_T_60; // @[Regfiles.scala 165:40]
  wire [4:0] iwb_stage_iReg__io_rename_0_req_ready_T_64 = iwb_stage_iReg__io_rename_0_req_ready_T_46 +
    iwb_stage_iReg__io_rename_0_req_ready_T_62; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_66 = iwb_stage_iReg__T_16 + iwb_stage_iReg__T_15; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_68 = iwb_stage_iReg__T_14 + iwb_stage_iReg__T_13; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_70 = iwb_stage_iReg__io_rename_0_req_ready_T_66 +
    iwb_stage_iReg__io_rename_0_req_ready_T_68; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_72 = iwb_stage_iReg__T_12 + iwb_stage_iReg__T_11; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_74 = iwb_stage_iReg__T_10 + iwb_stage_iReg__T_9; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_76 = iwb_stage_iReg__io_rename_0_req_ready_T_72 +
    iwb_stage_iReg__io_rename_0_req_ready_T_74; // @[Regfiles.scala 165:40]
  wire [3:0] iwb_stage_iReg__io_rename_0_req_ready_T_78 = iwb_stage_iReg__io_rename_0_req_ready_T_70 +
    iwb_stage_iReg__io_rename_0_req_ready_T_76; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_80 = iwb_stage_iReg__T_8 + iwb_stage_iReg__T_7; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_82 = iwb_stage_iReg__T_6 + iwb_stage_iReg__T_5; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_84 = iwb_stage_iReg__io_rename_0_req_ready_T_80 +
    iwb_stage_iReg__io_rename_0_req_ready_T_82; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_86 = iwb_stage_iReg__T_4 + iwb_stage_iReg__T_3; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_88 = {{1'd0}, iwb_stage_iReg__T_1}; // @[Regfiles.scala 165:40]
  wire [1:0] _GEN_457 = {{1'd0}, iwb_stage_iReg__T_2}; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_90 = _GEN_457 + iwb_stage_iReg__io_rename_0_req_ready_T_88; // @[Regfiles.scala 165:40]
  wire [1:0] iwb_stage_iReg__io_rename_0_req_ready_T_91 = iwb_stage_iReg__io_rename_0_req_ready_T_90[1:0]; // @[Regfiles.scala 165:40]
  wire [2:0] iwb_stage_iReg__io_rename_0_req_ready_T_92 = iwb_stage_iReg__io_rename_0_req_ready_T_86 +
    iwb_stage_iReg__io_rename_0_req_ready_T_91; // @[Regfiles.scala 165:40]
  wire [3:0] iwb_stage_iReg__io_rename_0_req_ready_T_94 = iwb_stage_iReg__io_rename_0_req_ready_T_84 +
    iwb_stage_iReg__io_rename_0_req_ready_T_92; // @[Regfiles.scala 165:40]
  wire [4:0] iwb_stage_iReg__io_rename_0_req_ready_T_96 = iwb_stage_iReg__io_rename_0_req_ready_T_78 +
    iwb_stage_iReg__io_rename_0_req_ready_T_94; // @[Regfiles.scala 165:40]
  wire [5:0] iwb_stage_iReg__io_rename_0_req_ready_T_98 = iwb_stage_iReg__io_rename_0_req_ready_T_64 +
    iwb_stage_iReg__io_rename_0_req_ready_T_96; // @[Regfiles.scala 165:40]
  wire  iwb_stage_iReg__T_39 = iwb_stage_iReg_io_commit_0_is_MisPredict | iwb_stage_iReg_io_commit_0_is_abort; // @[Regfiles.scala 172:39]
  wire  iwb_stage_iReg__T_40 = 5'h0 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_41 = iwb_stage_iReg__T_40 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_42 = 5'h1 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_43 = iwb_stage_iReg__T_42 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_44 = 5'h2 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_45 = iwb_stage_iReg__T_44 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_46 = 5'h3 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_47 = iwb_stage_iReg__T_46 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_48 = 5'h4 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_49 = iwb_stage_iReg__T_48 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_50 = 5'h5 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_51 = iwb_stage_iReg__T_50 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_52 = 5'h6 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_53 = iwb_stage_iReg__T_52 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_54 = 5'h7 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_55 = iwb_stage_iReg__T_54 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_56 = 5'h8 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_57 = iwb_stage_iReg__T_56 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_58 = 5'h9 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_59 = iwb_stage_iReg__T_58 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_60 = 5'ha == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_61 = iwb_stage_iReg__T_60 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_62 = 5'hb == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_63 = iwb_stage_iReg__T_62 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_64 = 5'hc == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_65 = iwb_stage_iReg__T_64 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_66 = 5'hd == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_67 = iwb_stage_iReg__T_66 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_68 = 5'he == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_69 = iwb_stage_iReg__T_68 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_70 = 5'hf == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_71 = iwb_stage_iReg__T_70 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_72 = 5'h10 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_73 = iwb_stage_iReg__T_72 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_74 = 5'h11 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_75 = iwb_stage_iReg__T_74 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_76 = 5'h12 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_77 = iwb_stage_iReg__T_76 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_78 = 5'h13 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_79 = iwb_stage_iReg__T_78 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_80 = 5'h14 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_81 = iwb_stage_iReg__T_80 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_82 = 5'h15 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_83 = iwb_stage_iReg__T_82 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_84 = 5'h16 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_85 = iwb_stage_iReg__T_84 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_86 = 5'h17 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_87 = iwb_stage_iReg__T_86 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_88 = 5'h18 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_89 = iwb_stage_iReg__T_88 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_90 = 5'h19 == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_91 = iwb_stage_iReg__T_90 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_92 = 5'h1a == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_93 = iwb_stage_iReg__T_92 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_94 = 5'h1b == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_95 = iwb_stage_iReg__T_94 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_96 = 5'h1c == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_97 = iwb_stage_iReg__T_96 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_98 = 5'h1d == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_99 = iwb_stage_iReg__T_98 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_100 = 5'h1e == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_101 = iwb_stage_iReg__T_100 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  wire  iwb_stage_iReg__T_102 = 5'h1f == iwb_stage_iReg_io_commit_0_raw; // @[Regfiles.scala 180:19]
  wire  iwb_stage_iReg__T_103 = iwb_stage_iReg__T_102 & iwb_stage_iReg_io_commit_0_is_MisPredict; // @[Regfiles.scala 180:30]
  reg  iwb_stage_iReg_io_rgRsp_0_valid_REG; // @[Regfiles.scala 191:36]
  reg [5:0] iwb_stage_iReg_io_rgRsp_0_bits_phy_r; // @[Reg.scala 19:16]
  reg [63:0] iwb_stage_iReg_io_rgRsp_0_bits_op_r; // @[Reg.scala 19:16]
  wire [63:0] iwb_stage_iReg__GEN_1352 = 6'h1 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_1 :
    iwb_stage_iReg_files_reg_0; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1353 = 6'h2 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_2 :
    iwb_stage_iReg__GEN_1352; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1354 = 6'h3 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_3 :
    iwb_stage_iReg__GEN_1353; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1355 = 6'h4 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_4 :
    iwb_stage_iReg__GEN_1354; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1356 = 6'h5 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_5 :
    iwb_stage_iReg__GEN_1355; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1357 = 6'h6 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_6 :
    iwb_stage_iReg__GEN_1356; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1358 = 6'h7 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_7 :
    iwb_stage_iReg__GEN_1357; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1359 = 6'h8 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_8 :
    iwb_stage_iReg__GEN_1358; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1360 = 6'h9 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_9 :
    iwb_stage_iReg__GEN_1359; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1361 = 6'ha == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_10 :
    iwb_stage_iReg__GEN_1360; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1362 = 6'hb == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_11 :
    iwb_stage_iReg__GEN_1361; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1363 = 6'hc == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_12 :
    iwb_stage_iReg__GEN_1362; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1364 = 6'hd == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_13 :
    iwb_stage_iReg__GEN_1363; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1365 = 6'he == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_14 :
    iwb_stage_iReg__GEN_1364; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1366 = 6'hf == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_15 :
    iwb_stage_iReg__GEN_1365; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1367 = 6'h10 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_16 :
    iwb_stage_iReg__GEN_1366; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1368 = 6'h11 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_17 :
    iwb_stage_iReg__GEN_1367; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1369 = 6'h12 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_18 :
    iwb_stage_iReg__GEN_1368; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1370 = 6'h13 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_19 :
    iwb_stage_iReg__GEN_1369; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1371 = 6'h14 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_20 :
    iwb_stage_iReg__GEN_1370; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1372 = 6'h15 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_21 :
    iwb_stage_iReg__GEN_1371; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1373 = 6'h16 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_22 :
    iwb_stage_iReg__GEN_1372; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1374 = 6'h17 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_23 :
    iwb_stage_iReg__GEN_1373; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1375 = 6'h18 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_24 :
    iwb_stage_iReg__GEN_1374; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1376 = 6'h19 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_25 :
    iwb_stage_iReg__GEN_1375; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1377 = 6'h1a == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_26 :
    iwb_stage_iReg__GEN_1376; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1378 = 6'h1b == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_27 :
    iwb_stage_iReg__GEN_1377; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1379 = 6'h1c == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_28 :
    iwb_stage_iReg__GEN_1378; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1380 = 6'h1d == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_29 :
    iwb_stage_iReg__GEN_1379; // @[Reg.scala 20:{22,22}]
  wire [63:0] iwb_stage_iReg__GEN_1381 = 6'h1e == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_files_reg_30 :
    iwb_stage_iReg__GEN_1380; // @[Reg.scala 20:{22,22}]
  wire [1:0] iwb_stage_iReg__GEN_1387 = 6'h1 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1388 = 6'h2 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_1387; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1389 = 6'h3 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_1388; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1390 = 6'h4 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_1389; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1391 = 6'h5 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_1390; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1392 = 6'h6 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_1391; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1393 = 6'h7 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_1392; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1394 = 6'h8 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_1393; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1395 = 6'h9 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_1394; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1396 = 6'ha == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_1395; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1397 = 6'hb == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_1396; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1398 = 6'hc == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_1397; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1399 = 6'hd == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_1398; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1400 = 6'he == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_1399; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1401 = 6'hf == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_1400; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1402 = 6'h10 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_1401; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1403 = 6'h11 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_1402; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1404 = 6'h12 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_1403; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1405 = 6'h13 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_1404; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1406 = 6'h14 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_1405; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1407 = 6'h15 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_1406; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1408 = 6'h16 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_1407; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1409 = 6'h17 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_1408; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1410 = 6'h18 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_1409; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1411 = 6'h19 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_1410; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1412 = 6'h1a == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_1411; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1413 = 6'h1b == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_1412; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1414 = 6'h1c == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_1413; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1415 = 6'h1d == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_1414; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1416 = 6'h1e == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_1415; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1417 = 6'h1f == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_1416; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1418 = 6'h20 == iwb_stage_iReg_io_rgReq_0_bits ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_1417; // @[Regfiles.scala 194:{64,64}]
  wire [1:0] iwb_stage_iReg__GEN_1419 = 6'h21 == iwb_stage_iReg_io_rgReq_0_bits ? 2'h3 : iwb_stage_iReg__GEN_1418; // @[Regfiles.scala 194:{64,64}]
  wire  iwb_stage_iReg__T_104 = iwb_stage_iReg__GEN_1419 == 2'h3; // @[Regfiles.scala 194:64]
  wire  iwb_stage_iReg__T_107 = ~iwb_stage_iReg__T_104; // @[Regfiles.scala 194:40]
  wire  iwb_stage_iReg__T_108 = iwb_stage_iReg_io_exe_writeBack_0_ready & iwb_stage_iReg_io_exe_writeBack_0_valid; // @[Decoupled.scala 52:35]
  wire [1:0] iwb_stage_iReg__GEN_1421 = 6'h1 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1422 = 6'h2 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_1421; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1423 = 6'h3 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_1422; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1424 = 6'h4 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_1423; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1425 = 6'h5 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_1424; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1426 = 6'h6 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_1425; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1427 = 6'h7 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_1426; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1428 = 6'h8 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_1427; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1429 = 6'h9 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_1428; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1430 = 6'ha == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_10
     : iwb_stage_iReg__GEN_1429; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1431 = 6'hb == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_11
     : iwb_stage_iReg__GEN_1430; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1432 = 6'hc == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_12
     : iwb_stage_iReg__GEN_1431; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1433 = 6'hd == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_13
     : iwb_stage_iReg__GEN_1432; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1434 = 6'he == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_14
     : iwb_stage_iReg__GEN_1433; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1435 = 6'hf == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_15
     : iwb_stage_iReg__GEN_1434; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1436 = 6'h10 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_16
     : iwb_stage_iReg__GEN_1435; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1437 = 6'h11 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_17
     : iwb_stage_iReg__GEN_1436; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1438 = 6'h12 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_18
     : iwb_stage_iReg__GEN_1437; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1439 = 6'h13 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_19
     : iwb_stage_iReg__GEN_1438; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1440 = 6'h14 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_20
     : iwb_stage_iReg__GEN_1439; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1441 = 6'h15 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_21
     : iwb_stage_iReg__GEN_1440; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1442 = 6'h16 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_22
     : iwb_stage_iReg__GEN_1441; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1443 = 6'h17 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_23
     : iwb_stage_iReg__GEN_1442; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1444 = 6'h18 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_24
     : iwb_stage_iReg__GEN_1443; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1445 = 6'h19 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_25
     : iwb_stage_iReg__GEN_1444; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1446 = 6'h1a == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_26
     : iwb_stage_iReg__GEN_1445; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1447 = 6'h1b == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_27
     : iwb_stage_iReg__GEN_1446; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1448 = 6'h1c == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_28
     : iwb_stage_iReg__GEN_1447; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1449 = 6'h1d == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_29
     : iwb_stage_iReg__GEN_1448; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1450 = 6'h1e == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_30
     : iwb_stage_iReg__GEN_1449; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1451 = 6'h1f == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_31
     : iwb_stage_iReg__GEN_1450; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1452 = 6'h20 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? iwb_stage_iReg_log_reg_32
     : iwb_stage_iReg__GEN_1451; // @[Regfiles.scala 203:{24,24}]
  wire [1:0] iwb_stage_iReg__GEN_1453 = 6'h21 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1452; // @[Regfiles.scala 203:{24,24}]
  wire  iwb_stage_iReg__T_109 = iwb_stage_iReg__GEN_1453 == 2'h1; // @[Regfiles.scala 203:24]
  wire  iwb_stage_iReg__T_112 = ~iwb_stage_iReg__T_109; // @[Regfiles.scala 203:13]
  wire [1:0] iwb_stage_iReg__GEN_1454 = 6'h0 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1221; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1455 = 6'h1 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1222; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1456 = 6'h2 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1223; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1457 = 6'h3 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1224; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1458 = 6'h4 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1225; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1459 = 6'h5 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1226; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1460 = 6'h6 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1227; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1461 = 6'h7 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1228; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1462 = 6'h8 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1229; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1463 = 6'h9 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1230; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1464 = 6'ha == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1231; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1465 = 6'hb == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1232; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1466 = 6'hc == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1233; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1467 = 6'hd == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1234; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1468 = 6'he == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1235; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1469 = 6'hf == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1236; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1470 = 6'h10 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1237; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1471 = 6'h11 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1238; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1472 = 6'h12 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1239; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1473 = 6'h13 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1240; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1474 = 6'h14 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1241; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1475 = 6'h15 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1242; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1476 = 6'h16 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1243; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1477 = 6'h17 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1244; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1478 = 6'h18 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1245; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1479 = 6'h19 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1246; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1480 = 6'h1a == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1247; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1481 = 6'h1b == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1248; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1482 = 6'h1c == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1249; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1483 = 6'h1d == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1250; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1484 = 6'h1e == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1251; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1485 = 6'h1f == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1252; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1486 = 6'h20 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 ? 2'h3 :
    iwb_stage_iReg__GEN_1253; // @[Regfiles.scala 204:{20,20}]
  wire [1:0] iwb_stage_iReg__GEN_1520 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1454 : iwb_stage_iReg__GEN_1221; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1521 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1455 : iwb_stage_iReg__GEN_1222; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1522 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1456 : iwb_stage_iReg__GEN_1223; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1523 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1457 : iwb_stage_iReg__GEN_1224; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1524 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1458 : iwb_stage_iReg__GEN_1225; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1525 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1459 : iwb_stage_iReg__GEN_1226; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1526 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1460 : iwb_stage_iReg__GEN_1227; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1527 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1461 : iwb_stage_iReg__GEN_1228; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1528 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1462 : iwb_stage_iReg__GEN_1229; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1529 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1463 : iwb_stage_iReg__GEN_1230; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1530 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1464 : iwb_stage_iReg__GEN_1231; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1531 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1465 : iwb_stage_iReg__GEN_1232; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1532 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1466 : iwb_stage_iReg__GEN_1233; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1533 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1467 : iwb_stage_iReg__GEN_1234; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1534 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1468 : iwb_stage_iReg__GEN_1235; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1535 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1469 : iwb_stage_iReg__GEN_1236; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1536 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1470 : iwb_stage_iReg__GEN_1237; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1537 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1471 : iwb_stage_iReg__GEN_1238; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1538 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1472 : iwb_stage_iReg__GEN_1239; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1539 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1473 : iwb_stage_iReg__GEN_1240; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1540 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1474 : iwb_stage_iReg__GEN_1241; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1541 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1475 : iwb_stage_iReg__GEN_1242; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1542 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1476 : iwb_stage_iReg__GEN_1243; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1543 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1477 : iwb_stage_iReg__GEN_1244; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1544 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1478 : iwb_stage_iReg__GEN_1245; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1545 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1479 : iwb_stage_iReg__GEN_1246; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1546 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1480 : iwb_stage_iReg__GEN_1247; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1547 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1481 : iwb_stage_iReg__GEN_1248; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1548 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1482 : iwb_stage_iReg__GEN_1249; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1549 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1483 : iwb_stage_iReg__GEN_1250; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1550 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1484 : iwb_stage_iReg__GEN_1251; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1551 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1485 : iwb_stage_iReg__GEN_1252; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1552 = iwb_stage_iReg__T_108 ? iwb_stage_iReg__GEN_1486 : iwb_stage_iReg__GEN_1253; // @[Regfiles.scala 201:38]
  wire [1:0] iwb_stage_iReg__GEN_1587 = 6'h1 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1588 = 6'h2 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_1587; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1589 = 6'h3 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_1588; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1590 = 6'h4 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_1589; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1591 = 6'h5 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_1590; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1592 = 6'h6 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_1591; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1593 = 6'h7 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_1592; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1594 = 6'h8 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_1593; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1595 = 6'h9 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_1594; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1596 = 6'ha == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_1595; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1597 = 6'hb == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_1596; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1598 = 6'hc == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_1597; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1599 = 6'hd == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_1598; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1600 = 6'he == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_1599; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1601 = 6'hf == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_1600; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1602 = 6'h10 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_1601; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1603 = 6'h11 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_1602; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1604 = 6'h12 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_1603; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1605 = 6'h13 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_1604; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1606 = 6'h14 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_1605; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1607 = 6'h15 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_1606; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1608 = 6'h16 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_1607; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1609 = 6'h17 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_1608; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1610 = 6'h18 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_1609; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1611 = 6'h19 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_1610; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1612 = 6'h1a == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_1611; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1613 = 6'h1b == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_1612; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1614 = 6'h1c == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_1613; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1615 = 6'h1d == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_1614; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1616 = 6'h1e == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_1615; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1617 = 6'h1f == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_1616; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1618 = 6'h20 == iwb_stage_iReg_io_commit_0_phy ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_1617; // @[Regfiles.scala 219:{46,46}]
  wire [1:0] iwb_stage_iReg__GEN_1619 = 6'h21 == iwb_stage_iReg_io_commit_0_phy ? 2'h3 : iwb_stage_iReg__GEN_1618; // @[Regfiles.scala 219:{46,46}]
  wire  iwb_stage_iReg__log_reg_0_T = iwb_stage_iReg_archit_ptr_0 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h0; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_0_T_33 = iwb_stage_iReg__log_reg_0_T | iwb_stage_iReg__log_reg_0_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_34 = iwb_stage_iReg__log_reg_0_T_33 | iwb_stage_iReg__log_reg_0_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_35 = iwb_stage_iReg__log_reg_0_T_34 | iwb_stage_iReg__log_reg_0_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_36 = iwb_stage_iReg__log_reg_0_T_35 | iwb_stage_iReg__log_reg_0_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_37 = iwb_stage_iReg__log_reg_0_T_36 | iwb_stage_iReg__log_reg_0_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_38 = iwb_stage_iReg__log_reg_0_T_37 | iwb_stage_iReg__log_reg_0_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_39 = iwb_stage_iReg__log_reg_0_T_38 | iwb_stage_iReg__log_reg_0_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_40 = iwb_stage_iReg__log_reg_0_T_39 | iwb_stage_iReg__log_reg_0_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_41 = iwb_stage_iReg__log_reg_0_T_40 | iwb_stage_iReg__log_reg_0_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_42 = iwb_stage_iReg__log_reg_0_T_41 | iwb_stage_iReg__log_reg_0_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_43 = iwb_stage_iReg__log_reg_0_T_42 | iwb_stage_iReg__log_reg_0_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_44 = iwb_stage_iReg__log_reg_0_T_43 | iwb_stage_iReg__log_reg_0_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_45 = iwb_stage_iReg__log_reg_0_T_44 | iwb_stage_iReg__log_reg_0_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_46 = iwb_stage_iReg__log_reg_0_T_45 | iwb_stage_iReg__log_reg_0_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_47 = iwb_stage_iReg__log_reg_0_T_46 | iwb_stage_iReg__log_reg_0_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_48 = iwb_stage_iReg__log_reg_0_T_47 | iwb_stage_iReg__log_reg_0_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_49 = iwb_stage_iReg__log_reg_0_T_48 | iwb_stage_iReg__log_reg_0_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_50 = iwb_stage_iReg__log_reg_0_T_49 | iwb_stage_iReg__log_reg_0_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_51 = iwb_stage_iReg__log_reg_0_T_50 | iwb_stage_iReg__log_reg_0_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_52 = iwb_stage_iReg__log_reg_0_T_51 | iwb_stage_iReg__log_reg_0_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_53 = iwb_stage_iReg__log_reg_0_T_52 | iwb_stage_iReg__log_reg_0_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_54 = iwb_stage_iReg__log_reg_0_T_53 | iwb_stage_iReg__log_reg_0_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_55 = iwb_stage_iReg__log_reg_0_T_54 | iwb_stage_iReg__log_reg_0_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_56 = iwb_stage_iReg__log_reg_0_T_55 | iwb_stage_iReg__log_reg_0_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_57 = iwb_stage_iReg__log_reg_0_T_56 | iwb_stage_iReg__log_reg_0_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_58 = iwb_stage_iReg__log_reg_0_T_57 | iwb_stage_iReg__log_reg_0_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_59 = iwb_stage_iReg__log_reg_0_T_58 | iwb_stage_iReg__log_reg_0_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_60 = iwb_stage_iReg__log_reg_0_T_59 | iwb_stage_iReg__log_reg_0_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_61 = iwb_stage_iReg__log_reg_0_T_60 | iwb_stage_iReg__log_reg_0_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_62 = iwb_stage_iReg__log_reg_0_T_61 | iwb_stage_iReg__log_reg_0_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_0_T_63 = iwb_stage_iReg__log_reg_0_T_62 | iwb_stage_iReg__log_reg_0_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_0_T_64 = iwb_stage_iReg__log_reg_0_T_63 ? iwb_stage_iReg_log_reg_0 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_1_T = iwb_stage_iReg_archit_ptr_0 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h1; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_1_T_33 = iwb_stage_iReg__log_reg_1_T | iwb_stage_iReg__log_reg_1_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_34 = iwb_stage_iReg__log_reg_1_T_33 | iwb_stage_iReg__log_reg_1_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_35 = iwb_stage_iReg__log_reg_1_T_34 | iwb_stage_iReg__log_reg_1_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_36 = iwb_stage_iReg__log_reg_1_T_35 | iwb_stage_iReg__log_reg_1_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_37 = iwb_stage_iReg__log_reg_1_T_36 | iwb_stage_iReg__log_reg_1_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_38 = iwb_stage_iReg__log_reg_1_T_37 | iwb_stage_iReg__log_reg_1_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_39 = iwb_stage_iReg__log_reg_1_T_38 | iwb_stage_iReg__log_reg_1_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_40 = iwb_stage_iReg__log_reg_1_T_39 | iwb_stage_iReg__log_reg_1_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_41 = iwb_stage_iReg__log_reg_1_T_40 | iwb_stage_iReg__log_reg_1_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_42 = iwb_stage_iReg__log_reg_1_T_41 | iwb_stage_iReg__log_reg_1_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_43 = iwb_stage_iReg__log_reg_1_T_42 | iwb_stage_iReg__log_reg_1_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_44 = iwb_stage_iReg__log_reg_1_T_43 | iwb_stage_iReg__log_reg_1_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_45 = iwb_stage_iReg__log_reg_1_T_44 | iwb_stage_iReg__log_reg_1_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_46 = iwb_stage_iReg__log_reg_1_T_45 | iwb_stage_iReg__log_reg_1_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_47 = iwb_stage_iReg__log_reg_1_T_46 | iwb_stage_iReg__log_reg_1_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_48 = iwb_stage_iReg__log_reg_1_T_47 | iwb_stage_iReg__log_reg_1_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_49 = iwb_stage_iReg__log_reg_1_T_48 | iwb_stage_iReg__log_reg_1_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_50 = iwb_stage_iReg__log_reg_1_T_49 | iwb_stage_iReg__log_reg_1_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_51 = iwb_stage_iReg__log_reg_1_T_50 | iwb_stage_iReg__log_reg_1_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_52 = iwb_stage_iReg__log_reg_1_T_51 | iwb_stage_iReg__log_reg_1_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_53 = iwb_stage_iReg__log_reg_1_T_52 | iwb_stage_iReg__log_reg_1_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_54 = iwb_stage_iReg__log_reg_1_T_53 | iwb_stage_iReg__log_reg_1_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_55 = iwb_stage_iReg__log_reg_1_T_54 | iwb_stage_iReg__log_reg_1_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_56 = iwb_stage_iReg__log_reg_1_T_55 | iwb_stage_iReg__log_reg_1_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_57 = iwb_stage_iReg__log_reg_1_T_56 | iwb_stage_iReg__log_reg_1_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_58 = iwb_stage_iReg__log_reg_1_T_57 | iwb_stage_iReg__log_reg_1_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_59 = iwb_stage_iReg__log_reg_1_T_58 | iwb_stage_iReg__log_reg_1_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_60 = iwb_stage_iReg__log_reg_1_T_59 | iwb_stage_iReg__log_reg_1_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_61 = iwb_stage_iReg__log_reg_1_T_60 | iwb_stage_iReg__log_reg_1_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_62 = iwb_stage_iReg__log_reg_1_T_61 | iwb_stage_iReg__log_reg_1_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_1_T_63 = iwb_stage_iReg__log_reg_1_T_62 | iwb_stage_iReg__log_reg_1_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_1_T_64 = iwb_stage_iReg__log_reg_1_T_63 ? iwb_stage_iReg_log_reg_1 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_2_T = iwb_stage_iReg_archit_ptr_0 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h2; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_2_T_33 = iwb_stage_iReg__log_reg_2_T | iwb_stage_iReg__log_reg_2_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_34 = iwb_stage_iReg__log_reg_2_T_33 | iwb_stage_iReg__log_reg_2_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_35 = iwb_stage_iReg__log_reg_2_T_34 | iwb_stage_iReg__log_reg_2_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_36 = iwb_stage_iReg__log_reg_2_T_35 | iwb_stage_iReg__log_reg_2_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_37 = iwb_stage_iReg__log_reg_2_T_36 | iwb_stage_iReg__log_reg_2_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_38 = iwb_stage_iReg__log_reg_2_T_37 | iwb_stage_iReg__log_reg_2_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_39 = iwb_stage_iReg__log_reg_2_T_38 | iwb_stage_iReg__log_reg_2_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_40 = iwb_stage_iReg__log_reg_2_T_39 | iwb_stage_iReg__log_reg_2_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_41 = iwb_stage_iReg__log_reg_2_T_40 | iwb_stage_iReg__log_reg_2_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_42 = iwb_stage_iReg__log_reg_2_T_41 | iwb_stage_iReg__log_reg_2_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_43 = iwb_stage_iReg__log_reg_2_T_42 | iwb_stage_iReg__log_reg_2_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_44 = iwb_stage_iReg__log_reg_2_T_43 | iwb_stage_iReg__log_reg_2_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_45 = iwb_stage_iReg__log_reg_2_T_44 | iwb_stage_iReg__log_reg_2_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_46 = iwb_stage_iReg__log_reg_2_T_45 | iwb_stage_iReg__log_reg_2_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_47 = iwb_stage_iReg__log_reg_2_T_46 | iwb_stage_iReg__log_reg_2_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_48 = iwb_stage_iReg__log_reg_2_T_47 | iwb_stage_iReg__log_reg_2_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_49 = iwb_stage_iReg__log_reg_2_T_48 | iwb_stage_iReg__log_reg_2_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_50 = iwb_stage_iReg__log_reg_2_T_49 | iwb_stage_iReg__log_reg_2_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_51 = iwb_stage_iReg__log_reg_2_T_50 | iwb_stage_iReg__log_reg_2_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_52 = iwb_stage_iReg__log_reg_2_T_51 | iwb_stage_iReg__log_reg_2_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_53 = iwb_stage_iReg__log_reg_2_T_52 | iwb_stage_iReg__log_reg_2_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_54 = iwb_stage_iReg__log_reg_2_T_53 | iwb_stage_iReg__log_reg_2_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_55 = iwb_stage_iReg__log_reg_2_T_54 | iwb_stage_iReg__log_reg_2_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_56 = iwb_stage_iReg__log_reg_2_T_55 | iwb_stage_iReg__log_reg_2_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_57 = iwb_stage_iReg__log_reg_2_T_56 | iwb_stage_iReg__log_reg_2_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_58 = iwb_stage_iReg__log_reg_2_T_57 | iwb_stage_iReg__log_reg_2_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_59 = iwb_stage_iReg__log_reg_2_T_58 | iwb_stage_iReg__log_reg_2_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_60 = iwb_stage_iReg__log_reg_2_T_59 | iwb_stage_iReg__log_reg_2_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_61 = iwb_stage_iReg__log_reg_2_T_60 | iwb_stage_iReg__log_reg_2_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_62 = iwb_stage_iReg__log_reg_2_T_61 | iwb_stage_iReg__log_reg_2_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_2_T_63 = iwb_stage_iReg__log_reg_2_T_62 | iwb_stage_iReg__log_reg_2_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_2_T_64 = iwb_stage_iReg__log_reg_2_T_63 ? iwb_stage_iReg_log_reg_2 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_3_T = iwb_stage_iReg_archit_ptr_0 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h3; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_3_T_33 = iwb_stage_iReg__log_reg_3_T | iwb_stage_iReg__log_reg_3_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_34 = iwb_stage_iReg__log_reg_3_T_33 | iwb_stage_iReg__log_reg_3_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_35 = iwb_stage_iReg__log_reg_3_T_34 | iwb_stage_iReg__log_reg_3_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_36 = iwb_stage_iReg__log_reg_3_T_35 | iwb_stage_iReg__log_reg_3_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_37 = iwb_stage_iReg__log_reg_3_T_36 | iwb_stage_iReg__log_reg_3_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_38 = iwb_stage_iReg__log_reg_3_T_37 | iwb_stage_iReg__log_reg_3_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_39 = iwb_stage_iReg__log_reg_3_T_38 | iwb_stage_iReg__log_reg_3_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_40 = iwb_stage_iReg__log_reg_3_T_39 | iwb_stage_iReg__log_reg_3_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_41 = iwb_stage_iReg__log_reg_3_T_40 | iwb_stage_iReg__log_reg_3_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_42 = iwb_stage_iReg__log_reg_3_T_41 | iwb_stage_iReg__log_reg_3_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_43 = iwb_stage_iReg__log_reg_3_T_42 | iwb_stage_iReg__log_reg_3_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_44 = iwb_stage_iReg__log_reg_3_T_43 | iwb_stage_iReg__log_reg_3_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_45 = iwb_stage_iReg__log_reg_3_T_44 | iwb_stage_iReg__log_reg_3_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_46 = iwb_stage_iReg__log_reg_3_T_45 | iwb_stage_iReg__log_reg_3_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_47 = iwb_stage_iReg__log_reg_3_T_46 | iwb_stage_iReg__log_reg_3_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_48 = iwb_stage_iReg__log_reg_3_T_47 | iwb_stage_iReg__log_reg_3_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_49 = iwb_stage_iReg__log_reg_3_T_48 | iwb_stage_iReg__log_reg_3_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_50 = iwb_stage_iReg__log_reg_3_T_49 | iwb_stage_iReg__log_reg_3_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_51 = iwb_stage_iReg__log_reg_3_T_50 | iwb_stage_iReg__log_reg_3_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_52 = iwb_stage_iReg__log_reg_3_T_51 | iwb_stage_iReg__log_reg_3_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_53 = iwb_stage_iReg__log_reg_3_T_52 | iwb_stage_iReg__log_reg_3_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_54 = iwb_stage_iReg__log_reg_3_T_53 | iwb_stage_iReg__log_reg_3_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_55 = iwb_stage_iReg__log_reg_3_T_54 | iwb_stage_iReg__log_reg_3_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_56 = iwb_stage_iReg__log_reg_3_T_55 | iwb_stage_iReg__log_reg_3_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_57 = iwb_stage_iReg__log_reg_3_T_56 | iwb_stage_iReg__log_reg_3_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_58 = iwb_stage_iReg__log_reg_3_T_57 | iwb_stage_iReg__log_reg_3_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_59 = iwb_stage_iReg__log_reg_3_T_58 | iwb_stage_iReg__log_reg_3_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_60 = iwb_stage_iReg__log_reg_3_T_59 | iwb_stage_iReg__log_reg_3_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_61 = iwb_stage_iReg__log_reg_3_T_60 | iwb_stage_iReg__log_reg_3_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_62 = iwb_stage_iReg__log_reg_3_T_61 | iwb_stage_iReg__log_reg_3_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_3_T_63 = iwb_stage_iReg__log_reg_3_T_62 | iwb_stage_iReg__log_reg_3_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_3_T_64 = iwb_stage_iReg__log_reg_3_T_63 ? iwb_stage_iReg_log_reg_3 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_4_T = iwb_stage_iReg_archit_ptr_0 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h4; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_4_T_33 = iwb_stage_iReg__log_reg_4_T | iwb_stage_iReg__log_reg_4_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_34 = iwb_stage_iReg__log_reg_4_T_33 | iwb_stage_iReg__log_reg_4_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_35 = iwb_stage_iReg__log_reg_4_T_34 | iwb_stage_iReg__log_reg_4_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_36 = iwb_stage_iReg__log_reg_4_T_35 | iwb_stage_iReg__log_reg_4_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_37 = iwb_stage_iReg__log_reg_4_T_36 | iwb_stage_iReg__log_reg_4_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_38 = iwb_stage_iReg__log_reg_4_T_37 | iwb_stage_iReg__log_reg_4_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_39 = iwb_stage_iReg__log_reg_4_T_38 | iwb_stage_iReg__log_reg_4_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_40 = iwb_stage_iReg__log_reg_4_T_39 | iwb_stage_iReg__log_reg_4_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_41 = iwb_stage_iReg__log_reg_4_T_40 | iwb_stage_iReg__log_reg_4_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_42 = iwb_stage_iReg__log_reg_4_T_41 | iwb_stage_iReg__log_reg_4_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_43 = iwb_stage_iReg__log_reg_4_T_42 | iwb_stage_iReg__log_reg_4_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_44 = iwb_stage_iReg__log_reg_4_T_43 | iwb_stage_iReg__log_reg_4_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_45 = iwb_stage_iReg__log_reg_4_T_44 | iwb_stage_iReg__log_reg_4_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_46 = iwb_stage_iReg__log_reg_4_T_45 | iwb_stage_iReg__log_reg_4_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_47 = iwb_stage_iReg__log_reg_4_T_46 | iwb_stage_iReg__log_reg_4_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_48 = iwb_stage_iReg__log_reg_4_T_47 | iwb_stage_iReg__log_reg_4_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_49 = iwb_stage_iReg__log_reg_4_T_48 | iwb_stage_iReg__log_reg_4_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_50 = iwb_stage_iReg__log_reg_4_T_49 | iwb_stage_iReg__log_reg_4_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_51 = iwb_stage_iReg__log_reg_4_T_50 | iwb_stage_iReg__log_reg_4_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_52 = iwb_stage_iReg__log_reg_4_T_51 | iwb_stage_iReg__log_reg_4_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_53 = iwb_stage_iReg__log_reg_4_T_52 | iwb_stage_iReg__log_reg_4_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_54 = iwb_stage_iReg__log_reg_4_T_53 | iwb_stage_iReg__log_reg_4_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_55 = iwb_stage_iReg__log_reg_4_T_54 | iwb_stage_iReg__log_reg_4_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_56 = iwb_stage_iReg__log_reg_4_T_55 | iwb_stage_iReg__log_reg_4_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_57 = iwb_stage_iReg__log_reg_4_T_56 | iwb_stage_iReg__log_reg_4_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_58 = iwb_stage_iReg__log_reg_4_T_57 | iwb_stage_iReg__log_reg_4_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_59 = iwb_stage_iReg__log_reg_4_T_58 | iwb_stage_iReg__log_reg_4_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_60 = iwb_stage_iReg__log_reg_4_T_59 | iwb_stage_iReg__log_reg_4_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_61 = iwb_stage_iReg__log_reg_4_T_60 | iwb_stage_iReg__log_reg_4_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_62 = iwb_stage_iReg__log_reg_4_T_61 | iwb_stage_iReg__log_reg_4_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_4_T_63 = iwb_stage_iReg__log_reg_4_T_62 | iwb_stage_iReg__log_reg_4_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_4_T_64 = iwb_stage_iReg__log_reg_4_T_63 ? iwb_stage_iReg_log_reg_4 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_5_T = iwb_stage_iReg_archit_ptr_0 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h5; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_5_T_33 = iwb_stage_iReg__log_reg_5_T | iwb_stage_iReg__log_reg_5_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_34 = iwb_stage_iReg__log_reg_5_T_33 | iwb_stage_iReg__log_reg_5_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_35 = iwb_stage_iReg__log_reg_5_T_34 | iwb_stage_iReg__log_reg_5_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_36 = iwb_stage_iReg__log_reg_5_T_35 | iwb_stage_iReg__log_reg_5_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_37 = iwb_stage_iReg__log_reg_5_T_36 | iwb_stage_iReg__log_reg_5_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_38 = iwb_stage_iReg__log_reg_5_T_37 | iwb_stage_iReg__log_reg_5_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_39 = iwb_stage_iReg__log_reg_5_T_38 | iwb_stage_iReg__log_reg_5_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_40 = iwb_stage_iReg__log_reg_5_T_39 | iwb_stage_iReg__log_reg_5_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_41 = iwb_stage_iReg__log_reg_5_T_40 | iwb_stage_iReg__log_reg_5_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_42 = iwb_stage_iReg__log_reg_5_T_41 | iwb_stage_iReg__log_reg_5_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_43 = iwb_stage_iReg__log_reg_5_T_42 | iwb_stage_iReg__log_reg_5_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_44 = iwb_stage_iReg__log_reg_5_T_43 | iwb_stage_iReg__log_reg_5_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_45 = iwb_stage_iReg__log_reg_5_T_44 | iwb_stage_iReg__log_reg_5_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_46 = iwb_stage_iReg__log_reg_5_T_45 | iwb_stage_iReg__log_reg_5_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_47 = iwb_stage_iReg__log_reg_5_T_46 | iwb_stage_iReg__log_reg_5_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_48 = iwb_stage_iReg__log_reg_5_T_47 | iwb_stage_iReg__log_reg_5_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_49 = iwb_stage_iReg__log_reg_5_T_48 | iwb_stage_iReg__log_reg_5_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_50 = iwb_stage_iReg__log_reg_5_T_49 | iwb_stage_iReg__log_reg_5_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_51 = iwb_stage_iReg__log_reg_5_T_50 | iwb_stage_iReg__log_reg_5_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_52 = iwb_stage_iReg__log_reg_5_T_51 | iwb_stage_iReg__log_reg_5_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_53 = iwb_stage_iReg__log_reg_5_T_52 | iwb_stage_iReg__log_reg_5_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_54 = iwb_stage_iReg__log_reg_5_T_53 | iwb_stage_iReg__log_reg_5_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_55 = iwb_stage_iReg__log_reg_5_T_54 | iwb_stage_iReg__log_reg_5_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_56 = iwb_stage_iReg__log_reg_5_T_55 | iwb_stage_iReg__log_reg_5_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_57 = iwb_stage_iReg__log_reg_5_T_56 | iwb_stage_iReg__log_reg_5_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_58 = iwb_stage_iReg__log_reg_5_T_57 | iwb_stage_iReg__log_reg_5_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_59 = iwb_stage_iReg__log_reg_5_T_58 | iwb_stage_iReg__log_reg_5_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_60 = iwb_stage_iReg__log_reg_5_T_59 | iwb_stage_iReg__log_reg_5_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_61 = iwb_stage_iReg__log_reg_5_T_60 | iwb_stage_iReg__log_reg_5_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_62 = iwb_stage_iReg__log_reg_5_T_61 | iwb_stage_iReg__log_reg_5_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_5_T_63 = iwb_stage_iReg__log_reg_5_T_62 | iwb_stage_iReg__log_reg_5_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_5_T_64 = iwb_stage_iReg__log_reg_5_T_63 ? iwb_stage_iReg_log_reg_5 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_6_T = iwb_stage_iReg_archit_ptr_0 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h6; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_6_T_33 = iwb_stage_iReg__log_reg_6_T | iwb_stage_iReg__log_reg_6_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_34 = iwb_stage_iReg__log_reg_6_T_33 | iwb_stage_iReg__log_reg_6_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_35 = iwb_stage_iReg__log_reg_6_T_34 | iwb_stage_iReg__log_reg_6_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_36 = iwb_stage_iReg__log_reg_6_T_35 | iwb_stage_iReg__log_reg_6_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_37 = iwb_stage_iReg__log_reg_6_T_36 | iwb_stage_iReg__log_reg_6_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_38 = iwb_stage_iReg__log_reg_6_T_37 | iwb_stage_iReg__log_reg_6_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_39 = iwb_stage_iReg__log_reg_6_T_38 | iwb_stage_iReg__log_reg_6_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_40 = iwb_stage_iReg__log_reg_6_T_39 | iwb_stage_iReg__log_reg_6_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_41 = iwb_stage_iReg__log_reg_6_T_40 | iwb_stage_iReg__log_reg_6_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_42 = iwb_stage_iReg__log_reg_6_T_41 | iwb_stage_iReg__log_reg_6_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_43 = iwb_stage_iReg__log_reg_6_T_42 | iwb_stage_iReg__log_reg_6_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_44 = iwb_stage_iReg__log_reg_6_T_43 | iwb_stage_iReg__log_reg_6_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_45 = iwb_stage_iReg__log_reg_6_T_44 | iwb_stage_iReg__log_reg_6_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_46 = iwb_stage_iReg__log_reg_6_T_45 | iwb_stage_iReg__log_reg_6_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_47 = iwb_stage_iReg__log_reg_6_T_46 | iwb_stage_iReg__log_reg_6_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_48 = iwb_stage_iReg__log_reg_6_T_47 | iwb_stage_iReg__log_reg_6_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_49 = iwb_stage_iReg__log_reg_6_T_48 | iwb_stage_iReg__log_reg_6_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_50 = iwb_stage_iReg__log_reg_6_T_49 | iwb_stage_iReg__log_reg_6_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_51 = iwb_stage_iReg__log_reg_6_T_50 | iwb_stage_iReg__log_reg_6_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_52 = iwb_stage_iReg__log_reg_6_T_51 | iwb_stage_iReg__log_reg_6_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_53 = iwb_stage_iReg__log_reg_6_T_52 | iwb_stage_iReg__log_reg_6_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_54 = iwb_stage_iReg__log_reg_6_T_53 | iwb_stage_iReg__log_reg_6_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_55 = iwb_stage_iReg__log_reg_6_T_54 | iwb_stage_iReg__log_reg_6_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_56 = iwb_stage_iReg__log_reg_6_T_55 | iwb_stage_iReg__log_reg_6_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_57 = iwb_stage_iReg__log_reg_6_T_56 | iwb_stage_iReg__log_reg_6_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_58 = iwb_stage_iReg__log_reg_6_T_57 | iwb_stage_iReg__log_reg_6_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_59 = iwb_stage_iReg__log_reg_6_T_58 | iwb_stage_iReg__log_reg_6_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_60 = iwb_stage_iReg__log_reg_6_T_59 | iwb_stage_iReg__log_reg_6_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_61 = iwb_stage_iReg__log_reg_6_T_60 | iwb_stage_iReg__log_reg_6_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_62 = iwb_stage_iReg__log_reg_6_T_61 | iwb_stage_iReg__log_reg_6_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_6_T_63 = iwb_stage_iReg__log_reg_6_T_62 | iwb_stage_iReg__log_reg_6_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_6_T_64 = iwb_stage_iReg__log_reg_6_T_63 ? iwb_stage_iReg_log_reg_6 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_7_T = iwb_stage_iReg_archit_ptr_0 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h7; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_7_T_33 = iwb_stage_iReg__log_reg_7_T | iwb_stage_iReg__log_reg_7_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_34 = iwb_stage_iReg__log_reg_7_T_33 | iwb_stage_iReg__log_reg_7_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_35 = iwb_stage_iReg__log_reg_7_T_34 | iwb_stage_iReg__log_reg_7_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_36 = iwb_stage_iReg__log_reg_7_T_35 | iwb_stage_iReg__log_reg_7_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_37 = iwb_stage_iReg__log_reg_7_T_36 | iwb_stage_iReg__log_reg_7_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_38 = iwb_stage_iReg__log_reg_7_T_37 | iwb_stage_iReg__log_reg_7_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_39 = iwb_stage_iReg__log_reg_7_T_38 | iwb_stage_iReg__log_reg_7_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_40 = iwb_stage_iReg__log_reg_7_T_39 | iwb_stage_iReg__log_reg_7_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_41 = iwb_stage_iReg__log_reg_7_T_40 | iwb_stage_iReg__log_reg_7_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_42 = iwb_stage_iReg__log_reg_7_T_41 | iwb_stage_iReg__log_reg_7_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_43 = iwb_stage_iReg__log_reg_7_T_42 | iwb_stage_iReg__log_reg_7_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_44 = iwb_stage_iReg__log_reg_7_T_43 | iwb_stage_iReg__log_reg_7_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_45 = iwb_stage_iReg__log_reg_7_T_44 | iwb_stage_iReg__log_reg_7_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_46 = iwb_stage_iReg__log_reg_7_T_45 | iwb_stage_iReg__log_reg_7_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_47 = iwb_stage_iReg__log_reg_7_T_46 | iwb_stage_iReg__log_reg_7_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_48 = iwb_stage_iReg__log_reg_7_T_47 | iwb_stage_iReg__log_reg_7_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_49 = iwb_stage_iReg__log_reg_7_T_48 | iwb_stage_iReg__log_reg_7_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_50 = iwb_stage_iReg__log_reg_7_T_49 | iwb_stage_iReg__log_reg_7_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_51 = iwb_stage_iReg__log_reg_7_T_50 | iwb_stage_iReg__log_reg_7_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_52 = iwb_stage_iReg__log_reg_7_T_51 | iwb_stage_iReg__log_reg_7_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_53 = iwb_stage_iReg__log_reg_7_T_52 | iwb_stage_iReg__log_reg_7_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_54 = iwb_stage_iReg__log_reg_7_T_53 | iwb_stage_iReg__log_reg_7_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_55 = iwb_stage_iReg__log_reg_7_T_54 | iwb_stage_iReg__log_reg_7_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_56 = iwb_stage_iReg__log_reg_7_T_55 | iwb_stage_iReg__log_reg_7_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_57 = iwb_stage_iReg__log_reg_7_T_56 | iwb_stage_iReg__log_reg_7_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_58 = iwb_stage_iReg__log_reg_7_T_57 | iwb_stage_iReg__log_reg_7_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_59 = iwb_stage_iReg__log_reg_7_T_58 | iwb_stage_iReg__log_reg_7_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_60 = iwb_stage_iReg__log_reg_7_T_59 | iwb_stage_iReg__log_reg_7_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_61 = iwb_stage_iReg__log_reg_7_T_60 | iwb_stage_iReg__log_reg_7_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_62 = iwb_stage_iReg__log_reg_7_T_61 | iwb_stage_iReg__log_reg_7_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_7_T_63 = iwb_stage_iReg__log_reg_7_T_62 | iwb_stage_iReg__log_reg_7_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_7_T_64 = iwb_stage_iReg__log_reg_7_T_63 ? iwb_stage_iReg_log_reg_7 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_8_T = iwb_stage_iReg_archit_ptr_0 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h8; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_8_T_33 = iwb_stage_iReg__log_reg_8_T | iwb_stage_iReg__log_reg_8_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_34 = iwb_stage_iReg__log_reg_8_T_33 | iwb_stage_iReg__log_reg_8_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_35 = iwb_stage_iReg__log_reg_8_T_34 | iwb_stage_iReg__log_reg_8_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_36 = iwb_stage_iReg__log_reg_8_T_35 | iwb_stage_iReg__log_reg_8_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_37 = iwb_stage_iReg__log_reg_8_T_36 | iwb_stage_iReg__log_reg_8_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_38 = iwb_stage_iReg__log_reg_8_T_37 | iwb_stage_iReg__log_reg_8_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_39 = iwb_stage_iReg__log_reg_8_T_38 | iwb_stage_iReg__log_reg_8_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_40 = iwb_stage_iReg__log_reg_8_T_39 | iwb_stage_iReg__log_reg_8_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_41 = iwb_stage_iReg__log_reg_8_T_40 | iwb_stage_iReg__log_reg_8_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_42 = iwb_stage_iReg__log_reg_8_T_41 | iwb_stage_iReg__log_reg_8_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_43 = iwb_stage_iReg__log_reg_8_T_42 | iwb_stage_iReg__log_reg_8_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_44 = iwb_stage_iReg__log_reg_8_T_43 | iwb_stage_iReg__log_reg_8_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_45 = iwb_stage_iReg__log_reg_8_T_44 | iwb_stage_iReg__log_reg_8_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_46 = iwb_stage_iReg__log_reg_8_T_45 | iwb_stage_iReg__log_reg_8_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_47 = iwb_stage_iReg__log_reg_8_T_46 | iwb_stage_iReg__log_reg_8_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_48 = iwb_stage_iReg__log_reg_8_T_47 | iwb_stage_iReg__log_reg_8_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_49 = iwb_stage_iReg__log_reg_8_T_48 | iwb_stage_iReg__log_reg_8_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_50 = iwb_stage_iReg__log_reg_8_T_49 | iwb_stage_iReg__log_reg_8_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_51 = iwb_stage_iReg__log_reg_8_T_50 | iwb_stage_iReg__log_reg_8_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_52 = iwb_stage_iReg__log_reg_8_T_51 | iwb_stage_iReg__log_reg_8_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_53 = iwb_stage_iReg__log_reg_8_T_52 | iwb_stage_iReg__log_reg_8_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_54 = iwb_stage_iReg__log_reg_8_T_53 | iwb_stage_iReg__log_reg_8_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_55 = iwb_stage_iReg__log_reg_8_T_54 | iwb_stage_iReg__log_reg_8_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_56 = iwb_stage_iReg__log_reg_8_T_55 | iwb_stage_iReg__log_reg_8_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_57 = iwb_stage_iReg__log_reg_8_T_56 | iwb_stage_iReg__log_reg_8_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_58 = iwb_stage_iReg__log_reg_8_T_57 | iwb_stage_iReg__log_reg_8_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_59 = iwb_stage_iReg__log_reg_8_T_58 | iwb_stage_iReg__log_reg_8_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_60 = iwb_stage_iReg__log_reg_8_T_59 | iwb_stage_iReg__log_reg_8_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_61 = iwb_stage_iReg__log_reg_8_T_60 | iwb_stage_iReg__log_reg_8_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_62 = iwb_stage_iReg__log_reg_8_T_61 | iwb_stage_iReg__log_reg_8_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_8_T_63 = iwb_stage_iReg__log_reg_8_T_62 | iwb_stage_iReg__log_reg_8_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_8_T_64 = iwb_stage_iReg__log_reg_8_T_63 ? iwb_stage_iReg_log_reg_8 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_9_T = iwb_stage_iReg_archit_ptr_0 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h9; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_9_T_33 = iwb_stage_iReg__log_reg_9_T | iwb_stage_iReg__log_reg_9_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_34 = iwb_stage_iReg__log_reg_9_T_33 | iwb_stage_iReg__log_reg_9_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_35 = iwb_stage_iReg__log_reg_9_T_34 | iwb_stage_iReg__log_reg_9_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_36 = iwb_stage_iReg__log_reg_9_T_35 | iwb_stage_iReg__log_reg_9_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_37 = iwb_stage_iReg__log_reg_9_T_36 | iwb_stage_iReg__log_reg_9_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_38 = iwb_stage_iReg__log_reg_9_T_37 | iwb_stage_iReg__log_reg_9_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_39 = iwb_stage_iReg__log_reg_9_T_38 | iwb_stage_iReg__log_reg_9_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_40 = iwb_stage_iReg__log_reg_9_T_39 | iwb_stage_iReg__log_reg_9_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_41 = iwb_stage_iReg__log_reg_9_T_40 | iwb_stage_iReg__log_reg_9_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_42 = iwb_stage_iReg__log_reg_9_T_41 | iwb_stage_iReg__log_reg_9_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_43 = iwb_stage_iReg__log_reg_9_T_42 | iwb_stage_iReg__log_reg_9_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_44 = iwb_stage_iReg__log_reg_9_T_43 | iwb_stage_iReg__log_reg_9_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_45 = iwb_stage_iReg__log_reg_9_T_44 | iwb_stage_iReg__log_reg_9_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_46 = iwb_stage_iReg__log_reg_9_T_45 | iwb_stage_iReg__log_reg_9_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_47 = iwb_stage_iReg__log_reg_9_T_46 | iwb_stage_iReg__log_reg_9_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_48 = iwb_stage_iReg__log_reg_9_T_47 | iwb_stage_iReg__log_reg_9_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_49 = iwb_stage_iReg__log_reg_9_T_48 | iwb_stage_iReg__log_reg_9_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_50 = iwb_stage_iReg__log_reg_9_T_49 | iwb_stage_iReg__log_reg_9_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_51 = iwb_stage_iReg__log_reg_9_T_50 | iwb_stage_iReg__log_reg_9_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_52 = iwb_stage_iReg__log_reg_9_T_51 | iwb_stage_iReg__log_reg_9_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_53 = iwb_stage_iReg__log_reg_9_T_52 | iwb_stage_iReg__log_reg_9_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_54 = iwb_stage_iReg__log_reg_9_T_53 | iwb_stage_iReg__log_reg_9_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_55 = iwb_stage_iReg__log_reg_9_T_54 | iwb_stage_iReg__log_reg_9_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_56 = iwb_stage_iReg__log_reg_9_T_55 | iwb_stage_iReg__log_reg_9_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_57 = iwb_stage_iReg__log_reg_9_T_56 | iwb_stage_iReg__log_reg_9_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_58 = iwb_stage_iReg__log_reg_9_T_57 | iwb_stage_iReg__log_reg_9_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_59 = iwb_stage_iReg__log_reg_9_T_58 | iwb_stage_iReg__log_reg_9_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_60 = iwb_stage_iReg__log_reg_9_T_59 | iwb_stage_iReg__log_reg_9_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_61 = iwb_stage_iReg__log_reg_9_T_60 | iwb_stage_iReg__log_reg_9_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_62 = iwb_stage_iReg__log_reg_9_T_61 | iwb_stage_iReg__log_reg_9_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_9_T_63 = iwb_stage_iReg__log_reg_9_T_62 | iwb_stage_iReg__log_reg_9_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_9_T_64 = iwb_stage_iReg__log_reg_9_T_63 ? iwb_stage_iReg_log_reg_9 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_10_T = iwb_stage_iReg_archit_ptr_0 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'ha; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_10_T_33 = iwb_stage_iReg__log_reg_10_T | iwb_stage_iReg__log_reg_10_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_34 = iwb_stage_iReg__log_reg_10_T_33 | iwb_stage_iReg__log_reg_10_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_35 = iwb_stage_iReg__log_reg_10_T_34 | iwb_stage_iReg__log_reg_10_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_36 = iwb_stage_iReg__log_reg_10_T_35 | iwb_stage_iReg__log_reg_10_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_37 = iwb_stage_iReg__log_reg_10_T_36 | iwb_stage_iReg__log_reg_10_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_38 = iwb_stage_iReg__log_reg_10_T_37 | iwb_stage_iReg__log_reg_10_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_39 = iwb_stage_iReg__log_reg_10_T_38 | iwb_stage_iReg__log_reg_10_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_40 = iwb_stage_iReg__log_reg_10_T_39 | iwb_stage_iReg__log_reg_10_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_41 = iwb_stage_iReg__log_reg_10_T_40 | iwb_stage_iReg__log_reg_10_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_42 = iwb_stage_iReg__log_reg_10_T_41 | iwb_stage_iReg__log_reg_10_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_43 = iwb_stage_iReg__log_reg_10_T_42 | iwb_stage_iReg__log_reg_10_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_44 = iwb_stage_iReg__log_reg_10_T_43 | iwb_stage_iReg__log_reg_10_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_45 = iwb_stage_iReg__log_reg_10_T_44 | iwb_stage_iReg__log_reg_10_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_46 = iwb_stage_iReg__log_reg_10_T_45 | iwb_stage_iReg__log_reg_10_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_47 = iwb_stage_iReg__log_reg_10_T_46 | iwb_stage_iReg__log_reg_10_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_48 = iwb_stage_iReg__log_reg_10_T_47 | iwb_stage_iReg__log_reg_10_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_49 = iwb_stage_iReg__log_reg_10_T_48 | iwb_stage_iReg__log_reg_10_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_50 = iwb_stage_iReg__log_reg_10_T_49 | iwb_stage_iReg__log_reg_10_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_51 = iwb_stage_iReg__log_reg_10_T_50 | iwb_stage_iReg__log_reg_10_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_52 = iwb_stage_iReg__log_reg_10_T_51 | iwb_stage_iReg__log_reg_10_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_53 = iwb_stage_iReg__log_reg_10_T_52 | iwb_stage_iReg__log_reg_10_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_54 = iwb_stage_iReg__log_reg_10_T_53 | iwb_stage_iReg__log_reg_10_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_55 = iwb_stage_iReg__log_reg_10_T_54 | iwb_stage_iReg__log_reg_10_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_56 = iwb_stage_iReg__log_reg_10_T_55 | iwb_stage_iReg__log_reg_10_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_57 = iwb_stage_iReg__log_reg_10_T_56 | iwb_stage_iReg__log_reg_10_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_58 = iwb_stage_iReg__log_reg_10_T_57 | iwb_stage_iReg__log_reg_10_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_59 = iwb_stage_iReg__log_reg_10_T_58 | iwb_stage_iReg__log_reg_10_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_60 = iwb_stage_iReg__log_reg_10_T_59 | iwb_stage_iReg__log_reg_10_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_61 = iwb_stage_iReg__log_reg_10_T_60 | iwb_stage_iReg__log_reg_10_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_62 = iwb_stage_iReg__log_reg_10_T_61 | iwb_stage_iReg__log_reg_10_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_10_T_63 = iwb_stage_iReg__log_reg_10_T_62 | iwb_stage_iReg__log_reg_10_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_10_T_64 = iwb_stage_iReg__log_reg_10_T_63 ? iwb_stage_iReg_log_reg_10 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_11_T = iwb_stage_iReg_archit_ptr_0 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'hb; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_11_T_33 = iwb_stage_iReg__log_reg_11_T | iwb_stage_iReg__log_reg_11_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_34 = iwb_stage_iReg__log_reg_11_T_33 | iwb_stage_iReg__log_reg_11_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_35 = iwb_stage_iReg__log_reg_11_T_34 | iwb_stage_iReg__log_reg_11_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_36 = iwb_stage_iReg__log_reg_11_T_35 | iwb_stage_iReg__log_reg_11_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_37 = iwb_stage_iReg__log_reg_11_T_36 | iwb_stage_iReg__log_reg_11_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_38 = iwb_stage_iReg__log_reg_11_T_37 | iwb_stage_iReg__log_reg_11_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_39 = iwb_stage_iReg__log_reg_11_T_38 | iwb_stage_iReg__log_reg_11_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_40 = iwb_stage_iReg__log_reg_11_T_39 | iwb_stage_iReg__log_reg_11_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_41 = iwb_stage_iReg__log_reg_11_T_40 | iwb_stage_iReg__log_reg_11_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_42 = iwb_stage_iReg__log_reg_11_T_41 | iwb_stage_iReg__log_reg_11_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_43 = iwb_stage_iReg__log_reg_11_T_42 | iwb_stage_iReg__log_reg_11_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_44 = iwb_stage_iReg__log_reg_11_T_43 | iwb_stage_iReg__log_reg_11_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_45 = iwb_stage_iReg__log_reg_11_T_44 | iwb_stage_iReg__log_reg_11_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_46 = iwb_stage_iReg__log_reg_11_T_45 | iwb_stage_iReg__log_reg_11_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_47 = iwb_stage_iReg__log_reg_11_T_46 | iwb_stage_iReg__log_reg_11_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_48 = iwb_stage_iReg__log_reg_11_T_47 | iwb_stage_iReg__log_reg_11_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_49 = iwb_stage_iReg__log_reg_11_T_48 | iwb_stage_iReg__log_reg_11_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_50 = iwb_stage_iReg__log_reg_11_T_49 | iwb_stage_iReg__log_reg_11_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_51 = iwb_stage_iReg__log_reg_11_T_50 | iwb_stage_iReg__log_reg_11_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_52 = iwb_stage_iReg__log_reg_11_T_51 | iwb_stage_iReg__log_reg_11_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_53 = iwb_stage_iReg__log_reg_11_T_52 | iwb_stage_iReg__log_reg_11_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_54 = iwb_stage_iReg__log_reg_11_T_53 | iwb_stage_iReg__log_reg_11_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_55 = iwb_stage_iReg__log_reg_11_T_54 | iwb_stage_iReg__log_reg_11_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_56 = iwb_stage_iReg__log_reg_11_T_55 | iwb_stage_iReg__log_reg_11_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_57 = iwb_stage_iReg__log_reg_11_T_56 | iwb_stage_iReg__log_reg_11_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_58 = iwb_stage_iReg__log_reg_11_T_57 | iwb_stage_iReg__log_reg_11_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_59 = iwb_stage_iReg__log_reg_11_T_58 | iwb_stage_iReg__log_reg_11_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_60 = iwb_stage_iReg__log_reg_11_T_59 | iwb_stage_iReg__log_reg_11_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_61 = iwb_stage_iReg__log_reg_11_T_60 | iwb_stage_iReg__log_reg_11_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_62 = iwb_stage_iReg__log_reg_11_T_61 | iwb_stage_iReg__log_reg_11_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_11_T_63 = iwb_stage_iReg__log_reg_11_T_62 | iwb_stage_iReg__log_reg_11_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_11_T_64 = iwb_stage_iReg__log_reg_11_T_63 ? iwb_stage_iReg_log_reg_11 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_12_T = iwb_stage_iReg_archit_ptr_0 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'hc; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_12_T_33 = iwb_stage_iReg__log_reg_12_T | iwb_stage_iReg__log_reg_12_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_34 = iwb_stage_iReg__log_reg_12_T_33 | iwb_stage_iReg__log_reg_12_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_35 = iwb_stage_iReg__log_reg_12_T_34 | iwb_stage_iReg__log_reg_12_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_36 = iwb_stage_iReg__log_reg_12_T_35 | iwb_stage_iReg__log_reg_12_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_37 = iwb_stage_iReg__log_reg_12_T_36 | iwb_stage_iReg__log_reg_12_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_38 = iwb_stage_iReg__log_reg_12_T_37 | iwb_stage_iReg__log_reg_12_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_39 = iwb_stage_iReg__log_reg_12_T_38 | iwb_stage_iReg__log_reg_12_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_40 = iwb_stage_iReg__log_reg_12_T_39 | iwb_stage_iReg__log_reg_12_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_41 = iwb_stage_iReg__log_reg_12_T_40 | iwb_stage_iReg__log_reg_12_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_42 = iwb_stage_iReg__log_reg_12_T_41 | iwb_stage_iReg__log_reg_12_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_43 = iwb_stage_iReg__log_reg_12_T_42 | iwb_stage_iReg__log_reg_12_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_44 = iwb_stage_iReg__log_reg_12_T_43 | iwb_stage_iReg__log_reg_12_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_45 = iwb_stage_iReg__log_reg_12_T_44 | iwb_stage_iReg__log_reg_12_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_46 = iwb_stage_iReg__log_reg_12_T_45 | iwb_stage_iReg__log_reg_12_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_47 = iwb_stage_iReg__log_reg_12_T_46 | iwb_stage_iReg__log_reg_12_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_48 = iwb_stage_iReg__log_reg_12_T_47 | iwb_stage_iReg__log_reg_12_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_49 = iwb_stage_iReg__log_reg_12_T_48 | iwb_stage_iReg__log_reg_12_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_50 = iwb_stage_iReg__log_reg_12_T_49 | iwb_stage_iReg__log_reg_12_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_51 = iwb_stage_iReg__log_reg_12_T_50 | iwb_stage_iReg__log_reg_12_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_52 = iwb_stage_iReg__log_reg_12_T_51 | iwb_stage_iReg__log_reg_12_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_53 = iwb_stage_iReg__log_reg_12_T_52 | iwb_stage_iReg__log_reg_12_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_54 = iwb_stage_iReg__log_reg_12_T_53 | iwb_stage_iReg__log_reg_12_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_55 = iwb_stage_iReg__log_reg_12_T_54 | iwb_stage_iReg__log_reg_12_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_56 = iwb_stage_iReg__log_reg_12_T_55 | iwb_stage_iReg__log_reg_12_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_57 = iwb_stage_iReg__log_reg_12_T_56 | iwb_stage_iReg__log_reg_12_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_58 = iwb_stage_iReg__log_reg_12_T_57 | iwb_stage_iReg__log_reg_12_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_59 = iwb_stage_iReg__log_reg_12_T_58 | iwb_stage_iReg__log_reg_12_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_60 = iwb_stage_iReg__log_reg_12_T_59 | iwb_stage_iReg__log_reg_12_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_61 = iwb_stage_iReg__log_reg_12_T_60 | iwb_stage_iReg__log_reg_12_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_62 = iwb_stage_iReg__log_reg_12_T_61 | iwb_stage_iReg__log_reg_12_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_12_T_63 = iwb_stage_iReg__log_reg_12_T_62 | iwb_stage_iReg__log_reg_12_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_12_T_64 = iwb_stage_iReg__log_reg_12_T_63 ? iwb_stage_iReg_log_reg_12 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_13_T = iwb_stage_iReg_archit_ptr_0 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'hd; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_13_T_33 = iwb_stage_iReg__log_reg_13_T | iwb_stage_iReg__log_reg_13_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_34 = iwb_stage_iReg__log_reg_13_T_33 | iwb_stage_iReg__log_reg_13_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_35 = iwb_stage_iReg__log_reg_13_T_34 | iwb_stage_iReg__log_reg_13_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_36 = iwb_stage_iReg__log_reg_13_T_35 | iwb_stage_iReg__log_reg_13_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_37 = iwb_stage_iReg__log_reg_13_T_36 | iwb_stage_iReg__log_reg_13_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_38 = iwb_stage_iReg__log_reg_13_T_37 | iwb_stage_iReg__log_reg_13_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_39 = iwb_stage_iReg__log_reg_13_T_38 | iwb_stage_iReg__log_reg_13_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_40 = iwb_stage_iReg__log_reg_13_T_39 | iwb_stage_iReg__log_reg_13_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_41 = iwb_stage_iReg__log_reg_13_T_40 | iwb_stage_iReg__log_reg_13_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_42 = iwb_stage_iReg__log_reg_13_T_41 | iwb_stage_iReg__log_reg_13_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_43 = iwb_stage_iReg__log_reg_13_T_42 | iwb_stage_iReg__log_reg_13_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_44 = iwb_stage_iReg__log_reg_13_T_43 | iwb_stage_iReg__log_reg_13_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_45 = iwb_stage_iReg__log_reg_13_T_44 | iwb_stage_iReg__log_reg_13_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_46 = iwb_stage_iReg__log_reg_13_T_45 | iwb_stage_iReg__log_reg_13_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_47 = iwb_stage_iReg__log_reg_13_T_46 | iwb_stage_iReg__log_reg_13_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_48 = iwb_stage_iReg__log_reg_13_T_47 | iwb_stage_iReg__log_reg_13_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_49 = iwb_stage_iReg__log_reg_13_T_48 | iwb_stage_iReg__log_reg_13_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_50 = iwb_stage_iReg__log_reg_13_T_49 | iwb_stage_iReg__log_reg_13_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_51 = iwb_stage_iReg__log_reg_13_T_50 | iwb_stage_iReg__log_reg_13_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_52 = iwb_stage_iReg__log_reg_13_T_51 | iwb_stage_iReg__log_reg_13_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_53 = iwb_stage_iReg__log_reg_13_T_52 | iwb_stage_iReg__log_reg_13_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_54 = iwb_stage_iReg__log_reg_13_T_53 | iwb_stage_iReg__log_reg_13_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_55 = iwb_stage_iReg__log_reg_13_T_54 | iwb_stage_iReg__log_reg_13_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_56 = iwb_stage_iReg__log_reg_13_T_55 | iwb_stage_iReg__log_reg_13_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_57 = iwb_stage_iReg__log_reg_13_T_56 | iwb_stage_iReg__log_reg_13_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_58 = iwb_stage_iReg__log_reg_13_T_57 | iwb_stage_iReg__log_reg_13_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_59 = iwb_stage_iReg__log_reg_13_T_58 | iwb_stage_iReg__log_reg_13_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_60 = iwb_stage_iReg__log_reg_13_T_59 | iwb_stage_iReg__log_reg_13_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_61 = iwb_stage_iReg__log_reg_13_T_60 | iwb_stage_iReg__log_reg_13_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_62 = iwb_stage_iReg__log_reg_13_T_61 | iwb_stage_iReg__log_reg_13_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_13_T_63 = iwb_stage_iReg__log_reg_13_T_62 | iwb_stage_iReg__log_reg_13_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_13_T_64 = iwb_stage_iReg__log_reg_13_T_63 ? iwb_stage_iReg_log_reg_13 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_14_T = iwb_stage_iReg_archit_ptr_0 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'he; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_14_T_33 = iwb_stage_iReg__log_reg_14_T | iwb_stage_iReg__log_reg_14_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_34 = iwb_stage_iReg__log_reg_14_T_33 | iwb_stage_iReg__log_reg_14_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_35 = iwb_stage_iReg__log_reg_14_T_34 | iwb_stage_iReg__log_reg_14_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_36 = iwb_stage_iReg__log_reg_14_T_35 | iwb_stage_iReg__log_reg_14_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_37 = iwb_stage_iReg__log_reg_14_T_36 | iwb_stage_iReg__log_reg_14_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_38 = iwb_stage_iReg__log_reg_14_T_37 | iwb_stage_iReg__log_reg_14_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_39 = iwb_stage_iReg__log_reg_14_T_38 | iwb_stage_iReg__log_reg_14_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_40 = iwb_stage_iReg__log_reg_14_T_39 | iwb_stage_iReg__log_reg_14_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_41 = iwb_stage_iReg__log_reg_14_T_40 | iwb_stage_iReg__log_reg_14_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_42 = iwb_stage_iReg__log_reg_14_T_41 | iwb_stage_iReg__log_reg_14_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_43 = iwb_stage_iReg__log_reg_14_T_42 | iwb_stage_iReg__log_reg_14_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_44 = iwb_stage_iReg__log_reg_14_T_43 | iwb_stage_iReg__log_reg_14_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_45 = iwb_stage_iReg__log_reg_14_T_44 | iwb_stage_iReg__log_reg_14_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_46 = iwb_stage_iReg__log_reg_14_T_45 | iwb_stage_iReg__log_reg_14_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_47 = iwb_stage_iReg__log_reg_14_T_46 | iwb_stage_iReg__log_reg_14_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_48 = iwb_stage_iReg__log_reg_14_T_47 | iwb_stage_iReg__log_reg_14_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_49 = iwb_stage_iReg__log_reg_14_T_48 | iwb_stage_iReg__log_reg_14_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_50 = iwb_stage_iReg__log_reg_14_T_49 | iwb_stage_iReg__log_reg_14_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_51 = iwb_stage_iReg__log_reg_14_T_50 | iwb_stage_iReg__log_reg_14_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_52 = iwb_stage_iReg__log_reg_14_T_51 | iwb_stage_iReg__log_reg_14_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_53 = iwb_stage_iReg__log_reg_14_T_52 | iwb_stage_iReg__log_reg_14_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_54 = iwb_stage_iReg__log_reg_14_T_53 | iwb_stage_iReg__log_reg_14_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_55 = iwb_stage_iReg__log_reg_14_T_54 | iwb_stage_iReg__log_reg_14_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_56 = iwb_stage_iReg__log_reg_14_T_55 | iwb_stage_iReg__log_reg_14_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_57 = iwb_stage_iReg__log_reg_14_T_56 | iwb_stage_iReg__log_reg_14_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_58 = iwb_stage_iReg__log_reg_14_T_57 | iwb_stage_iReg__log_reg_14_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_59 = iwb_stage_iReg__log_reg_14_T_58 | iwb_stage_iReg__log_reg_14_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_60 = iwb_stage_iReg__log_reg_14_T_59 | iwb_stage_iReg__log_reg_14_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_61 = iwb_stage_iReg__log_reg_14_T_60 | iwb_stage_iReg__log_reg_14_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_62 = iwb_stage_iReg__log_reg_14_T_61 | iwb_stage_iReg__log_reg_14_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_14_T_63 = iwb_stage_iReg__log_reg_14_T_62 | iwb_stage_iReg__log_reg_14_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_14_T_64 = iwb_stage_iReg__log_reg_14_T_63 ? iwb_stage_iReg_log_reg_14 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_15_T = iwb_stage_iReg_archit_ptr_0 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'hf; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_15_T_33 = iwb_stage_iReg__log_reg_15_T | iwb_stage_iReg__log_reg_15_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_34 = iwb_stage_iReg__log_reg_15_T_33 | iwb_stage_iReg__log_reg_15_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_35 = iwb_stage_iReg__log_reg_15_T_34 | iwb_stage_iReg__log_reg_15_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_36 = iwb_stage_iReg__log_reg_15_T_35 | iwb_stage_iReg__log_reg_15_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_37 = iwb_stage_iReg__log_reg_15_T_36 | iwb_stage_iReg__log_reg_15_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_38 = iwb_stage_iReg__log_reg_15_T_37 | iwb_stage_iReg__log_reg_15_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_39 = iwb_stage_iReg__log_reg_15_T_38 | iwb_stage_iReg__log_reg_15_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_40 = iwb_stage_iReg__log_reg_15_T_39 | iwb_stage_iReg__log_reg_15_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_41 = iwb_stage_iReg__log_reg_15_T_40 | iwb_stage_iReg__log_reg_15_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_42 = iwb_stage_iReg__log_reg_15_T_41 | iwb_stage_iReg__log_reg_15_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_43 = iwb_stage_iReg__log_reg_15_T_42 | iwb_stage_iReg__log_reg_15_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_44 = iwb_stage_iReg__log_reg_15_T_43 | iwb_stage_iReg__log_reg_15_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_45 = iwb_stage_iReg__log_reg_15_T_44 | iwb_stage_iReg__log_reg_15_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_46 = iwb_stage_iReg__log_reg_15_T_45 | iwb_stage_iReg__log_reg_15_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_47 = iwb_stage_iReg__log_reg_15_T_46 | iwb_stage_iReg__log_reg_15_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_48 = iwb_stage_iReg__log_reg_15_T_47 | iwb_stage_iReg__log_reg_15_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_49 = iwb_stage_iReg__log_reg_15_T_48 | iwb_stage_iReg__log_reg_15_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_50 = iwb_stage_iReg__log_reg_15_T_49 | iwb_stage_iReg__log_reg_15_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_51 = iwb_stage_iReg__log_reg_15_T_50 | iwb_stage_iReg__log_reg_15_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_52 = iwb_stage_iReg__log_reg_15_T_51 | iwb_stage_iReg__log_reg_15_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_53 = iwb_stage_iReg__log_reg_15_T_52 | iwb_stage_iReg__log_reg_15_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_54 = iwb_stage_iReg__log_reg_15_T_53 | iwb_stage_iReg__log_reg_15_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_55 = iwb_stage_iReg__log_reg_15_T_54 | iwb_stage_iReg__log_reg_15_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_56 = iwb_stage_iReg__log_reg_15_T_55 | iwb_stage_iReg__log_reg_15_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_57 = iwb_stage_iReg__log_reg_15_T_56 | iwb_stage_iReg__log_reg_15_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_58 = iwb_stage_iReg__log_reg_15_T_57 | iwb_stage_iReg__log_reg_15_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_59 = iwb_stage_iReg__log_reg_15_T_58 | iwb_stage_iReg__log_reg_15_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_60 = iwb_stage_iReg__log_reg_15_T_59 | iwb_stage_iReg__log_reg_15_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_61 = iwb_stage_iReg__log_reg_15_T_60 | iwb_stage_iReg__log_reg_15_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_62 = iwb_stage_iReg__log_reg_15_T_61 | iwb_stage_iReg__log_reg_15_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_15_T_63 = iwb_stage_iReg__log_reg_15_T_62 | iwb_stage_iReg__log_reg_15_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_15_T_64 = iwb_stage_iReg__log_reg_15_T_63 ? iwb_stage_iReg_log_reg_15 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_16_T = iwb_stage_iReg_archit_ptr_0 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h10; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_16_T_33 = iwb_stage_iReg__log_reg_16_T | iwb_stage_iReg__log_reg_16_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_34 = iwb_stage_iReg__log_reg_16_T_33 | iwb_stage_iReg__log_reg_16_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_35 = iwb_stage_iReg__log_reg_16_T_34 | iwb_stage_iReg__log_reg_16_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_36 = iwb_stage_iReg__log_reg_16_T_35 | iwb_stage_iReg__log_reg_16_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_37 = iwb_stage_iReg__log_reg_16_T_36 | iwb_stage_iReg__log_reg_16_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_38 = iwb_stage_iReg__log_reg_16_T_37 | iwb_stage_iReg__log_reg_16_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_39 = iwb_stage_iReg__log_reg_16_T_38 | iwb_stage_iReg__log_reg_16_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_40 = iwb_stage_iReg__log_reg_16_T_39 | iwb_stage_iReg__log_reg_16_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_41 = iwb_stage_iReg__log_reg_16_T_40 | iwb_stage_iReg__log_reg_16_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_42 = iwb_stage_iReg__log_reg_16_T_41 | iwb_stage_iReg__log_reg_16_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_43 = iwb_stage_iReg__log_reg_16_T_42 | iwb_stage_iReg__log_reg_16_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_44 = iwb_stage_iReg__log_reg_16_T_43 | iwb_stage_iReg__log_reg_16_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_45 = iwb_stage_iReg__log_reg_16_T_44 | iwb_stage_iReg__log_reg_16_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_46 = iwb_stage_iReg__log_reg_16_T_45 | iwb_stage_iReg__log_reg_16_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_47 = iwb_stage_iReg__log_reg_16_T_46 | iwb_stage_iReg__log_reg_16_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_48 = iwb_stage_iReg__log_reg_16_T_47 | iwb_stage_iReg__log_reg_16_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_49 = iwb_stage_iReg__log_reg_16_T_48 | iwb_stage_iReg__log_reg_16_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_50 = iwb_stage_iReg__log_reg_16_T_49 | iwb_stage_iReg__log_reg_16_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_51 = iwb_stage_iReg__log_reg_16_T_50 | iwb_stage_iReg__log_reg_16_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_52 = iwb_stage_iReg__log_reg_16_T_51 | iwb_stage_iReg__log_reg_16_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_53 = iwb_stage_iReg__log_reg_16_T_52 | iwb_stage_iReg__log_reg_16_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_54 = iwb_stage_iReg__log_reg_16_T_53 | iwb_stage_iReg__log_reg_16_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_55 = iwb_stage_iReg__log_reg_16_T_54 | iwb_stage_iReg__log_reg_16_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_56 = iwb_stage_iReg__log_reg_16_T_55 | iwb_stage_iReg__log_reg_16_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_57 = iwb_stage_iReg__log_reg_16_T_56 | iwb_stage_iReg__log_reg_16_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_58 = iwb_stage_iReg__log_reg_16_T_57 | iwb_stage_iReg__log_reg_16_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_59 = iwb_stage_iReg__log_reg_16_T_58 | iwb_stage_iReg__log_reg_16_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_60 = iwb_stage_iReg__log_reg_16_T_59 | iwb_stage_iReg__log_reg_16_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_61 = iwb_stage_iReg__log_reg_16_T_60 | iwb_stage_iReg__log_reg_16_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_62 = iwb_stage_iReg__log_reg_16_T_61 | iwb_stage_iReg__log_reg_16_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_16_T_63 = iwb_stage_iReg__log_reg_16_T_62 | iwb_stage_iReg__log_reg_16_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_16_T_64 = iwb_stage_iReg__log_reg_16_T_63 ? iwb_stage_iReg_log_reg_16 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_17_T = iwb_stage_iReg_archit_ptr_0 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h11; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_17_T_33 = iwb_stage_iReg__log_reg_17_T | iwb_stage_iReg__log_reg_17_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_34 = iwb_stage_iReg__log_reg_17_T_33 | iwb_stage_iReg__log_reg_17_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_35 = iwb_stage_iReg__log_reg_17_T_34 | iwb_stage_iReg__log_reg_17_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_36 = iwb_stage_iReg__log_reg_17_T_35 | iwb_stage_iReg__log_reg_17_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_37 = iwb_stage_iReg__log_reg_17_T_36 | iwb_stage_iReg__log_reg_17_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_38 = iwb_stage_iReg__log_reg_17_T_37 | iwb_stage_iReg__log_reg_17_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_39 = iwb_stage_iReg__log_reg_17_T_38 | iwb_stage_iReg__log_reg_17_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_40 = iwb_stage_iReg__log_reg_17_T_39 | iwb_stage_iReg__log_reg_17_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_41 = iwb_stage_iReg__log_reg_17_T_40 | iwb_stage_iReg__log_reg_17_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_42 = iwb_stage_iReg__log_reg_17_T_41 | iwb_stage_iReg__log_reg_17_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_43 = iwb_stage_iReg__log_reg_17_T_42 | iwb_stage_iReg__log_reg_17_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_44 = iwb_stage_iReg__log_reg_17_T_43 | iwb_stage_iReg__log_reg_17_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_45 = iwb_stage_iReg__log_reg_17_T_44 | iwb_stage_iReg__log_reg_17_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_46 = iwb_stage_iReg__log_reg_17_T_45 | iwb_stage_iReg__log_reg_17_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_47 = iwb_stage_iReg__log_reg_17_T_46 | iwb_stage_iReg__log_reg_17_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_48 = iwb_stage_iReg__log_reg_17_T_47 | iwb_stage_iReg__log_reg_17_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_49 = iwb_stage_iReg__log_reg_17_T_48 | iwb_stage_iReg__log_reg_17_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_50 = iwb_stage_iReg__log_reg_17_T_49 | iwb_stage_iReg__log_reg_17_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_51 = iwb_stage_iReg__log_reg_17_T_50 | iwb_stage_iReg__log_reg_17_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_52 = iwb_stage_iReg__log_reg_17_T_51 | iwb_stage_iReg__log_reg_17_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_53 = iwb_stage_iReg__log_reg_17_T_52 | iwb_stage_iReg__log_reg_17_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_54 = iwb_stage_iReg__log_reg_17_T_53 | iwb_stage_iReg__log_reg_17_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_55 = iwb_stage_iReg__log_reg_17_T_54 | iwb_stage_iReg__log_reg_17_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_56 = iwb_stage_iReg__log_reg_17_T_55 | iwb_stage_iReg__log_reg_17_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_57 = iwb_stage_iReg__log_reg_17_T_56 | iwb_stage_iReg__log_reg_17_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_58 = iwb_stage_iReg__log_reg_17_T_57 | iwb_stage_iReg__log_reg_17_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_59 = iwb_stage_iReg__log_reg_17_T_58 | iwb_stage_iReg__log_reg_17_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_60 = iwb_stage_iReg__log_reg_17_T_59 | iwb_stage_iReg__log_reg_17_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_61 = iwb_stage_iReg__log_reg_17_T_60 | iwb_stage_iReg__log_reg_17_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_62 = iwb_stage_iReg__log_reg_17_T_61 | iwb_stage_iReg__log_reg_17_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_17_T_63 = iwb_stage_iReg__log_reg_17_T_62 | iwb_stage_iReg__log_reg_17_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_17_T_64 = iwb_stage_iReg__log_reg_17_T_63 ? iwb_stage_iReg_log_reg_17 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_18_T = iwb_stage_iReg_archit_ptr_0 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h12; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_18_T_33 = iwb_stage_iReg__log_reg_18_T | iwb_stage_iReg__log_reg_18_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_34 = iwb_stage_iReg__log_reg_18_T_33 | iwb_stage_iReg__log_reg_18_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_35 = iwb_stage_iReg__log_reg_18_T_34 | iwb_stage_iReg__log_reg_18_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_36 = iwb_stage_iReg__log_reg_18_T_35 | iwb_stage_iReg__log_reg_18_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_37 = iwb_stage_iReg__log_reg_18_T_36 | iwb_stage_iReg__log_reg_18_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_38 = iwb_stage_iReg__log_reg_18_T_37 | iwb_stage_iReg__log_reg_18_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_39 = iwb_stage_iReg__log_reg_18_T_38 | iwb_stage_iReg__log_reg_18_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_40 = iwb_stage_iReg__log_reg_18_T_39 | iwb_stage_iReg__log_reg_18_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_41 = iwb_stage_iReg__log_reg_18_T_40 | iwb_stage_iReg__log_reg_18_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_42 = iwb_stage_iReg__log_reg_18_T_41 | iwb_stage_iReg__log_reg_18_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_43 = iwb_stage_iReg__log_reg_18_T_42 | iwb_stage_iReg__log_reg_18_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_44 = iwb_stage_iReg__log_reg_18_T_43 | iwb_stage_iReg__log_reg_18_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_45 = iwb_stage_iReg__log_reg_18_T_44 | iwb_stage_iReg__log_reg_18_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_46 = iwb_stage_iReg__log_reg_18_T_45 | iwb_stage_iReg__log_reg_18_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_47 = iwb_stage_iReg__log_reg_18_T_46 | iwb_stage_iReg__log_reg_18_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_48 = iwb_stage_iReg__log_reg_18_T_47 | iwb_stage_iReg__log_reg_18_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_49 = iwb_stage_iReg__log_reg_18_T_48 | iwb_stage_iReg__log_reg_18_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_50 = iwb_stage_iReg__log_reg_18_T_49 | iwb_stage_iReg__log_reg_18_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_51 = iwb_stage_iReg__log_reg_18_T_50 | iwb_stage_iReg__log_reg_18_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_52 = iwb_stage_iReg__log_reg_18_T_51 | iwb_stage_iReg__log_reg_18_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_53 = iwb_stage_iReg__log_reg_18_T_52 | iwb_stage_iReg__log_reg_18_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_54 = iwb_stage_iReg__log_reg_18_T_53 | iwb_stage_iReg__log_reg_18_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_55 = iwb_stage_iReg__log_reg_18_T_54 | iwb_stage_iReg__log_reg_18_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_56 = iwb_stage_iReg__log_reg_18_T_55 | iwb_stage_iReg__log_reg_18_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_57 = iwb_stage_iReg__log_reg_18_T_56 | iwb_stage_iReg__log_reg_18_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_58 = iwb_stage_iReg__log_reg_18_T_57 | iwb_stage_iReg__log_reg_18_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_59 = iwb_stage_iReg__log_reg_18_T_58 | iwb_stage_iReg__log_reg_18_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_60 = iwb_stage_iReg__log_reg_18_T_59 | iwb_stage_iReg__log_reg_18_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_61 = iwb_stage_iReg__log_reg_18_T_60 | iwb_stage_iReg__log_reg_18_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_62 = iwb_stage_iReg__log_reg_18_T_61 | iwb_stage_iReg__log_reg_18_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_18_T_63 = iwb_stage_iReg__log_reg_18_T_62 | iwb_stage_iReg__log_reg_18_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_18_T_64 = iwb_stage_iReg__log_reg_18_T_63 ? iwb_stage_iReg_log_reg_18 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_19_T = iwb_stage_iReg_archit_ptr_0 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h13; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_19_T_33 = iwb_stage_iReg__log_reg_19_T | iwb_stage_iReg__log_reg_19_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_34 = iwb_stage_iReg__log_reg_19_T_33 | iwb_stage_iReg__log_reg_19_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_35 = iwb_stage_iReg__log_reg_19_T_34 | iwb_stage_iReg__log_reg_19_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_36 = iwb_stage_iReg__log_reg_19_T_35 | iwb_stage_iReg__log_reg_19_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_37 = iwb_stage_iReg__log_reg_19_T_36 | iwb_stage_iReg__log_reg_19_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_38 = iwb_stage_iReg__log_reg_19_T_37 | iwb_stage_iReg__log_reg_19_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_39 = iwb_stage_iReg__log_reg_19_T_38 | iwb_stage_iReg__log_reg_19_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_40 = iwb_stage_iReg__log_reg_19_T_39 | iwb_stage_iReg__log_reg_19_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_41 = iwb_stage_iReg__log_reg_19_T_40 | iwb_stage_iReg__log_reg_19_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_42 = iwb_stage_iReg__log_reg_19_T_41 | iwb_stage_iReg__log_reg_19_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_43 = iwb_stage_iReg__log_reg_19_T_42 | iwb_stage_iReg__log_reg_19_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_44 = iwb_stage_iReg__log_reg_19_T_43 | iwb_stage_iReg__log_reg_19_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_45 = iwb_stage_iReg__log_reg_19_T_44 | iwb_stage_iReg__log_reg_19_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_46 = iwb_stage_iReg__log_reg_19_T_45 | iwb_stage_iReg__log_reg_19_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_47 = iwb_stage_iReg__log_reg_19_T_46 | iwb_stage_iReg__log_reg_19_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_48 = iwb_stage_iReg__log_reg_19_T_47 | iwb_stage_iReg__log_reg_19_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_49 = iwb_stage_iReg__log_reg_19_T_48 | iwb_stage_iReg__log_reg_19_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_50 = iwb_stage_iReg__log_reg_19_T_49 | iwb_stage_iReg__log_reg_19_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_51 = iwb_stage_iReg__log_reg_19_T_50 | iwb_stage_iReg__log_reg_19_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_52 = iwb_stage_iReg__log_reg_19_T_51 | iwb_stage_iReg__log_reg_19_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_53 = iwb_stage_iReg__log_reg_19_T_52 | iwb_stage_iReg__log_reg_19_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_54 = iwb_stage_iReg__log_reg_19_T_53 | iwb_stage_iReg__log_reg_19_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_55 = iwb_stage_iReg__log_reg_19_T_54 | iwb_stage_iReg__log_reg_19_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_56 = iwb_stage_iReg__log_reg_19_T_55 | iwb_stage_iReg__log_reg_19_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_57 = iwb_stage_iReg__log_reg_19_T_56 | iwb_stage_iReg__log_reg_19_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_58 = iwb_stage_iReg__log_reg_19_T_57 | iwb_stage_iReg__log_reg_19_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_59 = iwb_stage_iReg__log_reg_19_T_58 | iwb_stage_iReg__log_reg_19_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_60 = iwb_stage_iReg__log_reg_19_T_59 | iwb_stage_iReg__log_reg_19_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_61 = iwb_stage_iReg__log_reg_19_T_60 | iwb_stage_iReg__log_reg_19_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_62 = iwb_stage_iReg__log_reg_19_T_61 | iwb_stage_iReg__log_reg_19_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_19_T_63 = iwb_stage_iReg__log_reg_19_T_62 | iwb_stage_iReg__log_reg_19_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_19_T_64 = iwb_stage_iReg__log_reg_19_T_63 ? iwb_stage_iReg_log_reg_19 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_20_T = iwb_stage_iReg_archit_ptr_0 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h14; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_20_T_33 = iwb_stage_iReg__log_reg_20_T | iwb_stage_iReg__log_reg_20_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_34 = iwb_stage_iReg__log_reg_20_T_33 | iwb_stage_iReg__log_reg_20_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_35 = iwb_stage_iReg__log_reg_20_T_34 | iwb_stage_iReg__log_reg_20_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_36 = iwb_stage_iReg__log_reg_20_T_35 | iwb_stage_iReg__log_reg_20_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_37 = iwb_stage_iReg__log_reg_20_T_36 | iwb_stage_iReg__log_reg_20_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_38 = iwb_stage_iReg__log_reg_20_T_37 | iwb_stage_iReg__log_reg_20_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_39 = iwb_stage_iReg__log_reg_20_T_38 | iwb_stage_iReg__log_reg_20_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_40 = iwb_stage_iReg__log_reg_20_T_39 | iwb_stage_iReg__log_reg_20_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_41 = iwb_stage_iReg__log_reg_20_T_40 | iwb_stage_iReg__log_reg_20_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_42 = iwb_stage_iReg__log_reg_20_T_41 | iwb_stage_iReg__log_reg_20_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_43 = iwb_stage_iReg__log_reg_20_T_42 | iwb_stage_iReg__log_reg_20_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_44 = iwb_stage_iReg__log_reg_20_T_43 | iwb_stage_iReg__log_reg_20_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_45 = iwb_stage_iReg__log_reg_20_T_44 | iwb_stage_iReg__log_reg_20_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_46 = iwb_stage_iReg__log_reg_20_T_45 | iwb_stage_iReg__log_reg_20_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_47 = iwb_stage_iReg__log_reg_20_T_46 | iwb_stage_iReg__log_reg_20_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_48 = iwb_stage_iReg__log_reg_20_T_47 | iwb_stage_iReg__log_reg_20_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_49 = iwb_stage_iReg__log_reg_20_T_48 | iwb_stage_iReg__log_reg_20_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_50 = iwb_stage_iReg__log_reg_20_T_49 | iwb_stage_iReg__log_reg_20_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_51 = iwb_stage_iReg__log_reg_20_T_50 | iwb_stage_iReg__log_reg_20_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_52 = iwb_stage_iReg__log_reg_20_T_51 | iwb_stage_iReg__log_reg_20_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_53 = iwb_stage_iReg__log_reg_20_T_52 | iwb_stage_iReg__log_reg_20_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_54 = iwb_stage_iReg__log_reg_20_T_53 | iwb_stage_iReg__log_reg_20_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_55 = iwb_stage_iReg__log_reg_20_T_54 | iwb_stage_iReg__log_reg_20_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_56 = iwb_stage_iReg__log_reg_20_T_55 | iwb_stage_iReg__log_reg_20_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_57 = iwb_stage_iReg__log_reg_20_T_56 | iwb_stage_iReg__log_reg_20_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_58 = iwb_stage_iReg__log_reg_20_T_57 | iwb_stage_iReg__log_reg_20_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_59 = iwb_stage_iReg__log_reg_20_T_58 | iwb_stage_iReg__log_reg_20_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_60 = iwb_stage_iReg__log_reg_20_T_59 | iwb_stage_iReg__log_reg_20_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_61 = iwb_stage_iReg__log_reg_20_T_60 | iwb_stage_iReg__log_reg_20_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_62 = iwb_stage_iReg__log_reg_20_T_61 | iwb_stage_iReg__log_reg_20_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_20_T_63 = iwb_stage_iReg__log_reg_20_T_62 | iwb_stage_iReg__log_reg_20_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_20_T_64 = iwb_stage_iReg__log_reg_20_T_63 ? iwb_stage_iReg_log_reg_20 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_21_T = iwb_stage_iReg_archit_ptr_0 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h15; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_21_T_33 = iwb_stage_iReg__log_reg_21_T | iwb_stage_iReg__log_reg_21_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_34 = iwb_stage_iReg__log_reg_21_T_33 | iwb_stage_iReg__log_reg_21_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_35 = iwb_stage_iReg__log_reg_21_T_34 | iwb_stage_iReg__log_reg_21_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_36 = iwb_stage_iReg__log_reg_21_T_35 | iwb_stage_iReg__log_reg_21_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_37 = iwb_stage_iReg__log_reg_21_T_36 | iwb_stage_iReg__log_reg_21_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_38 = iwb_stage_iReg__log_reg_21_T_37 | iwb_stage_iReg__log_reg_21_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_39 = iwb_stage_iReg__log_reg_21_T_38 | iwb_stage_iReg__log_reg_21_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_40 = iwb_stage_iReg__log_reg_21_T_39 | iwb_stage_iReg__log_reg_21_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_41 = iwb_stage_iReg__log_reg_21_T_40 | iwb_stage_iReg__log_reg_21_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_42 = iwb_stage_iReg__log_reg_21_T_41 | iwb_stage_iReg__log_reg_21_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_43 = iwb_stage_iReg__log_reg_21_T_42 | iwb_stage_iReg__log_reg_21_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_44 = iwb_stage_iReg__log_reg_21_T_43 | iwb_stage_iReg__log_reg_21_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_45 = iwb_stage_iReg__log_reg_21_T_44 | iwb_stage_iReg__log_reg_21_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_46 = iwb_stage_iReg__log_reg_21_T_45 | iwb_stage_iReg__log_reg_21_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_47 = iwb_stage_iReg__log_reg_21_T_46 | iwb_stage_iReg__log_reg_21_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_48 = iwb_stage_iReg__log_reg_21_T_47 | iwb_stage_iReg__log_reg_21_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_49 = iwb_stage_iReg__log_reg_21_T_48 | iwb_stage_iReg__log_reg_21_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_50 = iwb_stage_iReg__log_reg_21_T_49 | iwb_stage_iReg__log_reg_21_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_51 = iwb_stage_iReg__log_reg_21_T_50 | iwb_stage_iReg__log_reg_21_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_52 = iwb_stage_iReg__log_reg_21_T_51 | iwb_stage_iReg__log_reg_21_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_53 = iwb_stage_iReg__log_reg_21_T_52 | iwb_stage_iReg__log_reg_21_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_54 = iwb_stage_iReg__log_reg_21_T_53 | iwb_stage_iReg__log_reg_21_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_55 = iwb_stage_iReg__log_reg_21_T_54 | iwb_stage_iReg__log_reg_21_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_56 = iwb_stage_iReg__log_reg_21_T_55 | iwb_stage_iReg__log_reg_21_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_57 = iwb_stage_iReg__log_reg_21_T_56 | iwb_stage_iReg__log_reg_21_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_58 = iwb_stage_iReg__log_reg_21_T_57 | iwb_stage_iReg__log_reg_21_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_59 = iwb_stage_iReg__log_reg_21_T_58 | iwb_stage_iReg__log_reg_21_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_60 = iwb_stage_iReg__log_reg_21_T_59 | iwb_stage_iReg__log_reg_21_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_61 = iwb_stage_iReg__log_reg_21_T_60 | iwb_stage_iReg__log_reg_21_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_62 = iwb_stage_iReg__log_reg_21_T_61 | iwb_stage_iReg__log_reg_21_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_21_T_63 = iwb_stage_iReg__log_reg_21_T_62 | iwb_stage_iReg__log_reg_21_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_21_T_64 = iwb_stage_iReg__log_reg_21_T_63 ? iwb_stage_iReg_log_reg_21 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_22_T = iwb_stage_iReg_archit_ptr_0 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h16; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_22_T_33 = iwb_stage_iReg__log_reg_22_T | iwb_stage_iReg__log_reg_22_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_34 = iwb_stage_iReg__log_reg_22_T_33 | iwb_stage_iReg__log_reg_22_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_35 = iwb_stage_iReg__log_reg_22_T_34 | iwb_stage_iReg__log_reg_22_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_36 = iwb_stage_iReg__log_reg_22_T_35 | iwb_stage_iReg__log_reg_22_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_37 = iwb_stage_iReg__log_reg_22_T_36 | iwb_stage_iReg__log_reg_22_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_38 = iwb_stage_iReg__log_reg_22_T_37 | iwb_stage_iReg__log_reg_22_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_39 = iwb_stage_iReg__log_reg_22_T_38 | iwb_stage_iReg__log_reg_22_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_40 = iwb_stage_iReg__log_reg_22_T_39 | iwb_stage_iReg__log_reg_22_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_41 = iwb_stage_iReg__log_reg_22_T_40 | iwb_stage_iReg__log_reg_22_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_42 = iwb_stage_iReg__log_reg_22_T_41 | iwb_stage_iReg__log_reg_22_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_43 = iwb_stage_iReg__log_reg_22_T_42 | iwb_stage_iReg__log_reg_22_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_44 = iwb_stage_iReg__log_reg_22_T_43 | iwb_stage_iReg__log_reg_22_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_45 = iwb_stage_iReg__log_reg_22_T_44 | iwb_stage_iReg__log_reg_22_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_46 = iwb_stage_iReg__log_reg_22_T_45 | iwb_stage_iReg__log_reg_22_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_47 = iwb_stage_iReg__log_reg_22_T_46 | iwb_stage_iReg__log_reg_22_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_48 = iwb_stage_iReg__log_reg_22_T_47 | iwb_stage_iReg__log_reg_22_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_49 = iwb_stage_iReg__log_reg_22_T_48 | iwb_stage_iReg__log_reg_22_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_50 = iwb_stage_iReg__log_reg_22_T_49 | iwb_stage_iReg__log_reg_22_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_51 = iwb_stage_iReg__log_reg_22_T_50 | iwb_stage_iReg__log_reg_22_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_52 = iwb_stage_iReg__log_reg_22_T_51 | iwb_stage_iReg__log_reg_22_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_53 = iwb_stage_iReg__log_reg_22_T_52 | iwb_stage_iReg__log_reg_22_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_54 = iwb_stage_iReg__log_reg_22_T_53 | iwb_stage_iReg__log_reg_22_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_55 = iwb_stage_iReg__log_reg_22_T_54 | iwb_stage_iReg__log_reg_22_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_56 = iwb_stage_iReg__log_reg_22_T_55 | iwb_stage_iReg__log_reg_22_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_57 = iwb_stage_iReg__log_reg_22_T_56 | iwb_stage_iReg__log_reg_22_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_58 = iwb_stage_iReg__log_reg_22_T_57 | iwb_stage_iReg__log_reg_22_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_59 = iwb_stage_iReg__log_reg_22_T_58 | iwb_stage_iReg__log_reg_22_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_60 = iwb_stage_iReg__log_reg_22_T_59 | iwb_stage_iReg__log_reg_22_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_61 = iwb_stage_iReg__log_reg_22_T_60 | iwb_stage_iReg__log_reg_22_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_62 = iwb_stage_iReg__log_reg_22_T_61 | iwb_stage_iReg__log_reg_22_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_22_T_63 = iwb_stage_iReg__log_reg_22_T_62 | iwb_stage_iReg__log_reg_22_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_22_T_64 = iwb_stage_iReg__log_reg_22_T_63 ? iwb_stage_iReg_log_reg_22 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_23_T = iwb_stage_iReg_archit_ptr_0 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h17; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_23_T_33 = iwb_stage_iReg__log_reg_23_T | iwb_stage_iReg__log_reg_23_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_34 = iwb_stage_iReg__log_reg_23_T_33 | iwb_stage_iReg__log_reg_23_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_35 = iwb_stage_iReg__log_reg_23_T_34 | iwb_stage_iReg__log_reg_23_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_36 = iwb_stage_iReg__log_reg_23_T_35 | iwb_stage_iReg__log_reg_23_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_37 = iwb_stage_iReg__log_reg_23_T_36 | iwb_stage_iReg__log_reg_23_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_38 = iwb_stage_iReg__log_reg_23_T_37 | iwb_stage_iReg__log_reg_23_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_39 = iwb_stage_iReg__log_reg_23_T_38 | iwb_stage_iReg__log_reg_23_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_40 = iwb_stage_iReg__log_reg_23_T_39 | iwb_stage_iReg__log_reg_23_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_41 = iwb_stage_iReg__log_reg_23_T_40 | iwb_stage_iReg__log_reg_23_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_42 = iwb_stage_iReg__log_reg_23_T_41 | iwb_stage_iReg__log_reg_23_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_43 = iwb_stage_iReg__log_reg_23_T_42 | iwb_stage_iReg__log_reg_23_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_44 = iwb_stage_iReg__log_reg_23_T_43 | iwb_stage_iReg__log_reg_23_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_45 = iwb_stage_iReg__log_reg_23_T_44 | iwb_stage_iReg__log_reg_23_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_46 = iwb_stage_iReg__log_reg_23_T_45 | iwb_stage_iReg__log_reg_23_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_47 = iwb_stage_iReg__log_reg_23_T_46 | iwb_stage_iReg__log_reg_23_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_48 = iwb_stage_iReg__log_reg_23_T_47 | iwb_stage_iReg__log_reg_23_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_49 = iwb_stage_iReg__log_reg_23_T_48 | iwb_stage_iReg__log_reg_23_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_50 = iwb_stage_iReg__log_reg_23_T_49 | iwb_stage_iReg__log_reg_23_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_51 = iwb_stage_iReg__log_reg_23_T_50 | iwb_stage_iReg__log_reg_23_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_52 = iwb_stage_iReg__log_reg_23_T_51 | iwb_stage_iReg__log_reg_23_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_53 = iwb_stage_iReg__log_reg_23_T_52 | iwb_stage_iReg__log_reg_23_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_54 = iwb_stage_iReg__log_reg_23_T_53 | iwb_stage_iReg__log_reg_23_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_55 = iwb_stage_iReg__log_reg_23_T_54 | iwb_stage_iReg__log_reg_23_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_56 = iwb_stage_iReg__log_reg_23_T_55 | iwb_stage_iReg__log_reg_23_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_57 = iwb_stage_iReg__log_reg_23_T_56 | iwb_stage_iReg__log_reg_23_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_58 = iwb_stage_iReg__log_reg_23_T_57 | iwb_stage_iReg__log_reg_23_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_59 = iwb_stage_iReg__log_reg_23_T_58 | iwb_stage_iReg__log_reg_23_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_60 = iwb_stage_iReg__log_reg_23_T_59 | iwb_stage_iReg__log_reg_23_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_61 = iwb_stage_iReg__log_reg_23_T_60 | iwb_stage_iReg__log_reg_23_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_62 = iwb_stage_iReg__log_reg_23_T_61 | iwb_stage_iReg__log_reg_23_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_23_T_63 = iwb_stage_iReg__log_reg_23_T_62 | iwb_stage_iReg__log_reg_23_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_23_T_64 = iwb_stage_iReg__log_reg_23_T_63 ? iwb_stage_iReg_log_reg_23 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_24_T = iwb_stage_iReg_archit_ptr_0 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h18; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_24_T_33 = iwb_stage_iReg__log_reg_24_T | iwb_stage_iReg__log_reg_24_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_34 = iwb_stage_iReg__log_reg_24_T_33 | iwb_stage_iReg__log_reg_24_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_35 = iwb_stage_iReg__log_reg_24_T_34 | iwb_stage_iReg__log_reg_24_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_36 = iwb_stage_iReg__log_reg_24_T_35 | iwb_stage_iReg__log_reg_24_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_37 = iwb_stage_iReg__log_reg_24_T_36 | iwb_stage_iReg__log_reg_24_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_38 = iwb_stage_iReg__log_reg_24_T_37 | iwb_stage_iReg__log_reg_24_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_39 = iwb_stage_iReg__log_reg_24_T_38 | iwb_stage_iReg__log_reg_24_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_40 = iwb_stage_iReg__log_reg_24_T_39 | iwb_stage_iReg__log_reg_24_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_41 = iwb_stage_iReg__log_reg_24_T_40 | iwb_stage_iReg__log_reg_24_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_42 = iwb_stage_iReg__log_reg_24_T_41 | iwb_stage_iReg__log_reg_24_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_43 = iwb_stage_iReg__log_reg_24_T_42 | iwb_stage_iReg__log_reg_24_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_44 = iwb_stage_iReg__log_reg_24_T_43 | iwb_stage_iReg__log_reg_24_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_45 = iwb_stage_iReg__log_reg_24_T_44 | iwb_stage_iReg__log_reg_24_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_46 = iwb_stage_iReg__log_reg_24_T_45 | iwb_stage_iReg__log_reg_24_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_47 = iwb_stage_iReg__log_reg_24_T_46 | iwb_stage_iReg__log_reg_24_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_48 = iwb_stage_iReg__log_reg_24_T_47 | iwb_stage_iReg__log_reg_24_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_49 = iwb_stage_iReg__log_reg_24_T_48 | iwb_stage_iReg__log_reg_24_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_50 = iwb_stage_iReg__log_reg_24_T_49 | iwb_stage_iReg__log_reg_24_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_51 = iwb_stage_iReg__log_reg_24_T_50 | iwb_stage_iReg__log_reg_24_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_52 = iwb_stage_iReg__log_reg_24_T_51 | iwb_stage_iReg__log_reg_24_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_53 = iwb_stage_iReg__log_reg_24_T_52 | iwb_stage_iReg__log_reg_24_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_54 = iwb_stage_iReg__log_reg_24_T_53 | iwb_stage_iReg__log_reg_24_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_55 = iwb_stage_iReg__log_reg_24_T_54 | iwb_stage_iReg__log_reg_24_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_56 = iwb_stage_iReg__log_reg_24_T_55 | iwb_stage_iReg__log_reg_24_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_57 = iwb_stage_iReg__log_reg_24_T_56 | iwb_stage_iReg__log_reg_24_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_58 = iwb_stage_iReg__log_reg_24_T_57 | iwb_stage_iReg__log_reg_24_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_59 = iwb_stage_iReg__log_reg_24_T_58 | iwb_stage_iReg__log_reg_24_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_60 = iwb_stage_iReg__log_reg_24_T_59 | iwb_stage_iReg__log_reg_24_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_61 = iwb_stage_iReg__log_reg_24_T_60 | iwb_stage_iReg__log_reg_24_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_62 = iwb_stage_iReg__log_reg_24_T_61 | iwb_stage_iReg__log_reg_24_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_24_T_63 = iwb_stage_iReg__log_reg_24_T_62 | iwb_stage_iReg__log_reg_24_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_24_T_64 = iwb_stage_iReg__log_reg_24_T_63 ? iwb_stage_iReg_log_reg_24 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_25_T = iwb_stage_iReg_archit_ptr_0 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h19; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_25_T_33 = iwb_stage_iReg__log_reg_25_T | iwb_stage_iReg__log_reg_25_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_34 = iwb_stage_iReg__log_reg_25_T_33 | iwb_stage_iReg__log_reg_25_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_35 = iwb_stage_iReg__log_reg_25_T_34 | iwb_stage_iReg__log_reg_25_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_36 = iwb_stage_iReg__log_reg_25_T_35 | iwb_stage_iReg__log_reg_25_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_37 = iwb_stage_iReg__log_reg_25_T_36 | iwb_stage_iReg__log_reg_25_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_38 = iwb_stage_iReg__log_reg_25_T_37 | iwb_stage_iReg__log_reg_25_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_39 = iwb_stage_iReg__log_reg_25_T_38 | iwb_stage_iReg__log_reg_25_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_40 = iwb_stage_iReg__log_reg_25_T_39 | iwb_stage_iReg__log_reg_25_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_41 = iwb_stage_iReg__log_reg_25_T_40 | iwb_stage_iReg__log_reg_25_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_42 = iwb_stage_iReg__log_reg_25_T_41 | iwb_stage_iReg__log_reg_25_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_43 = iwb_stage_iReg__log_reg_25_T_42 | iwb_stage_iReg__log_reg_25_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_44 = iwb_stage_iReg__log_reg_25_T_43 | iwb_stage_iReg__log_reg_25_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_45 = iwb_stage_iReg__log_reg_25_T_44 | iwb_stage_iReg__log_reg_25_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_46 = iwb_stage_iReg__log_reg_25_T_45 | iwb_stage_iReg__log_reg_25_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_47 = iwb_stage_iReg__log_reg_25_T_46 | iwb_stage_iReg__log_reg_25_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_48 = iwb_stage_iReg__log_reg_25_T_47 | iwb_stage_iReg__log_reg_25_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_49 = iwb_stage_iReg__log_reg_25_T_48 | iwb_stage_iReg__log_reg_25_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_50 = iwb_stage_iReg__log_reg_25_T_49 | iwb_stage_iReg__log_reg_25_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_51 = iwb_stage_iReg__log_reg_25_T_50 | iwb_stage_iReg__log_reg_25_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_52 = iwb_stage_iReg__log_reg_25_T_51 | iwb_stage_iReg__log_reg_25_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_53 = iwb_stage_iReg__log_reg_25_T_52 | iwb_stage_iReg__log_reg_25_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_54 = iwb_stage_iReg__log_reg_25_T_53 | iwb_stage_iReg__log_reg_25_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_55 = iwb_stage_iReg__log_reg_25_T_54 | iwb_stage_iReg__log_reg_25_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_56 = iwb_stage_iReg__log_reg_25_T_55 | iwb_stage_iReg__log_reg_25_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_57 = iwb_stage_iReg__log_reg_25_T_56 | iwb_stage_iReg__log_reg_25_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_58 = iwb_stage_iReg__log_reg_25_T_57 | iwb_stage_iReg__log_reg_25_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_59 = iwb_stage_iReg__log_reg_25_T_58 | iwb_stage_iReg__log_reg_25_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_60 = iwb_stage_iReg__log_reg_25_T_59 | iwb_stage_iReg__log_reg_25_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_61 = iwb_stage_iReg__log_reg_25_T_60 | iwb_stage_iReg__log_reg_25_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_62 = iwb_stage_iReg__log_reg_25_T_61 | iwb_stage_iReg__log_reg_25_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_25_T_63 = iwb_stage_iReg__log_reg_25_T_62 | iwb_stage_iReg__log_reg_25_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_25_T_64 = iwb_stage_iReg__log_reg_25_T_63 ? iwb_stage_iReg_log_reg_25 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_26_T = iwb_stage_iReg_archit_ptr_0 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h1a; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_26_T_33 = iwb_stage_iReg__log_reg_26_T | iwb_stage_iReg__log_reg_26_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_34 = iwb_stage_iReg__log_reg_26_T_33 | iwb_stage_iReg__log_reg_26_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_35 = iwb_stage_iReg__log_reg_26_T_34 | iwb_stage_iReg__log_reg_26_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_36 = iwb_stage_iReg__log_reg_26_T_35 | iwb_stage_iReg__log_reg_26_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_37 = iwb_stage_iReg__log_reg_26_T_36 | iwb_stage_iReg__log_reg_26_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_38 = iwb_stage_iReg__log_reg_26_T_37 | iwb_stage_iReg__log_reg_26_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_39 = iwb_stage_iReg__log_reg_26_T_38 | iwb_stage_iReg__log_reg_26_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_40 = iwb_stage_iReg__log_reg_26_T_39 | iwb_stage_iReg__log_reg_26_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_41 = iwb_stage_iReg__log_reg_26_T_40 | iwb_stage_iReg__log_reg_26_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_42 = iwb_stage_iReg__log_reg_26_T_41 | iwb_stage_iReg__log_reg_26_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_43 = iwb_stage_iReg__log_reg_26_T_42 | iwb_stage_iReg__log_reg_26_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_44 = iwb_stage_iReg__log_reg_26_T_43 | iwb_stage_iReg__log_reg_26_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_45 = iwb_stage_iReg__log_reg_26_T_44 | iwb_stage_iReg__log_reg_26_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_46 = iwb_stage_iReg__log_reg_26_T_45 | iwb_stage_iReg__log_reg_26_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_47 = iwb_stage_iReg__log_reg_26_T_46 | iwb_stage_iReg__log_reg_26_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_48 = iwb_stage_iReg__log_reg_26_T_47 | iwb_stage_iReg__log_reg_26_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_49 = iwb_stage_iReg__log_reg_26_T_48 | iwb_stage_iReg__log_reg_26_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_50 = iwb_stage_iReg__log_reg_26_T_49 | iwb_stage_iReg__log_reg_26_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_51 = iwb_stage_iReg__log_reg_26_T_50 | iwb_stage_iReg__log_reg_26_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_52 = iwb_stage_iReg__log_reg_26_T_51 | iwb_stage_iReg__log_reg_26_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_53 = iwb_stage_iReg__log_reg_26_T_52 | iwb_stage_iReg__log_reg_26_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_54 = iwb_stage_iReg__log_reg_26_T_53 | iwb_stage_iReg__log_reg_26_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_55 = iwb_stage_iReg__log_reg_26_T_54 | iwb_stage_iReg__log_reg_26_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_56 = iwb_stage_iReg__log_reg_26_T_55 | iwb_stage_iReg__log_reg_26_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_57 = iwb_stage_iReg__log_reg_26_T_56 | iwb_stage_iReg__log_reg_26_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_58 = iwb_stage_iReg__log_reg_26_T_57 | iwb_stage_iReg__log_reg_26_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_59 = iwb_stage_iReg__log_reg_26_T_58 | iwb_stage_iReg__log_reg_26_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_60 = iwb_stage_iReg__log_reg_26_T_59 | iwb_stage_iReg__log_reg_26_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_61 = iwb_stage_iReg__log_reg_26_T_60 | iwb_stage_iReg__log_reg_26_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_62 = iwb_stage_iReg__log_reg_26_T_61 | iwb_stage_iReg__log_reg_26_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_26_T_63 = iwb_stage_iReg__log_reg_26_T_62 | iwb_stage_iReg__log_reg_26_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_26_T_64 = iwb_stage_iReg__log_reg_26_T_63 ? iwb_stage_iReg_log_reg_26 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_27_T = iwb_stage_iReg_archit_ptr_0 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h1b; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_27_T_33 = iwb_stage_iReg__log_reg_27_T | iwb_stage_iReg__log_reg_27_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_34 = iwb_stage_iReg__log_reg_27_T_33 | iwb_stage_iReg__log_reg_27_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_35 = iwb_stage_iReg__log_reg_27_T_34 | iwb_stage_iReg__log_reg_27_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_36 = iwb_stage_iReg__log_reg_27_T_35 | iwb_stage_iReg__log_reg_27_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_37 = iwb_stage_iReg__log_reg_27_T_36 | iwb_stage_iReg__log_reg_27_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_38 = iwb_stage_iReg__log_reg_27_T_37 | iwb_stage_iReg__log_reg_27_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_39 = iwb_stage_iReg__log_reg_27_T_38 | iwb_stage_iReg__log_reg_27_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_40 = iwb_stage_iReg__log_reg_27_T_39 | iwb_stage_iReg__log_reg_27_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_41 = iwb_stage_iReg__log_reg_27_T_40 | iwb_stage_iReg__log_reg_27_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_42 = iwb_stage_iReg__log_reg_27_T_41 | iwb_stage_iReg__log_reg_27_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_43 = iwb_stage_iReg__log_reg_27_T_42 | iwb_stage_iReg__log_reg_27_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_44 = iwb_stage_iReg__log_reg_27_T_43 | iwb_stage_iReg__log_reg_27_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_45 = iwb_stage_iReg__log_reg_27_T_44 | iwb_stage_iReg__log_reg_27_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_46 = iwb_stage_iReg__log_reg_27_T_45 | iwb_stage_iReg__log_reg_27_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_47 = iwb_stage_iReg__log_reg_27_T_46 | iwb_stage_iReg__log_reg_27_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_48 = iwb_stage_iReg__log_reg_27_T_47 | iwb_stage_iReg__log_reg_27_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_49 = iwb_stage_iReg__log_reg_27_T_48 | iwb_stage_iReg__log_reg_27_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_50 = iwb_stage_iReg__log_reg_27_T_49 | iwb_stage_iReg__log_reg_27_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_51 = iwb_stage_iReg__log_reg_27_T_50 | iwb_stage_iReg__log_reg_27_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_52 = iwb_stage_iReg__log_reg_27_T_51 | iwb_stage_iReg__log_reg_27_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_53 = iwb_stage_iReg__log_reg_27_T_52 | iwb_stage_iReg__log_reg_27_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_54 = iwb_stage_iReg__log_reg_27_T_53 | iwb_stage_iReg__log_reg_27_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_55 = iwb_stage_iReg__log_reg_27_T_54 | iwb_stage_iReg__log_reg_27_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_56 = iwb_stage_iReg__log_reg_27_T_55 | iwb_stage_iReg__log_reg_27_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_57 = iwb_stage_iReg__log_reg_27_T_56 | iwb_stage_iReg__log_reg_27_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_58 = iwb_stage_iReg__log_reg_27_T_57 | iwb_stage_iReg__log_reg_27_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_59 = iwb_stage_iReg__log_reg_27_T_58 | iwb_stage_iReg__log_reg_27_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_60 = iwb_stage_iReg__log_reg_27_T_59 | iwb_stage_iReg__log_reg_27_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_61 = iwb_stage_iReg__log_reg_27_T_60 | iwb_stage_iReg__log_reg_27_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_62 = iwb_stage_iReg__log_reg_27_T_61 | iwb_stage_iReg__log_reg_27_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_27_T_63 = iwb_stage_iReg__log_reg_27_T_62 | iwb_stage_iReg__log_reg_27_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_27_T_64 = iwb_stage_iReg__log_reg_27_T_63 ? iwb_stage_iReg_log_reg_27 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_28_T = iwb_stage_iReg_archit_ptr_0 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h1c; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_28_T_33 = iwb_stage_iReg__log_reg_28_T | iwb_stage_iReg__log_reg_28_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_34 = iwb_stage_iReg__log_reg_28_T_33 | iwb_stage_iReg__log_reg_28_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_35 = iwb_stage_iReg__log_reg_28_T_34 | iwb_stage_iReg__log_reg_28_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_36 = iwb_stage_iReg__log_reg_28_T_35 | iwb_stage_iReg__log_reg_28_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_37 = iwb_stage_iReg__log_reg_28_T_36 | iwb_stage_iReg__log_reg_28_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_38 = iwb_stage_iReg__log_reg_28_T_37 | iwb_stage_iReg__log_reg_28_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_39 = iwb_stage_iReg__log_reg_28_T_38 | iwb_stage_iReg__log_reg_28_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_40 = iwb_stage_iReg__log_reg_28_T_39 | iwb_stage_iReg__log_reg_28_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_41 = iwb_stage_iReg__log_reg_28_T_40 | iwb_stage_iReg__log_reg_28_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_42 = iwb_stage_iReg__log_reg_28_T_41 | iwb_stage_iReg__log_reg_28_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_43 = iwb_stage_iReg__log_reg_28_T_42 | iwb_stage_iReg__log_reg_28_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_44 = iwb_stage_iReg__log_reg_28_T_43 | iwb_stage_iReg__log_reg_28_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_45 = iwb_stage_iReg__log_reg_28_T_44 | iwb_stage_iReg__log_reg_28_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_46 = iwb_stage_iReg__log_reg_28_T_45 | iwb_stage_iReg__log_reg_28_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_47 = iwb_stage_iReg__log_reg_28_T_46 | iwb_stage_iReg__log_reg_28_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_48 = iwb_stage_iReg__log_reg_28_T_47 | iwb_stage_iReg__log_reg_28_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_49 = iwb_stage_iReg__log_reg_28_T_48 | iwb_stage_iReg__log_reg_28_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_50 = iwb_stage_iReg__log_reg_28_T_49 | iwb_stage_iReg__log_reg_28_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_51 = iwb_stage_iReg__log_reg_28_T_50 | iwb_stage_iReg__log_reg_28_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_52 = iwb_stage_iReg__log_reg_28_T_51 | iwb_stage_iReg__log_reg_28_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_53 = iwb_stage_iReg__log_reg_28_T_52 | iwb_stage_iReg__log_reg_28_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_54 = iwb_stage_iReg__log_reg_28_T_53 | iwb_stage_iReg__log_reg_28_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_55 = iwb_stage_iReg__log_reg_28_T_54 | iwb_stage_iReg__log_reg_28_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_56 = iwb_stage_iReg__log_reg_28_T_55 | iwb_stage_iReg__log_reg_28_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_57 = iwb_stage_iReg__log_reg_28_T_56 | iwb_stage_iReg__log_reg_28_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_58 = iwb_stage_iReg__log_reg_28_T_57 | iwb_stage_iReg__log_reg_28_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_59 = iwb_stage_iReg__log_reg_28_T_58 | iwb_stage_iReg__log_reg_28_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_60 = iwb_stage_iReg__log_reg_28_T_59 | iwb_stage_iReg__log_reg_28_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_61 = iwb_stage_iReg__log_reg_28_T_60 | iwb_stage_iReg__log_reg_28_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_62 = iwb_stage_iReg__log_reg_28_T_61 | iwb_stage_iReg__log_reg_28_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_28_T_63 = iwb_stage_iReg__log_reg_28_T_62 | iwb_stage_iReg__log_reg_28_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_28_T_64 = iwb_stage_iReg__log_reg_28_T_63 ? iwb_stage_iReg_log_reg_28 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_29_T = iwb_stage_iReg_archit_ptr_0 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h1d; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_29_T_33 = iwb_stage_iReg__log_reg_29_T | iwb_stage_iReg__log_reg_29_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_34 = iwb_stage_iReg__log_reg_29_T_33 | iwb_stage_iReg__log_reg_29_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_35 = iwb_stage_iReg__log_reg_29_T_34 | iwb_stage_iReg__log_reg_29_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_36 = iwb_stage_iReg__log_reg_29_T_35 | iwb_stage_iReg__log_reg_29_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_37 = iwb_stage_iReg__log_reg_29_T_36 | iwb_stage_iReg__log_reg_29_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_38 = iwb_stage_iReg__log_reg_29_T_37 | iwb_stage_iReg__log_reg_29_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_39 = iwb_stage_iReg__log_reg_29_T_38 | iwb_stage_iReg__log_reg_29_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_40 = iwb_stage_iReg__log_reg_29_T_39 | iwb_stage_iReg__log_reg_29_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_41 = iwb_stage_iReg__log_reg_29_T_40 | iwb_stage_iReg__log_reg_29_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_42 = iwb_stage_iReg__log_reg_29_T_41 | iwb_stage_iReg__log_reg_29_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_43 = iwb_stage_iReg__log_reg_29_T_42 | iwb_stage_iReg__log_reg_29_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_44 = iwb_stage_iReg__log_reg_29_T_43 | iwb_stage_iReg__log_reg_29_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_45 = iwb_stage_iReg__log_reg_29_T_44 | iwb_stage_iReg__log_reg_29_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_46 = iwb_stage_iReg__log_reg_29_T_45 | iwb_stage_iReg__log_reg_29_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_47 = iwb_stage_iReg__log_reg_29_T_46 | iwb_stage_iReg__log_reg_29_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_48 = iwb_stage_iReg__log_reg_29_T_47 | iwb_stage_iReg__log_reg_29_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_49 = iwb_stage_iReg__log_reg_29_T_48 | iwb_stage_iReg__log_reg_29_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_50 = iwb_stage_iReg__log_reg_29_T_49 | iwb_stage_iReg__log_reg_29_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_51 = iwb_stage_iReg__log_reg_29_T_50 | iwb_stage_iReg__log_reg_29_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_52 = iwb_stage_iReg__log_reg_29_T_51 | iwb_stage_iReg__log_reg_29_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_53 = iwb_stage_iReg__log_reg_29_T_52 | iwb_stage_iReg__log_reg_29_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_54 = iwb_stage_iReg__log_reg_29_T_53 | iwb_stage_iReg__log_reg_29_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_55 = iwb_stage_iReg__log_reg_29_T_54 | iwb_stage_iReg__log_reg_29_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_56 = iwb_stage_iReg__log_reg_29_T_55 | iwb_stage_iReg__log_reg_29_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_57 = iwb_stage_iReg__log_reg_29_T_56 | iwb_stage_iReg__log_reg_29_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_58 = iwb_stage_iReg__log_reg_29_T_57 | iwb_stage_iReg__log_reg_29_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_59 = iwb_stage_iReg__log_reg_29_T_58 | iwb_stage_iReg__log_reg_29_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_60 = iwb_stage_iReg__log_reg_29_T_59 | iwb_stage_iReg__log_reg_29_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_61 = iwb_stage_iReg__log_reg_29_T_60 | iwb_stage_iReg__log_reg_29_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_62 = iwb_stage_iReg__log_reg_29_T_61 | iwb_stage_iReg__log_reg_29_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_29_T_63 = iwb_stage_iReg__log_reg_29_T_62 | iwb_stage_iReg__log_reg_29_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_29_T_64 = iwb_stage_iReg__log_reg_29_T_63 ? iwb_stage_iReg_log_reg_29 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_30_T = iwb_stage_iReg_archit_ptr_0 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h1e; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_30_T_33 = iwb_stage_iReg__log_reg_30_T | iwb_stage_iReg__log_reg_30_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_34 = iwb_stage_iReg__log_reg_30_T_33 | iwb_stage_iReg__log_reg_30_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_35 = iwb_stage_iReg__log_reg_30_T_34 | iwb_stage_iReg__log_reg_30_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_36 = iwb_stage_iReg__log_reg_30_T_35 | iwb_stage_iReg__log_reg_30_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_37 = iwb_stage_iReg__log_reg_30_T_36 | iwb_stage_iReg__log_reg_30_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_38 = iwb_stage_iReg__log_reg_30_T_37 | iwb_stage_iReg__log_reg_30_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_39 = iwb_stage_iReg__log_reg_30_T_38 | iwb_stage_iReg__log_reg_30_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_40 = iwb_stage_iReg__log_reg_30_T_39 | iwb_stage_iReg__log_reg_30_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_41 = iwb_stage_iReg__log_reg_30_T_40 | iwb_stage_iReg__log_reg_30_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_42 = iwb_stage_iReg__log_reg_30_T_41 | iwb_stage_iReg__log_reg_30_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_43 = iwb_stage_iReg__log_reg_30_T_42 | iwb_stage_iReg__log_reg_30_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_44 = iwb_stage_iReg__log_reg_30_T_43 | iwb_stage_iReg__log_reg_30_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_45 = iwb_stage_iReg__log_reg_30_T_44 | iwb_stage_iReg__log_reg_30_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_46 = iwb_stage_iReg__log_reg_30_T_45 | iwb_stage_iReg__log_reg_30_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_47 = iwb_stage_iReg__log_reg_30_T_46 | iwb_stage_iReg__log_reg_30_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_48 = iwb_stage_iReg__log_reg_30_T_47 | iwb_stage_iReg__log_reg_30_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_49 = iwb_stage_iReg__log_reg_30_T_48 | iwb_stage_iReg__log_reg_30_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_50 = iwb_stage_iReg__log_reg_30_T_49 | iwb_stage_iReg__log_reg_30_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_51 = iwb_stage_iReg__log_reg_30_T_50 | iwb_stage_iReg__log_reg_30_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_52 = iwb_stage_iReg__log_reg_30_T_51 | iwb_stage_iReg__log_reg_30_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_53 = iwb_stage_iReg__log_reg_30_T_52 | iwb_stage_iReg__log_reg_30_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_54 = iwb_stage_iReg__log_reg_30_T_53 | iwb_stage_iReg__log_reg_30_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_55 = iwb_stage_iReg__log_reg_30_T_54 | iwb_stage_iReg__log_reg_30_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_56 = iwb_stage_iReg__log_reg_30_T_55 | iwb_stage_iReg__log_reg_30_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_57 = iwb_stage_iReg__log_reg_30_T_56 | iwb_stage_iReg__log_reg_30_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_58 = iwb_stage_iReg__log_reg_30_T_57 | iwb_stage_iReg__log_reg_30_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_59 = iwb_stage_iReg__log_reg_30_T_58 | iwb_stage_iReg__log_reg_30_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_60 = iwb_stage_iReg__log_reg_30_T_59 | iwb_stage_iReg__log_reg_30_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_61 = iwb_stage_iReg__log_reg_30_T_60 | iwb_stage_iReg__log_reg_30_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_62 = iwb_stage_iReg__log_reg_30_T_61 | iwb_stage_iReg__log_reg_30_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_30_T_63 = iwb_stage_iReg__log_reg_30_T_62 | iwb_stage_iReg__log_reg_30_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_30_T_64 = iwb_stage_iReg__log_reg_30_T_63 ? iwb_stage_iReg_log_reg_30 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_31_T = iwb_stage_iReg_archit_ptr_0 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h1f; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_31_T_33 = iwb_stage_iReg__log_reg_31_T | iwb_stage_iReg__log_reg_31_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_34 = iwb_stage_iReg__log_reg_31_T_33 | iwb_stage_iReg__log_reg_31_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_35 = iwb_stage_iReg__log_reg_31_T_34 | iwb_stage_iReg__log_reg_31_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_36 = iwb_stage_iReg__log_reg_31_T_35 | iwb_stage_iReg__log_reg_31_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_37 = iwb_stage_iReg__log_reg_31_T_36 | iwb_stage_iReg__log_reg_31_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_38 = iwb_stage_iReg__log_reg_31_T_37 | iwb_stage_iReg__log_reg_31_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_39 = iwb_stage_iReg__log_reg_31_T_38 | iwb_stage_iReg__log_reg_31_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_40 = iwb_stage_iReg__log_reg_31_T_39 | iwb_stage_iReg__log_reg_31_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_41 = iwb_stage_iReg__log_reg_31_T_40 | iwb_stage_iReg__log_reg_31_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_42 = iwb_stage_iReg__log_reg_31_T_41 | iwb_stage_iReg__log_reg_31_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_43 = iwb_stage_iReg__log_reg_31_T_42 | iwb_stage_iReg__log_reg_31_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_44 = iwb_stage_iReg__log_reg_31_T_43 | iwb_stage_iReg__log_reg_31_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_45 = iwb_stage_iReg__log_reg_31_T_44 | iwb_stage_iReg__log_reg_31_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_46 = iwb_stage_iReg__log_reg_31_T_45 | iwb_stage_iReg__log_reg_31_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_47 = iwb_stage_iReg__log_reg_31_T_46 | iwb_stage_iReg__log_reg_31_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_48 = iwb_stage_iReg__log_reg_31_T_47 | iwb_stage_iReg__log_reg_31_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_49 = iwb_stage_iReg__log_reg_31_T_48 | iwb_stage_iReg__log_reg_31_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_50 = iwb_stage_iReg__log_reg_31_T_49 | iwb_stage_iReg__log_reg_31_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_51 = iwb_stage_iReg__log_reg_31_T_50 | iwb_stage_iReg__log_reg_31_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_52 = iwb_stage_iReg__log_reg_31_T_51 | iwb_stage_iReg__log_reg_31_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_53 = iwb_stage_iReg__log_reg_31_T_52 | iwb_stage_iReg__log_reg_31_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_54 = iwb_stage_iReg__log_reg_31_T_53 | iwb_stage_iReg__log_reg_31_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_55 = iwb_stage_iReg__log_reg_31_T_54 | iwb_stage_iReg__log_reg_31_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_56 = iwb_stage_iReg__log_reg_31_T_55 | iwb_stage_iReg__log_reg_31_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_57 = iwb_stage_iReg__log_reg_31_T_56 | iwb_stage_iReg__log_reg_31_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_58 = iwb_stage_iReg__log_reg_31_T_57 | iwb_stage_iReg__log_reg_31_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_59 = iwb_stage_iReg__log_reg_31_T_58 | iwb_stage_iReg__log_reg_31_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_60 = iwb_stage_iReg__log_reg_31_T_59 | iwb_stage_iReg__log_reg_31_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_61 = iwb_stage_iReg__log_reg_31_T_60 | iwb_stage_iReg__log_reg_31_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_62 = iwb_stage_iReg__log_reg_31_T_61 | iwb_stage_iReg__log_reg_31_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_31_T_63 = iwb_stage_iReg__log_reg_31_T_62 | iwb_stage_iReg__log_reg_31_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_31_T_64 = iwb_stage_iReg__log_reg_31_T_63 ? iwb_stage_iReg_log_reg_31 : 2'h0; // @[Regfiles.scala 223:63]
  wire  iwb_stage_iReg__log_reg_32_T = iwb_stage_iReg_archit_ptr_0 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_1 = iwb_stage_iReg_archit_ptr_1 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_2 = iwb_stage_iReg_archit_ptr_2 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_3 = iwb_stage_iReg_archit_ptr_3 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_4 = iwb_stage_iReg_archit_ptr_4 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_5 = iwb_stage_iReg_archit_ptr_5 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_6 = iwb_stage_iReg_archit_ptr_6 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_7 = iwb_stage_iReg_archit_ptr_7 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_8 = iwb_stage_iReg_archit_ptr_8 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_9 = iwb_stage_iReg_archit_ptr_9 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_10 = iwb_stage_iReg_archit_ptr_10 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_11 = iwb_stage_iReg_archit_ptr_11 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_12 = iwb_stage_iReg_archit_ptr_12 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_13 = iwb_stage_iReg_archit_ptr_13 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_14 = iwb_stage_iReg_archit_ptr_14 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_15 = iwb_stage_iReg_archit_ptr_15 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_16 = iwb_stage_iReg_archit_ptr_16 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_17 = iwb_stage_iReg_archit_ptr_17 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_18 = iwb_stage_iReg_archit_ptr_18 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_19 = iwb_stage_iReg_archit_ptr_19 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_20 = iwb_stage_iReg_archit_ptr_20 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_21 = iwb_stage_iReg_archit_ptr_21 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_22 = iwb_stage_iReg_archit_ptr_22 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_23 = iwb_stage_iReg_archit_ptr_23 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_24 = iwb_stage_iReg_archit_ptr_24 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_25 = iwb_stage_iReg_archit_ptr_25 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_26 = iwb_stage_iReg_archit_ptr_26 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_27 = iwb_stage_iReg_archit_ptr_27 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_28 = iwb_stage_iReg_archit_ptr_28 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_29 = iwb_stage_iReg_archit_ptr_29 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_30 = iwb_stage_iReg_archit_ptr_30 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_31 = iwb_stage_iReg_archit_ptr_31 == 6'h20; // @[Regfiles.scala 223:99]
  wire  iwb_stage_iReg__log_reg_32_T_33 = iwb_stage_iReg__log_reg_32_T | iwb_stage_iReg__log_reg_32_T_1; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_34 = iwb_stage_iReg__log_reg_32_T_33 | iwb_stage_iReg__log_reg_32_T_2; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_35 = iwb_stage_iReg__log_reg_32_T_34 | iwb_stage_iReg__log_reg_32_T_3; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_36 = iwb_stage_iReg__log_reg_32_T_35 | iwb_stage_iReg__log_reg_32_T_4; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_37 = iwb_stage_iReg__log_reg_32_T_36 | iwb_stage_iReg__log_reg_32_T_5; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_38 = iwb_stage_iReg__log_reg_32_T_37 | iwb_stage_iReg__log_reg_32_T_6; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_39 = iwb_stage_iReg__log_reg_32_T_38 | iwb_stage_iReg__log_reg_32_T_7; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_40 = iwb_stage_iReg__log_reg_32_T_39 | iwb_stage_iReg__log_reg_32_T_8; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_41 = iwb_stage_iReg__log_reg_32_T_40 | iwb_stage_iReg__log_reg_32_T_9; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_42 = iwb_stage_iReg__log_reg_32_T_41 | iwb_stage_iReg__log_reg_32_T_10; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_43 = iwb_stage_iReg__log_reg_32_T_42 | iwb_stage_iReg__log_reg_32_T_11; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_44 = iwb_stage_iReg__log_reg_32_T_43 | iwb_stage_iReg__log_reg_32_T_12; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_45 = iwb_stage_iReg__log_reg_32_T_44 | iwb_stage_iReg__log_reg_32_T_13; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_46 = iwb_stage_iReg__log_reg_32_T_45 | iwb_stage_iReg__log_reg_32_T_14; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_47 = iwb_stage_iReg__log_reg_32_T_46 | iwb_stage_iReg__log_reg_32_T_15; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_48 = iwb_stage_iReg__log_reg_32_T_47 | iwb_stage_iReg__log_reg_32_T_16; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_49 = iwb_stage_iReg__log_reg_32_T_48 | iwb_stage_iReg__log_reg_32_T_17; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_50 = iwb_stage_iReg__log_reg_32_T_49 | iwb_stage_iReg__log_reg_32_T_18; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_51 = iwb_stage_iReg__log_reg_32_T_50 | iwb_stage_iReg__log_reg_32_T_19; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_52 = iwb_stage_iReg__log_reg_32_T_51 | iwb_stage_iReg__log_reg_32_T_20; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_53 = iwb_stage_iReg__log_reg_32_T_52 | iwb_stage_iReg__log_reg_32_T_21; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_54 = iwb_stage_iReg__log_reg_32_T_53 | iwb_stage_iReg__log_reg_32_T_22; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_55 = iwb_stage_iReg__log_reg_32_T_54 | iwb_stage_iReg__log_reg_32_T_23; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_56 = iwb_stage_iReg__log_reg_32_T_55 | iwb_stage_iReg__log_reg_32_T_24; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_57 = iwb_stage_iReg__log_reg_32_T_56 | iwb_stage_iReg__log_reg_32_T_25; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_58 = iwb_stage_iReg__log_reg_32_T_57 | iwb_stage_iReg__log_reg_32_T_26; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_59 = iwb_stage_iReg__log_reg_32_T_58 | iwb_stage_iReg__log_reg_32_T_27; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_60 = iwb_stage_iReg__log_reg_32_T_59 | iwb_stage_iReg__log_reg_32_T_28; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_61 = iwb_stage_iReg__log_reg_32_T_60 | iwb_stage_iReg__log_reg_32_T_29; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_62 = iwb_stage_iReg__log_reg_32_T_61 | iwb_stage_iReg__log_reg_32_T_30; // @[Regfiles.scala 223:82]
  wire  iwb_stage_iReg__log_reg_32_T_63 = iwb_stage_iReg__log_reg_32_T_62 | iwb_stage_iReg__log_reg_32_T_31; // @[Regfiles.scala 223:82]
  wire [1:0] iwb_stage_iReg__log_reg_32_T_64 = iwb_stage_iReg__log_reg_32_T_63 ? iwb_stage_iReg_log_reg_32 : 2'h0; // @[Regfiles.scala 223:63]
  wire [1:0] iwb_stage_iReg__GEN_1620 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_0_T_64 : iwb_stage_iReg__GEN_1520
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1621 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_1_T_64 : iwb_stage_iReg__GEN_1521
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1622 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_2_T_64 : iwb_stage_iReg__GEN_1522
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1623 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_3_T_64 : iwb_stage_iReg__GEN_1523
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1624 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_4_T_64 : iwb_stage_iReg__GEN_1524
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1625 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_5_T_64 : iwb_stage_iReg__GEN_1525
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1626 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_6_T_64 : iwb_stage_iReg__GEN_1526
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1627 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_7_T_64 : iwb_stage_iReg__GEN_1527
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1628 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_8_T_64 : iwb_stage_iReg__GEN_1528
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1629 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_9_T_64 : iwb_stage_iReg__GEN_1529
    ; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1630 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_10_T_64 :
    iwb_stage_iReg__GEN_1530; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1631 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_11_T_64 :
    iwb_stage_iReg__GEN_1531; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1632 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_12_T_64 :
    iwb_stage_iReg__GEN_1532; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1633 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_13_T_64 :
    iwb_stage_iReg__GEN_1533; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1634 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_14_T_64 :
    iwb_stage_iReg__GEN_1534; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1635 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_15_T_64 :
    iwb_stage_iReg__GEN_1535; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1636 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_16_T_64 :
    iwb_stage_iReg__GEN_1536; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1637 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_17_T_64 :
    iwb_stage_iReg__GEN_1537; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1638 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_18_T_64 :
    iwb_stage_iReg__GEN_1538; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1639 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_19_T_64 :
    iwb_stage_iReg__GEN_1539; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1640 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_20_T_64 :
    iwb_stage_iReg__GEN_1540; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1641 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_21_T_64 :
    iwb_stage_iReg__GEN_1541; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1642 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_22_T_64 :
    iwb_stage_iReg__GEN_1542; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1643 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_23_T_64 :
    iwb_stage_iReg__GEN_1543; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1644 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_24_T_64 :
    iwb_stage_iReg__GEN_1544; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1645 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_25_T_64 :
    iwb_stage_iReg__GEN_1545; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1646 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_26_T_64 :
    iwb_stage_iReg__GEN_1546; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1647 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_27_T_64 :
    iwb_stage_iReg__GEN_1547; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1648 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_28_T_64 :
    iwb_stage_iReg__GEN_1548; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1649 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_29_T_64 :
    iwb_stage_iReg__GEN_1549; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1650 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_30_T_64 :
    iwb_stage_iReg__GEN_1550; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1651 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_31_T_64 :
    iwb_stage_iReg__GEN_1551; // @[Regfiles.scala 221:64 223:57]
  wire [1:0] iwb_stage_iReg__GEN_1652 = iwb_stage_iReg__T_39 ? iwb_stage_iReg__log_reg_32_T_64 :
    iwb_stage_iReg__GEN_1552; // @[Regfiles.scala 221:64 223:57]
  wire  iwb_stage_iReg__T_114 = iwb_stage_iReg_io_commit_0_is_MisPredict | iwb_stage_iReg_io_commit_0_is_comfirm; // @[Regfiles.scala 225:38]
  wire  iwb_stage_iReg__T_117 = ~iwb_stage_iReg_io_commit_0_is_writeback; // @[Regfiles.scala 227:13]
  wire [5:0] iwb_stage_iReg__GEN_1654 = 5'h1 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_1 :
    iwb_stage_iReg_archit_ptr_0; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1655 = 5'h2 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_2 :
    iwb_stage_iReg__GEN_1654; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1656 = 5'h3 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_3 :
    iwb_stage_iReg__GEN_1655; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1657 = 5'h4 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_4 :
    iwb_stage_iReg__GEN_1656; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1658 = 5'h5 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_5 :
    iwb_stage_iReg__GEN_1657; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1659 = 5'h6 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_6 :
    iwb_stage_iReg__GEN_1658; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1660 = 5'h7 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_7 :
    iwb_stage_iReg__GEN_1659; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1661 = 5'h8 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_8 :
    iwb_stage_iReg__GEN_1660; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1662 = 5'h9 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_9 :
    iwb_stage_iReg__GEN_1661; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1663 = 5'ha == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_10 :
    iwb_stage_iReg__GEN_1662; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1664 = 5'hb == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_11 :
    iwb_stage_iReg__GEN_1663; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1665 = 5'hc == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_12 :
    iwb_stage_iReg__GEN_1664; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1666 = 5'hd == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_13 :
    iwb_stage_iReg__GEN_1665; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1667 = 5'he == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_14 :
    iwb_stage_iReg__GEN_1666; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1668 = 5'hf == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_15 :
    iwb_stage_iReg__GEN_1667; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1669 = 5'h10 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_16 :
    iwb_stage_iReg__GEN_1668; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1670 = 5'h11 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_17 :
    iwb_stage_iReg__GEN_1669; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1671 = 5'h12 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_18 :
    iwb_stage_iReg__GEN_1670; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1672 = 5'h13 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_19 :
    iwb_stage_iReg__GEN_1671; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1673 = 5'h14 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_20 :
    iwb_stage_iReg__GEN_1672; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1674 = 5'h15 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_21 :
    iwb_stage_iReg__GEN_1673; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1675 = 5'h16 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_22 :
    iwb_stage_iReg__GEN_1674; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1676 = 5'h17 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_23 :
    iwb_stage_iReg__GEN_1675; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1677 = 5'h18 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_24 :
    iwb_stage_iReg__GEN_1676; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1678 = 5'h19 == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_25 :
    iwb_stage_iReg__GEN_1677; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1679 = 5'h1a == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_26 :
    iwb_stage_iReg__GEN_1678; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1680 = 5'h1b == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_27 :
    iwb_stage_iReg__GEN_1679; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1681 = 5'h1c == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_28 :
    iwb_stage_iReg__GEN_1680; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1682 = 5'h1d == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_29 :
    iwb_stage_iReg__GEN_1681; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1683 = 5'h1e == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_30 :
    iwb_stage_iReg__GEN_1682; // @[Regfiles.scala 229:{18,18}]
  wire [5:0] iwb_stage_iReg__GEN_1684 = 5'h1f == iwb_stage_iReg_io_commit_0_raw ? iwb_stage_iReg_archit_ptr_31 :
    iwb_stage_iReg__GEN_1683; // @[Regfiles.scala 229:{18,18}]
  wire  iwb_stage_iReg__T_118 = 6'h0 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_119 = 6'h1 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_120 = 6'h2 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_121 = 6'h3 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_122 = 6'h4 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_123 = 6'h5 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_124 = 6'h6 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_125 = 6'h7 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_126 = 6'h8 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_127 = 6'h9 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_128 = 6'ha == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_129 = 6'hb == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_130 = 6'hc == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_131 = 6'hd == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_132 = 6'he == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_133 = 6'hf == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_134 = 6'h10 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_135 = 6'h11 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_136 = 6'h12 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_137 = 6'h13 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_138 = 6'h14 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_139 = 6'h15 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_140 = 6'h16 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_141 = 6'h17 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_142 = 6'h18 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_143 = 6'h19 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_144 = 6'h1a == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_145 = 6'h1b == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_146 = 6'h1c == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_147 = 6'h1d == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_148 = 6'h1e == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_149 = 6'h1f == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_150 = 6'h20 == iwb_stage_iReg__GEN_1684; // @[Regfiles.scala 229:18]
  wire  iwb_stage_iReg__T_151 = iwb_stage_iReg__GEN_1618 == 2'h3; // @[Regfiles.scala 231:31]
  wire  iwb_stage_iReg__T_154 = ~iwb_stage_iReg__T_151; // @[Regfiles.scala 231:13]
  wire [1:0] iwb_stage_iReg__GEN_1882 = 6'h1 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1883 = 6'h2 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_1882; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1884 = 6'h3 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_1883; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1885 = 6'h4 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_1884; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1886 = 6'h5 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_1885; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1887 = 6'h6 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_1886; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1888 = 6'h7 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_1887; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1889 = 6'h8 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_1888; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1890 = 6'h9 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_1889; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1891 = 6'ha == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_1890; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1892 = 6'hb == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_1891; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1893 = 6'hc == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_1892; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1894 = 6'hd == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_1893; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1895 = 6'he == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_1894; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1896 = 6'hf == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_1895; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1897 = 6'h10 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_1896; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1898 = 6'h11 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_1897; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1899 = 6'h12 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_1898; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1900 = 6'h13 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_1899; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1901 = 6'h14 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_1900; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1902 = 6'h15 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_1901; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1903 = 6'h16 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_1902; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1904 = 6'h17 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_1903; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1905 = 6'h18 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_1904; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1906 = 6'h19 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_1905; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1907 = 6'h1a == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_1906; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1908 = 6'h1b == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_1907; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1909 = 6'h1c == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_1908; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1910 = 6'h1d == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_1909; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1911 = 6'h1e == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_1910; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1912 = 6'h1f == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_1911; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1913 = 6'h20 == iwb_stage_iReg_archit_ptr_0 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_1912; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1914 = 6'h21 == iwb_stage_iReg_archit_ptr_0 ? 2'h3 : iwb_stage_iReg__GEN_1913; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_156 = iwb_stage_iReg__GEN_1914 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_159 = ~iwb_stage_iReg__T_156; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_1916 = 6'h1 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1917 = 6'h2 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_1916; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1918 = 6'h3 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_1917; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1919 = 6'h4 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_1918; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1920 = 6'h5 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_1919; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1921 = 6'h6 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_1920; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1922 = 6'h7 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_1921; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1923 = 6'h8 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_1922; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1924 = 6'h9 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_1923; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1925 = 6'ha == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_1924; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1926 = 6'hb == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_1925; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1927 = 6'hc == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_1926; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1928 = 6'hd == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_1927; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1929 = 6'he == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_1928; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1930 = 6'hf == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_1929; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1931 = 6'h10 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_1930; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1932 = 6'h11 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_1931; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1933 = 6'h12 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_1932; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1934 = 6'h13 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_1933; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1935 = 6'h14 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_1934; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1936 = 6'h15 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_1935; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1937 = 6'h16 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_1936; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1938 = 6'h17 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_1937; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1939 = 6'h18 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_1938; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1940 = 6'h19 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_1939; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1941 = 6'h1a == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_1940; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1942 = 6'h1b == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_1941; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1943 = 6'h1c == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_1942; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1944 = 6'h1d == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_1943; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1945 = 6'h1e == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_1944; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1946 = 6'h1f == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_1945; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1947 = 6'h20 == iwb_stage_iReg_archit_ptr_1 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_1946; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1948 = 6'h21 == iwb_stage_iReg_archit_ptr_1 ? 2'h3 : iwb_stage_iReg__GEN_1947; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_160 = iwb_stage_iReg__GEN_1948 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_163 = ~iwb_stage_iReg__T_160; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_1950 = 6'h1 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1951 = 6'h2 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_1950; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1952 = 6'h3 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_1951; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1953 = 6'h4 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_1952; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1954 = 6'h5 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_1953; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1955 = 6'h6 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_1954; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1956 = 6'h7 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_1955; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1957 = 6'h8 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_1956; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1958 = 6'h9 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_1957; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1959 = 6'ha == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_1958; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1960 = 6'hb == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_1959; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1961 = 6'hc == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_1960; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1962 = 6'hd == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_1961; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1963 = 6'he == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_1962; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1964 = 6'hf == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_1963; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1965 = 6'h10 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_1964; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1966 = 6'h11 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_1965; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1967 = 6'h12 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_1966; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1968 = 6'h13 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_1967; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1969 = 6'h14 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_1968; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1970 = 6'h15 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_1969; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1971 = 6'h16 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_1970; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1972 = 6'h17 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_1971; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1973 = 6'h18 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_1972; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1974 = 6'h19 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_1973; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1975 = 6'h1a == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_1974; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1976 = 6'h1b == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_1975; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1977 = 6'h1c == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_1976; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1978 = 6'h1d == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_1977; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1979 = 6'h1e == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_1978; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1980 = 6'h1f == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_1979; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1981 = 6'h20 == iwb_stage_iReg_archit_ptr_2 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_1980; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1982 = 6'h21 == iwb_stage_iReg_archit_ptr_2 ? 2'h3 : iwb_stage_iReg__GEN_1981; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_164 = iwb_stage_iReg__GEN_1982 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_167 = ~iwb_stage_iReg__T_164; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_1984 = 6'h1 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1985 = 6'h2 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_1984; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1986 = 6'h3 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_1985; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1987 = 6'h4 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_1986; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1988 = 6'h5 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_1987; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1989 = 6'h6 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_1988; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1990 = 6'h7 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_1989; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1991 = 6'h8 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_1990; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1992 = 6'h9 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_1991; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1993 = 6'ha == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_1992; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1994 = 6'hb == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_1993; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1995 = 6'hc == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_1994; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1996 = 6'hd == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_1995; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1997 = 6'he == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_1996; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1998 = 6'hf == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_1997; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_1999 = 6'h10 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_1998; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2000 = 6'h11 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_1999; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2001 = 6'h12 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2000; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2002 = 6'h13 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2001; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2003 = 6'h14 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2002; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2004 = 6'h15 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2003; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2005 = 6'h16 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2004; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2006 = 6'h17 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2005; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2007 = 6'h18 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2006; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2008 = 6'h19 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2007; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2009 = 6'h1a == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2008; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2010 = 6'h1b == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2009; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2011 = 6'h1c == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2010; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2012 = 6'h1d == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2011; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2013 = 6'h1e == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2012; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2014 = 6'h1f == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2013; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2015 = 6'h20 == iwb_stage_iReg_archit_ptr_3 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2014; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2016 = 6'h21 == iwb_stage_iReg_archit_ptr_3 ? 2'h3 : iwb_stage_iReg__GEN_2015; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_168 = iwb_stage_iReg__GEN_2016 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_171 = ~iwb_stage_iReg__T_168; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2018 = 6'h1 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2019 = 6'h2 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2018; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2020 = 6'h3 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2019; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2021 = 6'h4 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2020; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2022 = 6'h5 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2021; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2023 = 6'h6 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2022; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2024 = 6'h7 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2023; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2025 = 6'h8 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2024; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2026 = 6'h9 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2025; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2027 = 6'ha == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2026; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2028 = 6'hb == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2027; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2029 = 6'hc == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2028; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2030 = 6'hd == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2029; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2031 = 6'he == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2030; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2032 = 6'hf == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2031; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2033 = 6'h10 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2032; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2034 = 6'h11 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2033; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2035 = 6'h12 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2034; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2036 = 6'h13 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2035; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2037 = 6'h14 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2036; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2038 = 6'h15 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2037; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2039 = 6'h16 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2038; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2040 = 6'h17 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2039; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2041 = 6'h18 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2040; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2042 = 6'h19 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2041; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2043 = 6'h1a == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2042; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2044 = 6'h1b == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2043; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2045 = 6'h1c == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2044; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2046 = 6'h1d == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2045; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2047 = 6'h1e == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2046; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2048 = 6'h1f == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2047; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2049 = 6'h20 == iwb_stage_iReg_archit_ptr_4 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2048; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2050 = 6'h21 == iwb_stage_iReg_archit_ptr_4 ? 2'h3 : iwb_stage_iReg__GEN_2049; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_172 = iwb_stage_iReg__GEN_2050 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_175 = ~iwb_stage_iReg__T_172; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2052 = 6'h1 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2053 = 6'h2 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2052; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2054 = 6'h3 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2053; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2055 = 6'h4 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2054; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2056 = 6'h5 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2055; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2057 = 6'h6 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2056; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2058 = 6'h7 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2057; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2059 = 6'h8 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2058; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2060 = 6'h9 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2059; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2061 = 6'ha == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2060; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2062 = 6'hb == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2061; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2063 = 6'hc == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2062; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2064 = 6'hd == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2063; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2065 = 6'he == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2064; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2066 = 6'hf == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2065; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2067 = 6'h10 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2066; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2068 = 6'h11 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2067; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2069 = 6'h12 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2068; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2070 = 6'h13 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2069; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2071 = 6'h14 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2070; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2072 = 6'h15 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2071; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2073 = 6'h16 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2072; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2074 = 6'h17 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2073; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2075 = 6'h18 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2074; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2076 = 6'h19 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2075; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2077 = 6'h1a == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2076; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2078 = 6'h1b == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2077; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2079 = 6'h1c == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2078; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2080 = 6'h1d == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2079; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2081 = 6'h1e == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2080; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2082 = 6'h1f == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2081; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2083 = 6'h20 == iwb_stage_iReg_archit_ptr_5 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2082; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2084 = 6'h21 == iwb_stage_iReg_archit_ptr_5 ? 2'h3 : iwb_stage_iReg__GEN_2083; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_176 = iwb_stage_iReg__GEN_2084 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_179 = ~iwb_stage_iReg__T_176; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2086 = 6'h1 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2087 = 6'h2 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2086; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2088 = 6'h3 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2087; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2089 = 6'h4 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2088; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2090 = 6'h5 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2089; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2091 = 6'h6 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2090; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2092 = 6'h7 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2091; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2093 = 6'h8 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2092; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2094 = 6'h9 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2093; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2095 = 6'ha == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2094; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2096 = 6'hb == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2095; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2097 = 6'hc == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2096; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2098 = 6'hd == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2097; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2099 = 6'he == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2098; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2100 = 6'hf == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2099; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2101 = 6'h10 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2100; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2102 = 6'h11 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2101; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2103 = 6'h12 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2102; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2104 = 6'h13 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2103; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2105 = 6'h14 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2104; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2106 = 6'h15 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2105; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2107 = 6'h16 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2106; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2108 = 6'h17 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2107; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2109 = 6'h18 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2108; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2110 = 6'h19 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2109; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2111 = 6'h1a == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2110; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2112 = 6'h1b == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2111; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2113 = 6'h1c == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2112; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2114 = 6'h1d == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2113; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2115 = 6'h1e == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2114; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2116 = 6'h1f == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2115; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2117 = 6'h20 == iwb_stage_iReg_archit_ptr_6 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2116; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2118 = 6'h21 == iwb_stage_iReg_archit_ptr_6 ? 2'h3 : iwb_stage_iReg__GEN_2117; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_180 = iwb_stage_iReg__GEN_2118 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_183 = ~iwb_stage_iReg__T_180; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2120 = 6'h1 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2121 = 6'h2 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2120; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2122 = 6'h3 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2121; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2123 = 6'h4 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2122; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2124 = 6'h5 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2123; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2125 = 6'h6 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2124; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2126 = 6'h7 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2125; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2127 = 6'h8 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2126; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2128 = 6'h9 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2127; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2129 = 6'ha == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2128; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2130 = 6'hb == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2129; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2131 = 6'hc == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2130; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2132 = 6'hd == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2131; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2133 = 6'he == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2132; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2134 = 6'hf == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2133; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2135 = 6'h10 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2134; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2136 = 6'h11 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2135; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2137 = 6'h12 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2136; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2138 = 6'h13 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2137; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2139 = 6'h14 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2138; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2140 = 6'h15 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2139; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2141 = 6'h16 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2140; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2142 = 6'h17 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2141; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2143 = 6'h18 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2142; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2144 = 6'h19 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2143; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2145 = 6'h1a == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2144; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2146 = 6'h1b == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2145; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2147 = 6'h1c == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2146; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2148 = 6'h1d == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2147; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2149 = 6'h1e == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2148; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2150 = 6'h1f == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2149; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2151 = 6'h20 == iwb_stage_iReg_archit_ptr_7 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2150; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2152 = 6'h21 == iwb_stage_iReg_archit_ptr_7 ? 2'h3 : iwb_stage_iReg__GEN_2151; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_184 = iwb_stage_iReg__GEN_2152 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_187 = ~iwb_stage_iReg__T_184; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2154 = 6'h1 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2155 = 6'h2 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2154; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2156 = 6'h3 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2155; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2157 = 6'h4 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2156; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2158 = 6'h5 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2157; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2159 = 6'h6 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2158; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2160 = 6'h7 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2159; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2161 = 6'h8 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2160; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2162 = 6'h9 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2161; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2163 = 6'ha == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2162; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2164 = 6'hb == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2163; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2165 = 6'hc == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2164; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2166 = 6'hd == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2165; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2167 = 6'he == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2166; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2168 = 6'hf == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2167; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2169 = 6'h10 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2168; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2170 = 6'h11 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2169; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2171 = 6'h12 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2170; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2172 = 6'h13 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2171; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2173 = 6'h14 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2172; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2174 = 6'h15 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2173; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2175 = 6'h16 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2174; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2176 = 6'h17 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2175; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2177 = 6'h18 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2176; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2178 = 6'h19 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2177; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2179 = 6'h1a == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2178; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2180 = 6'h1b == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2179; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2181 = 6'h1c == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2180; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2182 = 6'h1d == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2181; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2183 = 6'h1e == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2182; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2184 = 6'h1f == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2183; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2185 = 6'h20 == iwb_stage_iReg_archit_ptr_8 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2184; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2186 = 6'h21 == iwb_stage_iReg_archit_ptr_8 ? 2'h3 : iwb_stage_iReg__GEN_2185; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_188 = iwb_stage_iReg__GEN_2186 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_191 = ~iwb_stage_iReg__T_188; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2188 = 6'h1 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2189 = 6'h2 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2188; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2190 = 6'h3 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2189; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2191 = 6'h4 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2190; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2192 = 6'h5 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2191; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2193 = 6'h6 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2192; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2194 = 6'h7 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2193; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2195 = 6'h8 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2194; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2196 = 6'h9 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2195; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2197 = 6'ha == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2196; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2198 = 6'hb == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2197; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2199 = 6'hc == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2198; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2200 = 6'hd == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2199; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2201 = 6'he == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2200; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2202 = 6'hf == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2201; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2203 = 6'h10 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2202; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2204 = 6'h11 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2203; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2205 = 6'h12 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2204; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2206 = 6'h13 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2205; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2207 = 6'h14 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2206; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2208 = 6'h15 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2207; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2209 = 6'h16 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2208; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2210 = 6'h17 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2209; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2211 = 6'h18 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2210; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2212 = 6'h19 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2211; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2213 = 6'h1a == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2212; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2214 = 6'h1b == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2213; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2215 = 6'h1c == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2214; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2216 = 6'h1d == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2215; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2217 = 6'h1e == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2216; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2218 = 6'h1f == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2217; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2219 = 6'h20 == iwb_stage_iReg_archit_ptr_9 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2218; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2220 = 6'h21 == iwb_stage_iReg_archit_ptr_9 ? 2'h3 : iwb_stage_iReg__GEN_2219; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_192 = iwb_stage_iReg__GEN_2220 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_195 = ~iwb_stage_iReg__T_192; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2222 = 6'h1 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2223 = 6'h2 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2222; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2224 = 6'h3 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2223; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2225 = 6'h4 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2224; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2226 = 6'h5 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2225; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2227 = 6'h6 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2226; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2228 = 6'h7 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2227; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2229 = 6'h8 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2228; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2230 = 6'h9 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2229; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2231 = 6'ha == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2230; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2232 = 6'hb == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2231; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2233 = 6'hc == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2232; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2234 = 6'hd == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2233; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2235 = 6'he == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2234; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2236 = 6'hf == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2235; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2237 = 6'h10 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2236; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2238 = 6'h11 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2237; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2239 = 6'h12 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2238; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2240 = 6'h13 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2239; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2241 = 6'h14 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2240; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2242 = 6'h15 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2241; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2243 = 6'h16 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2242; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2244 = 6'h17 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2243; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2245 = 6'h18 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2244; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2246 = 6'h19 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2245; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2247 = 6'h1a == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2246; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2248 = 6'h1b == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2247; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2249 = 6'h1c == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2248; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2250 = 6'h1d == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2249; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2251 = 6'h1e == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2250; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2252 = 6'h1f == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2251; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2253 = 6'h20 == iwb_stage_iReg_archit_ptr_10 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2252; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2254 = 6'h21 == iwb_stage_iReg_archit_ptr_10 ? 2'h3 : iwb_stage_iReg__GEN_2253; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_196 = iwb_stage_iReg__GEN_2254 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_199 = ~iwb_stage_iReg__T_196; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2256 = 6'h1 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2257 = 6'h2 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2256; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2258 = 6'h3 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2257; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2259 = 6'h4 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2258; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2260 = 6'h5 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2259; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2261 = 6'h6 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2260; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2262 = 6'h7 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2261; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2263 = 6'h8 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2262; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2264 = 6'h9 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2263; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2265 = 6'ha == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2264; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2266 = 6'hb == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2265; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2267 = 6'hc == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2266; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2268 = 6'hd == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2267; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2269 = 6'he == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2268; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2270 = 6'hf == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2269; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2271 = 6'h10 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2270; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2272 = 6'h11 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2271; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2273 = 6'h12 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2272; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2274 = 6'h13 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2273; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2275 = 6'h14 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2274; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2276 = 6'h15 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2275; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2277 = 6'h16 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2276; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2278 = 6'h17 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2277; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2279 = 6'h18 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2278; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2280 = 6'h19 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2279; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2281 = 6'h1a == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2280; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2282 = 6'h1b == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2281; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2283 = 6'h1c == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2282; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2284 = 6'h1d == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2283; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2285 = 6'h1e == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2284; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2286 = 6'h1f == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2285; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2287 = 6'h20 == iwb_stage_iReg_archit_ptr_11 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2286; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2288 = 6'h21 == iwb_stage_iReg_archit_ptr_11 ? 2'h3 : iwb_stage_iReg__GEN_2287; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_200 = iwb_stage_iReg__GEN_2288 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_203 = ~iwb_stage_iReg__T_200; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2290 = 6'h1 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2291 = 6'h2 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2290; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2292 = 6'h3 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2291; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2293 = 6'h4 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2292; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2294 = 6'h5 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2293; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2295 = 6'h6 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2294; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2296 = 6'h7 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2295; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2297 = 6'h8 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2296; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2298 = 6'h9 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2297; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2299 = 6'ha == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2298; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2300 = 6'hb == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2299; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2301 = 6'hc == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2300; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2302 = 6'hd == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2301; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2303 = 6'he == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2302; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2304 = 6'hf == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2303; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2305 = 6'h10 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2304; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2306 = 6'h11 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2305; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2307 = 6'h12 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2306; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2308 = 6'h13 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2307; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2309 = 6'h14 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2308; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2310 = 6'h15 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2309; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2311 = 6'h16 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2310; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2312 = 6'h17 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2311; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2313 = 6'h18 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2312; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2314 = 6'h19 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2313; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2315 = 6'h1a == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2314; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2316 = 6'h1b == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2315; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2317 = 6'h1c == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2316; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2318 = 6'h1d == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2317; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2319 = 6'h1e == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2318; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2320 = 6'h1f == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2319; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2321 = 6'h20 == iwb_stage_iReg_archit_ptr_12 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2320; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2322 = 6'h21 == iwb_stage_iReg_archit_ptr_12 ? 2'h3 : iwb_stage_iReg__GEN_2321; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_204 = iwb_stage_iReg__GEN_2322 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_207 = ~iwb_stage_iReg__T_204; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2324 = 6'h1 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2325 = 6'h2 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2324; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2326 = 6'h3 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2325; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2327 = 6'h4 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2326; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2328 = 6'h5 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2327; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2329 = 6'h6 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2328; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2330 = 6'h7 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2329; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2331 = 6'h8 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2330; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2332 = 6'h9 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2331; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2333 = 6'ha == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2332; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2334 = 6'hb == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2333; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2335 = 6'hc == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2334; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2336 = 6'hd == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2335; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2337 = 6'he == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2336; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2338 = 6'hf == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2337; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2339 = 6'h10 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2338; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2340 = 6'h11 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2339; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2341 = 6'h12 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2340; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2342 = 6'h13 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2341; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2343 = 6'h14 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2342; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2344 = 6'h15 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2343; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2345 = 6'h16 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2344; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2346 = 6'h17 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2345; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2347 = 6'h18 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2346; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2348 = 6'h19 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2347; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2349 = 6'h1a == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2348; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2350 = 6'h1b == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2349; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2351 = 6'h1c == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2350; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2352 = 6'h1d == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2351; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2353 = 6'h1e == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2352; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2354 = 6'h1f == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2353; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2355 = 6'h20 == iwb_stage_iReg_archit_ptr_13 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2354; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2356 = 6'h21 == iwb_stage_iReg_archit_ptr_13 ? 2'h3 : iwb_stage_iReg__GEN_2355; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_208 = iwb_stage_iReg__GEN_2356 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_211 = ~iwb_stage_iReg__T_208; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2358 = 6'h1 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2359 = 6'h2 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2358; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2360 = 6'h3 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2359; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2361 = 6'h4 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2360; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2362 = 6'h5 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2361; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2363 = 6'h6 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2362; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2364 = 6'h7 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2363; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2365 = 6'h8 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2364; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2366 = 6'h9 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2365; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2367 = 6'ha == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2366; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2368 = 6'hb == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2367; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2369 = 6'hc == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2368; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2370 = 6'hd == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2369; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2371 = 6'he == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2370; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2372 = 6'hf == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2371; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2373 = 6'h10 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2372; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2374 = 6'h11 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2373; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2375 = 6'h12 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2374; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2376 = 6'h13 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2375; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2377 = 6'h14 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2376; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2378 = 6'h15 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2377; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2379 = 6'h16 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2378; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2380 = 6'h17 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2379; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2381 = 6'h18 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2380; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2382 = 6'h19 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2381; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2383 = 6'h1a == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2382; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2384 = 6'h1b == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2383; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2385 = 6'h1c == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2384; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2386 = 6'h1d == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2385; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2387 = 6'h1e == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2386; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2388 = 6'h1f == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2387; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2389 = 6'h20 == iwb_stage_iReg_archit_ptr_14 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2388; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2390 = 6'h21 == iwb_stage_iReg_archit_ptr_14 ? 2'h3 : iwb_stage_iReg__GEN_2389; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_212 = iwb_stage_iReg__GEN_2390 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_215 = ~iwb_stage_iReg__T_212; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2392 = 6'h1 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2393 = 6'h2 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2392; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2394 = 6'h3 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2393; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2395 = 6'h4 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2394; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2396 = 6'h5 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2395; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2397 = 6'h6 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2396; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2398 = 6'h7 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2397; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2399 = 6'h8 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2398; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2400 = 6'h9 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2399; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2401 = 6'ha == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2400; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2402 = 6'hb == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2401; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2403 = 6'hc == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2402; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2404 = 6'hd == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2403; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2405 = 6'he == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2404; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2406 = 6'hf == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2405; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2407 = 6'h10 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2406; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2408 = 6'h11 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2407; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2409 = 6'h12 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2408; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2410 = 6'h13 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2409; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2411 = 6'h14 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2410; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2412 = 6'h15 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2411; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2413 = 6'h16 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2412; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2414 = 6'h17 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2413; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2415 = 6'h18 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2414; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2416 = 6'h19 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2415; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2417 = 6'h1a == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2416; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2418 = 6'h1b == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2417; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2419 = 6'h1c == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2418; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2420 = 6'h1d == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2419; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2421 = 6'h1e == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2420; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2422 = 6'h1f == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2421; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2423 = 6'h20 == iwb_stage_iReg_archit_ptr_15 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2422; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2424 = 6'h21 == iwb_stage_iReg_archit_ptr_15 ? 2'h3 : iwb_stage_iReg__GEN_2423; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_216 = iwb_stage_iReg__GEN_2424 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_219 = ~iwb_stage_iReg__T_216; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2426 = 6'h1 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2427 = 6'h2 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2426; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2428 = 6'h3 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2427; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2429 = 6'h4 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2428; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2430 = 6'h5 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2429; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2431 = 6'h6 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2430; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2432 = 6'h7 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2431; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2433 = 6'h8 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2432; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2434 = 6'h9 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2433; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2435 = 6'ha == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2434; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2436 = 6'hb == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2435; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2437 = 6'hc == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2436; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2438 = 6'hd == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2437; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2439 = 6'he == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2438; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2440 = 6'hf == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2439; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2441 = 6'h10 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2440; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2442 = 6'h11 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2441; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2443 = 6'h12 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2442; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2444 = 6'h13 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2443; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2445 = 6'h14 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2444; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2446 = 6'h15 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2445; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2447 = 6'h16 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2446; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2448 = 6'h17 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2447; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2449 = 6'h18 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2448; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2450 = 6'h19 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2449; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2451 = 6'h1a == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2450; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2452 = 6'h1b == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2451; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2453 = 6'h1c == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2452; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2454 = 6'h1d == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2453; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2455 = 6'h1e == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2454; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2456 = 6'h1f == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2455; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2457 = 6'h20 == iwb_stage_iReg_archit_ptr_16 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2456; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2458 = 6'h21 == iwb_stage_iReg_archit_ptr_16 ? 2'h3 : iwb_stage_iReg__GEN_2457; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_220 = iwb_stage_iReg__GEN_2458 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_223 = ~iwb_stage_iReg__T_220; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2460 = 6'h1 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2461 = 6'h2 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2460; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2462 = 6'h3 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2461; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2463 = 6'h4 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2462; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2464 = 6'h5 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2463; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2465 = 6'h6 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2464; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2466 = 6'h7 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2465; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2467 = 6'h8 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2466; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2468 = 6'h9 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2467; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2469 = 6'ha == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2468; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2470 = 6'hb == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2469; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2471 = 6'hc == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2470; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2472 = 6'hd == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2471; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2473 = 6'he == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2472; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2474 = 6'hf == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2473; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2475 = 6'h10 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2474; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2476 = 6'h11 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2475; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2477 = 6'h12 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2476; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2478 = 6'h13 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2477; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2479 = 6'h14 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2478; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2480 = 6'h15 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2479; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2481 = 6'h16 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2480; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2482 = 6'h17 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2481; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2483 = 6'h18 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2482; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2484 = 6'h19 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2483; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2485 = 6'h1a == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2484; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2486 = 6'h1b == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2485; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2487 = 6'h1c == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2486; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2488 = 6'h1d == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2487; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2489 = 6'h1e == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2488; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2490 = 6'h1f == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2489; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2491 = 6'h20 == iwb_stage_iReg_archit_ptr_17 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2490; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2492 = 6'h21 == iwb_stage_iReg_archit_ptr_17 ? 2'h3 : iwb_stage_iReg__GEN_2491; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_224 = iwb_stage_iReg__GEN_2492 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_227 = ~iwb_stage_iReg__T_224; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2494 = 6'h1 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2495 = 6'h2 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2494; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2496 = 6'h3 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2495; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2497 = 6'h4 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2496; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2498 = 6'h5 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2497; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2499 = 6'h6 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2498; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2500 = 6'h7 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2499; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2501 = 6'h8 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2500; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2502 = 6'h9 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2501; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2503 = 6'ha == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2502; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2504 = 6'hb == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2503; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2505 = 6'hc == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2504; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2506 = 6'hd == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2505; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2507 = 6'he == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2506; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2508 = 6'hf == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2507; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2509 = 6'h10 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2508; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2510 = 6'h11 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2509; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2511 = 6'h12 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2510; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2512 = 6'h13 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2511; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2513 = 6'h14 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2512; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2514 = 6'h15 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2513; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2515 = 6'h16 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2514; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2516 = 6'h17 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2515; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2517 = 6'h18 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2516; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2518 = 6'h19 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2517; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2519 = 6'h1a == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2518; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2520 = 6'h1b == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2519; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2521 = 6'h1c == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2520; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2522 = 6'h1d == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2521; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2523 = 6'h1e == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2522; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2524 = 6'h1f == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2523; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2525 = 6'h20 == iwb_stage_iReg_archit_ptr_18 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2524; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2526 = 6'h21 == iwb_stage_iReg_archit_ptr_18 ? 2'h3 : iwb_stage_iReg__GEN_2525; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_228 = iwb_stage_iReg__GEN_2526 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_231 = ~iwb_stage_iReg__T_228; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2528 = 6'h1 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2529 = 6'h2 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2528; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2530 = 6'h3 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2529; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2531 = 6'h4 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2530; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2532 = 6'h5 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2531; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2533 = 6'h6 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2532; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2534 = 6'h7 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2533; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2535 = 6'h8 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2534; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2536 = 6'h9 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2535; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2537 = 6'ha == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2536; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2538 = 6'hb == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2537; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2539 = 6'hc == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2538; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2540 = 6'hd == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2539; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2541 = 6'he == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2540; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2542 = 6'hf == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2541; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2543 = 6'h10 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2542; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2544 = 6'h11 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2543; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2545 = 6'h12 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2544; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2546 = 6'h13 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2545; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2547 = 6'h14 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2546; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2548 = 6'h15 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2547; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2549 = 6'h16 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2548; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2550 = 6'h17 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2549; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2551 = 6'h18 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2550; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2552 = 6'h19 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2551; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2553 = 6'h1a == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2552; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2554 = 6'h1b == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2553; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2555 = 6'h1c == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2554; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2556 = 6'h1d == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2555; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2557 = 6'h1e == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2556; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2558 = 6'h1f == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2557; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2559 = 6'h20 == iwb_stage_iReg_archit_ptr_19 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2558; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2560 = 6'h21 == iwb_stage_iReg_archit_ptr_19 ? 2'h3 : iwb_stage_iReg__GEN_2559; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_232 = iwb_stage_iReg__GEN_2560 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_235 = ~iwb_stage_iReg__T_232; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2562 = 6'h1 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2563 = 6'h2 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2562; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2564 = 6'h3 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2563; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2565 = 6'h4 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2564; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2566 = 6'h5 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2565; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2567 = 6'h6 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2566; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2568 = 6'h7 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2567; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2569 = 6'h8 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2568; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2570 = 6'h9 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2569; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2571 = 6'ha == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2570; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2572 = 6'hb == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2571; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2573 = 6'hc == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2572; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2574 = 6'hd == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2573; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2575 = 6'he == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2574; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2576 = 6'hf == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2575; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2577 = 6'h10 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2576; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2578 = 6'h11 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2577; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2579 = 6'h12 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2578; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2580 = 6'h13 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2579; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2581 = 6'h14 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2580; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2582 = 6'h15 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2581; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2583 = 6'h16 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2582; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2584 = 6'h17 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2583; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2585 = 6'h18 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2584; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2586 = 6'h19 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2585; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2587 = 6'h1a == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2586; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2588 = 6'h1b == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2587; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2589 = 6'h1c == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2588; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2590 = 6'h1d == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2589; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2591 = 6'h1e == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2590; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2592 = 6'h1f == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2591; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2593 = 6'h20 == iwb_stage_iReg_archit_ptr_20 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2592; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2594 = 6'h21 == iwb_stage_iReg_archit_ptr_20 ? 2'h3 : iwb_stage_iReg__GEN_2593; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_236 = iwb_stage_iReg__GEN_2594 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_239 = ~iwb_stage_iReg__T_236; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2596 = 6'h1 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2597 = 6'h2 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2596; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2598 = 6'h3 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2597; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2599 = 6'h4 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2598; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2600 = 6'h5 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2599; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2601 = 6'h6 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2600; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2602 = 6'h7 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2601; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2603 = 6'h8 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2602; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2604 = 6'h9 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2603; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2605 = 6'ha == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2604; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2606 = 6'hb == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2605; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2607 = 6'hc == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2606; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2608 = 6'hd == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2607; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2609 = 6'he == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2608; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2610 = 6'hf == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2609; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2611 = 6'h10 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2610; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2612 = 6'h11 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2611; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2613 = 6'h12 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2612; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2614 = 6'h13 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2613; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2615 = 6'h14 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2614; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2616 = 6'h15 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2615; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2617 = 6'h16 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2616; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2618 = 6'h17 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2617; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2619 = 6'h18 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2618; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2620 = 6'h19 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2619; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2621 = 6'h1a == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2620; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2622 = 6'h1b == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2621; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2623 = 6'h1c == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2622; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2624 = 6'h1d == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2623; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2625 = 6'h1e == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2624; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2626 = 6'h1f == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2625; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2627 = 6'h20 == iwb_stage_iReg_archit_ptr_21 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2626; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2628 = 6'h21 == iwb_stage_iReg_archit_ptr_21 ? 2'h3 : iwb_stage_iReg__GEN_2627; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_240 = iwb_stage_iReg__GEN_2628 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_243 = ~iwb_stage_iReg__T_240; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2630 = 6'h1 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2631 = 6'h2 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2630; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2632 = 6'h3 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2631; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2633 = 6'h4 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2632; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2634 = 6'h5 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2633; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2635 = 6'h6 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2634; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2636 = 6'h7 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2635; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2637 = 6'h8 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2636; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2638 = 6'h9 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2637; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2639 = 6'ha == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2638; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2640 = 6'hb == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2639; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2641 = 6'hc == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2640; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2642 = 6'hd == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2641; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2643 = 6'he == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2642; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2644 = 6'hf == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2643; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2645 = 6'h10 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2644; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2646 = 6'h11 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2645; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2647 = 6'h12 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2646; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2648 = 6'h13 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2647; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2649 = 6'h14 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2648; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2650 = 6'h15 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2649; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2651 = 6'h16 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2650; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2652 = 6'h17 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2651; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2653 = 6'h18 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2652; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2654 = 6'h19 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2653; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2655 = 6'h1a == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2654; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2656 = 6'h1b == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2655; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2657 = 6'h1c == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2656; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2658 = 6'h1d == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2657; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2659 = 6'h1e == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2658; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2660 = 6'h1f == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2659; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2661 = 6'h20 == iwb_stage_iReg_archit_ptr_22 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2660; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2662 = 6'h21 == iwb_stage_iReg_archit_ptr_22 ? 2'h3 : iwb_stage_iReg__GEN_2661; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_244 = iwb_stage_iReg__GEN_2662 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_247 = ~iwb_stage_iReg__T_244; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2664 = 6'h1 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2665 = 6'h2 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2664; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2666 = 6'h3 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2665; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2667 = 6'h4 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2666; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2668 = 6'h5 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2667; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2669 = 6'h6 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2668; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2670 = 6'h7 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2669; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2671 = 6'h8 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2670; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2672 = 6'h9 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2671; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2673 = 6'ha == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2672; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2674 = 6'hb == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2673; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2675 = 6'hc == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2674; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2676 = 6'hd == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2675; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2677 = 6'he == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2676; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2678 = 6'hf == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2677; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2679 = 6'h10 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2678; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2680 = 6'h11 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2679; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2681 = 6'h12 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2680; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2682 = 6'h13 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2681; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2683 = 6'h14 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2682; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2684 = 6'h15 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2683; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2685 = 6'h16 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2684; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2686 = 6'h17 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2685; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2687 = 6'h18 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2686; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2688 = 6'h19 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2687; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2689 = 6'h1a == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2688; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2690 = 6'h1b == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2689; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2691 = 6'h1c == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2690; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2692 = 6'h1d == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2691; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2693 = 6'h1e == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2692; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2694 = 6'h1f == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2693; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2695 = 6'h20 == iwb_stage_iReg_archit_ptr_23 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2694; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2696 = 6'h21 == iwb_stage_iReg_archit_ptr_23 ? 2'h3 : iwb_stage_iReg__GEN_2695; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_248 = iwb_stage_iReg__GEN_2696 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_251 = ~iwb_stage_iReg__T_248; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2698 = 6'h1 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2699 = 6'h2 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2698; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2700 = 6'h3 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2699; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2701 = 6'h4 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2700; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2702 = 6'h5 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2701; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2703 = 6'h6 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2702; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2704 = 6'h7 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2703; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2705 = 6'h8 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2704; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2706 = 6'h9 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2705; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2707 = 6'ha == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2706; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2708 = 6'hb == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2707; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2709 = 6'hc == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2708; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2710 = 6'hd == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2709; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2711 = 6'he == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2710; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2712 = 6'hf == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2711; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2713 = 6'h10 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2712; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2714 = 6'h11 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2713; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2715 = 6'h12 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2714; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2716 = 6'h13 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2715; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2717 = 6'h14 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2716; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2718 = 6'h15 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2717; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2719 = 6'h16 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2718; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2720 = 6'h17 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2719; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2721 = 6'h18 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2720; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2722 = 6'h19 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2721; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2723 = 6'h1a == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2722; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2724 = 6'h1b == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2723; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2725 = 6'h1c == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2724; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2726 = 6'h1d == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2725; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2727 = 6'h1e == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2726; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2728 = 6'h1f == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2727; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2729 = 6'h20 == iwb_stage_iReg_archit_ptr_24 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2728; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2730 = 6'h21 == iwb_stage_iReg_archit_ptr_24 ? 2'h3 : iwb_stage_iReg__GEN_2729; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_252 = iwb_stage_iReg__GEN_2730 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_255 = ~iwb_stage_iReg__T_252; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2732 = 6'h1 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2733 = 6'h2 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2732; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2734 = 6'h3 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2733; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2735 = 6'h4 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2734; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2736 = 6'h5 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2735; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2737 = 6'h6 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2736; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2738 = 6'h7 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2737; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2739 = 6'h8 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2738; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2740 = 6'h9 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2739; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2741 = 6'ha == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2740; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2742 = 6'hb == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2741; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2743 = 6'hc == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2742; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2744 = 6'hd == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2743; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2745 = 6'he == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2744; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2746 = 6'hf == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2745; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2747 = 6'h10 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2746; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2748 = 6'h11 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2747; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2749 = 6'h12 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2748; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2750 = 6'h13 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2749; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2751 = 6'h14 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2750; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2752 = 6'h15 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2751; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2753 = 6'h16 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2752; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2754 = 6'h17 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2753; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2755 = 6'h18 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2754; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2756 = 6'h19 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2755; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2757 = 6'h1a == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2756; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2758 = 6'h1b == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2757; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2759 = 6'h1c == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2758; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2760 = 6'h1d == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2759; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2761 = 6'h1e == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2760; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2762 = 6'h1f == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2761; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2763 = 6'h20 == iwb_stage_iReg_archit_ptr_25 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2762; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2764 = 6'h21 == iwb_stage_iReg_archit_ptr_25 ? 2'h3 : iwb_stage_iReg__GEN_2763; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_256 = iwb_stage_iReg__GEN_2764 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_259 = ~iwb_stage_iReg__T_256; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2766 = 6'h1 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2767 = 6'h2 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2766; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2768 = 6'h3 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2767; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2769 = 6'h4 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2768; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2770 = 6'h5 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2769; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2771 = 6'h6 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2770; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2772 = 6'h7 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2771; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2773 = 6'h8 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2772; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2774 = 6'h9 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2773; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2775 = 6'ha == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2774; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2776 = 6'hb == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2775; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2777 = 6'hc == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2776; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2778 = 6'hd == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2777; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2779 = 6'he == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2778; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2780 = 6'hf == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2779; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2781 = 6'h10 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2780; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2782 = 6'h11 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2781; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2783 = 6'h12 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2782; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2784 = 6'h13 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2783; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2785 = 6'h14 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2784; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2786 = 6'h15 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2785; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2787 = 6'h16 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2786; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2788 = 6'h17 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2787; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2789 = 6'h18 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2788; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2790 = 6'h19 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2789; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2791 = 6'h1a == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2790; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2792 = 6'h1b == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2791; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2793 = 6'h1c == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2792; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2794 = 6'h1d == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2793; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2795 = 6'h1e == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2794; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2796 = 6'h1f == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2795; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2797 = 6'h20 == iwb_stage_iReg_archit_ptr_26 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2796; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2798 = 6'h21 == iwb_stage_iReg_archit_ptr_26 ? 2'h3 : iwb_stage_iReg__GEN_2797; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_260 = iwb_stage_iReg__GEN_2798 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_263 = ~iwb_stage_iReg__T_260; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2800 = 6'h1 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2801 = 6'h2 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2800; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2802 = 6'h3 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2801; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2803 = 6'h4 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2802; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2804 = 6'h5 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2803; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2805 = 6'h6 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2804; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2806 = 6'h7 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2805; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2807 = 6'h8 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2806; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2808 = 6'h9 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2807; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2809 = 6'ha == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2808; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2810 = 6'hb == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2809; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2811 = 6'hc == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2810; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2812 = 6'hd == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2811; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2813 = 6'he == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2812; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2814 = 6'hf == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2813; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2815 = 6'h10 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2814; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2816 = 6'h11 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2815; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2817 = 6'h12 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2816; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2818 = 6'h13 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2817; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2819 = 6'h14 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2818; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2820 = 6'h15 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2819; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2821 = 6'h16 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2820; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2822 = 6'h17 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2821; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2823 = 6'h18 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2822; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2824 = 6'h19 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2823; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2825 = 6'h1a == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2824; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2826 = 6'h1b == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2825; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2827 = 6'h1c == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2826; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2828 = 6'h1d == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2827; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2829 = 6'h1e == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2828; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2830 = 6'h1f == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2829; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2831 = 6'h20 == iwb_stage_iReg_archit_ptr_27 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2830; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2832 = 6'h21 == iwb_stage_iReg_archit_ptr_27 ? 2'h3 : iwb_stage_iReg__GEN_2831; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_264 = iwb_stage_iReg__GEN_2832 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_267 = ~iwb_stage_iReg__T_264; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2834 = 6'h1 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2835 = 6'h2 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2834; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2836 = 6'h3 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2835; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2837 = 6'h4 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2836; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2838 = 6'h5 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2837; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2839 = 6'h6 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2838; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2840 = 6'h7 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2839; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2841 = 6'h8 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2840; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2842 = 6'h9 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2841; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2843 = 6'ha == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2842; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2844 = 6'hb == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2843; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2845 = 6'hc == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2844; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2846 = 6'hd == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2845; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2847 = 6'he == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2846; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2848 = 6'hf == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2847; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2849 = 6'h10 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2848; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2850 = 6'h11 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2849; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2851 = 6'h12 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2850; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2852 = 6'h13 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2851; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2853 = 6'h14 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2852; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2854 = 6'h15 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2853; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2855 = 6'h16 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2854; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2856 = 6'h17 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2855; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2857 = 6'h18 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2856; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2858 = 6'h19 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2857; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2859 = 6'h1a == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2858; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2860 = 6'h1b == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2859; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2861 = 6'h1c == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2860; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2862 = 6'h1d == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2861; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2863 = 6'h1e == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2862; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2864 = 6'h1f == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2863; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2865 = 6'h20 == iwb_stage_iReg_archit_ptr_28 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2864; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2866 = 6'h21 == iwb_stage_iReg_archit_ptr_28 ? 2'h3 : iwb_stage_iReg__GEN_2865; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_268 = iwb_stage_iReg__GEN_2866 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_271 = ~iwb_stage_iReg__T_268; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2868 = 6'h1 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2869 = 6'h2 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2868; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2870 = 6'h3 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2869; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2871 = 6'h4 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2870; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2872 = 6'h5 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2871; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2873 = 6'h6 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2872; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2874 = 6'h7 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2873; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2875 = 6'h8 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2874; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2876 = 6'h9 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2875; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2877 = 6'ha == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2876; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2878 = 6'hb == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2877; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2879 = 6'hc == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2878; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2880 = 6'hd == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2879; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2881 = 6'he == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2880; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2882 = 6'hf == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2881; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2883 = 6'h10 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2882; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2884 = 6'h11 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2883; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2885 = 6'h12 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2884; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2886 = 6'h13 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2885; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2887 = 6'h14 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2886; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2888 = 6'h15 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2887; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2889 = 6'h16 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2888; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2890 = 6'h17 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2889; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2891 = 6'h18 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2890; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2892 = 6'h19 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2891; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2893 = 6'h1a == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2892; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2894 = 6'h1b == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2893; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2895 = 6'h1c == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2894; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2896 = 6'h1d == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2895; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2897 = 6'h1e == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2896; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2898 = 6'h1f == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2897; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2899 = 6'h20 == iwb_stage_iReg_archit_ptr_29 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2898; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2900 = 6'h21 == iwb_stage_iReg_archit_ptr_29 ? 2'h3 : iwb_stage_iReg__GEN_2899; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_272 = iwb_stage_iReg__GEN_2900 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_275 = ~iwb_stage_iReg__T_272; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2902 = 6'h1 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2903 = 6'h2 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2902; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2904 = 6'h3 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2903; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2905 = 6'h4 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2904; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2906 = 6'h5 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2905; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2907 = 6'h6 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2906; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2908 = 6'h7 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2907; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2909 = 6'h8 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2908; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2910 = 6'h9 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2909; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2911 = 6'ha == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2910; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2912 = 6'hb == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2911; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2913 = 6'hc == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2912; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2914 = 6'hd == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2913; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2915 = 6'he == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2914; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2916 = 6'hf == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2915; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2917 = 6'h10 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2916; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2918 = 6'h11 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2917; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2919 = 6'h12 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2918; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2920 = 6'h13 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2919; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2921 = 6'h14 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2920; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2922 = 6'h15 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2921; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2923 = 6'h16 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2922; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2924 = 6'h17 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2923; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2925 = 6'h18 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2924; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2926 = 6'h19 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2925; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2927 = 6'h1a == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2926; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2928 = 6'h1b == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2927; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2929 = 6'h1c == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2928; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2930 = 6'h1d == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2929; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2931 = 6'h1e == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2930; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2932 = 6'h1f == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2931; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2933 = 6'h20 == iwb_stage_iReg_archit_ptr_30 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2932; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2934 = 6'h21 == iwb_stage_iReg_archit_ptr_30 ? 2'h3 : iwb_stage_iReg__GEN_2933; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_276 = iwb_stage_iReg__GEN_2934 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_279 = ~iwb_stage_iReg__T_276; // @[Regfiles.scala 242:16]
  wire [1:0] iwb_stage_iReg__GEN_2936 = 6'h1 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_1 :
    iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2937 = 6'h2 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_2 :
    iwb_stage_iReg__GEN_2936; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2938 = 6'h3 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_3 :
    iwb_stage_iReg__GEN_2937; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2939 = 6'h4 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_4 :
    iwb_stage_iReg__GEN_2938; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2940 = 6'h5 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_5 :
    iwb_stage_iReg__GEN_2939; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2941 = 6'h6 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_6 :
    iwb_stage_iReg__GEN_2940; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2942 = 6'h7 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_7 :
    iwb_stage_iReg__GEN_2941; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2943 = 6'h8 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_8 :
    iwb_stage_iReg__GEN_2942; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2944 = 6'h9 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_9 :
    iwb_stage_iReg__GEN_2943; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2945 = 6'ha == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_10 :
    iwb_stage_iReg__GEN_2944; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2946 = 6'hb == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_11 :
    iwb_stage_iReg__GEN_2945; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2947 = 6'hc == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_12 :
    iwb_stage_iReg__GEN_2946; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2948 = 6'hd == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_13 :
    iwb_stage_iReg__GEN_2947; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2949 = 6'he == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_14 :
    iwb_stage_iReg__GEN_2948; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2950 = 6'hf == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_15 :
    iwb_stage_iReg__GEN_2949; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2951 = 6'h10 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_16 :
    iwb_stage_iReg__GEN_2950; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2952 = 6'h11 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_17 :
    iwb_stage_iReg__GEN_2951; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2953 = 6'h12 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_18 :
    iwb_stage_iReg__GEN_2952; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2954 = 6'h13 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_19 :
    iwb_stage_iReg__GEN_2953; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2955 = 6'h14 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_20 :
    iwb_stage_iReg__GEN_2954; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2956 = 6'h15 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_21 :
    iwb_stage_iReg__GEN_2955; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2957 = 6'h16 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_22 :
    iwb_stage_iReg__GEN_2956; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2958 = 6'h17 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_23 :
    iwb_stage_iReg__GEN_2957; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2959 = 6'h18 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_24 :
    iwb_stage_iReg__GEN_2958; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2960 = 6'h19 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_25 :
    iwb_stage_iReg__GEN_2959; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2961 = 6'h1a == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_26 :
    iwb_stage_iReg__GEN_2960; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2962 = 6'h1b == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_27 :
    iwb_stage_iReg__GEN_2961; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2963 = 6'h1c == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_28 :
    iwb_stage_iReg__GEN_2962; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2964 = 6'h1d == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_29 :
    iwb_stage_iReg__GEN_2963; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2965 = 6'h1e == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_30 :
    iwb_stage_iReg__GEN_2964; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2966 = 6'h1f == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_31 :
    iwb_stage_iReg__GEN_2965; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2967 = 6'h20 == iwb_stage_iReg_archit_ptr_31 ? iwb_stage_iReg_log_reg_32 :
    iwb_stage_iReg__GEN_2966; // @[Regfiles.scala 242:{25,25}]
  wire [1:0] iwb_stage_iReg__GEN_2968 = 6'h21 == iwb_stage_iReg_archit_ptr_31 ? 2'h3 : iwb_stage_iReg__GEN_2967; // @[Regfiles.scala 242:{25,25}]
  wire  iwb_stage_iReg__T_280 = iwb_stage_iReg__GEN_2968 == 2'h3; // @[Regfiles.scala 242:25]
  wire  iwb_stage_iReg__T_283 = ~iwb_stage_iReg__T_280; // @[Regfiles.scala 242:16]
  wire  iwb_stage_iReg__io_lookup_0_rsp_rs1_T = iwb_stage_iReg_io_lookup_0_req_rs1 == 5'h0; // @[Regfiles.scala 258:41]
  wire [5:0] iwb_stage_iReg__GEN_2970 = 5'h1 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_1 :
    iwb_stage_iReg_rename_ptr_0; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2971 = 5'h2 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_2 :
    iwb_stage_iReg__GEN_2970; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2972 = 5'h3 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_3 :
    iwb_stage_iReg__GEN_2971; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2973 = 5'h4 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_4 :
    iwb_stage_iReg__GEN_2972; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2974 = 5'h5 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_5 :
    iwb_stage_iReg__GEN_2973; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2975 = 5'h6 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_6 :
    iwb_stage_iReg__GEN_2974; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2976 = 5'h7 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_7 :
    iwb_stage_iReg__GEN_2975; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2977 = 5'h8 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_8 :
    iwb_stage_iReg__GEN_2976; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2978 = 5'h9 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_9 :
    iwb_stage_iReg__GEN_2977; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2979 = 5'ha == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_10 :
    iwb_stage_iReg__GEN_2978; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2980 = 5'hb == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_11 :
    iwb_stage_iReg__GEN_2979; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2981 = 5'hc == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_12 :
    iwb_stage_iReg__GEN_2980; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2982 = 5'hd == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_13 :
    iwb_stage_iReg__GEN_2981; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2983 = 5'he == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_14 :
    iwb_stage_iReg__GEN_2982; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2984 = 5'hf == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_15 :
    iwb_stage_iReg__GEN_2983; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2985 = 5'h10 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_16 :
    iwb_stage_iReg__GEN_2984; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2986 = 5'h11 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_17 :
    iwb_stage_iReg__GEN_2985; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2987 = 5'h12 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_18 :
    iwb_stage_iReg__GEN_2986; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2988 = 5'h13 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_19 :
    iwb_stage_iReg__GEN_2987; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2989 = 5'h14 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_20 :
    iwb_stage_iReg__GEN_2988; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2990 = 5'h15 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_21 :
    iwb_stage_iReg__GEN_2989; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2991 = 5'h16 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_22 :
    iwb_stage_iReg__GEN_2990; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2992 = 5'h17 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_23 :
    iwb_stage_iReg__GEN_2991; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2993 = 5'h18 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_24 :
    iwb_stage_iReg__GEN_2992; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2994 = 5'h19 == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_25 :
    iwb_stage_iReg__GEN_2993; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2995 = 5'h1a == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_26 :
    iwb_stage_iReg__GEN_2994; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2996 = 5'h1b == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_27 :
    iwb_stage_iReg__GEN_2995; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2997 = 5'h1c == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_28 :
    iwb_stage_iReg__GEN_2996; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2998 = 5'h1d == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_29 :
    iwb_stage_iReg__GEN_2997; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_2999 = 5'h1e == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_30 :
    iwb_stage_iReg__GEN_2998; // @[Regfiles.scala 258:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3000 = 5'h1f == iwb_stage_iReg_io_lookup_0_req_rs1 ? iwb_stage_iReg_rename_ptr_31 :
    iwb_stage_iReg__GEN_2999; // @[Regfiles.scala 258:{34,34}]
  wire  iwb_stage_iReg__io_lookup_0_rsp_rs2_T = iwb_stage_iReg_io_lookup_0_req_rs2 == 5'h0; // @[Regfiles.scala 259:41]
  wire [5:0] iwb_stage_iReg__GEN_3002 = 5'h1 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_1 :
    iwb_stage_iReg_rename_ptr_0; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3003 = 5'h2 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_2 :
    iwb_stage_iReg__GEN_3002; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3004 = 5'h3 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_3 :
    iwb_stage_iReg__GEN_3003; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3005 = 5'h4 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_4 :
    iwb_stage_iReg__GEN_3004; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3006 = 5'h5 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_5 :
    iwb_stage_iReg__GEN_3005; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3007 = 5'h6 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_6 :
    iwb_stage_iReg__GEN_3006; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3008 = 5'h7 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_7 :
    iwb_stage_iReg__GEN_3007; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3009 = 5'h8 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_8 :
    iwb_stage_iReg__GEN_3008; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3010 = 5'h9 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_9 :
    iwb_stage_iReg__GEN_3009; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3011 = 5'ha == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_10 :
    iwb_stage_iReg__GEN_3010; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3012 = 5'hb == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_11 :
    iwb_stage_iReg__GEN_3011; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3013 = 5'hc == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_12 :
    iwb_stage_iReg__GEN_3012; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3014 = 5'hd == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_13 :
    iwb_stage_iReg__GEN_3013; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3015 = 5'he == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_14 :
    iwb_stage_iReg__GEN_3014; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3016 = 5'hf == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_15 :
    iwb_stage_iReg__GEN_3015; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3017 = 5'h10 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_16 :
    iwb_stage_iReg__GEN_3016; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3018 = 5'h11 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_17 :
    iwb_stage_iReg__GEN_3017; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3019 = 5'h12 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_18 :
    iwb_stage_iReg__GEN_3018; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3020 = 5'h13 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_19 :
    iwb_stage_iReg__GEN_3019; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3021 = 5'h14 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_20 :
    iwb_stage_iReg__GEN_3020; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3022 = 5'h15 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_21 :
    iwb_stage_iReg__GEN_3021; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3023 = 5'h16 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_22 :
    iwb_stage_iReg__GEN_3022; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3024 = 5'h17 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_23 :
    iwb_stage_iReg__GEN_3023; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3025 = 5'h18 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_24 :
    iwb_stage_iReg__GEN_3024; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3026 = 5'h19 == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_25 :
    iwb_stage_iReg__GEN_3025; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3027 = 5'h1a == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_26 :
    iwb_stage_iReg__GEN_3026; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3028 = 5'h1b == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_27 :
    iwb_stage_iReg__GEN_3027; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3029 = 5'h1c == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_28 :
    iwb_stage_iReg__GEN_3028; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3030 = 5'h1d == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_29 :
    iwb_stage_iReg__GEN_3029; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3031 = 5'h1e == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_30 :
    iwb_stage_iReg__GEN_3030; // @[Regfiles.scala 259:{34,34}]
  wire [5:0] iwb_stage_iReg__GEN_3032 = 5'h1f == iwb_stage_iReg_io_lookup_0_req_rs2 ? iwb_stage_iReg_rename_ptr_31 :
    iwb_stage_iReg__GEN_3031; // @[Regfiles.scala 259:{34,34}]
  wire  _GEN_461 = iwb_stage_iReg__T_114 & iwb_stage_iReg__T_37; // @[Regfiles.scala 227:13]
  wire  iwb_stage_fReg_clock;
  wire  iwb_stage_fReg_reset;
  wire [5:0] iwb_stage_fReg_io_lookup_0_rsp_rs1;
  wire [5:0] iwb_stage_fReg_io_lookup_0_rsp_rs2;
  wire [5:0] iwb_stage_fReg_io_lookup_0_rsp_rs3;
  wire [5:0] iwb_stage_fReg_io_rename_0_rsp_rd0;
  wire  iwb_stage_fReg_io_rename_0_req_ready;
  wire [1:0] iwb_stage_fReg_io_rgLog_0;
  wire [1:0] iwb_stage_fReg_io_rgLog_1;
  wire [1:0] iwb_stage_fReg_io_rgLog_2;
  wire [1:0] iwb_stage_fReg_io_rgLog_3;
  wire [1:0] iwb_stage_fReg_io_rgLog_4;
  wire [1:0] iwb_stage_fReg_io_rgLog_5;
  wire [1:0] iwb_stage_fReg_io_rgLog_6;
  wire [1:0] iwb_stage_fReg_io_rgLog_7;
  wire [1:0] iwb_stage_fReg_io_rgLog_8;
  wire [1:0] iwb_stage_fReg_io_rgLog_9;
  wire [1:0] iwb_stage_fReg_io_rgLog_10;
  wire [1:0] iwb_stage_fReg_io_rgLog_11;
  wire [1:0] iwb_stage_fReg_io_rgLog_12;
  wire [1:0] iwb_stage_fReg_io_rgLog_13;
  wire [1:0] iwb_stage_fReg_io_rgLog_14;
  wire [1:0] iwb_stage_fReg_io_rgLog_15;
  wire [1:0] iwb_stage_fReg_io_rgLog_16;
  wire [1:0] iwb_stage_fReg_io_rgLog_17;
  wire [1:0] iwb_stage_fReg_io_rgLog_18;
  wire [1:0] iwb_stage_fReg_io_rgLog_19;
  wire [1:0] iwb_stage_fReg_io_rgLog_20;
  wire [1:0] iwb_stage_fReg_io_rgLog_21;
  wire [1:0] iwb_stage_fReg_io_rgLog_22;
  wire [1:0] iwb_stage_fReg_io_rgLog_23;
  wire [1:0] iwb_stage_fReg_io_rgLog_24;
  wire [1:0] iwb_stage_fReg_io_rgLog_25;
  wire [1:0] iwb_stage_fReg_io_rgLog_26;
  wire [1:0] iwb_stage_fReg_io_rgLog_27;
  wire [1:0] iwb_stage_fReg_io_rgLog_28;
  wire [1:0] iwb_stage_fReg_io_rgLog_29;
  wire [1:0] iwb_stage_fReg_io_rgLog_30;
  wire [1:0] iwb_stage_fReg_io_rgLog_31;
  wire [1:0] iwb_stage_fReg_io_rgLog_32;
  wire [1:0] iwb_stage_fReg_io_rgLog_33;
  wire  iwb_stage_fReg_io_exe_writeBack_0_ready;
  wire  iwb_stage_fReg_io_exe_writeBack_0_valid;
  wire  iwb_stage_fReg_io_exe_writeBack_1_valid;
  wire  iwb_stage_fReg_io_commit_0_is_writeback;
  wire  iwb_stage_fReg__T = ~iwb_stage_fReg_io_exe_writeBack_0_valid; // @[Regfiles.scala 324:13]
  wire  iwb_stage_fReg__T_2 = ~iwb_stage_fReg_reset; // @[Regfiles.scala 324:11]
  wire  iwb_stage_fReg__T_3 = ~iwb_stage_fReg__T; // @[Regfiles.scala 324:11]
  wire  iwb_stage_fReg__T_4 = ~iwb_stage_fReg_io_exe_writeBack_1_valid; // @[Regfiles.scala 324:13]
  wire  iwb_stage_fReg__T_7 = ~iwb_stage_fReg__T_4; // @[Regfiles.scala 324:11]
  wire  iwb_stage_iwriteBack_arb_io_enq_0_ready;
  wire  iwb_stage_iwriteBack_arb_io_enq_0_valid;
  wire [5:0] iwb_stage_iwriteBack_arb_io_enq_0_bits_rd0;
  wire [63:0] iwb_stage_iwriteBack_arb_io_enq_0_bits_res;
  wire  iwb_stage_iwriteBack_arb_io_enq_1_ready;
  wire  iwb_stage_iwriteBack_arb_io_enq_1_valid;
  wire [5:0] iwb_stage_iwriteBack_arb_io_enq_1_bits_rd0;
  wire [63:0] iwb_stage_iwriteBack_arb_io_enq_1_bits_res;
  wire  iwb_stage_iwriteBack_arb_io_enq_2_ready;
  wire  iwb_stage_iwriteBack_arb_io_enq_2_valid;
  wire [5:0] iwb_stage_iwriteBack_arb_io_enq_2_bits_rd0;
  wire [63:0] iwb_stage_iwriteBack_arb_io_enq_2_bits_res;
  wire  iwb_stage_iwriteBack_arb_io_enq_3_ready;
  wire  iwb_stage_iwriteBack_arb_io_enq_3_valid;
  wire [5:0] iwb_stage_iwriteBack_arb_io_enq_3_bits_rd0;
  wire [63:0] iwb_stage_iwriteBack_arb_io_enq_3_bits_res;
  wire  iwb_stage_iwriteBack_arb_io_enq_4_ready;
  wire  iwb_stage_iwriteBack_arb_io_enq_4_valid;
  wire [5:0] iwb_stage_iwriteBack_arb_io_enq_4_bits_rd0;
  wire [63:0] iwb_stage_iwriteBack_arb_io_enq_4_bits_res;
  wire  iwb_stage_iwriteBack_arb_io_enq_5_valid;
  wire [5:0] iwb_stage_iwriteBack_arb_io_enq_5_bits_rd0;
  wire [63:0] iwb_stage_iwriteBack_arb_io_enq_5_bits_res;
  wire  iwb_stage_iwriteBack_arb_io_deq_0_ready;
  wire  iwb_stage_iwriteBack_arb_io_deq_0_valid;
  wire [5:0] iwb_stage_iwriteBack_arb_io_deq_0_bits_rd0;
  wire [63:0] iwb_stage_iwriteBack_arb_io_deq_0_bits_res;
  wire [2:0] iwb_stage_iwriteBack_arb_io_chosen_0;
  wire [2:0] iwb_stage_iwriteBack_arb__GEN_0 = iwb_stage_iwriteBack_arb_io_enq_5_valid ? 3'h5 : 3'h0; // @[XArbiter.scala 34:18 36:31 37:38]
  wire [2:0] iwb_stage_iwriteBack_arb__GEN_1 = iwb_stage_iwriteBack_arb_io_enq_4_valid ? 3'h4 :
    iwb_stage_iwriteBack_arb__GEN_0; // @[XArbiter.scala 36:31 37:38]
  wire [2:0] iwb_stage_iwriteBack_arb__GEN_2 = iwb_stage_iwriteBack_arb_io_enq_3_valid ? 3'h3 :
    iwb_stage_iwriteBack_arb__GEN_1; // @[XArbiter.scala 36:31 37:38]
  wire [2:0] iwb_stage_iwriteBack_arb__GEN_3 = iwb_stage_iwriteBack_arb_io_enq_2_valid ? 3'h2 :
    iwb_stage_iwriteBack_arb__GEN_2; // @[XArbiter.scala 36:31 37:38]
  wire [2:0] iwb_stage_iwriteBack_arb__GEN_4 = iwb_stage_iwriteBack_arb_io_enq_1_valid ? 3'h1 :
    iwb_stage_iwriteBack_arb__GEN_3; // @[XArbiter.scala 36:31 37:38]
  wire [1:0] iwb_stage_iwriteBack_arb__T_6 = iwb_stage_iwriteBack_arb_io_enq_1_valid +
    iwb_stage_iwriteBack_arb_io_enq_2_valid; // @[XArbiter.scala 53:23]
  wire [1:0] _GEN_463 = {{1'd0}, iwb_stage_iwriteBack_arb_io_enq_0_valid}; // @[XArbiter.scala 53:23]
  wire [2:0] iwb_stage_iwriteBack_arb__T_8 = _GEN_463 + iwb_stage_iwriteBack_arb__T_6; // @[XArbiter.scala 53:23]
  wire [1:0] iwb_stage_iwriteBack_arb__T_9 = iwb_stage_iwriteBack_arb__T_8[1:0]; // @[XArbiter.scala 53:23]
  wire [1:0] iwb_stage_iwriteBack_arb__T_10 = iwb_stage_iwriteBack_arb_io_enq_4_valid +
    iwb_stage_iwriteBack_arb_io_enq_5_valid; // @[XArbiter.scala 53:23]
  wire [1:0] _GEN_464 = {{1'd0}, iwb_stage_iwriteBack_arb_io_enq_3_valid}; // @[XArbiter.scala 53:23]
  wire [2:0] iwb_stage_iwriteBack_arb__T_12 = _GEN_464 + iwb_stage_iwriteBack_arb__T_10; // @[XArbiter.scala 53:23]
  wire [1:0] iwb_stage_iwriteBack_arb__T_13 = iwb_stage_iwriteBack_arb__T_12[1:0]; // @[XArbiter.scala 53:23]
  wire [2:0] iwb_stage_iwriteBack_arb__T_14 = iwb_stage_iwriteBack_arb__T_9 + iwb_stage_iwriteBack_arb__T_13; // @[XArbiter.scala 53:23]
  wire  iwb_stage_iwriteBack_arb__T_16 = iwb_stage_iwriteBack_arb__T_14 > 3'h0; // @[XArbiter.scala 53:68]
  wire [5:0] iwb_stage_iwriteBack_arb__GEN_7 = 3'h1 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_1_bits_rd0 : iwb_stage_iwriteBack_arb_io_enq_0_bits_rd0; // @[XArbiter.scala 55:{22,22}]
  wire [5:0] iwb_stage_iwriteBack_arb__GEN_8 = 3'h2 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_2_bits_rd0 : iwb_stage_iwriteBack_arb__GEN_7; // @[XArbiter.scala 55:{22,22}]
  wire [5:0] iwb_stage_iwriteBack_arb__GEN_9 = 3'h3 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_3_bits_rd0 : iwb_stage_iwriteBack_arb__GEN_8; // @[XArbiter.scala 55:{22,22}]
  wire [5:0] iwb_stage_iwriteBack_arb__GEN_10 = 3'h4 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_4_bits_rd0 : iwb_stage_iwriteBack_arb__GEN_9; // @[XArbiter.scala 55:{22,22}]
  wire [63:0] iwb_stage_iwriteBack_arb__GEN_13 = 3'h1 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_1_bits_res : iwb_stage_iwriteBack_arb_io_enq_0_bits_res; // @[XArbiter.scala 55:{22,22}]
  wire [63:0] iwb_stage_iwriteBack_arb__GEN_14 = 3'h2 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_2_bits_res : iwb_stage_iwriteBack_arb__GEN_13; // @[XArbiter.scala 55:{22,22}]
  wire [63:0] iwb_stage_iwriteBack_arb__GEN_15 = 3'h3 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_3_bits_res : iwb_stage_iwriteBack_arb__GEN_14; // @[XArbiter.scala 55:{22,22}]
  wire [63:0] iwb_stage_iwriteBack_arb__GEN_16 = 3'h4 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_4_bits_res : iwb_stage_iwriteBack_arb__GEN_15; // @[XArbiter.scala 55:{22,22}]
  wire  iwb_stage_iwriteBack_arb__GEN_18 = 3'h0 == iwb_stage_iwriteBack_arb_io_chosen_0 &
    iwb_stage_iwriteBack_arb_io_deq_0_ready; // @[XArbiter.scala 57:{25,25} 50:51]
  wire  iwb_stage_iwriteBack_arb__GEN_19 = 3'h1 == iwb_stage_iwriteBack_arb_io_chosen_0 &
    iwb_stage_iwriteBack_arb_io_deq_0_ready; // @[XArbiter.scala 57:{25,25} 50:51]
  wire  iwb_stage_iwriteBack_arb__GEN_20 = 3'h2 == iwb_stage_iwriteBack_arb_io_chosen_0 &
    iwb_stage_iwriteBack_arb_io_deq_0_ready; // @[XArbiter.scala 57:{25,25} 50:51]
  wire  iwb_stage_iwriteBack_arb__GEN_21 = 3'h3 == iwb_stage_iwriteBack_arb_io_chosen_0 &
    iwb_stage_iwriteBack_arb_io_deq_0_ready; // @[XArbiter.scala 57:{25,25} 50:51]
  wire  iwb_stage_iwriteBack_arb__GEN_22 = 3'h4 == iwb_stage_iwriteBack_arb_io_chosen_0 &
    iwb_stage_iwriteBack_arb_io_deq_0_ready; // @[XArbiter.scala 57:{25,25} 50:51]
  wire  iwb_stage__GEN_7 = iwb_stage_io_commit_0_toF & iwb_stage_fReg_io_commit_0_is_writeback; // @[WriteBack.scala 100:31 103:{46,65}]
  wire  cmm_stage_clock;
  wire  cmm_stage_reset;
  wire  cmm_stage_io_cm_op_0_is_comfirm;
  wire  cmm_stage_io_cm_op_0_is_MisPredict;
  wire  cmm_stage_io_cm_op_0_is_abort;
  wire [4:0] cmm_stage_io_cm_op_0_raw;
  wire [5:0] cmm_stage_io_cm_op_0_phy;
  wire  cmm_stage_io_cm_op_0_toX;
  wire  cmm_stage_io_cm_op_0_toF;
  wire  cmm_stage_io_cm_op_0_is_writeback;
  wire  cmm_stage_io_rod_0_ready;
  wire  cmm_stage_io_rod_0_valid;
  wire [38:0] cmm_stage_io_rod_0_bits_pc;
  wire [4:0] cmm_stage_io_rod_0_bits_rd0_raw;
  wire [5:0] cmm_stage_io_rod_0_bits_rd0_phy;
  wire  cmm_stage_io_rod_0_bits_is_branch;
  wire  cmm_stage_io_rod_0_bits_is_jalr;
  wire  cmm_stage_io_rod_0_bits_is_lu;
  wire  cmm_stage_io_rod_0_bits_is_su;
  wire  cmm_stage_io_rod_0_bits_is_amo;
  wire  cmm_stage_io_rod_0_bits_is_fence_i;
  wire  cmm_stage_io_rod_0_bits_is_sfence_vma;
  wire  cmm_stage_io_rod_0_bits_is_wfi;
  wire  cmm_stage_io_rod_0_bits_is_csr;
  wire  cmm_stage_io_rod_0_bits_is_fpu;
  wire  cmm_stage_io_rod_0_bits_is_fcsr;
  wire  cmm_stage_io_rod_0_bits_is_xcmm;
  wire  cmm_stage_io_rod_0_bits_is_fcmm;
  wire  cmm_stage_io_rod_0_bits_privil_ecall;
  wire  cmm_stage_io_rod_0_bits_privil_ebreak;
  wire  cmm_stage_io_rod_0_bits_privil_mret;
  wire  cmm_stage_io_rod_0_bits_privil_sret;
  wire  cmm_stage_io_rod_0_bits_privil_dret;
  wire  cmm_stage_io_rod_0_bits_privil_is_access_fault;
  wire  cmm_stage_io_rod_0_bits_privil_is_paging_fault;
  wire  cmm_stage_io_rod_0_bits_is_illeage;
  wire  cmm_stage_io_cmm_lsu_is_amo_pending;
  wire  cmm_stage_io_cmm_lsu_is_store_commit_0;
  wire  cmm_stage_io_lsu_cmm_is_access_fault;
  wire  cmm_stage_io_lsu_cmm_is_paging_fault;
  wire  cmm_stage_io_lsu_cmm_is_misAlign;
  wire [63:0] cmm_stage_io_lsu_cmm_trap_addr;
  wire  cmm_stage_io_csr_addr_valid;
  wire [11:0] cmm_stage_io_csr_addr_bits;
  wire  cmm_stage_io_csr_data_valid;
  wire [63:0] cmm_stage_io_csr_data_bits;
  wire  cmm_stage_io_csr_cmm_op_ready;
  wire  cmm_stage_io_csr_cmm_op_valid;
  wire [11:0] cmm_stage_io_csr_cmm_op_bits_addr;
  wire [63:0] cmm_stage_io_csr_cmm_op_bits_dat_i;
  wire  cmm_stage_io_csr_cmm_op_bits_op_rw;
  wire  cmm_stage_io_csr_cmm_op_bits_op_rs;
  wire  cmm_stage_io_csr_cmm_op_bits_op_rc;
  wire  cmm_stage_io_bctq_ready;
  wire  cmm_stage_io_bctq_valid;
  wire  cmm_stage_io_bctq_bits_isPredictTaken;
  wire  cmm_stage_io_bctq_bits_isFinalTaken;
  wire [63:0] cmm_stage_io_bctq_bits_finalTarget;
  wire  cmm_stage_io_jctq_ready;
  wire  cmm_stage_io_jctq_valid;
  wire [38:0] cmm_stage_io_jctq_bits_btbResp_target;
  wire [38:0] cmm_stage_io_jctq_bits_rasResp_target;
  wire  cmm_stage_io_jctq_bits_isRas;
  wire [63:0] cmm_stage_io_jctq_bits_finalTarget;
  wire  cmm_stage_io_cmmRedirect_valid;
  wire [63:0] cmm_stage_io_cmmRedirect_bits_pc;
  wire [63:0] cmm_stage_io_if_cmm_ill_vaddr;
  wire  cmm_stage_io_ifence;
  wire [63:0] cmm_stage_io_cmm_mmu_satp;
  wire [1:0] cmm_stage_io_cmm_mmu_priv_lvl_if;
  wire [1:0] cmm_stage_io_cmm_mmu_priv_lvl_ls;
  wire [63:0] cmm_stage_io_cmm_mmu_mstatus;
  wire [63:0] cmm_stage_io_cmm_mmu_sstatus;
  wire  cmm_stage_io_cmm_mmu_sfence_vma;
  wire  cmm_stage_io_fcsr_cmm_op_0_valid;
  wire [11:0] cmm_stage_io_fcsr_cmm_op_0_bits_addr;
  wire [63:0] cmm_stage_io_fcsr_cmm_op_0_bits_dat_i;
  wire  cmm_stage_io_fcsr_cmm_op_0_bits_op_rw;
  wire  cmm_stage_io_fcsr_cmm_op_0_bits_op_rs;
  wire  cmm_stage_io_fcsr_cmm_op_0_bits_op_rc;
  wire  cmm_stage_io_dm_hartIsInReset;
  wire  cmm_stage_io_dm_hartResetReq;
  wire  cmm_stage_io_dm_hartHaltReq;
  wire  cmm_stage_io_rtc_clock;
  wire  cmm_stage_io_aclint_msi;
  wire  cmm_stage_io_aclint_mti;
  wire  cmm_stage_io_aclint_ssi;
  wire  cmm_stage_io_aclint_sti;
  wire  cmm_stage_io_plic_mei;
  wire  cmm_stage_io_plic_sei;
  wire  cmm_stage_bctq_mdl_io_enq_0_ready;
  wire  cmm_stage_bctq_mdl_io_enq_0_valid;
  wire  cmm_stage_bctq_mdl_io_enq_0_bits_isPredictTaken;
  wire  cmm_stage_bctq_mdl_io_enq_0_bits_isFinalTaken;
  wire [63:0] cmm_stage_bctq_mdl_io_enq_0_bits_finalTarget;
  wire  cmm_stage_bctq_mdl_io_deq_0_ready;
  wire  cmm_stage_bctq_mdl_io_deq_0_valid;
  wire  cmm_stage_bctq_mdl_io_deq_0_bits_isPredictTaken;
  wire  cmm_stage_bctq_mdl_io_deq_0_bits_isFinalTaken;
  wire [63:0] cmm_stage_bctq_mdl_io_deq_0_bits_finalTarget;
  wire  cmm_stage_bctq_mdl_io_mapper_0;
  wire  cmm_stage_jctq_mdl_io_enq_0_ready;
  wire  cmm_stage_jctq_mdl_io_enq_0_valid;
  wire [38:0] cmm_stage_jctq_mdl_io_enq_0_bits_btbResp_target;
  wire [38:0] cmm_stage_jctq_mdl_io_enq_0_bits_rasResp_target;
  wire  cmm_stage_jctq_mdl_io_enq_0_bits_isRas;
  wire [63:0] cmm_stage_jctq_mdl_io_enq_0_bits_finalTarget;
  wire  cmm_stage_jctq_mdl_io_deq_0_ready;
  wire  cmm_stage_jctq_mdl_io_deq_0_valid;
  wire [38:0] cmm_stage_jctq_mdl_io_deq_0_bits_btbResp_target;
  wire [38:0] cmm_stage_jctq_mdl_io_deq_0_bits_rasResp_target;
  wire  cmm_stage_jctq_mdl_io_deq_0_bits_isRas;
  wire [63:0] cmm_stage_jctq_mdl_io_deq_0_bits_finalTarget;
  wire  cmm_stage_jctq_mdl_io_mapper_0;
  wire  cmm_stage_csrExe_mdl_io_enq_0_ready;
  wire  cmm_stage_csrExe_mdl_io_enq_0_valid;
  wire [11:0] cmm_stage_csrExe_mdl_io_enq_0_bits_addr;
  wire [63:0] cmm_stage_csrExe_mdl_io_enq_0_bits_dat_i;
  wire  cmm_stage_csrExe_mdl_io_enq_0_bits_op_rw;
  wire  cmm_stage_csrExe_mdl_io_enq_0_bits_op_rs;
  wire  cmm_stage_csrExe_mdl_io_enq_0_bits_op_rc;
  wire  cmm_stage_csrExe_mdl_io_deq_0_ready;
  wire  cmm_stage_csrExe_mdl_io_deq_0_valid;
  wire [11:0] cmm_stage_csrExe_mdl_io_deq_0_bits_addr;
  wire [63:0] cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i;
  wire  cmm_stage_csrExe_mdl_io_deq_0_bits_op_rw;
  wire  cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs;
  wire  cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc;
  wire  cmm_stage_csrExe_mdl_io_mapper_0;
  wire  cmm_stage_fcsrExe_mdl_io_enq_0_valid;
  wire [11:0] cmm_stage_fcsrExe_mdl_io_enq_0_bits_addr;
  wire [63:0] cmm_stage_fcsrExe_mdl_io_enq_0_bits_dat_i;
  wire  cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rw;
  wire  cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rs;
  wire  cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rc;
  wire  cmm_stage_fcsrExe_mdl_io_deq_0_ready;
  wire  cmm_stage_fcsrExe_mdl_io_deq_0_valid;
  wire [11:0] cmm_stage_fcsrExe_mdl_io_deq_0_bits_addr;
  wire [63:0] cmm_stage_fcsrExe_mdl_io_deq_0_bits_dat_i;
  wire  cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rw;
  wire  cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rs;
  wire  cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rc;
  wire  cmm_stage_fcsrExe_mdl_io_mapper_0;
  reg [1:0] cmm_stage_csrfiles_priv_lvl; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_DMode; // @[Commit.scala 322:21]
  reg [2:0] cmm_stage_csrfiles_fcsr_frm; // @[Commit.scala 322:21]
  reg [4:0] cmm_stage_csrfiles_fcsr_fflags; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_time; // @[Commit.scala 322:21]
  reg [61:0] cmm_stage_csrfiles_stvec_base; // @[Commit.scala 322:21]
  reg [31:0] cmm_stage_csrfiles_scounteren_hpm; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_sscratch; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_sepc; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_scause_interrupt; // @[Commit.scala 322:21]
  reg [62:0] cmm_stage_csrfiles_scause_exception_code; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_stval; // @[Commit.scala 322:21]
  reg [3:0] cmm_stage_csrfiles_satp_mode; // @[Commit.scala 322:21]
  reg [15:0] cmm_stage_csrfiles_satp_asid; // @[Commit.scala 322:21]
  reg [43:0] cmm_stage_csrfiles_satp_ppn; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_marchid; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_sd; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_tsr; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_tw; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_tvm; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_mxr; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_sum; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_mprv; // @[Commit.scala 322:21]
  reg [1:0] cmm_stage_csrfiles_mstatus_fs; // @[Commit.scala 322:21]
  reg [1:0] cmm_stage_csrfiles_mstatus_mpp; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_spp; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_mpie; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_spie; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_mie; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mstatus_sie; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_misa; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_medeleg; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_mideleg; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mie_mei; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mie_sei; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mie_mti; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mie_sti; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mie_msi; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mie_ssi; // @[Commit.scala 322:21]
  reg [61:0] cmm_stage_csrfiles_mtvec_base; // @[Commit.scala 322:21]
  reg [31:0] cmm_stage_csrfiles_mcounteren_hpm; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_mscratch; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_mepc; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mcause_interrupt; // @[Commit.scala 322:21]
  reg [62:0] cmm_stage_csrfiles_mcause_exception_code; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_mtval; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mip_mei; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mip_sei; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mip_mti; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mip_sti; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mip_msi; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_mip_ssi; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_mtinst; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_mtval2; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_mcycle; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_minstret; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_tselect; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_tdata1; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_tdata2; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_tdata3; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_dcsr_ebreakm; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_dcsr_ebreaks; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_dcsr_ebreaku; // @[Commit.scala 322:21]
  reg [2:0] cmm_stage_csrfiles_dcsr_cause; // @[Commit.scala 322:21]
  reg  cmm_stage_csrfiles_dcsr_step; // @[Commit.scala 322:21]
  reg [1:0] cmm_stage_csrfiles_dcsr_prv; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_dpc; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_dscratch0; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_dscratch1; // @[Commit.scala 322:21]
  reg [63:0] cmm_stage_csrfiles_dscratch2; // @[Commit.scala 322:21]
  wire  cmm_stage__T_6 = ~cmm_stage_io_rod_0_valid; // @[Commit.scala 419:12]
  wire  cmm_stage__is_xRet_is_mRet_T = cmm_stage_csrfiles_priv_lvl == 2'h3; // @[Commit.scala 165:55]
  wire  cmm_stage_is_xRet_is_mRet = cmm_stage_io_rod_0_bits_privil_mret & cmm_stage__is_xRet_is_mRet_T; // @[Commit.scala 165:35]
  wire  cmm_stage__is_xRet_is_sRet_T_1 = cmm_stage_csrfiles_priv_lvl == 2'h1; // @[Commit.scala 170:91]
  wire  cmm_stage__is_xRet_is_sRet_T_3 = ~cmm_stage_csrfiles_mstatus_tsr; // @[Commit.scala 170:105]
  wire  cmm_stage__is_xRet_is_sRet_T_4 = cmm_stage__is_xRet_is_sRet_T_1 & cmm_stage__is_xRet_is_sRet_T_3; // @[Commit.scala 170:103]
  wire  cmm_stage__is_xRet_is_sRet_T_5 = cmm_stage__is_xRet_is_mRet_T | cmm_stage__is_xRet_is_sRet_T_4; // @[Commit.scala 170:69]
  wire  cmm_stage_is_xRet_is_sRet = cmm_stage_io_rod_0_bits_privil_sret & cmm_stage__is_xRet_is_sRet_T_5; // @[Commit.scala 170:35]
  wire  cmm_stage__is_xRet_T = cmm_stage_is_xRet_is_mRet | cmm_stage_is_xRet_is_sRet; // @[Commit.scala 217:27]
  wire  cmm_stage_is_xRet_is_dRet = cmm_stage_io_rod_0_bits_privil_dret & cmm_stage_csrfiles_DMode; // @[Commit.scala 175:35]
  wire  cmm_stage_is_xRet = cmm_stage__is_xRet_T | cmm_stage_is_xRet_is_dRet; // @[Commit.scala 217:37]
  wire  cmm_stage__is_trap_is_interrupt_is_m_interrupt_is_msi_T = cmm_stage_csrfiles_mip_msi &
    cmm_stage_csrfiles_mie_msi; // @[CsrFiles.scala 284:26]
  wire  cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_msi = cmm_stage__is_trap_is_interrupt_is_m_interrupt_is_msi_T
     & cmm_stage_csrfiles_mstatus_mie; // @[CsrFiles.scala 284:36]
  wire  cmm_stage__is_trap_is_interrupt_is_m_interrupt_is_mti_T = cmm_stage_csrfiles_mip_mti &
    cmm_stage_csrfiles_mie_mti; // @[CsrFiles.scala 292:26]
  wire  cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_mti = cmm_stage__is_trap_is_interrupt_is_m_interrupt_is_mti_T
     & cmm_stage_csrfiles_mstatus_mie; // @[CsrFiles.scala 292:36]
  wire  cmm_stage__is_trap_is_interrupt_is_m_interrupt_T_2 = cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_msi |
    cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_mti; // @[CsrFiles.scala 304:33]
  wire  cmm_stage__is_trap_is_interrupt_is_m_interrupt_is_mei_T = cmm_stage_csrfiles_mip_mei &
    cmm_stage_csrfiles_mie_mei; // @[CsrFiles.scala 300:26]
  wire  cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_mei = cmm_stage__is_trap_is_interrupt_is_m_interrupt_is_mei_T
     & cmm_stage_csrfiles_mstatus_mie; // @[CsrFiles.scala 300:36]
  wire  cmm_stage_is_trap_is_interrupt_is_m_interrupt = cmm_stage__is_trap_is_interrupt_is_m_interrupt_T_2 |
    cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_mei; // @[CsrFiles.scala 304:42]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T = cmm_stage_csrfiles_mip_ssi &
    cmm_stage_csrfiles_mie_ssi; // @[CsrFiles.scala 280:26]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_1 =
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T & cmm_stage_csrfiles_mstatus_sie; // @[CsrFiles.scala 280:36]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_3 = cmm_stage_csrfiles_mideleg[1]; // @[CsrFiles.scala 280:85]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_4 = cmm_stage__is_xRet_is_mRet_T &
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_3; // @[CsrFiles.scala 280:76]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_5 = ~
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_4; // @[CsrFiles.scala 280:52]
  wire  cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_ssi = cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_1
     & cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_5; // @[CsrFiles.scala 280:50]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T = cmm_stage_csrfiles_mip_sti &
    cmm_stage_csrfiles_mie_sti; // @[CsrFiles.scala 288:26]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_1 =
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T & cmm_stage_csrfiles_mstatus_sie; // @[CsrFiles.scala 288:36]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_3 = cmm_stage_csrfiles_mideleg[5]; // @[CsrFiles.scala 288:85]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_4 = cmm_stage__is_xRet_is_mRet_T &
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_3; // @[CsrFiles.scala 288:76]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_5 = ~
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_4; // @[CsrFiles.scala 288:52]
  wire  cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_sti = cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_1
     & cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_5; // @[CsrFiles.scala 288:50]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_T_2 = cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_ssi |
    cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_sti; // @[CsrFiles.scala 308:33]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T = cmm_stage_csrfiles_mip_sei &
    cmm_stage_csrfiles_mie_sei; // @[CsrFiles.scala 296:26]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_1 =
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T & cmm_stage_csrfiles_mstatus_sie; // @[CsrFiles.scala 296:36]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_3 = cmm_stage_csrfiles_mideleg[9]; // @[CsrFiles.scala 296:85]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_4 = cmm_stage__is_xRet_is_mRet_T &
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_3; // @[CsrFiles.scala 296:76]
  wire  cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_5 = ~
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_4; // @[CsrFiles.scala 296:52]
  wire  cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_sei = cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_1
     & cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_5; // @[CsrFiles.scala 296:50]
  wire  cmm_stage_is_trap_is_interrupt_is_s_interrupt = cmm_stage__is_trap_is_interrupt_is_s_interrupt_T_2 |
    cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_sei; // @[CsrFiles.scala 308:42]
  wire  cmm_stage__is_trap_is_interrupt_T = cmm_stage_is_trap_is_interrupt_is_m_interrupt |
    cmm_stage_is_trap_is_interrupt_is_s_interrupt; // @[Commit.scala 207:51]
  wire  cmm_stage__is_trap_is_interrupt_T_2 = ~cmm_stage_csrfiles_DMode; // @[Commit.scala 207:80]
  wire  cmm_stage__is_trap_is_interrupt_T_3 = cmm_stage__is_trap_is_interrupt_T & cmm_stage__is_trap_is_interrupt_T_2; // @[Commit.scala 207:78]
  reg  cmm_stage_is_single_step; // @[Commit.scala 404:31]
  wire  cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_T_2 = cmm_stage_is_single_step |
    cmm_stage_io_dm_hartHaltReq; // @[Commit.scala 260:24]
  wire  cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_4 =
    cmm_stage__is_xRet_is_mRet_T & cmm_stage_csrfiles_dcsr_ebreakm; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_5 =
    cmm_stage__is_xRet_is_sRet_T_1 & cmm_stage_csrfiles_dcsr_ebreaks; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_7 =
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_4 |
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3 =
    cmm_stage_csrfiles_priv_lvl == 2'h0; // @[Commit.scala 232:29]
  wire  cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_6 =
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3 &
    cmm_stage_csrfiles_dcsr_ebreaku; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_8 =
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_7 |
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_6; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn =
    cmm_stage__is_trap_is_interrupt_T_2 &
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_8; // @[Commit.scala 228:49]
  wire  cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm =
    cmm_stage_io_rod_0_bits_privil_ebreak &
    cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn; // @[Commit.scala 253:42]
  wire  cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_T_3 =
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_T_2 |
    cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm; // @[Commit.scala 261:25]
  wire  cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt = cmm_stage__is_trap_is_interrupt_T_2 &
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_T_3; // @[Commit.scala 258:46]
  reg  cmm_stage_emu_reset; // @[Commit.scala 363:26]
  wire  cmm_stage_is_trap_is_interrupt_is_nomask_interrupt =
    cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt | cmm_stage_emu_reset; // @[Commit.scala 268:50]
  wire  cmm_stage__is_trap_is_interrupt_T_4 = cmm_stage__is_trap_is_interrupt_T_3 |
    cmm_stage_is_trap_is_interrupt_is_nomask_interrupt; // @[Commit.scala 207:100]
  wire  cmm_stage_is_trap_is_interrupt = cmm_stage__is_trap_is_interrupt_T_4 & cmm_stage__is_trap_is_interrupt_T_2; // @[Commit.scala 207:123]
  wire  cmm_stage__is_trap_is_exception_is_ebreak_exc_T_1 = ~
    cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn; // @[Commit.scala 120:45]
  wire  cmm_stage_is_trap_is_exception_is_ebreak_exc = cmm_stage_io_rod_0_bits_privil_ebreak &
    cmm_stage__is_trap_is_exception_is_ebreak_exc_T_1; // @[Commit.scala 120:43]
  wire  cmm_stage__is_trap_is_exception_T = cmm_stage_io_rod_0_bits_privil_ecall |
    cmm_stage_is_trap_is_exception_is_ebreak_exc; // @[Commit.scala 192:32]
  wire  cmm_stage__is_trap_is_exception_T_1 = cmm_stage__is_trap_is_exception_T |
    cmm_stage_io_rod_0_bits_privil_is_access_fault; // @[Commit.scala 193:32]
  wire  cmm_stage__is_trap_is_exception_T_2 = cmm_stage__is_trap_is_exception_T_1 |
    cmm_stage_io_rod_0_bits_privil_is_paging_fault; // @[Commit.scala 194:32]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0 = cmm_stage_io_csr_addr_bits == 12'h3a0; // @[CsrFiles.scala 314:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1 = cmm_stage_io_csr_addr_bits == 12'h3a2; // @[CsrFiles.scala 314:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_1 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_226 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2 = cmm_stage_io_csr_addr_bits == 12'h3a4; // @[CsrFiles.scala 314:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_2 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_227 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_226 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3 = cmm_stage_io_csr_addr_bits == 12'h3a6; // @[CsrFiles.scala 314:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_3 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_228 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_227 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_3; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4 = cmm_stage_io_csr_addr_bits == 12'h3a8; // @[CsrFiles.scala 314:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_4 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_229 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_228 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_4; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5 = cmm_stage_io_csr_addr_bits == 12'h3aa; // @[CsrFiles.scala 314:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_5 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_230 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_229 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6 = cmm_stage_io_csr_addr_bits == 12'h3ac; // @[CsrFiles.scala 314:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_6 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_231 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_230 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_6; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7 = cmm_stage_io_csr_addr_bits == 12'h3ae; // @[CsrFiles.scala 314:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_7 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_232 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_231 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_7; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0_1 = cmm_stage_io_csr_addr_bits == 12'h3b0; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_8 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_233 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_232 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_8; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1_1 = cmm_stage_io_csr_addr_bits == 12'h3b1; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_9 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_234 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_233 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_9; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2_1 = cmm_stage_io_csr_addr_bits == 12'h3b2; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_10 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_235 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_234 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_10; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3_1 = cmm_stage_io_csr_addr_bits == 12'h3b3; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_11 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_236 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_235 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_11; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4_1 = cmm_stage_io_csr_addr_bits == 12'h3b4; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_12 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_237 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_236 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_12; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5_1 = cmm_stage_io_csr_addr_bits == 12'h3b5; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_13 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_238 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_237 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_13; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6_1 = cmm_stage_io_csr_addr_bits == 12'h3b6; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_14 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_239 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_238 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_14; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7_1 = cmm_stage_io_csr_addr_bits == 12'h3b7; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_15 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7_1 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_240 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_239 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_8 = cmm_stage_io_csr_addr_bits == 12'h3b8; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_16 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_8 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_241 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_240 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_16; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_9 = cmm_stage_io_csr_addr_bits == 12'h3b9; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_17 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_9 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_242 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_241 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_17; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_10 = cmm_stage_io_csr_addr_bits == 12'h3ba; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_18 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_10 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_243 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_242 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_18; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_11 = cmm_stage_io_csr_addr_bits == 12'h3bb; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_19 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_11 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_244 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_243 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_19; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_12 = cmm_stage_io_csr_addr_bits == 12'h3bc; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_20 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_12 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_245 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_244 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_20; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_13 = cmm_stage_io_csr_addr_bits == 12'h3bd; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_21 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_13 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_246 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_245 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_21; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_14 = cmm_stage_io_csr_addr_bits == 12'h3be; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_22 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_14 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_247 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_246 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_22; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_15 = cmm_stage_io_csr_addr_bits == 12'h3bf; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_23 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_15 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_248 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_247 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_23; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_16 = cmm_stage_io_csr_addr_bits == 12'h3c0; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_24 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_16 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_249 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_248 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_24; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_17 = cmm_stage_io_csr_addr_bits == 12'h3c1; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_25 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_17 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_250 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_249 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_25; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_18 = cmm_stage_io_csr_addr_bits == 12'h3c2; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_26 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_18 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_251 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_250 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_26; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_19 = cmm_stage_io_csr_addr_bits == 12'h3c3; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_27 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_19 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_252 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_251 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_27; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_20 = cmm_stage_io_csr_addr_bits == 12'h3c4; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_28 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_20 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_253 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_252 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_28; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_21 = cmm_stage_io_csr_addr_bits == 12'h3c5; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_29 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_21 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_254 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_253 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_29; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_22 = cmm_stage_io_csr_addr_bits == 12'h3c6; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_30 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_22 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_255 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_254 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_30; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_23 = cmm_stage_io_csr_addr_bits == 12'h3c7; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_31 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_23 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_256 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_255 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_31; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_24 = cmm_stage_io_csr_addr_bits == 12'h3c8; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_32 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_24 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_257 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_256 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_32; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_25 = cmm_stage_io_csr_addr_bits == 12'h3c9; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_33 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_25 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_258 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_257 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_33; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_26 = cmm_stage_io_csr_addr_bits == 12'h3ca; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_34 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_26 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_259 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_258 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_34; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_27 = cmm_stage_io_csr_addr_bits == 12'h3cb; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_35 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_27 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_260 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_259 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_35; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_28 = cmm_stage_io_csr_addr_bits == 12'h3cc; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_36 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_28 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_261 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_260 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_36; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_29 = cmm_stage_io_csr_addr_bits == 12'h3cd; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_37 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_29 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_262 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_261 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_37; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_30 = cmm_stage_io_csr_addr_bits == 12'h3ce; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_38 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_30 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_263 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_262 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_38; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_31 = cmm_stage_io_csr_addr_bits == 12'h3cf; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_39 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_31 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_264 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_263 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_39; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_32 = cmm_stage_io_csr_addr_bits == 12'h3d0; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_40 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_32 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_265 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_264 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_40; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_33 = cmm_stage_io_csr_addr_bits == 12'h3d1; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_41 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_33 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_266 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_265 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_41; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_34 = cmm_stage_io_csr_addr_bits == 12'h3d2; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_42 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_34 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_267 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_266 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_42; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_35 = cmm_stage_io_csr_addr_bits == 12'h3d3; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_43 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_35 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_268 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_267 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_43; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_36 = cmm_stage_io_csr_addr_bits == 12'h3d4; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_44 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_36 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_269 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_268 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_44; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_37 = cmm_stage_io_csr_addr_bits == 12'h3d5; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_45 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_37 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_270 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_269 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_45; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_38 = cmm_stage_io_csr_addr_bits == 12'h3d6; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_46 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_38 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_271 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_270 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_46; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_39 = cmm_stage_io_csr_addr_bits == 12'h3d7; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_47 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_39 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_272 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_271 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_47; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_40 = cmm_stage_io_csr_addr_bits == 12'h3d8; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_48 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_40 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_273 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_272 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_48; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_41 = cmm_stage_io_csr_addr_bits == 12'h3d9; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_49 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_41 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_274 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_273 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_49; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_42 = cmm_stage_io_csr_addr_bits == 12'h3da; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_50 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_42 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_275 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_274 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_50; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_43 = cmm_stage_io_csr_addr_bits == 12'h3db; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_51 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_43 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_276 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_275 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_51; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_44 = cmm_stage_io_csr_addr_bits == 12'h3dc; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_52 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_44 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_277 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_276 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_52; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_45 = cmm_stage_io_csr_addr_bits == 12'h3dd; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_53 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_45 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_278 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_277 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_53; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_46 = cmm_stage_io_csr_addr_bits == 12'h3de; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_54 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_46 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_279 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_278 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_54; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_47 = cmm_stage_io_csr_addr_bits == 12'h3df; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_55 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_47 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_280 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_279 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_55; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_48 = cmm_stage_io_csr_addr_bits == 12'h3e0; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_56 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_48 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_281 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_280 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_56; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_49 = cmm_stage_io_csr_addr_bits == 12'h3e1; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_57 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_49 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_282 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_281 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_57; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_50 = cmm_stage_io_csr_addr_bits == 12'h3e2; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_58 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_50 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_283 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_282 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_58; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_51 = cmm_stage_io_csr_addr_bits == 12'h3e3; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_59 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_51 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_284 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_283 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_59; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_52 = cmm_stage_io_csr_addr_bits == 12'h3e4; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_60 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_52 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_285 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_284 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_60; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_53 = cmm_stage_io_csr_addr_bits == 12'h3e5; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_61 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_53 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_286 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_285 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_61; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_54 = cmm_stage_io_csr_addr_bits == 12'h3e6; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_62 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_54 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_287 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_286 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_62; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_55 = cmm_stage_io_csr_addr_bits == 12'h3e7; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_63 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_55 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_288 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_287 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_63; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_56 = cmm_stage_io_csr_addr_bits == 12'h3e8; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_64 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_56 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_289 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_288 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_64; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_57 = cmm_stage_io_csr_addr_bits == 12'h3e9; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_65 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_57 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_290 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_289 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_65; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_58 = cmm_stage_io_csr_addr_bits == 12'h3ea; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_66 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_58 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_291 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_290 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_66; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_59 = cmm_stage_io_csr_addr_bits == 12'h3eb; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_67 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_59 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_292 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_291 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_67; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_60 = cmm_stage_io_csr_addr_bits == 12'h3ec; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_68 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_60 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_293 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_292 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_68; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_61 = cmm_stage_io_csr_addr_bits == 12'h3ed; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_69 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_61 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_294 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_293 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_69; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_62 = cmm_stage_io_csr_addr_bits == 12'h3ee; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_70 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_62 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_295 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_294 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_70; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_63 = cmm_stage_io_csr_addr_bits == 12'h3ef; // @[CsrFiles.scala 320:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_71 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_63 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_296 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_295 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_71; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0_2 = cmm_stage_io_csr_addr_bits == 12'hc03; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_297 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_296 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1_2 = cmm_stage_io_csr_addr_bits == 12'hc04; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_298 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_297 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2_2 = cmm_stage_io_csr_addr_bits == 12'hc05; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_299 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_298 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3_2 = cmm_stage_io_csr_addr_bits == 12'hc06; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_300 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_299 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4_2 = cmm_stage_io_csr_addr_bits == 12'hc07; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_301 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_300 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5_2 = cmm_stage_io_csr_addr_bits == 12'hc08; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_302 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_301 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6_2 = cmm_stage_io_csr_addr_bits == 12'hc09; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_303 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_302 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7_2 = cmm_stage_io_csr_addr_bits == 12'hc0a; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_304 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_303 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7_2; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_8_1 = cmm_stage_io_csr_addr_bits == 12'hc0b; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_305 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_304 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_8_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_9_1 = cmm_stage_io_csr_addr_bits == 12'hc0c; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_306 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_305 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_9_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_10_1 = cmm_stage_io_csr_addr_bits == 12'hc0d; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_307 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_306 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_10_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_11_1 = cmm_stage_io_csr_addr_bits == 12'hc0e; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_308 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_307 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_11_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_12_1 = cmm_stage_io_csr_addr_bits == 12'hc0f; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_309 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_308 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_12_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_13_1 = cmm_stage_io_csr_addr_bits == 12'hc10; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_310 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_309 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_13_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_14_1 = cmm_stage_io_csr_addr_bits == 12'hc11; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_311 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_310 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_14_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_15_1 = cmm_stage_io_csr_addr_bits == 12'hc12; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_312 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_311 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_15_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_16_1 = cmm_stage_io_csr_addr_bits == 12'hc13; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_313 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_312 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_16_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_17_1 = cmm_stage_io_csr_addr_bits == 12'hc14; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_314 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_313 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_17_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_18_1 = cmm_stage_io_csr_addr_bits == 12'hc15; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_315 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_314 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_18_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_19_1 = cmm_stage_io_csr_addr_bits == 12'hc16; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_316 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_315 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_19_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_20_1 = cmm_stage_io_csr_addr_bits == 12'hc17; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_317 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_316 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_20_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_21_1 = cmm_stage_io_csr_addr_bits == 12'hc18; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_318 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_317 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_21_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_22_1 = cmm_stage_io_csr_addr_bits == 12'hc19; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_319 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_318 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_22_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_23_1 = cmm_stage_io_csr_addr_bits == 12'hc1a; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_320 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_319 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_23_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_24_1 = cmm_stage_io_csr_addr_bits == 12'hc1b; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_321 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_320 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_24_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_25_1 = cmm_stage_io_csr_addr_bits == 12'hc1c; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_322 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_321 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_25_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_26_1 = cmm_stage_io_csr_addr_bits == 12'hc1d; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_323 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_322 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_26_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_27_1 = cmm_stage_io_csr_addr_bits == 12'hc1e; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_324 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_323 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_27_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_28_1 = cmm_stage_io_csr_addr_bits == 12'hc1f; // @[CsrFiles.scala 326:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_325 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_324 |
    cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_28_1; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0_3 = cmm_stage_io_csr_addr_bits == 12'hb03; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_2 = cmm_stage_csrfiles_mcounteren_hpm[3]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_3 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_2; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_0_2 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_3; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_101 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_0_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_326 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_325 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_101; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1_3 = cmm_stage_io_csr_addr_bits == 12'hb04; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_6 = cmm_stage_csrfiles_mcounteren_hpm[4]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_7 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_6; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_1_2 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_7; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_102 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_1_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_327 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_326 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_102; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2_3 = cmm_stage_io_csr_addr_bits == 12'hb05; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_10 = cmm_stage_csrfiles_mcounteren_hpm[5]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_11 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_10; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_2_2 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_11; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_103 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_2_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_328 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_327 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_103; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3_3 = cmm_stage_io_csr_addr_bits == 12'hb06; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_14 = cmm_stage_csrfiles_mcounteren_hpm[6]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_15 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_14; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_3_2 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_15; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_104 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_3_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_329 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_328 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_104; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4_3 = cmm_stage_io_csr_addr_bits == 12'hb07; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_18 = cmm_stage_csrfiles_mcounteren_hpm[7]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_19 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_18; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_4_2 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_19; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_105 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_4_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_330 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_329 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_105; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5_3 = cmm_stage_io_csr_addr_bits == 12'hb08; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_22 = cmm_stage_csrfiles_mcounteren_hpm[8]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_23 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_22; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_5_2 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_23; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_106 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_5_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_331 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_330 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_106; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6_3 = cmm_stage_io_csr_addr_bits == 12'hb09; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_26 = cmm_stage_csrfiles_mcounteren_hpm[9]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_27 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_26; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_6_2 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_27; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_107 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_6_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_332 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_331 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_107; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7_3 = cmm_stage_io_csr_addr_bits == 12'hb0a; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_30 = cmm_stage_csrfiles_mcounteren_hpm[10]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_31 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_30; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_7_2 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_31; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_108 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_7_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_333 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_332 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_108; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_8_2 = cmm_stage_io_csr_addr_bits == 12'hb0b; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_34 = cmm_stage_csrfiles_mcounteren_hpm[11]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_35 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_34; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_8_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_35; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_109 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_8_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_8_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_334 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_333 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_109; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_9_2 = cmm_stage_io_csr_addr_bits == 12'hb0c; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_38 = cmm_stage_csrfiles_mcounteren_hpm[12]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_39 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_38; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_9_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_39; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_110 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_9_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_9_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_335 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_334 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_110; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_10_2 = cmm_stage_io_csr_addr_bits == 12'hb0d; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_42 = cmm_stage_csrfiles_mcounteren_hpm[13]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_43 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_42; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_10_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_43; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_111 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_10_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_10_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_336 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_335 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_111; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_11_2 = cmm_stage_io_csr_addr_bits == 12'hb0e; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_46 = cmm_stage_csrfiles_mcounteren_hpm[14]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_47 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_46; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_11_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_47; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_112 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_11_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_11_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_337 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_336 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_112; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_12_2 = cmm_stage_io_csr_addr_bits == 12'hb0f; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_50 = cmm_stage_csrfiles_mcounteren_hpm[15]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_51 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_50; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_12_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_51; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_113 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_12_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_12_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_338 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_337 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_113; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_13_2 = cmm_stage_io_csr_addr_bits == 12'hb10; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_54 = cmm_stage_csrfiles_mcounteren_hpm[16]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_55 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_54; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_13_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_55; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_114 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_13_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_13_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_339 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_338 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_114; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_14_2 = cmm_stage_io_csr_addr_bits == 12'hb11; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_58 = cmm_stage_csrfiles_mcounteren_hpm[17]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_59 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_58; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_14_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_59; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_115 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_14_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_14_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_340 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_339 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_115; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_15_2 = cmm_stage_io_csr_addr_bits == 12'hb12; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_62 = cmm_stage_csrfiles_mcounteren_hpm[18]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_63 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_62; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_15_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_63; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_116 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_15_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_15_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_341 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_340 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_116; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_16_2 = cmm_stage_io_csr_addr_bits == 12'hb13; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_66 = cmm_stage_csrfiles_mcounteren_hpm[19]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_67 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_66; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_16_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_67; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_117 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_16_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_16_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_342 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_341 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_117; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_17_2 = cmm_stage_io_csr_addr_bits == 12'hb14; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_70 = cmm_stage_csrfiles_mcounteren_hpm[20]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_71 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_70; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_17_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_71; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_118 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_17_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_17_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_343 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_342 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_118; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_18_2 = cmm_stage_io_csr_addr_bits == 12'hb15; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_74 = cmm_stage_csrfiles_mcounteren_hpm[21]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_75 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_74; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_18_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_75; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_119 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_18_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_18_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_344 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_343 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_119; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_19_2 = cmm_stage_io_csr_addr_bits == 12'hb16; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_78 = cmm_stage_csrfiles_mcounteren_hpm[22]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_79 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_78; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_19_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_79; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_120 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_19_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_19_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_345 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_344 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_120; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_20_2 = cmm_stage_io_csr_addr_bits == 12'hb17; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_82 = cmm_stage_csrfiles_mcounteren_hpm[23]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_83 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_82; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_20_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_83; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_121 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_20_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_20_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_346 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_345 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_121; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_21_2 = cmm_stage_io_csr_addr_bits == 12'hb18; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_86 = cmm_stage_csrfiles_mcounteren_hpm[24]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_87 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_86; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_21_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_87; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_122 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_21_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_21_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_347 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_346 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_122; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_22_2 = cmm_stage_io_csr_addr_bits == 12'hb19; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_90 = cmm_stage_csrfiles_mcounteren_hpm[25]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_91 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_90; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_22_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_91; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_123 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_22_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_22_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_348 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_347 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_123; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_23_2 = cmm_stage_io_csr_addr_bits == 12'hb1a; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_94 = cmm_stage_csrfiles_mcounteren_hpm[26]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_95 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_94; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_23_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_95; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_124 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_23_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_23_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_349 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_348 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_124; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_24_2 = cmm_stage_io_csr_addr_bits == 12'hb1b; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_98 = cmm_stage_csrfiles_mcounteren_hpm[27]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_99 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_98; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_24_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_99; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_125 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_24_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_24_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_350 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_349 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_125; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_25_2 = cmm_stage_io_csr_addr_bits == 12'hb1c; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_102 = cmm_stage_csrfiles_mcounteren_hpm[28]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_103 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_102; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_25_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_103; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_126 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_25_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_25_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_351 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_350 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_126; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_26_2 = cmm_stage_io_csr_addr_bits == 12'hb1d; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_106 = cmm_stage_csrfiles_mcounteren_hpm[29]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_107 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_106; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_26_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_107; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_127 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_26_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_26_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_352 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_351 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_127; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_27_2 = cmm_stage_io_csr_addr_bits == 12'hb1e; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_110 = cmm_stage_csrfiles_mcounteren_hpm[30]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_111 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_110; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_27_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_111; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_128 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_27_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_27_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_353 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_352 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_128; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_28_2 = cmm_stage_io_csr_addr_bits == 12'hb1f; // @[CsrFiles.scala 332:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_114 = cmm_stage_csrfiles_mcounteren_hpm[31]; // @[CsrFiles.scala 333:118]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_115 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_114; // @[CsrFiles.scala 333:99]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_28_1 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_reg_sel_T_115; // @[CsrFiles.scala 333:75]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_129 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_28_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_28_1; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_354 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_353 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_129; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0_4 = cmm_stage_io_csr_addr_bits == 12'h323; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_130 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_0_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_355 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_354 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_130; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1_4 = cmm_stage_io_csr_addr_bits == 12'h324; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_131 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_1_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_356 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_355 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_131; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2_4 = cmm_stage_io_csr_addr_bits == 12'h325; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_132 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_2_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_357 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_356 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_132; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3_4 = cmm_stage_io_csr_addr_bits == 12'h326; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_133 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_3_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_358 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_357 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_133; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4_4 = cmm_stage_io_csr_addr_bits == 12'h327; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_134 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_4_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_359 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_358 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_134; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5_4 = cmm_stage_io_csr_addr_bits == 12'h328; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_135 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_5_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_360 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_359 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_135; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6_4 = cmm_stage_io_csr_addr_bits == 12'h329; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_136 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_6_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_361 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_360 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_136; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7_4 = cmm_stage_io_csr_addr_bits == 12'h32a; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_137 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_7_4 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_362 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_361 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_137; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_8_3 = cmm_stage_io_csr_addr_bits == 12'h32b; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_138 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_8_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_363 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_362 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_138; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_9_3 = cmm_stage_io_csr_addr_bits == 12'h32c; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_139 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_9_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_364 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_363 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_139; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_10_3 = cmm_stage_io_csr_addr_bits == 12'h32d; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_140 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_10_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_365 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_364 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_140; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_11_3 = cmm_stage_io_csr_addr_bits == 12'h32e; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_141 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_11_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_366 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_365 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_141; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_12_3 = cmm_stage_io_csr_addr_bits == 12'h32f; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_142 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_12_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_367 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_366 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_142; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_13_3 = cmm_stage_io_csr_addr_bits == 12'h330; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_143 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_13_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_368 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_367 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_143; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_14_3 = cmm_stage_io_csr_addr_bits == 12'h331; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_144 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_14_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_369 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_368 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_144; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_15_3 = cmm_stage_io_csr_addr_bits == 12'h332; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_145 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_15_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_370 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_369 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_145; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_16_3 = cmm_stage_io_csr_addr_bits == 12'h333; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_146 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_16_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_371 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_370 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_146; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_17_3 = cmm_stage_io_csr_addr_bits == 12'h334; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_147 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_17_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_372 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_371 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_147; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_18_3 = cmm_stage_io_csr_addr_bits == 12'h335; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_148 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_18_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_373 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_372 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_148; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_19_3 = cmm_stage_io_csr_addr_bits == 12'h336; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_149 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_19_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_374 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_373 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_149; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_20_3 = cmm_stage_io_csr_addr_bits == 12'h337; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_150 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_20_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_375 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_374 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_150; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_21_3 = cmm_stage_io_csr_addr_bits == 12'h338; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_151 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_21_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_376 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_375 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_151; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_22_3 = cmm_stage_io_csr_addr_bits == 12'h339; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_152 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_22_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_377 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_376 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_152; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_23_3 = cmm_stage_io_csr_addr_bits == 12'h33a; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_153 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_23_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_378 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_377 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_153; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_24_3 = cmm_stage_io_csr_addr_bits == 12'h33b; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_154 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_24_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_379 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_378 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_154; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_25_3 = cmm_stage_io_csr_addr_bits == 12'h33c; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_155 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_25_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_380 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_379 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_155; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_26_3 = cmm_stage_io_csr_addr_bits == 12'h33d; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_156 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_26_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_381 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_380 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_156; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_27_3 = cmm_stage_io_csr_addr_bits == 12'h33e; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_157 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_27_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_382 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_381 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_157; // @[Mux.scala 27:73]
  wire  cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_28_3 = cmm_stage_io_csr_addr_bits == 12'h33f; // @[CsrFiles.scala 338:59]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_158 = cmm_stage_cmm_state_0_is_csrr_illegal_addr_chk_28_3 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_383 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_382 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_158; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T = cmm_stage_io_csr_addr_bits == 12'h1; // @[CsrFiles.scala 352:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_384 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_383 |
    cmm_stage__cmm_state_0_is_csrr_illegal_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_2 = cmm_stage_io_csr_addr_bits == 12'h2; // @[CsrFiles.scala 353:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_385 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_384 |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_2; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_4 = cmm_stage_io_csr_addr_bits == 12'h3; // @[CsrFiles.scala 354:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_386 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_385 |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_4; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_6 = cmm_stage_io_csr_addr_bits == 12'hc00; // @[CsrFiles.scala 355:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_387 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_386 |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_6; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_8 = cmm_stage_io_csr_addr_bits == 12'hc01; // @[CsrFiles.scala 356:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_388 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_387 |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_8; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_10 = cmm_stage_io_csr_addr_bits == 12'hc02; // @[CsrFiles.scala 357:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_389 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_388 |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_10; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_12 = cmm_stage_io_csr_addr_bits == 12'h100; // @[CsrFiles.scala 358:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_390 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_389 |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_12; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_14 = cmm_stage_io_csr_addr_bits == 12'h104; // @[CsrFiles.scala 361:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_15 = cmm_stage_csrfiles_priv_lvl >= 2'h1; // @[CsrFiles.scala 361:46]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_166 = cmm_stage__cmm_state_0_is_csrr_illegal_T_14 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_391 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_390 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_166; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_16 = cmm_stage_io_csr_addr_bits == 12'h105; // @[CsrFiles.scala 362:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_167 = cmm_stage__cmm_state_0_is_csrr_illegal_T_16 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_392 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_391 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_167; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_18 = cmm_stage_io_csr_addr_bits == 12'h106; // @[CsrFiles.scala 363:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_168 = cmm_stage__cmm_state_0_is_csrr_illegal_T_18 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_393 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_392 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_168; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_20 = cmm_stage_io_csr_addr_bits == 12'h140; // @[CsrFiles.scala 364:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_169 = cmm_stage__cmm_state_0_is_csrr_illegal_T_20 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_394 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_393 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_169; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_22 = cmm_stage_io_csr_addr_bits == 12'h141; // @[CsrFiles.scala 365:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_170 = cmm_stage__cmm_state_0_is_csrr_illegal_T_22 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_395 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_394 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_170; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_24 = cmm_stage_io_csr_addr_bits == 12'h142; // @[CsrFiles.scala 366:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_171 = cmm_stage__cmm_state_0_is_csrr_illegal_T_24 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_396 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_395 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_171; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_26 = cmm_stage_io_csr_addr_bits == 12'h143; // @[CsrFiles.scala 367:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_172 = cmm_stage__cmm_state_0_is_csrr_illegal_T_26 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_397 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_396 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_172; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_28 = cmm_stage_io_csr_addr_bits == 12'h144; // @[CsrFiles.scala 368:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_173 = cmm_stage__cmm_state_0_is_csrr_illegal_T_28 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_398 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_397 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_173; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_30 = cmm_stage_io_csr_addr_bits == 12'h180; // @[CsrFiles.scala 369:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_33 = ~cmm_stage_csrfiles_mstatus_tvm; // @[CsrFiles.scala 369:98]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_34 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_33; // @[CsrFiles.scala 369:84]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_35 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_34; // @[CsrFiles.scala 369:60]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_174 = cmm_stage__cmm_state_0_is_csrr_illegal_T_30 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_35; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_399 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_398 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_174; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_58 = cmm_stage_io_csr_addr_bits == 12'hf11; // @[CsrFiles.scala 392:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_197 = cmm_stage__cmm_state_0_is_csrr_illegal_T_58 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_422 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_399 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_197; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_60 = cmm_stage_io_csr_addr_bits == 12'hf12; // @[CsrFiles.scala 393:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_198 = cmm_stage__cmm_state_0_is_csrr_illegal_T_60 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_423 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_422 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_198; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_62 = cmm_stage_io_csr_addr_bits == 12'hf13; // @[CsrFiles.scala 394:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_199 = cmm_stage__cmm_state_0_is_csrr_illegal_T_62 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_424 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_423 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_199; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_64 = cmm_stage_io_csr_addr_bits == 12'hf14; // @[CsrFiles.scala 395:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_200 = cmm_stage__cmm_state_0_is_csrr_illegal_T_64 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_425 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_424 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_200; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_66 = cmm_stage_io_csr_addr_bits == 12'h300; // @[CsrFiles.scala 396:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_201 = cmm_stage__cmm_state_0_is_csrr_illegal_T_66 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_426 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_425 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_201; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_68 = cmm_stage_io_csr_addr_bits == 12'h301; // @[CsrFiles.scala 397:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_202 = cmm_stage__cmm_state_0_is_csrr_illegal_T_68 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_427 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_426 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_202; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_70 = cmm_stage_io_csr_addr_bits == 12'h302; // @[CsrFiles.scala 398:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_203 = cmm_stage__cmm_state_0_is_csrr_illegal_T_70 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_428 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_427 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_203; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_72 = cmm_stage_io_csr_addr_bits == 12'h303; // @[CsrFiles.scala 399:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_204 = cmm_stage__cmm_state_0_is_csrr_illegal_T_72 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_429 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_428 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_204; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_74 = cmm_stage_io_csr_addr_bits == 12'h304; // @[CsrFiles.scala 400:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_205 = cmm_stage__cmm_state_0_is_csrr_illegal_T_74 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_430 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_429 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_205; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_76 = cmm_stage_io_csr_addr_bits == 12'h305; // @[CsrFiles.scala 401:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_206 = cmm_stage__cmm_state_0_is_csrr_illegal_T_76 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_431 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_430 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_206; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_78 = cmm_stage_io_csr_addr_bits == 12'h306; // @[CsrFiles.scala 402:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_207 = cmm_stage__cmm_state_0_is_csrr_illegal_T_78 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_432 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_431 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_207; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_80 = cmm_stage_io_csr_addr_bits == 12'h340; // @[CsrFiles.scala 403:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_208 = cmm_stage__cmm_state_0_is_csrr_illegal_T_80 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_433 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_432 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_208; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_82 = cmm_stage_io_csr_addr_bits == 12'h341; // @[CsrFiles.scala 404:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_209 = cmm_stage__cmm_state_0_is_csrr_illegal_T_82 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_434 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_433 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_209; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_84 = cmm_stage_io_csr_addr_bits == 12'h342; // @[CsrFiles.scala 405:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_210 = cmm_stage__cmm_state_0_is_csrr_illegal_T_84 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_435 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_434 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_210; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_86 = cmm_stage_io_csr_addr_bits == 12'h343; // @[CsrFiles.scala 406:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_211 = cmm_stage__cmm_state_0_is_csrr_illegal_T_86 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_436 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_435 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_211; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_88 = cmm_stage_io_csr_addr_bits == 12'h344; // @[CsrFiles.scala 407:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_212 = cmm_stage__cmm_state_0_is_csrr_illegal_T_88 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_437 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_436 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_212; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_90 = cmm_stage_io_csr_addr_bits == 12'h34a; // @[CsrFiles.scala 408:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_213 = cmm_stage__cmm_state_0_is_csrr_illegal_T_90 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_438 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_437 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_213; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_92 = cmm_stage_io_csr_addr_bits == 12'h34b; // @[CsrFiles.scala 409:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_214 = cmm_stage__cmm_state_0_is_csrr_illegal_T_92 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_439 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_438 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_214; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_94 = cmm_stage_io_csr_addr_bits == 12'hb00; // @[CsrFiles.scala 411:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_97 = cmm_stage_csrfiles_mcounteren_hpm[0]; // @[CsrFiles.scala 137:15]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_98 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_97; // @[CsrFiles.scala 411:82]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_99 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_98; // @[CsrFiles.scala 411:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_215 = cmm_stage__cmm_state_0_is_csrr_illegal_T_94 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_99; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_440 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_439 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_215; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_100 = cmm_stage_io_csr_addr_bits == 12'hb02; // @[CsrFiles.scala 412:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_103 = cmm_stage_csrfiles_mcounteren_hpm[2]; // @[CsrFiles.scala 135:15]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_104 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_103; // @[CsrFiles.scala 412:82]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_105 = cmm_stage__is_xRet_is_mRet_T |
    cmm_stage__cmm_state_0_is_csrr_illegal_T_104; // @[CsrFiles.scala 412:58]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_216 = cmm_stage__cmm_state_0_is_csrr_illegal_T_100 &
    cmm_stage__cmm_state_0_is_csrr_illegal_T_105; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_441 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_440 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_216; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_106 = cmm_stage_io_csr_addr_bits == 12'h320; // @[CsrFiles.scala 413:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_217 = cmm_stage__cmm_state_0_is_csrr_illegal_T_106 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_442 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_441 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_217; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_108 = cmm_stage_io_csr_addr_bits == 12'h7a0; // @[CsrFiles.scala 414:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_218 = cmm_stage__cmm_state_0_is_csrr_illegal_T_108 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_443 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_442 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_218; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_110 = cmm_stage_io_csr_addr_bits == 12'h7a1; // @[CsrFiles.scala 415:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_219 = cmm_stage__cmm_state_0_is_csrr_illegal_T_110 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_444 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_443 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_219; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_112 = cmm_stage_io_csr_addr_bits == 12'h7a2; // @[CsrFiles.scala 416:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_220 = cmm_stage__cmm_state_0_is_csrr_illegal_T_112 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_445 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_444 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_220; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_114 = cmm_stage_io_csr_addr_bits == 12'h7a3; // @[CsrFiles.scala 417:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_221 = cmm_stage__cmm_state_0_is_csrr_illegal_T_114 &
    cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_446 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_445 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_221; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_116 = cmm_stage_io_csr_addr_bits == 12'h7b0; // @[CsrFiles.scala 418:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_222 = cmm_stage__cmm_state_0_is_csrr_illegal_T_116 &
    cmm_stage_csrfiles_DMode; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_447 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_446 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_222; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_117 = cmm_stage_io_csr_addr_bits == 12'h7b1; // @[CsrFiles.scala 419:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_223 = cmm_stage__cmm_state_0_is_csrr_illegal_T_117 &
    cmm_stage_csrfiles_DMode; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_448 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_447 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_223; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_118 = cmm_stage_io_csr_addr_bits == 12'h7b2; // @[CsrFiles.scala 420:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_224 = cmm_stage__cmm_state_0_is_csrr_illegal_T_118 &
    cmm_stage_csrfiles_DMode; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_449 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_448 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_224; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_119 = cmm_stage_io_csr_addr_bits == 12'h7b3; // @[CsrFiles.scala 421:18]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_225 = cmm_stage__cmm_state_0_is_csrr_illegal_T_119 &
    cmm_stage_csrfiles_DMode; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_res_T_450 = cmm_stage__cmm_state_0_is_csrr_illegal_res_T_449 |
    cmm_stage__cmm_state_0_is_csrr_illegal_res_T_225; // @[Mux.scala 27:73]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_120 = ~cmm_stage__cmm_state_0_is_csrr_illegal_res_T_450; // @[CsrFiles.scala 425:5]
  wire  cmm_stage__cmm_state_0_is_csrr_illegal_T_121 = cmm_stage__cmm_state_0_is_csrr_illegal_T_120 &
    cmm_stage_io_csr_addr_valid; // @[Commit.scala 647:101]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_T = cmm_stage__cmm_state_0_is_csrr_illegal_T_121 &
    cmm_stage_io_rod_0_bits_is_csr; // @[Commit.scala 148:25]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_T_1 = ~cmm_stage_io_cm_op_0_is_writeback; // @[Commit.scala 148:40]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_T_2 = cmm_stage__is_trap_is_exception_is_csr_illegal_T &
    cmm_stage__is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 148:38]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc |
    cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs; // @[Commit.scala 135:42]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_1 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T | cmm_stage_csrExe_mdl_io_deq_0_bits_op_rw; // @[Commit.scala 135:57]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3a0; // @[CsrFiles.scala 431:58]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3a2; // @[CsrFiles.scala 431:58]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_226 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3a4; // @[CsrFiles.scala 431:58]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_227 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_226 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3a6; // @[CsrFiles.scala 431:58]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_228 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_227 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3a8; // @[CsrFiles.scala 431:58]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_229 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_228 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3aa; // @[CsrFiles.scala 431:58]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_230 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_229 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ac; // @[CsrFiles.scala 431:58]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_231 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_230 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ae; // @[CsrFiles.scala 431:58]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_232 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_231 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b0; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_233 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_232 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b1; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_234 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_233 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b2; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_235 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_234 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b3; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_236 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_235 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b4; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_237 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_236 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b5; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_238 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_237 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b6; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_239 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_238 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b7; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_240 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_239 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b8; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_241 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_240 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3b9; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_242 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_241 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ba; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_243 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_242 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3bb; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_244 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_243 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3bc; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_245 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_244 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3bd; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_246 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_245 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3be; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_247 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_246 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3bf; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_248 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_247 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c0; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_249 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_248 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c1; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_250 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_249 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c2; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_251 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_250 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c3; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_252 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_251 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c4; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_253 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_252 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c5; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_254 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_253 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c6; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_255 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_254 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c7; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_256 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_255 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c8; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_257 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_256 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3c9; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_258 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_257 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ca; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_259 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_258 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3cb; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_260 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_259 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3cc; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_261 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_260 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_29 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3cd; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_262 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_261 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_29; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_30 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ce; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_263 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_262 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_30; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_31 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3cf; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_264 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_263 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_31; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_32 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d0; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_265 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_264 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_32; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_33 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d1; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_266 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_265 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_33; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_34 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d2; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_267 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_266 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_34; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_35 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d3; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_268 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_267 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_35; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_36 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d4; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_269 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_268 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_36; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_37 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d5; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_270 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_269 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_37; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_38 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d6; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_271 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_270 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_38; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_39 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d7; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_272 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_271 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_39; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_40 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d8; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_273 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_272 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_40; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_41 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3d9; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_274 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_273 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_41; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_42 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3da; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_275 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_274 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_42; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_43 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3db; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_276 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_275 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_43; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_44 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3dc; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_277 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_276 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_44; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_45 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3dd; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_278 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_277 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_45; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_46 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3de; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_279 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_278 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_46; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_47 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3df; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_280 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_279 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_47; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_48 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e0; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_281 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_280 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_48; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_49 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e1; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_282 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_281 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_49; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_50 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e2; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_283 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_282 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_50; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_51 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e3; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_284 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_283 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_51; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_52 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e4; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_285 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_284 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_52; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_53 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e5; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_286 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_285 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_53; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_54 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e6; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_287 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_286 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_54; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_55 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e7; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_288 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_287 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_55; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_56 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e8; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_289 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_288 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_56; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_57 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3e9; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_290 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_289 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_57; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_58 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ea; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_291 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_290 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_58; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_59 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3eb; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_292 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_291 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_59; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_60 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ec; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_293 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_292 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_60; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_61 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ed; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_294 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_293 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_61; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_62 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ee; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_295 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_294 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_62; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_63 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3ef; // @[CsrFiles.scala 437:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_296 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_295 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_63; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc03; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_297 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_296 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc04; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_298 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_297 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc05; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_299 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_298 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc06; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_300 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_299 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc07; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_301 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_300 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc08; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_302 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_301 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc09; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_303 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_302 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc0a; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_304 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_303 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc0b; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_305 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_304 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc0c; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_306 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_305 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc0d; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_307 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_306 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc0e; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_308 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_307 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc0f; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_309 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_308 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc10; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_310 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_309 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc11; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_311 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_310 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc12; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_312 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_311 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc13; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_313 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_312 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc14; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_314 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_313 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc15; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_315 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_314 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc16; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_316 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_315 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc17; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_317 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_316 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc18; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_318 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_317 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc19; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_319 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_318 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc1a; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_320 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_319 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc1b; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_321 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_320 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc1c; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_322 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_321 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc1d; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_323 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_322 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc1e; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_324 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_323 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_1 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc1f; // @[CsrFiles.scala 443:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_325 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_324 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_1; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb03; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_326 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_325 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb04; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_327 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_326 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb05; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_328 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_327 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb06; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_329 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_328 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb07; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_330 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_329 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb08; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_331 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_330 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb09; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_332 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_331 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb0a; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_333 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_332 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb0b; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_334 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_333 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb0c; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_335 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_334 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb0d; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_336 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_335 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb0e; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_337 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_336 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb0f; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_338 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_337 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb10; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_339 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_338 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb11; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_340 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_339 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb12; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_341 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_340 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb13; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_342 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_341 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb14; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_343 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_342 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb15; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_344 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_343 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb16; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_345 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_344 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb17; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_346 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_345 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb18; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_347 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_346 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb19; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_348 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_347 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb1a; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_349 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_348 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb1b; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_350 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_349 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb1c; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_351 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_350 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb1d; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_352 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_351 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb1e; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_353 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_352 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_2 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hb1f; // @[CsrFiles.scala 449:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_354 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_353 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_2; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h323; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_355 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_354 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h324; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_356 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_355 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h325; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_357 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_356 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h326; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_358 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_357 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h327; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_359 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_358 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h328; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_360 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_359 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h329; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_361 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_360 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_4 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h32a; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_362 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_361 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_4; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h32b; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_363 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_362 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h32c; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_364 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_363 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h32d; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_365 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_364 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h32e; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_366 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_365 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h32f; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_367 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_366 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h330; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_368 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_367 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h331; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_369 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_368 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h332; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_370 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_369 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h333; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_371 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_370 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h334; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_372 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_371 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h335; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_373 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_372 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h336; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_374 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_373 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h337; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_375 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_374 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h338; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_376 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_375 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h339; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_377 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_376 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h33a; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_378 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_377 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h33b; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_379 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_378 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h33c; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_380 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_379 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h33d; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_381 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_380 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h33e; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_382 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_381 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_3; // @[Mux.scala 27:73]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_3 =
    cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h33f; // @[CsrFiles.scala 455:59]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_383 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_382 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_3; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_2 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h1
    ; // @[CsrFiles.scala 469:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_384 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_383 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_3 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h2
    ; // @[CsrFiles.scala 470:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_385 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_384 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_3; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h3
    ; // @[CsrFiles.scala 471:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_386 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_385 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_4; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc00
    ; // @[CsrFiles.scala 472:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_6 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc01
    ; // @[CsrFiles.scala 473:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_7 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'hc02
    ; // @[CsrFiles.scala 474:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_8 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h100
    ; // @[CsrFiles.scala 475:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_390 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_386 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_8; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_9 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h104
    ; // @[CsrFiles.scala 478:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_391 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_390 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_9; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_10 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h105; // @[CsrFiles.scala 479:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_392 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_391 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_10; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_11 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h106; // @[CsrFiles.scala 480:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_393 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_392 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_11; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_12 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h140; // @[CsrFiles.scala 481:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_394 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_393 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_12; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_13 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h141; // @[CsrFiles.scala 482:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_395 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_394 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_13; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_14 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h142; // @[CsrFiles.scala 483:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_396 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_395 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_14; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_15 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h143; // @[CsrFiles.scala 484:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_397 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_396 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_16 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h144; // @[CsrFiles.scala 485:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_398 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_397 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_16; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_17 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h180; // @[CsrFiles.scala 486:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_399 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_398 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_17; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_40 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'hf11; // @[CsrFiles.scala 509:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_422 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_399 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_40; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_41 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'hf12; // @[CsrFiles.scala 510:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_423 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_422 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_41; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_42 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'hf13; // @[CsrFiles.scala 511:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_424 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_423 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_42; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_43 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'hf14; // @[CsrFiles.scala 512:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_425 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_424 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_43; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_44 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h300; // @[CsrFiles.scala 513:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_426 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_425 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_44; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_45 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h301; // @[CsrFiles.scala 514:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_427 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_426 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_45; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_46 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h302; // @[CsrFiles.scala 515:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_428 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_427 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_46; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_47 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h303; // @[CsrFiles.scala 516:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_429 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_428 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_47; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_48 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h304; // @[CsrFiles.scala 517:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_430 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_429 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_48; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_49 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h305; // @[CsrFiles.scala 518:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_431 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_430 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_49; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_50 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h306; // @[CsrFiles.scala 519:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_432 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_431 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_50; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_51 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h340; // @[CsrFiles.scala 520:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_433 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_432 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_51; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_52 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h341; // @[CsrFiles.scala 521:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_434 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_433 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_52; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_53 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h342; // @[CsrFiles.scala 522:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_435 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_434 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_53; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_54 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h343; // @[CsrFiles.scala 523:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_436 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_435 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_54; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_55 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h344; // @[CsrFiles.scala 524:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_437 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_436 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_55; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_56 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h34a; // @[CsrFiles.scala 525:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_438 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_437 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_56; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_57 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h34b; // @[CsrFiles.scala 526:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_439 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_438 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_57; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_58 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'hb00; // @[CsrFiles.scala 528:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_440 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_439 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_58; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_59 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'hb02; // @[CsrFiles.scala 529:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_441 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_440 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_59; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_60 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h320; // @[CsrFiles.scala 530:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_442 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_441 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_60; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_61 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h7a0; // @[CsrFiles.scala 531:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_443 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_442 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_61; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_62 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h7a1; // @[CsrFiles.scala 532:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_444 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_443 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_62; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_63 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h7a2; // @[CsrFiles.scala 533:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_445 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_444 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_63; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_64 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h7a3; // @[CsrFiles.scala 534:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_446 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_445 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_64; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_65 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h7b0; // @[CsrFiles.scala 535:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_222 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_65 & cmm_stage_csrfiles_DMode; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_447 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_446 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_222; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_66 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h7b1; // @[CsrFiles.scala 536:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_223 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_66 & cmm_stage_csrfiles_DMode; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_448 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_447 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_223; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_67 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h7b2; // @[CsrFiles.scala 537:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_224 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_67 & cmm_stage_csrfiles_DMode; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_449 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_448 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_224; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_68 = cmm_stage_csrExe_mdl_io_deq_0_bits_addr
     == 12'h7b3; // @[CsrFiles.scala 538:18]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_225 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_68 & cmm_stage_csrfiles_DMode; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_450 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_449 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_225; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_69 = ~
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_450; // @[CsrFiles.scala 542:5]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_451 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_452 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_677 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_451 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_452; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_453 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_678 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_677 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_453; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_454 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_679 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_678 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_454; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_455 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_680 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_679 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_455; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_456 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_681 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_680 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_456; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_457 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_682 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_681 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_457; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_458 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_683 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_682 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_458; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_459 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_684 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_683 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_459; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_460 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_685 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_684 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_460; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_461 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_686 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_685 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_461; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_462 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_687 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_686 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_462; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_463 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_688 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_687 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_463; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_464 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_689 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_688 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_464; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_465 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_690 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_689 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_465; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_466 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_1 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_691 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_690 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_466; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_467 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_692 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_691 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_467; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_468 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_693 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_692 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_468; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_469 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_694 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_693 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_469; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_470 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_695 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_694 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_470; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_471 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_696 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_695 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_471; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_472 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_697 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_696 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_472; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_473 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_698 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_697 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_473; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_474 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_699 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_698 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_474; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_475 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_700 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_699 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_475; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_476 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_701 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_700 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_476; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_477 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_702 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_701 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_477; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_478 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_703 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_702 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_478; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_479 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_704 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_703 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_479; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_480 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_705 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_704 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_480; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_481 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_706 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_705 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_481; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_482 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_707 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_706 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_482; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_483 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_708 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_707 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_483; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_484 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_709 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_708 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_484; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_485 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_710 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_709 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_485; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_486 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_711 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_710 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_486; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_487 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_712 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_711 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_487; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_488 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_29 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_713 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_712 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_488; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_489 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_30 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_714 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_713 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_489; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_490 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_31 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_715 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_714 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_490; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_491 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_32 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_716 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_715 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_491; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_492 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_33 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_717 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_716 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_492; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_493 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_34 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_718 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_717 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_493; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_494 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_35 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_719 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_718 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_494; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_495 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_36 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_720 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_719 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_495; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_496 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_37 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_721 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_720 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_496; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_497 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_38 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_722 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_721 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_497; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_498 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_39 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_723 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_722 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_498; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_499 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_40 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_724 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_723 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_499; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_500 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_41 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_725 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_724 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_500; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_501 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_42 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_726 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_725 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_501; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_502 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_43 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_727 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_726 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_502; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_503 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_44 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_728 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_727 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_503; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_504 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_45 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_729 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_728 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_504; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_505 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_46 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_730 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_729 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_505; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_506 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_47 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_731 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_730 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_506; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_507 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_48 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_732 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_731 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_507; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_508 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_49 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_733 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_732 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_508; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_509 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_50 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_734 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_733 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_509; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_510 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_51 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_735 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_734 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_510; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_511 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_52 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_736 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_735 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_511; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_512 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_53 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_737 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_736 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_512; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_513 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_54 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_738 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_737 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_513; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_514 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_55 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_739 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_738 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_514; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_515 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_56 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_740 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_739 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_515; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_516 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_57 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_741 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_740 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_516; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_517 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_58 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_742 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_741 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_517; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_518 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_59 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_743 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_742 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_518; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_519 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_60 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_744 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_743 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_519; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_520 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_61 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_745 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_744 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_520; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_521 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_62 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_746 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_745 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_521; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_522 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_63 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_747 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_746 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_522; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_748 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_747 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_749 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_748 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_750 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_749 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_751 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_750 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_752 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_751 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_753 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_752 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_754 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_753 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_755 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_754 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_756 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_755 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_757 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_756 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_758 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_757 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_759 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_758 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_760 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_759 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_761 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_760 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_762 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_761 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_763 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_762 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_764 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_763 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_765 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_764 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_766 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_765 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_767 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_766 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_768 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_767 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_769 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_768 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_770 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_769 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_771 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_770 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_772 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_771 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_773 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_772 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_774 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_773 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_775 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_774 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_776 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_775 |
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_552 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_0_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_777 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_776 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_552; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_553 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_1_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_778 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_777 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_553; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_554 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_2_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_779 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_778 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_554; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_555 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_3_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_780 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_779 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_555; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_556 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_4_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_781 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_780 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_556; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_557 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_5_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_782 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_781 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_557; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_558 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_6_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_783 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_782 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_558; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_559 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_3 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_7_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_784 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_783 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_559; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_560 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_8_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_785 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_784 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_560; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_561 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_9_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_786 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_785 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_561; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_562 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_10_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_787 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_786 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_562; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_563 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_11_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_788 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_787 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_563; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_564 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_12_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_789 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_788 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_564; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_565 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_13_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_790 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_789 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_565; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_566 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_14_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_791 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_790 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_566; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_567 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_15_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_792 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_791 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_567; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_568 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_16_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_793 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_792 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_568; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_569 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_17_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_794 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_793 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_569; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_570 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_18_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_795 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_794 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_570; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_571 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_19_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_796 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_795 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_571; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_572 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_20_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_797 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_796 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_572; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_573 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_21_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_798 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_797 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_573; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_574 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_22_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_799 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_798 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_574; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_575 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_23_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_800 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_799 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_575; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_576 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_24_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_801 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_800 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_576; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_577 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_25_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_802 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_801 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_577; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_578 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_26_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_803 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_802 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_578; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_579 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_27_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_804 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_803 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_579; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_580 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_2 &
    cmm_stage_cmm_state_0_is_csrr_illegal_reg_sel_28_1; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_805 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_804 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_580; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_581 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_0_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_806 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_805 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_581; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_582 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_1_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_807 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_806 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_582; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_583 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_2_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_808 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_807 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_583; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_584 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_3_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_809 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_808 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_584; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_585 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_4_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_810 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_809 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_585; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_586 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_5_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_811 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_810 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_586; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_587 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_6_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_812 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_811 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_587; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_588 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_7_4 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_813 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_812 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_588; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_589 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_8_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_814 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_813 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_589; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_590 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_9_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_815 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_814 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_590; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_591 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_10_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_816 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_815 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_591; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_592 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_11_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_817 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_816 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_592; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_593 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_12_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_818 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_817 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_593; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_594 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_13_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_819 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_818 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_594; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_595 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_14_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_820 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_819 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_595; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_596 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_15_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_821 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_820 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_596; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_597 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_16_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_822 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_821 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_597; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_598 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_17_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_823 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_822 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_598; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_599 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_18_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_824 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_823 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_599; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_600 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_19_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_825 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_824 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_600; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_601 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_20_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_826 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_825 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_601; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_602 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_21_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_827 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_826 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_602; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_603 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_22_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_828 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_827 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_603; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_604 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_23_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_829 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_828 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_604; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_605 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_24_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_830 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_829 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_605; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_606 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_25_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_831 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_830 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_606; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_607 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_26_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_832 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_831 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_607; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_608 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_27_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_833 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_832 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_608; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_609 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal_addr_chk_28_3 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_834 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_833 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_609; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_835 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_834 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_2; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_836 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_835 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_3; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_837 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_836 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_4; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_838 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_837 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_839 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_838 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_6; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_840 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_839 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_7; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_841 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_840 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_8; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_617 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_9 & cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_842 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_841 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_617; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_618 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_10 & cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_843 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_842 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_618; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_619 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_11 & cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_844 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_843 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_619; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_620 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_12 & cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_845 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_844 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_620; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_621 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_13 & cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_846 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_845 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_621; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_622 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_14 & cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_847 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_846 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_622; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_623 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_15 & cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_848 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_847 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_623; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_624 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_16 & cmm_stage__cmm_state_0_is_csrr_illegal_T_15; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_849 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_848 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_624; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_625 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_17 & cmm_stage__cmm_state_0_is_csrr_illegal_T_35; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_850 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_849 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_625; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_648 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_40 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_873 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_850 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_648; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_649 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_41 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_874 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_873 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_649; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_650 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_42 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_875 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_874 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_650; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_651 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_43 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_876 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_875 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_651; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_652 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_44 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_877 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_876 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_652; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_653 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_45 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_878 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_877 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_653; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_654 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_46 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_879 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_878 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_654; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_655 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_47 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_880 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_879 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_655; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_656 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_48 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_881 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_880 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_656; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_657 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_49 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_882 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_881 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_657; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_658 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_50 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_883 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_882 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_658; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_659 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_51 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_884 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_883 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_659; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_660 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_52 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_885 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_884 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_660; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_661 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_53 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_886 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_885 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_661; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_662 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_54 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_887 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_886 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_662; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_663 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_55 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_888 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_887 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_663; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_664 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_56 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_889 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_888 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_664; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_665 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_57 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_890 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_889 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_665; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_666 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_58 & cmm_stage__cmm_state_0_is_csrr_illegal_T_99; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_891 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_890 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_666; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_667 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_59 & cmm_stage__cmm_state_0_is_csrr_illegal_T_105; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_892 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_891 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_667; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_668 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_60 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_893 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_892 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_668; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_669 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_61 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_894 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_893 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_669; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_670 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_62 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_895 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_894 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_670; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_671 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_63 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_896 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_895 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_671; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_672 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_64 & cmm_stage__is_xRet_is_mRet_T; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_897 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_896 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_672; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_898 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_897 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_222; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_899 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_898 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_223; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_900 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_899 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_224; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_901 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_900 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_225; // @[Mux.scala 27:73]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_190 = ~
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_res_T_901; // @[CsrFiles.scala 425:5]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_191 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_69 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_190; // @[Commit.scala 135:117]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_1 &
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_191; // @[Commit.scala 135:74]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_T_3 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_csrw_illegal & cmm_stage_io_rod_0_bits_is_csr; // @[Commit.scala 149:25]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_T_4 = cmm_stage__is_trap_is_exception_is_csr_illegal_T_3 &
    cmm_stage_io_cm_op_0_is_writeback; // @[Commit.scala 149:38]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_T_5 = cmm_stage__is_trap_is_exception_is_csr_illegal_T_2 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_T_4; // @[Commit.scala 148:48]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rc |
    cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rs; // @[Commit.scala 140:44]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T_1 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T | cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rw; // @[Commit.scala 140:60]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T_2 = cmm_stage_csrfiles_mstatus_fs == 2'h0; // @[Commit.scala 140:101]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T_1 &
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T_2; // @[Commit.scala 140:78]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_T_6 =
    cmm_stage_is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal & cmm_stage_io_rod_0_bits_is_fcsr; // @[Commit.scala 150:25]
  wire  cmm_stage__is_trap_is_exception_is_csr_illegal_T_7 = cmm_stage__is_trap_is_exception_is_csr_illegal_T_6 &
    cmm_stage_io_cm_op_0_is_writeback; // @[Commit.scala 150:39]
  wire  cmm_stage_is_trap_is_exception_is_csr_illegal = cmm_stage__is_trap_is_exception_is_csr_illegal_T_5 |
    cmm_stage__is_trap_is_exception_is_csr_illegal_T_7; // @[Commit.scala 149:48]
  wire  cmm_stage__is_trap_is_exception_is_illeage_T = cmm_stage_io_rod_0_bits_is_illeage |
    cmm_stage_is_trap_is_exception_is_csr_illegal; // @[Commit.scala 160:37]
  wire  cmm_stage__is_trap_is_exception_is_ill_sfence_T = cmm_stage_io_cm_op_0_is_writeback &
    cmm_stage_io_rod_0_bits_is_sfence_vma; // @[Commit.scala 152:31]
  wire  cmm_stage__is_trap_is_exception_is_ill_sfence_T_2 = cmm_stage_csrfiles_mstatus_tvm &
    cmm_stage__is_xRet_is_sRet_T_1; // @[Commit.scala 152:77]
  wire  cmm_stage__is_trap_is_exception_is_ill_sfence_T_4 = cmm_stage__is_trap_is_exception_is_ill_sfence_T_2 |
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3; // @[Commit.scala 152:110]
  wire  cmm_stage_is_trap_is_exception_is_ill_sfence = cmm_stage__is_trap_is_exception_is_ill_sfence_T &
    cmm_stage__is_trap_is_exception_is_ill_sfence_T_4; // @[Commit.scala 152:51]
  wire  cmm_stage__is_trap_is_exception_is_illeage_T_1 = cmm_stage__is_trap_is_exception_is_illeage_T |
    cmm_stage_is_trap_is_exception_is_ill_sfence; // @[Commit.scala 160:54]
  wire  cmm_stage__is_trap_is_exception_is_ill_wfi_T = cmm_stage_io_cm_op_0_is_writeback &
    cmm_stage_io_rod_0_bits_is_wfi; // @[Commit.scala 153:29]
  wire  cmm_stage__is_trap_is_exception_is_ill_wfi_T_1 = cmm_stage_csrfiles_priv_lvl < 2'h3; // @[Commit.scala 153:94]
  wire  cmm_stage__is_trap_is_exception_is_ill_wfi_T_2 = cmm_stage_csrfiles_mstatus_tw &
    cmm_stage__is_trap_is_exception_is_ill_wfi_T_1; // @[Commit.scala 153:74]
  wire  cmm_stage_is_trap_is_exception_is_ill_wfi = cmm_stage__is_trap_is_exception_is_ill_wfi_T &
    cmm_stage__is_trap_is_exception_is_ill_wfi_T_2; // @[Commit.scala 153:49]
  wire  cmm_stage__is_trap_is_exception_is_illeage_T_2 = cmm_stage__is_trap_is_exception_is_illeage_T_1 |
    cmm_stage_is_trap_is_exception_is_ill_wfi; // @[Commit.scala 160:70]
  wire  cmm_stage__is_trap_is_exception_is_ill_mRet_T = cmm_stage_csrfiles_priv_lvl != 2'h3; // @[Commit.scala 155:59]
  wire  cmm_stage_is_trap_is_exception_is_ill_mRet = cmm_stage_io_rod_0_bits_privil_mret &
    cmm_stage__is_trap_is_exception_is_ill_mRet_T; // @[Commit.scala 155:39]
  wire  cmm_stage__is_trap_is_exception_is_illeage_T_3 = cmm_stage__is_trap_is_exception_is_illeage_T_2 |
    cmm_stage_is_trap_is_exception_is_ill_mRet; // @[Commit.scala 160:83]
  wire  cmm_stage__is_trap_is_exception_is_ill_sRet_T_2 = cmm_stage__is_xRet_is_sRet_T_1 &
    cmm_stage_csrfiles_mstatus_tsr; // @[Commit.scala 156:107]
  wire  cmm_stage__is_trap_is_exception_is_ill_sRet_T_3 =
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3 |
    cmm_stage__is_trap_is_exception_is_ill_sRet_T_2; // @[Commit.scala 156:73]
  wire  cmm_stage_is_trap_is_exception_is_ill_sRet = cmm_stage_io_rod_0_bits_privil_sret &
    cmm_stage__is_trap_is_exception_is_ill_sRet_T_3; // @[Commit.scala 156:39]
  wire  cmm_stage__is_trap_is_exception_is_illeage_T_4 = cmm_stage__is_trap_is_exception_is_illeage_T_3 |
    cmm_stage_is_trap_is_exception_is_ill_sRet; // @[Commit.scala 160:97]
  wire  cmm_stage_is_trap_is_exception_is_ill_dRet = cmm_stage_io_rod_0_bits_privil_dret &
    cmm_stage__is_trap_is_interrupt_T_2; // @[Commit.scala 157:39]
  wire  cmm_stage__is_trap_is_exception_is_illeage_T_5 = cmm_stage__is_trap_is_exception_is_illeage_T_4 |
    cmm_stage_is_trap_is_exception_is_ill_dRet; // @[Commit.scala 160:111]
  wire  cmm_stage__is_trap_is_exception_is_ill_fpus_T = cmm_stage_io_cm_op_0_is_writeback &
    cmm_stage_io_rod_0_bits_is_fpu; // @[Commit.scala 158:30]
  wire  cmm_stage_is_trap_is_exception_is_ill_fpus = cmm_stage__is_trap_is_exception_is_ill_fpus_T &
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_fcsrw_illegal_T_2; // @[Commit.scala 158:45]
  wire  cmm_stage_is_trap_is_exception_is_illeage = cmm_stage__is_trap_is_exception_is_illeage_T_5 |
    cmm_stage_is_trap_is_exception_is_ill_fpus; // @[Commit.scala 160:125]
  wire  cmm_stage__is_trap_is_exception_T_4 = cmm_stage__is_trap_is_exception_T_2 |
    cmm_stage_is_trap_is_exception_is_illeage; // @[Commit.scala 195:32]
  wire  cmm_stage__is_trap_is_exception_is_load_accessFault_T = cmm_stage_io_lsu_cmm_is_access_fault &
    cmm_stage_io_rod_0_bits_is_lu; // @[Commit.scala 66:55]
  wire  cmm_stage_is_trap_is_exception_is_load_accessFault = cmm_stage__is_trap_is_exception_is_load_accessFault_T &
    cmm_stage__is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 66:67]
  wire  cmm_stage__is_trap_is_exception_T_5 = cmm_stage__is_trap_is_exception_T_4 |
    cmm_stage_is_trap_is_exception_is_load_accessFault; // @[Commit.scala 196:32]
  wire  cmm_stage__is_trap_is_exception_is_store_accessFault_T = cmm_stage_io_rod_0_bits_is_su |
    cmm_stage_io_rod_0_bits_is_amo; // @[Commit.scala 71:70]
  wire  cmm_stage__is_trap_is_exception_is_store_accessFault_T_1 = cmm_stage_io_lsu_cmm_is_access_fault &
    cmm_stage__is_trap_is_exception_is_store_accessFault_T; // @[Commit.scala 71:56]
  wire  cmm_stage_is_trap_is_exception_is_store_accessFault = cmm_stage__is_trap_is_exception_is_store_accessFault_T_1
     & cmm_stage__is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 71:85]
  wire  cmm_stage__is_trap_is_exception_T_6 = cmm_stage__is_trap_is_exception_T_5 |
    cmm_stage_is_trap_is_exception_is_store_accessFault; // @[Commit.scala 197:32]
  wire  cmm_stage__is_trap_is_exception_is_load_misAlign_T = cmm_stage_io_lsu_cmm_is_misAlign &
    cmm_stage_io_rod_0_bits_is_lu; // @[Commit.scala 86:48]
  wire  cmm_stage_is_trap_is_exception_is_load_misAlign = cmm_stage__is_trap_is_exception_is_load_misAlign_T &
    cmm_stage__is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 86:60]
  wire  cmm_stage__is_trap_is_exception_T_7 = cmm_stage__is_trap_is_exception_T_6 |
    cmm_stage_is_trap_is_exception_is_load_misAlign; // @[Commit.scala 198:32]
  wire  cmm_stage__is_trap_is_exception_is_store_misAlign_T_1 = cmm_stage_io_lsu_cmm_is_misAlign &
    cmm_stage__is_trap_is_exception_is_store_accessFault_T; // @[Commit.scala 95:49]
  wire  cmm_stage_is_trap_is_exception_is_store_misAlign = cmm_stage__is_trap_is_exception_is_store_misAlign_T_1 &
    cmm_stage__is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 95:76]
  wire  cmm_stage__is_trap_is_exception_T_8 = cmm_stage__is_trap_is_exception_T_7 |
    cmm_stage_is_trap_is_exception_is_store_misAlign; // @[Commit.scala 199:32]
  wire  cmm_stage__is_trap_is_exception_is_load_pagingFault_T = cmm_stage_io_lsu_cmm_is_paging_fault &
    cmm_stage_io_rod_0_bits_is_lu; // @[Commit.scala 76:55]
  wire  cmm_stage_is_trap_is_exception_is_load_pagingFault = cmm_stage__is_trap_is_exception_is_load_pagingFault_T &
    cmm_stage__is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 76:67]
  wire  cmm_stage__is_trap_is_exception_T_9 = cmm_stage__is_trap_is_exception_T_8 |
    cmm_stage_is_trap_is_exception_is_load_pagingFault; // @[Commit.scala 200:32]
  wire  cmm_stage__is_trap_is_exception_is_store_pagingFault_T_1 = cmm_stage_io_lsu_cmm_is_paging_fault &
    cmm_stage__is_trap_is_exception_is_store_accessFault_T; // @[Commit.scala 81:56]
  wire  cmm_stage_is_trap_is_exception_is_store_pagingFault = cmm_stage__is_trap_is_exception_is_store_pagingFault_T_1
     & cmm_stage__is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 81:85]
  wire  cmm_stage_is_trap_is_exception = cmm_stage__is_trap_is_exception_T_9 |
    cmm_stage_is_trap_is_exception_is_store_pagingFault; // @[Commit.scala 201:32]
  wire  cmm_stage_is_trap = cmm_stage_is_trap_is_interrupt | cmm_stage_is_trap_is_exception; // @[Commit.scala 212:32]
  wire  cmm_stage__T_7 = cmm_stage_is_xRet | cmm_stage_is_trap; // @[Commit.scala 426:32]
  wire  cmm_stage_is_fence_i = cmm_stage_io_rod_0_bits_is_fence_i & cmm_stage_io_cm_op_0_is_writeback; // @[Commit.scala 180:37]
  wire  cmm_stage__T_8 = cmm_stage__T_7 | cmm_stage_is_fence_i; // @[Commit.scala 426:55]
  wire  cmm_stage__is_sfence_vma_T = cmm_stage_io_rod_0_bits_is_sfence_vma & cmm_stage_io_cm_op_0_is_writeback; // @[Commit.scala 185:43]
  wire  cmm_stage__is_sfence_vma_T_4 = cmm_stage__cmm_state_0_is_csrr_illegal_T_33 & cmm_stage__is_xRet_is_sRet_T_1; // @[Commit.scala 185:85]
  wire  cmm_stage__is_sfence_vma_T_6 = cmm_stage__is_sfence_vma_T_4 | cmm_stage__is_xRet_is_mRet_T; // @[Commit.scala 185:118]
  wire  cmm_stage_is_sfence_vma = cmm_stage__is_sfence_vma_T & cmm_stage__is_sfence_vma_T_6; // @[Commit.scala 185:51]
  wire  cmm_stage__T_9 = cmm_stage__T_8 | cmm_stage_is_sfence_vma; // @[Commit.scala 426:81]
  wire  cmm_stage__T_10 = cmm_stage_bctq_mdl_io_deq_0_bits_isPredictTaken !=
    cmm_stage_bctq_mdl_io_deq_0_bits_isFinalTaken; // @[frontend.scala 245:37]
  wire  cmm_stage__T_11 = cmm_stage_io_rod_0_bits_is_branch & cmm_stage__T_10; // @[Commit.scala 431:47]
  wire  cmm_stage__T_12 = cmm_stage__T_11 & cmm_stage_bctq_mdl_io_deq_0_valid; // @[Commit.scala 431:75]
  wire [63:0] _GEN_470 = {{25'd0}, cmm_stage_jctq_mdl_io_deq_0_bits_rasResp_target}; // @[frontend.scala 250:48]
  wire  cmm_stage__T_13 = _GEN_470 != cmm_stage_jctq_mdl_io_deq_0_bits_finalTarget; // @[frontend.scala 250:48]
  wire [63:0] _GEN_471 = {{25'd0}, cmm_stage_jctq_mdl_io_deq_0_bits_btbResp_target}; // @[frontend.scala 250:80]
  wire  cmm_stage__T_14 = _GEN_471 != cmm_stage_jctq_mdl_io_deq_0_bits_finalTarget; // @[frontend.scala 250:80]
  wire  cmm_stage__T_15 = cmm_stage_jctq_mdl_io_deq_0_bits_isRas ? cmm_stage__T_13 : cmm_stage__T_14; // @[frontend.scala 250:25]
  wire  cmm_stage__T_16 = cmm_stage_io_rod_0_bits_is_jalr & cmm_stage__T_15; // @[Commit.scala 431:121]
  wire  cmm_stage__T_17 = cmm_stage__T_16 & cmm_stage_jctq_mdl_io_deq_0_valid; // @[Commit.scala 431:149]
  wire  cmm_stage__T_18 = cmm_stage__T_12 | cmm_stage__T_17; // @[Commit.scala 431:93]
  wire  cmm_stage__T_19 = cmm_stage__T_18 & cmm_stage_io_cm_op_0_is_writeback; // @[Commit.scala 431:167]
  wire  cmm_stage_is_step_1 = cmm_stage_csrfiles_dcsr_step & cmm_stage__is_trap_is_interrupt_T_2; // @[Commit.scala 243:38]
  wire  cmm_stage__T_21 = ~cmm_stage_is_step_1; // @[Commit.scala 431:190]
  wire  cmm_stage__T_22 = cmm_stage__T_19 & cmm_stage__T_21; // @[Commit.scala 431:188]
  wire  cmm_stage__T_23 = ~cmm_stage_csrExe_mdl_io_deq_0_valid; // @[Commit.scala 435:40]
  wire  cmm_stage__T_24 = cmm_stage_io_rod_0_bits_is_csr & cmm_stage__T_23; // @[Commit.scala 435:38]
  wire  cmm_stage__T_25 = ~cmm_stage_fcsrExe_mdl_io_deq_0_valid; // @[Commit.scala 435:87]
  wire  cmm_stage__T_26 = cmm_stage_io_rod_0_bits_is_fcsr & cmm_stage__T_25; // @[Commit.scala 435:85]
  wire  cmm_stage__T_27 = cmm_stage__T_24 | cmm_stage__T_26; // @[Commit.scala 435:58]
  wire  cmm_stage__T_28 = ~cmm_stage_bctq_mdl_io_deq_0_valid; // @[Commit.scala 435:137]
  wire  cmm_stage__T_29 = cmm_stage_io_rod_0_bits_is_branch & cmm_stage__T_28; // @[Commit.scala 435:135]
  wire  cmm_stage__T_30 = cmm_stage__T_27 | cmm_stage__T_29; // @[Commit.scala 435:106]
  wire  cmm_stage__T_31 = ~cmm_stage_jctq_mdl_io_deq_0_valid; // @[Commit.scala 435:182]
  wire  cmm_stage__T_32 = cmm_stage_io_rod_0_bits_is_jalr & cmm_stage__T_31; // @[Commit.scala 435:180]
  wire  cmm_stage__T_33 = cmm_stage__T_30 | cmm_stage__T_32; // @[Commit.scala 435:153]
  wire [1:0] cmm_stage__GEN_462 = cmm_stage__T_33 ? 2'h0 : 2'h3; // @[Commit.scala 435:200 436:27 438:27]
  wire [1:0] cmm_stage__GEN_463 = cmm_stage_io_cm_op_0_is_writeback ? cmm_stage__GEN_462 : 2'h0; // @[Commit.scala 434:41 442:25]
  wire [1:0] cmm_stage__GEN_464 = cmm_stage__T_22 ? 2'h2 : cmm_stage__GEN_463; // @[Commit.scala 431:213 432:27]
  wire [1:0] cmm_stage__GEN_465 = cmm_stage__T_9 ? 2'h1 : cmm_stage__GEN_464; // @[Commit.scala 427:11 428:25]
  wire [1:0] cmm_stage__GEN_467 = cmm_stage__T_6 ? 2'h0 : cmm_stage__GEN_465; // @[Commit.scala 419:33 420:23]
  wire  cmm_stage_commit_state_is_comfirm_0 = cmm_stage__GEN_467 == 2'h3; // @[Commit.scala 324:87]
  wire  cmm_stage_commit_state_is_misPredict_0 = cmm_stage__GEN_467 == 2'h2; // @[Commit.scala 325:87]
  wire  cmm_stage_commit_state_is_abort_0 = cmm_stage__GEN_467 == 2'h1; // @[Commit.scala 326:87]
  wire  cmm_stage_is_retired_0 = cmm_stage_commit_state_is_comfirm_0 | cmm_stage_commit_state_is_misPredict_0; // @[Commit.scala 333:77]
  wire  cmm_stage__GEN_0 = cmm_stage_emu_reset ? 1'h0 : cmm_stage_emu_reset; // @[Commit.scala 363:26 365:{26,38}]
  wire  cmm_stage__GEN_1 = cmm_stage_io_dm_hartResetReq | cmm_stage__GEN_0; // @[Commit.scala 364:{30,42}]
  wire [63:0] cmm_stage__csrfiles_mcycle_T_1 = cmm_stage_csrfiles_mcycle + 64'h1; // @[Commit.scala 395:38]
  reg  cmm_stage_rtc_0; // @[Reg.scala 35:20]
  reg  cmm_stage_rtc_1; // @[Reg.scala 35:20]
  reg  cmm_stage_rtc_2; // @[Reg.scala 35:20]
  reg  cmm_stage_rtc_3; // @[Reg.scala 35:20]
  wire  cmm_stage__T = cmm_stage_rtc_3 ^ cmm_stage_rtc_2; // @[Commit.scala 396:77]
  wire [63:0] cmm_stage__csrfiles_time_T_1 = cmm_stage_csrfiles_time + 64'h1; // @[Commit.scala 396:120]
  wire  cmm_stage__T_1 = cmm_stage_is_retired_0 | cmm_stage_commit_state_is_abort_0; // @[Commit.scala 398:59]
  wire [1:0] cmm_stage__GEN_469 = cmm_stage_emu_reset ? 2'h3 : cmm_stage_csrfiles_priv_lvl; // @[CsrFiles.scala 707:{30,41}]
  wire [1:0] cmm_stage__GEN_470 = cmm_stage_is_xRet_is_dRet ? cmm_stage_csrfiles_dcsr_prv : cmm_stage__GEN_469; // @[CsrFiles.scala 710:{24,35}]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_72 = cmm_stage_csrfiles_medeleg[15]; // @[CsrFiles.scala 736:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_73 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_72
    ; // @[CsrFiles.scala 736:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_74 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_73 ? 2'h3 : 2'h1; // @[CsrFiles.scala 736:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_75 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_74; // @[CsrFiles.scala 736:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_67 = cmm_stage_csrfiles_medeleg[13]; // @[CsrFiles.scala 735:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_68 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_67
    ; // @[CsrFiles.scala 735:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_69 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_68 ? 2'h3 : 2'h1; // @[CsrFiles.scala 735:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_70 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_69; // @[CsrFiles.scala 735:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_62 = cmm_stage_csrfiles_medeleg[12]; // @[CsrFiles.scala 734:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_63 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_62
    ; // @[CsrFiles.scala 734:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_64 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_63 ? 2'h3 : 2'h1; // @[CsrFiles.scala 734:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_65 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_64; // @[CsrFiles.scala 734:58]
  wire  cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_M = cmm_stage_io_rod_0_bits_privil_ecall &
    cmm_stage__is_xRet_is_mRet_T; // @[Commit.scala 115:31]
  wire  cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_S = cmm_stage_io_rod_0_bits_privil_ecall &
    cmm_stage__is_xRet_is_sRet_T_1; // @[Commit.scala 110:31]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_58 = cmm_stage_csrfiles_medeleg[9]; // @[CsrFiles.scala 732:79]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_59 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_58
    ; // @[CsrFiles.scala 732:59]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_60 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_59 ? 2'h3 : 2'h1; // @[CsrFiles.scala 732:58]
  wire  cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_U = cmm_stage_io_rod_0_bits_privil_ecall &
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3; // @[Commit.scala 105:31]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_55 = cmm_stage_csrfiles_medeleg[8]; // @[CsrFiles.scala 731:79]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_56 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_55
    ; // @[CsrFiles.scala 731:59]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_57 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_56 ? 2'h3 : 2'h1; // @[CsrFiles.scala 731:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_51 = cmm_stage_csrfiles_medeleg[7]; // @[CsrFiles.scala 730:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_52 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_51
    ; // @[CsrFiles.scala 730:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_53 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_52 ? 2'h3 : 2'h1; // @[CsrFiles.scala 730:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_54 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_53; // @[CsrFiles.scala 730:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_46 = cmm_stage_csrfiles_medeleg[6]; // @[CsrFiles.scala 729:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_47 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_46
    ; // @[CsrFiles.scala 729:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_48 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_47 ? 2'h3 : 2'h1; // @[CsrFiles.scala 729:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_49 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_48; // @[CsrFiles.scala 729:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_41 = cmm_stage_csrfiles_medeleg[5]; // @[CsrFiles.scala 728:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_42 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_41
    ; // @[CsrFiles.scala 728:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_43 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_42 ? 2'h3 : 2'h1; // @[CsrFiles.scala 728:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_44 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_43; // @[CsrFiles.scala 728:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_36 = cmm_stage_csrfiles_medeleg[4]; // @[CsrFiles.scala 727:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_37 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_36
    ; // @[CsrFiles.scala 727:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_38 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_37 ? 2'h3 : 2'h1; // @[CsrFiles.scala 727:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_39 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_38; // @[CsrFiles.scala 727:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_31 = cmm_stage_csrfiles_medeleg[3]; // @[CsrFiles.scala 726:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_32 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_31
    ; // @[CsrFiles.scala 726:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_33 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_32 ? 2'h3 : 2'h1; // @[CsrFiles.scala 726:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_34 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_33; // @[CsrFiles.scala 726:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_26 = cmm_stage_csrfiles_medeleg[2]; // @[CsrFiles.scala 725:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_27 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_26
    ; // @[CsrFiles.scala 725:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_28 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_27 ? 2'h3 : 2'h1; // @[CsrFiles.scala 725:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_29 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_28; // @[CsrFiles.scala 725:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_21 = cmm_stage_csrfiles_medeleg[1]; // @[CsrFiles.scala 724:127]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_22 = ~cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_21
    ; // @[CsrFiles.scala 724:107]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_23 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_22 ? 2'h3 : 2'h1; // @[CsrFiles.scala 724:106]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_24 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_23; // @[CsrFiles.scala 724:58]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_12 = ~
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sei_T_3; // @[CsrFiles.scala 719:99]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_13 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_12 ? 2'h3 : 2'h1; // @[CsrFiles.scala 719:97]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_14 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_13; // @[CsrFiles.scala 719:49]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_7 = ~
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_sti_T_3; // @[CsrFiles.scala 717:99]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_8 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_7 ? 2'h3 : 2'h1; // @[CsrFiles.scala 717:97]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_9 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_8; // @[CsrFiles.scala 717:49]
  wire  cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_2 = ~
    cmm_stage__is_trap_is_interrupt_is_s_interrupt_is_ssi_T_3; // @[CsrFiles.scala 715:99]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_3 =
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_2 ? 2'h3 : 2'h1; // @[CsrFiles.scala 715:97]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_4 = cmm_stage__is_xRet_is_mRet_T ? 2'h3 :
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_3; // @[CsrFiles.scala 715:49]
  wire [1:0] cmm_stage__GEN_471 = cmm_stage_is_xRet_is_mRet ? cmm_stage_csrfiles_mstatus_mpp : cmm_stage__GEN_469; // @[CsrFiles.scala 712:{24,35}]
  wire [1:0] cmm_stage__GEN_472 = cmm_stage_is_xRet_is_sRet ? {{1'd0}, cmm_stage_csrfiles_mstatus_spp} :
    cmm_stage__GEN_471; // @[CsrFiles.scala 713:{24,35}]
  wire [1:0] cmm_stage__GEN_473 = cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_ssi ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_4 : cmm_stage__GEN_472; // @[CsrFiles.scala 715:{32,43}]
  wire [1:0] cmm_stage__GEN_474 = cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_msi ? 2'h3 : cmm_stage__GEN_473; // @[CsrFiles.scala 716:{32,43}]
  wire [1:0] cmm_stage__GEN_475 = cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_sti ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_9 : cmm_stage__GEN_474; // @[CsrFiles.scala 717:{32,43}]
  wire [1:0] cmm_stage__GEN_476 = cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_mti ? 2'h3 : cmm_stage__GEN_475; // @[CsrFiles.scala 718:{32,43}]
  wire [1:0] cmm_stage__GEN_477 = cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_sei ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_14 : cmm_stage__GEN_476; // @[CsrFiles.scala 719:{32,43}]
  wire [1:0] cmm_stage__GEN_478 = cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_mei ? 2'h3 : cmm_stage__GEN_477; // @[CsrFiles.scala 720:{32,43}]
  wire [1:0] cmm_stage__GEN_480 = cmm_stage_io_rod_0_bits_privil_is_access_fault ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_24 : cmm_stage__GEN_478; // @[CsrFiles.scala 724:{41,52}]
  wire [1:0] cmm_stage__GEN_481 = cmm_stage_is_trap_is_exception_is_illeage ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_29 : cmm_stage__GEN_480; // @[CsrFiles.scala 725:{41,52}]
  wire [1:0] cmm_stage__GEN_482 = cmm_stage_is_trap_is_exception_is_ebreak_exc ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_34 : cmm_stage__GEN_481; // @[CsrFiles.scala 726:{41,52}]
  wire [1:0] cmm_stage__GEN_483 = cmm_stage_is_trap_is_exception_is_load_misAlign ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_39 : cmm_stage__GEN_482; // @[CsrFiles.scala 727:{41,52}]
  wire [1:0] cmm_stage__GEN_484 = cmm_stage_is_trap_is_exception_is_load_accessFault ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_44 : cmm_stage__GEN_483; // @[CsrFiles.scala 728:{41,52}]
  wire [1:0] cmm_stage__GEN_485 = cmm_stage_is_trap_is_exception_is_store_misAlign ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_49 : cmm_stage__GEN_484; // @[CsrFiles.scala 729:{41,52}]
  wire [1:0] cmm_stage__GEN_486 = cmm_stage_is_trap_is_exception_is_store_accessFault ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_54 : cmm_stage__GEN_485; // @[CsrFiles.scala 730:{41,52}]
  wire [1:0] cmm_stage__GEN_487 = cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_U ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_57 : cmm_stage__GEN_486; // @[CsrFiles.scala 731:{41,52}]
  wire [1:0] cmm_stage__GEN_488 = cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_S ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_60 : cmm_stage__GEN_487; // @[CsrFiles.scala 732:{41,52}]
  wire [1:0] cmm_stage__GEN_489 = cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_M ? 2'h3 : cmm_stage__GEN_488; // @[CsrFiles.scala 733:{41,52}]
  wire [1:0] cmm_stage__GEN_490 = cmm_stage_io_rod_0_bits_privil_is_paging_fault ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_65 : cmm_stage__GEN_489; // @[CsrFiles.scala 734:{41,52}]
  wire [1:0] cmm_stage__GEN_491 = cmm_stage_is_trap_is_exception_is_load_pagingFault ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_70 : cmm_stage__GEN_490; // @[CsrFiles.scala 735:{41,52}]
  wire [1:0] cmm_stage__GEN_492 = cmm_stage_is_trap_is_exception_is_store_pagingFault ?
    cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_75 : cmm_stage__GEN_491; // @[CsrFiles.scala 736:{41,52}]
  wire [1:0] cmm_stage__GEN_493 = cmm_stage_csrfiles_DMode ? cmm_stage__GEN_470 : cmm_stage__GEN_492; // @[CsrFiles.scala 709:31]
  wire  cmm_stage__GEN_494 = cmm_stage_is_xRet_is_dRet ? 1'h0 : cmm_stage_csrfiles_DMode; // @[CsrFiles.scala 1872:{31,39}]
  wire  cmm_stage__GEN_495 = cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt | cmm_stage__GEN_494; // @[CsrFiles.scala 1871:{37,45}]
  wire  cmm_stage__csr_state_0_csrfiles_fcsr_enable_T = cmm_stage_fcsrExe_mdl_io_deq_0_bits_addr == 12'h1; // @[CsrFiles.scala 42:27]
  wire  cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_1 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rw |
    cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rs; // @[CsrFiles.scala 42:49]
  wire  cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_2 = cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_1 |
    cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rc; // @[CsrFiles.scala 42:60]
  wire  cmm_stage_csr_state_0_csrfiles_fcsr_enable0 = cmm_stage__csr_state_0_csrfiles_fcsr_enable_T &
    cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_2; // @[CsrFiles.scala 42:37]
  wire  cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_3 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_addr == 12'h2; // @[CsrFiles.scala 42:27]
  wire  cmm_stage_csr_state_0_csrfiles_fcsr_enable1 = cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_3 &
    cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_11 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rw ?
    cmm_stage_fcsrExe_mdl_io_deq_0_bits_dat_i : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _GEN_472 = {{61'd0}, cmm_stage_csrfiles_fcsr_frm}; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_8 = _GEN_472 | cmm_stage_fcsrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_12 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_8 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_14 = cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_11 |
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_12; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_9 = ~cmm_stage_fcsrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 46:32]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_10 = _GEN_472 & cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_9; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_13 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_10 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_15 = cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_14 |
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_13; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_6 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_addr == 12'h3; // @[CsrFiles.scala 42:27]
  wire  cmm_stage_csr_state_0_csrfiles_fcsr_enable2 = cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_6 &
    cmm_stage__csr_state_0_csrfiles_fcsr_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [7:0] cmm_stage__csr_state_0_csrfiles_fcsr_T = {cmm_stage_csrfiles_fcsr_frm,cmm_stage_csrfiles_fcsr_fflags}; // @[CsrFiles.scala 675:59]
  wire [63:0] _GEN_474 = {{56'd0}, cmm_stage__csr_state_0_csrfiles_fcsr_T}; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_16 = _GEN_474 | cmm_stage_fcsrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_20 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_16 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_22 = cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_11 |
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_20; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_18 = _GEN_474 & cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_9; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_21 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_18 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_23 = cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_22 |
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_21; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_fcsr_fcsr_frm_T = cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_23[7:5]; // @[CsrFiles.scala 680:70]
  wire [2:0] cmm_stage__GEN_497 = cmm_stage_csr_state_0_csrfiles_fcsr_enable2 ?
    cmm_stage__csr_state_0_csrfiles_fcsr_fcsr_frm_T : cmm_stage_csrfiles_fcsr_frm; // @[CsrFiles.scala 680:{24,62}]
  wire [63:0] cmm_stage__GEN_498 = cmm_stage_csr_state_0_csrfiles_fcsr_enable1 ?
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_15 : {{61'd0}, cmm_stage__GEN_497}; // @[CsrFiles.scala 679:{24,35}]
  wire [63:0] cmm_stage__GEN_501 = cmm_stage_csr_state_0_csrfiles_fcsr_enable0 ? {{61'd0}, cmm_stage_csrfiles_fcsr_frm}
     : cmm_stage__GEN_498; // @[CsrFiles.scala 678:19]
  wire [2:0] cmm_stage_csr_state_0_csrfiles_fcsr_fcsr_frm = cmm_stage__GEN_501[2:0];
  wire [63:0] _GEN_476 = {{59'd0}, cmm_stage_csrfiles_fcsr_fflags}; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T = _GEN_476 | cmm_stage_fcsrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_4 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_11 |
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_2 = _GEN_476 & cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_9; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_5 = cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_5; // @[Mux.scala 27:73]
  wire [4:0] cmm_stage__csr_state_0_csrfiles_fcsr_fcsr_fflags_T = cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_23[4:0]; // @[CsrFiles.scala 680:46]
  wire [4:0] cmm_stage__GEN_496 = cmm_stage_csr_state_0_csrfiles_fcsr_enable2 ?
    cmm_stage__csr_state_0_csrfiles_fcsr_fcsr_fflags_T : cmm_stage_csrfiles_fcsr_fflags; // @[CsrFiles.scala 680:{24,38}]
  wire [4:0] cmm_stage__GEN_499 = cmm_stage_csr_state_0_csrfiles_fcsr_enable1 ? cmm_stage_csrfiles_fcsr_fflags :
    cmm_stage__GEN_496; // @[CsrFiles.scala 679:24]
  wire [63:0] cmm_stage__GEN_500 = cmm_stage_csr_state_0_csrfiles_fcsr_enable0 ?
    cmm_stage__csr_state_0_csrfiles_fcsr_dnxt_T_7 : {{59'd0}, cmm_stage__GEN_499}; // @[CsrFiles.scala 678:{19,33}]
  wire [4:0] cmm_stage_csr_state_0_csrfiles_fcsr_fcsr_fflags = cmm_stage__GEN_500[4:0];
  wire  cmm_stage__csr_state_0_csrfiles_stvec_enable_T_1 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rw |
    cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs; // @[CsrFiles.scala 42:49]
  wire  cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2 = cmm_stage__csr_state_0_csrfiles_stvec_enable_T_1 |
    cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc; // @[CsrFiles.scala 42:60]
  wire  cmm_stage_csr_state_0_csrfiles_stvec_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_10 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rw ?
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_T = {cmm_stage_csrfiles_stvec_base,2'h0}; // @[CsrFiles.scala 1321:58]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T = cmm_stage__csr_state_0_csrfiles_stvec_T |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1 = ~cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 46:32]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_2 = cmm_stage__csr_state_0_csrfiles_stvec_T &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_5; // @[Mux.scala 27:73]
  wire [61:0] cmm_stage__csr_state_0_csrfiles_stvec_stvec_base_T = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_7[63:2]; // @[CsrFiles.scala 1322:38]
  wire  cmm_stage_csr_state_0_csrfiles_scounteren_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_50 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] _GEN_478 = {{32'd0}, cmm_stage_csrfiles_scounteren_hpm}; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T = _GEN_478 | cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_2 = _GEN_478 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_6
     | cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_5; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__GEN_503 = cmm_stage_csr_state_0_csrfiles_scounteren_enable ?
    cmm_stage__csr_state_0_csrfiles_scounteren_dnxt_T_7 : {{32'd0}, cmm_stage_csrfiles_scounteren_hpm}; // @[CsrFiles.scala 1342:{20,37}]
  wire [31:0] cmm_stage_csr_state_0_csrfiles_scounteren_scounteren_hpm = cmm_stage__GEN_503[31:0];
  wire  cmm_stage_csr_state_0_csrfiles_sscratch_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_12 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T = cmm_stage_csrfiles_sscratch |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_2 = cmm_stage_csrfiles_sscratch &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_sepc_T_7 = cmm_stage__GEN_493 == 2'h1; // @[CsrFiles.scala 1373:44]
  wire  cmm_stage__csr_state_0_csrfiles_sepc_T_8 = cmm_stage_is_trap & cmm_stage__csr_state_0_csrfiles_sepc_T_7; // @[CsrFiles.scala 1373:22]
  wire  cmm_stage__csr_state_0_csrfiles_sepc_T_10 = cmm_stage__csr_state_0_csrfiles_sepc_T_8 &
    cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 1373:56]
  wire  cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T = cmm_stage_io_rod_0_bits_pc[38]; // @[Util.scala 47:31]
  wire [24:0] cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_2 =
    cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T ? 25'h1ffffff : 25'h0; // @[Bitwise.scala 77:12]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_4 = {
    cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_2,cmm_stage_io_rod_0_bits_pc}; // @[Cat.scala 33:92]
  wire  cmm_stage_csr_state_0_csrfiles_sepc_enable = cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_13
     & cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T = cmm_stage_csrfiles_sepc |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_2 = cmm_stage_csrfiles_sepc &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_scause_T_10 = cmm_stage__is_trap_is_interrupt_T &
    cmm_stage__csr_state_0_csrfiles_sepc_T_7; // @[CsrFiles.scala 1388:71]
  wire  cmm_stage__csr_state_0_csrfiles_scause_T_12 = cmm_stage__csr_state_0_csrfiles_scause_T_10 &
    cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 1388:105]
  wire  cmm_stage__csr_state_0_csrfiles_scause_T_21 = cmm_stage_is_trap_is_exception &
    cmm_stage__csr_state_0_csrfiles_sepc_T_7; // @[CsrFiles.scala 1399:32]
  wire  cmm_stage__csr_state_0_csrfiles_scause_T_23 = cmm_stage__csr_state_0_csrfiles_scause_T_21 &
    cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 1399:66]
  wire  cmm_stage_csr_state_0_csrfiles_scause_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_14 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scause_T = {cmm_stage_csrfiles_scause_interrupt,
    cmm_stage_csrfiles_scause_exception_code}; // @[CsrFiles.scala 1386:59]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scause_dnxt_T = cmm_stage__csr_state_0_csrfiles_scause_T |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_scause_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_2 = cmm_stage__csr_state_0_csrfiles_scause_T &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_scause_scause_interrupt_T = cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_7[63]; // @[CsrFiles.scala 1419:36]
  wire  cmm_stage__GEN_579 = cmm_stage_csr_state_0_csrfiles_scause_enable ?
    cmm_stage__csr_state_0_csrfiles_scause_scause_interrupt_T : cmm_stage_csrfiles_scause_interrupt; // @[CsrFiles.scala 1418:23 1419:29]
  wire  cmm_stage__GEN_581 = cmm_stage__csr_state_0_csrfiles_scause_T_23 ? 1'h0 : cmm_stage__GEN_579; // @[CsrFiles.scala 1399:89 1400:24]
  wire  cmm_stage__GEN_583 = cmm_stage__csr_state_0_csrfiles_scause_T_12 | cmm_stage__GEN_581; // @[CsrFiles.scala 1388:128 1389:24]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_7 =
    cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_msi ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_480 = {{1'd0}, cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_ssi}; // @[Mux.scala 27:73]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_12 = _GEN_480 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_7; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_8 =
    cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_sti ? 3'h5 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _GEN_481 = {{1'd0}, cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_12}; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_13 = _GEN_481 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_8; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_9 =
    cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_mti ? 3'h7 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_14 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_13 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_9; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_10 =
    cmm_stage_is_trap_is_interrupt_is_s_interrupt_is_sei ? 4'h9 : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _GEN_482 = {{1'd0}, cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_14}; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_15 = _GEN_482 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_10; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_11 =
    cmm_stage_is_trap_is_interrupt_is_m_interrupt_is_mei ? 4'hb : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_16 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_15 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_11; // @[Mux.scala 27:73]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_20 =
    cmm_stage_is_trap_is_exception_is_illeage ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_483 = {{1'd0}, cmm_stage_io_rod_0_bits_privil_is_access_fault}; // @[Mux.scala 27:73]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_33 = _GEN_483 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_20; // @[Mux.scala 27:73]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_21 =
    cmm_stage_is_trap_is_exception_is_ebreak_exc ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_34 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_33 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_21; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_22 =
    cmm_stage_is_trap_is_exception_is_load_misAlign ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _GEN_484 = {{1'd0}, cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_34}; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_35 = _GEN_484 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_22; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_23 =
    cmm_stage_is_trap_is_exception_is_load_accessFault ? 3'h5 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_36 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_35 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_23; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_24 =
    cmm_stage_is_trap_is_exception_is_store_misAlign ? 3'h6 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_37 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_36 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_24; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_25 =
    cmm_stage_is_trap_is_exception_is_store_accessFault ? 3'h7 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_38 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_37 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_25; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_26 =
    cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_U ? 4'h8 : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _GEN_485 = {{1'd0}, cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_38}; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_39 = _GEN_485 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_26; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_27 =
    cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_S ? 4'h9 : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_40 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_39 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_27; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_28 =
    cmm_stage_csr_state_0_csrfiles_priv_lvl_is_ecall_M ? 4'hb : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_41 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_40 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_28; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_29 =
    cmm_stage_io_rod_0_bits_privil_is_paging_fault ? 4'hc : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_42 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_41 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_29; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_30 =
    cmm_stage_is_trap_is_exception_is_load_pagingFault ? 4'hd : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_43 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_42 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_30; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_31 =
    cmm_stage_is_trap_is_exception_is_store_pagingFault ? 4'hf : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_44 =
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_43 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_31; // @[Mux.scala 27:73]
  wire [62:0] cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_45 =
    cmm_stage__csr_state_0_csrfiles_scause_dnxt_T_7[62:0]; // @[CsrFiles.scala 1420:36]
  wire [62:0] cmm_stage__GEN_580 = cmm_stage_csr_state_0_csrfiles_scause_enable ?
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_45 : cmm_stage_csrfiles_scause_exception_code; // @[CsrFiles.scala 1418:23 1420:29]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_1 = cmm_stage_io_rod_0_bits_privil_is_access_fault ?
    cmm_stage_io_if_cmm_ill_vaddr : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_2 = cmm_stage_io_rod_0_bits_privil_is_paging_fault ?
    cmm_stage_io_if_cmm_ill_vaddr : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_11 = cmm_stage__csr_state_0_csrfiles_stval_stval_T_1 |
    cmm_stage__csr_state_0_csrfiles_stval_stval_T_2; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_5 = cmm_stage_is_trap_is_exception_is_load_misAlign ?
    cmm_stage_io_lsu_cmm_trap_addr : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_14 = cmm_stage__csr_state_0_csrfiles_stval_stval_T_11 |
    cmm_stage__csr_state_0_csrfiles_stval_stval_T_5; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_6 = cmm_stage_is_trap_is_exception_is_load_accessFault ?
    cmm_stage_io_lsu_cmm_trap_addr : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_15 = cmm_stage__csr_state_0_csrfiles_stval_stval_T_14 |
    cmm_stage__csr_state_0_csrfiles_stval_stval_T_6; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_7 = cmm_stage_is_trap_is_exception_is_store_misAlign ?
    cmm_stage_io_lsu_cmm_trap_addr : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_16 = cmm_stage__csr_state_0_csrfiles_stval_stval_T_15 |
    cmm_stage__csr_state_0_csrfiles_stval_stval_T_7; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_8 = cmm_stage_is_trap_is_exception_is_store_accessFault ?
    cmm_stage_io_lsu_cmm_trap_addr : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_17 = cmm_stage__csr_state_0_csrfiles_stval_stval_T_16 |
    cmm_stage__csr_state_0_csrfiles_stval_stval_T_8; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_9 = cmm_stage_is_trap_is_exception_is_load_pagingFault ?
    cmm_stage_io_lsu_cmm_trap_addr : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_18 = cmm_stage__csr_state_0_csrfiles_stval_stval_T_17 |
    cmm_stage__csr_state_0_csrfiles_stval_stval_T_9; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_10 = cmm_stage_is_trap_is_exception_is_store_pagingFault ?
    cmm_stage_io_lsu_cmm_trap_addr : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_stval_T_19 = cmm_stage__csr_state_0_csrfiles_stval_stval_T_18 |
    cmm_stage__csr_state_0_csrfiles_stval_stval_T_10; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_stval_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_15 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_dnxt_T = cmm_stage_csrfiles_stval |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_stval_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_2 = cmm_stage_csrfiles_stval &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_satp_enable = cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_17
     & cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [19:0] cmm_stage_csr_state_0_csrfiles_satp_hi = {cmm_stage_csrfiles_satp_mode,cmm_stage_csrfiles_satp_asid}; // @[CsrFiles.scala 1494:57]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_satp_T = {cmm_stage_csrfiles_satp_mode,cmm_stage_csrfiles_satp_asid,
    cmm_stage_csrfiles_satp_ppn}; // @[CsrFiles.scala 1494:57]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_satp_dnxt_T = cmm_stage__csr_state_0_csrfiles_satp_T |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_satp_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_2 = cmm_stage__csr_state_0_csrfiles_satp_T &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_5; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_satp_satp_mode_T = cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_7[63:60]; // @[CsrFiles.scala 1497:24]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_satp_satp_mode_T_1 = cmm_stage__csr_state_0_csrfiles_satp_satp_mode_T & 4'h8
    ; // @[CsrFiles.scala 1497:32]
  wire [15:0] cmm_stage__csr_state_0_csrfiles_satp_satp_asid_T = cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_7[59:44]; // @[CsrFiles.scala 1498:24]
  wire [43:0] cmm_stage__csr_state_0_csrfiles_satp_satp_ppn_T = cmm_stage__csr_state_0_csrfiles_satp_dnxt_T_7[43:0]; // @[CsrFiles.scala 1499:24]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_is_fpu_state_change_T = ~cmm_stage_is_trap; // @[Commit.scala 222:31]
  wire  cmm_stage_csr_state_0_csrfiles_mstatus_is_fpu_state_change =
    cmm_stage__csr_state_0_csrfiles_mstatus_is_fpu_state_change_T & cmm_stage_io_rod_0_bits_is_fpu; // @[Commit.scala 222:40]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_T_24 = cmm_stage_csrfiles_mstatus_fs != 2'h0; // @[CsrFiles.scala 808:58]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_T_25 = cmm_stage_csr_state_0_csrfiles_mstatus_is_fpu_state_change &
    cmm_stage__csr_state_0_csrfiles_mstatus_T_24; // @[CsrFiles.scala 808:33]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_T_3 = cmm_stage_is_trap & cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 758:22]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_T_21 = cmm_stage_is_xRet_is_mRet & cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 770:27]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_T_23 = cmm_stage_is_xRet_is_sRet & cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 777:27]
  wire  cmm_stage_csr_state_0_csrfiles_mstatus_enable0 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_8 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [46:0] cmm_stage_csr_state_0_csrfiles_mstatus_hi = {cmm_stage_csrfiles_mstatus_sd,25'h0,2'h0,13'h1400,
    cmm_stage_csrfiles_mstatus_tsr,cmm_stage_csrfiles_mstatus_tw,cmm_stage_csrfiles_mstatus_tvm,
    cmm_stage_csrfiles_mstatus_mxr,cmm_stage_csrfiles_mstatus_sum,cmm_stage_csrfiles_mstatus_mprv}; // @[CsrFiles.scala 755:62]
  wire [5:0] cmm_stage_csr_state_0_csrfiles_mstatus_lo_lo = {cmm_stage_csrfiles_mstatus_spie,1'h0,
    cmm_stage_csrfiles_mstatus_mie,1'h0,cmm_stage_csrfiles_mstatus_sie,1'h0}; // @[CsrFiles.scala 755:62]
  wire [16:0] cmm_stage_csr_state_0_csrfiles_mstatus_lo = {2'h0,cmm_stage_csrfiles_mstatus_fs,
    cmm_stage_csrfiles_mstatus_mpp,2'h0,cmm_stage_csrfiles_mstatus_spp,cmm_stage_csrfiles_mstatus_mpie,1'h0,
    cmm_stage_csr_state_0_csrfiles_mstatus_lo_lo}; // @[CsrFiles.scala 755:62]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mstatus_T = {cmm_stage_csr_state_0_csrfiles_mstatus_hi,2'h0,
    cmm_stage_csrfiles_mstatus_fs,cmm_stage_csrfiles_mstatus_mpp,2'h0,cmm_stage_csrfiles_mstatus_spp,
    cmm_stage_csrfiles_mstatus_mpie,1'h0,cmm_stage_csr_state_0_csrfiles_mstatus_lo_lo}; // @[CsrFiles.scala 755:62]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T = cmm_stage__csr_state_0_csrfiles_mstatus_T |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_2 = cmm_stage__csr_state_0_csrfiles_mstatus_T &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_5; // @[Mux.scala 27:73]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_fs_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[14:
    13]; // @[CsrFiles.scala 787:28]
  wire  cmm_stage_csr_state_0_csrfiles_mstatus_enable1 =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_44 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [1:0] cmm_stage__GEN_722 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_fs_T : cmm_stage_csrfiles_mstatus_fs; // @[CsrFiles.scala 792:24 799:20]
  wire [1:0] cmm_stage__GEN_731 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_fs_T : cmm_stage__GEN_722; // @[CsrFiles.scala 783:24 787:20]
  wire [1:0] cmm_stage__GEN_747 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_fs :
    cmm_stage__GEN_731; // @[CsrFiles.scala 777:51]
  wire [1:0] cmm_stage__GEN_763 = cmm_stage__csr_state_0_csrfiles_mstatus_T_21 ? cmm_stage_csrfiles_mstatus_fs :
    cmm_stage__GEN_747; // @[CsrFiles.scala 770:50]
  wire [1:0] cmm_stage__GEN_777 = cmm_stage__csr_state_0_csrfiles_mstatus_T_3 ? cmm_stage_csrfiles_mstatus_fs :
    cmm_stage__GEN_763; // @[CsrFiles.scala 758:45]
  wire [1:0] cmm_stage__GEN_781 = cmm_stage__csr_state_0_csrfiles_mstatus_T_25 ? 2'h3 : cmm_stage__GEN_777; // @[CsrFiles.scala 808:67 809:18]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_sd_T_1 = cmm_stage__GEN_781 == 2'h3; // @[CsrFiles.scala 747:57]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_tsr_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[22]; // @[CsrFiles.scala 793:28]
  wire  cmm_stage__GEN_716 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_tsr_T : cmm_stage_csrfiles_mstatus_tsr; // @[CsrFiles.scala 792:24 793:20]
  wire  cmm_stage__GEN_735 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ? cmm_stage_csrfiles_mstatus_tsr :
    cmm_stage__GEN_716; // @[CsrFiles.scala 783:24]
  wire  cmm_stage__GEN_749 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_tsr :
    cmm_stage__GEN_735; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_tw_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[21]; // @[CsrFiles.scala 794:28]
  wire  cmm_stage__GEN_717 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_tw_T : cmm_stage_csrfiles_mstatus_tw; // @[CsrFiles.scala 792:24 794:20]
  wire  cmm_stage__GEN_736 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ? cmm_stage_csrfiles_mstatus_tw :
    cmm_stage__GEN_717; // @[CsrFiles.scala 783:24]
  wire  cmm_stage__GEN_750 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_tw :
    cmm_stage__GEN_736; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_tvm_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[20]; // @[CsrFiles.scala 795:28]
  wire  cmm_stage__GEN_718 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_tvm_T : cmm_stage_csrfiles_mstatus_tvm; // @[CsrFiles.scala 792:24 795:20]
  wire  cmm_stage__GEN_737 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ? cmm_stage_csrfiles_mstatus_tvm :
    cmm_stage__GEN_718; // @[CsrFiles.scala 783:24]
  wire  cmm_stage__GEN_751 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_tvm :
    cmm_stage__GEN_737; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mxr_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[19]; // @[CsrFiles.scala 785:28]
  wire  cmm_stage__GEN_719 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mxr_T : cmm_stage_csrfiles_mstatus_mxr; // @[CsrFiles.scala 792:24 796:20]
  wire  cmm_stage__GEN_729 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mxr_T : cmm_stage__GEN_719; // @[CsrFiles.scala 783:24 785:20]
  wire  cmm_stage__GEN_745 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_mxr :
    cmm_stage__GEN_729; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_sum_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[18]; // @[CsrFiles.scala 786:28]
  wire  cmm_stage__GEN_720 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_sum_T : cmm_stage_csrfiles_mstatus_sum; // @[CsrFiles.scala 792:24 797:20]
  wire  cmm_stage__GEN_730 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_sum_T : cmm_stage__GEN_720; // @[CsrFiles.scala 783:24 786:20]
  wire  cmm_stage__GEN_746 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_sum :
    cmm_stage__GEN_730; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mprv_T_7 = cmm_stage__GEN_493 != 2'h3; // @[CsrFiles.scala 775:48]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mprv_T_8 =
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mprv_T_7 ? 1'h0 : cmm_stage_csrfiles_mstatus_mprv; // @[CsrFiles.scala 775:26]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mprv_T_18 = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[17]
    ; // @[CsrFiles.scala 798:28]
  wire  cmm_stage__GEN_721 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mprv_T_18 : cmm_stage_csrfiles_mstatus_mprv; // @[CsrFiles.scala 792:24 798:20]
  wire  cmm_stage__GEN_738 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ? cmm_stage_csrfiles_mstatus_mprv :
    cmm_stage__GEN_721; // @[CsrFiles.scala 783:24]
  wire  cmm_stage__GEN_744 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mprv_T_8 : cmm_stage__GEN_738; // @[CsrFiles.scala 777:51 781:20]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_T_11 = cmm_stage__GEN_493 == 2'h3; // @[CsrFiles.scala 759:33]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mpp_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[12
    :11]; // @[CsrFiles.scala 800:28]
  wire [1:0] cmm_stage__GEN_723 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mpp_T : cmm_stage_csrfiles_mstatus_mpp; // @[CsrFiles.scala 792:24 800:20]
  wire [1:0] cmm_stage__GEN_739 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ? cmm_stage_csrfiles_mstatus_mpp :
    cmm_stage__GEN_723; // @[CsrFiles.scala 783:24]
  wire [1:0] cmm_stage__GEN_752 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_mpp :
    cmm_stage__GEN_739; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_spp_T_1 =
    cmm_stage__is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm_is_ebreak_breakpointn_T_3 ? 1'h0
     : 1'h1; // @[CsrFiles.scala 765:28]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_spp_T_2 = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[8]; // @[CsrFiles.scala 788:28]
  wire  cmm_stage__GEN_724 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_spp_T_2 : cmm_stage_csrfiles_mstatus_spp; // @[CsrFiles.scala 792:24 801:20]
  wire  cmm_stage__GEN_732 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_spp_T_2 : cmm_stage__GEN_724; // @[CsrFiles.scala 783:24 788:20]
  wire  cmm_stage__GEN_748 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_spp :
    cmm_stage__GEN_732; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mpie_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[7]; // @[CsrFiles.scala 802:28]
  wire  cmm_stage__GEN_725 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mpie_T : cmm_stage_csrfiles_mstatus_mpie; // @[CsrFiles.scala 792:24 802:20]
  wire  cmm_stage__GEN_740 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ? cmm_stage_csrfiles_mstatus_mpie :
    cmm_stage__GEN_725; // @[CsrFiles.scala 783:24]
  wire  cmm_stage__GEN_753 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_mpie :
    cmm_stage__GEN_740; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__GEN_756 = cmm_stage__csr_state_0_csrfiles_mstatus_T_21 | cmm_stage__GEN_753; // @[CsrFiles.scala 770:50 772:20]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_spie_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[5]; // @[CsrFiles.scala 789:28]
  wire  cmm_stage__GEN_726 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_spie_T : cmm_stage_csrfiles_mstatus_spie; // @[CsrFiles.scala 792:24 803:20]
  wire  cmm_stage__GEN_733 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_spie_T : cmm_stage__GEN_726; // @[CsrFiles.scala 783:24 789:20]
  wire  cmm_stage__GEN_742 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 | cmm_stage__GEN_733; // @[CsrFiles.scala 777:51 778:20]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mie_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[3]; // @[CsrFiles.scala 804:28]
  wire  cmm_stage__GEN_727 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mie_T : cmm_stage_csrfiles_mstatus_mie; // @[CsrFiles.scala 792:24 804:20]
  wire  cmm_stage__GEN_741 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ? cmm_stage_csrfiles_mstatus_mie :
    cmm_stage__GEN_727; // @[CsrFiles.scala 783:24]
  wire  cmm_stage__GEN_754 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_mie :
    cmm_stage__GEN_741; // @[CsrFiles.scala 777:51]
  wire  cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_sie_T = cmm_stage__csr_state_0_csrfiles_mstatus_dnxt_T_7[1]; // @[CsrFiles.scala 790:28]
  wire  cmm_stage__GEN_728 = cmm_stage_csr_state_0_csrfiles_mstatus_enable1 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_sie_T : cmm_stage_csrfiles_mstatus_sie; // @[CsrFiles.scala 792:24 805:20]
  wire  cmm_stage__GEN_734 = cmm_stage_csr_state_0_csrfiles_mstatus_enable0 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_sie_T : cmm_stage__GEN_728; // @[CsrFiles.scala 783:24 790:20]
  wire  cmm_stage__GEN_743 = cmm_stage__csr_state_0_csrfiles_mstatus_T_23 ? cmm_stage_csrfiles_mstatus_spie :
    cmm_stage__GEN_734; // @[CsrFiles.scala 777:51 779:20]
  wire  cmm_stage_csr_state_0_csrfiles_medeleg_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_46 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T = cmm_stage_csrfiles_medeleg |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_2 = cmm_stage_csrfiles_medeleg &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_mideleg_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_47 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T = cmm_stage_csrfiles_mideleg |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_2 = cmm_stage_csrfiles_mideleg &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_mie_enable0 = cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_48
     & cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [5:0] cmm_stage_csr_state_0_csrfiles_mie_lo = {cmm_stage_csrfiles_mie_sti,1'h0,cmm_stage_csrfiles_mie_msi,1'h0,
    cmm_stage_csrfiles_mie_ssi,1'h0}; // @[CsrFiles.scala 879:58]
  wire [15:0] cmm_stage__csr_state_0_csrfiles_mie_T = {4'h0,cmm_stage_csrfiles_mie_mei,1'h0,cmm_stage_csrfiles_mie_sei,1'h0
    ,cmm_stage_csrfiles_mie_mti,1'h0,cmm_stage_csr_state_0_csrfiles_mie_lo}; // @[CsrFiles.scala 879:58]
  wire [63:0] _GEN_486 = {{48'd0}, cmm_stage__csr_state_0_csrfiles_mie_T}; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mie_dnxt_T = _GEN_486 | cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mie_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_2 = _GEN_486 & cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_mie_mie_mei_T = cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_7[11]; // @[CsrFiles.scala 883:23]
  wire  cmm_stage__csr_state_0_csrfiles_mie_mie_sei_T = cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_7[9]; // @[CsrFiles.scala 884:23]
  wire  cmm_stage_csr_state_0_csrfiles_mie_enable1 = cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_9
     & cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire  cmm_stage__csr_state_0_csrfiles_mie_mie_mti_T = cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_7[7]; // @[CsrFiles.scala 885:23]
  wire  cmm_stage__csr_state_0_csrfiles_mie_mie_sti_T = cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_7[5]; // @[CsrFiles.scala 886:23]
  wire  cmm_stage__csr_state_0_csrfiles_mie_mie_msi_T = cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_7[3]; // @[CsrFiles.scala 887:23]
  wire  cmm_stage__csr_state_0_csrfiles_mie_mie_ssi_T = cmm_stage__csr_state_0_csrfiles_mie_dnxt_T_7[1]; // @[CsrFiles.scala 888:23]
  wire  cmm_stage_csr_state_0_csrfiles_mtvec_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_49 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtvec_T = {cmm_stage_csrfiles_mtvec_base,2'h0}; // @[CsrFiles.scala 911:58]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T = cmm_stage__csr_state_0_csrfiles_mtvec_T |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_2 = cmm_stage__csr_state_0_csrfiles_mtvec_T &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_5; // @[Mux.scala 27:73]
  wire [61:0] cmm_stage__csr_state_0_csrfiles_mtvec_mtvec_base_T = cmm_stage__csr_state_0_csrfiles_mtvec_dnxt_T_7[63:2]; // @[CsrFiles.scala 912:38]
  wire [63:0] _GEN_490 = {{32'd0}, cmm_stage_csrfiles_mcounteren_hpm}; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T = _GEN_490 | cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_2 = _GEN_490 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_6
     | cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_5; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__GEN_794 = cmm_stage_csr_state_0_csrfiles_scounteren_enable ?
    cmm_stage__csr_state_0_csrfiles_mcounteren_dnxt_T_7 : {{32'd0}, cmm_stage_csrfiles_mcounteren_hpm}; // @[CsrFiles.scala 933:{18,35}]
  wire [31:0] cmm_stage_csr_state_0_csrfiles_mcounteren_mcounteren_hpm = cmm_stage__GEN_794[31:0];
  wire  cmm_stage_csr_state_0_csrfiles_mscratch_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_51 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T = cmm_stage_csrfiles_mscratch |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_2 = cmm_stage_csrfiles_mscratch &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_mepc_T_8 = cmm_stage_is_trap & cmm_stage__csr_state_0_csrfiles_mstatus_T_11; // @[CsrFiles.scala 962:22]
  wire  cmm_stage__csr_state_0_csrfiles_mepc_T_10 = cmm_stage__csr_state_0_csrfiles_mepc_T_8 &
    cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 962:56]
  wire  cmm_stage_csr_state_0_csrfiles_mepc_enable = cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_52
     & cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T = cmm_stage_csrfiles_mepc |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_2 = cmm_stage_csrfiles_mepc &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_mcause_T_9 = cmm_stage_is_trap_is_interrupt_is_m_interrupt &
    cmm_stage__csr_state_0_csrfiles_mstatus_T_11; // @[CsrFiles.scala 978:38]
  wire  cmm_stage__csr_state_0_csrfiles_mcause_T_11 = cmm_stage__csr_state_0_csrfiles_mcause_T_9 &
    cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 978:72]
  wire  cmm_stage__csr_state_0_csrfiles_mcause_T_20 = cmm_stage_is_trap_is_exception &
    cmm_stage__csr_state_0_csrfiles_mstatus_T_11; // @[CsrFiles.scala 989:32]
  wire  cmm_stage__csr_state_0_csrfiles_mcause_T_22 = cmm_stage__csr_state_0_csrfiles_mcause_T_20 &
    cmm_stage__is_trap_is_interrupt_T_2; // @[CsrFiles.scala 989:66]
  wire  cmm_stage_csr_state_0_csrfiles_mcause_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_53 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcause_T = {cmm_stage_csrfiles_mcause_interrupt,
    cmm_stage_csrfiles_mcause_exception_code}; // @[CsrFiles.scala 976:59]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T = cmm_stage__csr_state_0_csrfiles_mcause_T |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_2 = cmm_stage__csr_state_0_csrfiles_mcause_T &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_mcause_mcause_interrupt_T = cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_7[63]; // @[CsrFiles.scala 1009:36]
  wire  cmm_stage__GEN_870 = cmm_stage_csr_state_0_csrfiles_mcause_enable ?
    cmm_stage__csr_state_0_csrfiles_mcause_mcause_interrupt_T : cmm_stage_csrfiles_mcause_interrupt; // @[CsrFiles.scala 1008:23 1009:29]
  wire  cmm_stage__GEN_872 = cmm_stage__csr_state_0_csrfiles_mcause_T_22 ? 1'h0 : cmm_stage__GEN_870; // @[CsrFiles.scala 989:89 990:24]
  wire  cmm_stage__GEN_874 = cmm_stage__csr_state_0_csrfiles_mcause_T_11 | cmm_stage__GEN_872; // @[CsrFiles.scala 978:95 979:24]
  wire [2:0] _GEN_492 = {{1'd0}, cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_7}; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_mcause_mcause_exception_code_T_6 = _GEN_492 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_9; // @[Mux.scala 27:73]
  wire [3:0] _GEN_493 = {{1'd0}, cmm_stage__csr_state_0_csrfiles_mcause_mcause_exception_code_T_6}; // @[Mux.scala 27:73]
  wire [3:0] cmm_stage__csr_state_0_csrfiles_mcause_mcause_exception_code_T_7 = _GEN_493 |
    cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_11; // @[Mux.scala 27:73]
  wire [62:0] cmm_stage__csr_state_0_csrfiles_mcause_mcause_exception_code_T_36 =
    cmm_stage__csr_state_0_csrfiles_mcause_dnxt_T_7[62:0]; // @[CsrFiles.scala 1010:36]
  wire [62:0] cmm_stage__GEN_871 = cmm_stage_csr_state_0_csrfiles_mcause_enable ?
    cmm_stage__csr_state_0_csrfiles_mcause_mcause_exception_code_T_36 : cmm_stage_csrfiles_mcause_exception_code; // @[CsrFiles.scala 1008:23 1010:29]
  wire  cmm_stage_csr_state_0_csrfiles_mtval_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_54 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T = cmm_stage_csrfiles_mtval |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_2 = cmm_stage_csrfiles_mtval &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_mtinst_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_56 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T = cmm_stage_csrfiles_mtinst |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_2 = cmm_stage_csrfiles_mtinst &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_mtval2_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_57 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T = cmm_stage_csrfiles_mtval2 |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_2 = cmm_stage_csrfiles_mtval2 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_mcycle_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_58 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T = cmm_stage_csrfiles_mcycle |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_2 = cmm_stage_csrfiles_mcycle &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_minstret_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_59 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T = cmm_stage_csrfiles_minstret |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_2 = cmm_stage_csrfiles_minstret &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_5; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_minstret_minstret_T_1 = cmm_stage_csrfiles_minstret + 64'h1; // @[CsrFiles.scala 1159:51]
  wire  cmm_stage_csr_state_0_csrfiles_tselect_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_61 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T = cmm_stage_csrfiles_tselect |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_2 = cmm_stage_csrfiles_tselect &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_5; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tselect_tselect_T_1 = ~cmm_stage__csr_state_0_csrfiles_tselect_dnxt_T_7; // @[CsrFiles.scala 1746:51]
  wire  cmm_stage_csr_state_0_csrfiles_tdata1_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_62 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T = cmm_stage_csrfiles_tdata1 |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_2 = cmm_stage_csrfiles_tdata1 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_tdata2_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_63 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T = cmm_stage_csrfiles_tdata2 |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_2 = cmm_stage_csrfiles_tdata2 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_tdata3_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_64 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T = cmm_stage_csrfiles_tdata3 |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_2 = cmm_stage_csrfiles_tdata3 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_dcsr_enable = cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_65
     & cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [9:0] cmm_stage_csr_state_0_csrfiles_dcsr_lo = {1'h0,cmm_stage_csrfiles_dcsr_cause,2'h0,1'h0,
    cmm_stage_csrfiles_dcsr_step,cmm_stage_csrfiles_dcsr_prv}; // @[CsrFiles.scala 1794:59]
  wire [31:0] cmm_stage__csr_state_0_csrfiles_dcsr_T = {16'h4000,cmm_stage_csrfiles_dcsr_ebreakm,1'h0,
    cmm_stage_csrfiles_dcsr_ebreaks,cmm_stage_csrfiles_dcsr_ebreaku,2'h0,cmm_stage_csr_state_0_csrfiles_dcsr_lo}; // @[CsrFiles.scala 1794:59]
  wire [63:0] _GEN_497 = {{32'd0}, cmm_stage__csr_state_0_csrfiles_dcsr_T}; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T = _GEN_497 | cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_2 = _GEN_497 & cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_ebreakm_T = cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_7[15]; // @[CsrFiles.scala 1809:31]
  wire  cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_ebreaks_T = cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_7[13]; // @[CsrFiles.scala 1810:31]
  wire  cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_ebreaku_T = cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_7[12]; // @[CsrFiles.scala 1811:31]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_cause_T = cmm_stage_is_single_step ? 3'h4 : 3'h0; // @[Mux.scala 101:16]
  wire [2:0] cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_cause_T_1 = cmm_stage_io_dm_hartHaltReq ? 3'h3 :
    cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_cause_T; // @[Mux.scala 101:16]
  wire  cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_step_T = cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_7[2]; // @[CsrFiles.scala 1812:26]
  wire [1:0] cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_prv_T = cmm_stage__csr_state_0_csrfiles_dcsr_dnxt_T_7[1:0]; // @[CsrFiles.scala 1813:26]
  wire  cmm_stage_csr_state_0_csrfiles_dpc_enable = cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_66
     & cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T = cmm_stage_csrfiles_dpc |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_2 = cmm_stage_csrfiles_dpc &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_dpc_T_2 = cmm_stage__is_trap_is_interrupt_T_2 & cmm_stage__GEN_495; // @[CsrFiles.scala 1827:50]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dpc_T =
    cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm ?
    cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dpc_T_1 = cmm_stage_is_single_step ?
    cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dpc_T_4 = cmm_stage__csr_state_0_csrfiles_dpc_dpc_T |
    cmm_stage__csr_state_0_csrfiles_dpc_dpc_T_1; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dpc_T_3 = cmm_stage_io_dm_hartHaltReq ?
    cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dpc_dpc_T_6 = cmm_stage__csr_state_0_csrfiles_dpc_dpc_T_4 |
    cmm_stage__csr_state_0_csrfiles_dpc_dpc_T_3; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_dscratch0_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_67 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T = cmm_stage_csrfiles_dscratch0 |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_2 = cmm_stage_csrfiles_dscratch0 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage_csr_state_0_csrfiles_dscratch1_enable =
    cmm_stage__is_trap_is_exception_is_csr_illegal_is_csrw_illegal_T_68 &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T = cmm_stage_csrfiles_dscratch1 |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_2 = cmm_stage_csrfiles_dscratch1 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__csr_state_0_csrfiles_dscratch2_enable_T = cmm_stage_csrExe_mdl_io_deq_0_bits_addr == 12'h7b4; // @[CsrFiles.scala 42:27]
  wire  cmm_stage_csr_state_0_csrfiles_dscratch2_enable = cmm_stage__csr_state_0_csrfiles_dscratch2_enable_T &
    cmm_stage__csr_state_0_csrfiles_stvec_enable_T_2; // @[CsrFiles.scala 42:37]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T = cmm_stage_csrfiles_dscratch2 |
    cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i; // @[CsrFiles.scala 45:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_4 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs ?
    cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_6 = cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_3 |
    cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_4; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_2 = cmm_stage_csrfiles_dscratch2 &
    cmm_stage__csr_state_0_csrfiles_stvec_dnxt_T_1; // @[CsrFiles.scala 46:30]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_5 = cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc ?
    cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_7 = cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_6 |
    cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_5; // @[Mux.scala 27:73]
  wire  cmm_stage__T_5 = cmm_stage__T_1 & cmm_stage_is_step_1; // @[Commit.scala 404:91]
  wire  cmm_stage__GEN_460 = cmm_stage_csrfiles_DMode ? 1'h0 : cmm_stage_is_single_step; // @[Commit.scala 404:{171,188,31}]
  wire  cmm_stage__GEN_461 = cmm_stage__T_5 | cmm_stage__GEN_460; // @[Commit.scala 404:{115,132}]
  wire  cmm_stage__io_cmm_lsu_is_amo_pending_T = cmm_stage_io_rod_0_valid & cmm_stage_io_rod_0_bits_is_amo; // @[Commit.scala 547:21]
  wire  cmm_stage__mdl_io_deq_0_ready_T = cmm_stage_is_retired_0 & cmm_stage_io_rod_0_bits_is_branch; // @[Commit.scala 679:36]
  wire  cmm_stage__T_34 = cmm_stage_bctq_mdl_io_deq_0_ready & cmm_stage_bctq_mdl_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  cmm_stage__T_36 = cmm_stage__T_34 == cmm_stage__mdl_io_deq_0_ready_T; // @[Commit.scala 680:26]
  wire  cmm_stage__T_38 = ~cmm_stage_reset; // @[Commit.scala 680:11]
  wire  cmm_stage__T_39 = ~cmm_stage__T_36; // @[Commit.scala 680:11]
  wire  cmm_stage__T_41 = cmm_stage_io_bctq_ready & cmm_stage_io_bctq_valid; // @[Decoupled.scala 52:35]
  wire  cmm_stage__T_42 = cmm_stage__T_34 == cmm_stage__T_41; // @[Commit.scala 681:42]
  wire  cmm_stage__T_45 = ~cmm_stage__T_42; // @[Commit.scala 681:11]
  wire  cmm_stage__mdl_io_deq_0_ready_T_1 = cmm_stage_is_retired_0 & cmm_stage_io_rod_0_bits_is_jalr; // @[Commit.scala 685:36]
  wire  cmm_stage__T_46 = cmm_stage_jctq_mdl_io_deq_0_ready & cmm_stage_jctq_mdl_io_deq_0_valid; // @[Decoupled.scala 52:35]
  wire  cmm_stage__T_48 = cmm_stage__T_46 == cmm_stage__mdl_io_deq_0_ready_T_1; // @[Commit.scala 686:26]
  wire  cmm_stage__T_51 = ~cmm_stage__T_48; // @[Commit.scala 686:11]
  wire  cmm_stage__T_53 = cmm_stage_io_jctq_ready & cmm_stage_io_jctq_valid; // @[Decoupled.scala 52:35]
  wire  cmm_stage__T_54 = cmm_stage__T_46 == cmm_stage__T_53; // @[Commit.scala 687:42]
  wire  cmm_stage__T_57 = ~cmm_stage__T_54; // @[Commit.scala 687:11]
  wire  cmm_stage__T_60 = cmm_stage__T_11 & cmm_stage_is_retired_0; // @[Commit.scala 712:63]
  wire  cmm_stage__T_63 = cmm_stage__T_60 & cmm_stage__T_21; // @[Commit.scala 712:79]
  wire [63:0] cmm_stage__GEN_935 = cmm_stage__T_63 ? cmm_stage_bctq_mdl_io_deq_0_bits_finalTarget : 64'h0; // @[Commit.scala 712:104 709:26 714:30]
  wire  cmm_stage__T_68 = cmm_stage__T_16 & cmm_stage_is_retired_0; // @[Commit.scala 717:63]
  wire  cmm_stage__T_71 = cmm_stage__T_68 & cmm_stage__T_21; // @[Commit.scala 717:79]
  wire  cmm_stage__GEN_936 = cmm_stage__T_71 | cmm_stage__T_63; // @[Commit.scala 717:104 718:28]
  wire [63:0] cmm_stage__GEN_937 = cmm_stage__T_71 ? cmm_stage_jctq_mdl_io_deq_0_bits_finalTarget : cmm_stage__GEN_935; // @[Commit.scala 717:104 719:30]
  wire  cmm_stage__T_72 = cmm_stage_is_fence_i | cmm_stage_is_sfence_vma; // @[Commit.scala 725:39]
  wire [63:0] cmm_stage__io_cmmRedirect_bits_pc_T_1 = cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_4 + 64'h4
    ; // @[Commit.scala 727:72]
  wire  cmm_stage__GEN_938 = cmm_stage__T_72 | cmm_stage__GEN_936; // @[Commit.scala 725:70 726:32]
  wire [63:0] cmm_stage__GEN_939 = cmm_stage__T_72 ? cmm_stage__io_cmmRedirect_bits_pc_T_1 : cmm_stage__GEN_937; // @[Commit.scala 725:70 727:34]
  wire [11:0] cmm_stage__GEN_941 = cmm_stage_is_trap_is_exception_is_ebreak_exc ? 12'h800 : 12'h808; // @[Commit.scala 733:46 735:36 738:36]
  wire  cmm_stage__GEN_942 = cmm_stage_is_trap_is_exception | cmm_stage__GEN_938; // @[Commit.scala 732:43]
  wire [63:0] cmm_stage__GEN_943 = cmm_stage_is_trap_is_exception ? {{52'd0}, cmm_stage__GEN_941} : cmm_stage__GEN_939; // @[Commit.scala 732:43]
  wire  cmm_stage__GEN_944 = cmm_stage_is_xRet_is_dRet | cmm_stage__GEN_942; // @[Commit.scala 741:38 742:32]
  wire [63:0] cmm_stage__GEN_945 = cmm_stage_is_xRet_is_dRet ? cmm_stage_csrfiles_dpc : cmm_stage__GEN_943; // @[Commit.scala 741:38 743:34]
  wire  cmm_stage__GEN_946 = cmm_stage_is_xRet_is_mRet | cmm_stage__GEN_936; // @[Commit.scala 746:38 747:32]
  wire [63:0] cmm_stage__GEN_947 = cmm_stage_is_xRet_is_mRet ? cmm_stage_csrfiles_mepc : cmm_stage__GEN_937; // @[Commit.scala 746:38 748:34]
  wire  cmm_stage__GEN_948 = cmm_stage_is_xRet_is_sRet | cmm_stage__GEN_946; // @[Commit.scala 750:38 751:32]
  wire [63:0] cmm_stage__GEN_949 = cmm_stage_is_xRet_is_sRet ? cmm_stage_csrfiles_sepc : cmm_stage__GEN_947; // @[Commit.scala 750:38 752:34]
  wire [63:0] cmm_stage__io_cmmRedirect_bits_pc_T_20 = cmm_stage__csr_state_0_csrfiles_sepc_T_7 ?
    cmm_stage__csr_state_0_csrfiles_stvec_T : 64'h80000000; // @[Mux.scala 101:16]
  wire [63:0] cmm_stage__io_cmmRedirect_bits_pc_T_21 = cmm_stage__csr_state_0_csrfiles_mstatus_T_11 ?
    cmm_stage__csr_state_0_csrfiles_mtvec_T : cmm_stage__io_cmmRedirect_bits_pc_T_20; // @[Mux.scala 101:16]
  wire [63:0] cmm_stage__io_cmmRedirect_bits_pc_T_22 =
    cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt ? 64'h800 :
    cmm_stage__io_cmmRedirect_bits_pc_T_21; // @[Mux.scala 101:16]
  wire [63:0] cmm_stage__io_cmmRedirect_bits_pc_T_23 = cmm_stage_emu_reset ? 64'h80000000 :
    cmm_stage__io_cmmRedirect_bits_pc_T_22; // @[Mux.scala 101:16]
  wire  cmm_stage__GEN_998 = cmm_stage_is_trap | cmm_stage__GEN_948; // @[Commit.scala 754:38 755:32]
  wire [63:0] cmm_stage__GEN_999 = cmm_stage_is_trap ? cmm_stage__io_cmmRedirect_bits_pc_T_23 : cmm_stage__GEN_949; // @[Commit.scala 754:38 756:34]
  wire  cmm_stage__GEN_1000 = cmm_stage__T_72 | cmm_stage__GEN_998; // @[Commit.scala 763:70 764:32]
  wire [63:0] cmm_stage__GEN_1001 = cmm_stage__T_72 ? cmm_stage__io_cmmRedirect_bits_pc_T_1 : cmm_stage__GEN_999; // @[Commit.scala 763:70 765:34]
  wire [1:0] cmm_stage__T_77 = cmm_stage_is_xRet + cmm_stage_is_trap; // @[Bitwise.scala 51:90]
  wire [1:0] cmm_stage__T_79 = cmm_stage_is_fence_i + cmm_stage_is_sfence_vma; // @[Bitwise.scala 51:90]
  wire [2:0] cmm_stage__T_81 = cmm_stage__T_77 + cmm_stage__T_79; // @[Bitwise.scala 51:90]
  wire  cmm_stage__T_83 = cmm_stage__T_81 <= 3'h1; // @[Commit.scala 768:129]
  wire  cmm_stage__T_86 = ~cmm_stage__T_83; // @[Commit.scala 768:15]
  wire  cmm_stage__GEN_1002 = cmm_stage_csrfiles_DMode ? cmm_stage__GEN_944 : cmm_stage__GEN_1000; // @[Commit.scala 724:43]
  wire [63:0] cmm_stage__GEN_1003 = cmm_stage_csrfiles_DMode ? cmm_stage__GEN_945 : cmm_stage__GEN_1001; // @[Commit.scala 724:43]
  wire [63:0] cmm_stage__io_csr_data_bits_T_10 = cmm_stage__csr_state_0_csrfiles_mstatus_T & 64'h80000003000de162; // @[CsrFiles.scala 272:33]
  wire  cmm_stage__io_csr_data_bits_T_11 = cmm_stage__io_csr_data_bits_T_10[0]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_12 = cmm_stage__io_csr_data_bits_T_10[1]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_13 = cmm_stage__io_csr_data_bits_T_10[2]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_14 = cmm_stage__io_csr_data_bits_T_10[3]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_15 = cmm_stage__io_csr_data_bits_T_10[4]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_16 = cmm_stage__io_csr_data_bits_T_10[5]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_17 = cmm_stage__io_csr_data_bits_T_10[6]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_18 = cmm_stage__io_csr_data_bits_T_10[7]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_19 = cmm_stage__io_csr_data_bits_T_10[8]; // @[CsrFiles.scala 272:116]
  wire [1:0] cmm_stage__io_csr_data_bits_T_20 = cmm_stage__io_csr_data_bits_T_10[10:9]; // @[CsrFiles.scala 272:116]
  wire [1:0] cmm_stage__io_csr_data_bits_T_21 = cmm_stage__io_csr_data_bits_T_10[12:11]; // @[CsrFiles.scala 272:116]
  wire [1:0] cmm_stage__io_csr_data_bits_T_22 = cmm_stage__io_csr_data_bits_T_10[14:13]; // @[CsrFiles.scala 272:116]
  wire [1:0] cmm_stage__io_csr_data_bits_T_23 = cmm_stage__io_csr_data_bits_T_10[16:15]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_24 = cmm_stage__io_csr_data_bits_T_10[17]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_25 = cmm_stage__io_csr_data_bits_T_10[18]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_26 = cmm_stage__io_csr_data_bits_T_10[19]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_27 = cmm_stage__io_csr_data_bits_T_10[20]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_28 = cmm_stage__io_csr_data_bits_T_10[21]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_29 = cmm_stage__io_csr_data_bits_T_10[22]; // @[CsrFiles.scala 272:116]
  wire [8:0] cmm_stage__io_csr_data_bits_T_30 = cmm_stage__io_csr_data_bits_T_10[31:23]; // @[CsrFiles.scala 272:116]
  wire [1:0] cmm_stage__io_csr_data_bits_T_31 = cmm_stage__io_csr_data_bits_T_10[33:32]; // @[CsrFiles.scala 272:116]
  wire [1:0] cmm_stage__io_csr_data_bits_T_32 = cmm_stage__io_csr_data_bits_T_10[35:34]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_33 = cmm_stage__io_csr_data_bits_T_10[36]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_34 = cmm_stage__io_csr_data_bits_T_10[37]; // @[CsrFiles.scala 272:116]
  wire [24:0] cmm_stage__io_csr_data_bits_T_35 = cmm_stage__io_csr_data_bits_T_10[62:38]; // @[CsrFiles.scala 272:116]
  wire  cmm_stage__io_csr_data_bits_T_36 = cmm_stage__io_csr_data_bits_T_10[63]; // @[CsrFiles.scala 272:116]
  wire [5:0] cmm_stage_io_csr_data_bits_lo_lo_1 = {cmm_stage__io_csr_data_bits_T_16,cmm_stage__io_csr_data_bits_T_15,
    cmm_stage__io_csr_data_bits_T_14,cmm_stage__io_csr_data_bits_T_13,cmm_stage__io_csr_data_bits_T_12,
    cmm_stage__io_csr_data_bits_T_11}; // @[CsrFiles.scala 591:44]
  wire [16:0] cmm_stage_io_csr_data_bits_lo_2 = {cmm_stage__io_csr_data_bits_T_23,cmm_stage__io_csr_data_bits_T_22,
    cmm_stage__io_csr_data_bits_T_21,cmm_stage__io_csr_data_bits_T_20,cmm_stage__io_csr_data_bits_T_19,
    cmm_stage__io_csr_data_bits_T_18,cmm_stage__io_csr_data_bits_T_17,cmm_stage_io_csr_data_bits_lo_lo_1}; // @[CsrFiles.scala 591:44]
  wire [5:0] cmm_stage_io_csr_data_bits_hi_lo_1 = {cmm_stage__io_csr_data_bits_T_29,cmm_stage__io_csr_data_bits_T_28,
    cmm_stage__io_csr_data_bits_T_27,cmm_stage__io_csr_data_bits_T_26,cmm_stage__io_csr_data_bits_T_25,
    cmm_stage__io_csr_data_bits_T_24}; // @[CsrFiles.scala 591:44]
  wire [46:0] cmm_stage_io_csr_data_bits_hi_2 = {cmm_stage__io_csr_data_bits_T_36,cmm_stage__io_csr_data_bits_T_35,
    cmm_stage__io_csr_data_bits_T_34,cmm_stage__io_csr_data_bits_T_33,cmm_stage__io_csr_data_bits_T_32,
    cmm_stage__io_csr_data_bits_T_31,cmm_stage__io_csr_data_bits_T_30,cmm_stage_io_csr_data_bits_hi_lo_1}; // @[CsrFiles.scala 591:44]
  wire [63:0] cmm_stage__io_csr_data_bits_T_37 = {cmm_stage__io_csr_data_bits_T_36,cmm_stage__io_csr_data_bits_T_35,
    cmm_stage__io_csr_data_bits_T_34,cmm_stage__io_csr_data_bits_T_33,cmm_stage__io_csr_data_bits_T_32,
    cmm_stage__io_csr_data_bits_T_31,cmm_stage__io_csr_data_bits_T_30,cmm_stage_io_csr_data_bits_hi_lo_1,
    cmm_stage_io_csr_data_bits_lo_2}; // @[CsrFiles.scala 591:44]
  wire [5:0] cmm_stage_io_csr_data_bits_lo_4 = {cmm_stage_csrfiles_mip_sti,1'h0,cmm_stage_csrfiles_mip_msi,1'h0,
    cmm_stage_csrfiles_mip_ssi,1'h0}; // @[CsrFiles.scala 601:40]
  wire [15:0] cmm_stage__io_csr_data_bits_T_49 = {4'h0,cmm_stage_csrfiles_mip_mei,1'h0,cmm_stage_csrfiles_mip_sei,1'h0,
    cmm_stage_csrfiles_mip_mti,1'h0,cmm_stage_io_csr_data_bits_lo_4}; // @[CsrFiles.scala 601:40]
  wire  cmm_stage__io_csr_data_bits_T_87 = cmm_stage_io_csr_addr_bits == 12'h7b4; // @[CsrFiles.scala 655:18]
  wire [4:0] cmm_stage__io_csr_data_bits_T_88 = cmm_stage__cmm_state_0_is_csrr_illegal_T ?
    cmm_stage_csrfiles_fcsr_fflags : 5'h0; // @[Mux.scala 27:73]
  wire [2:0] cmm_stage__io_csr_data_bits_T_89 = cmm_stage__cmm_state_0_is_csrr_illegal_T_2 ? cmm_stage_csrfiles_fcsr_frm
     : 3'h0; // @[Mux.scala 27:73]
  wire [7:0] cmm_stage__io_csr_data_bits_T_90 = cmm_stage__cmm_state_0_is_csrr_illegal_T_4 ?
    cmm_stage__csr_state_0_csrfiles_fcsr_T : 8'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_91 = cmm_stage__cmm_state_0_is_csrr_illegal_T_6 ? cmm_stage_csrfiles_mcycle
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_92 = cmm_stage__cmm_state_0_is_csrr_illegal_T_8 ? cmm_stage_csrfiles_time : 64'h0
    ; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_93 = cmm_stage__cmm_state_0_is_csrr_illegal_T_10 ?
    cmm_stage_csrfiles_minstret : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_94 = cmm_stage__cmm_state_0_is_csrr_illegal_T_12 ?
    cmm_stage__io_csr_data_bits_T_37 : 64'h0; // @[Mux.scala 27:73]
  wire [15:0] cmm_stage__io_csr_data_bits_T_95 = cmm_stage__cmm_state_0_is_csrr_illegal_T_14 ?
    cmm_stage__csr_state_0_csrfiles_mie_T : 16'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_96 = cmm_stage__cmm_state_0_is_csrr_illegal_T_16 ?
    cmm_stage__csr_state_0_csrfiles_stvec_T : 64'h0; // @[Mux.scala 27:73]
  wire [31:0] cmm_stage__io_csr_data_bits_T_97 = cmm_stage__cmm_state_0_is_csrr_illegal_T_18 ?
    cmm_stage_csrfiles_scounteren_hpm : 32'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_98 = cmm_stage__cmm_state_0_is_csrr_illegal_T_20 ?
    cmm_stage_csrfiles_sscratch : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_99 = cmm_stage__cmm_state_0_is_csrr_illegal_T_22 ? cmm_stage_csrfiles_sepc
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_100 = cmm_stage__cmm_state_0_is_csrr_illegal_T_24 ?
    cmm_stage__csr_state_0_csrfiles_scause_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_101 = cmm_stage__cmm_state_0_is_csrr_illegal_T_26 ? cmm_stage_csrfiles_stval
     : 64'h0; // @[Mux.scala 27:73]
  wire [15:0] cmm_stage__io_csr_data_bits_T_102 = cmm_stage__cmm_state_0_is_csrr_illegal_T_28 ?
    cmm_stage__io_csr_data_bits_T_49 : 16'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_103 = cmm_stage__cmm_state_0_is_csrr_illegal_T_30 ?
    cmm_stage__csr_state_0_csrfiles_satp_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_105 = cmm_stage__cmm_state_0_is_csrr_illegal_T_60 ?
    cmm_stage_csrfiles_marchid : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_108 = cmm_stage__cmm_state_0_is_csrr_illegal_T_66 ?
    cmm_stage__csr_state_0_csrfiles_mstatus_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_109 = cmm_stage__cmm_state_0_is_csrr_illegal_T_68 ? cmm_stage_csrfiles_misa
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_110 = cmm_stage__cmm_state_0_is_csrr_illegal_T_70 ?
    cmm_stage_csrfiles_medeleg : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_111 = cmm_stage__cmm_state_0_is_csrr_illegal_T_72 ?
    cmm_stage_csrfiles_mideleg : 64'h0; // @[Mux.scala 27:73]
  wire [15:0] cmm_stage__io_csr_data_bits_T_112 = cmm_stage__cmm_state_0_is_csrr_illegal_T_74 ?
    cmm_stage__csr_state_0_csrfiles_mie_T : 16'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_113 = cmm_stage__cmm_state_0_is_csrr_illegal_T_76 ?
    cmm_stage__csr_state_0_csrfiles_mtvec_T : 64'h0; // @[Mux.scala 27:73]
  wire [31:0] cmm_stage__io_csr_data_bits_T_114 = cmm_stage__cmm_state_0_is_csrr_illegal_T_78 ?
    cmm_stage_csrfiles_mcounteren_hpm : 32'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_115 = cmm_stage__cmm_state_0_is_csrr_illegal_T_80 ?
    cmm_stage_csrfiles_mscratch : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_116 = cmm_stage__cmm_state_0_is_csrr_illegal_T_82 ? cmm_stage_csrfiles_mepc
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_117 = cmm_stage__cmm_state_0_is_csrr_illegal_T_84 ?
    cmm_stage__csr_state_0_csrfiles_mcause_T : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_118 = cmm_stage__cmm_state_0_is_csrr_illegal_T_86 ? cmm_stage_csrfiles_mtval
     : 64'h0; // @[Mux.scala 27:73]
  wire [15:0] cmm_stage__io_csr_data_bits_T_119 = cmm_stage__cmm_state_0_is_csrr_illegal_T_88 ?
    cmm_stage__io_csr_data_bits_T_49 : 16'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_120 = cmm_stage__cmm_state_0_is_csrr_illegal_T_90 ?
    cmm_stage_csrfiles_mtinst : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_121 = cmm_stage__cmm_state_0_is_csrr_illegal_T_92 ?
    cmm_stage_csrfiles_mtval2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_122 = cmm_stage__cmm_state_0_is_csrr_illegal_T_94 ?
    cmm_stage_csrfiles_mcycle : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_123 = cmm_stage__cmm_state_0_is_csrr_illegal_T_100 ?
    cmm_stage_csrfiles_minstret : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_125 = cmm_stage__cmm_state_0_is_csrr_illegal_T_108 ?
    cmm_stage_csrfiles_tselect : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_126 = cmm_stage__cmm_state_0_is_csrr_illegal_T_110 ?
    cmm_stage_csrfiles_tdata1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_127 = cmm_stage__cmm_state_0_is_csrr_illegal_T_112 ?
    cmm_stage_csrfiles_tdata2 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_128 = cmm_stage__cmm_state_0_is_csrr_illegal_T_114 ?
    cmm_stage_csrfiles_tdata3 : 64'h0; // @[Mux.scala 27:73]
  wire [31:0] cmm_stage__io_csr_data_bits_T_129 = cmm_stage__cmm_state_0_is_csrr_illegal_T_116 ?
    cmm_stage__csr_state_0_csrfiles_dcsr_T : 32'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_130 = cmm_stage__cmm_state_0_is_csrr_illegal_T_117 ? cmm_stage_csrfiles_dpc
     : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_131 = cmm_stage__cmm_state_0_is_csrr_illegal_T_118 ?
    cmm_stage_csrfiles_dscratch0 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_132 = cmm_stage__cmm_state_0_is_csrr_illegal_T_119 ?
    cmm_stage_csrfiles_dscratch1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_133 = cmm_stage__io_csr_data_bits_T_87 ? cmm_stage_csrfiles_dscratch2 : 64'h0
    ; // @[Mux.scala 27:73]
  wire [4:0] _GEN_501 = {{2'd0}, cmm_stage__io_csr_data_bits_T_89}; // @[Mux.scala 27:73]
  wire [4:0] cmm_stage__io_csr_data_bits_T_134 = cmm_stage__io_csr_data_bits_T_88 | _GEN_501; // @[Mux.scala 27:73]
  wire [7:0] _GEN_502 = {{3'd0}, cmm_stage__io_csr_data_bits_T_134}; // @[Mux.scala 27:73]
  wire [7:0] cmm_stage__io_csr_data_bits_T_135 = _GEN_502 | cmm_stage__io_csr_data_bits_T_90; // @[Mux.scala 27:73]
  wire [63:0] _GEN_503 = {{56'd0}, cmm_stage__io_csr_data_bits_T_135}; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_136 = _GEN_503 | cmm_stage__io_csr_data_bits_T_91; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_137 = cmm_stage__io_csr_data_bits_T_136 | cmm_stage__io_csr_data_bits_T_92; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_138 = cmm_stage__io_csr_data_bits_T_137 | cmm_stage__io_csr_data_bits_T_93; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_139 = cmm_stage__io_csr_data_bits_T_138 | cmm_stage__io_csr_data_bits_T_94; // @[Mux.scala 27:73]
  wire [63:0] _GEN_504 = {{48'd0}, cmm_stage__io_csr_data_bits_T_95}; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_140 = cmm_stage__io_csr_data_bits_T_139 | _GEN_504; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_141 = cmm_stage__io_csr_data_bits_T_140 | cmm_stage__io_csr_data_bits_T_96; // @[Mux.scala 27:73]
  wire [63:0] _GEN_505 = {{32'd0}, cmm_stage__io_csr_data_bits_T_97}; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_142 = cmm_stage__io_csr_data_bits_T_141 | _GEN_505; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_143 = cmm_stage__io_csr_data_bits_T_142 | cmm_stage__io_csr_data_bits_T_98; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_144 = cmm_stage__io_csr_data_bits_T_143 | cmm_stage__io_csr_data_bits_T_99; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_145 = cmm_stage__io_csr_data_bits_T_144 | cmm_stage__io_csr_data_bits_T_100; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_146 = cmm_stage__io_csr_data_bits_T_145 | cmm_stage__io_csr_data_bits_T_101; // @[Mux.scala 27:73]
  wire [63:0] _GEN_506 = {{48'd0}, cmm_stage__io_csr_data_bits_T_102}; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_147 = cmm_stage__io_csr_data_bits_T_146 | _GEN_506; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_148 = cmm_stage__io_csr_data_bits_T_147 | cmm_stage__io_csr_data_bits_T_103; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_150 = cmm_stage__io_csr_data_bits_T_148 | cmm_stage__io_csr_data_bits_T_105; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_153 = cmm_stage__io_csr_data_bits_T_150 | cmm_stage__io_csr_data_bits_T_108; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_154 = cmm_stage__io_csr_data_bits_T_153 | cmm_stage__io_csr_data_bits_T_109; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_155 = cmm_stage__io_csr_data_bits_T_154 | cmm_stage__io_csr_data_bits_T_110; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_156 = cmm_stage__io_csr_data_bits_T_155 | cmm_stage__io_csr_data_bits_T_111; // @[Mux.scala 27:73]
  wire [63:0] _GEN_507 = {{48'd0}, cmm_stage__io_csr_data_bits_T_112}; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_157 = cmm_stage__io_csr_data_bits_T_156 | _GEN_507; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_158 = cmm_stage__io_csr_data_bits_T_157 | cmm_stage__io_csr_data_bits_T_113; // @[Mux.scala 27:73]
  wire [63:0] _GEN_508 = {{32'd0}, cmm_stage__io_csr_data_bits_T_114}; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_159 = cmm_stage__io_csr_data_bits_T_158 | _GEN_508; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_160 = cmm_stage__io_csr_data_bits_T_159 | cmm_stage__io_csr_data_bits_T_115; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_161 = cmm_stage__io_csr_data_bits_T_160 | cmm_stage__io_csr_data_bits_T_116; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_162 = cmm_stage__io_csr_data_bits_T_161 | cmm_stage__io_csr_data_bits_T_117; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_163 = cmm_stage__io_csr_data_bits_T_162 | cmm_stage__io_csr_data_bits_T_118; // @[Mux.scala 27:73]
  wire [63:0] _GEN_509 = {{48'd0}, cmm_stage__io_csr_data_bits_T_119}; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_164 = cmm_stage__io_csr_data_bits_T_163 | _GEN_509; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_165 = cmm_stage__io_csr_data_bits_T_164 | cmm_stage__io_csr_data_bits_T_120; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_166 = cmm_stage__io_csr_data_bits_T_165 | cmm_stage__io_csr_data_bits_T_121; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_167 = cmm_stage__io_csr_data_bits_T_166 | cmm_stage__io_csr_data_bits_T_122; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_168 = cmm_stage__io_csr_data_bits_T_167 | cmm_stage__io_csr_data_bits_T_123; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_170 = cmm_stage__io_csr_data_bits_T_168 | cmm_stage__io_csr_data_bits_T_125; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_171 = cmm_stage__io_csr_data_bits_T_170 | cmm_stage__io_csr_data_bits_T_126; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_172 = cmm_stage__io_csr_data_bits_T_171 | cmm_stage__io_csr_data_bits_T_127; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_173 = cmm_stage__io_csr_data_bits_T_172 | cmm_stage__io_csr_data_bits_T_128; // @[Mux.scala 27:73]
  wire [63:0] _GEN_510 = {{32'd0}, cmm_stage__io_csr_data_bits_T_129}; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_174 = cmm_stage__io_csr_data_bits_T_173 | _GEN_510; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_175 = cmm_stage__io_csr_data_bits_T_174 | cmm_stage__io_csr_data_bits_T_130; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_176 = cmm_stage__io_csr_data_bits_T_175 | cmm_stage__io_csr_data_bits_T_131; // @[Mux.scala 27:73]
  wire [63:0] cmm_stage__io_csr_data_bits_T_177 = cmm_stage__io_csr_data_bits_T_176 | cmm_stage__io_csr_data_bits_T_132; // @[Mux.scala 27:73]
  wire  cmm_stage__io_csr_data_valid_T_121 = ~cmm_stage__cmm_state_0_is_csrr_illegal_T_120; // @[Commit.scala 798:44]
  wire  cmm_stage__T_88 = cmm_stage_csrExe_mdl_io_deq_0_ready & cmm_stage__T_23; // @[Commit.scala 803:31]
  wire  cmm_stage__T_89 = ~cmm_stage__T_88; // @[Commit.scala 803:13]
  wire  cmm_stage__T_92 = ~cmm_stage__T_89; // @[Commit.scala 803:11]
  wire  cmm_stage__T_94 = cmm_stage_fcsrExe_mdl_io_deq_0_ready & cmm_stage__T_25; // @[Commit.scala 814:32]
  wire  cmm_stage__T_95 = ~cmm_stage__T_94; // @[Commit.scala 814:13]
  wire  cmm_stage__T_98 = ~cmm_stage__T_95; // @[Commit.scala 814:11]
  wire  i_mmu_clock;
  wire  i_mmu_reset;
  wire  i_mmu_io_if_mmu_ready;
  wire  i_mmu_io_if_mmu_valid;
  wire  i_mmu_io_if_mmu_bits_is_X;
  wire [63:0] i_mmu_io_if_mmu_bits_vaddr;
  wire  i_mmu_io_mmu_if_ready;
  wire  i_mmu_io_mmu_if_valid;
  wire [63:0] i_mmu_io_mmu_if_bits_vaddr;
  wire [63:0] i_mmu_io_mmu_if_bits_paddr;
  wire  i_mmu_io_mmu_if_bits_is_paging_fault;
  wire  i_mmu_io_mmu_if_bits_is_access_fault;
  wire  i_mmu_io_if_flush;
  wire  i_mmu_io_lsu_mmu_ready;
  wire  i_mmu_io_lsu_mmu_valid;
  wire  i_mmu_io_lsu_mmu_bits_is_X;
  wire  i_mmu_io_lsu_mmu_bits_is_W;
  wire  i_mmu_io_lsu_mmu_bits_is_R;
  wire [63:0] i_mmu_io_lsu_mmu_bits_vaddr;
  wire  i_mmu_io_mmu_lsu_ready;
  wire  i_mmu_io_mmu_lsu_valid;
  wire [63:0] i_mmu_io_mmu_lsu_bits_paddr;
  wire  i_mmu_io_mmu_lsu_bits_is_paging_fault;
  wire  i_mmu_io_mmu_lsu_bits_is_access_fault;
  wire  i_mmu_io_lsu_flush;
  wire [63:0] i_mmu_io_cmm_mmu_satp;
  wire [1:0] i_mmu_io_cmm_mmu_priv_lvl_if;
  wire [1:0] i_mmu_io_cmm_mmu_priv_lvl_ls;
  wire [63:0] i_mmu_io_cmm_mmu_mstatus;
  wire [63:0] i_mmu_io_cmm_mmu_sstatus;
  wire  i_mmu_io_cmm_mmu_sfence_vma;
  wire  i_mmu_io_ptw_get_ready;
  wire  i_mmu_io_ptw_get_valid;
  wire [2:0] i_mmu_io_ptw_get_bits_opcode;
  wire [2:0] i_mmu_io_ptw_get_bits_param;
  wire [2:0] i_mmu_io_ptw_get_bits_size;
  wire  i_mmu_io_ptw_get_bits_source;
  wire [31:0] i_mmu_io_ptw_get_bits_address;
  wire [7:0] i_mmu_io_ptw_get_bits_mask;
  wire [63:0] i_mmu_io_ptw_get_bits_data;
  wire  i_mmu_io_ptw_get_bits_corrupt;
  wire  i_mmu_io_ptw_access_ready;
  wire  i_mmu_io_ptw_access_valid;
  wire [2:0] i_mmu_io_ptw_access_bits_opcode;
  wire [2:0] i_mmu_io_ptw_access_bits_size;
  wire  i_mmu_io_ptw_access_bits_source;
  wire [63:0] i_mmu_io_ptw_access_bits_data;
  wire  i_mmu_itlb_clock;
  wire  i_mmu_itlb_reset;
  wire  i_mmu_itlb_io_req_valid;
  wire [63:0] i_mmu_itlb_io_req_bits_vaddr;
  wire [63:0] i_mmu_itlb_io_pte_o_value;
  wire  i_mmu_itlb_io_pte_o_is_giga_page;
  wire  i_mmu_itlb_io_pte_o_is_mega_page;
  wire  i_mmu_itlb_io_is_hit;
  wire [15:0] i_mmu_itlb_io_asid_i;
  wire  i_mmu_itlb_io_tlb_renew_valid;
  wire [63:0] i_mmu_itlb_io_tlb_renew_bits_value;
  wire  i_mmu_itlb_io_tlb_renew_bits_is_giga_page;
  wire  i_mmu_itlb_io_tlb_renew_bits_is_mega_page;
  wire [15:0] i_mmu_itlb_io_tlb_renew_bits_asid;
  wire [8:0] i_mmu_itlb_io_tlb_renew_bits_vpn_0;
  wire [8:0] i_mmu_itlb_io_tlb_renew_bits_vpn_1;
  wire [8:0] i_mmu_itlb_io_tlb_renew_bits_vpn_2;
  wire  i_mmu_itlb_io_sfence_vma;
  wire  i_mmu_itlb_random_idx_prng_clock;
  wire  i_mmu_itlb_random_idx_prng_reset;
  wire  i_mmu_itlb_random_idx_prng_io_out_0;
  wire  i_mmu_itlb_random_idx_prng_io_out_1;
  reg  i_mmu_itlb_random_idx_prng_state_0; // @[PRNG.scala 55:49]
  reg  i_mmu_itlb_random_idx_prng_state_1; // @[PRNG.scala 55:49]
  wire  i_mmu_itlb_random_idx_prng__T = i_mmu_itlb_random_idx_prng_state_1 ^ i_mmu_itlb_random_idx_prng_state_0; // @[LFSR.scala 15:41]
  wire  i_mmu_itlb_random_idx_prng_1_clock;
  wire  i_mmu_itlb_random_idx_prng_1_reset;
  wire  i_mmu_itlb_random_idx_prng_1_io_out_0;
  wire  i_mmu_itlb_random_idx_prng_1_io_out_1;
  reg  i_mmu_itlb_random_idx_prng_1_state_0; // @[PRNG.scala 55:49]
  reg  i_mmu_itlb_random_idx_prng_1_state_1; // @[PRNG.scala 55:49]
  wire  i_mmu_itlb_random_idx_prng_1__T = i_mmu_itlb_random_idx_prng_1_state_1 ^ i_mmu_itlb_random_idx_prng_1_state_0; // @[LFSR.scala 15:41]
  wire  i_mmu_itlb_random_idx_prng_2_clock;
  wire  i_mmu_itlb_random_idx_prng_2_reset;
  wire  i_mmu_itlb_random_idx_prng_2_io_out_0;
  wire  i_mmu_itlb_random_idx_prng_2_io_out_1;
  reg  i_mmu_itlb_random_idx_prng_2_state_0; // @[PRNG.scala 55:49]
  reg  i_mmu_itlb_random_idx_prng_2_state_1; // @[PRNG.scala 55:49]
  wire  i_mmu_itlb_random_idx_prng_2__T = i_mmu_itlb_random_idx_prng_2_state_1 ^ i_mmu_itlb_random_idx_prng_2_state_0; // @[LFSR.scala 15:41]
  wire  i_mmu_itlb_random_idx_prng_3_clock;
  wire  i_mmu_itlb_random_idx_prng_3_reset;
  wire  i_mmu_itlb_random_idx_prng_3_io_out_0;
  wire  i_mmu_itlb_random_idx_prng_3_io_out_1;
  reg  i_mmu_itlb_random_idx_prng_3_state_0; // @[PRNG.scala 55:49]
  reg  i_mmu_itlb_random_idx_prng_3_state_1; // @[PRNG.scala 55:49]
  wire  i_mmu_itlb_random_idx_prng_3__T = i_mmu_itlb_random_idx_prng_3_state_1 ^ i_mmu_itlb_random_idx_prng_3_state_0; // @[LFSR.scala 15:41]
  reg  i_mmu_itlb_tag_0_is_valid; // @[TLB.scala 59:20]
  reg [15:0] i_mmu_itlb_tag_0_asid; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_itlb_tag_0_vpn_0; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_itlb_tag_0_vpn_1; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_itlb_tag_0_vpn_2; // @[TLB.scala 59:20]
  reg  i_mmu_itlb_tag_1_is_valid; // @[TLB.scala 59:20]
  reg [15:0] i_mmu_itlb_tag_1_asid; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_itlb_tag_1_vpn_0; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_itlb_tag_1_vpn_1; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_itlb_tag_1_vpn_2; // @[TLB.scala 59:20]
  reg [63:0] i_mmu_itlb_pte_0_value; // @[TLB.scala 62:20]
  reg  i_mmu_itlb_pte_0_is_giga_page; // @[TLB.scala 62:20]
  reg  i_mmu_itlb_pte_0_is_mega_page; // @[TLB.scala 62:20]
  reg [63:0] i_mmu_itlb_pte_1_value; // @[TLB.scala 62:20]
  reg  i_mmu_itlb_pte_1_is_giga_page; // @[TLB.scala 62:20]
  reg  i_mmu_itlb_pte_1_is_mega_page; // @[TLB.scala 62:20]
  wire  i_mmu_itlb_is_runout = i_mmu_itlb_tag_0_is_valid & i_mmu_itlb_tag_1_is_valid; // @[TLB.scala 85:31]
  wire [1:0] i_mmu_itlb_random_idx = {i_mmu_itlb_random_idx_prng_io_out_1,i_mmu_itlb_random_idx_prng_io_out_0}; // @[PRNG.scala 95:17]
  wire  i_mmu_itlb__empty_idx_T = ~i_mmu_itlb_tag_0_is_valid; // @[TLB.scala 88:70]
  wire  i_mmu_itlb_empty_idx = i_mmu_itlb__empty_idx_T ? 1'h0 : 1'h1; // @[TLB.scala 88:36]
  wire [1:0] i_mmu_itlb__T = i_mmu_itlb_is_runout ? i_mmu_itlb_random_idx : {{1'd0}, i_mmu_itlb_empty_idx}; // @[TLB.scala 90:15]
  wire  i_mmu_itlb__T_1 = i_mmu_itlb__T[0];
  wire  i_mmu_itlb__GEN_0 = ~i_mmu_itlb__T_1 | i_mmu_itlb_tag_0_is_valid; // @[TLB.scala 59:20 68:{34,34}]
  wire  i_mmu_itlb__GEN_1 = i_mmu_itlb__T_1 | i_mmu_itlb_tag_1_is_valid; // @[TLB.scala 59:20 68:{34,34}]
  wire [1:0] i_mmu_itlb_random_idx_1 = {i_mmu_itlb_random_idx_prng_1_io_out_1,i_mmu_itlb_random_idx_prng_1_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] i_mmu_itlb__T_2 = i_mmu_itlb_is_runout ? i_mmu_itlb_random_idx_1 : {{1'd0}, i_mmu_itlb_empty_idx}; // @[TLB.scala 90:15]
  wire  i_mmu_itlb__T_3 = i_mmu_itlb__T_2[0];
  wire [1:0] i_mmu_itlb_random_idx_2 = {i_mmu_itlb_random_idx_prng_2_io_out_1,i_mmu_itlb_random_idx_prng_2_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] i_mmu_itlb__T_4 = i_mmu_itlb_is_runout ? i_mmu_itlb_random_idx_2 : {{1'd0}, i_mmu_itlb_empty_idx}; // @[TLB.scala 90:15]
  wire  i_mmu_itlb__T_5 = i_mmu_itlb__T_4[0];
  wire [1:0] i_mmu_itlb_random_idx_3 = {i_mmu_itlb_random_idx_prng_3_io_out_1,i_mmu_itlb_random_idx_prng_3_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] i_mmu_itlb__T_6 = i_mmu_itlb_is_runout ? i_mmu_itlb_random_idx_3 : {{1'd0}, i_mmu_itlb_empty_idx}; // @[TLB.scala 90:15]
  wire  i_mmu_itlb__T_7 = i_mmu_itlb__T_6[0];
  wire  i_mmu_itlb__tlb_hit_lvl2_T = i_mmu_itlb_io_asid_i == i_mmu_itlb_tag_0_asid; // @[TLB.scala 102:46]
  wire  i_mmu_itlb__tlb_hit_lvl2_T_1 = i_mmu_itlb_tag_0_is_valid & i_mmu_itlb__tlb_hit_lvl2_T; // @[TLB.scala 102:34]
  wire [8:0] i_mmu_itlb__tlb_hit_lvl2_T_2 = i_mmu_itlb_io_req_bits_vaddr[38:30]; // @[TLB.scala 102:81]
  wire  i_mmu_itlb__tlb_hit_lvl2_T_3 = i_mmu_itlb__tlb_hit_lvl2_T_2 == i_mmu_itlb_tag_0_vpn_2; // @[TLB.scala 102:89]
  wire  i_mmu_itlb_tlb_hit_lvl2 = i_mmu_itlb__tlb_hit_lvl2_T_1 & i_mmu_itlb__tlb_hit_lvl2_T_3; // @[TLB.scala 102:62]
  wire [8:0] i_mmu_itlb__tlb_hit_lvl1_T = i_mmu_itlb_io_req_bits_vaddr[29:21]; // @[TLB.scala 103:35]
  wire  i_mmu_itlb_tlb_hit_lvl1 = i_mmu_itlb__tlb_hit_lvl1_T == i_mmu_itlb_tag_0_vpn_1; // @[TLB.scala 103:43]
  wire [8:0] i_mmu_itlb__tlb_hit_lvl0_T = i_mmu_itlb_io_req_bits_vaddr[20:12]; // @[TLB.scala 104:35]
  wire  i_mmu_itlb_tlb_hit_lvl0 = i_mmu_itlb__tlb_hit_lvl0_T == i_mmu_itlb_tag_0_vpn_0; // @[TLB.scala 104:43]
  wire  i_mmu_itlb__tlb_hit_T = i_mmu_itlb_pte_0_is_mega_page | i_mmu_itlb_tlb_hit_lvl0; // @[TLB.scala 106:68]
  wire  i_mmu_itlb__tlb_hit_T_1 = i_mmu_itlb_tlb_hit_lvl1 & i_mmu_itlb__tlb_hit_T; // @[TLB.scala 106:45]
  wire  i_mmu_itlb__tlb_hit_T_2 = i_mmu_itlb_pte_0_is_giga_page | i_mmu_itlb__tlb_hit_T_1; // @[TLB.scala 106:36]
  wire  i_mmu_itlb__tlb_hit_T_3 = i_mmu_itlb_tlb_hit_lvl2 & i_mmu_itlb__tlb_hit_T_2; // @[TLB.scala 106:12]
  wire  i_mmu_itlb__tlb_hit_lvl2_T_4 = i_mmu_itlb_io_asid_i == i_mmu_itlb_tag_1_asid; // @[TLB.scala 102:46]
  wire  i_mmu_itlb__tlb_hit_lvl2_T_5 = i_mmu_itlb_tag_1_is_valid & i_mmu_itlb__tlb_hit_lvl2_T_4; // @[TLB.scala 102:34]
  wire  i_mmu_itlb__tlb_hit_lvl2_T_7 = i_mmu_itlb__tlb_hit_lvl2_T_2 == i_mmu_itlb_tag_1_vpn_2; // @[TLB.scala 102:89]
  wire  i_mmu_itlb_tlb_hit_lvl2_1 = i_mmu_itlb__tlb_hit_lvl2_T_5 & i_mmu_itlb__tlb_hit_lvl2_T_7; // @[TLB.scala 102:62]
  wire  i_mmu_itlb_tlb_hit_lvl1_1 = i_mmu_itlb__tlb_hit_lvl1_T == i_mmu_itlb_tag_1_vpn_1; // @[TLB.scala 103:43]
  wire  i_mmu_itlb_tlb_hit_lvl0_1 = i_mmu_itlb__tlb_hit_lvl0_T == i_mmu_itlb_tag_1_vpn_0; // @[TLB.scala 104:43]
  wire  i_mmu_itlb__tlb_hit_T_4 = i_mmu_itlb_pte_1_is_mega_page | i_mmu_itlb_tlb_hit_lvl0_1; // @[TLB.scala 106:68]
  wire  i_mmu_itlb__tlb_hit_T_5 = i_mmu_itlb_tlb_hit_lvl1_1 & i_mmu_itlb__tlb_hit_T_4; // @[TLB.scala 106:45]
  wire  i_mmu_itlb__tlb_hit_T_6 = i_mmu_itlb_pte_1_is_giga_page | i_mmu_itlb__tlb_hit_T_5; // @[TLB.scala 106:36]
  wire  i_mmu_itlb__tlb_hit_T_7 = i_mmu_itlb_tlb_hit_lvl2_1 & i_mmu_itlb__tlb_hit_T_6; // @[TLB.scala 106:12]
  wire [1:0] i_mmu_itlb__T_8 = {i_mmu_itlb__tlb_hit_T_7,i_mmu_itlb__tlb_hit_T_3}; // @[TLB.scala 110:29]
  wire  i_mmu_itlb__T_9 = i_mmu_itlb__T_8[0]; // @[Bitwise.scala 53:100]
  wire  i_mmu_itlb__T_10 = i_mmu_itlb__T_8[1]; // @[Bitwise.scala 53:100]
  wire [1:0] i_mmu_itlb__T_11 = i_mmu_itlb__T_9 + i_mmu_itlb__T_10; // @[Bitwise.scala 51:90]
  wire  i_mmu_itlb__T_13 = i_mmu_itlb__T_11 <= 2'h1; // @[TLB.scala 110:38]
  wire  i_mmu_itlb__T_15 = ~i_mmu_itlb_reset; // @[TLB.scala 110:9]
  wire  i_mmu_itlb__T_16 = ~i_mmu_itlb__T_13; // @[TLB.scala 110:9]
  wire  i_mmu_itlb__io_pte_o_T = i_mmu_itlb__tlb_hit_T_3 & i_mmu_itlb_pte_0_is_mega_page; // @[Mux.scala 27:73]
  wire  i_mmu_itlb__io_pte_o_T_1 = i_mmu_itlb__tlb_hit_T_7 & i_mmu_itlb_pte_1_is_mega_page; // @[Mux.scala 27:73]
  wire  i_mmu_itlb__io_pte_o_T_3 = i_mmu_itlb__tlb_hit_T_3 & i_mmu_itlb_pte_0_is_giga_page; // @[Mux.scala 27:73]
  wire  i_mmu_itlb__io_pte_o_T_4 = i_mmu_itlb__tlb_hit_T_7 & i_mmu_itlb_pte_1_is_giga_page; // @[Mux.scala 27:73]
  wire [63:0] i_mmu_itlb__io_pte_o_T_9 = i_mmu_itlb__tlb_hit_T_3 ? i_mmu_itlb_pte_0_value : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] i_mmu_itlb__io_pte_o_T_10 = i_mmu_itlb__tlb_hit_T_7 ? i_mmu_itlb_pte_1_value : 64'h0; // @[Mux.scala 27:73]
  wire  i_mmu_itlb__io_is_hit_T_3 = i_mmu_itlb__tlb_hit_T_3 | i_mmu_itlb__tlb_hit_T_7; // @[TLB.scala 113:32]
  wire  i_mmu_dtlb_clock;
  wire  i_mmu_dtlb_reset;
  wire  i_mmu_dtlb_io_req_valid;
  wire [63:0] i_mmu_dtlb_io_req_bits_vaddr;
  wire [63:0] i_mmu_dtlb_io_pte_o_value;
  wire  i_mmu_dtlb_io_pte_o_is_giga_page;
  wire  i_mmu_dtlb_io_pte_o_is_mega_page;
  wire  i_mmu_dtlb_io_is_hit;
  wire [15:0] i_mmu_dtlb_io_asid_i;
  wire  i_mmu_dtlb_io_tlb_renew_valid;
  wire [63:0] i_mmu_dtlb_io_tlb_renew_bits_value;
  wire  i_mmu_dtlb_io_tlb_renew_bits_is_giga_page;
  wire  i_mmu_dtlb_io_tlb_renew_bits_is_mega_page;
  wire [15:0] i_mmu_dtlb_io_tlb_renew_bits_asid;
  wire [8:0] i_mmu_dtlb_io_tlb_renew_bits_vpn_0;
  wire [8:0] i_mmu_dtlb_io_tlb_renew_bits_vpn_1;
  wire [8:0] i_mmu_dtlb_io_tlb_renew_bits_vpn_2;
  wire  i_mmu_dtlb_io_sfence_vma;
  wire  i_mmu_dtlb_random_idx_prng_clock;
  wire  i_mmu_dtlb_random_idx_prng_reset;
  wire  i_mmu_dtlb_random_idx_prng_io_out_0;
  wire  i_mmu_dtlb_random_idx_prng_io_out_1;
  reg  i_mmu_dtlb_random_idx_prng_state_0; // @[PRNG.scala 55:49]
  reg  i_mmu_dtlb_random_idx_prng_state_1; // @[PRNG.scala 55:49]
  wire  i_mmu_dtlb_random_idx_prng__T = i_mmu_dtlb_random_idx_prng_state_1 ^ i_mmu_dtlb_random_idx_prng_state_0; // @[LFSR.scala 15:41]
  wire  i_mmu_dtlb_random_idx_prng_1_clock;
  wire  i_mmu_dtlb_random_idx_prng_1_reset;
  wire  i_mmu_dtlb_random_idx_prng_1_io_out_0;
  wire  i_mmu_dtlb_random_idx_prng_1_io_out_1;
  reg  i_mmu_dtlb_random_idx_prng_1_state_0; // @[PRNG.scala 55:49]
  reg  i_mmu_dtlb_random_idx_prng_1_state_1; // @[PRNG.scala 55:49]
  wire  i_mmu_dtlb_random_idx_prng_1__T = i_mmu_dtlb_random_idx_prng_1_state_1 ^ i_mmu_dtlb_random_idx_prng_1_state_0; // @[LFSR.scala 15:41]
  wire  i_mmu_dtlb_random_idx_prng_2_clock;
  wire  i_mmu_dtlb_random_idx_prng_2_reset;
  wire  i_mmu_dtlb_random_idx_prng_2_io_out_0;
  wire  i_mmu_dtlb_random_idx_prng_2_io_out_1;
  reg  i_mmu_dtlb_random_idx_prng_2_state_0; // @[PRNG.scala 55:49]
  reg  i_mmu_dtlb_random_idx_prng_2_state_1; // @[PRNG.scala 55:49]
  wire  i_mmu_dtlb_random_idx_prng_2__T = i_mmu_dtlb_random_idx_prng_2_state_1 ^ i_mmu_dtlb_random_idx_prng_2_state_0; // @[LFSR.scala 15:41]
  wire  i_mmu_dtlb_random_idx_prng_3_clock;
  wire  i_mmu_dtlb_random_idx_prng_3_reset;
  wire  i_mmu_dtlb_random_idx_prng_3_io_out_0;
  wire  i_mmu_dtlb_random_idx_prng_3_io_out_1;
  reg  i_mmu_dtlb_random_idx_prng_3_state_0; // @[PRNG.scala 55:49]
  reg  i_mmu_dtlb_random_idx_prng_3_state_1; // @[PRNG.scala 55:49]
  wire  i_mmu_dtlb_random_idx_prng_3__T = i_mmu_dtlb_random_idx_prng_3_state_1 ^ i_mmu_dtlb_random_idx_prng_3_state_0; // @[LFSR.scala 15:41]
  reg  i_mmu_dtlb_tag_0_is_valid; // @[TLB.scala 59:20]
  reg [15:0] i_mmu_dtlb_tag_0_asid; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_dtlb_tag_0_vpn_0; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_dtlb_tag_0_vpn_1; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_dtlb_tag_0_vpn_2; // @[TLB.scala 59:20]
  reg  i_mmu_dtlb_tag_1_is_valid; // @[TLB.scala 59:20]
  reg [15:0] i_mmu_dtlb_tag_1_asid; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_dtlb_tag_1_vpn_0; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_dtlb_tag_1_vpn_1; // @[TLB.scala 59:20]
  reg [8:0] i_mmu_dtlb_tag_1_vpn_2; // @[TLB.scala 59:20]
  reg [63:0] i_mmu_dtlb_pte_0_value; // @[TLB.scala 62:20]
  reg  i_mmu_dtlb_pte_0_is_giga_page; // @[TLB.scala 62:20]
  reg  i_mmu_dtlb_pte_0_is_mega_page; // @[TLB.scala 62:20]
  reg [63:0] i_mmu_dtlb_pte_1_value; // @[TLB.scala 62:20]
  reg  i_mmu_dtlb_pte_1_is_giga_page; // @[TLB.scala 62:20]
  reg  i_mmu_dtlb_pte_1_is_mega_page; // @[TLB.scala 62:20]
  wire  i_mmu_dtlb_is_runout = i_mmu_dtlb_tag_0_is_valid & i_mmu_dtlb_tag_1_is_valid; // @[TLB.scala 85:31]
  wire [1:0] i_mmu_dtlb_random_idx = {i_mmu_dtlb_random_idx_prng_io_out_1,i_mmu_dtlb_random_idx_prng_io_out_0}; // @[PRNG.scala 95:17]
  wire  i_mmu_dtlb__empty_idx_T = ~i_mmu_dtlb_tag_0_is_valid; // @[TLB.scala 88:70]
  wire  i_mmu_dtlb_empty_idx = i_mmu_dtlb__empty_idx_T ? 1'h0 : 1'h1; // @[TLB.scala 88:36]
  wire [1:0] i_mmu_dtlb__T = i_mmu_dtlb_is_runout ? i_mmu_dtlb_random_idx : {{1'd0}, i_mmu_dtlb_empty_idx}; // @[TLB.scala 90:15]
  wire  i_mmu_dtlb__T_1 = i_mmu_dtlb__T[0];
  wire  i_mmu_dtlb__GEN_0 = ~i_mmu_dtlb__T_1 | i_mmu_dtlb_tag_0_is_valid; // @[TLB.scala 59:20 68:{34,34}]
  wire  i_mmu_dtlb__GEN_1 = i_mmu_dtlb__T_1 | i_mmu_dtlb_tag_1_is_valid; // @[TLB.scala 59:20 68:{34,34}]
  wire [1:0] i_mmu_dtlb_random_idx_1 = {i_mmu_dtlb_random_idx_prng_1_io_out_1,i_mmu_dtlb_random_idx_prng_1_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] i_mmu_dtlb__T_2 = i_mmu_dtlb_is_runout ? i_mmu_dtlb_random_idx_1 : {{1'd0}, i_mmu_dtlb_empty_idx}; // @[TLB.scala 90:15]
  wire  i_mmu_dtlb__T_3 = i_mmu_dtlb__T_2[0];
  wire [1:0] i_mmu_dtlb_random_idx_2 = {i_mmu_dtlb_random_idx_prng_2_io_out_1,i_mmu_dtlb_random_idx_prng_2_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] i_mmu_dtlb__T_4 = i_mmu_dtlb_is_runout ? i_mmu_dtlb_random_idx_2 : {{1'd0}, i_mmu_dtlb_empty_idx}; // @[TLB.scala 90:15]
  wire  i_mmu_dtlb__T_5 = i_mmu_dtlb__T_4[0];
  wire [1:0] i_mmu_dtlb_random_idx_3 = {i_mmu_dtlb_random_idx_prng_3_io_out_1,i_mmu_dtlb_random_idx_prng_3_io_out_0}; // @[PRNG.scala 95:17]
  wire [1:0] i_mmu_dtlb__T_6 = i_mmu_dtlb_is_runout ? i_mmu_dtlb_random_idx_3 : {{1'd0}, i_mmu_dtlb_empty_idx}; // @[TLB.scala 90:15]
  wire  i_mmu_dtlb__T_7 = i_mmu_dtlb__T_6[0];
  wire  i_mmu_dtlb__tlb_hit_lvl2_T = i_mmu_dtlb_io_asid_i == i_mmu_dtlb_tag_0_asid; // @[TLB.scala 102:46]
  wire  i_mmu_dtlb__tlb_hit_lvl2_T_1 = i_mmu_dtlb_tag_0_is_valid & i_mmu_dtlb__tlb_hit_lvl2_T; // @[TLB.scala 102:34]
  wire [8:0] i_mmu_dtlb__tlb_hit_lvl2_T_2 = i_mmu_dtlb_io_req_bits_vaddr[38:30]; // @[TLB.scala 102:81]
  wire  i_mmu_dtlb__tlb_hit_lvl2_T_3 = i_mmu_dtlb__tlb_hit_lvl2_T_2 == i_mmu_dtlb_tag_0_vpn_2; // @[TLB.scala 102:89]
  wire  i_mmu_dtlb_tlb_hit_lvl2 = i_mmu_dtlb__tlb_hit_lvl2_T_1 & i_mmu_dtlb__tlb_hit_lvl2_T_3; // @[TLB.scala 102:62]
  wire [8:0] i_mmu_dtlb__tlb_hit_lvl1_T = i_mmu_dtlb_io_req_bits_vaddr[29:21]; // @[TLB.scala 103:35]
  wire  i_mmu_dtlb_tlb_hit_lvl1 = i_mmu_dtlb__tlb_hit_lvl1_T == i_mmu_dtlb_tag_0_vpn_1; // @[TLB.scala 103:43]
  wire [8:0] i_mmu_dtlb__tlb_hit_lvl0_T = i_mmu_dtlb_io_req_bits_vaddr[20:12]; // @[TLB.scala 104:35]
  wire  i_mmu_dtlb_tlb_hit_lvl0 = i_mmu_dtlb__tlb_hit_lvl0_T == i_mmu_dtlb_tag_0_vpn_0; // @[TLB.scala 104:43]
  wire  i_mmu_dtlb__tlb_hit_T = i_mmu_dtlb_pte_0_is_mega_page | i_mmu_dtlb_tlb_hit_lvl0; // @[TLB.scala 106:68]
  wire  i_mmu_dtlb__tlb_hit_T_1 = i_mmu_dtlb_tlb_hit_lvl1 & i_mmu_dtlb__tlb_hit_T; // @[TLB.scala 106:45]
  wire  i_mmu_dtlb__tlb_hit_T_2 = i_mmu_dtlb_pte_0_is_giga_page | i_mmu_dtlb__tlb_hit_T_1; // @[TLB.scala 106:36]
  wire  i_mmu_dtlb__tlb_hit_T_3 = i_mmu_dtlb_tlb_hit_lvl2 & i_mmu_dtlb__tlb_hit_T_2; // @[TLB.scala 106:12]
  wire  i_mmu_dtlb__tlb_hit_lvl2_T_4 = i_mmu_dtlb_io_asid_i == i_mmu_dtlb_tag_1_asid; // @[TLB.scala 102:46]
  wire  i_mmu_dtlb__tlb_hit_lvl2_T_5 = i_mmu_dtlb_tag_1_is_valid & i_mmu_dtlb__tlb_hit_lvl2_T_4; // @[TLB.scala 102:34]
  wire  i_mmu_dtlb__tlb_hit_lvl2_T_7 = i_mmu_dtlb__tlb_hit_lvl2_T_2 == i_mmu_dtlb_tag_1_vpn_2; // @[TLB.scala 102:89]
  wire  i_mmu_dtlb_tlb_hit_lvl2_1 = i_mmu_dtlb__tlb_hit_lvl2_T_5 & i_mmu_dtlb__tlb_hit_lvl2_T_7; // @[TLB.scala 102:62]
  wire  i_mmu_dtlb_tlb_hit_lvl1_1 = i_mmu_dtlb__tlb_hit_lvl1_T == i_mmu_dtlb_tag_1_vpn_1; // @[TLB.scala 103:43]
  wire  i_mmu_dtlb_tlb_hit_lvl0_1 = i_mmu_dtlb__tlb_hit_lvl0_T == i_mmu_dtlb_tag_1_vpn_0; // @[TLB.scala 104:43]
  wire  i_mmu_dtlb__tlb_hit_T_4 = i_mmu_dtlb_pte_1_is_mega_page | i_mmu_dtlb_tlb_hit_lvl0_1; // @[TLB.scala 106:68]
  wire  i_mmu_dtlb__tlb_hit_T_5 = i_mmu_dtlb_tlb_hit_lvl1_1 & i_mmu_dtlb__tlb_hit_T_4; // @[TLB.scala 106:45]
  wire  i_mmu_dtlb__tlb_hit_T_6 = i_mmu_dtlb_pte_1_is_giga_page | i_mmu_dtlb__tlb_hit_T_5; // @[TLB.scala 106:36]
  wire  i_mmu_dtlb__tlb_hit_T_7 = i_mmu_dtlb_tlb_hit_lvl2_1 & i_mmu_dtlb__tlb_hit_T_6; // @[TLB.scala 106:12]
  wire [1:0] i_mmu_dtlb__T_8 = {i_mmu_dtlb__tlb_hit_T_7,i_mmu_dtlb__tlb_hit_T_3}; // @[TLB.scala 110:29]
  wire  i_mmu_dtlb__T_9 = i_mmu_dtlb__T_8[0]; // @[Bitwise.scala 53:100]
  wire  i_mmu_dtlb__T_10 = i_mmu_dtlb__T_8[1]; // @[Bitwise.scala 53:100]
  wire [1:0] i_mmu_dtlb__T_11 = i_mmu_dtlb__T_9 + i_mmu_dtlb__T_10; // @[Bitwise.scala 51:90]
  wire  i_mmu_dtlb__T_13 = i_mmu_dtlb__T_11 <= 2'h1; // @[TLB.scala 110:38]
  wire  i_mmu_dtlb__T_15 = ~i_mmu_dtlb_reset; // @[TLB.scala 110:9]
  wire  i_mmu_dtlb__T_16 = ~i_mmu_dtlb__T_13; // @[TLB.scala 110:9]
  wire  i_mmu_dtlb__io_pte_o_T = i_mmu_dtlb__tlb_hit_T_3 & i_mmu_dtlb_pte_0_is_mega_page; // @[Mux.scala 27:73]
  wire  i_mmu_dtlb__io_pte_o_T_1 = i_mmu_dtlb__tlb_hit_T_7 & i_mmu_dtlb_pte_1_is_mega_page; // @[Mux.scala 27:73]
  wire  i_mmu_dtlb__io_pte_o_T_3 = i_mmu_dtlb__tlb_hit_T_3 & i_mmu_dtlb_pte_0_is_giga_page; // @[Mux.scala 27:73]
  wire  i_mmu_dtlb__io_pte_o_T_4 = i_mmu_dtlb__tlb_hit_T_7 & i_mmu_dtlb_pte_1_is_giga_page; // @[Mux.scala 27:73]
  wire [63:0] i_mmu_dtlb__io_pte_o_T_9 = i_mmu_dtlb__tlb_hit_T_3 ? i_mmu_dtlb_pte_0_value : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] i_mmu_dtlb__io_pte_o_T_10 = i_mmu_dtlb__tlb_hit_T_7 ? i_mmu_dtlb_pte_1_value : 64'h0; // @[Mux.scala 27:73]
  wire  i_mmu_dtlb__io_is_hit_T_3 = i_mmu_dtlb__tlb_hit_T_3 | i_mmu_dtlb__tlb_hit_T_7; // @[TLB.scala 113:32]
  wire  i_mmu_iptw_clock;
  wire  i_mmu_iptw_reset;
  wire  i_mmu_iptw_io_ptw_i_ready;
  wire  i_mmu_iptw_io_ptw_i_valid;
  wire  i_mmu_iptw_io_ptw_i_bits_is_X;
  wire [63:0] i_mmu_iptw_io_ptw_i_bits_vaddr;
  wire  i_mmu_iptw_io_ptw_o_ready;
  wire  i_mmu_iptw_io_ptw_o_valid;
  wire  i_mmu_iptw_io_ptw_o_bits_is_X;
  wire [63:0] i_mmu_iptw_io_ptw_o_bits_renew_value;
  wire  i_mmu_iptw_io_ptw_o_bits_renew_is_giga_page;
  wire  i_mmu_iptw_io_ptw_o_bits_renew_is_mega_page;
  wire [15:0] i_mmu_iptw_io_ptw_o_bits_renew_asid;
  wire [8:0] i_mmu_iptw_io_ptw_o_bits_renew_vpn_0;
  wire [8:0] i_mmu_iptw_io_ptw_o_bits_renew_vpn_1;
  wire [8:0] i_mmu_iptw_io_ptw_o_bits_renew_vpn_2;
  wire  i_mmu_iptw_io_ptw_o_bits_is_ptw_fail;
  wire  i_mmu_iptw_io_ptw_o_bits_is_access_fault;
  wire [63:0] i_mmu_iptw_io_cmm_mmu_satp;
  wire  i_mmu_iptw_io_cmm_mmu_sfence_vma;
  wire  i_mmu_iptw_io_ptw_get_ready;
  wire  i_mmu_iptw_io_ptw_get_valid;
  wire [2:0] i_mmu_iptw_io_ptw_get_bits_opcode;
  wire [2:0] i_mmu_iptw_io_ptw_get_bits_param;
  wire [2:0] i_mmu_iptw_io_ptw_get_bits_size;
  wire  i_mmu_iptw_io_ptw_get_bits_source;
  wire [31:0] i_mmu_iptw_io_ptw_get_bits_address;
  wire [7:0] i_mmu_iptw_io_ptw_get_bits_mask;
  wire [63:0] i_mmu_iptw_io_ptw_get_bits_data;
  wire  i_mmu_iptw_io_ptw_get_bits_corrupt;
  wire  i_mmu_iptw_io_ptw_access_ready;
  wire  i_mmu_iptw_io_ptw_access_valid;
  wire [2:0] i_mmu_iptw_io_ptw_access_bits_opcode;
  wire [2:0] i_mmu_iptw_io_ptw_access_bits_size;
  wire [63:0] i_mmu_iptw_io_ptw_access_bits_data;
  wire  i_mmu_iptw_walkRspBits_is_access_fault_mdl_io_is_fault;
  reg [1:0] i_mmu_iptw_currState; // @[PTW.scala 87:26]
  reg  i_mmu_iptw_kill_trans; // @[PTW.scala 89:27]
  wire  i_mmu_iptw__T = i_mmu_iptw_io_ptw_access_ready & i_mmu_iptw_io_ptw_access_valid; // @[Decoupled.scala 52:35]
  wire [10:0] i_mmu_iptw__beats1_decode_T_1 = 11'hf << i_mmu_iptw_io_ptw_access_bits_size; // @[package.scala 234:77]
  wire [3:0] i_mmu_iptw__beats1_decode_T_2 = i_mmu_iptw__beats1_decode_T_1[3:0]; // @[package.scala 234:82]
  wire [3:0] i_mmu_iptw__beats1_decode_T_3 = ~i_mmu_iptw__beats1_decode_T_2; // @[package.scala 234:46]
  wire  i_mmu_iptw_beats1_decode = i_mmu_iptw__beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  i_mmu_iptw_beats1_opdata = i_mmu_iptw_io_ptw_access_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  i_mmu_iptw_beats1 = i_mmu_iptw_beats1_opdata & i_mmu_iptw_beats1_decode; // @[Edges.scala 220:14]
  reg  i_mmu_iptw_counter; // @[Edges.scala 228:27]
  wire  i_mmu_iptw_counter1 = i_mmu_iptw_counter - 1'h1; // @[Edges.scala 229:28]
  wire  i_mmu_iptw_first = ~i_mmu_iptw_counter; // @[Edges.scala 230:25]
  wire  i_mmu_iptw__last_T_1 = ~i_mmu_iptw_beats1; // @[Edges.scala 231:47]
  wire  i_mmu_iptw_last = i_mmu_iptw_counter | i_mmu_iptw__last_T_1; // @[Edges.scala 231:37]
  wire  i_mmu_iptw_is_trans_done = i_mmu_iptw_last & i_mmu_iptw__T; // @[Edges.scala 232:22]
  reg [31:0] i_mmu_iptw_addr_qout; // @[PTW.scala 95:26]
  wire  i_mmu_iptw__walkReq_T = i_mmu_iptw_currState == 2'h0; // @[PTW.scala 102:63]
  wire  i_mmu_iptw__T_1 = 2'h0 == i_mmu_iptw_currState; // @[PTW.scala 110:23]
  wire  i_mmu_iptw__nextState_T = i_mmu_iptw_io_ptw_i_ready & i_mmu_iptw_io_ptw_i_valid; // @[Decoupled.scala 52:35]
  wire [1:0] i_mmu_iptw__nextState_T_1 = i_mmu_iptw__nextState_T ? 2'h1 : 2'h0; // @[PTW.scala 112:23]
  wire  i_mmu_iptw__T_2 = 2'h1 == i_mmu_iptw_currState; // @[PTW.scala 110:23]
  reg [63:0] i_mmu_iptw_ptw_access_data_lo_0; // @[PTW.scala 218:31]
  wire [127:0] i_mmu_iptw_ptw_access_data = {i_mmu_iptw_io_ptw_access_bits_data,i_mmu_iptw_ptw_access_data_lo_0}; // @[Cat.scala 33:92]
  wire [127:0] i_mmu_iptw__GEN_26 = i_mmu_iptw_is_trans_done ? i_mmu_iptw_ptw_access_data : 128'h0; // @[PTW.scala 226:27 227:12]
  wire  i_mmu_iptw__pte_value_data_sel_T = i_mmu_iptw_addr_qout[3]; // @[PTW.scala 231:31]
  wire [6:0] i_mmu_iptw__pte_value_data_sel_T_1 = {i_mmu_iptw__pte_value_data_sel_T, 6'h0}; // @[PTW.scala 231:54]
  wire [127:0] i_mmu_iptw__pte_value_data_sel_T_2 = i_mmu_iptw__GEN_26 >> i_mmu_iptw__pte_value_data_sel_T_1; // @[PTW.scala 230:22]
  wire [63:0] i_mmu_iptw_pte_value_data_sel = i_mmu_iptw__pte_value_data_sel_T_2[63:0]; // @[PTW.scala 224:24 230:14]
  reg [63:0] i_mmu_iptw_pte_value_value; // @[PTW.scala 234:24]
  wire [63:0] i_mmu_iptw__pte_value_T = i_mmu_iptw_is_trans_done ? i_mmu_iptw_pte_value_data_sel :
    i_mmu_iptw_pte_value_value; // @[PTW.scala 240:8]
  wire  i_mmu_iptw__is_ptw_end_T = i_mmu_iptw__pte_value_T[1]; // @[MMU.scala 36:16]
  wire  i_mmu_iptw__is_ptw_end_T_3 = i_mmu_iptw__pte_value_T[3]; // @[MMU.scala 38:16]
  wire  i_mmu_iptw__is_ptw_end_T_6 = i_mmu_iptw__is_ptw_end_T & i_mmu_iptw__is_ptw_end_T_3; // @[PTW.scala 164:22]
  wire  i_mmu_iptw__is_ptw_fail_T_1 = i_mmu_iptw_currState == 2'h1; // @[PTW.scala 172:20]
  wire [8:0] i_mmu_iptw__is_ptw_fail_T_2 = i_mmu_iptw__pte_value_T[18:10]; // @[MMU.scala 44:37]
  wire  i_mmu_iptw__is_ptw_fail_T_5 = i_mmu_iptw__is_ptw_fail_T_2 != 9'h0; // @[PTW.scala 172:57]
  wire [8:0] i_mmu_iptw__is_ptw_fail_T_7 = i_mmu_iptw__pte_value_T[27:19]; // @[MMU.scala 44:51]
  wire  i_mmu_iptw__is_ptw_fail_T_9 = i_mmu_iptw__is_ptw_fail_T_7 != 9'h0; // @[PTW.scala 172:78]
  wire  i_mmu_iptw__is_ptw_fail_T_10 = i_mmu_iptw__is_ptw_fail_T_5 | i_mmu_iptw__is_ptw_fail_T_9; // @[PTW.scala 172:65]
  wire  i_mmu_iptw__is_ptw_fail_T_18 = i_mmu_iptw__is_ptw_fail_T_1 & i_mmu_iptw__is_ptw_fail_T_10; // @[Mux.scala 27:73]
  wire  i_mmu_iptw__is_ptw_fail_T_11 = i_mmu_iptw_currState == 2'h2; // @[PTW.scala 173:20]
  wire  i_mmu_iptw__is_ptw_fail_T_19 = i_mmu_iptw__is_ptw_fail_T_11 & i_mmu_iptw__is_ptw_fail_T_5; // @[Mux.scala 27:73]
  wire  i_mmu_iptw__is_ptw_fail_T_22 = i_mmu_iptw__is_ptw_fail_T_18 | i_mmu_iptw__is_ptw_fail_T_19; // @[Mux.scala 27:73]
  wire  i_mmu_iptw__is_ptw_fail_T_16 = i_mmu_iptw_currState == 2'h3; // @[PTW.scala 174:20]
  wire  i_mmu_iptw__is_ptw_fail_T_24 = i_mmu_iptw__is_ptw_end_T_6 & i_mmu_iptw__is_ptw_fail_T_22; // @[PTW.scala 169:18]
  wire  i_mmu_iptw__is_ptw_fail_T_25 = i_mmu_iptw__pte_value_T[0]; // @[MMU.scala 35:16]
  wire  i_mmu_iptw__is_ptw_fail_T_27 = ~i_mmu_iptw__is_ptw_fail_T_25; // @[PTW.scala 178:14]
  wire  i_mmu_iptw__is_ptw_fail_T_30 = ~i_mmu_iptw__is_ptw_end_T; // @[PTW.scala 179:14]
  wire  i_mmu_iptw__is_ptw_fail_T_31 = i_mmu_iptw__pte_value_T[2]; // @[MMU.scala 37:16]
  wire  i_mmu_iptw__is_ptw_fail_T_34 = i_mmu_iptw__is_ptw_fail_T_30 & i_mmu_iptw__is_ptw_fail_T_31; // @[PTW.scala 179:26]
  wire  i_mmu_iptw__is_ptw_fail_T_35 = i_mmu_iptw__is_ptw_fail_T_27 | i_mmu_iptw__is_ptw_fail_T_34; // @[PTW.scala 178:27]
  wire  i_mmu_iptw__is_ptw_fail_T_36 = i_mmu_iptw__is_ptw_fail_T_24 | i_mmu_iptw__is_ptw_fail_T_35; // @[PTW.scala 176:7]
  wire  i_mmu_iptw__nextState_T_3 = i_mmu_iptw__is_ptw_end_T_6 | i_mmu_iptw__is_ptw_fail_T_36; // @[PTW.scala 118:27]
  wire  i_mmu_iptw__nextState_T_4 = i_mmu_iptw__nextState_T_3 | i_mmu_iptw_kill_trans; // @[PTW.scala 118:41]
  wire [1:0] i_mmu_iptw__nextState_T_5 = i_mmu_iptw__nextState_T_4 ? 2'h0 : 2'h2; // @[PTW.scala 118:14]
  wire [1:0] i_mmu_iptw__nextState_T_6 = i_mmu_iptw_is_trans_done ? i_mmu_iptw__nextState_T_5 : 2'h1; // @[PTW.scala 116:12]
  wire  i_mmu_iptw__T_3 = 2'h2 == i_mmu_iptw_currState; // @[PTW.scala 110:23]
  wire [1:0] i_mmu_iptw__nextState_T_10 = i_mmu_iptw__nextState_T_4 ? 2'h0 : 2'h3; // @[PTW.scala 126:14]
  wire [1:0] i_mmu_iptw__nextState_T_11 = i_mmu_iptw_is_trans_done ? i_mmu_iptw__nextState_T_10 : 2'h2; // @[PTW.scala 124:12]
  wire  i_mmu_iptw__T_4 = 2'h3 == i_mmu_iptw_currState; // @[PTW.scala 110:23]
  wire [1:0] i_mmu_iptw__nextState_T_16 = i_mmu_iptw_is_trans_done ? 2'h0 : 2'h3; // @[PTW.scala 132:12]
  wire [1:0] i_mmu_iptw__GEN_6 = i_mmu_iptw__T_4 ? i_mmu_iptw__nextState_T_16 : 2'h0; // @[PTW.scala 110:23 131:17]
  wire [1:0] i_mmu_iptw__GEN_7 = i_mmu_iptw__T_3 ? i_mmu_iptw__nextState_T_11 : i_mmu_iptw__GEN_6; // @[PTW.scala 110:23 123:17]
  wire [1:0] i_mmu_iptw__GEN_8 = i_mmu_iptw__T_2 ? i_mmu_iptw__nextState_T_6 : i_mmu_iptw__GEN_7; // @[PTW.scala 110:23 115:17]
  wire [1:0] i_mmu_iptw__GEN_9 = i_mmu_iptw__T_1 ? i_mmu_iptw__nextState_T_1 : i_mmu_iptw__GEN_8; // @[PTW.scala 110:23 112:17]
  wire  i_mmu_iptw__walkReq_T_1 = i_mmu_iptw__GEN_9 != 2'h0; // @[PTW.scala 102:95]
  wire  i_mmu_iptw__walkReq_T_2 = i_mmu_iptw__walkReq_T & i_mmu_iptw__walkReq_T_1; // @[PTW.scala 102:83]
  reg  i_mmu_iptw_walkReq_is_X; // @[Reg.scala 19:16]
  reg [63:0] i_mmu_iptw_walkReq_vaddr; // @[Reg.scala 19:16]
  wire [15:0] i_mmu_iptw__asidReq_T = i_mmu_iptw_io_cmm_mmu_satp[59:44]; // @[PTW.scala 103:43]
  reg [15:0] i_mmu_iptw_asidReq; // @[Reg.scala 19:16]
  reg  i_mmu_iptw_walkRspBits_is_X; // @[PTW.scala 104:28]
  reg [63:0] i_mmu_iptw_walkRspBits_renew_value; // @[PTW.scala 104:28]
  reg  i_mmu_iptw_walkRspBits_renew_is_giga_page; // @[PTW.scala 104:28]
  reg  i_mmu_iptw_walkRspBits_renew_is_mega_page; // @[PTW.scala 104:28]
  reg [15:0] i_mmu_iptw_walkRspBits_renew_asid; // @[PTW.scala 104:28]
  reg [8:0] i_mmu_iptw_walkRspBits_renew_vpn_0; // @[PTW.scala 104:28]
  reg [8:0] i_mmu_iptw_walkRspBits_renew_vpn_1; // @[PTW.scala 104:28]
  reg [8:0] i_mmu_iptw_walkRspBits_renew_vpn_2; // @[PTW.scala 104:28]
  reg  i_mmu_iptw_walkRspBits_is_ptw_fail; // @[PTW.scala 104:28]
  reg  i_mmu_iptw_walkRspBits_is_access_fault; // @[PTW.scala 104:28]
  reg  i_mmu_iptw_walkRspValid; // @[PTW.scala 105:29]
  wire  i_mmu_iptw__a_T = i_mmu_iptw__GEN_9 == 2'h1; // @[PTW.scala 148:19]
  wire [43:0] i_mmu_iptw__a_T_1 = i_mmu_iptw_io_cmm_mmu_satp[43:0]; // @[PTW.scala 148:59]
  wire  i_mmu_iptw__a_T_2 = i_mmu_iptw__GEN_9 == 2'h2; // @[PTW.scala 149:19]
  wire [25:0] i_mmu_iptw__a_T_5 = i_mmu_iptw__pte_value_T[53:28]; // @[MMU.scala 44:65]
  wire [43:0] i_mmu_iptw__a_T_12 = {i_mmu_iptw__a_T_5,i_mmu_iptw__is_ptw_fail_T_7,i_mmu_iptw__is_ptw_fail_T_2}; // @[Cat.scala 33:92]
  wire  i_mmu_iptw__a_T_13 = i_mmu_iptw__GEN_9 == 2'h3; // @[PTW.scala 150:19]
  wire [43:0] i_mmu_iptw__a_T_24 = i_mmu_iptw__a_T ? i_mmu_iptw__a_T_1 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] i_mmu_iptw__a_T_25 = i_mmu_iptw__a_T_2 ? i_mmu_iptw__a_T_12 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] i_mmu_iptw__a_T_26 = i_mmu_iptw__a_T_13 ? i_mmu_iptw__a_T_12 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] i_mmu_iptw__a_T_27 = i_mmu_iptw__a_T_24 | i_mmu_iptw__a_T_25; // @[Mux.scala 27:73]
  wire [43:0] i_mmu_iptw__a_T_28 = i_mmu_iptw__a_T_27 | i_mmu_iptw__a_T_26; // @[Mux.scala 27:73]
  wire [8:0] i_mmu_iptw__addr_dnxt_T_1 = i_mmu_iptw_io_ptw_i_bits_vaddr[38:30]; // @[PTW.scala 155:66]
  wire [11:0] i_mmu_iptw__addr_dnxt_T_2 = {i_mmu_iptw__addr_dnxt_T_1,3'h0}; // @[Cat.scala 33:92]
  wire [8:0] i_mmu_iptw__addr_dnxt_T_4 = i_mmu_iptw_walkReq_vaddr[29:21]; // @[PTW.scala 156:60]
  wire [11:0] i_mmu_iptw__addr_dnxt_T_5 = {i_mmu_iptw__addr_dnxt_T_4,3'h0}; // @[Cat.scala 33:92]
  wire [8:0] i_mmu_iptw__addr_dnxt_T_7 = i_mmu_iptw_walkReq_vaddr[20:12]; // @[PTW.scala 157:60]
  wire [11:0] i_mmu_iptw__addr_dnxt_T_8 = {i_mmu_iptw__addr_dnxt_T_7,3'h0}; // @[Cat.scala 33:92]
  wire [11:0] i_mmu_iptw__addr_dnxt_T_9 = i_mmu_iptw__a_T ? i_mmu_iptw__addr_dnxt_T_2 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] i_mmu_iptw__addr_dnxt_T_10 = i_mmu_iptw__a_T_2 ? i_mmu_iptw__addr_dnxt_T_5 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] i_mmu_iptw__addr_dnxt_T_11 = i_mmu_iptw__a_T_13 ? i_mmu_iptw__addr_dnxt_T_8 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] i_mmu_iptw__addr_dnxt_T_12 = i_mmu_iptw__addr_dnxt_T_9 | i_mmu_iptw__addr_dnxt_T_10; // @[Mux.scala 27:73]
  wire [11:0] i_mmu_iptw__addr_dnxt_T_13 = i_mmu_iptw__addr_dnxt_T_12 | i_mmu_iptw__addr_dnxt_T_11; // @[Mux.scala 27:73]
  wire [55:0] i_mmu_iptw__addr_dnxt_T_14 = {i_mmu_iptw__a_T_28,i_mmu_iptw__addr_dnxt_T_13}; // @[Cat.scala 33:92]
  wire  i_mmu_iptw__pte_is_mega_page_T_1 = i_mmu_iptw__is_ptw_end_T_6 & i_mmu_iptw__is_ptw_fail_T_11; // @[PTW.scala 184:34]
  wire  i_mmu_iptw__pte_is_giga_page_T_1 = i_mmu_iptw__is_ptw_end_T_6 & i_mmu_iptw__is_ptw_fail_T_1; // @[PTW.scala 185:34]
  wire  i_mmu_iptw__T_7 = i_mmu_iptw__walkReq_T & i_mmu_iptw__a_T; // @[PTW.scala 188:39]
  wire  i_mmu_iptw__T_8 = i_mmu_iptw_io_ptw_get_ready & i_mmu_iptw_io_ptw_get_valid; // @[Decoupled.scala 52:35]
  wire  i_mmu_iptw__walkRspBits_is_access_fault_T_1 = i_mmu_iptw_walkRspBits_is_access_fault |
    i_mmu_iptw_walkRspBits_is_access_fault_mdl_io_is_fault; // @[PTW.scala 193:35]
  wire  i_mmu_iptw__T_9 = i_mmu_iptw__GEN_9 == 2'h0; // @[PTW.scala 197:19]
  wire  i_mmu_iptw__T_10 = i_mmu_iptw_currState != 2'h0; // @[PTW.scala 197:51]
  wire  i_mmu_iptw__T_11 = i_mmu_iptw__T_9 & i_mmu_iptw__T_10; // @[PTW.scala 197:39]
  wire [8:0] i_mmu_iptw__walkRspBits_renew_vpn_2_T = i_mmu_iptw_walkReq_vaddr[38:30]; // @[PTW.scala 205:46]
  wire  i_mmu_iptw__T_12 = ~i_mmu_iptw_io_ptw_o_valid; // @[PTW.scala 210:28]
  wire  i_mmu_iptw__T_14 = ~i_mmu_iptw_reset; // @[PTW.scala 210:11]
  wire  i_mmu_iptw__T_15 = ~i_mmu_iptw__T_12; // @[PTW.scala 210:11]
  wire  i_mmu_iptw__T_16 = i_mmu_iptw_io_ptw_o_ready & i_mmu_iptw_io_ptw_o_valid; // @[Decoupled.scala 52:35]
  wire  i_mmu_iptw__GEN_12 = i_mmu_iptw__T_16 ? 1'h0 : i_mmu_iptw_walkRspValid; // @[PTW.scala 211:32 212:18 105:29]
  wire  i_mmu_iptw__GEN_25 = i_mmu_iptw__T_11 | i_mmu_iptw__GEN_12; // @[PTW.scala 197:73 208:18]
  wire  i_mmu_iptw__T_18 = ~i_mmu_iptw_is_trans_done; // @[PTW.scala 243:30]
  wire  i_mmu_iptw__T_19 = i_mmu_iptw__T & i_mmu_iptw__T_18; // @[PTW.scala 243:28]
  reg  i_mmu_iptw_ptw_get_valid; // @[PTW.scala 342:30]
  reg  i_mmu_iptw_ptw_access_ready; // @[PTW.scala 343:33]
  reg  i_mmu_iptw_is_get_reqed; // @[PTW.scala 348:29]
  wire  i_mmu_iptw__T_21 = i_mmu_iptw__GEN_9 != i_mmu_iptw_currState; // @[PTW.scala 350:24]
  wire  i_mmu_iptw__GEN_29 = i_mmu_iptw__T_21 ? 1'h0 : i_mmu_iptw_is_get_reqed; // @[PTW.scala 348:29 350:{40,55}]
  wire  i_mmu_iptw__GEN_30 = i_mmu_iptw__T_8 | i_mmu_iptw__GEN_29; // @[PTW.scala 349:{27,42}]
  wire  i_mmu_iptw__T_24 = i_mmu_iptw__is_ptw_fail_T_1 | i_mmu_iptw__is_ptw_fail_T_11; // @[PTW.scala 353:40]
  wire  i_mmu_iptw__T_26 = i_mmu_iptw__T_24 | i_mmu_iptw__is_ptw_fail_T_16; // @[PTW.scala 353:72]
  wire  i_mmu_iptw__T_29 = ~i_mmu_iptw_io_ptw_get_valid; // @[PTW.scala 353:117]
  wire  i_mmu_iptw__T_30 = i_mmu_iptw__T_26 & i_mmu_iptw__T_29; // @[PTW.scala 353:115]
  wire  i_mmu_iptw__T_31 = ~i_mmu_iptw_is_get_reqed; // @[PTW.scala 353:137]
  wire  i_mmu_iptw__T_32 = i_mmu_iptw__T_30 & i_mmu_iptw__T_31; // @[PTW.scala 353:135]
  wire  i_mmu_iptw__GEN_31 = i_mmu_iptw__T_8 ? 1'h0 : i_mmu_iptw_ptw_get_valid; // @[PTW.scala 355:34 356:19 342:30]
  wire  i_mmu_iptw__GEN_32 = i_mmu_iptw__T_32 | i_mmu_iptw__GEN_31; // @[PTW.scala 353:153 354:19]
  wire  i_mmu_iptw__T_34 = ~i_mmu_iptw_io_ptw_access_ready; // @[PTW.scala 359:31]
  wire  i_mmu_iptw__T_35 = i_mmu_iptw_io_ptw_access_valid & i_mmu_iptw__T_34; // @[PTW.scala 359:29]
  wire  i_mmu_iptw__GEN_33 = i_mmu_iptw__T ? 1'h0 : i_mmu_iptw_ptw_access_ready; // @[PTW.scala 361:37 362:22 343:33]
  wire  i_mmu_iptw__GEN_34 = i_mmu_iptw__T_35 | i_mmu_iptw__GEN_33; // @[PTW.scala 359:53 360:22]
  wire [35:0] _GEN_522 = {{4'd0}, i_mmu_iptw_addr_qout}; // @[PTW.scala 365:74]
  wire [35:0] i_mmu_iptw__io_ptw_get_bits_T_1 = _GEN_522 & 36'hffffffff0; // @[PTW.scala 365:74]
  wire  i_mmu_iptw__T_38 = i_mmu_iptw_io_cmm_mmu_sfence_vma & i_mmu_iptw__T_10; // @[PTW.scala 382:31]
  wire  i_mmu_iptw__GEN_35 = i_mmu_iptw__walkReq_T ? 1'h0 : i_mmu_iptw_kill_trans; // @[PTW.scala 384:48 385:16 89:27]
  wire  i_mmu_iptw__GEN_36 = i_mmu_iptw__T_38 | i_mmu_iptw__GEN_35; // @[PTW.scala 382:65 383:16]
  wire  i_mmu_iptw__io_ptw_o_valid_T = ~i_mmu_iptw_kill_trans; // @[PTW.scala 390:36]
  wire  i_mmu_iptw__io_ptw_i_ready_T_2 = i_mmu_iptw__walkReq_T & i_mmu_iptw__T_12; // @[PTW.scala 393:51]
  wire  i_mmu_iptw__io_ptw_i_ready_T_3 = ~i_mmu_iptw_io_cmm_mmu_sfence_vma; // @[PTW.scala 393:71]
  wire  i_mmu_iptw__io_ptw_i_ready_T_4 = i_mmu_iptw__io_ptw_i_ready_T_2 & i_mmu_iptw__io_ptw_i_ready_T_3; // @[PTW.scala 393:69]
  wire [31:0] i_mmu_iptw_addr_dnxt = i_mmu_iptw__addr_dnxt_T_14[31:0]; // @[PTW.scala 153:13 94:23]
  wire  i_mmu_dptw_clock;
  wire  i_mmu_dptw_reset;
  wire  i_mmu_dptw_io_ptw_i_ready;
  wire  i_mmu_dptw_io_ptw_i_valid;
  wire  i_mmu_dptw_io_ptw_i_bits_is_X;
  wire [63:0] i_mmu_dptw_io_ptw_i_bits_vaddr;
  wire  i_mmu_dptw_io_ptw_o_ready;
  wire  i_mmu_dptw_io_ptw_o_valid;
  wire  i_mmu_dptw_io_ptw_o_bits_is_X;
  wire [63:0] i_mmu_dptw_io_ptw_o_bits_renew_value;
  wire  i_mmu_dptw_io_ptw_o_bits_renew_is_giga_page;
  wire  i_mmu_dptw_io_ptw_o_bits_renew_is_mega_page;
  wire [15:0] i_mmu_dptw_io_ptw_o_bits_renew_asid;
  wire [8:0] i_mmu_dptw_io_ptw_o_bits_renew_vpn_0;
  wire [8:0] i_mmu_dptw_io_ptw_o_bits_renew_vpn_1;
  wire [8:0] i_mmu_dptw_io_ptw_o_bits_renew_vpn_2;
  wire  i_mmu_dptw_io_ptw_o_bits_is_ptw_fail;
  wire  i_mmu_dptw_io_ptw_o_bits_is_access_fault;
  wire [63:0] i_mmu_dptw_io_cmm_mmu_satp;
  wire  i_mmu_dptw_io_cmm_mmu_sfence_vma;
  wire  i_mmu_dptw_io_ptw_get_ready;
  wire  i_mmu_dptw_io_ptw_get_valid;
  wire [2:0] i_mmu_dptw_io_ptw_get_bits_opcode;
  wire [2:0] i_mmu_dptw_io_ptw_get_bits_param;
  wire [2:0] i_mmu_dptw_io_ptw_get_bits_size;
  wire  i_mmu_dptw_io_ptw_get_bits_source;
  wire [31:0] i_mmu_dptw_io_ptw_get_bits_address;
  wire [7:0] i_mmu_dptw_io_ptw_get_bits_mask;
  wire [63:0] i_mmu_dptw_io_ptw_get_bits_data;
  wire  i_mmu_dptw_io_ptw_get_bits_corrupt;
  wire  i_mmu_dptw_io_ptw_access_ready;
  wire  i_mmu_dptw_io_ptw_access_valid;
  wire [2:0] i_mmu_dptw_io_ptw_access_bits_opcode;
  wire [2:0] i_mmu_dptw_io_ptw_access_bits_size;
  wire [63:0] i_mmu_dptw_io_ptw_access_bits_data;
  wire  i_mmu_dptw_walkRspBits_is_access_fault_mdl_io_is_fault;
  reg [1:0] i_mmu_dptw_currState; // @[PTW.scala 87:26]
  reg  i_mmu_dptw_kill_trans; // @[PTW.scala 89:27]
  wire  i_mmu_dptw__T = i_mmu_dptw_io_ptw_access_ready & i_mmu_dptw_io_ptw_access_valid; // @[Decoupled.scala 52:35]
  wire [10:0] i_mmu_dptw__beats1_decode_T_1 = 11'hf << i_mmu_dptw_io_ptw_access_bits_size; // @[package.scala 234:77]
  wire [3:0] i_mmu_dptw__beats1_decode_T_2 = i_mmu_dptw__beats1_decode_T_1[3:0]; // @[package.scala 234:82]
  wire [3:0] i_mmu_dptw__beats1_decode_T_3 = ~i_mmu_dptw__beats1_decode_T_2; // @[package.scala 234:46]
  wire  i_mmu_dptw_beats1_decode = i_mmu_dptw__beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  i_mmu_dptw_beats1_opdata = i_mmu_dptw_io_ptw_access_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  i_mmu_dptw_beats1 = i_mmu_dptw_beats1_opdata & i_mmu_dptw_beats1_decode; // @[Edges.scala 220:14]
  reg  i_mmu_dptw_counter; // @[Edges.scala 228:27]
  wire  i_mmu_dptw_counter1 = i_mmu_dptw_counter - 1'h1; // @[Edges.scala 229:28]
  wire  i_mmu_dptw_first = ~i_mmu_dptw_counter; // @[Edges.scala 230:25]
  wire  i_mmu_dptw__last_T_1 = ~i_mmu_dptw_beats1; // @[Edges.scala 231:47]
  wire  i_mmu_dptw_last = i_mmu_dptw_counter | i_mmu_dptw__last_T_1; // @[Edges.scala 231:37]
  wire  i_mmu_dptw_is_trans_done = i_mmu_dptw_last & i_mmu_dptw__T; // @[Edges.scala 232:22]
  reg [31:0] i_mmu_dptw_addr_qout; // @[PTW.scala 95:26]
  wire  i_mmu_dptw__walkReq_T = i_mmu_dptw_currState == 2'h0; // @[PTW.scala 102:63]
  wire  i_mmu_dptw__T_1 = 2'h0 == i_mmu_dptw_currState; // @[PTW.scala 110:23]
  wire  i_mmu_dptw__nextState_T = i_mmu_dptw_io_ptw_i_ready & i_mmu_dptw_io_ptw_i_valid; // @[Decoupled.scala 52:35]
  wire [1:0] i_mmu_dptw__nextState_T_1 = i_mmu_dptw__nextState_T ? 2'h1 : 2'h0; // @[PTW.scala 112:23]
  wire  i_mmu_dptw__T_2 = 2'h1 == i_mmu_dptw_currState; // @[PTW.scala 110:23]
  reg [63:0] i_mmu_dptw_ptw_access_data_lo_0; // @[PTW.scala 218:31]
  wire [127:0] i_mmu_dptw_ptw_access_data = {i_mmu_dptw_io_ptw_access_bits_data,i_mmu_dptw_ptw_access_data_lo_0}; // @[Cat.scala 33:92]
  wire [127:0] i_mmu_dptw__GEN_26 = i_mmu_dptw_is_trans_done ? i_mmu_dptw_ptw_access_data : 128'h0; // @[PTW.scala 226:27 227:12]
  wire  i_mmu_dptw__pte_value_data_sel_T = i_mmu_dptw_addr_qout[3]; // @[PTW.scala 231:31]
  wire [6:0] i_mmu_dptw__pte_value_data_sel_T_1 = {i_mmu_dptw__pte_value_data_sel_T, 6'h0}; // @[PTW.scala 231:54]
  wire [127:0] i_mmu_dptw__pte_value_data_sel_T_2 = i_mmu_dptw__GEN_26 >> i_mmu_dptw__pte_value_data_sel_T_1; // @[PTW.scala 230:22]
  wire [63:0] i_mmu_dptw_pte_value_data_sel = i_mmu_dptw__pte_value_data_sel_T_2[63:0]; // @[PTW.scala 224:24 230:14]
  reg [63:0] i_mmu_dptw_pte_value_value; // @[PTW.scala 234:24]
  wire [63:0] i_mmu_dptw__pte_value_T = i_mmu_dptw_is_trans_done ? i_mmu_dptw_pte_value_data_sel :
    i_mmu_dptw_pte_value_value; // @[PTW.scala 240:8]
  wire  i_mmu_dptw__is_ptw_end_T = i_mmu_dptw__pte_value_T[1]; // @[MMU.scala 36:16]
  wire  i_mmu_dptw__is_ptw_end_T_3 = i_mmu_dptw__pte_value_T[3]; // @[MMU.scala 38:16]
  wire  i_mmu_dptw__is_ptw_end_T_6 = i_mmu_dptw__is_ptw_end_T & i_mmu_dptw__is_ptw_end_T_3; // @[PTW.scala 164:22]
  wire  i_mmu_dptw__is_ptw_fail_T_1 = i_mmu_dptw_currState == 2'h1; // @[PTW.scala 172:20]
  wire [8:0] i_mmu_dptw__is_ptw_fail_T_2 = i_mmu_dptw__pte_value_T[18:10]; // @[MMU.scala 44:37]
  wire  i_mmu_dptw__is_ptw_fail_T_5 = i_mmu_dptw__is_ptw_fail_T_2 != 9'h0; // @[PTW.scala 172:57]
  wire [8:0] i_mmu_dptw__is_ptw_fail_T_7 = i_mmu_dptw__pte_value_T[27:19]; // @[MMU.scala 44:51]
  wire  i_mmu_dptw__is_ptw_fail_T_9 = i_mmu_dptw__is_ptw_fail_T_7 != 9'h0; // @[PTW.scala 172:78]
  wire  i_mmu_dptw__is_ptw_fail_T_10 = i_mmu_dptw__is_ptw_fail_T_5 | i_mmu_dptw__is_ptw_fail_T_9; // @[PTW.scala 172:65]
  wire  i_mmu_dptw__is_ptw_fail_T_18 = i_mmu_dptw__is_ptw_fail_T_1 & i_mmu_dptw__is_ptw_fail_T_10; // @[Mux.scala 27:73]
  wire  i_mmu_dptw__is_ptw_fail_T_11 = i_mmu_dptw_currState == 2'h2; // @[PTW.scala 173:20]
  wire  i_mmu_dptw__is_ptw_fail_T_19 = i_mmu_dptw__is_ptw_fail_T_11 & i_mmu_dptw__is_ptw_fail_T_5; // @[Mux.scala 27:73]
  wire  i_mmu_dptw__is_ptw_fail_T_22 = i_mmu_dptw__is_ptw_fail_T_18 | i_mmu_dptw__is_ptw_fail_T_19; // @[Mux.scala 27:73]
  wire  i_mmu_dptw__is_ptw_fail_T_16 = i_mmu_dptw_currState == 2'h3; // @[PTW.scala 174:20]
  wire  i_mmu_dptw__is_ptw_fail_T_24 = i_mmu_dptw__is_ptw_end_T_6 & i_mmu_dptw__is_ptw_fail_T_22; // @[PTW.scala 169:18]
  wire  i_mmu_dptw__is_ptw_fail_T_25 = i_mmu_dptw__pte_value_T[0]; // @[MMU.scala 35:16]
  wire  i_mmu_dptw__is_ptw_fail_T_27 = ~i_mmu_dptw__is_ptw_fail_T_25; // @[PTW.scala 178:14]
  wire  i_mmu_dptw__is_ptw_fail_T_30 = ~i_mmu_dptw__is_ptw_end_T; // @[PTW.scala 179:14]
  wire  i_mmu_dptw__is_ptw_fail_T_31 = i_mmu_dptw__pte_value_T[2]; // @[MMU.scala 37:16]
  wire  i_mmu_dptw__is_ptw_fail_T_34 = i_mmu_dptw__is_ptw_fail_T_30 & i_mmu_dptw__is_ptw_fail_T_31; // @[PTW.scala 179:26]
  wire  i_mmu_dptw__is_ptw_fail_T_35 = i_mmu_dptw__is_ptw_fail_T_27 | i_mmu_dptw__is_ptw_fail_T_34; // @[PTW.scala 178:27]
  wire  i_mmu_dptw__is_ptw_fail_T_36 = i_mmu_dptw__is_ptw_fail_T_24 | i_mmu_dptw__is_ptw_fail_T_35; // @[PTW.scala 176:7]
  wire  i_mmu_dptw__nextState_T_3 = i_mmu_dptw__is_ptw_end_T_6 | i_mmu_dptw__is_ptw_fail_T_36; // @[PTW.scala 118:27]
  wire  i_mmu_dptw__nextState_T_4 = i_mmu_dptw__nextState_T_3 | i_mmu_dptw_kill_trans; // @[PTW.scala 118:41]
  wire [1:0] i_mmu_dptw__nextState_T_5 = i_mmu_dptw__nextState_T_4 ? 2'h0 : 2'h2; // @[PTW.scala 118:14]
  wire [1:0] i_mmu_dptw__nextState_T_6 = i_mmu_dptw_is_trans_done ? i_mmu_dptw__nextState_T_5 : 2'h1; // @[PTW.scala 116:12]
  wire  i_mmu_dptw__T_3 = 2'h2 == i_mmu_dptw_currState; // @[PTW.scala 110:23]
  wire [1:0] i_mmu_dptw__nextState_T_10 = i_mmu_dptw__nextState_T_4 ? 2'h0 : 2'h3; // @[PTW.scala 126:14]
  wire [1:0] i_mmu_dptw__nextState_T_11 = i_mmu_dptw_is_trans_done ? i_mmu_dptw__nextState_T_10 : 2'h2; // @[PTW.scala 124:12]
  wire  i_mmu_dptw__T_4 = 2'h3 == i_mmu_dptw_currState; // @[PTW.scala 110:23]
  wire [1:0] i_mmu_dptw__nextState_T_16 = i_mmu_dptw_is_trans_done ? 2'h0 : 2'h3; // @[PTW.scala 132:12]
  wire [1:0] i_mmu_dptw__GEN_6 = i_mmu_dptw__T_4 ? i_mmu_dptw__nextState_T_16 : 2'h0; // @[PTW.scala 110:23 131:17]
  wire [1:0] i_mmu_dptw__GEN_7 = i_mmu_dptw__T_3 ? i_mmu_dptw__nextState_T_11 : i_mmu_dptw__GEN_6; // @[PTW.scala 110:23 123:17]
  wire [1:0] i_mmu_dptw__GEN_8 = i_mmu_dptw__T_2 ? i_mmu_dptw__nextState_T_6 : i_mmu_dptw__GEN_7; // @[PTW.scala 110:23 115:17]
  wire [1:0] i_mmu_dptw__GEN_9 = i_mmu_dptw__T_1 ? i_mmu_dptw__nextState_T_1 : i_mmu_dptw__GEN_8; // @[PTW.scala 110:23 112:17]
  wire  i_mmu_dptw__walkReq_T_1 = i_mmu_dptw__GEN_9 != 2'h0; // @[PTW.scala 102:95]
  wire  i_mmu_dptw__walkReq_T_2 = i_mmu_dptw__walkReq_T & i_mmu_dptw__walkReq_T_1; // @[PTW.scala 102:83]
  reg  i_mmu_dptw_walkReq_is_X; // @[Reg.scala 19:16]
  reg [63:0] i_mmu_dptw_walkReq_vaddr; // @[Reg.scala 19:16]
  wire [15:0] i_mmu_dptw__asidReq_T = i_mmu_dptw_io_cmm_mmu_satp[59:44]; // @[PTW.scala 103:43]
  reg [15:0] i_mmu_dptw_asidReq; // @[Reg.scala 19:16]
  reg  i_mmu_dptw_walkRspBits_is_X; // @[PTW.scala 104:28]
  reg [63:0] i_mmu_dptw_walkRspBits_renew_value; // @[PTW.scala 104:28]
  reg  i_mmu_dptw_walkRspBits_renew_is_giga_page; // @[PTW.scala 104:28]
  reg  i_mmu_dptw_walkRspBits_renew_is_mega_page; // @[PTW.scala 104:28]
  reg [15:0] i_mmu_dptw_walkRspBits_renew_asid; // @[PTW.scala 104:28]
  reg [8:0] i_mmu_dptw_walkRspBits_renew_vpn_0; // @[PTW.scala 104:28]
  reg [8:0] i_mmu_dptw_walkRspBits_renew_vpn_1; // @[PTW.scala 104:28]
  reg [8:0] i_mmu_dptw_walkRspBits_renew_vpn_2; // @[PTW.scala 104:28]
  reg  i_mmu_dptw_walkRspBits_is_ptw_fail; // @[PTW.scala 104:28]
  reg  i_mmu_dptw_walkRspBits_is_access_fault; // @[PTW.scala 104:28]
  reg  i_mmu_dptw_walkRspValid; // @[PTW.scala 105:29]
  wire  i_mmu_dptw__a_T = i_mmu_dptw__GEN_9 == 2'h1; // @[PTW.scala 148:19]
  wire [43:0] i_mmu_dptw__a_T_1 = i_mmu_dptw_io_cmm_mmu_satp[43:0]; // @[PTW.scala 148:59]
  wire  i_mmu_dptw__a_T_2 = i_mmu_dptw__GEN_9 == 2'h2; // @[PTW.scala 149:19]
  wire [25:0] i_mmu_dptw__a_T_5 = i_mmu_dptw__pte_value_T[53:28]; // @[MMU.scala 44:65]
  wire [43:0] i_mmu_dptw__a_T_12 = {i_mmu_dptw__a_T_5,i_mmu_dptw__is_ptw_fail_T_7,i_mmu_dptw__is_ptw_fail_T_2}; // @[Cat.scala 33:92]
  wire  i_mmu_dptw__a_T_13 = i_mmu_dptw__GEN_9 == 2'h3; // @[PTW.scala 150:19]
  wire [43:0] i_mmu_dptw__a_T_24 = i_mmu_dptw__a_T ? i_mmu_dptw__a_T_1 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] i_mmu_dptw__a_T_25 = i_mmu_dptw__a_T_2 ? i_mmu_dptw__a_T_12 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] i_mmu_dptw__a_T_26 = i_mmu_dptw__a_T_13 ? i_mmu_dptw__a_T_12 : 44'h0; // @[Mux.scala 27:73]
  wire [43:0] i_mmu_dptw__a_T_27 = i_mmu_dptw__a_T_24 | i_mmu_dptw__a_T_25; // @[Mux.scala 27:73]
  wire [43:0] i_mmu_dptw__a_T_28 = i_mmu_dptw__a_T_27 | i_mmu_dptw__a_T_26; // @[Mux.scala 27:73]
  wire [8:0] i_mmu_dptw__addr_dnxt_T_1 = i_mmu_dptw_io_ptw_i_bits_vaddr[38:30]; // @[PTW.scala 155:66]
  wire [11:0] i_mmu_dptw__addr_dnxt_T_2 = {i_mmu_dptw__addr_dnxt_T_1,3'h0}; // @[Cat.scala 33:92]
  wire [8:0] i_mmu_dptw__addr_dnxt_T_4 = i_mmu_dptw_walkReq_vaddr[29:21]; // @[PTW.scala 156:60]
  wire [11:0] i_mmu_dptw__addr_dnxt_T_5 = {i_mmu_dptw__addr_dnxt_T_4,3'h0}; // @[Cat.scala 33:92]
  wire [8:0] i_mmu_dptw__addr_dnxt_T_7 = i_mmu_dptw_walkReq_vaddr[20:12]; // @[PTW.scala 157:60]
  wire [11:0] i_mmu_dptw__addr_dnxt_T_8 = {i_mmu_dptw__addr_dnxt_T_7,3'h0}; // @[Cat.scala 33:92]
  wire [11:0] i_mmu_dptw__addr_dnxt_T_9 = i_mmu_dptw__a_T ? i_mmu_dptw__addr_dnxt_T_2 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] i_mmu_dptw__addr_dnxt_T_10 = i_mmu_dptw__a_T_2 ? i_mmu_dptw__addr_dnxt_T_5 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] i_mmu_dptw__addr_dnxt_T_11 = i_mmu_dptw__a_T_13 ? i_mmu_dptw__addr_dnxt_T_8 : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] i_mmu_dptw__addr_dnxt_T_12 = i_mmu_dptw__addr_dnxt_T_9 | i_mmu_dptw__addr_dnxt_T_10; // @[Mux.scala 27:73]
  wire [11:0] i_mmu_dptw__addr_dnxt_T_13 = i_mmu_dptw__addr_dnxt_T_12 | i_mmu_dptw__addr_dnxt_T_11; // @[Mux.scala 27:73]
  wire [55:0] i_mmu_dptw__addr_dnxt_T_14 = {i_mmu_dptw__a_T_28,i_mmu_dptw__addr_dnxt_T_13}; // @[Cat.scala 33:92]
  wire  i_mmu_dptw__pte_is_mega_page_T_1 = i_mmu_dptw__is_ptw_end_T_6 & i_mmu_dptw__is_ptw_fail_T_11; // @[PTW.scala 184:34]
  wire  i_mmu_dptw__pte_is_giga_page_T_1 = i_mmu_dptw__is_ptw_end_T_6 & i_mmu_dptw__is_ptw_fail_T_1; // @[PTW.scala 185:34]
  wire  i_mmu_dptw__T_7 = i_mmu_dptw__walkReq_T & i_mmu_dptw__a_T; // @[PTW.scala 188:39]
  wire  i_mmu_dptw__T_8 = i_mmu_dptw_io_ptw_get_ready & i_mmu_dptw_io_ptw_get_valid; // @[Decoupled.scala 52:35]
  wire  i_mmu_dptw__walkRspBits_is_access_fault_T_1 = i_mmu_dptw_walkRspBits_is_access_fault |
    i_mmu_dptw_walkRspBits_is_access_fault_mdl_io_is_fault; // @[PTW.scala 193:35]
  wire  i_mmu_dptw__T_9 = i_mmu_dptw__GEN_9 == 2'h0; // @[PTW.scala 197:19]
  wire  i_mmu_dptw__T_10 = i_mmu_dptw_currState != 2'h0; // @[PTW.scala 197:51]
  wire  i_mmu_dptw__T_11 = i_mmu_dptw__T_9 & i_mmu_dptw__T_10; // @[PTW.scala 197:39]
  wire [8:0] i_mmu_dptw__walkRspBits_renew_vpn_2_T = i_mmu_dptw_walkReq_vaddr[38:30]; // @[PTW.scala 205:46]
  wire  i_mmu_dptw__T_12 = ~i_mmu_dptw_io_ptw_o_valid; // @[PTW.scala 210:28]
  wire  i_mmu_dptw__T_14 = ~i_mmu_dptw_reset; // @[PTW.scala 210:11]
  wire  i_mmu_dptw__T_15 = ~i_mmu_dptw__T_12; // @[PTW.scala 210:11]
  wire  i_mmu_dptw__T_16 = i_mmu_dptw_io_ptw_o_ready & i_mmu_dptw_io_ptw_o_valid; // @[Decoupled.scala 52:35]
  wire  i_mmu_dptw__GEN_12 = i_mmu_dptw__T_16 ? 1'h0 : i_mmu_dptw_walkRspValid; // @[PTW.scala 211:32 212:18 105:29]
  wire  i_mmu_dptw__GEN_25 = i_mmu_dptw__T_11 | i_mmu_dptw__GEN_12; // @[PTW.scala 197:73 208:18]
  wire  i_mmu_dptw__T_18 = ~i_mmu_dptw_is_trans_done; // @[PTW.scala 243:30]
  wire  i_mmu_dptw__T_19 = i_mmu_dptw__T & i_mmu_dptw__T_18; // @[PTW.scala 243:28]
  reg  i_mmu_dptw_ptw_get_valid; // @[PTW.scala 342:30]
  reg  i_mmu_dptw_ptw_access_ready; // @[PTW.scala 343:33]
  reg  i_mmu_dptw_is_get_reqed; // @[PTW.scala 348:29]
  wire  i_mmu_dptw__T_21 = i_mmu_dptw__GEN_9 != i_mmu_dptw_currState; // @[PTW.scala 350:24]
  wire  i_mmu_dptw__GEN_29 = i_mmu_dptw__T_21 ? 1'h0 : i_mmu_dptw_is_get_reqed; // @[PTW.scala 348:29 350:{40,55}]
  wire  i_mmu_dptw__GEN_30 = i_mmu_dptw__T_8 | i_mmu_dptw__GEN_29; // @[PTW.scala 349:{27,42}]
  wire  i_mmu_dptw__T_24 = i_mmu_dptw__is_ptw_fail_T_1 | i_mmu_dptw__is_ptw_fail_T_11; // @[PTW.scala 353:40]
  wire  i_mmu_dptw__T_26 = i_mmu_dptw__T_24 | i_mmu_dptw__is_ptw_fail_T_16; // @[PTW.scala 353:72]
  wire  i_mmu_dptw__T_29 = ~i_mmu_dptw_io_ptw_get_valid; // @[PTW.scala 353:117]
  wire  i_mmu_dptw__T_30 = i_mmu_dptw__T_26 & i_mmu_dptw__T_29; // @[PTW.scala 353:115]
  wire  i_mmu_dptw__T_31 = ~i_mmu_dptw_is_get_reqed; // @[PTW.scala 353:137]
  wire  i_mmu_dptw__T_32 = i_mmu_dptw__T_30 & i_mmu_dptw__T_31; // @[PTW.scala 353:135]
  wire  i_mmu_dptw__GEN_31 = i_mmu_dptw__T_8 ? 1'h0 : i_mmu_dptw_ptw_get_valid; // @[PTW.scala 355:34 356:19 342:30]
  wire  i_mmu_dptw__GEN_32 = i_mmu_dptw__T_32 | i_mmu_dptw__GEN_31; // @[PTW.scala 353:153 354:19]
  wire  i_mmu_dptw__T_34 = ~i_mmu_dptw_io_ptw_access_ready; // @[PTW.scala 359:31]
  wire  i_mmu_dptw__T_35 = i_mmu_dptw_io_ptw_access_valid & i_mmu_dptw__T_34; // @[PTW.scala 359:29]
  wire  i_mmu_dptw__GEN_33 = i_mmu_dptw__T ? 1'h0 : i_mmu_dptw_ptw_access_ready; // @[PTW.scala 361:37 362:22 343:33]
  wire  i_mmu_dptw__GEN_34 = i_mmu_dptw__T_35 | i_mmu_dptw__GEN_33; // @[PTW.scala 359:53 360:22]
  wire [35:0] _GEN_524 = {{4'd0}, i_mmu_dptw_addr_qout}; // @[PTW.scala 365:74]
  wire [35:0] i_mmu_dptw__io_ptw_get_bits_T_1 = _GEN_524 & 36'hffffffff0; // @[PTW.scala 365:74]
  wire  i_mmu_dptw__T_38 = i_mmu_dptw_io_cmm_mmu_sfence_vma & i_mmu_dptw__T_10; // @[PTW.scala 382:31]
  wire  i_mmu_dptw__GEN_35 = i_mmu_dptw__walkReq_T ? 1'h0 : i_mmu_dptw_kill_trans; // @[PTW.scala 384:48 385:16 89:27]
  wire  i_mmu_dptw__GEN_36 = i_mmu_dptw__T_38 | i_mmu_dptw__GEN_35; // @[PTW.scala 382:65 383:16]
  wire  i_mmu_dptw__io_ptw_o_valid_T = ~i_mmu_dptw_kill_trans; // @[PTW.scala 390:36]
  wire  i_mmu_dptw__io_ptw_i_ready_T_2 = i_mmu_dptw__walkReq_T & i_mmu_dptw__T_12; // @[PTW.scala 393:51]
  wire  i_mmu_dptw__io_ptw_i_ready_T_3 = ~i_mmu_dptw_io_cmm_mmu_sfence_vma; // @[PTW.scala 393:71]
  wire  i_mmu_dptw__io_ptw_i_ready_T_4 = i_mmu_dptw__io_ptw_i_ready_T_2 & i_mmu_dptw__io_ptw_i_ready_T_3; // @[PTW.scala 393:69]
  wire [31:0] i_mmu_dptw_addr_dnxt = i_mmu_dptw__addr_dnxt_T_14[31:0]; // @[PTW.scala 153:13 94:23]
  wire  i_mmu_io_mmu_if_bits_is_access_fault_mdl_io_is_fault;
  wire  i_mmu_io_mmu_lsu_bits_is_access_fault_mdl_io_is_fault;
  wire  i_mmu_ptwGetArb_io_in_0_ready;
  wire  i_mmu_ptwGetArb_io_in_0_valid;
  wire [2:0] i_mmu_ptwGetArb_io_in_0_bits_opcode;
  wire [2:0] i_mmu_ptwGetArb_io_in_0_bits_param;
  wire [2:0] i_mmu_ptwGetArb_io_in_0_bits_size;
  wire  i_mmu_ptwGetArb_io_in_0_bits_source;
  wire [31:0] i_mmu_ptwGetArb_io_in_0_bits_address;
  wire [7:0] i_mmu_ptwGetArb_io_in_0_bits_mask;
  wire [63:0] i_mmu_ptwGetArb_io_in_0_bits_data;
  wire  i_mmu_ptwGetArb_io_in_0_bits_corrupt;
  wire  i_mmu_ptwGetArb_io_in_1_ready;
  wire  i_mmu_ptwGetArb_io_in_1_valid;
  wire [2:0] i_mmu_ptwGetArb_io_in_1_bits_opcode;
  wire [2:0] i_mmu_ptwGetArb_io_in_1_bits_param;
  wire [2:0] i_mmu_ptwGetArb_io_in_1_bits_size;
  wire  i_mmu_ptwGetArb_io_in_1_bits_source;
  wire [31:0] i_mmu_ptwGetArb_io_in_1_bits_address;
  wire [7:0] i_mmu_ptwGetArb_io_in_1_bits_mask;
  wire [63:0] i_mmu_ptwGetArb_io_in_1_bits_data;
  wire  i_mmu_ptwGetArb_io_in_1_bits_corrupt;
  wire  i_mmu_ptwGetArb_io_out_ready;
  wire  i_mmu_ptwGetArb_io_out_valid;
  wire [2:0] i_mmu_ptwGetArb_io_out_bits_opcode;
  wire [2:0] i_mmu_ptwGetArb_io_out_bits_param;
  wire [2:0] i_mmu_ptwGetArb_io_out_bits_size;
  wire  i_mmu_ptwGetArb_io_out_bits_source;
  wire [31:0] i_mmu_ptwGetArb_io_out_bits_address;
  wire [7:0] i_mmu_ptwGetArb_io_out_bits_mask;
  wire [63:0] i_mmu_ptwGetArb_io_out_bits_data;
  wire  i_mmu_ptwGetArb_io_out_bits_corrupt;
  wire  i_mmu_ptwGetArb_grant_1 = ~i_mmu_ptwGetArb_io_in_0_valid; // @[Arbiter.scala 45:78]
  wire  i_mmu_ptwGetArb__io_out_valid_T = ~i_mmu_ptwGetArb_grant_1; // @[Arbiter.scala 147:19]
  wire [3:0] i_mmu__is_bypass_if_T = i_mmu_io_cmm_mmu_satp[63:60]; // @[MMU.scala 136:37]
  wire  i_mmu__is_bypass_if_T_1 = i_mmu__is_bypass_if_T == 4'h0; // @[MMU.scala 136:45]
  wire  i_mmu__is_bypass_if_T_2 = i_mmu_io_cmm_mmu_priv_lvl_if == 2'h3; // @[MMU.scala 136:78]
  wire  i_mmu_is_bypass_if = i_mmu__is_bypass_if_T_1 | i_mmu__is_bypass_if_T_2; // @[MMU.scala 136:53]
  wire  i_mmu__is_bypass_ls_T_2 = i_mmu_io_cmm_mmu_priv_lvl_ls == 2'h3; // @[MMU.scala 137:78]
  wire  i_mmu_is_bypass_ls = i_mmu__is_bypass_if_T_1 | i_mmu__is_bypass_ls_T_2; // @[MMU.scala 137:53]
  reg  i_mmu_kill_iptw; // @[MMU.scala 141:26]
  reg  i_mmu_kill_dptw; // @[MMU.scala 142:26]
  wire  i_mmu__GEN_0 = i_mmu_iptw_io_ptw_i_ready ? 1'h0 : i_mmu_kill_iptw; // @[MMU.scala 147:39 148:15 141:26]
  wire  i_mmu__GEN_1 = i_mmu_io_if_flush | i_mmu__GEN_0; // @[MMU.scala 145:23 146:15]
  wire  i_mmu__GEN_2 = i_mmu_dptw_io_ptw_i_ready ? 1'h0 : i_mmu_kill_dptw; // @[MMU.scala 152:39 153:15 142:26]
  wire  i_mmu__GEN_3 = i_mmu_io_lsu_flush | i_mmu__GEN_2; // @[MMU.scala 150:24 151:15]
  wire  i_mmu__io_if_mmu_ready_T = i_mmu_io_mmu_if_ready & i_mmu_io_mmu_if_valid; // @[Decoupled.scala 52:35]
  wire  i_mmu__io_if_mmu_ready_T_1 = ~i_mmu_io_if_flush; // @[MMU.scala 160:22]
  wire  i_mmu__io_if_mmu_ready_T_2 = i_mmu__io_if_mmu_ready_T & i_mmu__io_if_mmu_ready_T_1; // @[MMU.scala 160:20]
  wire  i_mmu__io_if_mmu_ready_T_3 = ~i_mmu_kill_iptw; // @[MMU.scala 160:37]
  wire  i_mmu__io_lsu_mmu_ready_T = i_mmu_io_mmu_lsu_ready & i_mmu_io_mmu_lsu_valid; // @[Decoupled.scala 52:35]
  wire  i_mmu__io_lsu_mmu_ready_T_1 = ~i_mmu_io_lsu_flush; // @[MMU.scala 168:23]
  wire  i_mmu__io_lsu_mmu_ready_T_2 = i_mmu__io_lsu_mmu_ready_T & i_mmu__io_lsu_mmu_ready_T_1; // @[MMU.scala 168:21]
  wire  i_mmu__io_lsu_mmu_ready_T_3 = ~i_mmu_kill_dptw; // @[MMU.scala 168:39]
  wire  i_mmu__T = i_mmu_io_lsu_mmu_ready & i_mmu_io_lsu_mmu_valid; // @[Decoupled.scala 52:35]
  wire  i_mmu__T_2 = i_mmu__T == i_mmu__io_lsu_mmu_ready_T; // @[MMU.scala 170:27]
  wire  i_mmu__T_4 = ~i_mmu_reset; // @[MMU.scala 170:9]
  wire  i_mmu__T_5 = ~i_mmu__T_2; // @[MMU.scala 170:9]
  wire  i_mmu__iptw_io_ptw_i_valid_T = ~i_mmu_itlb_io_is_hit; // @[MMU.scala 180:44]
  wire  i_mmu__iptw_io_ptw_i_valid_T_1 = i_mmu_io_if_mmu_valid & i_mmu__iptw_io_ptw_i_valid_T; // @[MMU.scala 180:42]
  wire  i_mmu__iptw_io_ptw_i_valid_T_2 = ~i_mmu_is_bypass_if; // @[MMU.scala 180:62]
  wire  i_mmu__iptw_io_ptw_i_valid_T_3 = i_mmu__iptw_io_ptw_i_valid_T_1 & i_mmu__iptw_io_ptw_i_valid_T_2; // @[MMU.scala 180:60]
  wire  i_mmu__dptw_io_ptw_i_valid_T = ~i_mmu_dtlb_io_is_hit; // @[MMU.scala 183:45]
  wire  i_mmu__dptw_io_ptw_i_valid_T_1 = i_mmu_io_lsu_mmu_valid & i_mmu__dptw_io_ptw_i_valid_T; // @[MMU.scala 183:43]
  wire  i_mmu__dptw_io_ptw_i_valid_T_2 = ~i_mmu_is_bypass_ls; // @[MMU.scala 183:63]
  wire  i_mmu__dptw_io_ptw_i_valid_T_3 = i_mmu__dptw_io_ptw_i_valid_T_1 & i_mmu__dptw_io_ptw_i_valid_T_2; // @[MMU.scala 183:61]
  wire [63:0] i_mmu_pte_value = i_mmu_itlb_io_is_hit ? i_mmu_itlb_io_pte_o_value : i_mmu_iptw_io_ptw_o_bits_renew_value; // @[MMU.scala 194:18]
  wire  i_mmu_pte_is_giga_page = i_mmu_itlb_io_is_hit ? i_mmu_itlb_io_pte_o_is_giga_page :
    i_mmu_iptw_io_ptw_o_bits_renew_is_giga_page; // @[MMU.scala 194:18]
  wire  i_mmu_pte_is_mega_page = i_mmu_itlb_io_is_hit ? i_mmu_itlb_io_pte_o_is_mega_page :
    i_mmu_iptw_io_ptw_o_bits_renew_is_mega_page; // @[MMU.scala 194:18]
  wire [25:0] i_mmu__ipaddr_pa_ppn_2_T_2 = i_mmu_pte_value[53:28]; // @[MMU.scala 44:65]
  wire [8:0] i_mmu__ipaddr_pa_ppn_1_T = i_mmu_io_if_mmu_bits_vaddr[29:21]; // @[MMU.scala 329:51]
  wire [8:0] i_mmu__ipaddr_pa_ppn_1_T_2 = i_mmu_pte_value[27:19]; // @[MMU.scala 44:51]
  wire [8:0] i_mmu_ipaddr_pa_ppn_1 = i_mmu_pte_is_giga_page ? i_mmu__ipaddr_pa_ppn_1_T : i_mmu__ipaddr_pa_ppn_1_T_2; // @[MMU.scala 329:23]
  wire  i_mmu__ipaddr_pa_ppn_0_T = i_mmu_pte_is_giga_page | i_mmu_pte_is_mega_page; // @[MMU.scala 330:43]
  wire [8:0] i_mmu__ipaddr_pa_ppn_0_T_1 = i_mmu_io_if_mmu_bits_vaddr[20:12]; // @[MMU.scala 330:69]
  wire [8:0] i_mmu__ipaddr_pa_ppn_0_T_2 = i_mmu_pte_value[18:10]; // @[MMU.scala 44:37]
  wire [8:0] i_mmu_ipaddr_pa_ppn_0 = i_mmu__ipaddr_pa_ppn_0_T ? i_mmu__ipaddr_pa_ppn_0_T_1 : i_mmu__ipaddr_pa_ppn_0_T_2; // @[MMU.scala 330:23]
  wire [11:0] i_mmu_ipaddr_pa_pgoff = i_mmu_io_if_mmu_bits_vaddr[11:0]; // @[MMU.scala 331:25]
  wire [55:0] i_mmu__ipaddr_paddr_T = {i_mmu__ipaddr_pa_ppn_2_T_2,i_mmu_ipaddr_pa_ppn_1,i_mmu_ipaddr_pa_ppn_0,
    i_mmu_ipaddr_pa_pgoff}; // @[Cat.scala 33:92]
  wire [63:0] i_mmu_ipaddr_paddr = {{8'd0}, i_mmu__ipaddr_paddr_T}; // @[MMU.scala 326:21 333:11]
  wire [63:0] i_mmu_ipaddr = i_mmu_is_bypass_if ? i_mmu_io_if_mmu_bits_vaddr : i_mmu_ipaddr_paddr; // @[MMU.scala 196:21]
  wire  i_mmu__io_mmu_if_bits_is_access_fault_T_1 = i_mmu_iptw_io_ptw_o_bits_is_access_fault &
    i_mmu_iptw_io_ptw_o_bits_is_X; // @[MMU.scala 203:43]
  wire  i_mmu__io_mmu_if_bits_is_access_fault_T_2 = i_mmu__io_mmu_if_bits_is_access_fault_T_1 &
    i_mmu_iptw_io_ptw_o_valid; // @[MMU.scala 203:69]
  wire  i_mmu__io_mmu_if_bits_is_access_fault_T_3 = i_mmu_io_mmu_if_bits_is_access_fault_mdl_io_is_fault |
    i_mmu__io_mmu_if_bits_is_access_fault_T_2; // @[MMU.scala 202:102]
  wire [31:0] i_mmu__io_mmu_if_bits_is_access_fault_T_4 = i_mmu_ipaddr[63:32]; // @[MMU.scala 204:13]
  wire  i_mmu__io_mmu_if_bits_is_access_fault_T_5 = i_mmu__io_mmu_if_bits_is_access_fault_T_4 != 32'h0; // @[MMU.scala 204:23]
  wire [24:0] i_mmu__io_mmu_if_bits_is_paging_fault_is_vaddr_illegal_T = i_mmu_io_if_mmu_bits_vaddr[63:39]; // @[MMU.scala 311:39]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_vaddr_illegal_T_1 = i_mmu_io_if_mmu_bits_vaddr[38]; // @[MMU.scala 311:68]
  wire [24:0] i_mmu__io_mmu_if_bits_is_paging_fault_is_vaddr_illegal_T_3 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_vaddr_illegal_T_1 ? 25'h1ffffff : 25'h0; // @[Bitwise.scala 77:12]
  wire  i_mmu_io_mmu_if_bits_is_paging_fault_is_vaddr_illegal = i_mmu__io_mmu_if_bits_is_paging_fault_is_vaddr_illegal_T
     != i_mmu__io_mmu_if_bits_is_paging_fault_is_vaddr_illegal_T_3; // @[MMU.scala 311:47]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T = i_mmu_io_cmm_mmu_priv_lvl_if == 2'h0; // @[MMU.scala 313:19]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_1 = i_mmu_pte_value[4]; // @[MMU.scala 39:16]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_3 = ~
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_1; // @[MMU.scala 313:39]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_4 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T &
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_3; // @[MMU.scala 313:31]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_5 = i_mmu_io_cmm_mmu_priv_lvl_if == 2'h1; // @[MMU.scala 314:19]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_9 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_5 &
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_1; // @[MMU.scala 314:31]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_10 = i_mmu_io_cmm_mmu_sstatus[18]; // @[MMU.scala 314:71]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_11 = ~
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_10; // @[MMU.scala 314:76]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_15 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_4 |
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_9; // @[MMU.scala 313:52]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_16 = i_mmu_io_cmm_mmu_mstatus[17]; // @[MMU.scala 315:29]
  wire [1:0] i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_17 = i_mmu_io_cmm_mmu_mstatus[12:11]; // @[MMU.scala 315:54]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_18 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_17 == 2'h1; // @[MMU.scala 315:62]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_19 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_16 &
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_18; // @[MMU.scala 315:34]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_23 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_19 &
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_1; // @[MMU.scala 315:74]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_26 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_23 &
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_11; // @[MMU.scala 315:93]
  wire  i_mmu_io_mmu_if_bits_is_paging_fault_is_U_access_illegal =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_15 |
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_26; // @[MMU.scala 314:116]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_A_illegal_T = i_mmu_pte_value[6]; // @[MMU.scala 41:16]
  wire  i_mmu_io_mmu_if_bits_is_paging_fault_is_A_illegal = ~i_mmu__io_mmu_if_bits_is_paging_fault_is_A_illegal_T; // @[MMU.scala 317:32]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_MXR_illegal_T = i_mmu_io_cmm_mmu_mstatus[19]; // @[MMU.scala 319:46]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_is_MXR_illegal_T_1 = ~
    i_mmu__io_mmu_if_bits_is_paging_fault_is_MXR_illegal_T; // @[MMU.scala 319:51]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_T_1 = i_mmu_io_mmu_if_bits_is_paging_fault_is_vaddr_illegal |
    i_mmu_io_mmu_if_bits_is_paging_fault_is_U_access_illegal; // @[MMU.scala 321:31]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_T_2 = i_mmu__io_mmu_if_bits_is_paging_fault_T_1 |
    i_mmu_io_mmu_if_bits_is_paging_fault_is_A_illegal; // @[MMU.scala 321:53]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_T_5 = i_mmu_iptw_io_ptw_o_bits_is_ptw_fail & i_mmu_iptw_io_ptw_o_bits_is_X
    ; // @[MMU.scala 210:41]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_T_6 = i_mmu__io_mmu_if_bits_is_paging_fault_T_5 &
    i_mmu_iptw_io_ptw_o_valid; // @[MMU.scala 210:67]
  wire  i_mmu__io_mmu_if_bits_is_paging_fault_T_7 = i_mmu__io_mmu_if_bits_is_paging_fault_T_2 |
    i_mmu__io_mmu_if_bits_is_paging_fault_T_6; // @[MMU.scala 209:89]
  wire  i_mmu__io_mmu_if_valid_T_1 = i_mmu_io_if_mmu_valid & i_mmu_is_bypass_if; // @[MMU.scala 215:26]
  wire  i_mmu__io_mmu_if_valid_T_2 = i_mmu_io_if_mmu_valid & i_mmu_itlb_io_is_hit; // @[MMU.scala 216:26]
  wire  i_mmu__io_mmu_if_valid_T_3 = i_mmu__io_mmu_if_valid_T_1 | i_mmu__io_mmu_if_valid_T_2; // @[MMU.scala 215:42]
  wire  i_mmu__io_mmu_if_valid_T_4 = i_mmu_iptw_io_ptw_o_bits_is_X & i_mmu_iptw_io_ptw_o_valid; // @[MMU.scala 217:53]
  wire  i_mmu__io_mmu_if_valid_T_5 = i_mmu_io_if_mmu_valid & i_mmu__io_mmu_if_valid_T_4; // @[MMU.scala 217:26]
  wire  i_mmu__io_mmu_if_valid_T_6 = i_mmu__io_mmu_if_valid_T_3 | i_mmu__io_mmu_if_valid_T_5; // @[MMU.scala 216:44]
  wire  i_mmu__T_7 = i_mmu__io_mmu_if_valid_T_4 & i_mmu_itlb_io_is_hit; // @[MMU.scala 220:63]
  wire  i_mmu__T_9 = i_mmu__T_7 & i_mmu__io_if_mmu_ready_T_3; // @[MMU.scala 220:80]
  wire  i_mmu__T_10 = ~i_mmu__T_9; // @[MMU.scala 220:13]
  wire  i_mmu__T_13 = ~i_mmu__T_10; // @[MMU.scala 220:11]
  wire [63:0] i_mmu_pte_1_value = i_mmu_dtlb_io_is_hit ? i_mmu_dtlb_io_pte_o_value :
    i_mmu_dptw_io_ptw_o_bits_renew_value; // @[MMU.scala 225:18]
  wire  i_mmu_pte_1_is_giga_page = i_mmu_dtlb_io_is_hit ? i_mmu_dtlb_io_pte_o_is_giga_page :
    i_mmu_dptw_io_ptw_o_bits_renew_is_giga_page; // @[MMU.scala 225:18]
  wire  i_mmu_pte_1_is_mega_page = i_mmu_dtlb_io_is_hit ? i_mmu_dtlb_io_pte_o_is_mega_page :
    i_mmu_dptw_io_ptw_o_bits_renew_is_mega_page; // @[MMU.scala 225:18]
  wire [25:0] i_mmu__dpaddr_pa_ppn_2_T_2 = i_mmu_pte_1_value[53:28]; // @[MMU.scala 44:65]
  wire [8:0] i_mmu__dpaddr_pa_ppn_1_T = i_mmu_io_lsu_mmu_bits_vaddr[29:21]; // @[MMU.scala 329:51]
  wire [8:0] i_mmu__dpaddr_pa_ppn_1_T_2 = i_mmu_pte_1_value[27:19]; // @[MMU.scala 44:51]
  wire [8:0] i_mmu_dpaddr_pa_ppn_1 = i_mmu_pte_1_is_giga_page ? i_mmu__dpaddr_pa_ppn_1_T : i_mmu__dpaddr_pa_ppn_1_T_2; // @[MMU.scala 329:23]
  wire  i_mmu__dpaddr_pa_ppn_0_T = i_mmu_pte_1_is_giga_page | i_mmu_pte_1_is_mega_page; // @[MMU.scala 330:43]
  wire [8:0] i_mmu__dpaddr_pa_ppn_0_T_1 = i_mmu_io_lsu_mmu_bits_vaddr[20:12]; // @[MMU.scala 330:69]
  wire [8:0] i_mmu__dpaddr_pa_ppn_0_T_2 = i_mmu_pte_1_value[18:10]; // @[MMU.scala 44:37]
  wire [8:0] i_mmu_dpaddr_pa_ppn_0 = i_mmu__dpaddr_pa_ppn_0_T ? i_mmu__dpaddr_pa_ppn_0_T_1 : i_mmu__dpaddr_pa_ppn_0_T_2; // @[MMU.scala 330:23]
  wire [11:0] i_mmu_dpaddr_pa_pgoff = i_mmu_io_lsu_mmu_bits_vaddr[11:0]; // @[MMU.scala 331:25]
  wire [55:0] i_mmu__dpaddr_paddr_T = {i_mmu__dpaddr_pa_ppn_2_T_2,i_mmu_dpaddr_pa_ppn_1,i_mmu_dpaddr_pa_ppn_0,
    i_mmu_dpaddr_pa_pgoff}; // @[Cat.scala 33:92]
  wire [63:0] i_mmu_dpaddr_paddr = {{8'd0}, i_mmu__dpaddr_paddr_T}; // @[MMU.scala 326:21 333:11]
  wire [63:0] i_mmu_dpaddr = i_mmu_is_bypass_ls ? i_mmu_io_lsu_mmu_bits_vaddr : i_mmu_dpaddr_paddr; // @[MMU.scala 228:21]
  wire  i_mmu__io_mmu_lsu_bits_is_access_fault_T_1 = ~i_mmu_dptw_io_ptw_o_bits_is_X; // @[MMU.scala 235:46]
  wire  i_mmu__io_mmu_lsu_bits_is_access_fault_T_2 = i_mmu__io_mmu_lsu_bits_is_access_fault_T_1 &
    i_mmu_dptw_io_ptw_o_valid; // @[MMU.scala 235:71]
  wire  i_mmu__io_mmu_lsu_bits_is_access_fault_T_3 = i_mmu_dptw_io_ptw_o_bits_is_access_fault &
    i_mmu__io_mmu_lsu_bits_is_access_fault_T_2; // @[MMU.scala 235:43]
  wire  i_mmu__io_mmu_lsu_bits_is_access_fault_T_4 = i_mmu_io_mmu_lsu_bits_is_access_fault_mdl_io_is_fault |
    i_mmu__io_mmu_lsu_bits_is_access_fault_T_3; // @[MMU.scala 234:104]
  wire [31:0] i_mmu__io_mmu_lsu_bits_is_access_fault_T_5 = i_mmu_dpaddr[63:32]; // @[MMU.scala 236:13]
  wire  i_mmu__io_mmu_lsu_bits_is_access_fault_T_6 = i_mmu__io_mmu_lsu_bits_is_access_fault_T_5 != 32'h0; // @[MMU.scala 236:23]
  wire [2:0] i_mmu__io_mmu_lsu_bits_is_paging_fault_T_1 = {i_mmu_io_lsu_mmu_bits_is_X,i_mmu_io_lsu_mmu_bits_is_W,
    i_mmu_io_lsu_mmu_bits_is_R}; // @[Cat.scala 33:92]
  wire [24:0] i_mmu__io_mmu_lsu_bits_is_paging_fault_is_vaddr_illegal_T = i_mmu_io_lsu_mmu_bits_vaddr[63:39]; // @[MMU.scala 311:39]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_vaddr_illegal_T_1 = i_mmu_io_lsu_mmu_bits_vaddr[38]; // @[MMU.scala 311:68]
  wire [24:0] i_mmu__io_mmu_lsu_bits_is_paging_fault_is_vaddr_illegal_T_3 =
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_vaddr_illegal_T_1 ? 25'h1ffffff : 25'h0; // @[Bitwise.scala 77:12]
  wire  i_mmu_io_mmu_lsu_bits_is_paging_fault_is_vaddr_illegal =
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_vaddr_illegal_T !=
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_vaddr_illegal_T_3; // @[MMU.scala 311:47]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T = i_mmu_io_cmm_mmu_priv_lvl_ls == 2'h0; // @[MMU.scala 313:19]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_1 = i_mmu_pte_1_value[4]; // @[MMU.scala 39:16]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_3 = ~
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_1; // @[MMU.scala 313:39]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_4 =
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T &
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_3; // @[MMU.scala 313:31]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_5 = i_mmu_io_cmm_mmu_priv_lvl_ls == 2'h1; // @[MMU.scala 314:19]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_9 =
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_5 &
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_1; // @[MMU.scala 314:31]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_12 = i_mmu__io_mmu_lsu_bits_is_paging_fault_T_1[2]; // @[MMU.scala 314:98]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_14 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_11 |
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_12; // @[MMU.scala 314:88]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_15 =
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_9 &
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_14; // @[MMU.scala 314:50]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_16 =
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_4 |
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_15; // @[MMU.scala 313:52]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_24 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_19 &
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_1; // @[MMU.scala 315:74]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_27 =
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_24 &
    i_mmu__io_mmu_if_bits_is_paging_fault_is_U_access_illegal_T_11; // @[MMU.scala 315:93]
  wire  i_mmu_io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal =
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_16 |
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal_T_27; // @[MMU.scala 314:116]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_A_illegal_T = i_mmu_pte_1_value[6]; // @[MMU.scala 41:16]
  wire  i_mmu_io_mmu_lsu_bits_is_paging_fault_is_A_illegal = ~i_mmu__io_mmu_lsu_bits_is_paging_fault_is_A_illegal_T; // @[MMU.scala 317:32]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_D_illegal_T = i_mmu_pte_1_value[7]; // @[MMU.scala 42:16]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_D_illegal_T_2 = ~i_mmu__io_mmu_lsu_bits_is_paging_fault_is_D_illegal_T
    ; // @[MMU.scala 318:32]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_D_illegal_T_3 = i_mmu__io_mmu_lsu_bits_is_paging_fault_T_1[1]; // @[MMU.scala 318:54]
  wire  i_mmu_io_mmu_lsu_bits_is_paging_fault_is_D_illegal = i_mmu__io_mmu_lsu_bits_is_paging_fault_is_D_illegal_T_2 &
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_D_illegal_T_3; // @[MMU.scala 318:44]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal_T_2 = i_mmu_pte_1_value[1]; // @[MMU.scala 36:16]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal_T_4 = ~
    i_mmu__io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal_T_2; // @[MMU.scala 319:71]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal_T_5 =
    i_mmu__io_mmu_if_bits_is_paging_fault_is_MXR_illegal_T_1 & i_mmu__io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal_T_4
    ; // @[MMU.scala 319:63]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal_T_6 = i_mmu__io_mmu_lsu_bits_is_paging_fault_T_1[0]; // @[MMU.scala 319:93]
  wire  i_mmu_io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal = i_mmu__io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal_T_5
     & i_mmu__io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal_T_6; // @[MMU.scala 319:83]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_T_2 = i_mmu_io_mmu_lsu_bits_is_paging_fault_is_vaddr_illegal |
    i_mmu_io_mmu_lsu_bits_is_paging_fault_is_U_access_illegal; // @[MMU.scala 321:31]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_T_3 = i_mmu__io_mmu_lsu_bits_is_paging_fault_T_2 |
    i_mmu_io_mmu_lsu_bits_is_paging_fault_is_A_illegal; // @[MMU.scala 321:53]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_T_4 = i_mmu__io_mmu_lsu_bits_is_paging_fault_T_3 |
    i_mmu_io_mmu_lsu_bits_is_paging_fault_is_D_illegal; // @[MMU.scala 321:68]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_T_5 = i_mmu__io_mmu_lsu_bits_is_paging_fault_T_4 |
    i_mmu_io_mmu_lsu_bits_is_paging_fault_is_MXR_illegal; // @[MMU.scala 321:83]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_T_7 = i_mmu_dptw_io_ptw_o_bits_is_ptw_fail &
    i_mmu__io_mmu_lsu_bits_is_access_fault_T_1; // @[MMU.scala 241:40]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_T_8 = i_mmu__io_mmu_lsu_bits_is_paging_fault_T_7 &
    i_mmu_dptw_io_ptw_o_valid; // @[MMU.scala 241:67]
  wire  i_mmu__io_mmu_lsu_bits_is_paging_fault_T_9 = i_mmu__io_mmu_lsu_bits_is_paging_fault_T_5 |
    i_mmu__io_mmu_lsu_bits_is_paging_fault_T_8; // @[MMU.scala 240:152]
  wire  i_mmu__io_mmu_lsu_valid_T_2 = i_mmu__io_lsu_mmu_ready_T_1 & i_mmu__io_lsu_mmu_ready_T_3; // @[MMU.scala 245:21]
  wire  i_mmu__io_mmu_lsu_valid_T_3 = i_mmu_io_lsu_mmu_valid & i_mmu_is_bypass_ls; // @[MMU.scala 246:27]
  wire  i_mmu__io_mmu_lsu_valid_T_4 = i_mmu_io_lsu_mmu_valid & i_mmu_dtlb_io_is_hit; // @[MMU.scala 247:27]
  wire  i_mmu__io_mmu_lsu_valid_T_5 = i_mmu__io_mmu_lsu_valid_T_3 | i_mmu__io_mmu_lsu_valid_T_4; // @[MMU.scala 246:43]
  wire  i_mmu__io_mmu_lsu_valid_T_8 = i_mmu_io_lsu_mmu_valid & i_mmu__io_mmu_lsu_bits_is_access_fault_T_2; // @[MMU.scala 248:27]
  wire  i_mmu__io_mmu_lsu_valid_T_9 = i_mmu__io_mmu_lsu_valid_T_5 | i_mmu__io_mmu_lsu_valid_T_8; // @[MMU.scala 247:45]
  wire  i_mmu__T_16 = i_mmu__io_mmu_lsu_bits_is_access_fault_T_2 & i_mmu_dtlb_io_is_hit; // @[MMU.scala 256:64]
  wire  i_mmu__T_18 = i_mmu__T_16 & i_mmu__io_lsu_mmu_ready_T_3; // @[MMU.scala 256:81]
  wire  i_mmu__T_19 = ~i_mmu__T_18; // @[MMU.scala 256:13]
  wire  i_mmu__T_22 = ~i_mmu__T_19; // @[MMU.scala 256:11]
  wire  i_mmu__iptw_io_ptw_o_ready_T = i_mmu_io_mmu_if_ready | i_mmu_kill_iptw; // @[MMU.scala 259:43]
  wire  i_mmu__dptw_io_ptw_o_ready_T = i_mmu_io_mmu_lsu_ready | i_mmu_kill_dptw; // @[MMU.scala 262:43]
  wire  i_mmu__itlb_io_tlb_renew_valid_T_1 = i_mmu_iptw__T_16 & i_mmu_iptw_io_ptw_o_bits_is_X; // @[MMU.scala 268:49]
  wire  i_mmu__itlb_io_tlb_renew_valid_T_2 = ~i_mmu_iptw_io_ptw_o_bits_is_ptw_fail; // @[MMU.scala 268:78]
  wire  i_mmu__itlb_io_tlb_renew_valid_T_3 = i_mmu__itlb_io_tlb_renew_valid_T_1 & i_mmu__itlb_io_tlb_renew_valid_T_2; // @[MMU.scala 268:76]
  wire  i_mmu__dtlb_io_tlb_renew_valid_T_2 = i_mmu_dptw__T_16 & i_mmu__io_mmu_lsu_bits_is_access_fault_T_1; // @[MMU.scala 269:49]
  wire  i_mmu__dtlb_io_tlb_renew_valid_T_3 = ~i_mmu_dptw_io_ptw_o_bits_is_ptw_fail; // @[MMU.scala 269:78]
  wire  i_mmu__dtlb_io_tlb_renew_valid_T_4 = i_mmu__dtlb_io_tlb_renew_valid_T_2 & i_mmu__dtlb_io_tlb_renew_valid_T_3; // @[MMU.scala 269:76]
  wire  i_mmu__T_23 = ~i_mmu_io_ptw_access_bits_source; // @[MMU.scala 292:35]
  wire  i_mmu__GEN_4 = i_mmu_io_ptw_access_bits_source & i_mmu_dptw_io_ptw_access_ready; // @[MMU.scala 283:23 294:52 295:24]
  wire  i_mmu__GEN_5 = i_mmu_io_ptw_access_bits_source & i_mmu_io_ptw_access_valid; // @[MMU.scala 294:52 295:24 280:28]
  wire [2:0] i_mmu__GEN_6 = i_mmu_io_ptw_access_bits_source ? i_mmu_io_ptw_access_bits_opcode : 3'h0; // @[MMU.scala 294:52 295:24 282:27]
  wire [2:0] i_mmu__GEN_8 = i_mmu_io_ptw_access_bits_source ? i_mmu_io_ptw_access_bits_size : 3'h0; // @[MMU.scala 294:52 295:24 282:27]
  wire [63:0] i_mmu__GEN_12 = i_mmu_io_ptw_access_bits_source ? i_mmu_io_ptw_access_bits_data : 64'h0; // @[MMU.scala 294:52 295:24 282:27]
  wire  i_mmu__T_25 = i_mmu_io_if_flush & i_mmu_io_lsu_flush; // @[MMU.scala 338:25]
  wire  i_mmu__T_28 = ~i_mmu__T_25; // @[MMU.scala 338:11]
  wire  prefetcher_io_intent_valid;
  wire [2:0] prefetcher_io_intent_bits_opcode;
  wire [2:0] prefetcher_io_intent_bits_param;
  wire [2:0] prefetcher_io_intent_bits_size;
  wire  prefetcher_io_intent_bits_source;
  wire [31:0] prefetcher_io_intent_bits_address;
  wire [7:0] prefetcher_io_intent_bits_mask;
  wire [63:0] prefetcher_io_intent_bits_data;
  wire  prefetcher_io_intent_bits_corrupt;
  wire  prefetcher_io_hintAck_ready;
  wire  _exe_stage_io_missUnit_dcache_grant_valid_T_2 = auto_dcache_client_out_d_bits_opcode == 3'h4 |
    auto_dcache_client_out_d_bits_opcode == 3'h5; // @[rift2Core.scala 274:122]
  wire  _exe_stage_io_writeBackUnit_dcache_grant_valid_T = auto_dcache_client_out_d_bits_opcode == 3'h6; // @[rift2Core.scala 277:106]
  assign if1_uBTB_io_resp_isActive_0 = 1'h1; // @[uBTB.scala 150:83]
  assign if1_uBTB_io_resp_isActive_1 = if1_uBTB__io_resp_isActive_0_T_2 >= 2'h1; // @[uBTB.scala 150:83]
  assign if1_uBTB_io_resp_isActive_2 = if1_uBTB__io_resp_isActive_0_T_2 >= 2'h2; // @[uBTB.scala 150:83]
  assign if1_uBTB_io_resp_isActive_3 = if1_uBTB__io_resp_isActive_0_T_2 >= 2'h3; // @[uBTB.scala 150:83]
  assign if1_io_pc_gen_valid = 1'h1; // @[IF1.scala 119:21]
  assign if1_io_pc_gen_bits_isActive_0 = if1_uBTB_io_resp_isActive_0; // @[IF1.scala 77:27]
  assign if1_io_pc_gen_bits_isActive_1 = if1_uBTB_io_resp_isActive_1; // @[IF1.scala 77:27]
  assign if1_io_pc_gen_bits_isActive_2 = if1_uBTB_io_resp_isActive_2; // @[IF1.scala 77:27]
  assign if1_io_pc_gen_bits_isActive_3 = if1_uBTB_io_resp_isActive_3; // @[IF1.scala 77:27]
  assign if1_io_pc_gen_bits_pc = if1_pc_qout; // @[IF1.scala 120:21]
  assign if2_ibuf_io_enq_0_ready = ~if2_ibuf__GEN_7; // @[MultiPortFifo.scala 64:94]
  assign if2_ibuf_io_enq_1_ready = ~if2_ibuf__GEN_15; // @[MultiPortFifo.scala 64:94]
  assign if2_ibuf_io_enq_2_ready = ~if2_ibuf__GEN_23; // @[MultiPortFifo.scala 64:94]
  assign if2_ibuf_io_enq_3_ready = ~if2_ibuf__GEN_31; // @[MultiPortFifo.scala 64:94]
  assign if2_ibuf_io_deq_0_valid = 3'h7 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_valid_7 : if2_ibuf__GEN_38; // @[MultiPortFifo.scala 65:{94,94}]
  assign if2_ibuf_io_deq_0_bits_pc = 3'h7 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_7_pc : if2_ibuf__GEN_1936; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_0_bits_instr = 3'h7 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_7_instr : if2_ibuf__GEN_1937
    ; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_0_bits_isRedirect = 3'h7 == if2_ibuf__io_deq_0_valid_T_1 ? if2_ibuf_buf_7_isRedirect :
    if2_ibuf__GEN_1939; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_1_valid = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_valid_7 : if2_ibuf__GEN_46; // @[MultiPortFifo.scala 65:{94,94}]
  assign if2_ibuf_io_deq_1_bits_pc = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_7_pc : if2_ibuf__GEN_1976; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_1_bits_instr = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_7_instr : if2_ibuf__GEN_1977
    ; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_1_bits_isFault = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_7_isFault :
    if2_ibuf__GEN_1978; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_1_bits_isRedirect = 3'h7 == if2_ibuf__io_deq_1_valid_T_1 ? if2_ibuf_buf_7_isRedirect :
    if2_ibuf__GEN_1979; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_2_valid = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_valid_7 : if2_ibuf__GEN_54; // @[MultiPortFifo.scala 65:{94,94}]
  assign if2_ibuf_io_deq_2_bits_pc = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_7_pc : if2_ibuf__GEN_2016; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_2_bits_instr = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_7_instr : if2_ibuf__GEN_2017
    ; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_2_bits_isFault = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_7_isFault :
    if2_ibuf__GEN_2018; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_2_bits_isRedirect = 3'h7 == if2_ibuf__io_deq_2_valid_T_1 ? if2_ibuf_buf_7_isRedirect :
    if2_ibuf__GEN_2019; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_3_valid = 3'h7 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_valid_7 : if2_ibuf__GEN_62; // @[MultiPortFifo.scala 65:{94,94}]
  assign if2_ibuf_io_deq_3_bits_pc = 3'h7 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_7_pc : if2_ibuf__GEN_2056; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_3_bits_instr = 3'h7 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_7_instr : if2_ibuf__GEN_2057
    ; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_3_bits_isFault = 3'h7 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_7_isFault :
    if2_ibuf__GEN_2058; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_ibuf_io_deq_3_bits_isRedirect = 3'h7 == if2_ibuf__io_deq_3_valid_T_1 ? if2_ibuf_buf_7_isRedirect :
    if2_ibuf__GEN_2059; // @[MultiPortFifo.scala 114:{14,14}]
  assign if2_datRAM_0_datMem_0_MPORT_en = if2_datRAM_0_datMem_0_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_0_MPORT_addr = if2_datRAM_0_datMem_0_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_0_MPORT_data = if2_datRAM_0_datMem_0[if2_datRAM_0_datMem_0_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_0_MPORT_1_data = if2_datRAM_0_io_dataw_0;
  assign if2_datRAM_0_datMem_0_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_0_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_0_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_1_MPORT_en = if2_datRAM_0_datMem_1_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_1_MPORT_addr = if2_datRAM_0_datMem_1_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_1_MPORT_data = if2_datRAM_0_datMem_1[if2_datRAM_0_datMem_1_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_1_MPORT_1_data = if2_datRAM_0_io_dataw_1;
  assign if2_datRAM_0_datMem_1_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_1_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_1_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_2_MPORT_en = if2_datRAM_0_datMem_2_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_2_MPORT_addr = if2_datRAM_0_datMem_2_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_2_MPORT_data = if2_datRAM_0_datMem_2[if2_datRAM_0_datMem_2_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_2_MPORT_1_data = if2_datRAM_0_io_dataw_2;
  assign if2_datRAM_0_datMem_2_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_2_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_2_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_3_MPORT_en = if2_datRAM_0_datMem_3_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_3_MPORT_addr = if2_datRAM_0_datMem_3_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_3_MPORT_data = if2_datRAM_0_datMem_3[if2_datRAM_0_datMem_3_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_3_MPORT_1_data = if2_datRAM_0_io_dataw_3;
  assign if2_datRAM_0_datMem_3_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_3_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_3_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_4_MPORT_en = if2_datRAM_0_datMem_4_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_4_MPORT_addr = if2_datRAM_0_datMem_4_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_4_MPORT_data = if2_datRAM_0_datMem_4[if2_datRAM_0_datMem_4_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_4_MPORT_1_data = if2_datRAM_0_io_dataw_4;
  assign if2_datRAM_0_datMem_4_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_4_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_4_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_5_MPORT_en = if2_datRAM_0_datMem_5_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_5_MPORT_addr = if2_datRAM_0_datMem_5_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_5_MPORT_data = if2_datRAM_0_datMem_5[if2_datRAM_0_datMem_5_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_5_MPORT_1_data = if2_datRAM_0_io_dataw_5;
  assign if2_datRAM_0_datMem_5_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_5_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_5_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_6_MPORT_en = if2_datRAM_0_datMem_6_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_6_MPORT_addr = if2_datRAM_0_datMem_6_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_6_MPORT_data = if2_datRAM_0_datMem_6[if2_datRAM_0_datMem_6_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_6_MPORT_1_data = if2_datRAM_0_io_dataw_6;
  assign if2_datRAM_0_datMem_6_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_6_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_6_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_7_MPORT_en = if2_datRAM_0_datMem_7_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_7_MPORT_addr = if2_datRAM_0_datMem_7_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_7_MPORT_data = if2_datRAM_0_datMem_7[if2_datRAM_0_datMem_7_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_7_MPORT_1_data = if2_datRAM_0_io_dataw_7;
  assign if2_datRAM_0_datMem_7_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_7_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_7_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_8_MPORT_en = if2_datRAM_0_datMem_8_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_8_MPORT_addr = if2_datRAM_0_datMem_8_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_8_MPORT_data = if2_datRAM_0_datMem_8[if2_datRAM_0_datMem_8_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_8_MPORT_1_data = if2_datRAM_0_io_dataw_8;
  assign if2_datRAM_0_datMem_8_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_8_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_8_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_9_MPORT_en = if2_datRAM_0_datMem_9_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_9_MPORT_addr = if2_datRAM_0_datMem_9_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_9_MPORT_data = if2_datRAM_0_datMem_9[if2_datRAM_0_datMem_9_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_9_MPORT_1_data = if2_datRAM_0_io_dataw_9;
  assign if2_datRAM_0_datMem_9_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_9_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_9_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_10_MPORT_en = if2_datRAM_0_datMem_10_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_10_MPORT_addr = if2_datRAM_0_datMem_10_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_10_MPORT_data = if2_datRAM_0_datMem_10[if2_datRAM_0_datMem_10_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_10_MPORT_1_data = if2_datRAM_0_io_dataw_10;
  assign if2_datRAM_0_datMem_10_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_10_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_10_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_11_MPORT_en = if2_datRAM_0_datMem_11_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_11_MPORT_addr = if2_datRAM_0_datMem_11_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_11_MPORT_data = if2_datRAM_0_datMem_11[if2_datRAM_0_datMem_11_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_11_MPORT_1_data = if2_datRAM_0_io_dataw_11;
  assign if2_datRAM_0_datMem_11_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_11_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_11_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_12_MPORT_en = if2_datRAM_0_datMem_12_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_12_MPORT_addr = if2_datRAM_0_datMem_12_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_12_MPORT_data = if2_datRAM_0_datMem_12[if2_datRAM_0_datMem_12_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_12_MPORT_1_data = if2_datRAM_0_io_dataw_12;
  assign if2_datRAM_0_datMem_12_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_12_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_12_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_13_MPORT_en = if2_datRAM_0_datMem_13_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_13_MPORT_addr = if2_datRAM_0_datMem_13_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_13_MPORT_data = if2_datRAM_0_datMem_13[if2_datRAM_0_datMem_13_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_13_MPORT_1_data = if2_datRAM_0_io_dataw_13;
  assign if2_datRAM_0_datMem_13_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_13_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_13_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_14_MPORT_en = if2_datRAM_0_datMem_14_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_14_MPORT_addr = if2_datRAM_0_datMem_14_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_14_MPORT_data = if2_datRAM_0_datMem_14[if2_datRAM_0_datMem_14_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_14_MPORT_1_data = if2_datRAM_0_io_dataw_14;
  assign if2_datRAM_0_datMem_14_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_14_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_14_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_datMem_15_MPORT_en = if2_datRAM_0_datMem_15_MPORT_en_pipe_0;
  assign if2_datRAM_0_datMem_15_MPORT_addr = if2_datRAM_0_datMem_15_MPORT_addr_pipe_0;
  assign if2_datRAM_0_datMem_15_MPORT_data = if2_datRAM_0_datMem_15[if2_datRAM_0_datMem_15_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign if2_datRAM_0_datMem_15_MPORT_1_data = if2_datRAM_0_io_dataw_15;
  assign if2_datRAM_0_datMem_15_MPORT_1_addr = if2_datRAM_0_io_addrw;
  assign if2_datRAM_0_datMem_15_MPORT_1_mask = 1'h1;
  assign if2_datRAM_0_datMem_15_MPORT_1_en = if2_datRAM_0_io_enw;
  assign if2_datRAM_0_io_datar_0 = if2_datRAM_0_datMem_0_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_1 = if2_datRAM_0_datMem_1_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_2 = if2_datRAM_0_datMem_2_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_3 = if2_datRAM_0_datMem_3_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_4 = if2_datRAM_0_datMem_4_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_5 = if2_datRAM_0_datMem_5_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_6 = if2_datRAM_0_datMem_6_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_7 = if2_datRAM_0_datMem_7_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_8 = if2_datRAM_0_datMem_8_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_9 = if2_datRAM_0_datMem_9_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_10 = if2_datRAM_0_datMem_10_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_11 = if2_datRAM_0_datMem_11_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_12 = if2_datRAM_0_datMem_12_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_13 = if2_datRAM_0_datMem_13_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_14 = if2_datRAM_0_datMem_14_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_datRAM_0_io_datar_15 = if2_datRAM_0_datMem_15_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign if2_tagRAM_0_tagMem_io_datar_MPORT_en = if2_tagRAM_0_tagMem_io_datar_MPORT_en_pipe_0;
  assign if2_tagRAM_0_tagMem_io_datar_MPORT_addr = if2_tagRAM_0_tagMem_io_datar_MPORT_addr_pipe_0;
  assign if2_tagRAM_0_tagMem_io_datar_MPORT_data = if2_tagRAM_0_tagMem[if2_tagRAM_0_tagMem_io_datar_MPORT_addr]; // @[CacheRAM.scala 152:27]
  assign if2_tagRAM_0_tagMem_MPORT_data = if2_tagRAM_0_io_dataw;
  assign if2_tagRAM_0_tagMem_MPORT_addr = if2_tagRAM_0_io_addrw;
  assign if2_tagRAM_0_tagMem_MPORT_mask = 1'h1;
  assign if2_tagRAM_0_tagMem_MPORT_en = if2_tagRAM_0_io_enw;
  assign if2_tagRAM_0_io_datar = if2_tagRAM_0_tagMem_io_datar_MPORT_data; // @[CacheRAM.scala 164:18 165:14]
  assign if2_io_if2_req_ready = if2_io_if_mmu_ready; // @[IF2.scala 111:20]
  assign if2_io_if2_resp_0_valid = if2_ibuf_io_deq_0_valid; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_0_bits_pc = if2_ibuf_io_deq_0_bits_pc; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_0_bits_instr = if2_ibuf_io_deq_0_bits_instr; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_0_bits_isRedirect = if2_ibuf_io_deq_0_bits_isRedirect; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_1_valid = if2_ibuf_io_deq_1_valid; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_1_bits_pc = if2_ibuf_io_deq_1_bits_pc; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_1_bits_instr = if2_ibuf_io_deq_1_bits_instr; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_1_bits_isFault = if2_ibuf_io_deq_1_bits_isFault; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_1_bits_isRedirect = if2_ibuf_io_deq_1_bits_isRedirect; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_2_valid = if2_ibuf_io_deq_2_valid; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_2_bits_pc = if2_ibuf_io_deq_2_bits_pc; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_2_bits_instr = if2_ibuf_io_deq_2_bits_instr; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_2_bits_isFault = if2_ibuf_io_deq_2_bits_isFault; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_2_bits_isRedirect = if2_ibuf_io_deq_2_bits_isRedirect; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_3_valid = if2_ibuf_io_deq_3_valid; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_3_bits_pc = if2_ibuf_io_deq_3_bits_pc; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_3_bits_instr = if2_ibuf_io_deq_3_bits_instr; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_3_bits_isFault = if2_ibuf_io_deq_3_bits_isFault; // @[IF2.scala 75:15]
  assign if2_io_if2_resp_3_bits_isRedirect = if2_ibuf_io_deq_3_bits_isRedirect; // @[IF2.scala 75:15]
  assign if2_io_if_mmu_valid = if2_io_if2_req_valid; // @[IF2.scala 106:19]
  assign if2_io_if_mmu_bits_is_X = 1'h1; // @[IF2.scala 110:23]
  assign if2_io_if_mmu_bits_vaddr = if2_io_if2_req_bits_pc; // @[IF2.scala 107:24]
  assign if2_io_mmu_if_ready = if2__io_mmu_if_ready_T_2 & if2__io_mmu_if_ready_T_4; // @[IF2.scala 113:56]
  assign if2_io_if_cmm_ill_vaddr = if2_io_mmu_if_bits_vaddr; // @[IF2.scala 125:23]
  assign if2_io_icache_get_valid = if2__io_icache_get_valid_T_2 & if2__T_3; // @[IF2.scala 282:62]
  assign if2_io_icache_get_bits_opcode = 3'h4; // @[Edges.scala 447:17 448:15]
  assign if2_io_icache_get_bits_param = 3'h0; // @[Edges.scala 447:17 449:15]
  assign if2_io_icache_get_bits_size = 3'h4; // @[Edges.scala 447:17 450:15]
  assign if2_io_icache_get_bits_source = 1'h0; // @[Edges.scala 447:17 451:15]
  assign if2_io_icache_get_bits_address = if2__io_icache_get_bits_T_2[31:0]; // @[Edges.scala 447:17 452:15]
  assign if2_io_icache_get_bits_mask = 8'hff; // @[Cat.scala 33:92]
  assign if2_io_icache_get_bits_data = 64'h0; // @[Edges.scala 447:17 454:15]
  assign if2_io_icache_get_bits_corrupt = 1'h0; // @[Edges.scala 447:17 455:15]
  assign if2_io_icache_access_ready = 1'h1; // @[IF2.scala 290:26]
  assign if2_ibuf_clock = if2_clock;
  assign if2_ibuf_reset = if2_reset;
  assign if2_ibuf_io_enq_0_valid = if2__ibuf_io_enq_0_valid_T_10 | if2__ibuf_io_enq_0_valid_T_16; // @[IF2.scala 361:222]
  assign if2_ibuf_io_enq_0_bits_pc = if2__GEN_17[38:0];
  assign if2_ibuf_io_enq_0_bits_instr = if2__GEN_16[15:0];
  assign if2_ibuf_io_enq_0_bits_isFault = if2__is_access_fault_T | if2__is_paging_fault_T; // @[IF2.scala 343:60 348:33]
  assign if2_ibuf_io_enq_1_valid = if2__ibuf_io_enq_1_valid_T_9 & if2_io_if2_req_bits_isActive_1; // @[IF2.scala 365:217]
  assign if2_ibuf_io_enq_1_bits_pc = if2__ibuf_io_enq_1_bits_pc_T_1[38:0]; // @[IF2.scala 332:31]
  assign if2_ibuf_io_enq_1_bits_instr = if2__ibuf_io_enq_1_bits_instr_T[15:0]; // @[IF2.scala 331:31]
  assign if2_ibuf_io_enq_2_valid = if2__ibuf_io_enq_2_valid_T_9 & if2_io_if2_req_bits_isActive_2; // @[IF2.scala 365:217]
  assign if2_ibuf_io_enq_2_bits_pc = if2__ibuf_io_enq_2_bits_pc_T_1[38:0]; // @[IF2.scala 332:31]
  assign if2_ibuf_io_enq_2_bits_instr = if2__ibuf_io_enq_2_bits_instr_T[15:0]; // @[IF2.scala 331:31]
  assign if2_ibuf_io_enq_3_valid = if2__ibuf_io_enq_3_valid_T_9 & if2_io_if2_req_bits_isActive_3; // @[IF2.scala 365:217]
  assign if2_ibuf_io_enq_3_bits_pc = if2__ibuf_io_enq_3_bits_pc_T_1[38:0]; // @[IF2.scala 332:31]
  assign if2_ibuf_io_enq_3_bits_instr = if2__reAlign_instr_res_T[63:48]; // @[IF2.scala 331:48]
  assign if2_ibuf_io_deq_0_ready = if2_io_if2_resp_0_ready; // @[IF2.scala 75:15]
  assign if2_ibuf_io_deq_1_ready = if2_io_if2_resp_1_ready; // @[IF2.scala 75:15]
  assign if2_ibuf_io_deq_2_ready = if2_io_if2_resp_2_ready; // @[IF2.scala 75:15]
  assign if2_ibuf_io_deq_3_ready = if2_io_if2_resp_3_ready; // @[IF2.scala 75:15]
  assign if2_ibuf_io_flush = if2_io_flush; // @[IF2.scala 74:17]
  assign if2_datRAM_0_clock = if2_clock;
  assign if2_datRAM_0_io_addrr = if2_io_mmu_if_bits_paddr[4]; // @[IF2.scala 236:47]
  assign if2_datRAM_0_io_addrw = if2_io_mmu_if_bits_paddr[4]; // @[IF2.scala 237:47]
  assign if2_datRAM_0_io_dataw_0 = if2__icache_access_data_T[7:0]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_1 = if2__icache_access_data_T[15:8]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_2 = if2__icache_access_data_T[23:16]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_3 = if2__icache_access_data_T[31:24]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_4 = if2__icache_access_data_T[39:32]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_5 = if2__icache_access_data_T[47:40]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_6 = if2__icache_access_data_T[55:48]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_7 = if2__icache_access_data_T[63:56]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_8 = if2__icache_access_data_T[71:64]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_9 = if2__icache_access_data_T[79:72]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_10 = if2__icache_access_data_T[87:80]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_11 = if2__icache_access_data_T[95:88]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_12 = if2__icache_access_data_T[103:96]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_13 = if2__icache_access_data_T[111:104]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_14 = if2__icache_access_data_T[119:112]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_dataw_15 = if2__icache_access_data_T[127:120]; // @[IF2.scala 249:65]
  assign if2_datRAM_0_io_enw = if2__datRAM_0_io_enw_T_6 & if2__T_3; // @[IF2.scala 244:115]
  assign if2_datRAM_0_io_enr = if2__icache_state_dnxt_T | if2__icache_state_dnxt_T_10; // @[IF2.scala 241:52]
  assign if2_tagRAM_0_clock = if2_clock;
  assign if2_tagRAM_0_io_addrr = if2_io_mmu_if_bits_paddr[4]; // @[IF2.scala 238:47]
  assign if2_tagRAM_0_io_addrw = if2_io_mmu_if_bits_paddr[4]; // @[IF2.scala 239:47]
  assign if2_tagRAM_0_io_dataw = if2_io_mmu_if_bits_paddr[31:5]; // @[IF2.scala 80:37]
  assign if2_tagRAM_0_io_enw = if2__datRAM_0_io_enw_T_6 & if2__T_3; // @[IF2.scala 245:115]
  assign if2_tagRAM_0_io_enr = if2__icache_state_dnxt_T | if2__icache_state_dnxt_T_10; // @[IF2.scala 242:52]
  assign if3_combPDT_io_enq_0_ready = if3_combPDT_io_deq_0_ready; // @[RePort.scala 80:69]
  assign if3_combPDT_io_enq_1_ready = if3_combPDT_io_deq_1_ready; // @[RePort.scala 80:91]
  assign if3_combPDT_io_enq_2_ready = if3_combPDT_io_deq_2_ready; // @[RePort.scala 80:91]
  assign if3_combPDT_io_enq_3_ready = if3_combPDT_io_deq_3_ready; // @[RePort.scala 80:91]
  assign if3_combPDT_io_deq_0_valid = if3_combPDT__T_8 > 3'h0; // @[RePort.scala 79:81]
  assign if3_combPDT_io_deq_0_bits_isRVC = if3_combPDT__T_24 & if3_combPDT__GEN_3; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_0_bits_instr = if3_combPDT__T_24 ? if3_combPDT__GEN_43 : 32'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_0_bits_pc = if3_combPDT__T_24 ? if3_combPDT__GEN_47 : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_0_bits_isRedirect = 1'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_0_bits_target = 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_1_valid = if3_combPDT__T_8 > 3'h1; // @[RePort.scala 79:81]
  assign if3_combPDT_io_deq_1_bits_isRVC = if3_combPDT__T_25 & if3_combPDT__GEN_78; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_1_bits_instr = if3_combPDT__T_25 ? if3_combPDT__GEN_118 : 32'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_1_bits_pc = if3_combPDT__T_25 ? if3_combPDT__GEN_122 : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_1_bits_isRedirect = 1'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_1_bits_target = 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_2_valid = if3_combPDT__T_8 > 3'h2; // @[RePort.scala 79:81]
  assign if3_combPDT_io_deq_2_bits_isRVC = if3_combPDT__T_26 & if3_combPDT__GEN_153; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_2_bits_instr = if3_combPDT__T_26 ? if3_combPDT__GEN_193 : 32'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_2_bits_pc = if3_combPDT__T_26 ? if3_combPDT__GEN_197 : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_2_bits_isRedirect = 1'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_2_bits_target = 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_3_valid = if3_combPDT__T_8 > 3'h3; // @[RePort.scala 79:81]
  assign if3_combPDT_io_deq_3_bits_isRVC = if3_combPDT__T_27 & if3_combPDT__GEN_228; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_3_bits_instr = if3_combPDT__T_27 ? if3_combPDT__GEN_268 : 32'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_3_bits_pc = if3_combPDT__T_27 ? if3_combPDT__GEN_272 : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_3_bits_isRedirect = 1'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_combPDT_io_deq_3_bits_target = 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_btb_bypassFifo_ram_target_io_deq_bits_MPORT_en = 1'h1;
  assign if3_btb_bypassFifo_ram_target_io_deq_bits_MPORT_addr = 1'h0;
  assign if3_btb_bypassFifo_ram_target_io_deq_bits_MPORT_data =
    if3_btb_bypassFifo_ram_target[if3_btb_bypassFifo_ram_target_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign if3_btb_bypassFifo_ram_target_MPORT_data = if3_btb_bypassFifo_io_enq_bits_target;
  assign if3_btb_bypassFifo_ram_target_MPORT_addr = 1'h0;
  assign if3_btb_bypassFifo_ram_target_MPORT_mask = 1'h1;
  assign if3_btb_bypassFifo_ram_target_MPORT_en = if3_btb_bypassFifo__empty_T ? if3_btb_bypassFifo__GEN_9 :
    if3_btb_bypassFifo__do_enq_T;
  assign if3_btb_bypassFifo_io_enq_ready = ~if3_btb_bypassFifo_maybe_full; // @[Decoupled.scala 305:19]
  assign if3_btb_bypassFifo_io_deq_valid = if3_btb_bypassFifo_io_enq_valid | if3_btb_bypassFifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign if3_btb_bypassFifo_io_deq_bits_target = if3_btb_bypassFifo__empty_T ? if3_btb_bypassFifo_io_enq_bits_target :
    if3_btb_bypassFifo_ram_target_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_en =
    if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_en_pipe_0;
  assign if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_addr =
    if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_addr_pipe_0;
  assign if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_data =
    if3_btb_btb_table_target[if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_addr]; // @[BTB.scala 54:32]
  assign if3_btb_btb_table_target_MPORT_data = if3_btb_por_reset ? 39'h80000000 : if3_btb_io_update_bits_target;
  assign if3_btb_btb_table_target_MPORT_addr = if3_btb_por_reset ? if3_btb_reset_cl :
    if3_btb_wr_cl_sel_out_out_out_out_out_1;
  assign if3_btb_btb_table_target_MPORT_mask = 1'h1;
  assign if3_btb_btb_table_target_MPORT_en = if3_btb_por_reset | if3_btb_io_update_valid;
  assign if3_btb_io_req_ready = if3_btb_bypassFifo_io_enq_ready; // @[BTB.scala 75:16]
  assign if3_btb_io_resp_valid = if3_btb_bypassFifo_io_deq_valid; // @[BTB.scala 77:17]
  assign if3_btb_io_resp_bits_target = if3_btb_bypassFifo_io_deq_bits_target; // @[BTB.scala 67:18]
  assign if3_btb_io_isReady = ~if3_btb_por_reset; // @[BTB.scala 49:19]
  assign if3_btb_bypassFifo_clock = if3_btb_clock;
  assign if3_btb_bypassFifo_reset = if3_btb_reset;
  assign if3_btb_bypassFifo_io_enq_valid = if3_btb_bypassFifo_io_enq_valid_REG; // @[BTB.scala 74:27]
  assign if3_btb_bypassFifo_io_enq_bits_target = if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_data; // @[BTB.scala 66:28]
  assign if3_btb_bypassFifo_io_deq_ready = if3_btb_io_resp_ready; // @[BTB.scala 78:27]
  assign if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_en = if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_en_pipe_0;
  assign if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_addr = if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_addr_pipe_0;
  assign if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_data =
    if3_bim_bim_P[if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_addr]; // @[BIM.scala 46:26]
  assign if3_bim_bim_P_MPORT_data = if3_bim_por_reset | if3_bim__T_6;
  assign if3_bim_bim_P_MPORT_addr = if3_bim_por_reset ? if3_bim_reset_cl : if3_bim_wr_cl_out_out_out_out_1;
  assign if3_bim_bim_P_MPORT_mask = 1'h1;
  assign if3_bim_bim_P_MPORT_en = if3_bim_por_reset | if3_bim__T_3;
  assign if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_en = if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_en_pipe_0;
  assign if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_addr = if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_addr_pipe_0;
  assign if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_data =
    if3_bim_bim_H[if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_addr]; // @[BIM.scala 52:26]
  assign if3_bim_bim_H_MPORT_1_data = if3_bim_por_reset ? 1'h0 : if3_bim__T_12;
  assign if3_bim_bim_H_MPORT_1_addr = if3_bim_por_reset ? if3_bim_reset_cl : if3_bim_wr_cl_out_out_out_out_1;
  assign if3_bim_bim_H_MPORT_1_mask = 1'h1;
  assign if3_bim_bim_H_MPORT_1_en = if3_bim_por_reset | if3_bim_io_update_valid;
  assign if3_bim_bypassFifo_ram_0_io_deq_bits_MPORT_en = 1'h1;
  assign if3_bim_bypassFifo_ram_0_io_deq_bits_MPORT_addr = 1'h0;
  assign if3_bim_bypassFifo_ram_0_io_deq_bits_MPORT_data =
    if3_bim_bypassFifo_ram_0[if3_bim_bypassFifo_ram_0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign if3_bim_bypassFifo_ram_0_MPORT_data = if3_bim_bypassFifo_io_enq_bits_0;
  assign if3_bim_bypassFifo_ram_0_MPORT_addr = 1'h0;
  assign if3_bim_bypassFifo_ram_0_MPORT_mask = 1'h1;
  assign if3_bim_bypassFifo_ram_0_MPORT_en = if3_bim_bypassFifo__empty_T ? if3_bim_bypassFifo__GEN_10 :
    if3_bim_bypassFifo__do_enq_T;
  assign if3_bim_bypassFifo_ram_1_io_deq_bits_MPORT_en = 1'h1;
  assign if3_bim_bypassFifo_ram_1_io_deq_bits_MPORT_addr = 1'h0;
  assign if3_bim_bypassFifo_ram_1_io_deq_bits_MPORT_data =
    if3_bim_bypassFifo_ram_1[if3_bim_bypassFifo_ram_1_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign if3_bim_bypassFifo_ram_1_MPORT_data = if3_bim_bypassFifo_io_enq_bits_1;
  assign if3_bim_bypassFifo_ram_1_MPORT_addr = 1'h0;
  assign if3_bim_bypassFifo_ram_1_MPORT_mask = 1'h1;
  assign if3_bim_bypassFifo_ram_1_MPORT_en = if3_bim_bypassFifo__empty_T ? if3_bim_bypassFifo__GEN_10 :
    if3_bim_bypassFifo__do_enq_T;
  assign if3_bim_bypassFifo_io_enq_ready = ~if3_bim_bypassFifo_maybe_full; // @[Decoupled.scala 305:19]
  assign if3_bim_bypassFifo_io_deq_valid = if3_bim_bypassFifo_io_enq_valid | if3_bim_bypassFifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign if3_bim_bypassFifo_io_deq_bits_0 = if3_bim_bypassFifo__empty_T ? if3_bim_bypassFifo_io_enq_bits_0 :
    if3_bim_bypassFifo_ram_0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign if3_bim_bypassFifo_io_deq_bits_1 = if3_bim_bypassFifo__empty_T ? if3_bim_bypassFifo_io_enq_bits_1 :
    if3_bim_bypassFifo_ram_1_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign if3_bim_io_req_ready = if3_bim_bypassFifo_io_enq_ready; // @[BIM.scala 89:161]
  assign if3_bim_io_resp_valid = if3_bim_bypassFifo_io_deq_valid; // @[BIM.scala 90:17]
  assign if3_bim_io_resp_bits_bim_p = if3_bim_bypassFifo_io_deq_bits_0; // @[BIM.scala 90:64]
  assign if3_bim_io_resp_bits_bim_h = if3_bim_bypassFifo_io_deq_bits_1; // @[BIM.scala 90:113]
  assign if3_bim_io_isReady = ~if3_bim_por_reset; // @[BIM.scala 40:17]
  assign if3_bim_bypassFifo_clock = if3_bim_clock;
  assign if3_bim_bypassFifo_reset = if3_bim_reset;
  assign if3_bim_bypassFifo_io_enq_valid = if3_bim_bypassFifo_io_enq_valid_REG; // @[BIM.scala 89:27]
  assign if3_bim_bypassFifo_io_enq_bits_0 = if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_data; // @[BIM.scala 89:78]
  assign if3_bim_bypassFifo_io_enq_bits_1 = if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_data; // @[BIM.scala 89:126]
  assign if3_bim_bypassFifo_io_deq_ready = if3_bim_io_resp_ready; // @[BIM.scala 90:167]
  assign if3_tage_io_resp_valid = 1'h0; // @[TAGE.scala 204:19]
  assign if3_btbFifo_fifo_io_enq_0_ready = ~if3_btbFifo_fifo__GEN_1; // @[MultiPortFifo.scala 64:94]
  assign if3_btbFifo_fifo_io_deq_0_valid = if3_btbFifo_fifo__io_deq_0_valid_T_1 ? if3_btbFifo_fifo_buf_valid_1 :
    if3_btbFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  assign if3_btbFifo_fifo_io_deq_0_bits_target = if3_btbFifo_fifo__io_deq_0_valid_T_1 ? if3_btbFifo_fifo_buf_1_target :
    if3_btbFifo_fifo_buf_0_target; // @[MultiPortFifo.scala 114:{14,14}]
  assign if3_btbFifo_rePortIn_io_enq_0_ready = if3_btbFifo_rePortIn_io_deq_0_ready; // @[RePort.scala 80:69]
  assign if3_btbFifo_rePortIn_io_deq_0_valid = if3_btbFifo_rePortIn__T > 1'h0; // @[RePort.scala 79:81]
  assign if3_btbFifo_rePortIn_io_deq_0_bits_target = if3_btbFifo_rePortIn__T_6 ?
    if3_btbFifo_rePortIn_io_enq_0_bits_target : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_btbFifo_zipPort_io_enq_0_ready = if3_btbFifo_zipPort__T_2 ? 1'h0 : if3_btbFifo_zipPort_io_deq_0_ready; // @[RePort.scala 235:64 242:23]
  assign if3_btbFifo_zipPort_io_enq_1_ready = if3_btbFifo_zipPort__T_2 & if3_btbFifo_zipPort_io_deq_0_ready; // @[RePort.scala 235:64 243:23]
  assign if3_btbFifo_zipPort_io_deq_0_valid = if3_btbFifo_zipPort__T_2 | if3_btbFifo_zipPort_io_enq_0_valid; // @[RePort.scala 235:64 236:23]
  assign if3_btbFifo_zipPort_io_deq_0_bits_target = if3_btbFifo_zipPort__T_2 ? if3_btbFifo_zipPort_io_enq_1_bits_target
     : if3_btbFifo_zipPort_io_enq_0_bits_target; // @[RePort.scala 235:64 239:23]
  assign if3_btbFifo_io_enq_0_ready = if3_btbFifo_rePortIn_io_enq_0_ready; // @[MultiPortFifo.scala 128:23]
  assign if3_btbFifo_io_deq_0_valid = if3_btbFifo_zipPort_io_deq_0_valid; // @[MultiPortFifo.scala 142:27]
  assign if3_btbFifo_io_deq_0_bits_target = if3_btbFifo_zipPort_io_deq_0_bits_target; // @[MultiPortFifo.scala 142:27]
  assign if3_btbFifo_fifo_clock = if3_btbFifo_clock;
  assign if3_btbFifo_fifo_reset = if3_btbFifo_reset;
  assign if3_btbFifo_fifo_io_enq_0_valid = if3_btbFifo_rePortIn_io_deq_0_valid; // @[MultiPortFifo.scala 129:23]
  assign if3_btbFifo_fifo_io_enq_0_bits_target = if3_btbFifo_rePortIn_io_deq_0_bits_target; // @[MultiPortFifo.scala 129:23]
  assign if3_btbFifo_fifo_io_deq_0_ready = if3_btbFifo_zipPort_io_enq_0_ready; // @[MultiPortFifo.scala 132:27]
  assign if3_btbFifo_fifo_io_flush = if3_btbFifo_io_flush; // @[MultiPortFifo.scala 148:21]
  assign if3_btbFifo_rePortIn_clock = if3_btbFifo_clock;
  assign if3_btbFifo_rePortIn_reset = if3_btbFifo_reset;
  assign if3_btbFifo_rePortIn_io_enq_0_valid = if3_btbFifo__T ? 1'h0 : if3_btbFifo_io_enq_0_valid; // @[MultiPortFifo.scala 128:23 151:44 152:36]
  assign if3_btbFifo_rePortIn_io_enq_0_bits_target = if3_btbFifo__T ? 39'h0 : if3_btbFifo_io_enq_0_bits_target; // @[MultiPortFifo.scala 128:23 151:44 153:36]
  assign if3_btbFifo_rePortIn_io_deq_0_ready = if3_btbFifo_fifo_io_enq_0_ready; // @[MultiPortFifo.scala 129:23]
  assign if3_btbFifo_zipPort_io_enq_0_valid = if3_btbFifo_fifo_io_deq_0_valid; // @[MultiPortFifo.scala 132:27]
  assign if3_btbFifo_zipPort_io_enq_0_bits_target = if3_btbFifo_fifo_io_deq_0_bits_target; // @[MultiPortFifo.scala 132:27]
  assign if3_btbFifo_zipPort_io_enq_1_valid = if3_btbFifo_io_enq_0_valid; // @[MultiPortFifo.scala 136:33]
  assign if3_btbFifo_zipPort_io_enq_1_bits_target = if3_btbFifo_io_enq_0_bits_target; // @[MultiPortFifo.scala 137:33]
  assign if3_btbFifo_zipPort_io_deq_0_ready = if3_btbFifo_io_deq_0_ready; // @[MultiPortFifo.scala 142:27]
  assign if3_bimFifo_fifo_io_enq_0_ready = ~if3_bimFifo_fifo__GEN_1; // @[MultiPortFifo.scala 64:94]
  assign if3_bimFifo_fifo_io_deq_0_valid = if3_bimFifo_fifo__io_deq_0_valid_T_1 ? if3_bimFifo_fifo_buf_valid_1 :
    if3_bimFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  assign if3_bimFifo_fifo_io_deq_0_bits_bim_p = if3_bimFifo_fifo__io_deq_0_valid_T_1 ? if3_bimFifo_fifo_buf_1_bim_p :
    if3_bimFifo_fifo_buf_0_bim_p; // @[MultiPortFifo.scala 114:{14,14}]
  assign if3_bimFifo_fifo_io_deq_0_bits_bim_h = if3_bimFifo_fifo__io_deq_0_valid_T_1 ? if3_bimFifo_fifo_buf_1_bim_h :
    if3_bimFifo_fifo_buf_0_bim_h; // @[MultiPortFifo.scala 114:{14,14}]
  assign if3_bimFifo_rePortIn_io_enq_0_ready = if3_bimFifo_rePortIn_io_deq_0_ready; // @[RePort.scala 80:69]
  assign if3_bimFifo_rePortIn_io_deq_0_valid = if3_bimFifo_rePortIn__T > 1'h0; // @[RePort.scala 79:81]
  assign if3_bimFifo_rePortIn_io_deq_0_bits_bim_p = if3_bimFifo_rePortIn__T_6 & if3_bimFifo_rePortIn_io_enq_0_bits_bim_p
    ; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_bimFifo_rePortIn_io_deq_0_bits_bim_h = if3_bimFifo_rePortIn__T_6 & if3_bimFifo_rePortIn_io_enq_0_bits_bim_h
    ; // @[RePort.scala 37:21 75:24 76:22]
  assign if3_bimFifo_zipPort_io_enq_0_ready = if3_bimFifo_zipPort__T_2 ? 1'h0 : if3_bimFifo_zipPort_io_deq_0_ready; // @[RePort.scala 235:64 242:23]
  assign if3_bimFifo_zipPort_io_enq_1_ready = if3_bimFifo_zipPort__T_2 & if3_bimFifo_zipPort_io_deq_0_ready; // @[RePort.scala 235:64 243:23]
  assign if3_bimFifo_zipPort_io_deq_0_valid = if3_bimFifo_zipPort__T_2 | if3_bimFifo_zipPort_io_enq_0_valid; // @[RePort.scala 235:64 236:23]
  assign if3_bimFifo_zipPort_io_deq_0_bits_bim_p = if3_bimFifo_zipPort__T_2 ? if3_bimFifo_zipPort_io_enq_1_bits_bim_p :
    if3_bimFifo_zipPort_io_enq_0_bits_bim_p; // @[RePort.scala 235:64 239:23]
  assign if3_bimFifo_zipPort_io_deq_0_bits_bim_h = if3_bimFifo_zipPort__T_2 ? if3_bimFifo_zipPort_io_enq_1_bits_bim_h :
    if3_bimFifo_zipPort_io_enq_0_bits_bim_h; // @[RePort.scala 235:64 239:23]
  assign if3_bimFifo_io_enq_0_ready = if3_bimFifo_rePortIn_io_enq_0_ready; // @[MultiPortFifo.scala 128:23]
  assign if3_bimFifo_io_deq_0_valid = if3_bimFifo_zipPort_io_deq_0_valid; // @[MultiPortFifo.scala 142:27]
  assign if3_bimFifo_io_deq_0_bits_bim_p = if3_bimFifo_zipPort_io_deq_0_bits_bim_p; // @[MultiPortFifo.scala 142:27]
  assign if3_bimFifo_io_deq_0_bits_bim_h = if3_bimFifo_zipPort_io_deq_0_bits_bim_h; // @[MultiPortFifo.scala 142:27]
  assign if3_bimFifo_fifo_clock = if3_bimFifo_clock;
  assign if3_bimFifo_fifo_reset = if3_bimFifo_reset;
  assign if3_bimFifo_fifo_io_enq_0_valid = if3_bimFifo_rePortIn_io_deq_0_valid; // @[MultiPortFifo.scala 129:23]
  assign if3_bimFifo_fifo_io_enq_0_bits_bim_p = if3_bimFifo_rePortIn_io_deq_0_bits_bim_p; // @[MultiPortFifo.scala 129:23]
  assign if3_bimFifo_fifo_io_enq_0_bits_bim_h = if3_bimFifo_rePortIn_io_deq_0_bits_bim_h; // @[MultiPortFifo.scala 129:23]
  assign if3_bimFifo_fifo_io_deq_0_ready = if3_bimFifo_zipPort_io_enq_0_ready; // @[MultiPortFifo.scala 132:27]
  assign if3_bimFifo_fifo_io_flush = if3_bimFifo_io_flush; // @[MultiPortFifo.scala 148:21]
  assign if3_bimFifo_rePortIn_clock = if3_bimFifo_clock;
  assign if3_bimFifo_rePortIn_reset = if3_bimFifo_reset;
  assign if3_bimFifo_rePortIn_io_enq_0_valid = if3_bimFifo__T ? 1'h0 : if3_bimFifo_io_enq_0_valid; // @[MultiPortFifo.scala 128:23 151:44 152:36]
  assign if3_bimFifo_rePortIn_io_enq_0_bits_bim_p = if3_bimFifo__T ? 1'h0 : if3_bimFifo_io_enq_0_bits_bim_p; // @[MultiPortFifo.scala 128:23 151:44 153:36]
  assign if3_bimFifo_rePortIn_io_enq_0_bits_bim_h = if3_bimFifo__T ? 1'h0 : if3_bimFifo_io_enq_0_bits_bim_h; // @[MultiPortFifo.scala 128:23 151:44 153:36]
  assign if3_bimFifo_rePortIn_io_deq_0_ready = if3_bimFifo_fifo_io_enq_0_ready; // @[MultiPortFifo.scala 129:23]
  assign if3_bimFifo_zipPort_io_enq_0_valid = if3_bimFifo_fifo_io_deq_0_valid; // @[MultiPortFifo.scala 132:27]
  assign if3_bimFifo_zipPort_io_enq_0_bits_bim_p = if3_bimFifo_fifo_io_deq_0_bits_bim_p; // @[MultiPortFifo.scala 132:27]
  assign if3_bimFifo_zipPort_io_enq_0_bits_bim_h = if3_bimFifo_fifo_io_deq_0_bits_bim_h; // @[MultiPortFifo.scala 132:27]
  assign if3_bimFifo_zipPort_io_enq_1_valid = if3_bimFifo_io_enq_0_valid; // @[MultiPortFifo.scala 136:33]
  assign if3_bimFifo_zipPort_io_enq_1_bits_bim_p = if3_bimFifo_io_enq_0_bits_bim_p; // @[MultiPortFifo.scala 137:33]
  assign if3_bimFifo_zipPort_io_enq_1_bits_bim_h = if3_bimFifo_io_enq_0_bits_bim_h; // @[MultiPortFifo.scala 137:33]
  assign if3_bimFifo_zipPort_io_deq_0_ready = if3_bimFifo_io_deq_0_ready; // @[MultiPortFifo.scala 142:27]
  assign if3_tageFifo_fifo_io_enq_0_ready = ~if3_tageFifo_fifo__GEN_1; // @[MultiPortFifo.scala 64:94]
  assign if3_tageFifo_fifo_io_deq_0_valid = if3_tageFifo_fifo__io_deq_0_valid_T_1 ? if3_tageFifo_fifo_buf_valid_1 :
    if3_tageFifo_fifo_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  assign if3_tageFifo_rePortIn_io_enq_0_ready = if3_tageFifo_rePortIn_io_deq_0_ready; // @[RePort.scala 80:69]
  assign if3_tageFifo_rePortIn_io_deq_0_valid = if3_tageFifo_rePortIn__T > 1'h0; // @[RePort.scala 79:81]
  assign if3_tageFifo_zipPort_io_enq_0_ready = if3_tageFifo_zipPort__T_2 ? 1'h0 : if3_tageFifo_zipPort_io_deq_0_ready; // @[RePort.scala 235:64 242:23]
  assign if3_tageFifo_zipPort_io_enq_1_ready = if3_tageFifo_zipPort__T_2 & if3_tageFifo_zipPort_io_deq_0_ready; // @[RePort.scala 235:64 243:23]
  assign if3_tageFifo_zipPort_io_deq_0_valid = if3_tageFifo_zipPort__T_2 | if3_tageFifo_zipPort_io_enq_0_valid; // @[RePort.scala 235:64 236:23]
  assign if3_tageFifo_io_deq_0_valid = if3_tageFifo_zipPort_io_deq_0_valid; // @[MultiPortFifo.scala 142:27]
  assign if3_tageFifo_fifo_clock = if3_tageFifo_clock;
  assign if3_tageFifo_fifo_reset = if3_tageFifo_reset;
  assign if3_tageFifo_fifo_io_enq_0_valid = if3_tageFifo_rePortIn_io_deq_0_valid; // @[MultiPortFifo.scala 129:23]
  assign if3_tageFifo_fifo_io_deq_0_ready = if3_tageFifo_zipPort_io_enq_0_ready; // @[MultiPortFifo.scala 132:27]
  assign if3_tageFifo_fifo_io_flush = if3_tageFifo_io_flush; // @[MultiPortFifo.scala 148:21]
  assign if3_tageFifo_rePortIn_clock = if3_tageFifo_clock;
  assign if3_tageFifo_rePortIn_reset = if3_tageFifo_reset;
  assign if3_tageFifo_rePortIn_io_enq_0_valid = if3_tageFifo__T ? 1'h0 : if3_tageFifo_io_enq_0_valid; // @[MultiPortFifo.scala 128:23 151:44 152:36]
  assign if3_tageFifo_rePortIn_io_deq_0_ready = if3_tageFifo_fifo_io_enq_0_ready; // @[MultiPortFifo.scala 129:23]
  assign if3_tageFifo_zipPort_io_enq_0_valid = if3_tageFifo_fifo_io_deq_0_valid; // @[MultiPortFifo.scala 132:27]
  assign if3_tageFifo_zipPort_io_enq_1_valid = if3_tageFifo_io_enq_0_valid; // @[MultiPortFifo.scala 136:33]
  assign if3_tageFifo_zipPort_io_deq_0_ready = if3_tageFifo_io_deq_0_ready; // @[MultiPortFifo.scala 142:27]
  assign if3_if3_resp_fifo_io_enq_0_ready = ~if3_if3_resp_fifo__GEN_3; // @[MultiPortFifo.scala 64:94]
  assign if3_if3_resp_fifo_io_enq_1_ready = ~if3_if3_resp_fifo__GEN_7; // @[MultiPortFifo.scala 64:94]
  assign if3_if3_resp_fifo_io_enq_2_ready = ~if3_if3_resp_fifo__GEN_11; // @[MultiPortFifo.scala 64:94]
  assign if3_if3_resp_fifo_io_enq_3_ready = ~if3_if3_resp_fifo__GEN_15; // @[MultiPortFifo.scala 64:94]
  assign if3_if3_resp_fifo_io_deq_0_valid = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ?
    if3_if3_resp_fifo_buf_valid_3 : if3_if3_resp_fifo__GEN_18; // @[MultiPortFifo.scala 65:{94,94}]
  assign if3_if3_resp_fifo_io_deq_0_bits_isRVC = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ?
    if3_if3_resp_fifo_buf_3_isRVC : if3_if3_resp_fifo__GEN_660; // @[MultiPortFifo.scala 114:{14,14}]
  assign if3_if3_resp_fifo_io_deq_0_bits_instr = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ?
    if3_if3_resp_fifo_buf_3_instr : if3_if3_resp_fifo__GEN_670; // @[MultiPortFifo.scala 114:{14,14}]
  assign if3_if3_resp_fifo_io_deq_0_bits_pc = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ? if3_if3_resp_fifo_buf_3_pc
     : if3_if3_resp_fifo__GEN_671; // @[MultiPortFifo.scala 114:{14,14}]
  assign if3_if3_resp_fifo_io_deq_0_bits_isRedirect = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ?
    if3_if3_resp_fifo_buf_3_isRedirect : if3_if3_resp_fifo__GEN_673; // @[MultiPortFifo.scala 114:{14,14}]
  assign if3_if3_resp_fifo_io_deq_0_bits_target = 2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1 ?
    if3_if3_resp_fifo_buf_3_target : if3_if3_resp_fifo__GEN_674; // @[MultiPortFifo.scala 114:{14,14}]
  assign if3_io_if3_req_0_ready = if3_is_instr32_0 ? if3__io_if3_req_0_ready_T_3 : if3__io_if3_req_0_ready_T_2; // @[IF3.scala 102:31]
  assign if3_io_if3_req_1_ready = if3__T_3 ? if3__GEN_83 : if3__GEN_34; // @[IF3.scala 101:33]
  assign if3_io_if3_req_2_ready = if3__T_6 ? if3__GEN_130 : if3__GEN_102; // @[IF3.scala 101:33]
  assign if3_io_if3_req_3_ready = if3__T_72 ? if3__GEN_166 : if3__GEN_148; // @[IF3.scala 101:33]
  assign if3_io_if3_resp_0_valid = if3_if3_resp_fifo_io_deq_0_valid; // @[IF3.scala 71:15]
  assign if3_io_if3_resp_0_bits_isRVC = if3_if3_resp_fifo_io_deq_0_bits_isRVC; // @[IF3.scala 71:15]
  assign if3_io_if3_resp_0_bits_instr = if3_if3_resp_fifo_io_deq_0_bits_instr; // @[IF3.scala 71:15]
  assign if3_io_if3_resp_0_bits_pc = if3_if3_resp_fifo_io_deq_0_bits_pc; // @[IF3.scala 71:15]
  assign if3_io_if3_resp_0_bits_isRedirect = if3_if3_resp_fifo_io_deq_0_bits_isRedirect; // @[IF3.scala 71:15]
  assign if3_io_if3_resp_0_bits_target = if3_if3_resp_fifo_io_deq_0_bits_target; // @[IF3.scala 71:15]
  assign if3_io_btbResp_0_valid = if3_btbFifo_io_deq_0_valid; // @[IF3.scala 397:19]
  assign if3_io_btbResp_0_bits_target = if3_btbFifo_io_deq_0_bits_target; // @[IF3.scala 397:19]
  assign if3_io_bimResp_0_valid = if3_bimFifo_io_deq_0_valid; // @[IF3.scala 398:19]
  assign if3_io_bimResp_0_bits_bim_p = if3_bimFifo_io_deq_0_bits_bim_p; // @[IF3.scala 398:19]
  assign if3_io_bimResp_0_bits_bim_h = if3_bimFifo_io_deq_0_bits_bim_h; // @[IF3.scala 398:19]
  assign if3_combPDT_clock = if3_clock;
  assign if3_combPDT_reset = if3_reset;
  assign if3_combPDT_io_enq_0_valid = if3_is_instr32_0 ? if3__reAlign_0_valid_T_5 : if3__reAlign_0_valid_T_21; // @[IF3.scala 102:31]
  assign if3_combPDT_io_enq_0_bits_isRVC = if3_is_instr32_0 ? if3_io_if3_req_1_bits_isFault : 1'h1; // @[IF3.scala 102:31 107:31 138:31]
  assign if3_combPDT_io_enq_0_bits_instr = if3_is_instr32_0 ? if3__reAlign_0_bits_instr_T_1 : {{16'd0},
    if3_io_if3_req_0_bits_instr}; // @[IF3.scala 102:31 106:38 137:33]
  assign if3_combPDT_io_enq_0_bits_pc = if3_io_if3_req_0_bits_pc; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_1_valid = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_308; // @[IF3.scala 234:29 236:26]
  assign if3_combPDT_io_enq_1_bits_isRVC = if3__T_3 & if3__GEN_95; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_1_bits_instr = if3__T_3 ? if3__GEN_71 : 32'h0; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_1_bits_pc = if3__T_3 ? if3_io_if3_req_1_bits_pc : 39'h0; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_2_valid = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_310; // @[IF3.scala 234:29 236:26]
  assign if3_combPDT_io_enq_2_bits_isRVC = if3__T_6 & if3__GEN_141; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_2_bits_instr = if3__T_6 ? if3__GEN_118 : 32'h0; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_2_bits_pc = if3__T_6 ? if3_io_if3_req_2_bits_pc : 39'h0; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_3_valid = if3_is_lock_pipe_0 ? 1'h0 : if3__GEN_312; // @[IF3.scala 234:29 236:26]
  assign if3_combPDT_io_enq_3_bits_isRVC = if3__T_72 & if3__GEN_164; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_3_bits_instr = if3__T_72 ? if3__GEN_154 : 32'h0; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_enq_3_bits_pc = if3__T_72 ? if3__GEN_151 : 39'h0; // @[IF3.scala 101:33 96:22]
  assign if3_combPDT_io_deq_0_ready = if3_if3_resp_fifo_io_enq_0_ready; // @[IF3.scala 70:24]
  assign if3_combPDT_io_deq_1_ready = if3_if3_resp_fifo_io_enq_1_ready; // @[IF3.scala 70:24]
  assign if3_combPDT_io_deq_2_ready = if3_if3_resp_fifo_io_enq_2_ready; // @[IF3.scala 70:24]
  assign if3_combPDT_io_deq_3_ready = if3_if3_resp_fifo_io_enq_3_ready; // @[IF3.scala 70:24]
  assign if3_btb_clock = if3_clock;
  assign if3_btb_reset = if3_reset;
  assign if3_btb_io_req_valid = if3__GEN_23 ? if3__btb_io_req_valid_T_11 : if3__GEN_269; // @[IF3.scala 196:27]
  assign if3_btb_io_req_bits_pc = if3__GEN_23 ? if3_io_if3_req_0_bits_pc : if3__GEN_270; // @[IF3.scala 196:27]
  assign if3_btb_io_resp_ready = if3_btbFifo_io_enq_0_ready; // @[IF3.scala 393:22]
  assign if3_btb_io_update_valid = if3_io_jcmm_update_valid; // @[IF3.scala 284:33]
  assign if3_btb_io_update_bits_target = if3_io_jcmm_update_bits_finalTarget[38:0]; // @[IF3.scala 286:33]
  assign if3_btb_io_update_bits_pc = if3_io_jcmm_update_bits_pc; // @[IF3.scala 285:33]
  assign if3_bim_clock = if3_clock;
  assign if3_bim_reset = if3_reset;
  assign if3_bim_io_req_valid = if3__GEN_24 ? if3__btb_io_req_valid_T_11 : if3__GEN_275; // @[IF3.scala 207:27]
  assign if3_bim_io_req_bits_pc = if3__GEN_24 ? if3_io_if3_req_0_bits_pc : if3__GEN_276; // @[IF3.scala 207:27]
  assign if3_bim_io_resp_ready = if3_bimFifo_io_enq_0_ready; // @[IF3.scala 394:22]
  assign if3_bim_io_update_valid = if3_io_bcmm_update_valid; // @[IF3.scala 288:38]
  assign if3_bim_io_update_bits_bim_p = if3_io_bcmm_update_bits_bimResp_bim_p; // @[IF3.scala 289:60]
  assign if3_bim_io_update_bits_bim_h = if3_io_bcmm_update_bits_bimResp_bim_h; // @[IF3.scala 289:60]
  assign if3_bim_io_update_bits_pc = if3_io_bcmm_update_bits_pc; // @[IF3.scala 290:38]
  assign if3_bim_io_update_bits_isFinalTaken = if3_io_bcmm_update_bits_isFinalTaken; // @[IF3.scala 291:38]
  assign if3_btbFifo_clock = if3_clock;
  assign if3_btbFifo_reset = if3_reset;
  assign if3_btbFifo_io_enq_0_valid = if3_btb_io_resp_valid; // @[IF3.scala 393:22]
  assign if3_btbFifo_io_enq_0_bits_target = if3_btb_io_resp_bits_target; // @[IF3.scala 393:22]
  assign if3_btbFifo_io_deq_0_ready = if3_io_btbResp_0_ready; // @[IF3.scala 397:19]
  assign if3_btbFifo_io_flush = if3_io_flush | if3_io_if4Redirect_valid; // @[IF3.scala 401:33]
  assign if3_bimFifo_clock = if3_clock;
  assign if3_bimFifo_reset = if3_reset;
  assign if3_bimFifo_io_enq_0_valid = if3_bim_io_resp_valid; // @[IF3.scala 394:22]
  assign if3_bimFifo_io_enq_0_bits_bim_p = if3_bim_io_resp_bits_bim_p; // @[IF3.scala 394:22]
  assign if3_bimFifo_io_enq_0_bits_bim_h = if3_bim_io_resp_bits_bim_h; // @[IF3.scala 394:22]
  assign if3_bimFifo_io_deq_0_ready = if3_io_bimResp_0_ready; // @[IF3.scala 398:19]
  assign if3_bimFifo_io_flush = if3_io_flush | if3_io_if4Redirect_valid; // @[IF3.scala 402:33]
  assign if3_tageFifo_clock = if3_clock;
  assign if3_tageFifo_reset = if3_reset;
  assign if3_tageFifo_io_enq_0_valid = if3_tage_io_resp_valid; // @[IF3.scala 395:22]
  assign if3_tageFifo_io_deq_0_ready = if3_io_tageResp_0_ready; // @[IF3.scala 399:19]
  assign if3_tageFifo_io_flush = if3_io_flush | if3_io_if4Redirect_valid; // @[IF3.scala 403:33]
  assign if3_if3_resp_fifo_clock = if3_clock;
  assign if3_if3_resp_fifo_reset = if3_reset;
  assign if3_if3_resp_fifo_io_enq_0_valid = if3_combPDT_io_deq_0_valid; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_0_bits_isRVC = if3_combPDT_io_deq_0_bits_isRVC; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_0_bits_instr = if3_combPDT_io_deq_0_bits_instr; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_0_bits_pc = if3_combPDT_io_deq_0_bits_pc; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_0_bits_isRedirect = if3_combPDT_io_deq_0_bits_isRedirect; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_0_bits_target = if3_combPDT_io_deq_0_bits_target; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_1_valid = if3_combPDT_io_deq_1_valid; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_1_bits_isRVC = if3_combPDT_io_deq_1_bits_isRVC; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_1_bits_instr = if3_combPDT_io_deq_1_bits_instr; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_1_bits_pc = if3_combPDT_io_deq_1_bits_pc; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_1_bits_isRedirect = if3_combPDT_io_deq_1_bits_isRedirect; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_1_bits_target = if3_combPDT_io_deq_1_bits_target; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_2_valid = if3_combPDT_io_deq_2_valid; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_2_bits_isRVC = if3_combPDT_io_deq_2_bits_isRVC; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_2_bits_instr = if3_combPDT_io_deq_2_bits_instr; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_2_bits_pc = if3_combPDT_io_deq_2_bits_pc; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_2_bits_isRedirect = if3_combPDT_io_deq_2_bits_isRedirect; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_2_bits_target = if3_combPDT_io_deq_2_bits_target; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_3_valid = if3_combPDT_io_deq_3_valid; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_3_bits_isRVC = if3_combPDT_io_deq_3_bits_isRVC; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_3_bits_instr = if3_combPDT_io_deq_3_bits_instr; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_3_bits_pc = if3_combPDT_io_deq_3_bits_pc; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_3_bits_isRedirect = if3_combPDT_io_deq_3_bits_isRedirect; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_enq_3_bits_target = if3_combPDT_io_deq_3_bits_target; // @[IF3.scala 70:24]
  assign if3_if3_resp_fifo_io_deq_0_ready = if3_io_if3_resp_0_ready; // @[IF3.scala 71:15]
  assign if3_if3_resp_fifo_io_flush = if3_io_if4Redirect_valid | if3_io_flush; // @[IF3.scala 69:49]
  assign if4_ras_buf_target_io_deq_bits_MPORT_en = 1'h1;
  assign if4_ras_buf_target_io_deq_bits_MPORT_addr = if4_ras__rd_idx_T - 2'h1;
  assign if4_ras_buf_target_io_deq_bits_MPORT_data = if4_ras_buf_target[if4_ras_buf_target_io_deq_bits_MPORT_addr]; // @[RAS.scala 43:18]
  assign if4_ras_buf_target_MPORT_data = if4_ras_io_enq_bits_target;
  assign if4_ras_buf_target_MPORT_addr = if4_ras_top_ptr[1:0];
  assign if4_ras_buf_target_MPORT_mask = 1'h1;
  assign if4_ras_buf_target_MPORT_en = if4_ras_io_enq_valid;
  assign if4_ras_io_deq_valid = ~if4_ras_is_empty; // @[RAS.scala 75:22]
  assign if4_ras_io_deq_bits_target = if4_ras_io_deq_bits_REG_target; // @[RAS.scala 76:19]
  assign if4_instr_fifo_io_enq_0_ready = ~if4_instr_fifo__GEN_1; // @[MultiPortFifo.scala 64:94]
  assign if4_instr_fifo_io_deq_0_valid = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_valid_1 :
    if4_instr_fifo_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_lui = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_lui : if4_instr_fifo_buf_0_alu_isa_lui; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_auipc = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_auipc : if4_instr_fifo_buf_0_alu_isa_auipc; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_addi = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_addi : if4_instr_fifo_buf_0_alu_isa_addi; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_addiw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_addiw : if4_instr_fifo_buf_0_alu_isa_addiw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_slti = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_slti : if4_instr_fifo_buf_0_alu_isa_slti; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_sltiu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_sltiu : if4_instr_fifo_buf_0_alu_isa_sltiu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_xori = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_xori : if4_instr_fifo_buf_0_alu_isa_xori; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_ori = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_ori : if4_instr_fifo_buf_0_alu_isa_ori; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_andi = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_andi : if4_instr_fifo_buf_0_alu_isa_andi; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_slli = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_slli : if4_instr_fifo_buf_0_alu_isa_slli; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_slliw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_slliw : if4_instr_fifo_buf_0_alu_isa_slliw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_srli = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_srli : if4_instr_fifo_buf_0_alu_isa_srli; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_srliw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_srliw : if4_instr_fifo_buf_0_alu_isa_srliw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_srai = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_srai : if4_instr_fifo_buf_0_alu_isa_srai; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_sraiw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_sraiw : if4_instr_fifo_buf_0_alu_isa_sraiw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_add = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_add : if4_instr_fifo_buf_0_alu_isa_add; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_addw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_addw : if4_instr_fifo_buf_0_alu_isa_addw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_sub = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_sub : if4_instr_fifo_buf_0_alu_isa_sub; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_subw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_subw : if4_instr_fifo_buf_0_alu_isa_subw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_sll = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_sll : if4_instr_fifo_buf_0_alu_isa_sll; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_sllw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_sllw : if4_instr_fifo_buf_0_alu_isa_sllw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_slt = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_slt : if4_instr_fifo_buf_0_alu_isa_slt; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_sltu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_sltu : if4_instr_fifo_buf_0_alu_isa_sltu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_xor = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_xor : if4_instr_fifo_buf_0_alu_isa_xor; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_srl = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_srl : if4_instr_fifo_buf_0_alu_isa_srl; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_srlw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_srlw : if4_instr_fifo_buf_0_alu_isa_srlw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_sra = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_sra : if4_instr_fifo_buf_0_alu_isa_sra; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_sraw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_sraw : if4_instr_fifo_buf_0_alu_isa_sraw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_or = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_alu_isa_or
     : if4_instr_fifo_buf_0_alu_isa_or; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_and = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_and : if4_instr_fifo_buf_0_alu_isa_and; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_alu_isa_wfi = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_alu_isa_wfi : if4_instr_fifo_buf_0_alu_isa_wfi; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_bru_isa_jal = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_bru_isa_jal : if4_instr_fifo_buf_0_bru_isa_jal; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_bru_isa_jalr = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_bru_isa_jalr : if4_instr_fifo_buf_0_bru_isa_jalr; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_bru_isa_beq = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_bru_isa_beq : if4_instr_fifo_buf_0_bru_isa_beq; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_bru_isa_bne = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_bru_isa_bne : if4_instr_fifo_buf_0_bru_isa_bne; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_bru_isa_blt = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_bru_isa_blt : if4_instr_fifo_buf_0_bru_isa_blt; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_bru_isa_bge = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_bru_isa_bge : if4_instr_fifo_buf_0_bru_isa_bge; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_bru_isa_bltu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_bru_isa_bltu : if4_instr_fifo_buf_0_bru_isa_bltu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_bru_isa_bgeu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_bru_isa_bgeu : if4_instr_fifo_buf_0_bru_isa_bgeu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_lb = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_lsu_isa_lb
     : if4_instr_fifo_buf_0_lsu_isa_lb; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_lh = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_lsu_isa_lh
     : if4_instr_fifo_buf_0_lsu_isa_lh; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_lw = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_lsu_isa_lw
     : if4_instr_fifo_buf_0_lsu_isa_lw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_ld = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_lsu_isa_ld
     : if4_instr_fifo_buf_0_lsu_isa_ld; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_lbu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_lbu : if4_instr_fifo_buf_0_lsu_isa_lbu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_lhu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_lhu : if4_instr_fifo_buf_0_lsu_isa_lhu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_lwu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_lwu : if4_instr_fifo_buf_0_lsu_isa_lwu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_sb = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_lsu_isa_sb
     : if4_instr_fifo_buf_0_lsu_isa_sb; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_sh = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_lsu_isa_sh
     : if4_instr_fifo_buf_0_lsu_isa_sh; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_sw = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_lsu_isa_sw
     : if4_instr_fifo_buf_0_lsu_isa_sw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_sd = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_lsu_isa_sd
     : if4_instr_fifo_buf_0_lsu_isa_sd; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_fence = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_fence : if4_instr_fifo_buf_0_lsu_isa_fence; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_fence_i = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_fence_i : if4_instr_fifo_buf_0_lsu_isa_fence_i; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_sfence_vma = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_sfence_vma : if4_instr_fifo_buf_0_lsu_isa_sfence_vma; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_lr_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_lr_w : if4_instr_fifo_buf_0_lsu_isa_lr_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_sc_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_sc_w : if4_instr_fifo_buf_0_lsu_isa_sc_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoswap_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoswap_w : if4_instr_fifo_buf_0_lsu_isa_amoswap_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoadd_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoadd_w : if4_instr_fifo_buf_0_lsu_isa_amoadd_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoxor_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoxor_w : if4_instr_fifo_buf_0_lsu_isa_amoxor_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoand_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoand_w : if4_instr_fifo_buf_0_lsu_isa_amoand_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoor_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoor_w : if4_instr_fifo_buf_0_lsu_isa_amoor_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amomin_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amomin_w : if4_instr_fifo_buf_0_lsu_isa_amomin_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amomax_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amomax_w : if4_instr_fifo_buf_0_lsu_isa_amomax_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amominu_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amominu_w : if4_instr_fifo_buf_0_lsu_isa_amominu_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amomaxu_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amomaxu_w : if4_instr_fifo_buf_0_lsu_isa_amomaxu_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_lr_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_lr_d : if4_instr_fifo_buf_0_lsu_isa_lr_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_sc_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_sc_d : if4_instr_fifo_buf_0_lsu_isa_sc_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoswap_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoswap_d : if4_instr_fifo_buf_0_lsu_isa_amoswap_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoadd_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoadd_d : if4_instr_fifo_buf_0_lsu_isa_amoadd_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoxor_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoxor_d : if4_instr_fifo_buf_0_lsu_isa_amoxor_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoand_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoand_d : if4_instr_fifo_buf_0_lsu_isa_amoand_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amoor_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amoor_d : if4_instr_fifo_buf_0_lsu_isa_amoor_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amomin_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amomin_d : if4_instr_fifo_buf_0_lsu_isa_amomin_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amomax_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amomax_d : if4_instr_fifo_buf_0_lsu_isa_amomax_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amominu_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amominu_d : if4_instr_fifo_buf_0_lsu_isa_amominu_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_amomaxu_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_amomaxu_d : if4_instr_fifo_buf_0_lsu_isa_amomaxu_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_flw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_flw : if4_instr_fifo_buf_0_lsu_isa_flw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_fsw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_fsw : if4_instr_fifo_buf_0_lsu_isa_fsw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_fld = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_fld : if4_instr_fifo_buf_0_lsu_isa_fld; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_lsu_isa_fsd = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_lsu_isa_fsd : if4_instr_fifo_buf_0_lsu_isa_fsd; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_csr_isa_rw = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_csr_isa_rw
     : if4_instr_fifo_buf_0_csr_isa_rw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_csr_isa_rs = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_csr_isa_rs
     : if4_instr_fifo_buf_0_csr_isa_rs; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_csr_isa_rc = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_csr_isa_rc
     : if4_instr_fifo_buf_0_csr_isa_rc; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_csr_isa_rwi = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_csr_isa_rwi : if4_instr_fifo_buf_0_csr_isa_rwi; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_csr_isa_rsi = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_csr_isa_rsi : if4_instr_fifo_buf_0_csr_isa_rsi; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_csr_isa_rci = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_csr_isa_rci : if4_instr_fifo_buf_0_csr_isa_rci; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_mul = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_mul : if4_instr_fifo_buf_0_mul_isa_mul; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_mulh = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_mulh : if4_instr_fifo_buf_0_mul_isa_mulh; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_mulhsu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_mulhsu : if4_instr_fifo_buf_0_mul_isa_mulhsu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_mulhu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_mulhu : if4_instr_fifo_buf_0_mul_isa_mulhu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_div = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_div : if4_instr_fifo_buf_0_mul_isa_div; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_divu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_divu : if4_instr_fifo_buf_0_mul_isa_divu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_rem = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_rem : if4_instr_fifo_buf_0_mul_isa_rem; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_remu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_remu : if4_instr_fifo_buf_0_mul_isa_remu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_mulw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_mulw : if4_instr_fifo_buf_0_mul_isa_mulw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_divw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_divw : if4_instr_fifo_buf_0_mul_isa_divw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_divuw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_divuw : if4_instr_fifo_buf_0_mul_isa_divuw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_remw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_remw : if4_instr_fifo_buf_0_mul_isa_remw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_mul_isa_remuw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_mul_isa_remuw : if4_instr_fifo_buf_0_mul_isa_remuw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_ecall = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_ecall : if4_instr_fifo_buf_0_privil_isa_ecall; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_ebreak = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_ebreak : if4_instr_fifo_buf_0_privil_isa_ebreak; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_mret = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_mret : if4_instr_fifo_buf_0_privil_isa_mret; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_uret = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_uret : if4_instr_fifo_buf_0_privil_isa_uret; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_sret = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_sret : if4_instr_fifo_buf_0_privil_isa_sret; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_dret = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_dret : if4_instr_fifo_buf_0_privil_isa_dret; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hfence_vvma = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hfence_vvma : if4_instr_fifo_buf_0_privil_isa_hfence_vvma; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hfence_gvma = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hfence_gvma : if4_instr_fifo_buf_0_privil_isa_hfence_gvma; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_b = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlv_b : if4_instr_fifo_buf_0_privil_isa_hlv_b; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_bu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlv_bu : if4_instr_fifo_buf_0_privil_isa_hlv_bu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_h = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlv_h : if4_instr_fifo_buf_0_privil_isa_hlv_h; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_hu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlv_hu : if4_instr_fifo_buf_0_privil_isa_hlv_hu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlvx_hu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlvx_hu : if4_instr_fifo_buf_0_privil_isa_hlvx_hu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlv_w : if4_instr_fifo_buf_0_privil_isa_hlv_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlvx_wu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlvx_wu : if4_instr_fifo_buf_0_privil_isa_hlvx_wu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_b = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hsv_b : if4_instr_fifo_buf_0_privil_isa_hsv_b; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_h = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hsv_h : if4_instr_fifo_buf_0_privil_isa_hsv_h; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hsv_w : if4_instr_fifo_buf_0_privil_isa_hsv_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_wu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlv_wu : if4_instr_fifo_buf_0_privil_isa_hlv_wu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hlv_d : if4_instr_fifo_buf_0_privil_isa_hlv_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_hsv_d : if4_instr_fifo_buf_0_privil_isa_hsv_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_is_access_fault = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_is_access_fault : if4_instr_fifo_buf_0_privil_isa_is_access_fault; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_privil_isa_is_paging_fault = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_privil_isa_is_paging_fault : if4_instr_fifo_buf_0_privil_isa_is_paging_fault; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmadd_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmadd_s : if4_instr_fifo_buf_0_fpu_isa_fmadd_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmsub_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmsub_s : if4_instr_fifo_buf_0_fpu_isa_fmsub_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmsub_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fnmsub_s : if4_instr_fifo_buf_0_fpu_isa_fnmsub_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmadd_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fnmadd_s : if4_instr_fifo_buf_0_fpu_isa_fnmadd_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fadd_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fadd_s : if4_instr_fifo_buf_0_fpu_isa_fadd_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsub_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsub_s : if4_instr_fifo_buf_0_fpu_isa_fsub_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmul_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmul_s : if4_instr_fifo_buf_0_fpu_isa_fmul_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fdiv_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fdiv_s : if4_instr_fifo_buf_0_fpu_isa_fdiv_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsqrt_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsqrt_s : if4_instr_fifo_buf_0_fpu_isa_fsqrt_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnj_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsgnj_s : if4_instr_fifo_buf_0_fpu_isa_fsgnj_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjn_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsgnjn_s : if4_instr_fifo_buf_0_fpu_isa_fsgnjn_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjx_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsgnjx_s : if4_instr_fifo_buf_0_fpu_isa_fsgnjx_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmin_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmin_s : if4_instr_fifo_buf_0_fpu_isa_fmin_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmax_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmax_s : if4_instr_fifo_buf_0_fpu_isa_fmax_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_w_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_w_s : if4_instr_fifo_buf_0_fpu_isa_fcvt_w_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_wu_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_s : if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_x_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmv_x_w : if4_instr_fifo_buf_0_fpu_isa_fmv_x_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_feq_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_feq_s : if4_instr_fifo_buf_0_fpu_isa_feq_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_flt_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_flt_s : if4_instr_fifo_buf_0_fpu_isa_flt_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fle_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fle_s : if4_instr_fifo_buf_0_fpu_isa_fle_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fclass_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fclass_s : if4_instr_fifo_buf_0_fpu_isa_fclass_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_s_w : if4_instr_fifo_buf_0_fpu_isa_fcvt_s_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_wu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_s_wu : if4_instr_fifo_buf_0_fpu_isa_fcvt_s_wu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_w_x = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmv_w_x : if4_instr_fifo_buf_0_fpu_isa_fmv_w_x; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_l_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_l_s : if4_instr_fifo_buf_0_fpu_isa_fcvt_l_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_lu_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_s : if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_l = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_s_l : if4_instr_fifo_buf_0_fpu_isa_fcvt_s_l; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_lu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_s_lu : if4_instr_fifo_buf_0_fpu_isa_fcvt_s_lu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmadd_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmadd_d : if4_instr_fifo_buf_0_fpu_isa_fmadd_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmsub_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmsub_d : if4_instr_fifo_buf_0_fpu_isa_fmsub_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmsub_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fnmsub_d : if4_instr_fifo_buf_0_fpu_isa_fnmsub_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmadd_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fnmadd_d : if4_instr_fifo_buf_0_fpu_isa_fnmadd_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fadd_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fadd_d : if4_instr_fifo_buf_0_fpu_isa_fadd_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsub_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsub_d : if4_instr_fifo_buf_0_fpu_isa_fsub_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmul_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmul_d : if4_instr_fifo_buf_0_fpu_isa_fmul_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fdiv_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fdiv_d : if4_instr_fifo_buf_0_fpu_isa_fdiv_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsqrt_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsqrt_d : if4_instr_fifo_buf_0_fpu_isa_fsqrt_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnj_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsgnj_d : if4_instr_fifo_buf_0_fpu_isa_fsgnj_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjn_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsgnjn_d : if4_instr_fifo_buf_0_fpu_isa_fsgnjn_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjx_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fsgnjx_d : if4_instr_fifo_buf_0_fpu_isa_fsgnjx_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmin_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmin_d : if4_instr_fifo_buf_0_fpu_isa_fmin_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmax_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmax_d : if4_instr_fifo_buf_0_fpu_isa_fmax_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_s_d : if4_instr_fifo_buf_0_fpu_isa_fcvt_s_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_s = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_d_s : if4_instr_fifo_buf_0_fpu_isa_fcvt_d_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_feq_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_feq_d : if4_instr_fifo_buf_0_fpu_isa_feq_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_flt_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_flt_d : if4_instr_fifo_buf_0_fpu_isa_flt_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fle_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fle_d : if4_instr_fifo_buf_0_fpu_isa_fle_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fclass_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fclass_d : if4_instr_fifo_buf_0_fpu_isa_fclass_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_w_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_w_d : if4_instr_fifo_buf_0_fpu_isa_fcvt_w_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_wu_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_d : if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_w = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_d_w : if4_instr_fifo_buf_0_fpu_isa_fcvt_d_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_wu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_d_wu : if4_instr_fifo_buf_0_fpu_isa_fcvt_d_wu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_l_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_l_d : if4_instr_fifo_buf_0_fpu_isa_fcvt_l_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_lu_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_d : if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_x_d = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmv_x_d : if4_instr_fifo_buf_0_fpu_isa_fmv_x_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_l = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_d_l : if4_instr_fifo_buf_0_fpu_isa_fcvt_d_l; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_lu = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcvt_d_lu : if4_instr_fifo_buf_0_fpu_isa_fcvt_d_lu; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_d_x = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fmv_d_x : if4_instr_fifo_buf_0_fpu_isa_fmv_d_x; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rw = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcsr_rw : if4_instr_fifo_buf_0_fpu_isa_fcsr_rw; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rs = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcsr_rs : if4_instr_fifo_buf_0_fpu_isa_fcsr_rs; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rc = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcsr_rc : if4_instr_fifo_buf_0_fpu_isa_fcsr_rc; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rwi = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcsr_rwi : if4_instr_fifo_buf_0_fpu_isa_fcsr_rwi; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rsi = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcsr_rsi : if4_instr_fifo_buf_0_fpu_isa_fcsr_rsi; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rci = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_fpu_isa_fcsr_rci : if4_instr_fifo_buf_0_fpu_isa_fcsr_rci; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_param_is_rvc = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_param_is_rvc : if4_instr_fifo_buf_0_param_is_rvc; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_param_pc = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_param_pc :
    if4_instr_fifo_buf_0_param_pc; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_param_imm = if4_instr_fifo__io_deq_0_valid_T_1 ? if4_instr_fifo_buf_1_param_imm :
    if4_instr_fifo_buf_0_param_imm; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_param_raw_rs1 = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_param_raw_rs1 : if4_instr_fifo_buf_0_param_raw_rs1; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_param_raw_rs2 = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_param_raw_rs2 : if4_instr_fifo_buf_0_param_raw_rs2; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_instr_fifo_io_deq_0_bits_param_raw_rd0 = if4_instr_fifo__io_deq_0_valid_T_1 ?
    if4_instr_fifo_buf_1_param_raw_rd0 : if4_instr_fifo_buf_0_param_raw_rd0; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_bftq_io_enq_0_ready = ~if4_bftq__GEN_1; // @[MultiPortFifo.scala 64:94]
  assign if4_bftq_io_deq_0_valid = if4_bftq__io_deq_0_valid_T_1 ? if4_bftq_buf_valid_1 : if4_bftq_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  assign if4_bftq_io_deq_0_bits_pc = if4_bftq__io_deq_0_valid_T_1 ? if4_bftq_buf_1_pc : if4_bftq_buf_0_pc; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_bftq_io_deq_0_bits_bimResp_bim_p = if4_bftq__io_deq_0_valid_T_1 ? if4_bftq_buf_1_bimResp_bim_p :
    if4_bftq_buf_0_bimResp_bim_p; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_bftq_io_deq_0_bits_bimResp_bim_h = if4_bftq__io_deq_0_valid_T_1 ? if4_bftq_buf_1_bimResp_bim_h :
    if4_bftq_buf_0_bimResp_bim_h; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_bftq_io_deq_0_bits_isPredictTaken = if4_bftq__io_deq_0_valid_T_1 ? if4_bftq_buf_1_isPredictTaken :
    if4_bftq_buf_0_isPredictTaken; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_jftq_io_enq_0_ready = ~if4_jftq__GEN_1; // @[MultiPortFifo.scala 64:94]
  assign if4_jftq_io_deq_0_valid = if4_jftq__io_deq_0_valid_T_1 ? if4_jftq_buf_valid_1 : if4_jftq_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  assign if4_jftq_io_deq_0_bits_pc = if4_jftq__io_deq_0_valid_T_1 ? if4_jftq_buf_1_pc : if4_jftq_buf_0_pc; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_jftq_io_deq_0_bits_btbResp_target = if4_jftq__io_deq_0_valid_T_1 ? if4_jftq_buf_1_btbResp_target :
    if4_jftq_buf_0_btbResp_target; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_jftq_io_deq_0_bits_rasResp_target = if4_jftq__io_deq_0_valid_T_1 ? if4_jftq_buf_1_rasResp_target :
    if4_jftq_buf_0_rasResp_target; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_jftq_io_deq_0_bits_isRas = if4_jftq__io_deq_0_valid_T_1 ? if4_jftq_buf_1_isRas : if4_jftq_buf_0_isRas; // @[MultiPortFifo.scala 114:{14,14}]
  assign if4_bRePort_io_enq_0_ready = if4_bRePort_io_deq_0_ready; // @[RePort.scala 80:69]
  assign if4_bRePort_io_deq_0_valid = if4_bRePort__T > 1'h0; // @[RePort.scala 79:81]
  assign if4_bRePort_io_deq_0_bits_pc = if4_bRePort__T_6 ? if4_bRePort_io_enq_0_bits_pc : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if4_bRePort_io_deq_0_bits_bimResp_bim_p = if4_bRePort__T_6 & if4_bRePort_io_enq_0_bits_bimResp_bim_p; // @[RePort.scala 37:21 75:24 76:22]
  assign if4_bRePort_io_deq_0_bits_bimResp_bim_h = if4_bRePort__T_6 & if4_bRePort_io_enq_0_bits_bimResp_bim_h; // @[RePort.scala 37:21 75:24 76:22]
  assign if4_bRePort_io_deq_0_bits_isPredictTaken = if4_bRePort__T_6 & if4_bRePort_io_enq_0_bits_isPredictTaken; // @[RePort.scala 37:21 75:24 76:22]
  assign if4_jRePort_io_enq_0_ready = if4_jRePort_io_deq_0_ready; // @[RePort.scala 80:69]
  assign if4_jRePort_io_deq_0_valid = if4_jRePort__T > 1'h0; // @[RePort.scala 79:81]
  assign if4_jRePort_io_deq_0_bits_pc = if4_jRePort__T_6 ? if4_jRePort_io_enq_0_bits_pc : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if4_jRePort_io_deq_0_bits_btbResp_target = if4_jRePort__T_6 ? if4_jRePort_io_enq_0_bits_btbResp_target : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if4_jRePort_io_deq_0_bits_rasResp_target = if4_jRePort__T_6 ? if4_jRePort_io_enq_0_bits_rasResp_target : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign if4_jRePort_io_deq_0_bits_isRas = if4_jRePort__T_6 & if4_jRePort_io_enq_0_bits_isRas; // @[RePort.scala 37:21 75:24 76:22]
  assign if4_tageRedirect_mdl_io_enq_0_ready = 1'h0; // @[RePort.scala 161:22 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_0_use = 2'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_0_is_hit = 1'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_1_use = 2'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_1_is_hit = 1'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_2_use = 2'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_2_is_hit = 1'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_3_use = 2'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_3_is_hit = 1'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_4_use = 2'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_4_is_hit = 1'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_5_use = 2'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_tageRedirect_mdl_io_deq_0_bits_5_is_hit = 1'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_bimRedirect_mdl_io_enq_0_ready = if4_bimRedirect_mdl_io_mapper_0 & if4_bimRedirect_mdl_io_deq_0_ready; // @[RePort.scala 161:22 180:{28,40}]
  assign if4_bimRedirect_mdl_io_deq_0_valid = if4_bimRedirect_mdl_io_mapper_0 & if4_bimRedirect_mdl_io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign if4_bimRedirect_mdl_io_deq_0_bits_bim_p = if4_bimRedirect_mdl_io_mapper_0 &
    if4_bimRedirect_mdl_io_enq_0_bits_bim_p; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_bimRedirect_mdl_io_deq_0_bits_bim_h = if4_bimRedirect_mdl_io_mapper_0 &
    if4_bimRedirect_mdl_io_enq_0_bits_bim_h; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_btbRedirect_mdl_io_enq_0_ready = if4_btbRedirect_mdl_io_mapper_0 & if4_btbRedirect_mdl_io_deq_0_ready; // @[RePort.scala 161:22 180:{28,40}]
  assign if4_btbRedirect_mdl_io_deq_0_valid = if4_btbRedirect_mdl_io_mapper_0 & if4_btbRedirect_mdl_io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign if4_btbRedirect_mdl_io_deq_0_bits_target = if4_btbRedirect_mdl_io_mapper_0 ?
    if4_btbRedirect_mdl_io_enq_0_bits_target : 39'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_lui =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_55 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_57; // @[Decoder.scala 73:94]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_auipc = 1'h0; // @[Decoder.scala 42:18 278:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addi =
    if4_instr_fifo_io_enq_0_bits_dec16__info_alu_isa_addi_T_19 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_50; // @[Decoder.scala 279:66]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addiw =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_30 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 70:74]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slti = 1'h0; // @[Decoder.scala 42:18 281:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sltiu = 1'h0; // @[Decoder.scala 42:18 282:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_xori = 1'h0; // @[Decoder.scala 42:18 283:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_ori = 1'h0; // @[Decoder.scala 42:18 284:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_andi = 16'h8801 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_60; // @[Decoder.scala 77:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slli =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_113 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_26; // @[Decoder.scala 87:74]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slliw = 1'h0; // @[Decoder.scala 42:18 287:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srli =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_61 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_49; // @[Decoder.scala 74:74]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srliw = 1'h0; // @[Decoder.scala 42:18 289:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srai =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_70 &
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_49; // @[Decoder.scala 75:74]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sraiw = 1'h0; // @[Decoder.scala 42:18 291:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_add =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_143 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_159; // @[Decoder.scala 292:36]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addw = 16'h9c21 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 83:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sub = 16'h8c01 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 78:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_subw = 16'h9c01 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 82:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sll = 1'h0; // @[Decoder.scala 42:18 296:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sllw = 1'h0; // @[Decoder.scala 42:18 297:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slt = 1'h0; // @[Decoder.scala 42:18 298:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sltu = 1'h0; // @[Decoder.scala 42:18 299:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_xor = 16'h8c21 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 79:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srl = 1'h0; // @[Decoder.scala 42:18 301:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srlw = 1'h0; // @[Decoder.scala 42:18 302:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sra = 1'h0; // @[Decoder.scala 42:18 303:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sraw = 1'h0; // @[Decoder.scala 42:18 304:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_or = 16'h8c41 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 80:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_and = 16'h8c61 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_82; // @[Decoder.scala 81:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_wfi = 1'h0; // @[Decoder.scala 42:18 307:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_jal = 16'ha001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 84:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_jalr =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_135 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_151; // @[Decoder.scala 310:36]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_beq = 16'hc001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 85:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bne = 16'he001 ==
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T; // @[Decoder.scala 86:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_blt = 1'h0; // @[Decoder.scala 42:18 313:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bge = 1'h0; // @[Decoder.scala 42:18 314:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bltu = 1'h0; // @[Decoder.scala 42:18 315:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bgeu = 1'h0; // @[Decoder.scala 42:18 316:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lb = 1'h0; // @[Decoder.scala 42:18 318:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lh = 1'h0; // @[Decoder.scala 42:18 319:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lw =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_10 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_123; // @[Decoder.scala 320:36]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_ld =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_14 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_129; // @[Decoder.scala 321:36]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lbu = 1'h0; // @[Decoder.scala 42:18 322:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lhu = 1'h0; // @[Decoder.scala 42:18 323:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lwu = 1'h0; // @[Decoder.scala 42:18 324:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sb = 1'h0; // @[Decoder.scala 42:18 325:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sh = 1'h0; // @[Decoder.scala 42:18 326:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sw =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_18 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_162; // @[Decoder.scala 327:36]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sd =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_20 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_164; // @[Decoder.scala 328:36]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fence = 1'h0; // @[Decoder.scala 42:18 329:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fence_i = 1'h0; // @[Decoder.scala 42:18 330:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sfence_vma = 1'h0; // @[Decoder.scala 42:18 331:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lr_w = 1'h0; // @[Decoder.scala 42:18 380:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sc_w = 1'h0; // @[Decoder.scala 42:18 381:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoswap_w = 1'h0; // @[Decoder.scala 42:18 382:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoadd_w = 1'h0; // @[Decoder.scala 42:18 383:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoxor_w = 1'h0; // @[Decoder.scala 42:18 384:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoand_w = 1'h0; // @[Decoder.scala 42:18 385:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoor_w = 1'h0; // @[Decoder.scala 42:18 386:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomin_w = 1'h0; // @[Decoder.scala 42:18 387:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomax_w = 1'h0; // @[Decoder.scala 42:18 388:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amominu_w = 1'h0; // @[Decoder.scala 42:18 389:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomaxu_w = 1'h0; // @[Decoder.scala 42:18 390:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lr_d = 1'h0; // @[Decoder.scala 42:18 391:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sc_d = 1'h0; // @[Decoder.scala 42:18 392:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoswap_d = 1'h0; // @[Decoder.scala 42:18 393:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoadd_d = 1'h0; // @[Decoder.scala 42:18 394:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoxor_d = 1'h0; // @[Decoder.scala 42:18 395:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoand_d = 1'h0; // @[Decoder.scala 42:18 396:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoor_d = 1'h0; // @[Decoder.scala 42:18 397:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomin_d = 1'h0; // @[Decoder.scala 42:18 398:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomax_d = 1'h0; // @[Decoder.scala 42:18 399:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amominu_d = 1'h0; // @[Decoder.scala 42:18 400:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomaxu_d = 1'h0; // @[Decoder.scala 42:18 401:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_flw = 1'h0; // @[Decoder.scala 42:18 403:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fsw = 1'h0; // @[Decoder.scala 42:18 404:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fld = 1'h0; // @[Decoder.scala 434:37]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fsd = 1'h0; // @[Decoder.scala 435:37]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rw = 1'h0; // @[Decoder.scala 42:18 333:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rs = 1'h0; // @[Decoder.scala 42:18 334:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rc = 1'h0; // @[Decoder.scala 42:18 335:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rwi = 1'h0; // @[Decoder.scala 42:18 336:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rsi = 1'h0; // @[Decoder.scala 42:18 337:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rci = 1'h0; // @[Decoder.scala 42:18 338:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mul = 1'h0; // @[Decoder.scala 42:18 340:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulh = 1'h0; // @[Decoder.scala 42:18 341:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulhsu = 1'h0; // @[Decoder.scala 42:18 342:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulhu = 1'h0; // @[Decoder.scala 42:18 343:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_div = 1'h0; // @[Decoder.scala 42:18 344:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divu = 1'h0; // @[Decoder.scala 42:18 345:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_rem = 1'h0; // @[Decoder.scala 42:18 346:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remu = 1'h0; // @[Decoder.scala 42:18 347:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulw = 1'h0; // @[Decoder.scala 42:18 348:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divw = 1'h0; // @[Decoder.scala 42:18 349:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divuw = 1'h0; // @[Decoder.scala 42:18 350:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remw = 1'h0; // @[Decoder.scala 42:18 351:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remuw = 1'h0; // @[Decoder.scala 42:18 352:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_ecall = 1'h0; // @[Decoder.scala 42:18 354:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_ebreak = 16'h9002 ==
    if4_instr_fifo_io_enq_0_bits_dec16_io_x; // @[Decoder.scala 93:24]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_mret = 1'h0; // @[Decoder.scala 42:18 356:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_uret = 1'h0; // @[Decoder.scala 42:18 357:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_sret = 1'h0; // @[Decoder.scala 42:18 358:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_dret = 1'h0; // @[Decoder.scala 42:18 359:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hfence_vvma = 1'h0; // @[Decoder.scala 42:18 363:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hfence_gvma = 1'h0; // @[Decoder.scala 42:18 364:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_b = 1'h0; // @[Decoder.scala 42:18 366:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_bu = 1'h0; // @[Decoder.scala 42:18 367:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_h = 1'h0; // @[Decoder.scala 42:18 368:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_hu = 1'h0; // @[Decoder.scala 42:18 369:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlvx_hu = 1'h0; // @[Decoder.scala 42:18 370:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_w = 1'h0; // @[Decoder.scala 42:18 371:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlvx_wu = 1'h0; // @[Decoder.scala 42:18 372:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_b = 1'h0; // @[Decoder.scala 42:18 373:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_h = 1'h0; // @[Decoder.scala 42:18 374:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_w = 1'h0; // @[Decoder.scala 42:18 375:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_wu = 1'h0; // @[Decoder.scala 42:18 376:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_d = 1'h0; // @[Decoder.scala 42:18 377:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_d = 1'h0; // @[Decoder.scala 42:18 378:31]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_is_access_fault = 16'h9c41 ==
    if4_instr_fifo_io_enq_0_bits_dec16_io_x; // @[Decoder.scala 473:42]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_is_paging_fault = 16'h9c45 ==
    if4_instr_fifo_io_enq_0_bits_dec16_io_x; // @[Decoder.scala 474:42]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmadd_s = 1'h0; // @[Decoder.scala 42:18 405:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmsub_s = 1'h0; // @[Decoder.scala 42:18 406:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmsub_s = 1'h0; // @[Decoder.scala 42:18 407:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmadd_s = 1'h0; // @[Decoder.scala 42:18 408:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fadd_s = 1'h0; // @[Decoder.scala 42:18 409:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsub_s = 1'h0; // @[Decoder.scala 42:18 410:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmul_s = 1'h0; // @[Decoder.scala 42:18 411:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fdiv_s = 1'h0; // @[Decoder.scala 42:18 412:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsqrt_s = 1'h0; // @[Decoder.scala 42:18 413:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnj_s = 1'h0; // @[Decoder.scala 42:18 414:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjn_s = 1'h0; // @[Decoder.scala 42:18 415:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjx_s = 1'h0; // @[Decoder.scala 42:18 416:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmin_s = 1'h0; // @[Decoder.scala 42:18 417:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmax_s = 1'h0; // @[Decoder.scala 42:18 418:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_w_s = 1'h0; // @[Decoder.scala 42:18 419:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_wu_s = 1'h0; // @[Decoder.scala 42:18 420:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_x_w = 1'h0; // @[Decoder.scala 42:18 421:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_feq_s = 1'h0; // @[Decoder.scala 42:18 422:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_flt_s = 1'h0; // @[Decoder.scala 42:18 423:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fle_s = 1'h0; // @[Decoder.scala 42:18 424:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fclass_s = 1'h0; // @[Decoder.scala 42:18 425:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_w = 1'h0; // @[Decoder.scala 42:18 426:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_wu = 1'h0; // @[Decoder.scala 42:18 427:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_w_x = 1'h0; // @[Decoder.scala 42:18 428:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_l_s = 1'h0; // @[Decoder.scala 42:18 429:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_lu_s = 1'h0; // @[Decoder.scala 42:18 430:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_l = 1'h0; // @[Decoder.scala 42:18 431:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_lu = 1'h0; // @[Decoder.scala 42:18 432:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmadd_d = 1'h0; // @[Decoder.scala 42:18 436:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmsub_d = 1'h0; // @[Decoder.scala 42:18 437:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmsub_d = 1'h0; // @[Decoder.scala 42:18 438:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmadd_d = 1'h0; // @[Decoder.scala 42:18 439:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fadd_d = 1'h0; // @[Decoder.scala 42:18 440:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsub_d = 1'h0; // @[Decoder.scala 42:18 441:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmul_d = 1'h0; // @[Decoder.scala 42:18 442:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fdiv_d = 1'h0; // @[Decoder.scala 42:18 443:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsqrt_d = 1'h0; // @[Decoder.scala 42:18 444:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnj_d = 1'h0; // @[Decoder.scala 42:18 445:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjn_d = 1'h0; // @[Decoder.scala 42:18 446:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjx_d = 1'h0; // @[Decoder.scala 42:18 447:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmin_d = 1'h0; // @[Decoder.scala 42:18 448:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmax_d = 1'h0; // @[Decoder.scala 42:18 449:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_d = 1'h0; // @[Decoder.scala 42:18 450:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_s = 1'h0; // @[Decoder.scala 42:18 451:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_feq_d = 1'h0; // @[Decoder.scala 42:18 452:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_flt_d = 1'h0; // @[Decoder.scala 42:18 453:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fle_d = 1'h0; // @[Decoder.scala 42:18 454:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fclass_d = 1'h0; // @[Decoder.scala 42:18 455:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_w_d = 1'h0; // @[Decoder.scala 42:18 456:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_wu_d = 1'h0; // @[Decoder.scala 42:18 457:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_w = 1'h0; // @[Decoder.scala 42:18 458:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_wu = 1'h0; // @[Decoder.scala 42:18 459:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_l_d = 1'h0; // @[Decoder.scala 42:18 460:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_lu_d = 1'h0; // @[Decoder.scala 42:18 461:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_x_d = 1'h0; // @[Decoder.scala 42:18 462:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_l = 1'h0; // @[Decoder.scala 42:18 463:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_lu = 1'h0; // @[Decoder.scala 42:18 464:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_d_x = 1'h0; // @[Decoder.scala 42:18 465:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rw = 1'h0; // @[Decoder.scala 42:18 466:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rs = 1'h0; // @[Decoder.scala 42:18 467:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rc = 1'h0; // @[Decoder.scala 42:18 468:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rwi = 1'h0; // @[Decoder.scala 42:18 469:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rsi = 1'h0; // @[Decoder.scala 42:18 470:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rci = 1'h0; // @[Decoder.scala 42:18 471:28]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_is_rvc = 1'h1; // @[Decoder.scala 42:18 46:21]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_pc = if4_instr_fifo_io_enq_0_bits_dec16_io_pc[38:0]; // @[Decoder.scala 42:18 45:17]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_imm = if4_instr_fifo_io_enq_0_bits_dec16__info_param_imm_T_249
     | _GEN_208; // @[Mux.scala 27:73]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rs1 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs1_T_240 | _GEN_205; // @[Mux.scala 27:73]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rs2 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_223 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rs2_T_188; // @[Mux.scala 27:73]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rd0 =
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_233 |
    if4_instr_fifo_io_enq_0_bits_dec16__info_param_raw_rd0_T_198; // @[Mux.scala 27:73]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_lui = 32'h37 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T; // @[Decoder.scala 692:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_auipc = 32'h17 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T; // @[Decoder.scala 693:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addi = 32'h13 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 694:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addiw = 32'h1b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 695:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slti = 32'h2013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 696:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sltiu = 32'h3013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 697:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_xori = 32'h4013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 698:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_ori = 32'h6013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 699:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_andi = 32'h7013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 700:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slli = 32'h1013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T; // @[Decoder.scala 701:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slliw = 32'h101b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 702:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srli = 32'h5013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T; // @[Decoder.scala 703:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srliw = 32'h501b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 704:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srai = 32'h40005013 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slli_T; // @[Decoder.scala 705:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sraiw = 32'h4000501b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 706:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_add = 32'h33 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 707:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addw = 32'h3b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 708:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sub = 32'h40000033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 709:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_subw = 32'h4000003b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 710:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sll = 32'h1033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 711:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sllw = 32'h103b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 712:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slt = 32'h2033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 713:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sltu = 32'h3033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 714:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_xor = 32'h4033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 715:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srl = 32'h5033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 716:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srlw = 32'h503b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 717:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sra = 32'h40005033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 718:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sraw = 32'h4000503b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 719:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_or = 32'h6033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 720:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_and = 32'h7033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 721:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_wfi = 32'h10500073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 722:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_jal = 32'h6f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T; // @[Decoder.scala 724:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_jalr = 32'h67 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 725:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_beq = 32'h63 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 726:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bne = 32'h1063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 727:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_blt = 32'h4063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 728:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bge = 32'h5063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 729:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bltu = 32'h6063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 730:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bgeu = 32'h7063 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 731:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lb = 32'h3 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 733:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lh = 32'h1003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 734:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lw = 32'h2003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 735:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_ld = 32'h3003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 736:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lbu = 32'h4003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 737:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lhu = 32'h5003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 738:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lwu = 32'h6003 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 739:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sb = 32'h23 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 740:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sh = 32'h1023 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 741:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sw = 32'h2023 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 742:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sd = 32'h3023 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 743:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fence = 32'hf ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 744:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fence_i = 32'h100f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_bru_isa_jalr_T; // @[Decoder.scala 745:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sfence_vma = 32'h12000073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 746:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lr_w = 32'h1000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_d_T; // @[Decoder.scala 812:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sc_w = 32'h1800202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 813:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoswap_w = 32'h800202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 814:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoadd_w = 32'h202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 815:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoxor_w = 32'h2000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 816:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoand_w = 32'h6000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 817:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoor_w = 32'h4000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 818:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomin_w = 32'h8000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 819:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomax_w = 32'ha000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 820:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amominu_w = 32'hc000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 821:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomaxu_w = 32'he000202f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 822:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lr_d = 32'h1000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_lr_d_T; // @[Decoder.scala 823:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sc_d = 32'h1800302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 824:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoswap_d = 32'h800302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 825:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoadd_d = 32'h302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 826:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoxor_d = 32'h2000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 827:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoand_d = 32'h6000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 828:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoor_d = 32'h4000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 829:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomin_d = 32'h8000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 830:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomax_d = 32'ha000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 831:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amominu_d = 32'hc000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 832:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomaxu_d = 32'he000302f ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_lsu_isa_sc_d_T; // @[Decoder.scala 833:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_flw = 1'h0; // @[Decoder.scala 498:20 901:24]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fsw = 1'h0; // @[Decoder.scala 498:20 902:24]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fld = 1'h0; // @[Decoder.scala 498:20 903:24]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fsd = 1'h0; // @[Decoder.scala 498:20 904:24]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rw = if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_1
     & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 748:87]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rs = if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rs_T_1
     & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 749:87]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rc = if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rc_T_1
     & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 750:87]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rwi =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rwi_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 751:87]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rsi =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rsi_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 752:87]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rci =
    if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rci_T_1 & if4_instr_fifo_io_enq_0_bits_dec32__info_csr_isa_rw_T_9; // @[Decoder.scala 753:87]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mul = 32'h2000033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 772:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulh = 32'h2001033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 773:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulhsu = 32'h2002033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 774:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulhu = 32'h2003033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 775:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_div = 32'h2004033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 776:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divu = 32'h2005033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 777:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_rem = 32'h2006033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 778:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remu = 32'h2007033 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 779:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulw = 32'h200003b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 780:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divw = 32'h200403b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 781:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divuw = 32'h200503b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 782:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remw = 32'h200603b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 783:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remuw = 32'h200703b ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_slliw_T; // @[Decoder.scala 784:37]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_ecall = 32'h73 == if4_instr_fifo_io_enq_0_bits_dec32_io_x
    ; // @[Decoder.scala 786:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_ebreak = 32'h100073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 787:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_mret = 32'h30200073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 788:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_uret = 32'h200073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 789:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_sret = 32'h10200073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 790:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_dret = 32'h7b200073 ==
    if4_instr_fifo_io_enq_0_bits_dec32_io_x; // @[Decoder.scala 791:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hfence_vvma = 32'h22000073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 795:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hfence_gvma = 32'h62000073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 796:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_b = 32'h60004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 798:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_bu = 32'h60104073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 799:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_h = 32'h64004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 800:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_hu = 32'h64104073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 801:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlvx_hu = 32'h64304073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 802:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_w = 32'h68004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 803:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlvx_wu = 32'h68304073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 804:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_b = 32'h62004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 805:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_h = 32'h66004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 806:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_w = 32'h6a004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 807:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_wu = 32'h68104073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 808:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_d = 32'h6c004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hlv_d_T; // @[Decoder.scala 809:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_d = 32'h6e004073 ==
    if4_instr_fifo_io_enq_0_bits_dec32__info_privil_isa_hsv_d_T; // @[Decoder.scala 810:40]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_is_access_fault = 1'h0; // @[Decoder.scala 498:20 909:41]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_is_paging_fault = 1'h0; // @[Decoder.scala 498:20 910:41]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmadd_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmsub_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmsub_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmadd_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fadd_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsub_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmul_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fdiv_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsqrt_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnj_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjn_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjx_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmin_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmax_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_w_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_wu_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_x_w = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_feq_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_flt_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fle_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fclass_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_w = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_wu = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_w_x = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_l_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_lu_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_l = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_lu = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmadd_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmsub_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmsub_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmadd_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fadd_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsub_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmul_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fdiv_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsqrt_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnj_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjn_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjx_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmin_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmax_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_s = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_feq_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_flt_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fle_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fclass_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_w_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_wu_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_w = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_wu = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_l_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_lu_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_x_d = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_l = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_lu = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_d_x = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rw = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rs = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rc = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rwi = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rsi = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rci = 1'h0; // @[Decoder.scala 905:{39,39}]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_is_rvc = 1'h0; // @[Decoder.scala 498:20 502:23]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_pc = if4_instr_fifo_io_enq_0_bits_dec32_io_pc[38:0]; // @[Decoder.scala 498:20 501:19]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_imm = if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_21
     ? if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_34 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_imm_T_184; // @[Mux.scala 101:16]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rs1 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs1_T_9; // @[Mux.scala 101:16]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rs2 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_lui_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rs2_T_85; // @[Mux.scala 101:16]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rd0 =
    if4_instr_fifo_io_enq_0_bits_dec32__info_alu_isa_wfi_T_1 ? 5'h0 :
    if4_instr_fifo_io_enq_0_bits_dec32__info_param_raw_rd0_T_24; // @[Mux.scala 101:16]
  assign if4_io_if4_req_0_ready = if4__io_if4_req_0_ready_T & if4_instr_fifo_io_enq_0_ready; // @[IF4.scala 254:76]
  assign if4_io_btbResp_0_ready = if4_btbRedirect_mdl_io_enq_0_ready; // @[RePort.scala 190:9]
  assign if4_io_bimResp_0_ready = if4_bimRedirect_mdl_io_enq_0_ready; // @[RePort.scala 190:9]
  assign if4_io_tageResp_0_ready = if4_tageRedirect_mdl_io_enq_0_ready; // @[RePort.scala 190:9]
  assign if4_io_if4_resp_0_valid = if4_instr_fifo_io_deq_0_valid; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_lui = if4_instr_fifo_io_deq_0_bits_alu_isa_lui; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_auipc = if4_instr_fifo_io_deq_0_bits_alu_isa_auipc; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_addi = if4_instr_fifo_io_deq_0_bits_alu_isa_addi; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_addiw = if4_instr_fifo_io_deq_0_bits_alu_isa_addiw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_slti = if4_instr_fifo_io_deq_0_bits_alu_isa_slti; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_sltiu = if4_instr_fifo_io_deq_0_bits_alu_isa_sltiu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_xori = if4_instr_fifo_io_deq_0_bits_alu_isa_xori; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_ori = if4_instr_fifo_io_deq_0_bits_alu_isa_ori; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_andi = if4_instr_fifo_io_deq_0_bits_alu_isa_andi; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_slli = if4_instr_fifo_io_deq_0_bits_alu_isa_slli; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_slliw = if4_instr_fifo_io_deq_0_bits_alu_isa_slliw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_srli = if4_instr_fifo_io_deq_0_bits_alu_isa_srli; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_srliw = if4_instr_fifo_io_deq_0_bits_alu_isa_srliw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_srai = if4_instr_fifo_io_deq_0_bits_alu_isa_srai; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_sraiw = if4_instr_fifo_io_deq_0_bits_alu_isa_sraiw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_add = if4_instr_fifo_io_deq_0_bits_alu_isa_add; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_addw = if4_instr_fifo_io_deq_0_bits_alu_isa_addw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_sub = if4_instr_fifo_io_deq_0_bits_alu_isa_sub; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_subw = if4_instr_fifo_io_deq_0_bits_alu_isa_subw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_sll = if4_instr_fifo_io_deq_0_bits_alu_isa_sll; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_sllw = if4_instr_fifo_io_deq_0_bits_alu_isa_sllw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_slt = if4_instr_fifo_io_deq_0_bits_alu_isa_slt; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_sltu = if4_instr_fifo_io_deq_0_bits_alu_isa_sltu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_xor = if4_instr_fifo_io_deq_0_bits_alu_isa_xor; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_srl = if4_instr_fifo_io_deq_0_bits_alu_isa_srl; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_srlw = if4_instr_fifo_io_deq_0_bits_alu_isa_srlw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_sra = if4_instr_fifo_io_deq_0_bits_alu_isa_sra; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_sraw = if4_instr_fifo_io_deq_0_bits_alu_isa_sraw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_or = if4_instr_fifo_io_deq_0_bits_alu_isa_or; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_and = if4_instr_fifo_io_deq_0_bits_alu_isa_and; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_alu_isa_wfi = if4_instr_fifo_io_deq_0_bits_alu_isa_wfi; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_bru_isa_jal = if4_instr_fifo_io_deq_0_bits_bru_isa_jal; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_bru_isa_jalr = if4_instr_fifo_io_deq_0_bits_bru_isa_jalr; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_bru_isa_beq = if4_instr_fifo_io_deq_0_bits_bru_isa_beq; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_bru_isa_bne = if4_instr_fifo_io_deq_0_bits_bru_isa_bne; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_bru_isa_blt = if4_instr_fifo_io_deq_0_bits_bru_isa_blt; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_bru_isa_bge = if4_instr_fifo_io_deq_0_bits_bru_isa_bge; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_bru_isa_bltu = if4_instr_fifo_io_deq_0_bits_bru_isa_bltu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_bru_isa_bgeu = if4_instr_fifo_io_deq_0_bits_bru_isa_bgeu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_lb = if4_instr_fifo_io_deq_0_bits_lsu_isa_lb; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_lh = if4_instr_fifo_io_deq_0_bits_lsu_isa_lh; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_lw = if4_instr_fifo_io_deq_0_bits_lsu_isa_lw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_ld = if4_instr_fifo_io_deq_0_bits_lsu_isa_ld; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_lbu = if4_instr_fifo_io_deq_0_bits_lsu_isa_lbu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_lhu = if4_instr_fifo_io_deq_0_bits_lsu_isa_lhu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_lwu = if4_instr_fifo_io_deq_0_bits_lsu_isa_lwu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_sb = if4_instr_fifo_io_deq_0_bits_lsu_isa_sb; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_sh = if4_instr_fifo_io_deq_0_bits_lsu_isa_sh; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_sw = if4_instr_fifo_io_deq_0_bits_lsu_isa_sw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_sd = if4_instr_fifo_io_deq_0_bits_lsu_isa_sd; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_fence = if4_instr_fifo_io_deq_0_bits_lsu_isa_fence; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_fence_i = if4_instr_fifo_io_deq_0_bits_lsu_isa_fence_i; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_sfence_vma = if4_instr_fifo_io_deq_0_bits_lsu_isa_sfence_vma; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_lr_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_lr_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_sc_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_sc_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoswap_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoswap_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoadd_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoadd_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoxor_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoxor_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoand_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoand_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoor_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoor_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amomin_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amomin_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amomax_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amomax_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amominu_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amominu_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amomaxu_w = if4_instr_fifo_io_deq_0_bits_lsu_isa_amomaxu_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_lr_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_lr_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_sc_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_sc_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoswap_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoswap_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoadd_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoadd_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoxor_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoxor_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoand_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoand_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amoor_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amoor_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amomin_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amomin_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amomax_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amomax_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amominu_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amominu_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_amomaxu_d = if4_instr_fifo_io_deq_0_bits_lsu_isa_amomaxu_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_flw = if4_instr_fifo_io_deq_0_bits_lsu_isa_flw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_fsw = if4_instr_fifo_io_deq_0_bits_lsu_isa_fsw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_fld = if4_instr_fifo_io_deq_0_bits_lsu_isa_fld; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_lsu_isa_fsd = if4_instr_fifo_io_deq_0_bits_lsu_isa_fsd; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_csr_isa_rw = if4_instr_fifo_io_deq_0_bits_csr_isa_rw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_csr_isa_rs = if4_instr_fifo_io_deq_0_bits_csr_isa_rs; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_csr_isa_rc = if4_instr_fifo_io_deq_0_bits_csr_isa_rc; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_csr_isa_rwi = if4_instr_fifo_io_deq_0_bits_csr_isa_rwi; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_csr_isa_rsi = if4_instr_fifo_io_deq_0_bits_csr_isa_rsi; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_csr_isa_rci = if4_instr_fifo_io_deq_0_bits_csr_isa_rci; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_mul = if4_instr_fifo_io_deq_0_bits_mul_isa_mul; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_mulh = if4_instr_fifo_io_deq_0_bits_mul_isa_mulh; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_mulhsu = if4_instr_fifo_io_deq_0_bits_mul_isa_mulhsu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_mulhu = if4_instr_fifo_io_deq_0_bits_mul_isa_mulhu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_div = if4_instr_fifo_io_deq_0_bits_mul_isa_div; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_divu = if4_instr_fifo_io_deq_0_bits_mul_isa_divu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_rem = if4_instr_fifo_io_deq_0_bits_mul_isa_rem; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_remu = if4_instr_fifo_io_deq_0_bits_mul_isa_remu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_mulw = if4_instr_fifo_io_deq_0_bits_mul_isa_mulw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_divw = if4_instr_fifo_io_deq_0_bits_mul_isa_divw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_divuw = if4_instr_fifo_io_deq_0_bits_mul_isa_divuw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_remw = if4_instr_fifo_io_deq_0_bits_mul_isa_remw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_mul_isa_remuw = if4_instr_fifo_io_deq_0_bits_mul_isa_remuw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_ecall = if4_instr_fifo_io_deq_0_bits_privil_isa_ecall; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_ebreak = if4_instr_fifo_io_deq_0_bits_privil_isa_ebreak; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_mret = if4_instr_fifo_io_deq_0_bits_privil_isa_mret; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_uret = if4_instr_fifo_io_deq_0_bits_privil_isa_uret; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_sret = if4_instr_fifo_io_deq_0_bits_privil_isa_sret; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_dret = if4_instr_fifo_io_deq_0_bits_privil_isa_dret; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hfence_vvma = if4_instr_fifo_io_deq_0_bits_privil_isa_hfence_vvma; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hfence_gvma = if4_instr_fifo_io_deq_0_bits_privil_isa_hfence_gvma; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlv_b = if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_b; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlv_bu = if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_bu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlv_h = if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_h; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlv_hu = if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_hu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlvx_hu = if4_instr_fifo_io_deq_0_bits_privil_isa_hlvx_hu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlv_w = if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlvx_wu = if4_instr_fifo_io_deq_0_bits_privil_isa_hlvx_wu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hsv_b = if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_b; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hsv_h = if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_h; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hsv_w = if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlv_wu = if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_wu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hlv_d = if4_instr_fifo_io_deq_0_bits_privil_isa_hlv_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_hsv_d = if4_instr_fifo_io_deq_0_bits_privil_isa_hsv_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_is_access_fault = if4_instr_fifo_io_deq_0_bits_privil_isa_is_access_fault; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_privil_isa_is_paging_fault = if4_instr_fifo_io_deq_0_bits_privil_isa_is_paging_fault; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmadd_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmadd_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmsub_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmsub_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fnmsub_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmsub_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fnmadd_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmadd_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fadd_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fadd_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsub_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsub_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmul_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmul_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fdiv_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fdiv_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsqrt_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsqrt_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsgnj_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnj_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsgnjn_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjn_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsgnjx_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjx_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmin_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmin_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmax_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmax_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_w_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_w_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_wu_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_wu_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmv_x_w = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_x_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_feq_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_feq_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_flt_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_flt_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fle_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fle_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fclass_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fclass_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_w = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_wu = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_wu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmv_w_x = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_w_x; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_l_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_l_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_lu_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_lu_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_l = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_l; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_lu = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_lu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmadd_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmadd_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmsub_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmsub_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fnmsub_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmsub_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fnmadd_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fnmadd_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fadd_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fadd_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsub_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsub_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmul_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmul_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fdiv_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fdiv_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsqrt_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsqrt_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsgnj_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnj_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsgnjn_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjn_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fsgnjx_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fsgnjx_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmin_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmin_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmax_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmax_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_s_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_s = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_s; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_feq_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_feq_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_flt_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_flt_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fle_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fle_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fclass_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fclass_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_w_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_w_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_wu_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_wu_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_w = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_w; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_wu = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_wu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_l_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_l_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_lu_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_lu_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmv_x_d = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_x_d; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_l = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_l; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_lu = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcvt_d_lu; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fmv_d_x = if4_instr_fifo_io_deq_0_bits_fpu_isa_fmv_d_x; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcsr_rw = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rw; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcsr_rs = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rs; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcsr_rc = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rc; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcsr_rwi = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rwi; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcsr_rsi = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rsi; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_fpu_isa_fcsr_rci = if4_instr_fifo_io_deq_0_bits_fpu_isa_fcsr_rci; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_param_is_rvc = if4_instr_fifo_io_deq_0_bits_param_is_rvc; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_param_pc = if4_instr_fifo_io_deq_0_bits_param_pc; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_param_imm = if4_instr_fifo_io_deq_0_bits_param_imm; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_param_raw_rs1 = if4_instr_fifo_io_deq_0_bits_param_raw_rs1; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_param_raw_rs2 = if4_instr_fifo_io_deq_0_bits_param_raw_rs2; // @[IF4.scala 237:15]
  assign if4_io_if4_resp_0_bits_param_raw_rd0 = if4_instr_fifo_io_deq_0_bits_param_raw_rd0; // @[IF4.scala 237:15]
  assign if4_io_if4Redirect_valid = if4__ras_io_deq_ready_T & if4__isDisAgreeWithIF1_0_T_4; // @[IF4.scala 171:44]
  assign if4_io_if4Redirect_bits_target = if4__io_if4Redirect_bits_target_T_4[38:0]; // @[IF4.scala 179:30]
  assign if4_io_bftq_valid = if4_bftq_io_deq_0_valid; // @[IF4.scala 238:11]
  assign if4_io_bftq_bits_pc = if4_bftq_io_deq_0_bits_pc; // @[IF4.scala 238:11]
  assign if4_io_bftq_bits_bimResp_bim_p = if4_bftq_io_deq_0_bits_bimResp_bim_p; // @[IF4.scala 238:11]
  assign if4_io_bftq_bits_bimResp_bim_h = if4_bftq_io_deq_0_bits_bimResp_bim_h; // @[IF4.scala 238:11]
  assign if4_io_bftq_bits_isPredictTaken = if4_bftq_io_deq_0_bits_isPredictTaken; // @[IF4.scala 238:11]
  assign if4_io_jftq_valid = if4_jftq_io_deq_0_valid; // @[IF4.scala 239:11]
  assign if4_io_jftq_bits_pc = if4_jftq_io_deq_0_bits_pc; // @[IF4.scala 239:11]
  assign if4_io_jftq_bits_btbResp_target = if4_jftq_io_deq_0_bits_btbResp_target; // @[IF4.scala 239:11]
  assign if4_io_jftq_bits_rasResp_target = if4_jftq_io_deq_0_bits_rasResp_target; // @[IF4.scala 239:11]
  assign if4_io_jftq_bits_isRas = if4_jftq_io_deq_0_bits_isRas; // @[IF4.scala 239:11]
  assign if4_ras_clock = if4_clock;
  assign if4_ras_reset = if4_reset;
  assign if4_ras_io_enq_valid = if4_preDecodeAgn_0_is_call & if4__ras_io_deq_ready_T; // @[IF4.scala 135:16]
  assign if4_ras_io_enq_bits_target = if4_preDecodeAgn_0_is_call ? if4__ras_io_enq_bits_target_T_2 : 39'h0; // @[Mux.scala 101:16]
  assign if4_ras_io_deq_ready = if4_preDecodeAgn_0_is_return & if4__ras_io_deq_ready_T; // @[IF4.scala 132:65]
  assign if4_ras_io_flush = if4_io_flush; // @[IF4.scala 212:16]
  assign if4_instr_fifo_clock = if4_clock;
  assign if4_instr_fifo_reset = if4_reset;
  assign if4_instr_fifo_io_enq_0_valid = if4_io_if4_req_0_ready & if4_io_if4_req_0_valid; // @[Decoupled.scala 52:35]
  assign if4_instr_fifo_io_deq_0_ready = if4_io_if4_resp_0_ready; // @[IF4.scala 237:15]
  assign if4_instr_fifo_io_flush = if4_io_flush; // @[IF4.scala 264:23]
  assign if4_bftq_clock = if4_clock;
  assign if4_bftq_reset = if4_reset;
  assign if4_bftq_io_enq_0_valid = if4_bRePort_io_deq_0_valid; // @[IF4.scala 241:15]
  assign if4_bftq_io_enq_0_bits_pc = if4_bRePort_io_deq_0_bits_pc; // @[IF4.scala 241:15]
  assign if4_bftq_io_enq_0_bits_bimResp_bim_p = if4_bRePort_io_deq_0_bits_bimResp_bim_p; // @[IF4.scala 241:15]
  assign if4_bftq_io_enq_0_bits_bimResp_bim_h = if4_bRePort_io_deq_0_bits_bimResp_bim_h; // @[IF4.scala 241:15]
  assign if4_bftq_io_enq_0_bits_isPredictTaken = if4_bRePort_io_deq_0_bits_isPredictTaken; // @[IF4.scala 241:15]
  assign if4_bftq_io_deq_0_ready = if4_io_bftq_ready; // @[IF4.scala 238:11]
  assign if4_bftq_io_flush = if4_io_flush; // @[IF4.scala 265:17]
  assign if4_jftq_clock = if4_clock;
  assign if4_jftq_reset = if4_reset;
  assign if4_jftq_io_enq_0_valid = if4_jRePort_io_deq_0_valid; // @[IF4.scala 242:15]
  assign if4_jftq_io_enq_0_bits_pc = if4_jRePort_io_deq_0_bits_pc; // @[IF4.scala 242:15]
  assign if4_jftq_io_enq_0_bits_btbResp_target = if4_jRePort_io_deq_0_bits_btbResp_target; // @[IF4.scala 242:15]
  assign if4_jftq_io_enq_0_bits_rasResp_target = if4_jRePort_io_deq_0_bits_rasResp_target; // @[IF4.scala 242:15]
  assign if4_jftq_io_enq_0_bits_isRas = if4_jRePort_io_deq_0_bits_isRas; // @[IF4.scala 242:15]
  assign if4_jftq_io_deq_0_ready = if4_io_jftq_ready; // @[IF4.scala 239:11]
  assign if4_jftq_io_flush = if4_io_flush; // @[IF4.scala 266:17]
  assign if4_bRePort_clock = if4_clock;
  assign if4_bRePort_reset = if4_reset;
  assign if4_bRePort_io_enq_0_valid = if4__ras_io_deq_ready_T & if4_preDecodeAgn_0_is_branch; // @[IF4.scala 247:51]
  assign if4_bRePort_io_enq_0_bits_pc = if4_io_if4_req_0_bits_pc; // @[IF4.scala 196:43]
  assign if4_bRePort_io_enq_0_bits_bimResp_bim_p = if4_bimRedirect_mdl_io_deq_0_bits_bim_p; // @[IF4.scala 198:43]
  assign if4_bRePort_io_enq_0_bits_bimResp_bim_h = if4_bimRedirect_mdl_io_deq_0_bits_bim_h; // @[IF4.scala 198:43]
  assign if4_bRePort_io_enq_0_bits_isPredictTaken = if4_bimRedirect_mdl_io_deq_0_bits_bim_p; // @[IF4.scala 200:43]
  assign if4_bRePort_io_deq_0_ready = if4_bftq_io_enq_0_ready; // @[IF4.scala 241:15]
  assign if4_jRePort_clock = if4_clock;
  assign if4_jRePort_reset = if4_reset;
  assign if4_jRePort_io_enq_0_valid = if4__ras_io_deq_ready_T & if4_preDecodeAgn_0_is_jalr; // @[IF4.scala 248:51]
  assign if4_jRePort_io_enq_0_bits_pc = if4_io_if4_req_0_bits_pc; // @[IF4.scala 202:36]
  assign if4_jRePort_io_enq_0_bits_btbResp_target = if4_btbRedirect_mdl_io_deq_0_bits_target; // @[IF4.scala 203:36]
  assign if4_jRePort_io_enq_0_bits_rasResp_target = if4_ras_io_deq_bits_target; // @[IF4.scala 204:36]
  assign if4_jRePort_io_enq_0_bits_isRas = if4_preDecodeAgn_0_is_return & if4_ras_io_deq_valid; // @[IF4.scala 205:52]
  assign if4_jRePort_io_deq_0_ready = if4_jftq_io_enq_0_ready; // @[IF4.scala 242:15]
  assign if4_bimRedirect_mdl_io_enq_0_valid = if4_io_bimResp_0_valid; // @[RePort.scala 190:9]
  assign if4_bimRedirect_mdl_io_enq_0_bits_bim_p = if4_io_bimResp_0_bits_bim_p; // @[RePort.scala 190:9]
  assign if4_bimRedirect_mdl_io_enq_0_bits_bim_h = if4_io_bimResp_0_bits_bim_h; // @[RePort.scala 190:9]
  assign if4_bimRedirect_mdl_io_deq_0_ready = if4_preDecodeAgn_0_is_branch & if4__ras_io_deq_ready_T; // @[IF4.scala 221:43]
  assign if4_bimRedirect_mdl_io_mapper_0 = if4_io_if4_req_0_bits_isRVC ? if4__preDecodeAgn_info16_is_branch_T_1 :
    if4__preDecodeAgn_info32_is_branch_T_1; // @[IF4.scala 58:46]
  assign if4_btbRedirect_mdl_io_enq_0_valid = if4_io_btbResp_0_valid; // @[RePort.scala 190:9]
  assign if4_btbRedirect_mdl_io_enq_0_bits_target = if4_io_btbResp_0_bits_target; // @[RePort.scala 190:9]
  assign if4_btbRedirect_mdl_io_deq_0_ready = if4_preDecodeAgn_0_is_jalr & if4__ras_io_deq_ready_T; // @[IF4.scala 220:43]
  assign if4_btbRedirect_mdl_io_mapper_0 = if4_io_if4_req_0_bits_isRVC ? if4__preDecodeAgn_info16_is_jalr_T_4 :
    if4__preDecodeAgn_info32_is_jalr_T_1; // @[IF4.scala 58:46]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_x = if4_io_if4_req_0_bits_instr[15:0]; // @[IF4.scala 94:46]
  assign if4_instr_fifo_io_enq_0_bits_dec16_io_pc = {{25'd0}, if4_io_if4_req_0_bits_pc}; // @[Decoder.scala 483:17]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_x = if4_io_if4_req_0_bits_instr; // @[Decoder.scala 922:16]
  assign if4_instr_fifo_io_enq_0_bits_dec32_io_pc = {{25'd0}, if4_io_if4_req_0_bits_pc}; // @[Decoder.scala 923:17]
  assign rnm_stage_rnRspReport_io_enq_0_ready = rnm_stage_rnRspReport_io_deq_0_ready; // @[RePort.scala 80:69]
  assign rnm_stage_rnRspReport_io_deq_0_valid = rnm_stage_rnRspReport__T > 1'h0; // @[RePort.scala 79:81]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_lui = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_lui; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_auipc = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_auipc; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addi = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addi; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addiw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addiw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slti = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slti; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sltiu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sltiu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_xori = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_xori; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_ori = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_ori; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_andi = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_andi; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slli = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slli; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slliw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slliw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srli = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srli; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srliw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srliw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srai = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srai; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sraiw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sraiw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_add = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_add; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sub = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sub; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_subw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_subw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sll = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sll; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sllw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sllw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slt = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slt; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sltu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sltu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_xor = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_xor; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srl = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srl; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srlw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srlw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sra = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sra; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sraw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sraw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_or = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_or; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_and = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_and; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_wfi = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_wfi; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_jal = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_jal; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_jalr = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_jalr; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_beq = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_beq; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bne = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bne; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_blt = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_blt; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bge = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bge; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bltu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bltu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bgeu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bgeu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lb = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lb; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lh = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lh; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_ld = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_ld; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lbu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lbu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lhu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lhu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lwu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lwu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sb = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sb; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sh = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sh; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sd = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sd; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fence = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fence; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fence_i = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fence_i; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sfence_vma = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sfence_vma; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lr_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lr_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sc_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sc_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoswap_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoswap_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoadd_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoadd_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoxor_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoxor_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoand_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoand_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoor_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoor_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomin_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomin_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomax_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomax_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amominu_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amominu_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomaxu_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomaxu_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lr_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lr_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sc_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sc_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoswap_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoswap_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoadd_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoadd_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoxor_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoxor_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoand_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoand_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoor_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoor_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomin_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomin_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomax_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomax_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amominu_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amominu_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomaxu_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomaxu_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_flw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_flw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fsw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fsw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fld = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fld; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fsd = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fsd; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rs = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rs; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rc = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rc; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rwi = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rwi; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rsi = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rsi; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rci = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rci; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mul = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mul; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulh = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulh; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulhsu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulhsu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulhu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulhu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_div = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_div; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_rem = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_rem; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remu = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remu; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divuw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divuw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remuw = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remuw; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmadd_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmadd_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmsub_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmsub_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmsub_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmsub_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmadd_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmadd_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fadd_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fadd_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsub_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsub_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmul_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmul_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fdiv_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fdiv_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsqrt_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsqrt_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnj_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnj_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjn_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjn_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjx_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjx_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmin_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmin_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmax_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmax_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_w_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_w_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_wu_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_wu_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmv_x_w = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmv_x_w; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_feq_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_feq_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_flt_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_flt_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fle_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fle_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fclass_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fclass_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_l_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_l_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_lu_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_lu_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmadd_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmadd_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmsub_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmsub_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmsub_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmsub_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmadd_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmadd_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fadd_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fadd_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsub_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsub_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmul_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmul_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fdiv_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fdiv_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsqrt_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsqrt_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnj_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnj_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjn_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjn_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjx_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjx_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmin_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmin_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmax_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmax_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_s_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_s_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_d_s = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_d_s; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_feq_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_feq_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_flt_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_flt_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fle_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fle_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fclass_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fclass_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_w_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_w_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_wu_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_wu_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_l_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_l_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_lu_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_lu_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmv_x_d = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmv_x_d; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_param_is_rvc = rnm_stage_rnRspReport__T_6 &
    rnm_stage_rnRspReport_io_enq_0_bits_param_is_rvc; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_param_pc = rnm_stage_rnRspReport__T_6 ?
    rnm_stage_rnRspReport_io_enq_0_bits_param_pc : 39'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_param_imm = rnm_stage_rnRspReport__T_6 ?
    rnm_stage_rnRspReport_io_enq_0_bits_param_imm : 64'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_param_raw_rs1 = rnm_stage_rnRspReport__T_6 ?
    rnm_stage_rnRspReport_io_enq_0_bits_param_raw_rs1 : 5'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_phy_rs1 = rnm_stage_rnRspReport__T_6 ?
    rnm_stage_rnRspReport_io_enq_0_bits_phy_rs1 : 6'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_phy_rs2 = rnm_stage_rnRspReport__T_6 ?
    rnm_stage_rnRspReport_io_enq_0_bits_phy_rs2 : 6'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_phy_rs3 = rnm_stage_rnRspReport__T_6 ?
    rnm_stage_rnRspReport_io_enq_0_bits_phy_rs3 : 6'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspReport_io_deq_0_bits_phy_rd0 = rnm_stage_rnRspReport__T_6 ?
    rnm_stage_rnRspReport_io_enq_0_bits_phy_rd0 : 6'h0; // @[RePort.scala 37:21 75:24 76:22]
  assign rnm_stage_rnRspFifo_io_enq_0_ready = ~rnm_stage_rnRspFifo__GEN_1; // @[MultiPortFifo.scala 64:94]
  assign rnm_stage_rnRspFifo_io_deq_0_valid = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ? rnm_stage_rnRspFifo_buf_valid_1
     : rnm_stage_rnRspFifo_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_lui = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_lui : rnm_stage_rnRspFifo_buf_0_alu_isa_lui; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_auipc = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_auipc : rnm_stage_rnRspFifo_buf_0_alu_isa_auipc; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addi = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_addi : rnm_stage_rnRspFifo_buf_0_alu_isa_addi; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addiw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_addiw : rnm_stage_rnRspFifo_buf_0_alu_isa_addiw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slti = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_slti : rnm_stage_rnRspFifo_buf_0_alu_isa_slti; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sltiu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_sltiu : rnm_stage_rnRspFifo_buf_0_alu_isa_sltiu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_xori = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_xori : rnm_stage_rnRspFifo_buf_0_alu_isa_xori; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_ori = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_ori : rnm_stage_rnRspFifo_buf_0_alu_isa_ori; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_andi = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_andi : rnm_stage_rnRspFifo_buf_0_alu_isa_andi; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slli = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_slli : rnm_stage_rnRspFifo_buf_0_alu_isa_slli; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slliw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_slliw : rnm_stage_rnRspFifo_buf_0_alu_isa_slliw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srli = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_srli : rnm_stage_rnRspFifo_buf_0_alu_isa_srli; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srliw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_srliw : rnm_stage_rnRspFifo_buf_0_alu_isa_srliw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srai = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_srai : rnm_stage_rnRspFifo_buf_0_alu_isa_srai; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sraiw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_sraiw : rnm_stage_rnRspFifo_buf_0_alu_isa_sraiw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_add = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_add : rnm_stage_rnRspFifo_buf_0_alu_isa_add; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_addw : rnm_stage_rnRspFifo_buf_0_alu_isa_addw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sub = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_sub : rnm_stage_rnRspFifo_buf_0_alu_isa_sub; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_subw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_subw : rnm_stage_rnRspFifo_buf_0_alu_isa_subw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sll = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_sll : rnm_stage_rnRspFifo_buf_0_alu_isa_sll; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sllw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_sllw : rnm_stage_rnRspFifo_buf_0_alu_isa_sllw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slt = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_slt : rnm_stage_rnRspFifo_buf_0_alu_isa_slt; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sltu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_sltu : rnm_stage_rnRspFifo_buf_0_alu_isa_sltu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_xor = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_xor : rnm_stage_rnRspFifo_buf_0_alu_isa_xor; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srl = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_srl : rnm_stage_rnRspFifo_buf_0_alu_isa_srl; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srlw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_srlw : rnm_stage_rnRspFifo_buf_0_alu_isa_srlw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sra = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_sra : rnm_stage_rnRspFifo_buf_0_alu_isa_sra; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sraw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_sraw : rnm_stage_rnRspFifo_buf_0_alu_isa_sraw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_or = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_or : rnm_stage_rnRspFifo_buf_0_alu_isa_or; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_and = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_and : rnm_stage_rnRspFifo_buf_0_alu_isa_and; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_wfi = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_alu_isa_wfi : rnm_stage_rnRspFifo_buf_0_alu_isa_wfi; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_jal = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_bru_isa_jal : rnm_stage_rnRspFifo_buf_0_bru_isa_jal; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_jalr = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_bru_isa_jalr : rnm_stage_rnRspFifo_buf_0_bru_isa_jalr; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_beq = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_bru_isa_beq : rnm_stage_rnRspFifo_buf_0_bru_isa_beq; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bne = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_bru_isa_bne : rnm_stage_rnRspFifo_buf_0_bru_isa_bne; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_blt = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_bru_isa_blt : rnm_stage_rnRspFifo_buf_0_bru_isa_blt; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bge = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_bru_isa_bge : rnm_stage_rnRspFifo_buf_0_bru_isa_bge; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bltu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_bru_isa_bltu : rnm_stage_rnRspFifo_buf_0_bru_isa_bltu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bgeu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_bru_isa_bgeu : rnm_stage_rnRspFifo_buf_0_bru_isa_bgeu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lb = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_lb : rnm_stage_rnRspFifo_buf_0_lsu_isa_lb; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lh = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_lh : rnm_stage_rnRspFifo_buf_0_lsu_isa_lh; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_lw : rnm_stage_rnRspFifo_buf_0_lsu_isa_lw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_ld = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_ld : rnm_stage_rnRspFifo_buf_0_lsu_isa_ld; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lbu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_lbu : rnm_stage_rnRspFifo_buf_0_lsu_isa_lbu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lhu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_lhu : rnm_stage_rnRspFifo_buf_0_lsu_isa_lhu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lwu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_lwu : rnm_stage_rnRspFifo_buf_0_lsu_isa_lwu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sb = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_sb : rnm_stage_rnRspFifo_buf_0_lsu_isa_sb; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sh = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_sh : rnm_stage_rnRspFifo_buf_0_lsu_isa_sh; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_sw : rnm_stage_rnRspFifo_buf_0_lsu_isa_sw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sd = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_sd : rnm_stage_rnRspFifo_buf_0_lsu_isa_sd; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fence = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_fence : rnm_stage_rnRspFifo_buf_0_lsu_isa_fence; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fence_i = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_fence_i : rnm_stage_rnRspFifo_buf_0_lsu_isa_fence_i; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sfence_vma = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_sfence_vma : rnm_stage_rnRspFifo_buf_0_lsu_isa_sfence_vma; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lr_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sc_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoswap_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoadd_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoxor_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoand_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoor_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomin_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomax_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amominu_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomaxu_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_w : rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lr_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sc_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoswap_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoadd_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoxor_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoand_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoor_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomin_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomax_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amominu_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomaxu_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_d : rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_flw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_flw : rnm_stage_rnRspFifo_buf_0_lsu_isa_flw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fsw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_fsw : rnm_stage_rnRspFifo_buf_0_lsu_isa_fsw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fld = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_fld : rnm_stage_rnRspFifo_buf_0_lsu_isa_fld; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fsd = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_lsu_isa_fsd : rnm_stage_rnRspFifo_buf_0_lsu_isa_fsd; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_csr_isa_rw : rnm_stage_rnRspFifo_buf_0_csr_isa_rw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rs = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_csr_isa_rs : rnm_stage_rnRspFifo_buf_0_csr_isa_rs; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rc = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_csr_isa_rc : rnm_stage_rnRspFifo_buf_0_csr_isa_rc; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rwi = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_csr_isa_rwi : rnm_stage_rnRspFifo_buf_0_csr_isa_rwi; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rsi = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_csr_isa_rsi : rnm_stage_rnRspFifo_buf_0_csr_isa_rsi; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rci = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_csr_isa_rci : rnm_stage_rnRspFifo_buf_0_csr_isa_rci; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mul = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_mul : rnm_stage_rnRspFifo_buf_0_mul_isa_mul; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulh = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_mulh : rnm_stage_rnRspFifo_buf_0_mul_isa_mulh; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulhsu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_mulhsu : rnm_stage_rnRspFifo_buf_0_mul_isa_mulhsu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulhu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_mulhu : rnm_stage_rnRspFifo_buf_0_mul_isa_mulhu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_div = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_div : rnm_stage_rnRspFifo_buf_0_mul_isa_div; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_divu : rnm_stage_rnRspFifo_buf_0_mul_isa_divu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_rem = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_rem : rnm_stage_rnRspFifo_buf_0_mul_isa_rem; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remu = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_remu : rnm_stage_rnRspFifo_buf_0_mul_isa_remu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_mulw : rnm_stage_rnRspFifo_buf_0_mul_isa_mulw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_divw : rnm_stage_rnRspFifo_buf_0_mul_isa_divw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divuw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_divuw : rnm_stage_rnRspFifo_buf_0_mul_isa_divuw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_remw : rnm_stage_rnRspFifo_buf_0_mul_isa_remw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remuw = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_mul_isa_remuw : rnm_stage_rnRspFifo_buf_0_mul_isa_remuw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmadd_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmsub_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmsub_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmadd_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fadd_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsub_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmul_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fdiv_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsqrt_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnj_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjn_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjx_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmin_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmax_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_w_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_wu_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmv_x_w = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_w : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_w; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_feq_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_flt_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fle_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fclass_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_l_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_lu_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmadd_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmsub_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmsub_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmadd_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fadd_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsub_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmul_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fdiv_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsqrt_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnj_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjn_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjx_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmin_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmax_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_s_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_s_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_s_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_d_s = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_d_s : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_d_s; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_feq_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_flt_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fle_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fclass_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_w_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_wu_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_l_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_lu_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmv_x_d = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_d : rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_d; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_param_is_rvc = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_param_is_rvc : rnm_stage_rnRspFifo_buf_0_param_is_rvc; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_param_pc = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_param_pc : rnm_stage_rnRspFifo_buf_0_param_pc; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_param_imm = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_param_imm : rnm_stage_rnRspFifo_buf_0_param_imm; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_param_raw_rs1 = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_param_raw_rs1 : rnm_stage_rnRspFifo_buf_0_param_raw_rs1; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs1 = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_phy_rs1 : rnm_stage_rnRspFifo_buf_0_phy_rs1; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs2 = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_phy_rs2 : rnm_stage_rnRspFifo_buf_0_phy_rs2; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs3 = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_phy_rs3 : rnm_stage_rnRspFifo_buf_0_phy_rs3; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_rnRspFifo_io_deq_0_bits_phy_rd0 = rnm_stage_rnRspFifo__io_deq_0_valid_T_1 ?
    rnm_stage_rnRspFifo_buf_1_phy_rd0 : rnm_stage_rnRspFifo_buf_0_phy_rd0; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_ready = ~rnm_stage_reOrder_fifo_i__GEN_1; // @[MultiPortFifo.scala 64:94]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_valid = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_valid_1 : rnm_stage_reOrder_fifo_i_buf_valid_0; // @[MultiPortFifo.scala 65:{94,94}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_pc = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_pc : rnm_stage_reOrder_fifo_i_buf_0_pc; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_rd0_raw = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_rd0_raw : rnm_stage_reOrder_fifo_i_buf_0_rd0_raw; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_rd0_phy = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_rd0_phy : rnm_stage_reOrder_fifo_i_buf_0_rd0_phy; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_branch = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_branch : rnm_stage_reOrder_fifo_i_buf_0_is_branch; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_jalr = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_jalr : rnm_stage_reOrder_fifo_i_buf_0_is_jalr; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_lu = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_lu : rnm_stage_reOrder_fifo_i_buf_0_is_lu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_su = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_su : rnm_stage_reOrder_fifo_i_buf_0_is_su; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_amo = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_amo : rnm_stage_reOrder_fifo_i_buf_0_is_amo; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fence_i = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_fence_i : rnm_stage_reOrder_fifo_i_buf_0_is_fence_i; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_sfence_vma = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_sfence_vma : rnm_stage_reOrder_fifo_i_buf_0_is_sfence_vma; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_wfi = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_wfi : rnm_stage_reOrder_fifo_i_buf_0_is_wfi; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_csr = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_csr : rnm_stage_reOrder_fifo_i_buf_0_is_csr; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fpu = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_fpu : rnm_stage_reOrder_fifo_i_buf_0_is_fpu; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fcsr = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_fcsr : rnm_stage_reOrder_fifo_i_buf_0_is_fcsr; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_xcmm = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_xcmm : rnm_stage_reOrder_fifo_i_buf_0_is_xcmm; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fcmm = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_fcmm : rnm_stage_reOrder_fifo_i_buf_0_is_fcmm; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_ecall = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_privil_ecall : rnm_stage_reOrder_fifo_i_buf_0_privil_ecall; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_ebreak = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_privil_ebreak : rnm_stage_reOrder_fifo_i_buf_0_privil_ebreak; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_mret = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_privil_mret : rnm_stage_reOrder_fifo_i_buf_0_privil_mret; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_sret = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_privil_sret : rnm_stage_reOrder_fifo_i_buf_0_privil_sret; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_dret = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_privil_dret : rnm_stage_reOrder_fifo_i_buf_0_privil_dret; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_is_access_fault = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_privil_is_access_fault : rnm_stage_reOrder_fifo_i_buf_0_privil_is_access_fault; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_is_paging_fault = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_privil_is_paging_fault : rnm_stage_reOrder_fifo_i_buf_0_privil_is_paging_fault; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_illeage = rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1 ?
    rnm_stage_reOrder_fifo_i_buf_1_is_illeage : rnm_stage_reOrder_fifo_i_buf_0_is_illeage; // @[MultiPortFifo.scala 114:{14,14}]
  assign rnm_stage_io_rnReq_0_ready = rnm_stage__io_rnReq_0_ready_T_1 & rnm_stage_rnRspFifo_io_enq_0_ready; // @[Rename.scala 91:92]
  assign rnm_stage_io_rnRsp_0_valid = rnm_stage_rnRspFifo_io_deq_0_valid; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_lui = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_lui; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_auipc = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_auipc; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_addi = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addi; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_addiw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addiw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_slti = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slti; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_sltiu = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sltiu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_xori = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_xori; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_ori = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_ori; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_andi = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_andi; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_slli = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slli; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_slliw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slliw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_srli = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srli; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_srliw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srliw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_srai = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srai; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_sraiw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sraiw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_add = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_add; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_addw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_addw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_sub = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sub; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_subw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_subw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_sll = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sll; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_sllw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sllw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_slt = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_slt; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_sltu = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sltu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_xor = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_xor; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_srl = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srl; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_srlw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_srlw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_sra = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sra; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_sraw = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_sraw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_or = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_or; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_and = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_and; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_alu_isa_wfi = rnm_stage_rnRspFifo_io_deq_0_bits_alu_isa_wfi; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_bru_isa_jal = rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_jal; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_bru_isa_jalr = rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_jalr; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_bru_isa_beq = rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_beq; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_bru_isa_bne = rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bne; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_bru_isa_blt = rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_blt; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_bru_isa_bge = rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bge; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_bru_isa_bltu = rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bltu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_bru_isa_bgeu = rnm_stage_rnRspFifo_io_deq_0_bits_bru_isa_bgeu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_lb = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lb; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_lh = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lh; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_lw = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_ld = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_ld; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_lbu = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lbu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_lhu = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lhu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_lwu = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lwu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_sb = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sb; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_sh = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sh; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_sw = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_sd = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sd; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_fence = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fence; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_fence_i = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fence_i; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_sfence_vma = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sfence_vma; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_lr_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lr_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_sc_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sc_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoswap_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoswap_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoadd_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoadd_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoxor_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoxor_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoand_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoand_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoor_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoor_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amomin_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomin_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amomax_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomax_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amominu_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amominu_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amomaxu_w = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomaxu_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_lr_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_lr_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_sc_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_sc_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoswap_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoswap_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoadd_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoadd_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoxor_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoxor_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoand_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoand_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amoor_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amoor_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amomin_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomin_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amomax_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomax_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amominu_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amominu_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_amomaxu_d = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_amomaxu_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_flw = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_flw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_fsw = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fsw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_fld = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fld; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_lsu_isa_fsd = rnm_stage_rnRspFifo_io_deq_0_bits_lsu_isa_fsd; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_csr_isa_rw = rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_csr_isa_rs = rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rs; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_csr_isa_rc = rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rc; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_csr_isa_rwi = rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rwi; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_csr_isa_rsi = rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rsi; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_csr_isa_rci = rnm_stage_rnRspFifo_io_deq_0_bits_csr_isa_rci; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_mul = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mul; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_mulh = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulh; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_mulhsu = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulhsu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_mulhu = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulhu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_div = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_div; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_divu = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_rem = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_rem; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_remu = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remu; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_mulw = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_mulw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_divw = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_divuw = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_divuw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_remw = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_mul_isa_remuw = rnm_stage_rnRspFifo_io_deq_0_bits_mul_isa_remuw; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmadd_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmadd_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmsub_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmsub_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmsub_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmsub_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmadd_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmadd_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fadd_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fadd_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsub_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsub_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmul_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmul_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fdiv_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fdiv_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsqrt_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsqrt_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnj_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnj_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjn_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjn_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjx_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjx_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmin_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmin_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmax_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmax_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_w_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_w_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_wu_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_wu_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmv_x_w = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmv_x_w; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_feq_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_feq_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_flt_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_flt_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fle_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fle_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fclass_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fclass_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_l_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_l_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_lu_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_lu_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmadd_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmadd_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmsub_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmsub_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmsub_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmsub_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmadd_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fnmadd_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fadd_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fadd_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsub_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsub_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmul_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmul_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fdiv_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fdiv_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsqrt_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsqrt_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnj_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnj_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjn_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjn_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjx_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fsgnjx_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmin_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmin_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmax_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmax_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_s_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_s_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_d_s = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_d_s; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_feq_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_feq_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_flt_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_flt_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fle_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fle_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fclass_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fclass_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_w_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_w_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_wu_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_wu_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_l_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_l_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_lu_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fcvt_lu_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_fpu_isa_fmv_x_d = rnm_stage_rnRspFifo_io_deq_0_bits_fpu_isa_fmv_x_d; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_param_is_rvc = rnm_stage_rnRspFifo_io_deq_0_bits_param_is_rvc; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_param_pc = rnm_stage_rnRspFifo_io_deq_0_bits_param_pc; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_param_imm = rnm_stage_rnRspFifo_io_deq_0_bits_param_imm; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_param_raw_rs1 = rnm_stage_rnRspFifo_io_deq_0_bits_param_raw_rs1; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_phy_rs1 = rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs1; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_phy_rs2 = rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs2; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_phy_rs3 = rnm_stage_rnRspFifo_io_deq_0_bits_phy_rs3; // @[Rename.scala 45:20]
  assign rnm_stage_io_rnRsp_0_bits_phy_rd0 = rnm_stage_rnRspFifo_io_deq_0_bits_phy_rd0; // @[Rename.scala 45:20]
  assign rnm_stage_io_xLookup_0_req_rs1 = rnm_stage_io_rnReq_0_bits_param_raw_rs1; // @[Rename.scala 63:27]
  assign rnm_stage_io_xLookup_0_req_rs2 = rnm_stage_io_rnReq_0_bits_param_raw_rs2; // @[Rename.scala 64:27]
  assign rnm_stage_io_xRename_0_req_valid = rnm_stage__rnRspReport_io_enq_0_valid_T &
    rnm_stage__io_xRename_0_req_valid_T_42; // @[Rename.scala 60:52]
  assign rnm_stage_io_xRename_0_req_bits_rd0 = rnm_stage_io_rnReq_0_bits_param_raw_rd0; // @[Rename.scala 61:32]
  assign rnm_stage_io_fRename_0_req_valid = rnm_stage__rnRspReport_io_enq_0_valid_T &
    rnm_stage__io_xRename_0_req_valid_T_41; // @[Rename.scala 67:52]
  assign rnm_stage_io_rod_i_0_valid = rnm_stage_reOrder_fifo_i_io_deq_0_valid; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_pc = rnm_stage_reOrder_fifo_i_io_deq_0_bits_pc; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_rd0_raw = rnm_stage_reOrder_fifo_i_io_deq_0_bits_rd0_raw; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_rd0_phy = rnm_stage_reOrder_fifo_i_io_deq_0_bits_rd0_phy; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_branch = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_branch; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_jalr = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_jalr; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_lu = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_lu; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_su = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_su; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_amo = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_amo; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_fence_i = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fence_i; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_sfence_vma = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_sfence_vma; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_wfi = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_wfi; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_csr = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_csr; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_fpu = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fpu; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_fcsr = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fcsr; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_xcmm = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_xcmm; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_fcmm = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_fcmm; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_privil_ecall = rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_ecall; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_privil_ebreak = rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_ebreak; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_privil_mret = rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_mret; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_privil_sret = rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_sret; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_privil_dret = rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_dret; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_privil_is_access_fault =
    rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_is_access_fault; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_privil_is_paging_fault =
    rnm_stage_reOrder_fifo_i_io_deq_0_bits_privil_is_paging_fault; // @[Rename.scala 49:16]
  assign rnm_stage_io_rod_i_0_bits_is_illeage = rnm_stage_reOrder_fifo_i_io_deq_0_bits_is_illeage; // @[Rename.scala 49:16]
  assign rnm_stage_rnRspReport_clock = rnm_stage_clock;
  assign rnm_stage_rnRspReport_reset = rnm_stage_reset;
  assign rnm_stage_rnRspReport_io_enq_0_valid = rnm_stage__rnRspReport_io_enq_0_valid_T &
    rnm_stage__rnRspReport_io_enq_0_valid_T_23; // @[Rename.scala 57:53]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_lui = rnm_stage_io_rnReq_0_bits_alu_isa_lui; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_auipc = rnm_stage_io_rnReq_0_bits_alu_isa_auipc; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addi = rnm_stage_io_rnReq_0_bits_alu_isa_addi; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addiw = rnm_stage_io_rnReq_0_bits_alu_isa_addiw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slti = rnm_stage_io_rnReq_0_bits_alu_isa_slti; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sltiu = rnm_stage_io_rnReq_0_bits_alu_isa_sltiu; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_xori = rnm_stage_io_rnReq_0_bits_alu_isa_xori; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_ori = rnm_stage_io_rnReq_0_bits_alu_isa_ori; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_andi = rnm_stage_io_rnReq_0_bits_alu_isa_andi; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slli = rnm_stage_io_rnReq_0_bits_alu_isa_slli; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slliw = rnm_stage_io_rnReq_0_bits_alu_isa_slliw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srli = rnm_stage_io_rnReq_0_bits_alu_isa_srli; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srliw = rnm_stage_io_rnReq_0_bits_alu_isa_srliw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srai = rnm_stage_io_rnReq_0_bits_alu_isa_srai; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sraiw = rnm_stage_io_rnReq_0_bits_alu_isa_sraiw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_add = rnm_stage_io_rnReq_0_bits_alu_isa_add; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_addw = rnm_stage_io_rnReq_0_bits_alu_isa_addw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sub = rnm_stage_io_rnReq_0_bits_alu_isa_sub; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_subw = rnm_stage_io_rnReq_0_bits_alu_isa_subw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sll = rnm_stage_io_rnReq_0_bits_alu_isa_sll; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sllw = rnm_stage_io_rnReq_0_bits_alu_isa_sllw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_slt = rnm_stage_io_rnReq_0_bits_alu_isa_slt; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sltu = rnm_stage_io_rnReq_0_bits_alu_isa_sltu; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_xor = rnm_stage_io_rnReq_0_bits_alu_isa_xor; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srl = rnm_stage_io_rnReq_0_bits_alu_isa_srl; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_srlw = rnm_stage_io_rnReq_0_bits_alu_isa_srlw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sra = rnm_stage_io_rnReq_0_bits_alu_isa_sra; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_sraw = rnm_stage_io_rnReq_0_bits_alu_isa_sraw; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_or = rnm_stage_io_rnReq_0_bits_alu_isa_or; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_and = rnm_stage_io_rnReq_0_bits_alu_isa_and; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_alu_isa_wfi = rnm_stage_io_rnReq_0_bits_alu_isa_wfi; // @[Rename.scala 102:19 104:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_jal = rnm_stage_io_rnReq_0_bits_bru_isa_jal; // @[Rename.scala 102:19 105:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_jalr = rnm_stage_io_rnReq_0_bits_bru_isa_jalr; // @[Rename.scala 102:19 105:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_beq = rnm_stage_io_rnReq_0_bits_bru_isa_beq; // @[Rename.scala 102:19 105:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bne = rnm_stage_io_rnReq_0_bits_bru_isa_bne; // @[Rename.scala 102:19 105:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_blt = rnm_stage_io_rnReq_0_bits_bru_isa_blt; // @[Rename.scala 102:19 105:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bge = rnm_stage_io_rnReq_0_bits_bru_isa_bge; // @[Rename.scala 102:19 105:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bltu = rnm_stage_io_rnReq_0_bits_bru_isa_bltu; // @[Rename.scala 102:19 105:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_bru_isa_bgeu = rnm_stage_io_rnReq_0_bits_bru_isa_bgeu; // @[Rename.scala 102:19 105:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lb = rnm_stage_io_rnReq_0_bits_lsu_isa_lb; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lh = rnm_stage_io_rnReq_0_bits_lsu_isa_lh; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lw = rnm_stage_io_rnReq_0_bits_lsu_isa_lw; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_ld = rnm_stage_io_rnReq_0_bits_lsu_isa_ld; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lbu = rnm_stage_io_rnReq_0_bits_lsu_isa_lbu; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lhu = rnm_stage_io_rnReq_0_bits_lsu_isa_lhu; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lwu = rnm_stage_io_rnReq_0_bits_lsu_isa_lwu; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sb = rnm_stage_io_rnReq_0_bits_lsu_isa_sb; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sh = rnm_stage_io_rnReq_0_bits_lsu_isa_sh; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sw = rnm_stage_io_rnReq_0_bits_lsu_isa_sw; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sd = rnm_stage_io_rnReq_0_bits_lsu_isa_sd; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fence = rnm_stage_io_rnReq_0_bits_lsu_isa_fence; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fence_i = rnm_stage_io_rnReq_0_bits_lsu_isa_fence_i; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sfence_vma = rnm_stage_io_rnReq_0_bits_lsu_isa_sfence_vma; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lr_w = rnm_stage_io_rnReq_0_bits_lsu_isa_lr_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sc_w = rnm_stage_io_rnReq_0_bits_lsu_isa_sc_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoswap_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amoswap_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoadd_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amoadd_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoxor_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amoxor_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoand_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amoand_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoor_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amoor_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomin_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amomin_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomax_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amomax_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amominu_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amominu_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomaxu_w = rnm_stage_io_rnReq_0_bits_lsu_isa_amomaxu_w; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_lr_d = rnm_stage_io_rnReq_0_bits_lsu_isa_lr_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_sc_d = rnm_stage_io_rnReq_0_bits_lsu_isa_sc_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoswap_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amoswap_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoadd_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amoadd_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoxor_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amoxor_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoand_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amoand_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amoor_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amoor_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomin_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amomin_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomax_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amomax_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amominu_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amominu_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_amomaxu_d = rnm_stage_io_rnReq_0_bits_lsu_isa_amomaxu_d; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_flw = rnm_stage_io_rnReq_0_bits_lsu_isa_flw; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fsw = rnm_stage_io_rnReq_0_bits_lsu_isa_fsw; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fld = rnm_stage_io_rnReq_0_bits_lsu_isa_fld; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_lsu_isa_fsd = rnm_stage_io_rnReq_0_bits_lsu_isa_fsd; // @[Rename.scala 102:19 106:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rw = rnm_stage_io_rnReq_0_bits_csr_isa_rw; // @[Rename.scala 102:19 107:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rs = rnm_stage_io_rnReq_0_bits_csr_isa_rs; // @[Rename.scala 102:19 107:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rc = rnm_stage_io_rnReq_0_bits_csr_isa_rc; // @[Rename.scala 102:19 107:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rwi = rnm_stage_io_rnReq_0_bits_csr_isa_rwi; // @[Rename.scala 102:19 107:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rsi = rnm_stage_io_rnReq_0_bits_csr_isa_rsi; // @[Rename.scala 102:19 107:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_csr_isa_rci = rnm_stage_io_rnReq_0_bits_csr_isa_rci; // @[Rename.scala 102:19 107:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mul = rnm_stage_io_rnReq_0_bits_mul_isa_mul; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulh = rnm_stage_io_rnReq_0_bits_mul_isa_mulh; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulhsu = rnm_stage_io_rnReq_0_bits_mul_isa_mulhsu; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulhu = rnm_stage_io_rnReq_0_bits_mul_isa_mulhu; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_div = rnm_stage_io_rnReq_0_bits_mul_isa_div; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divu = rnm_stage_io_rnReq_0_bits_mul_isa_divu; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_rem = rnm_stage_io_rnReq_0_bits_mul_isa_rem; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remu = rnm_stage_io_rnReq_0_bits_mul_isa_remu; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_mulw = rnm_stage_io_rnReq_0_bits_mul_isa_mulw; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divw = rnm_stage_io_rnReq_0_bits_mul_isa_divw; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_divuw = rnm_stage_io_rnReq_0_bits_mul_isa_divuw; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remw = rnm_stage_io_rnReq_0_bits_mul_isa_remw; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_mul_isa_remuw = rnm_stage_io_rnReq_0_bits_mul_isa_remuw; // @[Rename.scala 102:19 108:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmadd_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmsub_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmsub_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmadd_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fadd_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsub_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmul_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fdiv_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsqrt_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnj_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjn_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjx_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmin_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmax_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_w_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_wu_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmv_x_w = rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_w; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_feq_s = rnm_stage_io_rnReq_0_bits_fpu_isa_feq_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_flt_s = rnm_stage_io_rnReq_0_bits_fpu_isa_flt_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fle_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fle_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fclass_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_l_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_lu_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmadd_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmsub_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmsub_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fnmadd_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fadd_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsub_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmul_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fdiv_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsqrt_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnj_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjn_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fsgnjx_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmin_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmax_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_s_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_d_s = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_s; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_feq_d = rnm_stage_io_rnReq_0_bits_fpu_isa_feq_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_flt_d = rnm_stage_io_rnReq_0_bits_fpu_isa_flt_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fle_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fle_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fclass_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_w_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_wu_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_l_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fcvt_lu_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_fpu_isa_fmv_x_d = rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_d; // @[Rename.scala 102:19 110:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_param_is_rvc = rnm_stage_io_rnReq_0_bits_param_is_rvc; // @[Rename.scala 102:19 111:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_param_pc = rnm_stage_io_rnReq_0_bits_param_pc; // @[Rename.scala 102:19 111:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_param_imm = rnm_stage_io_rnReq_0_bits_param_imm; // @[Rename.scala 102:19 111:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_param_raw_rs1 = rnm_stage_io_rnReq_0_bits_param_raw_rs1; // @[Rename.scala 102:19 111:20]
  assign rnm_stage_rnRspReport_io_enq_0_bits_phy_rs1 = rnm_stage__reg_phy_0_rs2_T_46 ? rnm_stage_io_fLookup_0_rsp_rs1 :
    rnm_stage_io_xLookup_0_rsp_rs1; // @[Rename.scala 75:26]
  assign rnm_stage_rnRspReport_io_enq_0_bits_phy_rs2 = rnm_stage__rnRspReport_io_enq_0_bits_T_62 ? rnm_stage__GEN_0 :
    rnm_stage__reg_phy_0_rs2_T_49; // @[Rename.scala 112:20 114:34]
  assign rnm_stage_rnRspReport_io_enq_0_bits_phy_rs3 = rnm_stage__rnRspReport_io_enq_0_bits_T_62 ? rnm_stage__GEN_1 :
    rnm_stage__reg_phy_0_rs3_T_47; // @[Rename.scala 112:20 114:34]
  assign rnm_stage_rnRspReport_io_enq_0_bits_phy_rd0 = rnm_stage__reg_phy_0_rd0_T_2 | rnm_stage__reg_phy_0_rd0_T_3; // @[Mux.scala 27:73]
  assign rnm_stage_rnRspReport_io_deq_0_ready = rnm_stage_rnRspFifo_io_enq_0_ready; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_clock = rnm_stage_clock;
  assign rnm_stage_rnRspFifo_reset = rnm_stage_reset;
  assign rnm_stage_rnRspFifo_io_enq_0_valid = rnm_stage_rnRspReport_io_deq_0_valid; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_lui = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_lui; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_auipc = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_auipc; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addi = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addi; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addiw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addiw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slti = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slti; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sltiu = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sltiu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_xori = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_xori; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_ori = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_ori; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_andi = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_andi; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slli = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slli; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slliw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slliw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srli = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srli; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srliw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srliw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srai = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srai; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sraiw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sraiw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_add = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_add; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_addw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sub = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sub; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_subw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_subw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sll = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sll; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sllw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sllw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slt = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_slt; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sltu = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sltu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_xor = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_xor; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srl = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srl; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srlw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_srlw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sra = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sra; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sraw = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_sraw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_or = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_or; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_and = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_and; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_wfi = rnm_stage_rnRspReport_io_deq_0_bits_alu_isa_wfi; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_jal = rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_jal; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_jalr = rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_jalr; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_beq = rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_beq; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bne = rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bne; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_blt = rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_blt; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bge = rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bge; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bltu = rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bltu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bgeu = rnm_stage_rnRspReport_io_deq_0_bits_bru_isa_bgeu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lb = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lb; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lh = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lh; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lw = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_ld = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_ld; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lbu = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lbu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lhu = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lhu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lwu = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lwu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sb = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sb; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sh = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sh; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sw = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sd = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sd; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fence = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fence; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fence_i = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fence_i; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sfence_vma = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sfence_vma; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lr_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lr_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sc_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sc_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoswap_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoswap_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoadd_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoadd_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoxor_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoxor_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoand_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoand_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoor_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoor_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomin_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomin_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomax_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomax_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amominu_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amominu_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomaxu_w = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomaxu_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lr_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_lr_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sc_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_sc_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoswap_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoswap_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoadd_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoadd_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoxor_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoxor_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoand_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoand_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoor_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amoor_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomin_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomin_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomax_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomax_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amominu_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amominu_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomaxu_d = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_amomaxu_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_flw = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_flw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fsw = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fsw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fld = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fld; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fsd = rnm_stage_rnRspReport_io_deq_0_bits_lsu_isa_fsd; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rw = rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rs = rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rs; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rc = rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rc; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rwi = rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rwi; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rsi = rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rsi; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rci = rnm_stage_rnRspReport_io_deq_0_bits_csr_isa_rci; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mul = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mul; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulh = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulh; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulhsu = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulhsu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulhu = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulhu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_div = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_div; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divu = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_rem = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_rem; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remu = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remu; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulw = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_mulw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divw = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divuw = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_divuw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remw = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remuw = rnm_stage_rnRspReport_io_deq_0_bits_mul_isa_remuw; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmadd_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmadd_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmsub_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmsub_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmsub_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmsub_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmadd_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmadd_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fadd_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fadd_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsub_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsub_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmul_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmul_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fdiv_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fdiv_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsqrt_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsqrt_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnj_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnj_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjn_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjn_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjx_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjx_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmin_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmin_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmax_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmax_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_w_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_w_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_wu_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_wu_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmv_x_w = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmv_x_w; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_feq_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_feq_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_flt_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_flt_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fle_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fle_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fclass_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fclass_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_l_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_l_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_lu_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_lu_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmadd_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmadd_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmsub_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmsub_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmsub_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmsub_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmadd_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fnmadd_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fadd_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fadd_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsub_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsub_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmul_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmul_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fdiv_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fdiv_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsqrt_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsqrt_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnj_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnj_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjn_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjn_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjx_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fsgnjx_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmin_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmin_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmax_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmax_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_s_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_s_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_d_s = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_d_s; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_feq_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_feq_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_flt_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_flt_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fle_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fle_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fclass_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fclass_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_w_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_w_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_wu_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_wu_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_l_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_l_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_lu_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fcvt_lu_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmv_x_d = rnm_stage_rnRspReport_io_deq_0_bits_fpu_isa_fmv_x_d; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_param_is_rvc = rnm_stage_rnRspReport_io_deq_0_bits_param_is_rvc; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_param_pc = rnm_stage_rnRspReport_io_deq_0_bits_param_pc; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_param_imm = rnm_stage_rnRspReport_io_deq_0_bits_param_imm; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_param_raw_rs1 = rnm_stage_rnRspReport_io_deq_0_bits_param_raw_rs1; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs1 = rnm_stage_rnRspReport_io_deq_0_bits_phy_rs1; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs2 = rnm_stage_rnRspReport_io_deq_0_bits_phy_rs2; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs3 = rnm_stage_rnRspReport_io_deq_0_bits_phy_rs3; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_enq_0_bits_phy_rd0 = rnm_stage_rnRspReport_io_deq_0_bits_phy_rd0; // @[Rename.scala 44:20]
  assign rnm_stage_rnRspFifo_io_deq_0_ready = rnm_stage_io_rnRsp_0_ready; // @[Rename.scala 45:20]
  assign rnm_stage_reOrder_fifo_i_clock = rnm_stage_clock;
  assign rnm_stage_reOrder_fifo_i_reset = rnm_stage_reset;
  assign rnm_stage_reOrder_fifo_i_io_enq_0_valid = rnm_stage_io_rnReq_0_ready & rnm_stage_io_rnReq_0_valid; // @[Decoupled.scala 52:35]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_pc = rnm_stage_io_rnReq_0_bits_param_pc; // @[Rename.scala 123:19 125:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_rd0_raw = rnm_stage_io_rnReq_0_bits_param_raw_rd0; // @[Rename.scala 123:19 126:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_rd0_phy = rnm_stage__reg_phy_0_rd0_T_2 | rnm_stage__reg_phy_0_rd0_T_3; // @[Mux.scala 27:73]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_branch = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_branch_T_3 |
    rnm_stage_io_rnReq_0_bits_bru_isa_bgeu; // @[riscv_isa.scala 93:48]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_jalr = rnm_stage_io_rnReq_0_bits_bru_isa_jalr; // @[Rename.scala 123:19 129:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_lu = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_7 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_lu_T_8; // @[riscv_isa.scala 143:65]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_su = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_su_T_3 |
    rnm_stage_io_rnReq_0_bits_lsu_isa_fsd; // @[riscv_isa.scala 144:40]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_amo = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_16 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_amo_T_17; // @[riscv_isa.scala 148:205]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fence_i = rnm_stage_io_rnReq_0_bits_lsu_isa_fence_i; // @[Rename.scala 123:19 134:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_sfence_vma = rnm_stage_io_rnReq_0_bits_lsu_isa_sfence_vma; // @[Rename.scala 123:19 135:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_wfi = rnm_stage_io_rnReq_0_bits_alu_isa_wfi; // @[Rename.scala 123:19 136:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_csr = rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_csr_T_3 |
    rnm_stage_io_rnReq_0_bits_csr_isa_rci; // @[riscv_isa.scala 179:41]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fpu = rnm_stage__rnRspReport_io_enq_0_bits_T_62 |
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_fpu_T_65; // @[Rename.scala 139:50]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fcsr = rnm_stage__rnRspReport_io_enq_0_bits_T_61 |
    rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rci; // @[riscv_isa.scala 525:61]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_xcmm = ~rnm_stage__io_xRename_0_req_valid_T_41; // @[riscv_isa.scala 800:16]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fcmm = rnm_stage__io_xRename_0_req_valid_T_1 |
    rnm_stage__io_xRename_0_req_valid_T_40; // @[riscv_isa.scala 794:20]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_ecall = rnm_stage_io_rnReq_0_bits_privil_isa_ecall; // @[Rename.scala 123:19 140:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_ebreak = rnm_stage_io_rnReq_0_bits_privil_isa_ebreak; // @[Rename.scala 123:19 140:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_mret = rnm_stage_io_rnReq_0_bits_privil_isa_mret; // @[Rename.scala 123:19 140:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_sret = rnm_stage_io_rnReq_0_bits_privil_isa_sret; // @[Rename.scala 123:19 140:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_dret = rnm_stage_io_rnReq_0_bits_privil_isa_dret; // @[Rename.scala 123:19 140:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_is_access_fault =
    rnm_stage_io_rnReq_0_bits_privil_isa_is_access_fault; // @[Rename.scala 123:19 140:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_is_paging_fault =
    rnm_stage_io_rnReq_0_bits_privil_isa_is_paging_fault; // @[Rename.scala 123:19 140:26]
  assign rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_illeage = ~
    rnm_stage__reOrder_fifo_i_io_enq_0_bits_res_is_illeage_T_185; // @[riscv_isa.scala 801:20]
  assign rnm_stage_reOrder_fifo_i_io_deq_0_ready = rnm_stage_io_rod_i_0_ready; // @[Rename.scala 49:16]
  assign iss_stage_aluIssFifo_0_ram_fun_add_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_add_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_add_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_fun_add[iss_stage_aluIssFifo_0_ram_fun_add_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_fun_add_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_fun_add;
  assign iss_stage_aluIssFifo_0_ram_fun_add_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_add_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_add_MPORT_en = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22
     : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_fun_slt_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_slt_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_slt_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_fun_slt[iss_stage_aluIssFifo_0_ram_fun_slt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_fun_slt;
  assign iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_en = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22
     : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_fun_xor_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_xor_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_xor_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_fun_xor[iss_stage_aluIssFifo_0_ram_fun_xor_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_fun_xor;
  assign iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_en = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22
     : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_fun_or_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_or_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_or_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_fun_or[iss_stage_aluIssFifo_0_ram_fun_or_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_fun_or_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_fun_or;
  assign iss_stage_aluIssFifo_0_ram_fun_or_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_or_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_or_MPORT_en = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22
     : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_fun_and_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_and_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_and_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_fun_and[iss_stage_aluIssFifo_0_ram_fun_and_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_fun_and_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_fun_and;
  assign iss_stage_aluIssFifo_0_ram_fun_and_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_and_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_and_MPORT_en = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22
     : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_fun_sll_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_sll_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_sll_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_fun_sll[iss_stage_aluIssFifo_0_ram_fun_sll_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_fun_sll;
  assign iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_en = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22
     : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_fun_srl_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_srl_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_srl_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_fun_srl[iss_stage_aluIssFifo_0_ram_fun_srl_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_fun_srl;
  assign iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_en = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22
     : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_fun_sra_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_sra_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_sra_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_fun_sra[iss_stage_aluIssFifo_0_ram_fun_sra_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_fun_sra;
  assign iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_en = iss_stage_aluIssFifo_0__empty_T ? iss_stage_aluIssFifo_0__GEN_22
     : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_param_rd0[iss_stage_aluIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_param_rd0;
  assign iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_en = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0__GEN_22 : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_param_is_32w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_is_32w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_is_32w_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_param_is_32w[iss_stage_aluIssFifo_0_ram_param_is_32w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_param_is_32w;
  assign iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_en = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0__GEN_22 : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_param_is_usi_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_is_usi_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_is_usi_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_param_is_usi[iss_stage_aluIssFifo_0_ram_param_is_usi_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_param_is_usi;
  assign iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_en = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0__GEN_22 : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_param_dat_op1[iss_stage_aluIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_param_dat_op1;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_en = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0__GEN_22 : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_data =
    iss_stage_aluIssFifo_0_ram_param_dat_op2[iss_stage_aluIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_data = iss_stage_aluIssFifo_0_io_enq_bits_param_dat_op2;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_addr = 1'h0;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_mask = 1'h1;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_en = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0__GEN_22 : iss_stage_aluIssFifo_0__do_enq_T;
  assign iss_stage_aluIssFifo_0_io_enq_ready = ~iss_stage_aluIssFifo_0_maybe_full; // @[Decoupled.scala 305:19]
  assign iss_stage_aluIssFifo_0_io_deq_valid = iss_stage_aluIssFifo_0_io_enq_valid |
    iss_stage_aluIssFifo_0__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign iss_stage_aluIssFifo_0_io_deq_bits_fun_add = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_fun_add : iss_stage_aluIssFifo_0_ram_fun_add_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_fun_slt = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_fun_slt : iss_stage_aluIssFifo_0_ram_fun_slt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_fun_xor = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_fun_xor : iss_stage_aluIssFifo_0_ram_fun_xor_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_fun_or = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_fun_or : iss_stage_aluIssFifo_0_ram_fun_or_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_fun_and = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_fun_and : iss_stage_aluIssFifo_0_ram_fun_and_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_fun_sll = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_fun_sll : iss_stage_aluIssFifo_0_ram_fun_sll_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_fun_srl = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_fun_srl : iss_stage_aluIssFifo_0_ram_fun_srl_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_fun_sra = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_fun_sra : iss_stage_aluIssFifo_0_ram_fun_sra_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_param_rd0 = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_param_rd0 : iss_stage_aluIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_param_is_32w = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_param_is_32w : iss_stage_aluIssFifo_0_ram_param_is_32w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_param_is_usi = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_param_is_usi : iss_stage_aluIssFifo_0_ram_param_is_usi_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_param_dat_op1 = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_param_dat_op1 : iss_stage_aluIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_aluIssFifo_0_io_deq_bits_param_dat_op2 = iss_stage_aluIssFifo_0__empty_T ?
    iss_stage_aluIssFifo_0_io_enq_bits_param_dat_op2 : iss_stage_aluIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_ram_fun_mul_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mul_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mul_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_mul[iss_stage_mulIssFifo_0_ram_fun_mul_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_mul;
  assign iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_mulh_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mulh_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mulh_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_mulh[iss_stage_mulIssFifo_0_ram_fun_mulh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_mulh;
  assign iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhsu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhsu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhsu_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_mulhsu[iss_stage_mulIssFifo_0_ram_fun_mulhsu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_mulhsu;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_en = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0__GEN_25 : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhu_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_mulhu[iss_stage_mulIssFifo_0_ram_fun_mulhu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_mulhu;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_en = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0__GEN_25 : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_div_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_div_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_div_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_div[iss_stage_mulIssFifo_0_ram_fun_div_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_div_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_div;
  assign iss_stage_mulIssFifo_0_ram_fun_div_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_div_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_div_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_divu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_divu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_divu_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_divu[iss_stage_mulIssFifo_0_ram_fun_divu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_divu;
  assign iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_rem_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_rem_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_rem_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_rem[iss_stage_mulIssFifo_0_ram_fun_rem_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_rem;
  assign iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_remu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_remu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_remu_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_remu[iss_stage_mulIssFifo_0_ram_fun_remu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_remu;
  assign iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_mulw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mulw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mulw_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_mulw[iss_stage_mulIssFifo_0_ram_fun_mulw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_mulw;
  assign iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_divw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_divw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_divw_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_divw[iss_stage_mulIssFifo_0_ram_fun_divw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_divw;
  assign iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_divuw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_divuw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_divuw_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_divuw[iss_stage_mulIssFifo_0_ram_fun_divuw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_divuw;
  assign iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_en = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0__GEN_25 : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_remw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_remw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_remw_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_remw[iss_stage_mulIssFifo_0_ram_fun_remw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_remw;
  assign iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_en = iss_stage_mulIssFifo_0__empty_T ? iss_stage_mulIssFifo_0__GEN_25
     : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_fun_remuw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_remuw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_remuw_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_fun_remuw[iss_stage_mulIssFifo_0_ram_fun_remuw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_fun_remuw;
  assign iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_en = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0__GEN_25 : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_param_rd0[iss_stage_mulIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_param_rd0;
  assign iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_en = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0__GEN_25 : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_param_dat_op1[iss_stage_mulIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_param_dat_op1;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_en = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0__GEN_25 : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_data =
    iss_stage_mulIssFifo_0_ram_param_dat_op2[iss_stage_mulIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_data = iss_stage_mulIssFifo_0_io_enq_bits_param_dat_op2;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_addr = 1'h0;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_mask = 1'h1;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_en = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0__GEN_25 : iss_stage_mulIssFifo_0__do_enq_T;
  assign iss_stage_mulIssFifo_0_io_enq_ready = ~iss_stage_mulIssFifo_0_maybe_full; // @[Decoupled.scala 305:19]
  assign iss_stage_mulIssFifo_0_io_deq_valid = iss_stage_mulIssFifo_0_io_enq_valid |
    iss_stage_mulIssFifo_0__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_mul = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_mul : iss_stage_mulIssFifo_0_ram_fun_mul_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_mulh = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_mulh : iss_stage_mulIssFifo_0_ram_fun_mulh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_mulhsu = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_mulhsu : iss_stage_mulIssFifo_0_ram_fun_mulhsu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_mulhu = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_mulhu : iss_stage_mulIssFifo_0_ram_fun_mulhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_div = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_div : iss_stage_mulIssFifo_0_ram_fun_div_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_divu = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_divu : iss_stage_mulIssFifo_0_ram_fun_divu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_rem = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_rem : iss_stage_mulIssFifo_0_ram_fun_rem_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_remu = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_remu : iss_stage_mulIssFifo_0_ram_fun_remu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_mulw = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_mulw : iss_stage_mulIssFifo_0_ram_fun_mulw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_divw = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_divw : iss_stage_mulIssFifo_0_ram_fun_divw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_divuw = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_divuw : iss_stage_mulIssFifo_0_ram_fun_divuw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_remw = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_remw : iss_stage_mulIssFifo_0_ram_fun_remw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_fun_remuw = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_fun_remuw : iss_stage_mulIssFifo_0_ram_fun_remuw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_param_rd0 = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_param_rd0 : iss_stage_mulIssFifo_0_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_param_dat_op1 = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_param_dat_op1 : iss_stage_mulIssFifo_0_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_mulIssFifo_0_io_deq_bits_param_dat_op2 = iss_stage_mulIssFifo_0__empty_T ?
    iss_stage_mulIssFifo_0_io_enq_bits_param_dat_op2 : iss_stage_mulIssFifo_0_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_ram_fun_jalr_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_jalr_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_jalr_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_fun_jalr[iss_stage_bruIssFifo_ram_fun_jalr_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_fun_jalr_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_fun_jalr;
  assign iss_stage_bruIssFifo_ram_fun_jalr_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_jalr_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_jalr_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_fun_beq_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_beq_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_beq_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_fun_beq[iss_stage_bruIssFifo_ram_fun_beq_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_fun_beq_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_fun_beq;
  assign iss_stage_bruIssFifo_ram_fun_beq_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_beq_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_beq_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_fun_bne_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_bne_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_bne_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_fun_bne[iss_stage_bruIssFifo_ram_fun_bne_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_fun_bne_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_fun_bne;
  assign iss_stage_bruIssFifo_ram_fun_bne_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_bne_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_bne_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_fun_blt_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_blt_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_blt_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_fun_blt[iss_stage_bruIssFifo_ram_fun_blt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_fun_blt_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_fun_blt;
  assign iss_stage_bruIssFifo_ram_fun_blt_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_blt_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_blt_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_fun_bge_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_bge_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_bge_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_fun_bge[iss_stage_bruIssFifo_ram_fun_bge_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_fun_bge_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_fun_bge;
  assign iss_stage_bruIssFifo_ram_fun_bge_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_bge_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_bge_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_fun_bltu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_bltu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_bltu_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_fun_bltu[iss_stage_bruIssFifo_ram_fun_bltu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_fun_bltu_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_fun_bltu;
  assign iss_stage_bruIssFifo_ram_fun_bltu_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_bltu_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_bltu_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_fun_bgeu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_bgeu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_bgeu_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_fun_bgeu[iss_stage_bruIssFifo_ram_fun_bgeu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_fun_bgeu;
  assign iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_param_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_rd0_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_param_rd0[iss_stage_bruIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_param_rd0_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_param_rd0;
  assign iss_stage_bruIssFifo_ram_param_rd0_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_rd0_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_rd0_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_param_is_rvc_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_is_rvc_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_is_rvc_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_param_is_rvc[iss_stage_bruIssFifo_ram_param_is_rvc_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_param_is_rvc;
  assign iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23
     : iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_param_pc_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_pc_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_pc_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_param_pc[iss_stage_bruIssFifo_ram_param_pc_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_param_pc_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_param_pc;
  assign iss_stage_bruIssFifo_ram_param_pc_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_pc_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_pc_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_param_imm_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_imm_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_imm_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_param_imm[iss_stage_bruIssFifo_ram_param_imm_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_param_imm_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_param_imm;
  assign iss_stage_bruIssFifo_ram_param_imm_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_imm_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_imm_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23 :
    iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_param_dat_op1[iss_stage_bruIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_param_dat_op1;
  assign iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23
     : iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data =
    iss_stage_bruIssFifo_ram_param_dat_op2[iss_stage_bruIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_data = iss_stage_bruIssFifo_io_enq_bits_param_dat_op2;
  assign iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_addr = 1'h0;
  assign iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_mask = 1'h1;
  assign iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_en = iss_stage_bruIssFifo__empty_T ? iss_stage_bruIssFifo__GEN_23
     : iss_stage_bruIssFifo__do_enq_T;
  assign iss_stage_bruIssFifo_io_enq_ready = ~iss_stage_bruIssFifo_maybe_full; // @[Decoupled.scala 305:19]
  assign iss_stage_bruIssFifo_io_deq_valid = iss_stage_bruIssFifo_io_enq_valid | iss_stage_bruIssFifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign iss_stage_bruIssFifo_io_deq_bits_fun_jalr = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_fun_jalr : iss_stage_bruIssFifo_ram_fun_jalr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_fun_beq = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_fun_beq : iss_stage_bruIssFifo_ram_fun_beq_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_fun_bne = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_fun_bne : iss_stage_bruIssFifo_ram_fun_bne_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_fun_blt = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_fun_blt : iss_stage_bruIssFifo_ram_fun_blt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_fun_bge = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_fun_bge : iss_stage_bruIssFifo_ram_fun_bge_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_fun_bltu = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_fun_bltu : iss_stage_bruIssFifo_ram_fun_bltu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_fun_bgeu = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_fun_bgeu : iss_stage_bruIssFifo_ram_fun_bgeu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_param_rd0 = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_param_rd0 : iss_stage_bruIssFifo_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_param_is_rvc = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_param_is_rvc : iss_stage_bruIssFifo_ram_param_is_rvc_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_param_pc = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_param_pc : iss_stage_bruIssFifo_ram_param_pc_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_param_imm = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_param_imm : iss_stage_bruIssFifo_ram_param_imm_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_param_dat_op1 = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_param_dat_op1 : iss_stage_bruIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_bruIssFifo_io_deq_bits_param_dat_op2 = iss_stage_bruIssFifo__empty_T ?
    iss_stage_bruIssFifo_io_enq_bits_param_dat_op2 : iss_stage_bruIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_csrIssFifo_ram_fun_rw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_csrIssFifo_ram_fun_rw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_fun_rw_io_deq_bits_MPORT_data =
    iss_stage_csrIssFifo_ram_fun_rw[iss_stage_csrIssFifo_ram_fun_rw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_csrIssFifo_ram_fun_rw_MPORT_data = iss_stage_csrIssFifo_io_enq_bits_fun_rw;
  assign iss_stage_csrIssFifo_ram_fun_rw_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_fun_rw_MPORT_mask = 1'h1;
  assign iss_stage_csrIssFifo_ram_fun_rw_MPORT_en = iss_stage_csrIssFifo__empty_T ? iss_stage_csrIssFifo__GEN_15 :
    iss_stage_csrIssFifo__do_enq_T;
  assign iss_stage_csrIssFifo_ram_fun_rs_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_csrIssFifo_ram_fun_rs_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_fun_rs_io_deq_bits_MPORT_data =
    iss_stage_csrIssFifo_ram_fun_rs[iss_stage_csrIssFifo_ram_fun_rs_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_csrIssFifo_ram_fun_rs_MPORT_data = iss_stage_csrIssFifo_io_enq_bits_fun_rs;
  assign iss_stage_csrIssFifo_ram_fun_rs_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_fun_rs_MPORT_mask = 1'h1;
  assign iss_stage_csrIssFifo_ram_fun_rs_MPORT_en = iss_stage_csrIssFifo__empty_T ? iss_stage_csrIssFifo__GEN_15 :
    iss_stage_csrIssFifo__do_enq_T;
  assign iss_stage_csrIssFifo_ram_fun_rc_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_csrIssFifo_ram_fun_rc_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_fun_rc_io_deq_bits_MPORT_data =
    iss_stage_csrIssFifo_ram_fun_rc[iss_stage_csrIssFifo_ram_fun_rc_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_csrIssFifo_ram_fun_rc_MPORT_data = iss_stage_csrIssFifo_io_enq_bits_fun_rc;
  assign iss_stage_csrIssFifo_ram_fun_rc_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_fun_rc_MPORT_mask = 1'h1;
  assign iss_stage_csrIssFifo_ram_fun_rc_MPORT_en = iss_stage_csrIssFifo__empty_T ? iss_stage_csrIssFifo__GEN_15 :
    iss_stage_csrIssFifo__do_enq_T;
  assign iss_stage_csrIssFifo_ram_param_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_csrIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_param_rd0_io_deq_bits_MPORT_data =
    iss_stage_csrIssFifo_ram_param_rd0[iss_stage_csrIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_csrIssFifo_ram_param_rd0_MPORT_data = iss_stage_csrIssFifo_io_enq_bits_param_rd0;
  assign iss_stage_csrIssFifo_ram_param_rd0_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_param_rd0_MPORT_mask = 1'h1;
  assign iss_stage_csrIssFifo_ram_param_rd0_MPORT_en = iss_stage_csrIssFifo__empty_T ? iss_stage_csrIssFifo__GEN_15 :
    iss_stage_csrIssFifo__do_enq_T;
  assign iss_stage_csrIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_csrIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data =
    iss_stage_csrIssFifo_ram_param_dat_op1[iss_stage_csrIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_data = iss_stage_csrIssFifo_io_enq_bits_param_dat_op1;
  assign iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_mask = 1'h1;
  assign iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_en = iss_stage_csrIssFifo__empty_T ? iss_stage_csrIssFifo__GEN_15
     : iss_stage_csrIssFifo__do_enq_T;
  assign iss_stage_csrIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_csrIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data =
    iss_stage_csrIssFifo_ram_param_dat_op2[iss_stage_csrIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_data = iss_stage_csrIssFifo_io_enq_bits_param_dat_op2;
  assign iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_addr = 1'h0;
  assign iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_mask = 1'h1;
  assign iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_en = iss_stage_csrIssFifo__empty_T ? iss_stage_csrIssFifo__GEN_15
     : iss_stage_csrIssFifo__do_enq_T;
  assign iss_stage_csrIssFifo_io_enq_ready = ~iss_stage_csrIssFifo_maybe_full; // @[Decoupled.scala 305:19]
  assign iss_stage_csrIssFifo_io_deq_valid = iss_stage_csrIssFifo_io_enq_valid | iss_stage_csrIssFifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign iss_stage_csrIssFifo_io_deq_bits_fun_rw = iss_stage_csrIssFifo__empty_T ?
    iss_stage_csrIssFifo_io_enq_bits_fun_rw : iss_stage_csrIssFifo_ram_fun_rw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_csrIssFifo_io_deq_bits_fun_rs = iss_stage_csrIssFifo__empty_T ?
    iss_stage_csrIssFifo_io_enq_bits_fun_rs : iss_stage_csrIssFifo_ram_fun_rs_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_csrIssFifo_io_deq_bits_fun_rc = iss_stage_csrIssFifo__empty_T ?
    iss_stage_csrIssFifo_io_enq_bits_fun_rc : iss_stage_csrIssFifo_ram_fun_rc_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_csrIssFifo_io_deq_bits_param_rd0 = iss_stage_csrIssFifo__empty_T ?
    iss_stage_csrIssFifo_io_enq_bits_param_rd0 : iss_stage_csrIssFifo_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_csrIssFifo_io_deq_bits_param_dat_op1 = iss_stage_csrIssFifo__empty_T ?
    iss_stage_csrIssFifo_io_enq_bits_param_dat_op1 : iss_stage_csrIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_csrIssFifo_io_deq_bits_param_dat_op2 = iss_stage_csrIssFifo__empty_T ?
    iss_stage_csrIssFifo_io_enq_bits_param_dat_op2 : iss_stage_csrIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_ram_fun_lb_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lb_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lb_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_lb[iss_stage_lsuIssFifo_ram_fun_lb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_lb_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_lb;
  assign iss_stage_lsuIssFifo_ram_fun_lb_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lb_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lb_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_lh_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lh_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lh_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_lh[iss_stage_lsuIssFifo_ram_fun_lh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_lh_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_lh;
  assign iss_stage_lsuIssFifo_ram_fun_lh_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lh_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lh_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_lw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lw_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_lw[iss_stage_lsuIssFifo_ram_fun_lw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_lw_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_lw;
  assign iss_stage_lsuIssFifo_ram_fun_lw_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lw_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lw_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_ld_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_ld_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_ld_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_ld[iss_stage_lsuIssFifo_ram_fun_ld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_ld_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_ld;
  assign iss_stage_lsuIssFifo_ram_fun_ld_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_ld_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_ld_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_lbu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lbu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lbu_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_lbu[iss_stage_lsuIssFifo_ram_fun_lbu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_lbu;
  assign iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_lhu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lhu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lhu_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_lhu[iss_stage_lsuIssFifo_ram_fun_lhu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_lhu;
  assign iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_lwu_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lwu_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lwu_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_lwu[iss_stage_lsuIssFifo_ram_fun_lwu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_lwu;
  assign iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_sb_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sb_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sb_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_sb[iss_stage_lsuIssFifo_ram_fun_sb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_sb_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_sb;
  assign iss_stage_lsuIssFifo_ram_fun_sb_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sb_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sb_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_sh_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sh_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sh_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_sh[iss_stage_lsuIssFifo_ram_fun_sh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_sh_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_sh;
  assign iss_stage_lsuIssFifo_ram_fun_sh_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sh_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sh_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_sw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sw_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_sw[iss_stage_lsuIssFifo_ram_fun_sw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_sw_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_sw;
  assign iss_stage_lsuIssFifo_ram_fun_sw_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sw_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sw_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_sd_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sd_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sd_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_sd[iss_stage_lsuIssFifo_ram_fun_sd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_sd_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_sd;
  assign iss_stage_lsuIssFifo_ram_fun_sd_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sd_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sd_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_fence_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fence_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fence_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_fence[iss_stage_lsuIssFifo_ram_fun_fence_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_fence_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_fence;
  assign iss_stage_lsuIssFifo_ram_fun_fence_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fence_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fence_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_fence_i_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fence_i_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fence_i_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_fence_i[iss_stage_lsuIssFifo_ram_fun_fence_i_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_fence_i;
  assign iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_sfence_vma_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sfence_vma_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sfence_vma_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_sfence_vma[iss_stage_lsuIssFifo_ram_fun_sfence_vma_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_sfence_vma;
  assign iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_lr_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lr_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lr_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_lr_w[iss_stage_lsuIssFifo_ram_fun_lr_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_lr_w;
  assign iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_sc_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sc_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sc_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_sc_w[iss_stage_lsuIssFifo_ram_fun_sc_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_sc_w;
  assign iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoswap_w[iss_stage_lsuIssFifo_ram_fun_amoswap_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoswap_w;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoadd_w[iss_stage_lsuIssFifo_ram_fun_amoadd_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoadd_w;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoxor_w[iss_stage_lsuIssFifo_ram_fun_amoxor_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoxor_w;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoand_w[iss_stage_lsuIssFifo_ram_fun_amoand_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoand_w;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoor_w[iss_stage_lsuIssFifo_ram_fun_amoor_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoor_w;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amomin_w[iss_stage_lsuIssFifo_ram_fun_amomin_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amomin_w;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amomax_w[iss_stage_lsuIssFifo_ram_fun_amomax_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amomax_w;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amominu_w[iss_stage_lsuIssFifo_ram_fun_amominu_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amominu_w;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amomaxu_w[iss_stage_lsuIssFifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amomaxu_w;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_lr_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lr_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lr_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_lr_d[iss_stage_lsuIssFifo_ram_fun_lr_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_lr_d;
  assign iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_sc_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sc_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sc_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_sc_d[iss_stage_lsuIssFifo_ram_fun_sc_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_sc_d;
  assign iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoswap_d[iss_stage_lsuIssFifo_ram_fun_amoswap_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoswap_d;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoadd_d[iss_stage_lsuIssFifo_ram_fun_amoadd_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoadd_d;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoxor_d[iss_stage_lsuIssFifo_ram_fun_amoxor_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoxor_d;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoand_d[iss_stage_lsuIssFifo_ram_fun_amoand_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoand_d;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amoor_d[iss_stage_lsuIssFifo_ram_fun_amoor_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amoor_d;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amomin_d[iss_stage_lsuIssFifo_ram_fun_amomin_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amomin_d;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amomax_d[iss_stage_lsuIssFifo_ram_fun_amomax_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amomax_d;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amominu_d[iss_stage_lsuIssFifo_ram_fun_amominu_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amominu_d;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_amomaxu_d[iss_stage_lsuIssFifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_amomaxu_d;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_flw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_flw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_flw_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_flw[iss_stage_lsuIssFifo_ram_fun_flw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_flw_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_flw;
  assign iss_stage_lsuIssFifo_ram_fun_flw_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_flw_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_flw_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_fsw_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fsw_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fsw_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_fsw[iss_stage_lsuIssFifo_ram_fun_fsw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_fsw;
  assign iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_fld_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fld_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fld_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_fld[iss_stage_lsuIssFifo_ram_fun_fld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_fld_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_fld;
  assign iss_stage_lsuIssFifo_ram_fun_fld_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fld_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fld_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_fun_fsd_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fsd_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fsd_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_fun_fsd[iss_stage_lsuIssFifo_ram_fun_fsd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_fun_fsd;
  assign iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_param_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_param_rd0_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_param_rd0[iss_stage_lsuIssFifo_ram_param_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_param_rd0_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_param_rd0;
  assign iss_stage_lsuIssFifo_ram_param_rd0_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_param_rd0_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_param_rd0_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52 :
    iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_param_dat_op1[iss_stage_lsuIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_param_dat_op1;
  assign iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_en = 1'h1;
  assign iss_stage_lsuIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data =
    iss_stage_lsuIssFifo_ram_param_dat_op2[iss_stage_lsuIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_data = iss_stage_lsuIssFifo_io_enq_bits_param_dat_op2;
  assign iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_addr = 1'h0;
  assign iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_mask = 1'h1;
  assign iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_en = iss_stage_lsuIssFifo__empty_T ? iss_stage_lsuIssFifo__GEN_52
     : iss_stage_lsuIssFifo__do_enq_T;
  assign iss_stage_lsuIssFifo_io_enq_ready = ~iss_stage_lsuIssFifo_maybe_full; // @[Decoupled.scala 305:19]
  assign iss_stage_lsuIssFifo_io_deq_valid = iss_stage_lsuIssFifo_io_enq_valid | iss_stage_lsuIssFifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_lb = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_lb : iss_stage_lsuIssFifo_ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_lh = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_lh : iss_stage_lsuIssFifo_ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_lw = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_lw : iss_stage_lsuIssFifo_ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_ld = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_ld : iss_stage_lsuIssFifo_ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_lbu = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_lbu : iss_stage_lsuIssFifo_ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_lhu = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_lhu : iss_stage_lsuIssFifo_ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_lwu = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_lwu : iss_stage_lsuIssFifo_ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_sb = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_sb : iss_stage_lsuIssFifo_ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_sh = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_sh : iss_stage_lsuIssFifo_ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_sw = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_sw : iss_stage_lsuIssFifo_ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_sd = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_sd : iss_stage_lsuIssFifo_ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_fence = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_fence : iss_stage_lsuIssFifo_ram_fun_fence_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_fence_i = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_fence_i : iss_stage_lsuIssFifo_ram_fun_fence_i_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_sfence_vma = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_sfence_vma : iss_stage_lsuIssFifo_ram_fun_sfence_vma_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_lr_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_lr_w : iss_stage_lsuIssFifo_ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_sc_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_sc_w : iss_stage_lsuIssFifo_ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoswap_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoswap_w : iss_stage_lsuIssFifo_ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoadd_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoadd_w : iss_stage_lsuIssFifo_ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoxor_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoxor_w : iss_stage_lsuIssFifo_ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoand_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoand_w : iss_stage_lsuIssFifo_ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoor_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoor_w : iss_stage_lsuIssFifo_ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amomin_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amomin_w : iss_stage_lsuIssFifo_ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amomax_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amomax_w : iss_stage_lsuIssFifo_ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amominu_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amominu_w : iss_stage_lsuIssFifo_ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amomaxu_w = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amomaxu_w : iss_stage_lsuIssFifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_lr_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_lr_d : iss_stage_lsuIssFifo_ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_sc_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_sc_d : iss_stage_lsuIssFifo_ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoswap_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoswap_d : iss_stage_lsuIssFifo_ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoadd_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoadd_d : iss_stage_lsuIssFifo_ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoxor_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoxor_d : iss_stage_lsuIssFifo_ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoand_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoand_d : iss_stage_lsuIssFifo_ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amoor_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amoor_d : iss_stage_lsuIssFifo_ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amomin_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amomin_d : iss_stage_lsuIssFifo_ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amomax_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amomax_d : iss_stage_lsuIssFifo_ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amominu_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amominu_d : iss_stage_lsuIssFifo_ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_amomaxu_d = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_amomaxu_d : iss_stage_lsuIssFifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_flw = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_flw : iss_stage_lsuIssFifo_ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_fsw = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_fsw : iss_stage_lsuIssFifo_ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_fld = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_fld : iss_stage_lsuIssFifo_ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_fun_fsd = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_fun_fsd : iss_stage_lsuIssFifo_ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_param_rd0 = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_param_rd0 : iss_stage_lsuIssFifo_ram_param_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_param_dat_op1 = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_param_dat_op1 : iss_stage_lsuIssFifo_ram_param_dat_op1_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_lsuIssFifo_io_deq_bits_param_dat_op2 = iss_stage_lsuIssFifo__empty_T ?
    iss_stage_lsuIssFifo_io_enq_bits_param_dat_op2 : iss_stage_lsuIssFifo_ram_param_dat_op2_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign iss_stage_io_dptReq_0_ready = 1'h1; // @[Issue.scala 78:76]
  assign iss_stage_io_alu_iss_exe_0_valid = iss_stage_aluIssFifo_0_io_deq_valid; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_fun_add = iss_stage_aluIssFifo_0_io_deq_bits_fun_add; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_fun_slt = iss_stage_aluIssFifo_0_io_deq_bits_fun_slt; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_fun_xor = iss_stage_aluIssFifo_0_io_deq_bits_fun_xor; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_fun_or = iss_stage_aluIssFifo_0_io_deq_bits_fun_or; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_fun_and = iss_stage_aluIssFifo_0_io_deq_bits_fun_and; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_fun_sll = iss_stage_aluIssFifo_0_io_deq_bits_fun_sll; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_fun_srl = iss_stage_aluIssFifo_0_io_deq_bits_fun_srl; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_fun_sra = iss_stage_aluIssFifo_0_io_deq_bits_fun_sra; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_param_rd0 = iss_stage_aluIssFifo_0_io_deq_bits_param_rd0; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_param_is_32w = iss_stage_aluIssFifo_0_io_deq_bits_param_is_32w; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_param_is_usi = iss_stage_aluIssFifo_0_io_deq_bits_param_is_usi; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_param_dat_op1 = iss_stage_aluIssFifo_0_io_deq_bits_param_dat_op1; // @[Issue.scala 647:28]
  assign iss_stage_io_alu_iss_exe_0_bits_param_dat_op2 = iss_stage_aluIssFifo_0_io_deq_bits_param_dat_op2; // @[Issue.scala 647:28]
  assign iss_stage_io_mul_iss_exe_0_valid = iss_stage_mulIssFifo_0_io_deq_valid; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_mul = iss_stage_mulIssFifo_0_io_deq_bits_fun_mul; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_mulh = iss_stage_mulIssFifo_0_io_deq_bits_fun_mulh; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_mulhsu = iss_stage_mulIssFifo_0_io_deq_bits_fun_mulhsu; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_mulhu = iss_stage_mulIssFifo_0_io_deq_bits_fun_mulhu; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_div = iss_stage_mulIssFifo_0_io_deq_bits_fun_div; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_divu = iss_stage_mulIssFifo_0_io_deq_bits_fun_divu; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_rem = iss_stage_mulIssFifo_0_io_deq_bits_fun_rem; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_remu = iss_stage_mulIssFifo_0_io_deq_bits_fun_remu; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_mulw = iss_stage_mulIssFifo_0_io_deq_bits_fun_mulw; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_divw = iss_stage_mulIssFifo_0_io_deq_bits_fun_divw; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_divuw = iss_stage_mulIssFifo_0_io_deq_bits_fun_divuw; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_remw = iss_stage_mulIssFifo_0_io_deq_bits_fun_remw; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_fun_remuw = iss_stage_mulIssFifo_0_io_deq_bits_fun_remuw; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_param_rd0 = iss_stage_mulIssFifo_0_io_deq_bits_param_rd0; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_param_dat_op1 = iss_stage_mulIssFifo_0_io_deq_bits_param_dat_op1; // @[Issue.scala 712:30]
  assign iss_stage_io_mul_iss_exe_0_bits_param_dat_op2 = iss_stage_mulIssFifo_0_io_deq_bits_param_dat_op2; // @[Issue.scala 712:30]
  assign iss_stage_io_bru_iss_exe_valid = iss_stage_bruIssFifo_io_deq_valid; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_fun_jalr = iss_stage_bruIssFifo_io_deq_bits_fun_jalr; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_fun_beq = iss_stage_bruIssFifo_io_deq_bits_fun_beq; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_fun_bne = iss_stage_bruIssFifo_io_deq_bits_fun_bne; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_fun_blt = iss_stage_bruIssFifo_io_deq_bits_fun_blt; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_fun_bge = iss_stage_bruIssFifo_io_deq_bits_fun_bge; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_fun_bltu = iss_stage_bruIssFifo_io_deq_bits_fun_bltu; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_fun_bgeu = iss_stage_bruIssFifo_io_deq_bits_fun_bgeu; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_param_rd0 = iss_stage_bruIssFifo_io_deq_bits_param_rd0; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_param_is_rvc = iss_stage_bruIssFifo_io_deq_bits_param_is_rvc; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_param_pc = iss_stage_bruIssFifo_io_deq_bits_param_pc; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_param_imm = iss_stage_bruIssFifo_io_deq_bits_param_imm; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_param_dat_op1 = iss_stage_bruIssFifo_io_deq_bits_param_dat_op1; // @[Issue.scala 779:21]
  assign iss_stage_io_bru_iss_exe_bits_param_dat_op2 = iss_stage_bruIssFifo_io_deq_bits_param_dat_op2; // @[Issue.scala 779:21]
  assign iss_stage_io_csr_iss_exe_valid = iss_stage_csrIssFifo_io_deq_valid; // @[Issue.scala 845:21]
  assign iss_stage_io_csr_iss_exe_bits_fun_rw = iss_stage_csrIssFifo_io_deq_bits_fun_rw; // @[Issue.scala 845:21]
  assign iss_stage_io_csr_iss_exe_bits_fun_rs = iss_stage_csrIssFifo_io_deq_bits_fun_rs; // @[Issue.scala 845:21]
  assign iss_stage_io_csr_iss_exe_bits_fun_rc = iss_stage_csrIssFifo_io_deq_bits_fun_rc; // @[Issue.scala 845:21]
  assign iss_stage_io_csr_iss_exe_bits_param_rd0 = iss_stage_csrIssFifo_io_deq_bits_param_rd0; // @[Issue.scala 845:21]
  assign iss_stage_io_csr_iss_exe_bits_param_dat_op1 = iss_stage_csrIssFifo_io_deq_bits_param_dat_op1; // @[Issue.scala 845:21]
  assign iss_stage_io_csr_iss_exe_bits_param_dat_op2 = iss_stage_csrIssFifo_io_deq_bits_param_dat_op2; // @[Issue.scala 845:21]
  assign iss_stage_io_lsu_iss_exe_valid = iss_stage_lsuIssFifo_io_deq_valid; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_lb = iss_stage_lsuIssFifo_io_deq_bits_fun_lb; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_lh = iss_stage_lsuIssFifo_io_deq_bits_fun_lh; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_lw = iss_stage_lsuIssFifo_io_deq_bits_fun_lw; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_ld = iss_stage_lsuIssFifo_io_deq_bits_fun_ld; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_lbu = iss_stage_lsuIssFifo_io_deq_bits_fun_lbu; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_lhu = iss_stage_lsuIssFifo_io_deq_bits_fun_lhu; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_lwu = iss_stage_lsuIssFifo_io_deq_bits_fun_lwu; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_sb = iss_stage_lsuIssFifo_io_deq_bits_fun_sb; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_sh = iss_stage_lsuIssFifo_io_deq_bits_fun_sh; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_sw = iss_stage_lsuIssFifo_io_deq_bits_fun_sw; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_sd = iss_stage_lsuIssFifo_io_deq_bits_fun_sd; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_fence = iss_stage_lsuIssFifo_io_deq_bits_fun_fence; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_fence_i = iss_stage_lsuIssFifo_io_deq_bits_fun_fence_i; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_sfence_vma = iss_stage_lsuIssFifo_io_deq_bits_fun_sfence_vma; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_lr_w = iss_stage_lsuIssFifo_io_deq_bits_fun_lr_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_sc_w = iss_stage_lsuIssFifo_io_deq_bits_fun_sc_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoswap_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amoswap_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoadd_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amoadd_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoxor_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amoxor_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoand_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amoand_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoor_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amoor_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amomin_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amomin_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amomax_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amomax_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amominu_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amominu_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amomaxu_w = iss_stage_lsuIssFifo_io_deq_bits_fun_amomaxu_w; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_lr_d = iss_stage_lsuIssFifo_io_deq_bits_fun_lr_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_sc_d = iss_stage_lsuIssFifo_io_deq_bits_fun_sc_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoswap_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amoswap_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoadd_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amoadd_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoxor_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amoxor_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoand_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amoand_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amoor_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amoor_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amomin_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amomin_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amomax_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amomax_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amominu_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amominu_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_amomaxu_d = iss_stage_lsuIssFifo_io_deq_bits_fun_amomaxu_d; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_flw = iss_stage_lsuIssFifo_io_deq_bits_fun_flw; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_fsw = iss_stage_lsuIssFifo_io_deq_bits_fun_fsw; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_fld = iss_stage_lsuIssFifo_io_deq_bits_fun_fld; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_fun_fsd = iss_stage_lsuIssFifo_io_deq_bits_fun_fsd; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_param_rd0 = iss_stage_lsuIssFifo_io_deq_bits_param_rd0; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_param_dat_op1 = iss_stage_lsuIssFifo_io_deq_bits_param_dat_op1; // @[Issue.scala 908:21]
  assign iss_stage_io_lsu_iss_exe_bits_param_dat_op2 = iss_stage_lsuIssFifo_io_deq_bits_param_dat_op2; // @[Issue.scala 908:21]
  assign iss_stage_io_fpu_iss_exe_0_valid = 1'h0; // @[Issue.scala 987:29]
  assign iss_stage_io_irgReq_0_valid = iss_stage__rIOpNum_0_T | iss_stage__rIOpNum_0_T_1; // @[Issue.scala 318:49]
  assign iss_stage_io_irgReq_0_bits = iss_stage__rIOpNum_0_T ? iss_stage__selIRS1_0_T_22 : iss_stage__rIOpNum_0_T_2; // @[Issue.scala 313:26]
  assign iss_stage_aluIssFifo_0_clock = iss_stage_clock;
  assign iss_stage_aluIssFifo_0_reset = iss_stage_io_flush | iss_stage_reset; // @[Issue.scala 648:39]
  assign iss_stage_aluIssFifo_0_io_enq_valid = ~iss_stage__T_300; // @[Issue.scala 634:37]
  assign iss_stage_aluIssFifo_0_io_enq_bits_fun_add = iss_stage__aluIssFifo_0_io_enq_bits_T_47 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_48; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_fun_slt = iss_stage__aluIssFifo_0_io_enq_bits_T_44 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_45; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_fun_xor = iss_stage__aluIssFifo_0_io_enq_bits_T_41 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_42; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_fun_or = iss_stage__aluIssFifo_0_io_enq_bits_T_38 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_39; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_fun_and = iss_stage__aluIssFifo_0_io_enq_bits_T_35 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_36; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_fun_sll = iss_stage__aluIssFifo_0_io_enq_bits_T_32 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_33; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_fun_srl = iss_stage__aluIssFifo_0_io_enq_bits_T_29 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_30; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_fun_sra = iss_stage__aluIssFifo_0_io_enq_bits_T_26 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_27; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_param_rd0 = iss_stage__aluIssFifo_0_io_enq_bits_T_23 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_24; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_param_is_32w = iss_stage__aluIssFifo_0_io_enq_bits_T_20 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_21; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_param_is_usi = iss_stage__aluIssFifo_0_io_enq_bits_T_17 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_18; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_param_dat_op1 = iss_stage__aluIssFifo_0_io_enq_bits_T_14 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_15; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_enq_bits_param_dat_op2 = iss_stage__aluIssFifo_0_io_enq_bits_T_11 |
    iss_stage__aluIssFifo_0_io_enq_bits_T_12; // @[Mux.scala 27:73]
  assign iss_stage_aluIssFifo_0_io_deq_ready = iss_stage_io_alu_iss_exe_0_ready; // @[Issue.scala 647:28]
  assign iss_stage_mulIssFifo_0_clock = iss_stage_clock;
  assign iss_stage_mulIssFifo_0_reset = iss_stage_io_flush | iss_stage_reset; // @[Issue.scala 713:41]
  assign iss_stage_mulIssFifo_0_io_enq_valid = ~iss_stage__T_411; // @[Issue.scala 699:39]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_mul = iss_stage__mulIssFifo_0_io_enq_bits_T_56 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_57; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_mulh = iss_stage__mulIssFifo_0_io_enq_bits_T_53 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_54; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_mulhsu = iss_stage__mulIssFifo_0_io_enq_bits_T_50 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_51; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_mulhu = iss_stage__mulIssFifo_0_io_enq_bits_T_47 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_48; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_div = iss_stage__mulIssFifo_0_io_enq_bits_T_44 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_45; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_divu = iss_stage__mulIssFifo_0_io_enq_bits_T_41 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_42; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_rem = iss_stage__mulIssFifo_0_io_enq_bits_T_38 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_39; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_remu = iss_stage__mulIssFifo_0_io_enq_bits_T_35 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_36; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_mulw = iss_stage__mulIssFifo_0_io_enq_bits_T_32 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_33; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_divw = iss_stage__mulIssFifo_0_io_enq_bits_T_29 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_30; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_divuw = iss_stage__mulIssFifo_0_io_enq_bits_T_26 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_27; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_remw = iss_stage__mulIssFifo_0_io_enq_bits_T_23 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_24; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_fun_remuw = iss_stage__mulIssFifo_0_io_enq_bits_T_20 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_21; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_param_rd0 = iss_stage__mulIssFifo_0_io_enq_bits_T_17 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_18; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_param_dat_op1 = iss_stage__mulIssFifo_0_io_enq_bits_T_14 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_15; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_enq_bits_param_dat_op2 = iss_stage__mulIssFifo_0_io_enq_bits_T_11 |
    iss_stage__mulIssFifo_0_io_enq_bits_T_12; // @[Mux.scala 27:73]
  assign iss_stage_mulIssFifo_0_io_deq_ready = iss_stage_io_mul_iss_exe_0_ready; // @[Issue.scala 712:30]
  assign iss_stage_bruIssFifo_clock = iss_stage_clock;
  assign iss_stage_bruIssFifo_reset = iss_stage_io_flush | iss_stage_reset; // @[Issue.scala 780:32]
  assign iss_stage_bruIssFifo_io_enq_valid = iss_stage__bruIssFifo_io_enq_valid_T_5 |
    iss_stage__bruIssFifo_io_enq_valid_T_11; // @[Issue.scala 765:149]
  assign iss_stage_bruIssFifo_io_enq_bits_fun_jalr = iss_stage__bruIssFifo_io_enq_bits_T_51 |
    iss_stage__bruIssFifo_io_enq_bits_T_52; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_fun_beq = iss_stage__bruIssFifo_io_enq_bits_T_48 |
    iss_stage__bruIssFifo_io_enq_bits_T_49; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_fun_bne = iss_stage__bruIssFifo_io_enq_bits_T_45 |
    iss_stage__bruIssFifo_io_enq_bits_T_46; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_fun_blt = iss_stage__bruIssFifo_io_enq_bits_T_42 |
    iss_stage__bruIssFifo_io_enq_bits_T_43; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_fun_bge = iss_stage__bruIssFifo_io_enq_bits_T_39 |
    iss_stage__bruIssFifo_io_enq_bits_T_40; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_fun_bltu = iss_stage__bruIssFifo_io_enq_bits_T_36 |
    iss_stage__bruIssFifo_io_enq_bits_T_37; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_fun_bgeu = iss_stage__bruIssFifo_io_enq_bits_T_33 |
    iss_stage__bruIssFifo_io_enq_bits_T_34; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_param_rd0 = iss_stage__bruIssFifo_io_enq_bits_T_30 |
    iss_stage__bruIssFifo_io_enq_bits_T_31; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_param_is_rvc = iss_stage__bruIssFifo_io_enq_bits_T_27 |
    iss_stage__bruIssFifo_io_enq_bits_T_28; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_param_pc = iss_stage__bruIssFifo_io_enq_bits_T_24 |
    iss_stage__bruIssFifo_io_enq_bits_T_25; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_param_imm = iss_stage__bruIssFifo_io_enq_bits_T_21 |
    iss_stage__bruIssFifo_io_enq_bits_T_22; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_param_dat_op1 = iss_stage__bruIssFifo_io_enq_bits_T_18 |
    iss_stage__bruIssFifo_io_enq_bits_T_19; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_enq_bits_param_dat_op2 = iss_stage__bruIssFifo_io_enq_bits_T_15 |
    iss_stage__bruIssFifo_io_enq_bits_T_16; // @[Mux.scala 27:73]
  assign iss_stage_bruIssFifo_io_deq_ready = iss_stage_io_bru_iss_exe_ready; // @[Issue.scala 779:21]
  assign iss_stage_csrIssFifo_clock = iss_stage_clock;
  assign iss_stage_csrIssFifo_reset = iss_stage_io_flush | iss_stage_reset; // @[Issue.scala 846:32]
  assign iss_stage_csrIssFifo_io_enq_valid = iss_stage__csrIssFifo_io_enq_valid_T_5 |
    iss_stage__csrIssFifo_io_enq_valid_T_11; // @[Issue.scala 831:149]
  assign iss_stage_csrIssFifo_io_enq_bits_fun_rw = iss_stage__csrIssFifo_io_enq_bits_T_30 |
    iss_stage__csrIssFifo_io_enq_bits_T_31; // @[Mux.scala 27:73]
  assign iss_stage_csrIssFifo_io_enq_bits_fun_rs = iss_stage__csrIssFifo_io_enq_bits_T_27 |
    iss_stage__csrIssFifo_io_enq_bits_T_28; // @[Mux.scala 27:73]
  assign iss_stage_csrIssFifo_io_enq_bits_fun_rc = iss_stage__csrIssFifo_io_enq_bits_T_24 |
    iss_stage__csrIssFifo_io_enq_bits_T_25; // @[Mux.scala 27:73]
  assign iss_stage_csrIssFifo_io_enq_bits_param_rd0 = iss_stage__csrIssFifo_io_enq_bits_T_21 |
    iss_stage__csrIssFifo_io_enq_bits_T_22; // @[Mux.scala 27:73]
  assign iss_stage_csrIssFifo_io_enq_bits_param_dat_op1 = iss_stage__csrIssFifo_io_enq_bits_T_18 |
    iss_stage__csrIssFifo_io_enq_bits_T_19; // @[Mux.scala 27:73]
  assign iss_stage_csrIssFifo_io_enq_bits_param_dat_op2 = iss_stage__csrIssFifo_io_enq_bits_T_15 |
    iss_stage__csrIssFifo_io_enq_bits_T_16; // @[Mux.scala 27:73]
  assign iss_stage_csrIssFifo_io_deq_ready = iss_stage_io_csr_iss_exe_ready; // @[Issue.scala 845:21]
  assign iss_stage_lsuIssFifo_clock = iss_stage_clock;
  assign iss_stage_lsuIssFifo_reset = iss_stage_io_flush | iss_stage_reset; // @[Issue.scala 909:32]
  assign iss_stage_lsuIssFifo_io_enq_valid = iss_stage__lsuIssFifo_io_enq_valid_T_5 |
    iss_stage__lsuIssFifo_io_enq_valid_T_11; // @[Issue.scala 894:149]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_lb = iss_stage__lsuIssFifo_io_enq_bits_T_141 |
    iss_stage__lsuIssFifo_io_enq_bits_T_142; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_lh = iss_stage__lsuIssFifo_io_enq_bits_T_138 |
    iss_stage__lsuIssFifo_io_enq_bits_T_139; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_lw = iss_stage__lsuIssFifo_io_enq_bits_T_135 |
    iss_stage__lsuIssFifo_io_enq_bits_T_136; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_ld = iss_stage__lsuIssFifo_io_enq_bits_T_132 |
    iss_stage__lsuIssFifo_io_enq_bits_T_133; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_lbu = iss_stage__lsuIssFifo_io_enq_bits_T_129 |
    iss_stage__lsuIssFifo_io_enq_bits_T_130; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_lhu = iss_stage__lsuIssFifo_io_enq_bits_T_126 |
    iss_stage__lsuIssFifo_io_enq_bits_T_127; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_lwu = iss_stage__lsuIssFifo_io_enq_bits_T_123 |
    iss_stage__lsuIssFifo_io_enq_bits_T_124; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_sb = iss_stage__lsuIssFifo_io_enq_bits_T_120 |
    iss_stage__lsuIssFifo_io_enq_bits_T_121; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_sh = iss_stage__lsuIssFifo_io_enq_bits_T_117 |
    iss_stage__lsuIssFifo_io_enq_bits_T_118; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_sw = iss_stage__lsuIssFifo_io_enq_bits_T_114 |
    iss_stage__lsuIssFifo_io_enq_bits_T_115; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_sd = iss_stage__lsuIssFifo_io_enq_bits_T_111 |
    iss_stage__lsuIssFifo_io_enq_bits_T_112; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_fence = iss_stage__lsuIssFifo_io_enq_bits_T_108 |
    iss_stage__lsuIssFifo_io_enq_bits_T_109; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_fence_i = iss_stage__lsuIssFifo_io_enq_bits_T_105 |
    iss_stage__lsuIssFifo_io_enq_bits_T_106; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_sfence_vma = iss_stage__lsuIssFifo_io_enq_bits_T_102 |
    iss_stage__lsuIssFifo_io_enq_bits_T_103; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_lr_w = iss_stage__lsuIssFifo_io_enq_bits_T_99 |
    iss_stage__lsuIssFifo_io_enq_bits_T_100; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_sc_w = iss_stage__lsuIssFifo_io_enq_bits_T_96 |
    iss_stage__lsuIssFifo_io_enq_bits_T_97; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoswap_w = iss_stage__lsuIssFifo_io_enq_bits_T_93 |
    iss_stage__lsuIssFifo_io_enq_bits_T_94; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoadd_w = iss_stage__lsuIssFifo_io_enq_bits_T_90 |
    iss_stage__lsuIssFifo_io_enq_bits_T_91; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoxor_w = iss_stage__lsuIssFifo_io_enq_bits_T_87 |
    iss_stage__lsuIssFifo_io_enq_bits_T_88; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoand_w = iss_stage__lsuIssFifo_io_enq_bits_T_84 |
    iss_stage__lsuIssFifo_io_enq_bits_T_85; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoor_w = iss_stage__lsuIssFifo_io_enq_bits_T_81 |
    iss_stage__lsuIssFifo_io_enq_bits_T_82; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amomin_w = iss_stage__lsuIssFifo_io_enq_bits_T_78 |
    iss_stage__lsuIssFifo_io_enq_bits_T_79; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amomax_w = iss_stage__lsuIssFifo_io_enq_bits_T_75 |
    iss_stage__lsuIssFifo_io_enq_bits_T_76; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amominu_w = iss_stage__lsuIssFifo_io_enq_bits_T_72 |
    iss_stage__lsuIssFifo_io_enq_bits_T_73; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amomaxu_w = iss_stage__lsuIssFifo_io_enq_bits_T_69 |
    iss_stage__lsuIssFifo_io_enq_bits_T_70; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_lr_d = iss_stage__lsuIssFifo_io_enq_bits_T_66 |
    iss_stage__lsuIssFifo_io_enq_bits_T_67; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_sc_d = iss_stage__lsuIssFifo_io_enq_bits_T_63 |
    iss_stage__lsuIssFifo_io_enq_bits_T_64; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoswap_d = iss_stage__lsuIssFifo_io_enq_bits_T_60 |
    iss_stage__lsuIssFifo_io_enq_bits_T_61; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoadd_d = iss_stage__lsuIssFifo_io_enq_bits_T_57 |
    iss_stage__lsuIssFifo_io_enq_bits_T_58; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoxor_d = iss_stage__lsuIssFifo_io_enq_bits_T_54 |
    iss_stage__lsuIssFifo_io_enq_bits_T_55; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoand_d = iss_stage__lsuIssFifo_io_enq_bits_T_51 |
    iss_stage__lsuIssFifo_io_enq_bits_T_52; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amoor_d = iss_stage__lsuIssFifo_io_enq_bits_T_48 |
    iss_stage__lsuIssFifo_io_enq_bits_T_49; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amomin_d = iss_stage__lsuIssFifo_io_enq_bits_T_45 |
    iss_stage__lsuIssFifo_io_enq_bits_T_46; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amomax_d = iss_stage__lsuIssFifo_io_enq_bits_T_42 |
    iss_stage__lsuIssFifo_io_enq_bits_T_43; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amominu_d = iss_stage__lsuIssFifo_io_enq_bits_T_39 |
    iss_stage__lsuIssFifo_io_enq_bits_T_40; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_amomaxu_d = iss_stage__lsuIssFifo_io_enq_bits_T_36 |
    iss_stage__lsuIssFifo_io_enq_bits_T_37; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_flw = iss_stage__lsuIssFifo_io_enq_bits_T_33 |
    iss_stage__lsuIssFifo_io_enq_bits_T_34; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_fsw = iss_stage__lsuIssFifo_io_enq_bits_T_30 |
    iss_stage__lsuIssFifo_io_enq_bits_T_31; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_fld = iss_stage__lsuIssFifo_io_enq_bits_T_27 |
    iss_stage__lsuIssFifo_io_enq_bits_T_28; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_fun_fsd = iss_stage__lsuIssFifo_io_enq_bits_T_24 |
    iss_stage__lsuIssFifo_io_enq_bits_T_25; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_param_rd0 = iss_stage__lsuIssFifo_io_enq_bits_T_21 |
    iss_stage__lsuIssFifo_io_enq_bits_T_22; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_param_dat_op1 = iss_stage__lsuIssFifo_io_enq_bits_T_18 |
    iss_stage__lsuIssFifo_io_enq_bits_T_19; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_enq_bits_param_dat_op2 = iss_stage__lsuIssFifo_io_enq_bits_T_15 |
    iss_stage__lsuIssFifo_io_enq_bits_T_16; // @[Mux.scala 27:73]
  assign iss_stage_lsuIssFifo_io_deq_ready = iss_stage_io_lsu_iss_exe_ready; // @[Issue.scala 908:21]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data =
    exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0[exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_data = exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_bits_rd0;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_addr = 1'h0;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_mask = 1'h1;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_en = exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_ready &
    exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_valid;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data =
    exe_stage_alu_0_alu_exe_iwb_fifo_ram_res[exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_data = exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_bits_res;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_addr = 1'h0;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_mask = 1'h1;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_en = exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_ready &
    exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_valid;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_ready = exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_ready |
    exe_stage_alu_0_alu_exe_iwb_fifo__empty_T; // @[Decoupled.scala 305:16 325:{24,39}]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_valid = ~exe_stage_alu_0_alu_exe_iwb_fifo__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_bits_rd0 =
    exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_bits_res =
    exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_alu_0_io_alu_iss_exe_ready = exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_ready &
    exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_alu_0_io_alu_exe_iwb_valid = exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_valid; // @[Alu.scala 39:18]
  assign exe_stage_alu_0_io_alu_exe_iwb_bits_rd0 = exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_bits_rd0; // @[Alu.scala 39:18]
  assign exe_stage_alu_0_io_alu_exe_iwb_bits_res = exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_bits_res; // @[Alu.scala 39:18]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_clock = exe_stage_alu_0_clock;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_reset = exe_stage_alu_0_reset | exe_stage_alu_0_io_flush; // @[Alu.scala 40:42]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_valid = exe_stage_alu_0_io_alu_iss_exe_valid; // @[Alu.scala 90:33]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_bits_rd0 = exe_stage_alu_0_io_alu_iss_exe_bits_param_rd0; // @[Alu.scala 92:36]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_io_enq_bits_res = exe_stage_alu_0_res[63:0]; // @[Alu.scala 91:36]
  assign exe_stage_alu_0_alu_exe_iwb_fifo_io_deq_ready = exe_stage_alu_0_io_alu_exe_iwb_ready; // @[Alu.scala 39:18]
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data =
    exe_stage_bru_bru_exe_iwb_fifo_ram_rd0[exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_data = exe_stage_bru_bru_exe_iwb_fifo_io_enq_bits_rd0;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_addr = 1'h0;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_mask = 1'h1;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_en = exe_stage_bru_bru_exe_iwb_fifo_io_enq_ready &
    exe_stage_bru_bru_exe_iwb_fifo_io_enq_valid;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data =
    exe_stage_bru_bru_exe_iwb_fifo_ram_res[exe_stage_bru_bru_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_data = exe_stage_bru_bru_exe_iwb_fifo_io_enq_bits_res;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_addr = 1'h0;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_mask = 1'h1;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_en = exe_stage_bru_bru_exe_iwb_fifo_io_enq_ready &
    exe_stage_bru_bru_exe_iwb_fifo_io_enq_valid;
  assign exe_stage_bru_bru_exe_iwb_fifo_io_enq_ready = exe_stage_bru_bru_exe_iwb_fifo_io_deq_ready |
    exe_stage_bru_bru_exe_iwb_fifo__empty_T; // @[Decoupled.scala 305:16 325:{24,39}]
  assign exe_stage_bru_bru_exe_iwb_fifo_io_deq_valid = ~exe_stage_bru_bru_exe_iwb_fifo__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_bru_bru_exe_iwb_fifo_io_deq_bits_rd0 = exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_bru_exe_iwb_fifo_io_deq_bits_res = exe_stage_bru_bru_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_bctq_ram_pc_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_bctq_ram_pc_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_pc_io_deq_bits_MPORT_data =
    exe_stage_bru_bctq_ram_pc[exe_stage_bru_bctq_ram_pc_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_bctq_ram_pc_MPORT_data = exe_stage_bru_bctq_io_enq_bits_pc;
  assign exe_stage_bru_bctq_ram_pc_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_pc_MPORT_mask = 1'h1;
  assign exe_stage_bru_bctq_ram_pc_MPORT_en = exe_stage_bru_bctq_io_enq_ready & exe_stage_bru_bctq_io_enq_valid;
  assign exe_stage_bru_bctq_ram_bimResp_bim_p_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_bctq_ram_bimResp_bim_p_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_bimResp_bim_p_io_deq_bits_MPORT_data =
    exe_stage_bru_bctq_ram_bimResp_bim_p[exe_stage_bru_bctq_ram_bimResp_bim_p_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_data = exe_stage_bru_bctq_io_enq_bits_bimResp_bim_p;
  assign exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_mask = 1'h1;
  assign exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_en = exe_stage_bru_bctq_io_enq_ready &
    exe_stage_bru_bctq_io_enq_valid;
  assign exe_stage_bru_bctq_ram_bimResp_bim_h_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_bctq_ram_bimResp_bim_h_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_bimResp_bim_h_io_deq_bits_MPORT_data =
    exe_stage_bru_bctq_ram_bimResp_bim_h[exe_stage_bru_bctq_ram_bimResp_bim_h_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_data = exe_stage_bru_bctq_io_enq_bits_bimResp_bim_h;
  assign exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_mask = 1'h1;
  assign exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_en = exe_stage_bru_bctq_io_enq_ready &
    exe_stage_bru_bctq_io_enq_valid;
  assign exe_stage_bru_bctq_ram_isPredictTaken_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_bctq_ram_isPredictTaken_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_isPredictTaken_io_deq_bits_MPORT_data =
    exe_stage_bru_bctq_ram_isPredictTaken[exe_stage_bru_bctq_ram_isPredictTaken_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_bctq_ram_isPredictTaken_MPORT_data = exe_stage_bru_bctq_io_enq_bits_isPredictTaken;
  assign exe_stage_bru_bctq_ram_isPredictTaken_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_isPredictTaken_MPORT_mask = 1'h1;
  assign exe_stage_bru_bctq_ram_isPredictTaken_MPORT_en = exe_stage_bru_bctq_io_enq_ready &
    exe_stage_bru_bctq_io_enq_valid;
  assign exe_stage_bru_bctq_ram_isFinalTaken_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_bctq_ram_isFinalTaken_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_isFinalTaken_io_deq_bits_MPORT_data =
    exe_stage_bru_bctq_ram_isFinalTaken[exe_stage_bru_bctq_ram_isFinalTaken_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_bctq_ram_isFinalTaken_MPORT_data = exe_stage_bru_bctq_io_enq_bits_isFinalTaken;
  assign exe_stage_bru_bctq_ram_isFinalTaken_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_isFinalTaken_MPORT_mask = 1'h1;
  assign exe_stage_bru_bctq_ram_isFinalTaken_MPORT_en = exe_stage_bru_bctq_io_enq_ready &
    exe_stage_bru_bctq_io_enq_valid;
  assign exe_stage_bru_bctq_ram_finalTarget_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_bctq_ram_finalTarget_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_finalTarget_io_deq_bits_MPORT_data =
    exe_stage_bru_bctq_ram_finalTarget[exe_stage_bru_bctq_ram_finalTarget_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_bctq_ram_finalTarget_MPORT_data = exe_stage_bru_bctq_io_enq_bits_finalTarget;
  assign exe_stage_bru_bctq_ram_finalTarget_MPORT_addr = 1'h0;
  assign exe_stage_bru_bctq_ram_finalTarget_MPORT_mask = 1'h1;
  assign exe_stage_bru_bctq_ram_finalTarget_MPORT_en = exe_stage_bru_bctq_io_enq_ready & exe_stage_bru_bctq_io_enq_valid
    ;
  assign exe_stage_bru_bctq_io_enq_ready = ~exe_stage_bru_bctq_maybe_full; // @[Decoupled.scala 305:19]
  assign exe_stage_bru_bctq_io_deq_valid = ~exe_stage_bru_bctq__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_bru_bctq_io_deq_bits_pc = exe_stage_bru_bctq_ram_pc_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_bctq_io_deq_bits_bimResp_bim_p = exe_stage_bru_bctq_ram_bimResp_bim_p_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_bctq_io_deq_bits_bimResp_bim_h = exe_stage_bru_bctq_ram_bimResp_bim_h_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_bctq_io_deq_bits_isPredictTaken = exe_stage_bru_bctq_ram_isPredictTaken_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_bctq_io_deq_bits_isFinalTaken = exe_stage_bru_bctq_ram_isFinalTaken_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_bctq_io_deq_bits_finalTarget = exe_stage_bru_bctq_ram_finalTarget_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_jctq_ram_pc_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_jctq_ram_pc_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_pc_io_deq_bits_MPORT_data =
    exe_stage_bru_jctq_ram_pc[exe_stage_bru_jctq_ram_pc_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_jctq_ram_pc_MPORT_data = exe_stage_bru_jctq_io_enq_bits_pc;
  assign exe_stage_bru_jctq_ram_pc_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_pc_MPORT_mask = 1'h1;
  assign exe_stage_bru_jctq_ram_pc_MPORT_en = exe_stage_bru_jctq_io_enq_ready & exe_stage_bru_jctq_io_enq_valid;
  assign exe_stage_bru_jctq_ram_btbResp_target_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_jctq_ram_btbResp_target_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_btbResp_target_io_deq_bits_MPORT_data =
    exe_stage_bru_jctq_ram_btbResp_target[exe_stage_bru_jctq_ram_btbResp_target_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_jctq_ram_btbResp_target_MPORT_data = exe_stage_bru_jctq_io_enq_bits_btbResp_target;
  assign exe_stage_bru_jctq_ram_btbResp_target_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_btbResp_target_MPORT_mask = 1'h1;
  assign exe_stage_bru_jctq_ram_btbResp_target_MPORT_en = exe_stage_bru_jctq_io_enq_ready &
    exe_stage_bru_jctq_io_enq_valid;
  assign exe_stage_bru_jctq_ram_rasResp_target_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_jctq_ram_rasResp_target_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_rasResp_target_io_deq_bits_MPORT_data =
    exe_stage_bru_jctq_ram_rasResp_target[exe_stage_bru_jctq_ram_rasResp_target_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_jctq_ram_rasResp_target_MPORT_data = exe_stage_bru_jctq_io_enq_bits_rasResp_target;
  assign exe_stage_bru_jctq_ram_rasResp_target_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_rasResp_target_MPORT_mask = 1'h1;
  assign exe_stage_bru_jctq_ram_rasResp_target_MPORT_en = exe_stage_bru_jctq_io_enq_ready &
    exe_stage_bru_jctq_io_enq_valid;
  assign exe_stage_bru_jctq_ram_isRas_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_jctq_ram_isRas_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_isRas_io_deq_bits_MPORT_data =
    exe_stage_bru_jctq_ram_isRas[exe_stage_bru_jctq_ram_isRas_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_jctq_ram_isRas_MPORT_data = exe_stage_bru_jctq_io_enq_bits_isRas;
  assign exe_stage_bru_jctq_ram_isRas_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_isRas_MPORT_mask = 1'h1;
  assign exe_stage_bru_jctq_ram_isRas_MPORT_en = exe_stage_bru_jctq_io_enq_ready & exe_stage_bru_jctq_io_enq_valid;
  assign exe_stage_bru_jctq_ram_finalTarget_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_bru_jctq_ram_finalTarget_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_finalTarget_io_deq_bits_MPORT_data =
    exe_stage_bru_jctq_ram_finalTarget[exe_stage_bru_jctq_ram_finalTarget_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_bru_jctq_ram_finalTarget_MPORT_data = exe_stage_bru_jctq_io_enq_bits_finalTarget;
  assign exe_stage_bru_jctq_ram_finalTarget_MPORT_addr = 1'h0;
  assign exe_stage_bru_jctq_ram_finalTarget_MPORT_mask = 1'h1;
  assign exe_stage_bru_jctq_ram_finalTarget_MPORT_en = exe_stage_bru_jctq_io_enq_ready & exe_stage_bru_jctq_io_enq_valid
    ;
  assign exe_stage_bru_jctq_io_enq_ready = ~exe_stage_bru_jctq_maybe_full; // @[Decoupled.scala 305:19]
  assign exe_stage_bru_jctq_io_deq_valid = ~exe_stage_bru_jctq__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_bru_jctq_io_deq_bits_pc = exe_stage_bru_jctq_ram_pc_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_jctq_io_deq_bits_btbResp_target = exe_stage_bru_jctq_ram_btbResp_target_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_jctq_io_deq_bits_rasResp_target = exe_stage_bru_jctq_ram_rasResp_target_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_jctq_io_deq_bits_isRas = exe_stage_bru_jctq_ram_isRas_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_jctq_io_deq_bits_finalTarget = exe_stage_bru_jctq_ram_finalTarget_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_bru_io_bru_iss_exe_ready = exe_stage_bru__io_bru_iss_exe_ready_T_1 &
    exe_stage_bru__io_bru_iss_exe_ready_T_2; // @[Bru.scala 110:97]
  assign exe_stage_bru_io_bru_exe_iwb_valid = exe_stage_bru_bru_exe_iwb_fifo_io_deq_valid; // @[Bru.scala 101:18]
  assign exe_stage_bru_io_bru_exe_iwb_bits_rd0 = exe_stage_bru_bru_exe_iwb_fifo_io_deq_bits_rd0; // @[Bru.scala 101:18]
  assign exe_stage_bru_io_bru_exe_iwb_bits_res = exe_stage_bru_bru_exe_iwb_fifo_io_deq_bits_res; // @[Bru.scala 101:18]
  assign exe_stage_bru_io_bftq_ready = exe_stage_bru__io_bftq_ready_T & exe_stage_bru__io_bftq_ready_T_5; // @[Bru.scala 112:40]
  assign exe_stage_bru_io_jftq_ready = exe_stage_bru__io_bftq_ready_T & exe_stage_bru_io_bru_iss_exe_bits_fun_jalr; // @[Bru.scala 113:40]
  assign exe_stage_bru_io_bctq_valid = exe_stage_bru_bctq_io_deq_valid; // @[Bru.scala 102:11]
  assign exe_stage_bru_io_bctq_bits_pc = exe_stage_bru_bctq_io_deq_bits_pc; // @[Bru.scala 102:11]
  assign exe_stage_bru_io_bctq_bits_bimResp_bim_p = exe_stage_bru_bctq_io_deq_bits_bimResp_bim_p; // @[Bru.scala 102:11]
  assign exe_stage_bru_io_bctq_bits_bimResp_bim_h = exe_stage_bru_bctq_io_deq_bits_bimResp_bim_h; // @[Bru.scala 102:11]
  assign exe_stage_bru_io_bctq_bits_isPredictTaken = exe_stage_bru_bctq_io_deq_bits_isPredictTaken; // @[Bru.scala 102:11]
  assign exe_stage_bru_io_bctq_bits_isFinalTaken = exe_stage_bru_bctq_io_deq_bits_isFinalTaken; // @[Bru.scala 102:11]
  assign exe_stage_bru_io_bctq_bits_finalTarget = exe_stage_bru_bctq_io_deq_bits_finalTarget; // @[Bru.scala 102:11]
  assign exe_stage_bru_io_jctq_valid = exe_stage_bru_jctq_io_deq_valid; // @[Bru.scala 103:11]
  assign exe_stage_bru_io_jctq_bits_pc = exe_stage_bru_jctq_io_deq_bits_pc; // @[Bru.scala 103:11]
  assign exe_stage_bru_io_jctq_bits_btbResp_target = exe_stage_bru_jctq_io_deq_bits_btbResp_target; // @[Bru.scala 103:11]
  assign exe_stage_bru_io_jctq_bits_rasResp_target = exe_stage_bru_jctq_io_deq_bits_rasResp_target; // @[Bru.scala 103:11]
  assign exe_stage_bru_io_jctq_bits_isRas = exe_stage_bru_jctq_io_deq_bits_isRas; // @[Bru.scala 103:11]
  assign exe_stage_bru_io_jctq_bits_finalTarget = exe_stage_bru_jctq_io_deq_bits_finalTarget; // @[Bru.scala 103:11]
  assign exe_stage_bru_io_bcmm_update_valid = exe_stage_bru_io_bctq_ready & exe_stage_bru_io_bctq_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_bru_io_bcmm_update_bits_pc = exe_stage_bru__io_bcmm_update_bits_T ? exe_stage_bru_io_bctq_bits_pc : 39'h0
    ; // @[Bru.scala 85:30]
  assign exe_stage_bru_io_bcmm_update_bits_bimResp_bim_p = exe_stage_bru__io_bcmm_update_bits_T &
    exe_stage_bru_io_bctq_bits_bimResp_bim_p; // @[Bru.scala 85:30]
  assign exe_stage_bru_io_bcmm_update_bits_bimResp_bim_h = exe_stage_bru__io_bcmm_update_bits_T &
    exe_stage_bru_io_bctq_bits_bimResp_bim_h; // @[Bru.scala 85:30]
  assign exe_stage_bru_io_bcmm_update_bits_isFinalTaken = exe_stage_bru__io_bcmm_update_bits_T &
    exe_stage_bru_io_bctq_bits_isFinalTaken; // @[Bru.scala 85:30]
  assign exe_stage_bru_io_jcmm_update_valid = exe_stage_bru_io_jctq_ready & exe_stage_bru_io_jctq_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_bru_io_jcmm_update_bits_pc = exe_stage_bru__io_jcmm_update_bits_T ? exe_stage_bru_io_jctq_bits_pc : 39'h0
    ; // @[Bru.scala 87:30]
  assign exe_stage_bru_io_jcmm_update_bits_finalTarget = exe_stage_bru__io_jcmm_update_bits_T ?
    exe_stage_bru_io_jctq_bits_finalTarget : 64'h0; // @[Bru.scala 87:30]
  assign exe_stage_bru_bru_exe_iwb_fifo_clock = exe_stage_bru_clock;
  assign exe_stage_bru_bru_exe_iwb_fifo_reset = exe_stage_bru_reset | exe_stage_bru_io_flush; // @[Bru.scala 105:42]
  assign exe_stage_bru_bru_exe_iwb_fifo_io_enq_valid = exe_stage_bru_io_bru_iss_exe_ready &
    exe_stage_bru_io_bru_iss_exe_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_bru_bru_exe_iwb_fifo_io_enq_bits_rd0 = exe_stage_bru_io_bru_iss_exe_bits_param_rd0; // @[Bru.scala 120:36]
  assign exe_stage_bru_bru_exe_iwb_fifo_io_enq_bits_res = exe_stage_bru_io_bru_iss_exe_bits_param_pc + _GEN_288; // @[Bru.scala 119:42]
  assign exe_stage_bru_bru_exe_iwb_fifo_io_deq_ready = exe_stage_bru_io_bru_exe_iwb_ready; // @[Bru.scala 101:18]
  assign exe_stage_bru_bctq_clock = exe_stage_bru_clock;
  assign exe_stage_bru_bctq_reset = exe_stage_bru_reset | exe_stage_bru_io_flush; // @[Bru.scala 106:30]
  assign exe_stage_bru_bctq_io_enq_valid = exe_stage_bru__io_bftq_ready_T & exe_stage_bru__io_bftq_ready_T_5; // @[Bru.scala 116:44]
  assign exe_stage_bru_bctq_io_enq_bits_pc = exe_stage_bru_io_bftq_bits_pc; // @[Bru.scala 70:63]
  assign exe_stage_bru_bctq_io_enq_bits_bimResp_bim_p = exe_stage_bru_io_bftq_bits_bimResp_bim_p; // @[Bru.scala 70:63]
  assign exe_stage_bru_bctq_io_enq_bits_bimResp_bim_h = exe_stage_bru_io_bftq_bits_bimResp_bim_h; // @[Bru.scala 70:63]
  assign exe_stage_bru_bctq_io_enq_bits_isPredictTaken = exe_stage_bru_io_bftq_bits_isPredictTaken; // @[Bru.scala 70:63]
  assign exe_stage_bru_bctq_io_enq_bits_isFinalTaken = exe_stage_bru__is_branchTaken_T_19 |
    exe_stage_bru__is_branchTaken_T_15; // @[Mux.scala 27:73]
  assign exe_stage_bru_bctq_io_enq_bits_finalTarget = exe_stage_bru__is_branchTaken_T_20 ?
    exe_stage_bru__bctq_io_enq_bits_finalTarget_T_1 : exe_stage_bru__bctq_io_enq_bits_finalTarget_T_4; // @[Bru.scala 72:39]
  assign exe_stage_bru_bctq_io_deq_ready = exe_stage_bru_io_bctq_ready; // @[Bru.scala 102:11]
  assign exe_stage_bru_jctq_clock = exe_stage_bru_clock;
  assign exe_stage_bru_jctq_reset = exe_stage_bru_reset | exe_stage_bru_io_flush; // @[Bru.scala 107:30]
  assign exe_stage_bru_jctq_io_enq_valid = exe_stage_bru__io_bftq_ready_T & exe_stage_bru_io_bru_iss_exe_bits_fun_jalr; // @[Bru.scala 117:44]
  assign exe_stage_bru_jctq_io_enq_bits_pc = exe_stage_bru_io_jftq_bits_pc; // @[Bru.scala 78:61]
  assign exe_stage_bru_jctq_io_enq_bits_btbResp_target = exe_stage_bru_io_jftq_bits_btbResp_target; // @[Bru.scala 78:61]
  assign exe_stage_bru_jctq_io_enq_bits_rasResp_target = exe_stage_bru_io_jftq_bits_rasResp_target; // @[Bru.scala 78:61]
  assign exe_stage_bru_jctq_io_enq_bits_isRas = exe_stage_bru_io_jftq_bits_isRas; // @[Bru.scala 78:61]
  assign exe_stage_bru_jctq_io_enq_bits_finalTarget = {exe_stage_bru__jctq_io_enq_bits_finalTarget_T_2, 1'h0}; // @[Bru.scala 79:52]
  assign exe_stage_bru_jctq_io_deq_ready = exe_stage_bru_io_jctq_ready; // @[Bru.scala 103:11]
  assign exe_stage_lsu_stQueue_io_enq_ready = ~exe_stage_lsu_stQueue_full; // @[Store_queue.scala 89:19]
  assign exe_stage_lsu_stQueue_io_deq_valid = ~exe_stage_lsu_stQueue_emty; // @[Store_queue.scala 90:19]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_lb = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_47; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_lh = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_48; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_lw = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_49; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_ld = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_50; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_lbu = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_51; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_lhu = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_52; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_lwu = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_53; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_sb = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_54; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_sh = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_55; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_sw = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_56; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_sd = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_57; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_lr_w = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_61
    ; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_sc_w = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_62
    ; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoswap_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_63; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoadd_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_64; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoxor_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_65; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoand_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_66; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoor_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_67; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amomin_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_68; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amomax_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_69; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amominu_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_70; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amomaxu_w = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_71; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_lr_d = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_72
    ; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_sc_d = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_73
    ; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoswap_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_74; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoadd_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_75; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoxor_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_76; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoand_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_77; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amoor_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_78; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amomin_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_79; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amomax_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_80; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amominu_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_81; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_amomaxu_d = exe_stage_lsu_stQueue_io_deq_valid &
    exe_stage_lsu_stQueue__GEN_82; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_flw = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_83; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_fsw = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_84; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_fld = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_85; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_fun_fsd = exe_stage_lsu_stQueue_io_deq_valid & exe_stage_lsu_stQueue__GEN_86; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_param_rd0 = exe_stage_lsu_stQueue_io_deq_valid ?
    exe_stage_lsu_stQueue__GEN_87 : 6'h0; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_param_dat_op1 = exe_stage_lsu_stQueue_io_deq_valid ?
    exe_stage_lsu_stQueue__GEN_88 : 64'h0; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_deq_bits_param_dat_op2 = exe_stage_lsu_stQueue_io_deq_valid ?
    exe_stage_lsu_stQueue__GEN_89 : 64'h0; // @[Store_queue.scala 92:21]
  assign exe_stage_lsu_stQueue_io_is_empty = exe_stage_lsu_stQueue__io_is_empty_T & exe_stage_lsu_stQueue_emty; // @[Store_queue.scala 141:48]
  assign exe_stage_lsu_stQueue_io_overlapResp_valid = exe_stage_lsu_stQueue__T_30 ? exe_stage_lsu_stQueue__GEN_804 :
    exe_stage_lsu_stQueue__GEN_1072; // @[Store_queue.scala 148:51]
  assign exe_stage_lsu_stQueue_io_overlapResp_bits_wdata = exe_stage_lsu_stQueue__new_data_T_4 |
    exe_stage_lsu_stQueue__new_data_T_5; // @[Util.scala 108:35]
  assign exe_stage_lsu_stQueue_io_overlapResp_bits_wstrb = exe_stage_lsu_stQueue_wstrb | exe_stage_lsu_stQueue_wstrb_2; // @[Util.scala 109:30]
  assign exe_stage_lsu_ls_arb_io_in_0_ready = exe_stage_lsu_ls_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_ls_arb_io_in_1_ready = exe_stage_lsu_ls_arb_grant_1 & exe_stage_lsu_ls_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_ls_arb_io_out_valid = exe_stage_lsu_ls_arb__io_out_valid_T | exe_stage_lsu_ls_arb_io_in_1_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_lb = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_lb : exe_stage_lsu_ls_arb_io_in_1_bits_fun_lb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_lh = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_lh : exe_stage_lsu_ls_arb_io_in_1_bits_fun_lh; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_lw = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_lw : exe_stage_lsu_ls_arb_io_in_1_bits_fun_lw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_ld = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_ld : exe_stage_lsu_ls_arb_io_in_1_bits_fun_ld; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_lbu = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_lbu : exe_stage_lsu_ls_arb_io_in_1_bits_fun_lbu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_lhu = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_lhu : exe_stage_lsu_ls_arb_io_in_1_bits_fun_lhu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_lwu = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_lwu : exe_stage_lsu_ls_arb_io_in_1_bits_fun_lwu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_sb = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_sb : exe_stage_lsu_ls_arb_io_in_1_bits_fun_sb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_sh = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_sh : exe_stage_lsu_ls_arb_io_in_1_bits_fun_sh; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_sw = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_sw : exe_stage_lsu_ls_arb_io_in_1_bits_fun_sw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_sd = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_sd : exe_stage_lsu_ls_arb_io_in_1_bits_fun_sd; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_lr_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_lr_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_lr_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_sc_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_sc_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_sc_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoswap_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoswap_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoadd_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoadd_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoxor_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoxor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoand_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoand_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoor_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomin_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomin_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomax_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomax_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amominu_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amominu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_w = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomaxu_w : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomaxu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_lr_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_lr_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_lr_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_sc_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_sc_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_sc_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoswap_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoswap_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoadd_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoadd_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoxor_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoxor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoand_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoand_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoor_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomin_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomin_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomax_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomax_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amominu_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amominu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_d = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomaxu_d : exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomaxu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_flw = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_flw : exe_stage_lsu_ls_arb_io_in_1_bits_fun_flw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_fsw = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_fsw : exe_stage_lsu_ls_arb_io_in_1_bits_fun_fsw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_fld = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_fld : exe_stage_lsu_ls_arb_io_in_1_bits_fun_fld; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_fun_fsd = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_fun_fsd : exe_stage_lsu_ls_arb_io_in_1_bits_fun_fsd; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_param_rd0 = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_param_rd0 : exe_stage_lsu_ls_arb_io_in_1_bits_param_rd0; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_param_dat_op1 = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_param_dat_op1 : exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op1; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_ls_arb_io_out_bits_param_dat_op2 = exe_stage_lsu_ls_arb_io_in_0_valid ?
    exe_stage_lsu_ls_arb_io_in_0_bits_param_dat_op2 : exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op2; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_system_io_enq_ready = ~exe_stage_lsu_system_is_busy; // @[IO_Lsu.scala 53:19]
  assign exe_stage_lsu_system_io_deq_valid = exe_stage_lsu_system_io_access_valid; // @[IO_Lsu.scala 102:19]
  assign exe_stage_lsu_system_io_deq_bits_wb_rd0 = exe_stage_lsu_system_pending_param_rd0; // @[IO_Lsu.scala 104:22]
  assign exe_stage_lsu_system_io_deq_bits_wb_res = exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_62 |
    exe_stage_lsu_system__io_deq_bits_wb_res_res_pre_res_T_60; // @[Mux.scala 27:73]
  assign exe_stage_lsu_system_io_deq_bits_is_load_amo = exe_stage_lsu_system_io_access_bits_opcode == 3'h1; // @[IO_Lsu.scala 121:53]
  assign exe_stage_lsu_system_io_deq_bits_is_flw = exe_stage_lsu_system_io_deq_valid &
    exe_stage_lsu_system_pending_fun_flw; // @[IO_Lsu.scala 125:28]
  assign exe_stage_lsu_system_io_deq_bits_is_fld = exe_stage_lsu_system_io_deq_valid &
    exe_stage_lsu_system_pending_fun_fld; // @[IO_Lsu.scala 126:28]
  assign exe_stage_lsu_system_io_is_empty = ~exe_stage_lsu_system_is_busy; // @[IO_Lsu.scala 49:18]
  assign exe_stage_lsu_system_io_getPut_valid = exe_stage_lsu_system_is_busy & exe_stage_lsu_system__io_getPut_valid_T; // @[IO_Lsu.scala 51:30]
  assign exe_stage_lsu_system_io_getPut_bits_opcode = exe_stage_lsu_system__T_12 ? 3'h4 : 3'h1; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_system_io_getPut_bits_param = 3'h0; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_system_io_getPut_bits_size = 2'h3; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_system_io_getPut_bits_source = 1'h0; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_system_io_getPut_bits_address = exe_stage_lsu_system__T_12 ?
    exe_stage_lsu_system_io_getPut_bits_a_1_address : exe_stage_lsu_system_io_getPut_bits_a_1_address; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_system_io_getPut_bits_mask = exe_stage_lsu_system__T_12 ? 8'hff :
    exe_stage_lsu_system_io_getPut_bits_wstrb; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_system_io_getPut_bits_data = exe_stage_lsu_system__T_12 ? 64'h0 :
    exe_stage_lsu_system_io_getPut_bits_res; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_system_io_getPut_bits_corrupt = 1'h0; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_system_io_access_ready = exe_stage_lsu_system_io_deq_ready; // @[IO_Lsu.scala 129:19]
  assign exe_stage_lsu_periph_io_enq_ready = ~exe_stage_lsu_periph_is_busy; // @[IO_Lsu.scala 53:19]
  assign exe_stage_lsu_periph_io_deq_valid = exe_stage_lsu_periph_io_access_valid; // @[IO_Lsu.scala 102:19]
  assign exe_stage_lsu_periph_io_deq_bits_wb_rd0 = exe_stage_lsu_periph_pending_param_rd0; // @[IO_Lsu.scala 104:22]
  assign exe_stage_lsu_periph_io_deq_bits_wb_res = exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_62 |
    exe_stage_lsu_periph__io_deq_bits_wb_res_res_pre_res_T_60; // @[Mux.scala 27:73]
  assign exe_stage_lsu_periph_io_deq_bits_is_load_amo = exe_stage_lsu_periph_io_access_bits_opcode == 3'h1; // @[IO_Lsu.scala 121:53]
  assign exe_stage_lsu_periph_io_deq_bits_is_flw = exe_stage_lsu_periph_io_deq_valid &
    exe_stage_lsu_periph_pending_fun_flw; // @[IO_Lsu.scala 125:28]
  assign exe_stage_lsu_periph_io_deq_bits_is_fld = exe_stage_lsu_periph_io_deq_valid &
    exe_stage_lsu_periph_pending_fun_fld; // @[IO_Lsu.scala 126:28]
  assign exe_stage_lsu_periph_io_is_empty = ~exe_stage_lsu_periph_is_busy; // @[IO_Lsu.scala 49:18]
  assign exe_stage_lsu_periph_io_getPut_valid = exe_stage_lsu_periph_is_busy & exe_stage_lsu_periph__io_getPut_valid_T; // @[IO_Lsu.scala 51:30]
  assign exe_stage_lsu_periph_io_getPut_bits_opcode = exe_stage_lsu_periph__T_12 ? 3'h4 : 3'h1; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_periph_io_getPut_bits_param = 3'h0; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_periph_io_getPut_bits_size = 2'h3; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_periph_io_getPut_bits_source = 1'h0; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_periph_io_getPut_bits_address = exe_stage_lsu_periph__T_12 ?
    exe_stage_lsu_periph_io_getPut_bits_a_1_address : exe_stage_lsu_periph_io_getPut_bits_a_1_address; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_periph_io_getPut_bits_mask = exe_stage_lsu_periph__T_12 ? 8'hff :
    exe_stage_lsu_periph_io_getPut_bits_wstrb; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_periph_io_getPut_bits_data = exe_stage_lsu_periph__T_12 ? 64'h0 :
    exe_stage_lsu_periph_io_getPut_bits_res; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_periph_io_getPut_bits_corrupt = 1'h0; // @[IO_Lsu.scala 55:51 56:24]
  assign exe_stage_lsu_periph_io_access_ready = exe_stage_lsu_periph_io_deq_ready; // @[IO_Lsu.scala 129:19]
  assign exe_stage_lsu_cache_0_missUnit_io_rsp_valid = exe_stage_lsu_cache_0_missUnit_rsp_valid; // @[MissUnit.scala 99:16]
  assign exe_stage_lsu_cache_0_missUnit_io_rsp_bits_paddr = exe_stage_lsu_cache_0_missUnit_acquire_sel ?
    exe_stage_lsu_cache_0_missUnit_miss_queue_1_paddr : exe_stage_lsu_cache_0_missUnit_miss_queue_0_paddr; // @[MissUnit.scala 130:{49,49}]
  assign exe_stage_lsu_cache_0_missUnit_io_rsp_bits_wdata = {exe_stage_lsu_cache_0_missUnit_miss_rsp_1,
    exe_stage_lsu_cache_0_missUnit_miss_rsp_0}; // @[Cat.scala 33:92]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_valid = exe_stage_lsu_cache_0_missUnit_cache_acquire_vaild; // @[MissUnit.scala 95:26]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_opcode = 3'h6; // @[Edges.scala 345:17 346:15]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_param = 3'h1; // @[Edges.scala 345:17 347:15]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_size = 3'h4; // @[Edges.scala 345:17 348:15]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_source = 1'h0; // @[Edges.scala 345:17 349:15]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_address =
    exe_stage_lsu_cache_0_missUnit__io_cache_acquire_bits_T_1[31:0]; // @[Edges.scala 345:17 350:15]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_mask = 8'hff; // @[Cat.scala 33:92]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_data = 64'h0; // @[Edges.scala 345:17 352:15]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_corrupt = 1'h0; // @[Edges.scala 345:17 353:15]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grant_ready = exe_stage_lsu_cache_0_missUnit_mshr_state_qout == 3'h2; // @[MissUnit.scala 139:41]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_valid = exe_stage_lsu_cache_0_missUnit_cache_grantAck_valid; // @[MissUnit.scala 97:27]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_bits_sink =
    exe_stage_lsu_cache_0_missUnit_cache_grant_reg_sink; // @[Edges.scala 438:17 439:12]
  assign exe_stage_lsu_cache_0_missUnit_io_release_ban = exe_stage_lsu_cache_0_missUnit__io_release_ban_T |
    exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_11; // @[MissUnit.scala 161:45]
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram[exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_data =
    exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_bits;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_en =
    exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_ready & exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_ready = ~
    exe_stage_lsu_cache_0_probeUnit_probe_fifo_maybe_full; // @[Decoupled.scala 305:19]
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_valid = ~exe_stage_lsu_cache_0_probeUnit_probe_fifo__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_bits =
    exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_probeUnit_io_cache_probe_ready = exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_ready; // @[ProbeUnit.scala 52:24]
  assign exe_stage_lsu_cache_0_probeUnit_io_req_valid = exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_valid &
    exe_stage_lsu_cache_0_probeUnit__io_req_valid_T; // @[ProbeUnit.scala 54:43]
  assign exe_stage_lsu_cache_0_probeUnit_io_req_bits_paddr = exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_bits; // @[ProbeUnit.scala 56:21]
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_clock = exe_stage_lsu_cache_0_probeUnit_clock;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_reset = exe_stage_lsu_cache_0_probeUnit_reset;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_valid = exe_stage_lsu_cache_0_probeUnit_io_cache_probe_valid; // @[ProbeUnit.scala 50:27]
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_enq_bits =
    exe_stage_lsu_cache_0_probeUnit_io_cache_probe_bits_address; // @[ProbeUnit.scala 51:26]
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_io_deq_ready = exe_stage_lsu_cache_0_probeUnit_io_req_ready &
    exe_stage_lsu_cache_0_probeUnit__io_req_valid_T; // @[ProbeUnit.scala 55:43]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_paddr;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_en =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_17 :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_data;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_en =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_17 :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_releaseData;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_en =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_17 :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_release;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_en =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_17 :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_probe;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_en =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_17 :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_probeData;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_addr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_en =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_17 :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_ready = ~exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_full; // @[Decoupled.scala 305:19]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_valid =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_valid |
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_paddr =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_paddr :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_data =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_data :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_releaseData =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ?
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_releaseData :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_release =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ?
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_release :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probe =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ? exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_probe
     : exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_bits_is_probeData =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty ?
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_probeData :
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_valid =
    exe_stage_lsu_cache_0_writeBackUnit_cache_release_valid; // @[wrtieBackUnit.scala 81:26]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_opcode =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_47 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_45; // @[Mux.scala 27:73]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_param =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_40 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_38; // @[Mux.scala 27:73]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_size =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_33 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_31; // @[Mux.scala 27:73]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_source = 1'h0; // @[Mux.scala 27:73]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_address =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_19 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_17; // @[Mux.scala 27:73]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_data =
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_8 |
    exe_stage_lsu_cache_0_writeBackUnit__io_cache_release_bits_T_10; // @[Mux.scala 27:73]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_corrupt = 1'h0; // @[Mux.scala 27:73]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_ready =
    exe_stage_lsu_cache_0_writeBackUnit_cache_grant_ready; // @[wrtieBackUnit.scala 82:26]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_miss_ban = exe_stage_lsu_cache_0_writeBackUnit__io_miss_ban_T_2 |
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_valid; // @[wrtieBackUnit.scala 171:64]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock = exe_stage_lsu_cache_0_writeBackUnit_clock;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_reset = exe_stage_lsu_cache_0_writeBackUnit_reset;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_valid = exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_valid; // @[wrtieBackUnit.scala 63:24]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_paddr =
    exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_paddr; // @[wrtieBackUnit.scala 64:24]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_data =
    exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_data; // @[wrtieBackUnit.scala 64:24]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_releaseData =
    exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_releaseData; // @[wrtieBackUnit.scala 64:24]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_release =
    exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_release; // @[wrtieBackUnit.scala 64:24]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_probe =
    exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_probe; // @[wrtieBackUnit.scala 64:24]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_enq_bits_is_probeData =
    exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_probeData; // @[wrtieBackUnit.scala 64:24]
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_ready =
    exe_stage_lsu_cache_0_writeBackUnit__wb_fifo_io_deq_ready_T &
    exe_stage_lsu_cache_0_writeBackUnit__wb_fifo_io_deq_ready_T_1; // @[wrtieBackUnit.scala 169:27]
  assign exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_chkIdx[exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_chkIdx;
  assign exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_paddr_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_paddr_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_paddr_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_paddr[exe_stage_lsu_cache_0_lsEntry_ram_paddr_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_paddr;
  assign exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wdata_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wdata_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wdata_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_wdata[exe_stage_lsu_cache_0_lsEntry_ram_wdata_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_wdata;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wstrb_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wstrb_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wstrb_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_wstrb[exe_stage_lsu_cache_0_lsEntry_ram_wstrb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_wstrb;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lb[exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lb;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lh[exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lh;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lw[exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lw;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_ld[exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_ld;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu[exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lbu;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu[exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lhu;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu[exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lwu;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sb[exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sb;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sh[exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sh;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sw[exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sw;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sd[exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sd;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lr_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sc_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoswap_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoadd_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoxor_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoand_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoor_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomin_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomax_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amominu_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomaxu_w;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lr_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sc_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoswap_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoadd_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoxor_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoand_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoor_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomin_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomax_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amominu_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomaxu_d;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_flw[exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_flw;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw[exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fsw;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_fld[exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fld;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd[exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fsd;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_probe[exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_probe;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_grant[exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_grant;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_fun_preft[exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_preft;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_deq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0[exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_data = exe_stage_lsu_cache_0_lsEntry_io_enq_bits_rd_rd0;
  assign exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_addr = exe_stage_lsu_cache_0_lsEntry_enq_ptr_value;
  assign exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_en = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry__GEN_59 : exe_stage_lsu_cache_0_lsEntry__do_enq_T;
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_ready = ~exe_stage_lsu_cache_0_lsEntry_full; // @[Decoupled.scala 305:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_valid = exe_stage_lsu_cache_0_lsEntry_io_enq_valid |
    exe_stage_lsu_cache_0_lsEntry__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_chkIdx = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_chkIdx : exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_paddr = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_paddr : exe_stage_lsu_cache_0_lsEntry_ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_wdata = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_wdata : exe_stage_lsu_cache_0_lsEntry_ram_wdata_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_wstrb = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_wstrb : exe_stage_lsu_cache_0_lsEntry_ram_wstrb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lb = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lb : exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lh = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lh : exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lw = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lw : exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_ld = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_ld : exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lbu = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lbu : exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lhu = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lhu : exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lwu = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lwu : exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sb = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sb : exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sh = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sh : exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sw = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sw : exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sd = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sd : exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lr_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lr_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sc_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sc_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoswap_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoswap_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoadd_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoadd_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoxor_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoxor_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoand_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoand_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoor_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoor_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomin_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomin_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomax_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomax_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amominu_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amominu_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomaxu_w = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomaxu_w :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lr_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lr_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sc_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sc_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoswap_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoswap_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoadd_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoadd_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoxor_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoxor_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoand_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoand_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoor_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoor_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomin_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomin_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomax_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomax_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amominu_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amominu_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomaxu_d = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomaxu_d :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_flw = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_flw : exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fsw = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fsw : exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fld = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fld : exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fsd = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fsd : exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_probe = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_probe :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_grant = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_grant :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_preft = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_preft :
    exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_bits_rd_rd0 = exe_stage_lsu_cache_0_lsEntry_empty ?
    exe_stage_lsu_cache_0_lsEntry_io_enq_bits_rd_rd0 : exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx[exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_data = exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_chkIdx;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_en = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo__GEN_17 : exe_stage_lsu_cache_0_rtn_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0[exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_data = exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_wb_rd0;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_en = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo__GEN_17 : exe_stage_lsu_cache_0_rtn_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res[exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_data = exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_wb_res;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_en = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo__GEN_17 : exe_stage_lsu_cache_0_rtn_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_io_deq_bits_MPORT_addr =
    exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo[exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_data =
    exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_load_amo;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_en = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo__GEN_17 : exe_stage_lsu_cache_0_rtn_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw[exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_data = exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_flw;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_en = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo__GEN_17 : exe_stage_lsu_cache_0_rtn_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_io_deq_bits_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value
    ;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld[exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_data = exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_fld;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_addr = exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_en = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo__GEN_17 : exe_stage_lsu_cache_0_rtn_fifo__do_enq_T;
  assign exe_stage_lsu_cache_0_rtn_fifo_io_enq_ready = ~exe_stage_lsu_cache_0_rtn_fifo_full; // @[Decoupled.scala 305:19]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_deq_valid = exe_stage_lsu_cache_0_rtn_fifo_io_enq_valid |
    exe_stage_lsu_cache_0_rtn_fifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_chkIdx = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_chkIdx : exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_wb_rd0 = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_wb_rd0 : exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_wb_res = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_wb_res : exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_load_amo = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_load_amo :
    exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_flw = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_flw : exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_fld = exe_stage_lsu_cache_0_rtn_fifo_empty ?
    exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_fld : exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_io_deq_bits_MPORT_data
    ; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_ready = exe_stage_lsu_cache_0_op_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_ready = exe_stage_lsu_cache_0_op_arb_grant_1 &
    exe_stage_lsu_cache_0_op_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_valid = exe_stage_lsu_cache_0_op_arb__io_out_valid_T |
    exe_stage_lsu_cache_0_op_arb_io_in_1_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_chkIdx = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_chkIdx : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_chkIdx; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_paddr = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_paddr : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_paddr; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_wdata = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_wdata : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_wdata; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_wstrb = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_wstrb : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_wstrb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lb = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lb : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lh = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lh : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lh; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lw = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lw : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_ld = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_ld : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_ld; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lbu = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lbu : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lbu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lhu = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lhu : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lhu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lwu = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lwu : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lwu; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sb = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sb : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sb; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sh = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sh : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sh; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sw = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sw : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sd = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sd : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sd; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lr_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lr_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lr_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sc_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sc_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sc_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoswap_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoswap_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoswap_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoadd_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoadd_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoadd_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoxor_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoxor_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoxor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoand_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoand_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoand_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoor_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoor_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoor_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomin_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomin_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomin_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomax_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomax_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomax_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amominu_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amominu_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amominu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomaxu_w = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomaxu_w : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomaxu_w; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lr_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lr_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lr_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sc_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sc_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sc_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoswap_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoswap_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoswap_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoadd_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoadd_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoadd_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoxor_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoxor_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoxor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoand_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoand_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoand_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoor_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoor_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoor_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomin_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomin_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomin_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomax_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomax_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomax_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amominu_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amominu_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amominu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomaxu_d = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomaxu_d : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomaxu_d; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_flw = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_flw : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_flw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fsw = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fsw : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fsw; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fld = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fld : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fld; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fsd = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fsd : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fsd; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_probe = exe_stage_lsu_cache_0_op_arb_io_in_0_valid &
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_probe; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_grant = exe_stage_lsu_cache_0_op_arb_io_in_0_valid &
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_grant; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_preft = exe_stage_lsu_cache_0_op_arb_io_in_0_valid &
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_preft; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_op_arb_io_out_bits_rd_rd0 = exe_stage_lsu_cache_0_op_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_op_arb_io_in_0_bits_rd_rd0 : exe_stage_lsu_cache_0_op_arb_io_in_1_bits_rd_rd0; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_0_ready = exe_stage_lsu_cache_0_rd_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_1_ready = exe_stage_lsu_cache_0_rd_arb_grant_1 &
    exe_stage_lsu_cache_0_rd_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_ready = exe_stage_lsu_cache_0_rd_arb_grant_2 &
    exe_stage_lsu_cache_0_rd_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_valid = exe_stage_lsu_cache_0_rd_arb__io_out_valid_T |
    exe_stage_lsu_cache_0_rd_arb_io_in_2_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_chkIdx = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_1; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_paddr = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_rd_arb_io_in_0_bits_paddr : exe_stage_lsu_cache_0_rd_arb__GEN_2; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_wdata = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_rd_arb_io_in_0_bits_wdata : exe_stage_lsu_cache_0_rd_arb__GEN_3; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_wstrb = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 16'hffff :
    exe_stage_lsu_cache_0_rd_arb__GEN_4; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lb = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_5; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lh = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_6; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lw = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_7; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_ld = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_8; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lbu = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_9; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lhu = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_10; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lwu = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_11; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sb = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_12; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sh = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_13; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sw = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_14; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sd = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_15; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lr_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_19; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sc_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_20; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoswap_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_21; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoadd_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_22; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoxor_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_23; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoand_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_24; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoor_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_25; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomin_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_26; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomax_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_27; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amominu_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_28; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomaxu_w = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_29; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lr_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_30; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sc_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_31; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoswap_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_32; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoadd_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_33; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoxor_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_34; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoand_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_35; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoor_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_36; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomin_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_37; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomax_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_38; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amominu_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_39; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomaxu_d = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_40; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_flw = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_41; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fsw = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_42; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fld = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_43; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fsd = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_44; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_probe = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_45; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_grant = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid |
    exe_stage_lsu_cache_0_rd_arb__GEN_46; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_preft = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 1'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_47; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_bits_rd_rd0 = exe_stage_lsu_cache_0_rd_arb_io_in_0_valid ? 6'h0 :
    exe_stage_lsu_cache_0_rd_arb__GEN_48; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx[exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_chkIdx;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_paddr_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_paddr_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_paddr_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_paddr[exe_stage_lsu_cache_0_reload_fifo_ram_paddr_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_paddr;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wdata_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wdata_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wdata_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_wdata[exe_stage_lsu_cache_0_reload_fifo_ram_wdata_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_wdata;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_wstrb[exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_wstrb;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lb;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lh;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lw;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld[exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_ld;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lbu;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lhu;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lwu;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sb;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sh;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sw;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sd;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lr_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sc_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoswap_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready
     & exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoadd_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoxor_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoand_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoor_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomin_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomax_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amominu_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready
     & exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomaxu_w;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready
     & exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lr_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sc_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoswap_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready
     & exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoadd_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoxor_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoand_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoor_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomin_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomax_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amominu_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready
     & exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomaxu_d;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready
     & exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw[exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_flw;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw[exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fsw;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld[exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fld;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd[exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fsd;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe[exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_probe;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant[exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_grant;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft[exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_io_deq_bits_MPORT_addr]
    ; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_preft;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_io_deq_bits_MPORT_data =
    exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0[exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_data = exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_rd_rd0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_addr = 1'h0;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_en = exe_stage_lsu_cache_0_reload_fifo_io_enq_ready &
    exe_stage_lsu_cache_0_reload_fifo_io_enq_valid;
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_ready = exe_stage_lsu_cache_0_reload_fifo_io_deq_ready |
    exe_stage_lsu_cache_0_reload_fifo__empty_T; // @[Decoupled.scala 305:16 325:{24,39}]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_valid = ~exe_stage_lsu_cache_0_reload_fifo__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_chkIdx =
    exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_paddr =
    exe_stage_lsu_cache_0_reload_fifo_ram_paddr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_wdata =
    exe_stage_lsu_cache_0_reload_fifo_ram_wdata_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_wstrb =
    exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lb =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lh =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lw =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_ld =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lbu =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lhu =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lwu =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sb =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sh =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sw =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sd =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lr_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sc_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoswap_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoadd_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoxor_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoand_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoor_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomin_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomax_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amominu_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomaxu_w =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lr_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sc_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoswap_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoadd_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoxor_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoand_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoor_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomin_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomax_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amominu_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomaxu_d =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_flw =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fsw =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fld =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fsd =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_probe =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_grant =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_preft =
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_rd_rd0 =
    exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_1;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_1;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_2;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_2;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_3;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_3;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_4;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_4;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_5;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_5;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_6;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_6;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_7;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_7;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_8;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_8;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_9;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_9;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_10;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_10
    ;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_11;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_11
    ;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_12;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_12
    ;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_13;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_13
    ;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_14;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_14
    ;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_en =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_addr =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_data =
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_addr]; // @[CacheRAM.scala 46:27]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_data = exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_15;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_addr = exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_mask = exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_15
    ;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_en = exe_stage_lsu_cache_0_stage_datRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_0 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_1 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_2 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_3 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_4 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_5 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_6 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_7 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_8 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_9 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_10 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_11 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_12 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_13 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_14 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datar_15 = exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_data; // @[CacheRAM.scala 48:18 49:14]
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_en =
    exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_en_pipe_0;
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_addr =
    exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_addr_pipe_0;
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_data =
    exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem[exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_addr]; // @[CacheRAM.scala 152:27]
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_data = exe_stage_lsu_cache_0_stage_tagRAM_0_io_dataw;
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_addr = exe_stage_lsu_cache_0_stage_tagRAM_0_io_addrw;
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_mask = 1'h1;
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_en = exe_stage_lsu_cache_0_stage_tagRAM_0_io_enw;
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_io_datar = exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_data
    ; // @[CacheRAM.scala 164:18 165:14]
  assign exe_stage_lsu_cache_0_stage_io_enq_ready = 1'h1; // @[DcacheStage.scala 70:16]
  assign exe_stage_lsu_cache_0_stage_io_reload_valid = exe_stage_lsu_cache_0_stage_reloadValid; // @[DcacheStage.scala 359:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_chkIdx = exe_stage_lsu_cache_0_stage_reloadBits_chkIdx; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_paddr = exe_stage_lsu_cache_0_stage_reloadBits_paddr; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_wdata = exe_stage_lsu_cache_0_stage_reloadBits_wdata; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_wstrb = exe_stage_lsu_cache_0_stage_reloadBits_wstrb; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lb = exe_stage_lsu_cache_0_stage_reloadBits_fun_lb; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lh = exe_stage_lsu_cache_0_stage_reloadBits_fun_lh; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lw = exe_stage_lsu_cache_0_stage_reloadBits_fun_lw; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_ld = exe_stage_lsu_cache_0_stage_reloadBits_fun_ld; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lbu = exe_stage_lsu_cache_0_stage_reloadBits_fun_lbu; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lhu = exe_stage_lsu_cache_0_stage_reloadBits_fun_lhu; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lwu = exe_stage_lsu_cache_0_stage_reloadBits_fun_lwu; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sb = exe_stage_lsu_cache_0_stage_reloadBits_fun_sb; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sh = exe_stage_lsu_cache_0_stage_reloadBits_fun_sh; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sw = exe_stage_lsu_cache_0_stage_reloadBits_fun_sw; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sd = exe_stage_lsu_cache_0_stage_reloadBits_fun_sd; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lr_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_lr_w; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sc_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_sc_w; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoswap_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoswap_w
    ; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoadd_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoadd_w; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoxor_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoxor_w; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoand_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoand_w; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoor_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoor_w; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomin_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amomin_w; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomax_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amomax_w; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amominu_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amominu_w
    ; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomaxu_w = exe_stage_lsu_cache_0_stage_reloadBits_fun_amomaxu_w
    ; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lr_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_lr_d; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sc_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_sc_d; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoswap_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoswap_d
    ; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoadd_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoadd_d; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoxor_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoxor_d; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoand_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoand_d; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoor_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amoor_d; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomin_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amomin_d; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomax_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amomax_d; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amominu_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amominu_d
    ; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomaxu_d = exe_stage_lsu_cache_0_stage_reloadBits_fun_amomaxu_d
    ; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_flw = exe_stage_lsu_cache_0_stage_reloadBits_fun_flw; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fsw = exe_stage_lsu_cache_0_stage_reloadBits_fun_fsw; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fld = exe_stage_lsu_cache_0_stage_reloadBits_fun_fld; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fsd = exe_stage_lsu_cache_0_stage_reloadBits_fun_fsd; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_probe = exe_stage_lsu_cache_0_stage_reloadBits_fun_probe; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_grant = exe_stage_lsu_cache_0_stage_reloadBits_fun_grant; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_fun_preft = exe_stage_lsu_cache_0_stage_reloadBits_fun_preft; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_reload_bits_rd_rd0 = exe_stage_lsu_cache_0_stage_reloadBits_rd_rd0; // @[DcacheStage.scala 360:19]
  assign exe_stage_lsu_cache_0_stage_io_deq_valid = exe_stage_lsu_cache_0_stage_deqValid; // @[DcacheStage.scala 365:16]
  assign exe_stage_lsu_cache_0_stage_io_deq_bits_chkIdx = exe_stage_lsu_cache_0_stage_deqBits_chkIdx; // @[DcacheStage.scala 366:16]
  assign exe_stage_lsu_cache_0_stage_io_deq_bits_wb_rd0 = exe_stage_lsu_cache_0_stage_deqBits_wb_rd0; // @[DcacheStage.scala 366:16]
  assign exe_stage_lsu_cache_0_stage_io_deq_bits_wb_res = exe_stage_lsu_cache_0_stage_deqBits_wb_res; // @[DcacheStage.scala 366:16]
  assign exe_stage_lsu_cache_0_stage_io_deq_bits_is_load_amo = exe_stage_lsu_cache_0_stage_deqBits_is_load_amo; // @[DcacheStage.scala 366:16]
  assign exe_stage_lsu_cache_0_stage_io_deq_bits_is_flw = exe_stage_lsu_cache_0_stage_deqBits_is_flw; // @[DcacheStage.scala 366:16]
  assign exe_stage_lsu_cache_0_stage_io_deq_bits_is_fld = exe_stage_lsu_cache_0_stage_deqBits_is_fld; // @[DcacheStage.scala 366:16]
  assign exe_stage_lsu_cache_0_stage_io_missUnit_req_valid = exe_stage_lsu_cache_0_stage_missUnitReqValid; // @[DcacheStage.scala 294:25]
  assign exe_stage_lsu_cache_0_stage_io_missUnit_req_bits_paddr = exe_stage_lsu_cache_0_stage_missUnitReqPaddr; // @[DcacheStage.scala 295:30]
  assign exe_stage_lsu_cache_0_stage_io_wb_req_valid = exe_stage_lsu_cache_0_stage_wbReqValid; // @[DcacheStage.scala 313:19]
  assign exe_stage_lsu_cache_0_stage_io_wb_req_bits_paddr = exe_stage_lsu_cache_0_stage_wbReqPaddr; // @[DcacheStage.scala 314:24]
  assign exe_stage_lsu_cache_0_stage_io_wb_req_bits_data = exe_stage_lsu_cache_0_stage_wbReqData; // @[DcacheStage.scala 315:23]
  assign exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_releaseData = exe_stage_lsu_cache_0_stage_wbReqisData &
    exe_stage_lsu_cache_0_stage__io_wb_req_bits_is_releaseData_T; // @[DcacheStage.scala 317:49]
  assign exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_release =
    exe_stage_lsu_cache_0_stage__io_wb_req_bits_is_release_T &
    exe_stage_lsu_cache_0_stage__io_wb_req_bits_is_releaseData_T; // @[DcacheStage.scala 318:49]
  assign exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_probe = exe_stage_lsu_cache_0_stage__io_wb_req_bits_is_release_T
     & exe_stage_lsu_cache_0_stage_isPb; // @[DcacheStage.scala 320:49]
  assign exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_probeData = exe_stage_lsu_cache_0_stage_wbReqisData &
    exe_stage_lsu_cache_0_stage_isPb; // @[DcacheStage.scala 319:49]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_clock = exe_stage_lsu_cache_0_stage_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr = exe_stage_lsu_cache_0_stage_io_enq_bits_paddr[4]; // @[Dcache.scala 74:21]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_addrw = exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[4]; // @[Dcache.scala 74:21]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_0 = exe_stage_lsu_cache_0_stage__dataW_T_76[7:0]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_1 = exe_stage_lsu_cache_0_stage__dataW_T_76[15:8]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_2 = exe_stage_lsu_cache_0_stage__dataW_T_76[23:16]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_3 = exe_stage_lsu_cache_0_stage__dataW_T_76[31:24]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_4 = exe_stage_lsu_cache_0_stage__dataW_T_76[39:32]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_5 = exe_stage_lsu_cache_0_stage__dataW_T_76[47:40]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_6 = exe_stage_lsu_cache_0_stage__dataW_T_76[55:48]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_7 = exe_stage_lsu_cache_0_stage__dataW_T_76[63:56]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_8 = exe_stage_lsu_cache_0_stage__dataW_T_76[71:64]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_9 = exe_stage_lsu_cache_0_stage__dataW_T_76[79:72]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_10 = exe_stage_lsu_cache_0_stage__dataW_T_76[87:80]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_11 = exe_stage_lsu_cache_0_stage__dataW_T_76[95:88]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_12 = exe_stage_lsu_cache_0_stage__dataW_T_76[103:96]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_13 = exe_stage_lsu_cache_0_stage__dataW_T_76[111:104]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_14 = exe_stage_lsu_cache_0_stage__dataW_T_76[119:112]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_dataw_15 = exe_stage_lsu_cache_0_stage__dataW_T_76[127:120]; // @[DcacheStage.scala 222:60]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_0 = exe_stage_lsu_cache_0_stage__T_43[0]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_1 = exe_stage_lsu_cache_0_stage__T_43[1]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_2 = exe_stage_lsu_cache_0_stage__T_43[2]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_3 = exe_stage_lsu_cache_0_stage__T_43[3]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_4 = exe_stage_lsu_cache_0_stage__T_43[4]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_5 = exe_stage_lsu_cache_0_stage__T_43[5]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_6 = exe_stage_lsu_cache_0_stage__T_43[6]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_7 = exe_stage_lsu_cache_0_stage__T_43[7]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_8 = exe_stage_lsu_cache_0_stage__T_43[8]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_9 = exe_stage_lsu_cache_0_stage__T_43[9]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_10 = exe_stage_lsu_cache_0_stage__T_43[10]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_11 = exe_stage_lsu_cache_0_stage__T_43[11]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_12 = exe_stage_lsu_cache_0_stage__T_43[12]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_13 = exe_stage_lsu_cache_0_stage__T_43[13]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_14 = exe_stage_lsu_cache_0_stage__T_43[14]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_datawm_15 = exe_stage_lsu_cache_0_stage__T_43[15]; // @[DcacheStage.scala 113:8]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_enw = exe_stage_lsu_cache_0_stage__datEnW_0_T_30 &
    exe_stage_lsu_cache_0_stage__datEnW_0_T_76; // @[DcacheStage.scala 101:35]
  assign exe_stage_lsu_cache_0_stage_datRAM_0_io_enr = exe_stage_lsu_cache_0_stage_io_enq_ready &
    exe_stage_lsu_cache_0_stage_io_enq_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_clock = exe_stage_lsu_cache_0_stage_clock;
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_io_addrr = exe_stage_lsu_cache_0_stage_io_enq_bits_paddr[4]; // @[Dcache.scala 74:21]
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_io_addrw = exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[4]; // @[Dcache.scala 74:21]
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_io_dataw = exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr[31:5]; // @[Dcache.scala 73:21]
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_io_enw = exe_stage_lsu_cache_0_stage_pipeStage1Valid &
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant; // @[DcacheStage.scala 106:52]
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_io_enr = exe_stage_lsu_cache_0_stage_io_enq_ready &
    exe_stage_lsu_cache_0_stage_io_enq_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_lsu_cache_0_io_enq_ready = exe_stage_lsu_cache_0_op_arb_io_in_1_ready &
    exe_stage_lsu_cache_0_sbEnqReady; // @[Dcache.scala 253:41]
  assign exe_stage_lsu_cache_0_io_deq_valid = exe_stage_lsu_cache_0_rtn_fifo_io_deq_valid; // @[Dcache.scala 273:19]
  assign exe_stage_lsu_cache_0_io_deq_bits_chkIdx = exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_chkIdx; // @[Dcache.scala 273:19]
  assign exe_stage_lsu_cache_0_io_deq_bits_wb_rd0 = exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_wb_rd0; // @[Dcache.scala 273:19]
  assign exe_stage_lsu_cache_0_io_deq_bits_wb_res = exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_wb_res; // @[Dcache.scala 273:19]
  assign exe_stage_lsu_cache_0_io_deq_bits_is_load_amo = exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_load_amo; // @[Dcache.scala 273:19]
  assign exe_stage_lsu_cache_0_io_deq_bits_is_flw = exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_flw; // @[Dcache.scala 273:19]
  assign exe_stage_lsu_cache_0_io_deq_bits_is_fld = exe_stage_lsu_cache_0_rtn_fifo_io_deq_bits_is_fld; // @[Dcache.scala 273:19]
  assign exe_stage_lsu_cache_0_io_is_empty = exe_stage_lsu_cache_0__sbIdx_T & exe_stage_lsu_cache_0__sbEnqReady_T_1; // @[Dcache.scala 160:33]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_valid = exe_stage_lsu_cache_0_missUnit_io_cache_acquire_valid; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_opcode =
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_opcode; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_param =
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_param; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_size =
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_size; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_source =
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_source; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_address =
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_address; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_mask =
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_mask; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_data =
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_data; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_corrupt =
    exe_stage_lsu_cache_0_missUnit_io_cache_acquire_bits_corrupt; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grant_ready = exe_stage_lsu_cache_0_missUnit_io_cache_grant_ready; // @[Dcache.scala 185:33]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_valid =
    exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_valid; // @[Dcache.scala 186:37]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_bits_sink =
    exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_bits_sink; // @[Dcache.scala 186:37]
  assign exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_ready = exe_stage_lsu_cache_0_probeUnit_io_cache_probe_ready; // @[Dcache.scala 187:34]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_valid =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_valid; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_opcode =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_opcode; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_param =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_param; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_size =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_size; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_source =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_source; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_address =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_address; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_data =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_data; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_corrupt =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_bits_corrupt; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_ready =
    exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_ready; // @[Dcache.scala 189:38]
  assign exe_stage_lsu_cache_0_missUnit_clock = exe_stage_lsu_cache_0_clock;
  assign exe_stage_lsu_cache_0_missUnit_reset = exe_stage_lsu_cache_0_reset;
  assign exe_stage_lsu_cache_0_missUnit_io_req_valid = exe_stage_lsu_cache_0_stage_io_missUnit_req_valid; // @[Dcache.scala 216:32]
  assign exe_stage_lsu_cache_0_missUnit_io_req_bits_paddr = exe_stage_lsu_cache_0_stage_io_missUnit_req_bits_paddr; // @[Dcache.scala 216:32]
  assign exe_stage_lsu_cache_0_missUnit_io_rsp_ready = exe_stage_lsu_cache_0_rd_arb_io_in_0_ready; // @[Dcache.scala 225:31]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_acquire_ready = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_ready; // @[Dcache.scala 184:37]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grant_valid = exe_stage_lsu_cache_0_io_missUnit_dcache_grant_valid; // @[Dcache.scala 185:33]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_opcode =
    exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_opcode; // @[Dcache.scala 185:33]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_size =
    exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_size; // @[Dcache.scala 185:33]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_source =
    exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_source; // @[Dcache.scala 185:33]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_sink =
    exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_sink; // @[Dcache.scala 185:33]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_data =
    exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_data; // @[Dcache.scala 185:33]
  assign exe_stage_lsu_cache_0_missUnit_io_cache_grantAck_ready =
    exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_ready; // @[Dcache.scala 186:37]
  assign exe_stage_lsu_cache_0_missUnit_io_miss_ban = exe_stage_lsu_cache_0_writeBackUnit_io_miss_ban; // @[Dcache.scala 220:30]
  assign exe_stage_lsu_cache_0_probeUnit_clock = exe_stage_lsu_cache_0_clock;
  assign exe_stage_lsu_cache_0_probeUnit_reset = exe_stage_lsu_cache_0_reset;
  assign exe_stage_lsu_cache_0_probeUnit_io_cache_probe_valid = exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_valid; // @[Dcache.scala 187:34]
  assign exe_stage_lsu_cache_0_probeUnit_io_cache_probe_bits_address =
    exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_bits_address; // @[Dcache.scala 187:34]
  assign exe_stage_lsu_cache_0_probeUnit_io_req_ready = exe_stage_lsu_cache_0_rd_arb_io_in_1_ready; // @[Dcache.scala 229:32]
  assign exe_stage_lsu_cache_0_probeUnit_io_probeBan = exe_stage_lsu_cache_0_writeBackUnit_io_miss_ban; // @[Dcache.scala 219:31]
  assign exe_stage_lsu_cache_0_writeBackUnit_clock = exe_stage_lsu_cache_0_clock;
  assign exe_stage_lsu_cache_0_writeBackUnit_reset = exe_stage_lsu_cache_0_reset;
  assign exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_valid = exe_stage_lsu_cache_0_stage_io_wb_req_valid; // @[Dcache.scala 217:21]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_paddr = exe_stage_lsu_cache_0_stage_io_wb_req_bits_paddr; // @[Dcache.scala 217:21]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_data = exe_stage_lsu_cache_0_stage_io_wb_req_bits_data; // @[Dcache.scala 217:21]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_releaseData =
    exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_releaseData; // @[Dcache.scala 217:21]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_release =
    exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_release; // @[Dcache.scala 217:21]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_probe =
    exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_probe; // @[Dcache.scala 217:21]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_wb_req_bits_is_probeData =
    exe_stage_lsu_cache_0_stage_io_wb_req_bits_is_probeData; // @[Dcache.scala 217:21]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_release_ready =
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_ready; // @[Dcache.scala 188:41]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_valid =
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_valid; // @[Dcache.scala 189:38]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_bits_source =
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_bits_source; // @[Dcache.scala 189:38]
  assign exe_stage_lsu_cache_0_writeBackUnit_io_release_ban = exe_stage_lsu_cache_0_missUnit_io_release_ban; // @[Dcache.scala 221:38]
  assign exe_stage_lsu_cache_0_lsEntry_clock = exe_stage_lsu_cache_0_clock;
  assign exe_stage_lsu_cache_0_lsEntry_reset = exe_stage_lsu_cache_0_reset;
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_valid = exe_stage_lsu_cache_0_op_arb_io_out_valid; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_chkIdx = exe_stage_lsu_cache_0_op_arb_io_out_bits_chkIdx; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_paddr = exe_stage_lsu_cache_0_op_arb_io_out_bits_paddr; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_wdata = exe_stage_lsu_cache_0_op_arb_io_out_bits_wdata; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_wstrb = exe_stage_lsu_cache_0_op_arb_io_out_bits_wstrb; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lb = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lb; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lh = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lh; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lw = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lw; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_ld = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_ld; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lbu = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lbu; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lhu = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lhu; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lwu = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lwu; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sb = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sb; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sh = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sh; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sw = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sw; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sd = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sd; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lr_w = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lr_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sc_w = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sc_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoswap_w =
    exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoswap_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoadd_w = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoadd_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoxor_w = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoxor_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoand_w = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoand_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoor_w = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoor_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomin_w = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomin_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomax_w = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomax_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amominu_w =
    exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amominu_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomaxu_w =
    exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomaxu_w; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_lr_d = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_lr_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_sc_d = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_sc_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoswap_d =
    exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoswap_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoadd_d = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoadd_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoxor_d = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoxor_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoand_d = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoand_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amoor_d = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amoor_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomin_d = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomin_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomax_d = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomax_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amominu_d =
    exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amominu_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_amomaxu_d =
    exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_amomaxu_d; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_flw = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_flw; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fsw = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fsw; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fld = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fld; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_fsd = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_fsd; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_probe = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_probe; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_grant = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_grant; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_fun_preft = exe_stage_lsu_cache_0_op_arb_io_out_bits_fun_preft; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_enq_bits_rd_rd0 = exe_stage_lsu_cache_0_op_arb_io_out_bits_rd_rd0; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_lsEntry_io_deq_ready = exe_stage_lsu_cache_0_rd_arb_io_in_2_ready; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rtn_fifo_clock = exe_stage_lsu_cache_0_clock;
  assign exe_stage_lsu_cache_0_rtn_fifo_reset = exe_stage_lsu_cache_0_reset;
  assign exe_stage_lsu_cache_0_rtn_fifo_io_enq_valid = exe_stage_lsu_cache_0_stage_io_deq_valid; // @[Dcache.scala 270:25]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_chkIdx = exe_stage_lsu_cache_0_stage_io_deq_bits_chkIdx; // @[Dcache.scala 271:25]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_wb_rd0 = exe_stage_lsu_cache_0_stage_io_deq_bits_wb_rd0; // @[Dcache.scala 271:25]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_wb_res = exe_stage_lsu_cache_0_stage_io_deq_bits_wb_res; // @[Dcache.scala 271:25]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_load_amo = exe_stage_lsu_cache_0_stage_io_deq_bits_is_load_amo; // @[Dcache.scala 271:25]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_flw = exe_stage_lsu_cache_0_stage_io_deq_bits_is_flw; // @[Dcache.scala 271:25]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_enq_bits_is_fld = exe_stage_lsu_cache_0_stage_io_deq_bits_is_fld; // @[Dcache.scala 271:25]
  assign exe_stage_lsu_cache_0_rtn_fifo_io_deq_ready = exe_stage_lsu_cache_0_io_deq_ready; // @[Dcache.scala 273:19]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_valid = exe_stage_lsu_cache_0_reload_fifo_io_deq_valid; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_chkIdx = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_chkIdx; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_paddr = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_paddr; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_wdata = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_wdata; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_wstrb = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_wstrb; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lb = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lb; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lh = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lh; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lw = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lw; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_ld = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_ld; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lbu = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lbu; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lhu = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lhu; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lwu = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lwu; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sb = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sb; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sh = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sh; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sw = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sw; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sd = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sd; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lr_w = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lr_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sc_w = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sc_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoswap_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoswap_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoadd_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoadd_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoxor_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoxor_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoand_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoand_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoor_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoor_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomin_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomin_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomax_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomax_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amominu_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amominu_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomaxu_w =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomaxu_w; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_lr_d = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_lr_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_sc_d = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_sc_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoswap_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoswap_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoadd_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoadd_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoxor_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoxor_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoand_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoand_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amoor_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amoor_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomin_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomin_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomax_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomax_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amominu_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amominu_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_amomaxu_d =
    exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_amomaxu_d; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_flw = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_flw; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fsw = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fsw; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fld = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fld; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_fsd = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_fsd; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_probe = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_probe; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_grant = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_grant; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_fun_preft = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_fun_preft; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_0_bits_rd_rd0 = exe_stage_lsu_cache_0_reload_fifo_io_deq_bits_rd_rd0; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_valid = exe_stage_lsu_cache_0_io_enq_ready &
    exe_stage_lsu_cache_0_io_enq_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_chkIdx = exe_stage_lsu_cache_0__sbIdx_T ? 1'h0 : 1'h1; // @[Dcache.scala 143:33]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_paddr = exe_stage_lsu_cache_0_io_enq_bits_paddr; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_wdata = exe_stage_lsu_cache_0_io_enq_bits_wdata; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_wstrb = exe_stage_lsu_cache_0_io_enq_bits_wstrb; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lb = exe_stage_lsu_cache_0_io_enq_bits_fun_lb; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lh = exe_stage_lsu_cache_0_io_enq_bits_fun_lh; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lw = exe_stage_lsu_cache_0_io_enq_bits_fun_lw; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_ld = exe_stage_lsu_cache_0_io_enq_bits_fun_ld; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lbu = exe_stage_lsu_cache_0_io_enq_bits_fun_lbu; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lhu = exe_stage_lsu_cache_0_io_enq_bits_fun_lhu; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lwu = exe_stage_lsu_cache_0_io_enq_bits_fun_lwu; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sb = exe_stage_lsu_cache_0_io_enq_bits_fun_sb; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sh = exe_stage_lsu_cache_0_io_enq_bits_fun_sh; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sw = exe_stage_lsu_cache_0_io_enq_bits_fun_sw; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sd = exe_stage_lsu_cache_0_io_enq_bits_fun_sd; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lr_w = exe_stage_lsu_cache_0_io_enq_bits_fun_lr_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sc_w = exe_stage_lsu_cache_0_io_enq_bits_fun_sc_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoswap_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amoswap_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoadd_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amoadd_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoxor_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amoxor_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoand_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amoand_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoor_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amoor_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomin_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amomin_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomax_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amomax_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amominu_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amominu_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomaxu_w = exe_stage_lsu_cache_0_io_enq_bits_fun_amomaxu_w; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_lr_d = exe_stage_lsu_cache_0_io_enq_bits_fun_lr_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_sc_d = exe_stage_lsu_cache_0_io_enq_bits_fun_sc_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoswap_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amoswap_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoadd_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amoadd_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoxor_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amoxor_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoand_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amoand_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amoor_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amoor_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomin_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amomin_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomax_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amomax_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amominu_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amominu_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_amomaxu_d = exe_stage_lsu_cache_0_io_enq_bits_fun_amomaxu_d; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_flw = exe_stage_lsu_cache_0_io_enq_bits_fun_flw; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fsw = exe_stage_lsu_cache_0_io_enq_bits_fun_fsw; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fld = exe_stage_lsu_cache_0_io_enq_bits_fun_fld; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_fun_fsd = exe_stage_lsu_cache_0_io_enq_bits_fun_fsd; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_in_1_bits_rd_rd0 = exe_stage_lsu_cache_0_io_enq_bits_rd_rd0; // @[Dcache.scala 255:25]
  assign exe_stage_lsu_cache_0_op_arb_io_out_ready = exe_stage_lsu_cache_0_lsEntry_io_enq_ready; // @[Dcache.scala 257:17]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_0_valid = exe_stage_lsu_cache_0_missUnit_io_rsp_valid; // @[Dcache.scala 224:27]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_0_bits_paddr = exe_stage_lsu_cache_0_missUnit_io_rsp_bits_paddr; // @[Util.scala 48:19 50:15]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_0_bits_wdata = exe_stage_lsu_cache_0_missUnit_io_rsp_bits_wdata; // @[Util.scala 48:19 52:15]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_1_valid = exe_stage_lsu_cache_0_probeUnit_io_req_valid; // @[Dcache.scala 228:27]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_1_bits_paddr = exe_stage_lsu_cache_0_probeUnit_io_req_bits_paddr; // @[Util.scala 64:19 65:15]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_valid = exe_stage_lsu_cache_0_lsEntry_io_deq_valid; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_chkIdx = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_chkIdx; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_paddr = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_paddr; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_wdata = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_wdata; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_wstrb = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_wstrb; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lb = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lb; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lh = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lh; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lw = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lw; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_ld = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_ld; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lbu = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lbu; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lhu = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lhu; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lwu = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lwu; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sb = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sb; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sh = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sh; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sw = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sw; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sd = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sd; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lr_w = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lr_w; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sc_w = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sc_w; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoswap_w =
    exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoswap_w; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoadd_w = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoadd_w
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoxor_w = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoxor_w
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoand_w = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoand_w
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoor_w = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoor_w; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomin_w = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomin_w
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomax_w = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomax_w
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amominu_w =
    exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amominu_w; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomaxu_w =
    exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomaxu_w; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_lr_d = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_lr_d; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_sc_d = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_sc_d; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoswap_d =
    exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoswap_d; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoadd_d = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoadd_d
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoxor_d = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoxor_d
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoand_d = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoand_d
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amoor_d = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amoor_d; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomin_d = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomin_d
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomax_d = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomax_d
    ; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amominu_d =
    exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amominu_d; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_amomaxu_d =
    exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_amomaxu_d; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_flw = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_flw; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fsw = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fsw; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fld = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fld; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_fsd = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_fsd; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_probe = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_probe; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_grant = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_grant; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_fun_preft = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_fun_preft; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_in_2_bits_rd_rd0 = exe_stage_lsu_cache_0_lsEntry_io_deq_bits_rd_rd0; // @[Dcache.scala 264:18]
  assign exe_stage_lsu_cache_0_rd_arb_io_out_ready = exe_stage_lsu_cache_0_stage_io_enq_ready; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_reload_fifo_clock = exe_stage_lsu_cache_0_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_reset = exe_stage_lsu_cache_0_reset;
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_valid = exe_stage_lsu_cache_0_stage_io_reload_valid; // @[Dcache.scala 248:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_chkIdx = exe_stage_lsu_cache_0_stage_io_reload_bits_chkIdx; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_paddr = exe_stage_lsu_cache_0_stage_io_reload_bits_paddr; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_wdata = exe_stage_lsu_cache_0_stage_io_reload_bits_wdata; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_wstrb = exe_stage_lsu_cache_0_stage_io_reload_bits_wstrb; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lb = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lb; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lh = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lh; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lw = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lw; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_ld = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_ld; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lbu = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lbu; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lhu = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lhu; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lwu = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lwu; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sb = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sb; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sh = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sh; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sw = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sw; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sd = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sd; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lr_w = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lr_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sc_w = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sc_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoswap_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoswap_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoadd_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoadd_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoxor_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoxor_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoand_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoand_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoor_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoor_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomin_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomin_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomax_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomax_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amominu_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amominu_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomaxu_w =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomaxu_w; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_lr_d = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_lr_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_sc_d = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_sc_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoswap_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoswap_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoadd_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoadd_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoxor_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoxor_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoand_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoand_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amoor_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amoor_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomin_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomin_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomax_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomax_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amominu_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amominu_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_amomaxu_d =
    exe_stage_lsu_cache_0_stage_io_reload_bits_fun_amomaxu_d; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_flw = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_flw; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fsw = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fsw; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fld = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fld; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_fsd = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_fsd; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_probe = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_probe; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_grant = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_grant; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_fun_preft = exe_stage_lsu_cache_0_stage_io_reload_bits_fun_preft; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_enq_bits_rd_rd0 = exe_stage_lsu_cache_0_stage_io_reload_bits_rd_rd0; // @[Dcache.scala 249:28]
  assign exe_stage_lsu_cache_0_reload_fifo_io_deq_ready = exe_stage_lsu_cache_0_op_arb_io_in_0_ready; // @[Dcache.scala 252:22]
  assign exe_stage_lsu_cache_0_stage_clock = exe_stage_lsu_cache_0_clock;
  assign exe_stage_lsu_cache_0_stage_reset = exe_stage_lsu_cache_0_reset;
  assign exe_stage_lsu_cache_0_stage_io_enq_valid = exe_stage_lsu_cache_0_rd_arb_io_out_valid; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_chkIdx = exe_stage_lsu_cache_0_rd_arb_io_out_bits_chkIdx; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_paddr = exe_stage_lsu_cache_0_rd_arb_io_out_bits_paddr; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_wdata = exe_stage_lsu_cache_0_rd_arb_io_out_bits_wdata; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_wstrb = exe_stage_lsu_cache_0_rd_arb_io_out_bits_wstrb; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lb = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lb; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lh = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lh; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lw = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lw; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_ld = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_ld; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lbu = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lbu; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lhu = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lhu; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lwu = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lwu; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sb = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sb; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sh = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sh; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sw = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sw; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sd = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sd; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lr_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lr_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sc_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sc_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoswap_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoswap_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoadd_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoadd_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoxor_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoxor_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoand_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoand_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoor_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoor_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomin_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomin_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomax_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomax_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amominu_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amominu_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomaxu_w = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomaxu_w; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lr_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_lr_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sc_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_sc_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoswap_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoswap_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoadd_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoadd_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoxor_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoxor_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoand_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoand_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoor_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amoor_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomin_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomin_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomax_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomax_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amominu_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amominu_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomaxu_d = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_amomaxu_d; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_flw = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_flw; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fsw = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fsw; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fld = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fld; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fsd = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_fsd; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_probe = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_probe; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_grant = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_grant; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_fun_preft = exe_stage_lsu_cache_0_rd_arb_io_out_bits_fun_preft; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_enq_bits_rd_rd0 = exe_stage_lsu_cache_0_rd_arb_io_out_bits_rd_rd0; // @[Dcache.scala 265:16]
  assign exe_stage_lsu_cache_0_stage_io_isCacheEmpty = exe_stage_lsu_cache_0__sbIdx_T &
    exe_stage_lsu_cache_0__sbEnqReady_T_1; // @[Dcache.scala 160:33]
  assign exe_stage_lsu_cache_0_stage_io_flush = exe_stage_lsu_cache_0_io_flush; // @[Dcache.scala 259:18]
  assign exe_stage_lsu_lu_wb_arb_io_in_0_ready = exe_stage_lsu_lu_wb_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_lu_wb_arb_io_in_1_ready = exe_stage_lsu_lu_wb_arb_grant_1 & exe_stage_lsu_lu_wb_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_lu_wb_arb_io_in_2_ready = exe_stage_lsu_lu_wb_arb_grant_2 & exe_stage_lsu_lu_wb_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_lu_wb_arb_io_out_valid = exe_stage_lsu_lu_wb_arb__io_out_valid_T |
    exe_stage_lsu_lu_wb_arb_io_in_2_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_lsu_lu_wb_arb_io_out_bits_wb_rd0 = exe_stage_lsu_lu_wb_arb_io_in_0_valid ?
    exe_stage_lsu_lu_wb_arb_io_in_0_bits_wb_rd0 : exe_stage_lsu_lu_wb_arb__GEN_2; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_lu_wb_arb_io_out_bits_wb_res = exe_stage_lsu_lu_wb_arb_io_in_0_valid ?
    exe_stage_lsu_lu_wb_arb_io_in_0_bits_wb_res : exe_stage_lsu_lu_wb_arb__GEN_3; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_lu_wb_arb_io_out_bits_is_flw = exe_stage_lsu_lu_wb_arb_io_in_0_valid ?
    exe_stage_lsu_lu_wb_arb_io_in_0_bits_is_flw : exe_stage_lsu_lu_wb_arb__GEN_5; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_lu_wb_arb_io_out_bits_is_fld = exe_stage_lsu_lu_wb_arb_io_in_0_valid ?
    exe_stage_lsu_lu_wb_arb_io_in_0_bits_is_fld : exe_stage_lsu_lu_wb_arb__GEN_6; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_lu_wb_fifo_ram_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_lu_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_lu_wb_fifo_ram_rd0_io_deq_bits_MPORT_data =
    exe_stage_lsu_lu_wb_fifo_ram_rd0[exe_stage_lsu_lu_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_data = exe_stage_lsu_lu_wb_fifo_io_enq_bits_rd0;
  assign exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_addr = 1'h0;
  assign exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_mask = 1'h1;
  assign exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_en = exe_stage_lsu_lu_wb_fifo__empty_T ?
    exe_stage_lsu_lu_wb_fifo__GEN_10 : exe_stage_lsu_lu_wb_fifo__do_enq_T;
  assign exe_stage_lsu_lu_wb_fifo_ram_res_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_lu_wb_fifo_ram_res_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_lu_wb_fifo_ram_res_io_deq_bits_MPORT_data =
    exe_stage_lsu_lu_wb_fifo_ram_res[exe_stage_lsu_lu_wb_fifo_ram_res_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_data = exe_stage_lsu_lu_wb_fifo_io_enq_bits_res;
  assign exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_addr = 1'h0;
  assign exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_mask = 1'h1;
  assign exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_en = exe_stage_lsu_lu_wb_fifo__empty_T ?
    exe_stage_lsu_lu_wb_fifo__GEN_10 : exe_stage_lsu_lu_wb_fifo__do_enq_T;
  assign exe_stage_lsu_lu_wb_fifo_io_enq_ready = ~exe_stage_lsu_lu_wb_fifo_maybe_full; // @[Decoupled.scala 305:19]
  assign exe_stage_lsu_lu_wb_fifo_io_deq_valid = exe_stage_lsu_lu_wb_fifo_io_enq_valid |
    exe_stage_lsu_lu_wb_fifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign exe_stage_lsu_lu_wb_fifo_io_deq_bits_rd0 = exe_stage_lsu_lu_wb_fifo__empty_T ?
    exe_stage_lsu_lu_wb_fifo_io_enq_bits_rd0 : exe_stage_lsu_lu_wb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_lu_wb_fifo_io_deq_bits_res = exe_stage_lsu_lu_wb_fifo__empty_T ?
    exe_stage_lsu_lu_wb_fifo_io_enq_bits_res : exe_stage_lsu_lu_wb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_flu_wb_fifo_io_enq_ready = ~exe_stage_lsu_flu_wb_fifo_maybe_full; // @[Decoupled.scala 305:19]
  assign exe_stage_lsu_flu_wb_fifo_io_deq_valid = exe_stage_lsu_flu_wb_fifo_io_enq_valid |
    exe_stage_lsu_flu_wb_fifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign exe_stage_lsu_su_wb_fifo_ram_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_su_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_su_wb_fifo_ram_rd0_io_deq_bits_MPORT_data =
    exe_stage_lsu_su_wb_fifo_ram_rd0[exe_stage_lsu_su_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_data = exe_stage_lsu_su_wb_fifo_io_enq_bits_rd0;
  assign exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_addr = 1'h0;
  assign exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_mask = 1'h1;
  assign exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_en = exe_stage_lsu_su_wb_fifo__empty_T ?
    exe_stage_lsu_su_wb_fifo__GEN_10 : exe_stage_lsu_su_wb_fifo__do_enq_T;
  assign exe_stage_lsu_su_wb_fifo_ram_res_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_su_wb_fifo_ram_res_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_su_wb_fifo_ram_res_io_deq_bits_MPORT_data =
    exe_stage_lsu_su_wb_fifo_ram_res[exe_stage_lsu_su_wb_fifo_ram_res_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_su_wb_fifo_ram_res_MPORT_data = 64'h0;
  assign exe_stage_lsu_su_wb_fifo_ram_res_MPORT_addr = 1'h0;
  assign exe_stage_lsu_su_wb_fifo_ram_res_MPORT_mask = 1'h1;
  assign exe_stage_lsu_su_wb_fifo_ram_res_MPORT_en = exe_stage_lsu_su_wb_fifo__empty_T ?
    exe_stage_lsu_su_wb_fifo__GEN_10 : exe_stage_lsu_su_wb_fifo__do_enq_T;
  assign exe_stage_lsu_su_wb_fifo_io_enq_ready = ~exe_stage_lsu_su_wb_fifo_maybe_full; // @[Decoupled.scala 305:19]
  assign exe_stage_lsu_su_wb_fifo_io_deq_valid = exe_stage_lsu_su_wb_fifo_io_enq_valid |
    exe_stage_lsu_su_wb_fifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign exe_stage_lsu_su_wb_fifo_io_deq_bits_rd0 = exe_stage_lsu_su_wb_fifo__empty_T ?
    exe_stage_lsu_su_wb_fifo_io_enq_bits_rd0 : exe_stage_lsu_su_wb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_su_wb_fifo_io_deq_bits_res = exe_stage_lsu_su_wb_fifo__empty_T ? 64'h0 :
    exe_stage_lsu_su_wb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_fe_wb_fifo_ram_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_fe_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_fe_wb_fifo_ram_rd0_io_deq_bits_MPORT_data =
    exe_stage_lsu_fe_wb_fifo_ram_rd0[exe_stage_lsu_fe_wb_fifo_ram_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_data = exe_stage_lsu_fe_wb_fifo_io_enq_bits_rd0;
  assign exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_addr = 1'h0;
  assign exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_mask = 1'h1;
  assign exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_en = exe_stage_lsu_fe_wb_fifo__empty_T ?
    exe_stage_lsu_fe_wb_fifo__GEN_10 : exe_stage_lsu_fe_wb_fifo__do_enq_T;
  assign exe_stage_lsu_fe_wb_fifo_ram_res_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_lsu_fe_wb_fifo_ram_res_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_lsu_fe_wb_fifo_ram_res_io_deq_bits_MPORT_data =
    exe_stage_lsu_fe_wb_fifo_ram_res[exe_stage_lsu_fe_wb_fifo_ram_res_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_data = 64'h0;
  assign exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_addr = 1'h0;
  assign exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_mask = 1'h1;
  assign exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_en = exe_stage_lsu_fe_wb_fifo__empty_T ?
    exe_stage_lsu_fe_wb_fifo__GEN_10 : exe_stage_lsu_fe_wb_fifo__do_enq_T;
  assign exe_stage_lsu_fe_wb_fifo_io_enq_ready = ~exe_stage_lsu_fe_wb_fifo_maybe_full; // @[Decoupled.scala 305:19]
  assign exe_stage_lsu_fe_wb_fifo_io_deq_valid = exe_stage_lsu_fe_wb_fifo_io_enq_valid |
    exe_stage_lsu_fe_wb_fifo__io_deq_valid_T; // @[Decoupled.scala 304:16 316:{24,39}]
  assign exe_stage_lsu_fe_wb_fifo_io_deq_bits_rd0 = exe_stage_lsu_fe_wb_fifo__empty_T ?
    exe_stage_lsu_fe_wb_fifo_io_enq_bits_rd0 : exe_stage_lsu_fe_wb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_fe_wb_fifo_io_deq_bits_res = exe_stage_lsu_fe_wb_fifo__empty_T ? 64'h0 :
    exe_stage_lsu_fe_wb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign exe_stage_lsu_rtn_arb_io_in_0_ready = exe_stage_lsu_rtn_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_rtn_arb_io_in_1_ready = exe_stage_lsu_rtn_arb_grant_1 & exe_stage_lsu_rtn_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_rtn_arb_io_in_2_ready = exe_stage_lsu_rtn_arb_grant_2 & exe_stage_lsu_rtn_arb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_rtn_arb_io_out_valid = exe_stage_lsu_rtn_arb__io_out_valid_T |
    exe_stage_lsu_rtn_arb_io_in_2_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_lsu_rtn_arb_io_out_bits_rd0 = exe_stage_lsu_rtn_arb_io_in_0_valid ?
    exe_stage_lsu_rtn_arb_io_in_0_bits_rd0 : exe_stage_lsu_rtn_arb__GEN_1; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_rtn_arb_io_out_bits_res = exe_stage_lsu_rtn_arb_io_in_0_valid ?
    exe_stage_lsu_rtn_arb_io_in_0_bits_res : exe_stage_lsu_rtn_arb__GEN_2; // @[Arbiter.scala 138:26 140:19]
  assign exe_stage_lsu_acquireArb_io_in_0_ready = exe_stage_lsu_acquireArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_acquireArb_io_out_valid = exe_stage_lsu_acquireArb_io_in_0_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_lsu_acquireArb_io_out_bits_opcode = exe_stage_lsu_acquireArb_io_in_0_bits_opcode; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_acquireArb_io_out_bits_param = exe_stage_lsu_acquireArb_io_in_0_bits_param; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_acquireArb_io_out_bits_size = exe_stage_lsu_acquireArb_io_in_0_bits_size; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_acquireArb_io_out_bits_source = exe_stage_lsu_acquireArb_io_in_0_bits_source; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_acquireArb_io_out_bits_address = exe_stage_lsu_acquireArb_io_in_0_bits_address; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_acquireArb_io_out_bits_mask = exe_stage_lsu_acquireArb_io_in_0_bits_mask; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_acquireArb_io_out_bits_data = exe_stage_lsu_acquireArb_io_in_0_bits_data; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_acquireArb_io_out_bits_corrupt = exe_stage_lsu_acquireArb_io_in_0_bits_corrupt; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_grantAckArb_io_in_0_ready = exe_stage_lsu_grantAckArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_grantAckArb_io_out_valid = exe_stage_lsu_grantAckArb_io_in_0_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_lsu_grantAckArb_io_out_bits_sink = exe_stage_lsu_grantAckArb_io_in_0_bits_sink; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_releaseArb_io_in_0_ready = exe_stage_lsu_releaseArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_lsu_releaseArb_io_out_valid = exe_stage_lsu_releaseArb_io_in_0_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_lsu_releaseArb_io_out_bits_opcode = exe_stage_lsu_releaseArb_io_in_0_bits_opcode; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_releaseArb_io_out_bits_param = exe_stage_lsu_releaseArb_io_in_0_bits_param; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_releaseArb_io_out_bits_size = exe_stage_lsu_releaseArb_io_in_0_bits_size; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_releaseArb_io_out_bits_source = exe_stage_lsu_releaseArb_io_in_0_bits_source; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_releaseArb_io_out_bits_address = exe_stage_lsu_releaseArb_io_in_0_bits_address; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_releaseArb_io_out_bits_data = exe_stage_lsu_releaseArb_io_in_0_bits_data; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_releaseArb_io_out_bits_corrupt = exe_stage_lsu_releaseArb_io_in_0_bits_corrupt; // @[Arbiter.scala 136:15]
  assign exe_stage_lsu_io_lsu_iss_exe_ready = exe_stage_lsu__io_lsu_iss_exe_ready_T_3 |
    exe_stage_lsu__io_lsu_iss_exe_ready_T_7; // @[Lsu.scala 147:61]
  assign exe_stage_lsu_io_lsu_exe_iwb_valid = exe_stage_lsu_rtn_arb_io_out_valid; // @[Lsu.scala 477:18]
  assign exe_stage_lsu_io_lsu_exe_iwb_bits_rd0 = exe_stage_lsu_rtn_arb_io_out_bits_rd0; // @[Lsu.scala 477:18]
  assign exe_stage_lsu_io_lsu_exe_iwb_bits_res = exe_stage_lsu_rtn_arb_io_out_bits_res; // @[Lsu.scala 477:18]
  assign exe_stage_lsu_io_lsu_exe_fwb_valid = exe_stage_lsu_flu_wb_fifo_io_deq_valid; // @[Lsu.scala 450:22]
  assign exe_stage_lsu_io_lsu_cmm_is_access_fault = exe_stage_lsu_isAccessFaultReg; // @[Lsu.scala 501:30]
  assign exe_stage_lsu_io_lsu_cmm_is_paging_fault = exe_stage_lsu_isPagingFault; // @[Lsu.scala 502:30]
  assign exe_stage_lsu_io_lsu_cmm_is_misAlign = exe_stage_lsu_isMisAlign; // @[Lsu.scala 503:30]
  assign exe_stage_lsu_io_lsu_cmm_trap_addr = exe_stage_lsu_trapAddrReg; // @[Lsu.scala 504:30]
  assign exe_stage_lsu_io_lsu_mmu_valid = exe_stage_lsu_io_lsu_iss_exe_valid & exe_stage_lsu__io_lsu_mmu_valid_T_2; // @[Lsu.scala 141:44]
  assign exe_stage_lsu_io_lsu_mmu_bits_is_X = 1'h0; // @[Lsu.scala 145:24]
  assign exe_stage_lsu_io_lsu_mmu_bits_is_W = exe_stage_lsu__io_lsu_mmu_bits_is_W_T_6 | exe_stage_lsu__T_33; // @[riscv_isa.scala 162:28]
  assign exe_stage_lsu_io_lsu_mmu_bits_is_R = exe_stage_lsu__io_lsu_mmu_bits_is_R_T_11 | exe_stage_lsu__T_33; // @[riscv_isa.scala 161:28]
  assign exe_stage_lsu_io_lsu_mmu_bits_vaddr = exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op1; // @[Lsu.scala 142:25]
  assign exe_stage_lsu_io_mmu_lsu_ready = exe_stage_lsu__io_mmu_lsu_ready_T_46 & exe_stage_lsu__addrTransIO_valid_T_50; // @[Lsu.scala 139:104]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_valid = exe_stage_lsu_acquireArb_io_out_valid; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_bits_opcode = exe_stage_lsu_acquireArb_io_out_bits_opcode; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_bits_param = exe_stage_lsu_acquireArb_io_out_bits_param; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_bits_size = exe_stage_lsu_acquireArb_io_out_bits_size; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_bits_source = exe_stage_lsu_acquireArb_io_out_bits_source; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_bits_address = exe_stage_lsu_acquireArb_io_out_bits_address; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_bits_mask = exe_stage_lsu_acquireArb_io_out_bits_mask; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_bits_data = exe_stage_lsu_acquireArb_io_out_bits_data; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_bits_corrupt = exe_stage_lsu_acquireArb_io_out_bits_corrupt; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_io_missUnit_dcache_grant_ready = exe_stage_lsu__T_38 &
    exe_stage_lsu_cache_0_io_missUnit_dcache_grant_ready; // @[Lsu.scala 282:40 307:64 308:47]
  assign exe_stage_lsu_io_missUnit_dcache_grantAck_valid = exe_stage_lsu_grantAckArb_io_out_valid; // @[Lsu.scala 303:37]
  assign exe_stage_lsu_io_missUnit_dcache_grantAck_bits_sink = exe_stage_lsu_grantAckArb_io_out_bits_sink; // @[Lsu.scala 303:37]
  assign exe_stage_lsu_io_probeUnit_dcache_probe_ready = exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_ready; // @[Lsu.scala 313:120 285:41 314:48]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_valid = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_out_valid : exe_stage_lsu__GEN_365; // @[Lsu.scala 334:64 335:45]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_bits_opcode = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_out_bits_opcode : exe_stage_lsu__GEN_358; // @[Lsu.scala 334:64 335:45]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_bits_param = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_out_bits_param : exe_stage_lsu__GEN_359; // @[Lsu.scala 334:64 335:45]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_bits_size = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_out_bits_size : exe_stage_lsu__GEN_360; // @[Lsu.scala 334:64 335:45]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_bits_source = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_out_bits_source : exe_stage_lsu__GEN_361; // @[Lsu.scala 334:64 335:45]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_bits_address = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_out_bits_address : exe_stage_lsu__GEN_362; // @[Lsu.scala 334:64 335:45]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_bits_data = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_out_bits_data : exe_stage_lsu__GEN_363; // @[Lsu.scala 334:64 335:45]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_bits_corrupt = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_out_bits_corrupt : exe_stage_lsu__GEN_364; // @[Lsu.scala 334:64 335:45]
  assign exe_stage_lsu_io_writeBackUnit_dcache_grant_ready = exe_stage_lsu__T_40 &
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_ready; // @[Lsu.scala 288:45 317:69 318:52]
  assign exe_stage_lsu_io_system_getPut_valid = exe_stage_lsu_system_io_getPut_valid; // @[Lsu.scala 389:26]
  assign exe_stage_lsu_io_system_getPut_bits_opcode = exe_stage_lsu_system_io_getPut_bits_opcode; // @[Lsu.scala 390:26]
  assign exe_stage_lsu_io_system_getPut_bits_param = exe_stage_lsu_system_io_getPut_bits_param; // @[Lsu.scala 390:26]
  assign exe_stage_lsu_io_system_getPut_bits_size = exe_stage_lsu_system_io_getPut_bits_size; // @[Lsu.scala 390:26]
  assign exe_stage_lsu_io_system_getPut_bits_source = exe_stage_lsu_system_io_getPut_bits_source; // @[Lsu.scala 390:26]
  assign exe_stage_lsu_io_system_getPut_bits_address = exe_stage_lsu_system_io_getPut_bits_address; // @[Lsu.scala 390:26]
  assign exe_stage_lsu_io_system_getPut_bits_mask = exe_stage_lsu_system_io_getPut_bits_mask; // @[Lsu.scala 390:26]
  assign exe_stage_lsu_io_system_getPut_bits_data = exe_stage_lsu_system_io_getPut_bits_data; // @[Lsu.scala 390:26]
  assign exe_stage_lsu_io_system_getPut_bits_corrupt = exe_stage_lsu_system_io_getPut_bits_corrupt; // @[Lsu.scala 390:26]
  assign exe_stage_lsu_io_system_access_ready = exe_stage_lsu_system_io_access_ready; // @[Lsu.scala 394:26]
  assign exe_stage_lsu_io_periph_getPut_valid = exe_stage_lsu_periph_io_getPut_valid; // @[Lsu.scala 400:26]
  assign exe_stage_lsu_io_periph_getPut_bits_opcode = exe_stage_lsu_periph_io_getPut_bits_opcode; // @[Lsu.scala 401:26]
  assign exe_stage_lsu_io_periph_getPut_bits_param = exe_stage_lsu_periph_io_getPut_bits_param; // @[Lsu.scala 401:26]
  assign exe_stage_lsu_io_periph_getPut_bits_size = exe_stage_lsu_periph_io_getPut_bits_size; // @[Lsu.scala 401:26]
  assign exe_stage_lsu_io_periph_getPut_bits_source = exe_stage_lsu_periph_io_getPut_bits_source; // @[Lsu.scala 401:26]
  assign exe_stage_lsu_io_periph_getPut_bits_address = exe_stage_lsu_periph_io_getPut_bits_address; // @[Lsu.scala 401:26]
  assign exe_stage_lsu_io_periph_getPut_bits_mask = exe_stage_lsu_periph_io_getPut_bits_mask; // @[Lsu.scala 401:26]
  assign exe_stage_lsu_io_periph_getPut_bits_data = exe_stage_lsu_periph_io_getPut_bits_data; // @[Lsu.scala 401:26]
  assign exe_stage_lsu_io_periph_getPut_bits_corrupt = exe_stage_lsu_periph_io_getPut_bits_corrupt; // @[Lsu.scala 401:26]
  assign exe_stage_lsu_io_periph_access_ready = exe_stage_lsu_periph_io_access_ready; // @[Lsu.scala 405:26]
  assign exe_stage_lsu_stQueue_clock = exe_stage_lsu_clock;
  assign exe_stage_lsu_stQueue_reset = exe_stage_lsu_reset;
  assign exe_stage_lsu_stQueue_io_enq_valid = exe_stage_lsu__stQueue_io_enq_valid_T |
    exe_stage_lsu__stQueue_io_enq_valid_T_1; // @[Lsu.scala 194:39]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_lb = exe_stage_lsu__stQueue_io_enq_bits_T_131 |
    exe_stage_lsu__stQueue_io_enq_bits_T_132; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_lh = exe_stage_lsu__stQueue_io_enq_bits_T_128 |
    exe_stage_lsu__stQueue_io_enq_bits_T_129; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_lw = exe_stage_lsu__stQueue_io_enq_bits_T_125 |
    exe_stage_lsu__stQueue_io_enq_bits_T_126; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_ld = exe_stage_lsu__stQueue_io_enq_bits_T_122 |
    exe_stage_lsu__stQueue_io_enq_bits_T_123; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_lbu = exe_stage_lsu__stQueue_io_enq_bits_T_119 |
    exe_stage_lsu__stQueue_io_enq_bits_T_120; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_lhu = exe_stage_lsu__stQueue_io_enq_bits_T_116 |
    exe_stage_lsu__stQueue_io_enq_bits_T_117; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_lwu = exe_stage_lsu__stQueue_io_enq_bits_T_113 |
    exe_stage_lsu__stQueue_io_enq_bits_T_114; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_sb = exe_stage_lsu__stQueue_io_enq_bits_T_110 |
    exe_stage_lsu__stQueue_io_enq_bits_T_111; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_sh = exe_stage_lsu__stQueue_io_enq_bits_T_107 |
    exe_stage_lsu__stQueue_io_enq_bits_T_108; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_sw = exe_stage_lsu__stQueue_io_enq_bits_T_104 |
    exe_stage_lsu__stQueue_io_enq_bits_T_105; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_sd = exe_stage_lsu__stQueue_io_enq_bits_T_101 |
    exe_stage_lsu__stQueue_io_enq_bits_T_102; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_lr_w = exe_stage_lsu__stQueue_io_enq_bits_T_89 |
    exe_stage_lsu__stQueue_io_enq_bits_T_90; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_sc_w = exe_stage_lsu__stQueue_io_enq_bits_T_86 |
    exe_stage_lsu__stQueue_io_enq_bits_T_87; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoswap_w = exe_stage_lsu__stQueue_io_enq_bits_T_83 |
    exe_stage_lsu__stQueue_io_enq_bits_T_84; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoadd_w = exe_stage_lsu__stQueue_io_enq_bits_T_80 |
    exe_stage_lsu__stQueue_io_enq_bits_T_81; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoxor_w = exe_stage_lsu__stQueue_io_enq_bits_T_77 |
    exe_stage_lsu__stQueue_io_enq_bits_T_78; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoand_w = exe_stage_lsu__stQueue_io_enq_bits_T_74 |
    exe_stage_lsu__stQueue_io_enq_bits_T_75; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoor_w = exe_stage_lsu__stQueue_io_enq_bits_T_71 |
    exe_stage_lsu__stQueue_io_enq_bits_T_72; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amomin_w = exe_stage_lsu__stQueue_io_enq_bits_T_68 |
    exe_stage_lsu__stQueue_io_enq_bits_T_69; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amomax_w = exe_stage_lsu__stQueue_io_enq_bits_T_65 |
    exe_stage_lsu__stQueue_io_enq_bits_T_66; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amominu_w = exe_stage_lsu__stQueue_io_enq_bits_T_62 |
    exe_stage_lsu__stQueue_io_enq_bits_T_63; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amomaxu_w = exe_stage_lsu__stQueue_io_enq_bits_T_59 |
    exe_stage_lsu__stQueue_io_enq_bits_T_60; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_lr_d = exe_stage_lsu__stQueue_io_enq_bits_T_56 |
    exe_stage_lsu__stQueue_io_enq_bits_T_57; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_sc_d = exe_stage_lsu__stQueue_io_enq_bits_T_53 |
    exe_stage_lsu__stQueue_io_enq_bits_T_54; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoswap_d = exe_stage_lsu__stQueue_io_enq_bits_T_50 |
    exe_stage_lsu__stQueue_io_enq_bits_T_51; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoadd_d = exe_stage_lsu__stQueue_io_enq_bits_T_47 |
    exe_stage_lsu__stQueue_io_enq_bits_T_48; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoxor_d = exe_stage_lsu__stQueue_io_enq_bits_T_44 |
    exe_stage_lsu__stQueue_io_enq_bits_T_45; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoand_d = exe_stage_lsu__stQueue_io_enq_bits_T_41 |
    exe_stage_lsu__stQueue_io_enq_bits_T_42; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amoor_d = exe_stage_lsu__stQueue_io_enq_bits_T_38 |
    exe_stage_lsu__stQueue_io_enq_bits_T_39; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amomin_d = exe_stage_lsu__stQueue_io_enq_bits_T_35 |
    exe_stage_lsu__stQueue_io_enq_bits_T_36; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amomax_d = exe_stage_lsu__stQueue_io_enq_bits_T_32 |
    exe_stage_lsu__stQueue_io_enq_bits_T_33; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amominu_d = exe_stage_lsu__stQueue_io_enq_bits_T_29 |
    exe_stage_lsu__stQueue_io_enq_bits_T_30; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_amomaxu_d = exe_stage_lsu__stQueue_io_enq_bits_T_26 |
    exe_stage_lsu__stQueue_io_enq_bits_T_27; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_flw = exe_stage_lsu__stQueue_io_enq_bits_T_23 |
    exe_stage_lsu__stQueue_io_enq_bits_T_24; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_fsw = exe_stage_lsu__stQueue_io_enq_bits_T_20 |
    exe_stage_lsu__stQueue_io_enq_bits_T_21; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_fld = exe_stage_lsu__stQueue_io_enq_bits_T_17 |
    exe_stage_lsu__stQueue_io_enq_bits_T_18; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_fun_fsd = exe_stage_lsu__stQueue_io_enq_bits_T_14 |
    exe_stage_lsu__stQueue_io_enq_bits_T_15; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_param_rd0 = exe_stage_lsu__stQueue_io_enq_bits_T_11 |
    exe_stage_lsu__stQueue_io_enq_bits_T_12; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_param_dat_op1 = exe_stage_lsu__stQueue_io_enq_bits_T_8 |
    exe_stage_lsu__stQueue_io_enq_bits_T_9; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_enq_bits_param_dat_op2 = exe_stage_lsu__stQueue_io_enq_bits_T_5 |
    exe_stage_lsu__stQueue_io_enq_bits_T_6; // @[Mux.scala 27:73]
  assign exe_stage_lsu_stQueue_io_deq_ready = exe_stage_lsu_ls_arb_io_in_1_ready; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_stQueue_io_cmm_lsu_is_amo_pending = exe_stage_lsu_io_cmm_lsu_is_amo_pending; // @[Lsu.scala 200:22]
  assign exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 = exe_stage_lsu_io_cmm_lsu_is_store_commit_0; // @[Lsu.scala 200:22]
  assign exe_stage_lsu_stQueue_io_overlapReq_valid = exe_stage_lsu__T_9 & exe_stage_lsu__addrTransIO_valid_T_51; // @[Lsu.scala 162:38 163:23 167:18]
  assign exe_stage_lsu_stQueue_io_overlapReq_bits_paddr = exe_stage_lsu__GEN_42[31:0]; // @[Lsu.scala 208:36]
  assign exe_stage_lsu_stQueue_io_flush = exe_stage_lsu_io_flush; // @[Lsu.scala 202:20]
  assign exe_stage_lsu_ls_arb_io_in_0_valid = exe_stage_lsu__GEN_0 & exe_stage_lsu_stQueue_io_overlapResp_valid; // @[Lsu.scala 211:41]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_lb = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lb; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_lh = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lh; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_lw = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lw; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_ld = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_ld; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_lbu = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lbu; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_lhu = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lhu; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_lwu = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lwu; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_sb = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sb; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_sh = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sh; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_sw = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sw; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_sd = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sd; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_lr_w = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_sc_w = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoswap_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoadd_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoxor_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoand_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoor_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomin_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomax_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amominu_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomaxu_w = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_lr_d = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_sc_d = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoswap_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoadd_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoxor_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoand_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amoor_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomin_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomax_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amominu_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_amomaxu_d = exe_stage_lsu__T_9 &
    exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_flw = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_flw; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_fsw = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsw; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_fld = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fld; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_fun_fsd = exe_stage_lsu__T_9 & exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsd; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_param_rd0 = exe_stage_lsu__T_9 ? exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0
     : 6'h0; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_param_dat_op1 = exe_stage_lsu__T_9 ? exe_stage_lsu_io_mmu_lsu_bits_paddr : 64'h0
    ; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_0_bits_param_dat_op2 = exe_stage_lsu__T_9 ?
    exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op2 : 64'h0; // @[Lsu.scala 162:38 164:23 168:18]
  assign exe_stage_lsu_ls_arb_io_in_1_valid = exe_stage_lsu_stQueue_io_deq_valid; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_lb = exe_stage_lsu_stQueue_io_deq_bits_fun_lb; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_lh = exe_stage_lsu_stQueue_io_deq_bits_fun_lh; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_lw = exe_stage_lsu_stQueue_io_deq_bits_fun_lw; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_ld = exe_stage_lsu_stQueue_io_deq_bits_fun_ld; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_lbu = exe_stage_lsu_stQueue_io_deq_bits_fun_lbu; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_lhu = exe_stage_lsu_stQueue_io_deq_bits_fun_lhu; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_lwu = exe_stage_lsu_stQueue_io_deq_bits_fun_lwu; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_sb = exe_stage_lsu_stQueue_io_deq_bits_fun_sb; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_sh = exe_stage_lsu_stQueue_io_deq_bits_fun_sh; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_sw = exe_stage_lsu_stQueue_io_deq_bits_fun_sw; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_sd = exe_stage_lsu_stQueue_io_deq_bits_fun_sd; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_lr_w = exe_stage_lsu_stQueue_io_deq_bits_fun_lr_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_sc_w = exe_stage_lsu_stQueue_io_deq_bits_fun_sc_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoswap_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amoswap_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoadd_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amoadd_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoxor_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amoxor_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoand_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amoand_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoor_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amoor_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomin_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amomin_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomax_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amomax_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amominu_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amominu_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomaxu_w = exe_stage_lsu_stQueue_io_deq_bits_fun_amomaxu_w; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_lr_d = exe_stage_lsu_stQueue_io_deq_bits_fun_lr_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_sc_d = exe_stage_lsu_stQueue_io_deq_bits_fun_sc_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoswap_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amoswap_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoadd_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amoadd_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoxor_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amoxor_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoand_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amoand_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amoor_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amoor_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomin_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amomin_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomax_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amomax_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amominu_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amominu_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_amomaxu_d = exe_stage_lsu_stQueue_io_deq_bits_fun_amomaxu_d; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_flw = exe_stage_lsu_stQueue_io_deq_bits_fun_flw; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_fsw = exe_stage_lsu_stQueue_io_deq_bits_fun_fsw; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_fld = exe_stage_lsu_stQueue_io_deq_bits_fun_fld; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_fun_fsd = exe_stage_lsu_stQueue_io_deq_bits_fun_fsd; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_param_rd0 = exe_stage_lsu_stQueue_io_deq_bits_param_rd0; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op1 = exe_stage_lsu_stQueue_io_deq_bits_param_dat_op1; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op2 = exe_stage_lsu_stQueue_io_deq_bits_param_dat_op2; // @[Lsu.scala 215:19]
  assign exe_stage_lsu_ls_arb_io_out_ready = exe_stage_lsu__T_36 ? exe_stage_lsu_cache_0_io_enq_ready :
    exe_stage_lsu__GEN_229; // @[Lsu.scala 246:23 249:26]
  assign exe_stage_lsu_system_clock = exe_stage_lsu_clock;
  assign exe_stage_lsu_system_reset = exe_stage_lsu_reset;
  assign exe_stage_lsu_system_io_enq_valid = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_valid; // @[Lsu.scala 237:23 238:26 242:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_lb = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_lb; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_lh = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_lh; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_lw = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_lw; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_ld = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_ld; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_lbu = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_lbu; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_lhu = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_lhu; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_lwu = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_lwu; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_sb = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_sb; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_sh = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_sh; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_sw = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_sw; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_sd = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_sd; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_lr_w = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_lr_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_sc_w = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_sc_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoswap_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoadd_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoxor_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoand_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoor_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amomin_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amomax_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amominu_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amomaxu_w = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_w; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_lr_d = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_lr_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_sc_d = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_sc_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoswap_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoadd_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoxor_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoand_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amoor_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amomin_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amomax_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amominu_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_amomaxu_d = exe_stage_lsu__T_35 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_d; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_flw = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_flw; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_fsw = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_fsw; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_fld = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_fld; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_enq_bits_fun_fsd = exe_stage_lsu__T_35 & exe_stage_lsu_ls_arb_io_out_bits_fun_fsd; // @[Lsu.scala 237:23 239:26 243:26]
  assign exe_stage_lsu_system_io_deq_ready = exe_stage_lsu_lu_wb_arb_io_in_1_ready |
    exe_stage_lsu__system_io_deq_ready_T; // @[Lsu.scala 427:52]
  assign exe_stage_lsu_system_io_getPut_ready = exe_stage_lsu_io_system_getPut_ready; // @[Lsu.scala 391:26]
  assign exe_stage_lsu_system_io_access_valid = exe_stage_lsu_io_system_access_valid; // @[Lsu.scala 392:26]
  assign exe_stage_lsu_system_io_access_bits_opcode = exe_stage_lsu_io_system_access_bits_opcode; // @[Lsu.scala 393:26]
  assign exe_stage_lsu_system_io_access_bits_data = exe_stage_lsu_io_system_access_bits_data; // @[Lsu.scala 393:26]
  assign exe_stage_lsu_periph_clock = exe_stage_lsu_clock;
  assign exe_stage_lsu_periph_reset = exe_stage_lsu_reset;
  assign exe_stage_lsu_periph_io_enq_valid = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_valid; // @[Lsu.scala 228:23 229:26 233:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_lb = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_lb; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_lh = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_lh; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_lw = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_lw; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_ld = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_ld; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_lbu = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_lbu; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_lhu = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_lhu; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_lwu = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_lwu; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_sb = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_sb; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_sh = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_sh; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_sw = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_sw; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_sd = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_sd; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_lr_w = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_lr_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_sc_w = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_sc_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoswap_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoadd_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoxor_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoand_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoor_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amomin_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amomax_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amominu_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amomaxu_w = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_w; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_lr_d = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_lr_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_sc_d = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_sc_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoswap_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoadd_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoxor_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoand_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amoor_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amomin_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amomax_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amominu_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_amomaxu_d = exe_stage_lsu__T_34 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_d; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_flw = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_flw; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_fsw = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_fsw; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_fld = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_fld; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_enq_bits_fun_fsd = exe_stage_lsu__T_34 & exe_stage_lsu_ls_arb_io_out_bits_fun_fsd; // @[Lsu.scala 228:23 230:26 234:26]
  assign exe_stage_lsu_periph_io_deq_ready = exe_stage_lsu_lu_wb_arb_io_in_2_ready |
    exe_stage_lsu__periph_io_deq_ready_T; // @[Lsu.scala 432:54]
  assign exe_stage_lsu_periph_io_getPut_ready = exe_stage_lsu_io_periph_getPut_ready; // @[Lsu.scala 402:26]
  assign exe_stage_lsu_periph_io_access_valid = exe_stage_lsu_io_periph_access_valid; // @[Lsu.scala 403:26]
  assign exe_stage_lsu_periph_io_access_bits_opcode = exe_stage_lsu_io_periph_access_bits_opcode; // @[Lsu.scala 404:26]
  assign exe_stage_lsu_periph_io_access_bits_data = exe_stage_lsu_io_periph_access_bits_data; // @[Lsu.scala 404:26]
  assign exe_stage_lsu_cache_0_clock = exe_stage_lsu_clock;
  assign exe_stage_lsu_cache_0_reset = exe_stage_lsu_reset;
  assign exe_stage_lsu_cache_0_io_enq_valid = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_valid; // @[Lsu.scala 246:23 247:26 251:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_paddr = exe_stage_lsu__GEN_272[31:0]; // @[Util.scala 81:19 84:15]
  assign exe_stage_lsu_cache_0_io_enq_bits_wdata = exe_stage_lsu__CacheMuxBits_res_wdata_T_9 ?
    exe_stage_lsu_CacheMuxBits_res_wdata_align_data : exe_stage_lsu_CacheMuxBits_res_wdata_res; // @[Util.scala 85:21]
  assign exe_stage_lsu_cache_0_io_enq_bits_wstrb = exe_stage_lsu__CacheMuxBits_res_wdata_T_9 ?
    exe_stage_lsu_CacheMuxBits_res_wstrb_align_strb : exe_stage_lsu_CacheMuxBits_res_wstrb_wstrb; // @[Util.scala 86:21]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_lb = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lb; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_lh = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lh; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_lw = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lw; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_ld = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_ld; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_lbu = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lbu; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_lhu = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lhu; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_lwu = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lwu; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_sb = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sb; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_sh = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sh; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_sw = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sw; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_sd = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sd; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_lr_w = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lr_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_sc_w = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sc_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoswap_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoadd_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoxor_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoand_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoor_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amomin_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amomax_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amominu_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amomaxu_w = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_w; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_lr_d = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_lr_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_sc_d = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_sc_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoswap_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoswap_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoadd_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoadd_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoxor_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoxor_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoand_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoand_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amoor_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amoor_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amomin_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomin_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amomax_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomax_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amominu_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amominu_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_amomaxu_d = exe_stage_lsu__T_36 &
    exe_stage_lsu_ls_arb_io_out_bits_fun_amomaxu_d; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_flw = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_flw; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_fsw = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_fsw; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_fld = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_fld; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_fun_fsd = exe_stage_lsu__T_36 & exe_stage_lsu_ls_arb_io_out_bits_fun_fsd; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_enq_bits_rd_rd0 = exe_stage_lsu__T_36 ? exe_stage_lsu_ls_arb_io_out_bits_param_rd0 : 6'h0
    ; // @[Lsu.scala 246:23 248:26 252:26]
  assign exe_stage_lsu_cache_0_io_deq_ready = exe_stage_lsu_lu_wb_arb_io_in_0_ready |
    exe_stage_lsu__cache_0_io_deq_ready_T; // @[Lsu.scala 421:55]
  assign exe_stage_lsu_cache_0_io_flush = exe_stage_lsu_io_flush; // @[Lsu.scala 382:23]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_ready = exe_stage_lsu_acquireArb_io_in_0_ready; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grant_valid = exe_stage_lsu__T_38 &
    exe_stage_lsu_io_missUnit_dcache_grant_valid; // @[Lsu.scala 307:64 308:47 292:54]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_opcode = exe_stage_lsu__T_38 ?
    exe_stage_lsu_io_missUnit_dcache_grant_bits_opcode : 3'h0; // @[Lsu.scala 307:64 308:47 293:54]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_size = exe_stage_lsu__T_38 ?
    exe_stage_lsu_io_missUnit_dcache_grant_bits_size : 3'h0; // @[Lsu.scala 307:64 308:47 293:54]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_source = exe_stage_lsu__T_38 &
    exe_stage_lsu_io_missUnit_dcache_grant_bits_source; // @[Lsu.scala 307:64 308:47 293:54]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_sink = exe_stage_lsu__T_38 ?
    exe_stage_lsu_io_missUnit_dcache_grant_bits_sink : 5'h0; // @[Lsu.scala 307:64 308:47 293:54]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grant_bits_data = exe_stage_lsu__T_38 ?
    exe_stage_lsu_io_missUnit_dcache_grant_bits_data : 64'h0; // @[Lsu.scala 307:64 308:47 293:54]
  assign exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_ready = exe_stage_lsu_grantAckArb_io_in_0_ready; // @[Lsu.scala 311:28]
  assign exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_valid = exe_stage_lsu_io_probeUnit_dcache_probe_valid; // @[Lsu.scala 313:120 314:48 295:54]
  assign exe_stage_lsu_cache_0_io_probeUnit_dcache_probe_bits_address =
    exe_stage_lsu_io_probeUnit_dcache_probe_bits_address; // @[Lsu.scala 313:120 314:48 296:54]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_ready = exe_stage_lsu__T_42 ?
    exe_stage_lsu_releaseArb_io_in_0_ready : exe_stage_lsu__GEN_366; // @[Lsu.scala 332:29 334:64]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_valid = exe_stage_lsu__T_40 &
    exe_stage_lsu_io_writeBackUnit_dcache_grant_valid; // @[Lsu.scala 317:69 318:52 298:58]
  assign exe_stage_lsu_cache_0_io_writeBackUnit_dcache_grant_bits_source = exe_stage_lsu__T_40 &
    exe_stage_lsu_io_writeBackUnit_dcache_grant_bits_source; // @[Lsu.scala 317:69 318:52 299:58]
  assign exe_stage_lsu_lu_wb_arb_io_in_0_valid = exe_stage_lsu_cache_0_io_deq_valid &
    exe_stage_lsu_cache_0_io_deq_bits_is_load_amo; // @[Lsu.scala 419:55]
  assign exe_stage_lsu_lu_wb_arb_io_in_0_bits_wb_rd0 = exe_stage_lsu_lu_wb_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_io_deq_bits_wb_rd0 : 6'h0; // @[Lsu.scala 420:35]
  assign exe_stage_lsu_lu_wb_arb_io_in_0_bits_wb_res = exe_stage_lsu_lu_wb_arb_io_in_0_valid ?
    exe_stage_lsu_cache_0_io_deq_bits_wb_res : 64'h0; // @[Lsu.scala 420:35]
  assign exe_stage_lsu_lu_wb_arb_io_in_0_bits_is_flw = exe_stage_lsu_lu_wb_arb_io_in_0_valid &
    exe_stage_lsu_cache_0_io_deq_bits_is_flw; // @[Lsu.scala 420:35]
  assign exe_stage_lsu_lu_wb_arb_io_in_0_bits_is_fld = exe_stage_lsu_lu_wb_arb_io_in_0_valid &
    exe_stage_lsu_cache_0_io_deq_bits_is_fld; // @[Lsu.scala 420:35]
  assign exe_stage_lsu_lu_wb_arb_io_in_1_valid = exe_stage_lsu_system_io_deq_valid &
    exe_stage_lsu_system_io_deq_bits_is_load_amo; // @[Lsu.scala 425:52]
  assign exe_stage_lsu_lu_wb_arb_io_in_1_bits_wb_rd0 = exe_stage_lsu_lu_wb_arb_io_in_1_valid ?
    exe_stage_lsu_system_io_deq_bits_wb_rd0 : 6'h0; // @[Lsu.scala 426:34]
  assign exe_stage_lsu_lu_wb_arb_io_in_1_bits_wb_res = exe_stage_lsu_lu_wb_arb_io_in_1_valid ?
    exe_stage_lsu_system_io_deq_bits_wb_res : 64'h0; // @[Lsu.scala 426:34]
  assign exe_stage_lsu_lu_wb_arb_io_in_1_bits_is_flw = exe_stage_lsu_lu_wb_arb_io_in_1_valid &
    exe_stage_lsu_system_io_deq_bits_is_flw; // @[Lsu.scala 426:34]
  assign exe_stage_lsu_lu_wb_arb_io_in_1_bits_is_fld = exe_stage_lsu_lu_wb_arb_io_in_1_valid &
    exe_stage_lsu_system_io_deq_bits_is_fld; // @[Lsu.scala 426:34]
  assign exe_stage_lsu_lu_wb_arb_io_in_2_valid = exe_stage_lsu_periph_io_deq_valid &
    exe_stage_lsu_periph_io_deq_bits_is_load_amo; // @[Lsu.scala 430:54]
  assign exe_stage_lsu_lu_wb_arb_io_in_2_bits_wb_rd0 = exe_stage_lsu_lu_wb_arb_io_in_2_valid ?
    exe_stage_lsu_periph_io_deq_bits_wb_rd0 : 6'h0; // @[Lsu.scala 431:36]
  assign exe_stage_lsu_lu_wb_arb_io_in_2_bits_wb_res = exe_stage_lsu_lu_wb_arb_io_in_2_valid ?
    exe_stage_lsu_periph_io_deq_bits_wb_res : 64'h0; // @[Lsu.scala 431:36]
  assign exe_stage_lsu_lu_wb_arb_io_in_2_bits_is_flw = exe_stage_lsu_lu_wb_arb_io_in_2_valid &
    exe_stage_lsu_periph_io_deq_bits_is_flw; // @[Lsu.scala 431:36]
  assign exe_stage_lsu_lu_wb_arb_io_in_2_bits_is_fld = exe_stage_lsu_lu_wb_arb_io_in_2_valid &
    exe_stage_lsu_periph_io_deq_bits_is_fld; // @[Lsu.scala 431:36]
  assign exe_stage_lsu_lu_wb_arb_io_out_ready = exe_stage_lsu__lu_wb_arb_io_out_ready_T | exe_stage_lsu_trans_kill; // @[Lsu.scala 454:82]
  assign exe_stage_lsu_lu_wb_fifo_clock = exe_stage_lsu_clock;
  assign exe_stage_lsu_lu_wb_fifo_reset = exe_stage_lsu_reset | exe_stage_lsu_io_flush; // @[Lsu.scala 440:36]
  assign exe_stage_lsu_lu_wb_fifo_io_enq_valid = exe_stage_lsu__lu_wb_fifo_io_enq_valid_T_2 &
    exe_stage_lsu__lu_wb_fifo_io_enq_valid_T_3; // @[Lsu.scala 437:84]
  assign exe_stage_lsu_lu_wb_fifo_io_enq_bits_rd0 = exe_stage_lsu_lu_wb_arb_io_out_bits_wb_rd0; // @[Lsu.scala 438:30]
  assign exe_stage_lsu_lu_wb_fifo_io_enq_bits_res = exe_stage_lsu_lu_wb_arb_io_out_bits_wb_res; // @[Lsu.scala 439:30]
  assign exe_stage_lsu_lu_wb_fifo_io_deq_ready = exe_stage_lsu_rtn_arb_io_in_1_ready; // @[Lsu.scala 475:20]
  assign exe_stage_lsu_flu_wb_fifo_clock = exe_stage_lsu_clock;
  assign exe_stage_lsu_flu_wb_fifo_reset = exe_stage_lsu_reset | exe_stage_lsu_io_flush; // @[Lsu.scala 451:37]
  assign exe_stage_lsu_flu_wb_fifo_io_enq_valid = exe_stage_lsu__flu_wb_fifo_io_enq_valid_T_1 &
    exe_stage_lsu__lu_wb_fifo_io_enq_valid_T_3; // @[Lsu.scala 443:85]
  assign exe_stage_lsu_flu_wb_fifo_io_deq_ready = exe_stage_lsu_io_lsu_exe_fwb_ready; // @[Lsu.scala 450:22]
  assign exe_stage_lsu_su_wb_fifo_clock = exe_stage_lsu_clock;
  assign exe_stage_lsu_su_wb_fifo_reset = exe_stage_lsu_reset | exe_stage_lsu_io_flush; // @[Lsu.scala 460:36]
  assign exe_stage_lsu_su_wb_fifo_io_enq_valid = exe_stage_lsu__opStIO_ready_T & exe_stage_lsu__GEN_46; // @[Decoupled.scala 52:35]
  assign exe_stage_lsu_su_wb_fifo_io_enq_bits_rd0 = exe_stage_lsu__T_14 ? exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0 : 6'h0
    ; // @[Lsu.scala 171:38 173:23 177:18]
  assign exe_stage_lsu_su_wb_fifo_io_deq_ready = exe_stage_lsu_rtn_arb_io_in_0_ready; // @[Lsu.scala 474:20]
  assign exe_stage_lsu_fe_wb_fifo_clock = exe_stage_lsu_clock;
  assign exe_stage_lsu_fe_wb_fifo_reset = exe_stage_lsu_reset | exe_stage_lsu_io_flush; // @[Lsu.scala 470:36]
  assign exe_stage_lsu_fe_wb_fifo_io_enq_valid = exe_stage_lsu__fe_wb_fifo_io_enq_valid_T_2 &
    exe_stage_lsu_io_lsu_iss_exe_valid; // @[Lsu.scala 467:74]
  assign exe_stage_lsu_fe_wb_fifo_io_enq_bits_rd0 = exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0; // @[Lsu.scala 468:30]
  assign exe_stage_lsu_fe_wb_fifo_io_deq_ready = exe_stage_lsu_rtn_arb_io_in_2_ready; // @[Lsu.scala 476:20]
  assign exe_stage_lsu_rtn_arb_io_in_0_valid = exe_stage_lsu_su_wb_fifo_io_deq_valid; // @[Lsu.scala 474:20]
  assign exe_stage_lsu_rtn_arb_io_in_0_bits_rd0 = exe_stage_lsu_su_wb_fifo_io_deq_bits_rd0; // @[Lsu.scala 474:20]
  assign exe_stage_lsu_rtn_arb_io_in_0_bits_res = exe_stage_lsu_su_wb_fifo_io_deq_bits_res; // @[Lsu.scala 474:20]
  assign exe_stage_lsu_rtn_arb_io_in_1_valid = exe_stage_lsu_lu_wb_fifo_io_deq_valid; // @[Lsu.scala 475:20]
  assign exe_stage_lsu_rtn_arb_io_in_1_bits_rd0 = exe_stage_lsu_lu_wb_fifo_io_deq_bits_rd0; // @[Lsu.scala 475:20]
  assign exe_stage_lsu_rtn_arb_io_in_1_bits_res = exe_stage_lsu_lu_wb_fifo_io_deq_bits_res; // @[Lsu.scala 475:20]
  assign exe_stage_lsu_rtn_arb_io_in_2_valid = exe_stage_lsu_fe_wb_fifo_io_deq_valid; // @[Lsu.scala 476:20]
  assign exe_stage_lsu_rtn_arb_io_in_2_bits_rd0 = exe_stage_lsu_fe_wb_fifo_io_deq_bits_rd0; // @[Lsu.scala 476:20]
  assign exe_stage_lsu_rtn_arb_io_in_2_bits_res = exe_stage_lsu_fe_wb_fifo_io_deq_bits_res; // @[Lsu.scala 476:20]
  assign exe_stage_lsu_rtn_arb_io_out_ready = exe_stage_lsu_io_lsu_exe_iwb_ready; // @[Lsu.scala 477:18]
  assign exe_stage_lsu_acquireArb_io_in_0_valid = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_valid; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_in_0_bits_opcode = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_opcode; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_in_0_bits_param = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_param; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_in_0_bits_size = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_size; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_in_0_bits_source = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_source; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_in_0_bits_address = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_address; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_in_0_bits_mask = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_mask; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_in_0_bits_data = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_data; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_in_0_bits_corrupt = exe_stage_lsu_cache_0_io_missUnit_dcache_acquire_bits_corrupt; // @[Lsu.scala 305:27]
  assign exe_stage_lsu_acquireArb_io_out_ready = exe_stage_lsu_io_missUnit_dcache_acquire_ready; // @[Lsu.scala 302:37]
  assign exe_stage_lsu_grantAckArb_io_in_0_valid = exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_valid; // @[Lsu.scala 311:28]
  assign exe_stage_lsu_grantAckArb_io_in_0_bits_sink = exe_stage_lsu_cache_0_io_missUnit_dcache_grantAck_bits_sink; // @[Lsu.scala 311:28]
  assign exe_stage_lsu_grantAckArb_io_out_ready = exe_stage_lsu_io_missUnit_dcache_grantAck_ready; // @[Lsu.scala 303:37]
  assign exe_stage_lsu_releaseArb_io_in_0_valid = exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_valid; // @[Lsu.scala 332:29]
  assign exe_stage_lsu_releaseArb_io_in_0_bits_opcode =
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_opcode; // @[Lsu.scala 332:29]
  assign exe_stage_lsu_releaseArb_io_in_0_bits_param = exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_param; // @[Lsu.scala 332:29]
  assign exe_stage_lsu_releaseArb_io_in_0_bits_size = exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_size; // @[Lsu.scala 332:29]
  assign exe_stage_lsu_releaseArb_io_in_0_bits_source =
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_source; // @[Lsu.scala 332:29]
  assign exe_stage_lsu_releaseArb_io_in_0_bits_address =
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_address; // @[Lsu.scala 332:29]
  assign exe_stage_lsu_releaseArb_io_in_0_bits_data = exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_data; // @[Lsu.scala 332:29]
  assign exe_stage_lsu_releaseArb_io_in_0_bits_corrupt =
    exe_stage_lsu_cache_0_io_writeBackUnit_dcache_release_bits_corrupt; // @[Lsu.scala 332:29]
  assign exe_stage_lsu_releaseArb_io_out_ready = exe_stage_lsu__T_42 &
    exe_stage_lsu_io_writeBackUnit_dcache_release_ready; // @[Lsu.scala 334:64 335:45 337:33]
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data =
    exe_stage_csr_csr_exe_iwb_fifo_ram_rd0[exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_data = exe_stage_csr_csr_exe_iwb_fifo_io_enq_bits_rd0;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_mask = 1'h1;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_en = exe_stage_csr_csr_exe_iwb_fifo_io_enq_ready &
    exe_stage_csr_csr_exe_iwb_fifo_io_enq_valid;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data =
    exe_stage_csr_csr_exe_iwb_fifo_ram_res[exe_stage_csr_csr_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_data = exe_stage_csr_csr_exe_iwb_fifo_io_enq_bits_res;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_mask = 1'h1;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_en = exe_stage_csr_csr_exe_iwb_fifo_io_enq_ready &
    exe_stage_csr_csr_exe_iwb_fifo_io_enq_valid;
  assign exe_stage_csr_csr_exe_iwb_fifo_io_enq_ready = exe_stage_csr_csr_exe_iwb_fifo_io_deq_ready |
    exe_stage_csr_csr_exe_iwb_fifo__empty_T; // @[Decoupled.scala 305:16 325:{24,39}]
  assign exe_stage_csr_csr_exe_iwb_fifo_io_deq_valid = ~exe_stage_csr_csr_exe_iwb_fifo__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_csr_csr_exe_iwb_fifo_io_deq_bits_rd0 = exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_csr_csr_exe_iwb_fifo_io_deq_bits_res = exe_stage_csr_csr_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_csr_csr_op_fifo_ram_addr_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_addr_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_addr_io_deq_bits_MPORT_data =
    exe_stage_csr_csr_op_fifo_ram_addr[exe_stage_csr_csr_op_fifo_ram_addr_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_csr_csr_op_fifo_ram_addr_MPORT_data = exe_stage_csr_csr_op_fifo_io_enq_bits_addr;
  assign exe_stage_csr_csr_op_fifo_ram_addr_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_addr_MPORT_mask = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_addr_MPORT_en = exe_stage_csr_csr_op_fifo_io_enq_ready &
    exe_stage_csr_csr_op_fifo_io_enq_valid;
  assign exe_stage_csr_csr_op_fifo_ram_dat_i_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_dat_i_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_dat_i_io_deq_bits_MPORT_data =
    exe_stage_csr_csr_op_fifo_ram_dat_i[exe_stage_csr_csr_op_fifo_ram_dat_i_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_data = exe_stage_csr_csr_op_fifo_io_enq_bits_dat_i;
  assign exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_mask = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_en = exe_stage_csr_csr_op_fifo_io_enq_ready &
    exe_stage_csr_csr_op_fifo_io_enq_valid;
  assign exe_stage_csr_csr_op_fifo_ram_op_rw_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_op_rw_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_op_rw_io_deq_bits_MPORT_data =
    exe_stage_csr_csr_op_fifo_ram_op_rw[exe_stage_csr_csr_op_fifo_ram_op_rw_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_data = exe_stage_csr_csr_op_fifo_io_enq_bits_op_rw;
  assign exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_mask = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_en = exe_stage_csr_csr_op_fifo_io_enq_ready &
    exe_stage_csr_csr_op_fifo_io_enq_valid;
  assign exe_stage_csr_csr_op_fifo_ram_op_rs_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_op_rs_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_op_rs_io_deq_bits_MPORT_data =
    exe_stage_csr_csr_op_fifo_ram_op_rs[exe_stage_csr_csr_op_fifo_ram_op_rs_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_data = exe_stage_csr_csr_op_fifo_io_enq_bits_op_rs;
  assign exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_mask = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_en = exe_stage_csr_csr_op_fifo_io_enq_ready &
    exe_stage_csr_csr_op_fifo_io_enq_valid;
  assign exe_stage_csr_csr_op_fifo_ram_op_rc_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_op_rc_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_op_rc_io_deq_bits_MPORT_data =
    exe_stage_csr_csr_op_fifo_ram_op_rc[exe_stage_csr_csr_op_fifo_ram_op_rc_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_data = exe_stage_csr_csr_op_fifo_io_enq_bits_op_rc;
  assign exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_addr = 1'h0;
  assign exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_mask = 1'h1;
  assign exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_en = exe_stage_csr_csr_op_fifo_io_enq_ready &
    exe_stage_csr_csr_op_fifo_io_enq_valid;
  assign exe_stage_csr_csr_op_fifo_io_enq_ready = ~exe_stage_csr_csr_op_fifo_maybe_full; // @[Decoupled.scala 305:19]
  assign exe_stage_csr_csr_op_fifo_io_deq_valid = ~exe_stage_csr_csr_op_fifo__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_csr_csr_op_fifo_io_deq_bits_addr = exe_stage_csr_csr_op_fifo_ram_addr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_csr_csr_op_fifo_io_deq_bits_dat_i = exe_stage_csr_csr_op_fifo_ram_dat_i_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_csr_csr_op_fifo_io_deq_bits_op_rw = exe_stage_csr_csr_op_fifo_ram_op_rw_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_csr_csr_op_fifo_io_deq_bits_op_rs = exe_stage_csr_csr_op_fifo_ram_op_rs_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_csr_csr_op_fifo_io_deq_bits_op_rc = exe_stage_csr_csr_op_fifo_ram_op_rc_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_csr_io_csr_iss_exe_ready = exe_stage_csr_csr_exe_iwb_fifo_io_enq_ready &
    exe_stage_csr_csr_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_csr_io_csr_exe_iwb_valid = exe_stage_csr_csr_exe_iwb_fifo_io_deq_valid; // @[Csr.scala 44:18]
  assign exe_stage_csr_io_csr_exe_iwb_bits_rd0 = exe_stage_csr_csr_exe_iwb_fifo_io_deq_bits_rd0; // @[Csr.scala 44:18]
  assign exe_stage_csr_io_csr_exe_iwb_bits_res = exe_stage_csr_csr_exe_iwb_fifo_io_deq_bits_res; // @[Csr.scala 44:18]
  assign exe_stage_csr_io_csr_addr_valid = exe_stage_csr_io_csr_iss_exe_valid; // @[Csr.scala 69:21]
  assign exe_stage_csr_io_csr_addr_bits = exe_stage_csr_io_csr_iss_exe_bits_param_dat_op2[11:0]; // @[Csr.scala 68:21]
  assign exe_stage_csr_io_csr_cmm_op_valid = exe_stage_csr_csr_op_fifo_io_deq_valid; // @[Csr.scala 48:17]
  assign exe_stage_csr_io_csr_cmm_op_bits_addr = exe_stage_csr_csr_op_fifo_io_deq_bits_addr; // @[Csr.scala 48:17]
  assign exe_stage_csr_io_csr_cmm_op_bits_dat_i = exe_stage_csr_csr_op_fifo_io_deq_bits_dat_i; // @[Csr.scala 48:17]
  assign exe_stage_csr_io_csr_cmm_op_bits_op_rw = exe_stage_csr_csr_op_fifo_io_deq_bits_op_rw; // @[Csr.scala 48:17]
  assign exe_stage_csr_io_csr_cmm_op_bits_op_rs = exe_stage_csr_csr_op_fifo_io_deq_bits_op_rs; // @[Csr.scala 48:17]
  assign exe_stage_csr_io_csr_cmm_op_bits_op_rc = exe_stage_csr_csr_op_fifo_io_deq_bits_op_rc; // @[Csr.scala 48:17]
  assign exe_stage_csr_csr_exe_iwb_fifo_clock = exe_stage_csr_clock;
  assign exe_stage_csr_csr_exe_iwb_fifo_reset = exe_stage_csr_reset | exe_stage_csr_io_flush; // @[Csr.scala 45:42]
  assign exe_stage_csr_csr_exe_iwb_fifo_io_enq_valid = exe_stage_csr__csr_exe_iwb_fifo_io_enq_valid_T &
    exe_stage_csr_io_csr_data_valid; // @[Csr.scala 74:84]
  assign exe_stage_csr_csr_exe_iwb_fifo_io_enq_bits_rd0 = exe_stage_csr_io_csr_iss_exe_bits_param_rd0; // @[Csr.scala 76:36]
  assign exe_stage_csr_csr_exe_iwb_fifo_io_enq_bits_res = exe_stage_csr_io_csr_data_bits; // @[Csr.scala 75:36]
  assign exe_stage_csr_csr_exe_iwb_fifo_io_deq_ready = exe_stage_csr_io_csr_exe_iwb_ready; // @[Csr.scala 44:18]
  assign exe_stage_csr_csr_op_fifo_clock = exe_stage_csr_clock;
  assign exe_stage_csr_csr_op_fifo_reset = exe_stage_csr_reset | exe_stage_csr_io_flush; // @[Csr.scala 49:37]
  assign exe_stage_csr_csr_op_fifo_io_enq_valid = exe_stage_csr_csr_exe_iwb_fifo_io_enq_ready &
    exe_stage_csr_csr_exe_iwb_fifo_io_enq_valid; // @[Decoupled.scala 52:35]
  assign exe_stage_csr_csr_op_fifo_io_enq_bits_addr = exe_stage_csr_io_csr_iss_exe_bits_param_dat_op2[11:0]; // @[Csr.scala 62:32]
  assign exe_stage_csr_csr_op_fifo_io_enq_bits_dat_i = exe_stage_csr_io_csr_iss_exe_bits_param_dat_op1; // @[Csr.scala 63:33]
  assign exe_stage_csr_csr_op_fifo_io_enq_bits_op_rw = exe_stage_csr_io_csr_iss_exe_bits_fun_rw &
    exe_stage_csr__csr_op_fifo_io_enq_bits_op_rw_T; // @[Csr.scala 64:39]
  assign exe_stage_csr_csr_op_fifo_io_enq_bits_op_rs = exe_stage_csr_io_csr_iss_exe_bits_fun_rs &
    exe_stage_csr__csr_op_fifo_io_enq_bits_op_rw_T; // @[Csr.scala 65:39]
  assign exe_stage_csr_csr_op_fifo_io_enq_bits_op_rc = exe_stage_csr_io_csr_iss_exe_bits_fun_rc &
    exe_stage_csr__csr_op_fifo_io_enq_bits_op_rw_T; // @[Csr.scala 66:39]
  assign exe_stage_csr_csr_op_fifo_io_deq_ready = exe_stage_csr_io_csr_cmm_op_ready; // @[Csr.scala 48:17]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data =
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0[exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_data = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_bits_rd0;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_addr = 1'h0;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_mask = 1'h1;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_en = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_ready &
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_valid;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_en = 1'h1;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr = 1'h0;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data =
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res[exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_data = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_bits_res;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_addr = 1'h0;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_mask = 1'h1;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_en = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_ready &
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_valid;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_ready = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_ready |
    exe_stage_mulDiv_0_mul_exe_iwb_fifo__empty_T; // @[Decoupled.scala 305:16 325:{24,39}]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_valid = ~exe_stage_mulDiv_0_mul_exe_iwb_fifo__empty_T; // @[Decoupled.scala 304:19]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_bits_rd0 =
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_bits_res =
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign exe_stage_mulDiv_0_multiplier_io_enq_ready = exe_stage_mulDiv_0_multiplier_io_deq_ready; // @[Mul.scala 418:10]
  assign exe_stage_mulDiv_0_multiplier_io_deq_valid = exe_stage_mulDiv_0_multiplier_io_enq_valid; // @[Mul.scala 418:10]
  assign exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mul = exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mul; // @[Mul.scala 418:10]
  assign exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulh = exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulh; // @[Mul.scala 418:10]
  assign exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulhsu = exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulhsu; // @[Mul.scala 418:10]
  assign exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulhu = exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulhu; // @[Mul.scala 418:10]
  assign exe_stage_mulDiv_0_multiplier_io_deq_bits_fun_mulw = exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulw; // @[Mul.scala 418:10]
  assign exe_stage_mulDiv_0_multiplier_io_deq_bits_param_rd0 = exe_stage_mulDiv_0_multiplier_io_enq_bits_param_rd0; // @[Mul.scala 418:10]
  assign exe_stage_mulDiv_0_multiplier_io_res = $signed(exe_stage_mulDiv_0_multiplier_io_op1) * $signed(
    exe_stage_mulDiv_0_multiplier_io_op2); // @[Mul.scala 419:45]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_ready = ~exe_stage_mulDiv_0_dividor_algDivider_isDivBusy; // @[Mul.scala 594:19]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_valid = exe_stage_mulDiv_0_dividor_algDivider_isDivBusy &
    exe_stage_mulDiv_0_dividor_algDivider__divFinish_T; // @[Mul.scala 626:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_div =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_div; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divu =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divu; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_rem =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_rem; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remu =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remu; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divw =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divw; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_divuw =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divuw; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remw =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remw; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_fun_remuw =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remuw; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_rd0 =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_rd0; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_dat_op1 =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_dat_op1; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_dat_op2 =
    exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_dat_op2; // @[Mul.scala 628:15]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_quo = exe_stage_mulDiv_0_dividor_algDivider_dividend[63:0]; // @[Mul.scala 629:21]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_rem = exe_stage_mulDiv_0_dividor_algDivider_dividend[127:64]; // @[Mul.scala 630:21]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_ready = exe_stage_mulDiv_0_dividor_divRtnArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_ready = exe_stage_mulDiv_0_dividor_divRtnArb_grant_1 &
    exe_stage_mulDiv_0_dividor_divRtnArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_out_valid = exe_stage_mulDiv_0_dividor_divRtnArb__io_out_valid_T |
    exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_out_bits_rd0 = exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_valid ?
    exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_bits_rd0 : exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_bits_rd0; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_out_bits_res = exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_valid ?
    exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_bits_res : exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_bits_res; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_mulDiv_0_dividor_io_enq_ready = exe_stage_mulDiv_0_dividor_divBypass ?
    exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_ready : exe_stage_mulDiv_0_dividor_algDivider_io_enq_ready; // @[Mul.scala 559:22]
  assign exe_stage_mulDiv_0_dividor_io_deq_valid = exe_stage_mulDiv_0_dividor_divRtnArb_io_out_valid; // @[Mul.scala 560:10]
  assign exe_stage_mulDiv_0_dividor_io_deq_bits_rd0 = exe_stage_mulDiv_0_dividor_divRtnArb_io_out_bits_rd0; // @[Mul.scala 560:10]
  assign exe_stage_mulDiv_0_dividor_io_deq_bits_res = exe_stage_mulDiv_0_dividor_divRtnArb_io_out_bits_res; // @[Mul.scala 560:10]
  assign exe_stage_mulDiv_0_dividor_algDivider_clock = exe_stage_mulDiv_0_dividor_clock;
  assign exe_stage_mulDiv_0_dividor_algDivider_reset = exe_stage_mulDiv_0_dividor_reset;
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_valid = exe_stage_mulDiv_0_dividor_io_enq_valid &
    exe_stage_mulDiv_0_dividor__algDivider_io_enq_valid_T; // @[Mul.scala 509:45]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_div = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_div; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divu = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divu; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_rem = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_rem; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remu = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remu; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divw = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divw; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divuw = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divuw; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remw = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remw; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remuw = exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remuw; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_rd0 = exe_stage_mulDiv_0_dividor_io_enq_bits_param_rd0; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_dat_op1 =
    exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_dat_op2 =
    exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2; // @[Mul.scala 510:29]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_deq_ready = exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_ready; // @[Mul.scala 557:28]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_op1 = exe_stage_mulDiv_0_dividor_isUsiPre ?
    exe_stage_mulDiv_0_dividor__dividend_load_T_1 : exe_stage_mulDiv_0_dividor__dividend_load_T_15; // @[Mul.scala 447:10]
  assign exe_stage_mulDiv_0_dividor_algDivider_io_flush = exe_stage_mulDiv_0_dividor_io_flush; // @[Mul.scala 515:25]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_valid = exe_stage_mulDiv_0_dividor_algDivider_io_deq_valid; // @[Mul.scala 554:28]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_bits_rd0 =
    exe_stage_mulDiv_0_dividor_algDivider_io_deq_bits_param_rd0; // @[Mul.scala 556:31]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_in_0_bits_res = exe_stage_mulDiv_0_dividor__divRes_T_33 |
    exe_stage_mulDiv_0_dividor__divRes_T_27; // @[Mux.scala 27:73]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_valid = exe_stage_mulDiv_0_dividor_io_enq_valid &
    exe_stage_mulDiv_0_dividor_divBypass; // @[Mul.scala 549:44]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_bits_rd0 = exe_stage_mulDiv_0_dividor_io_enq_bits_param_rd0; // @[Mul.scala 551:31]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_in_1_bits_res = exe_stage_mulDiv_0_dividor__byPassRes_T_13 |
    exe_stage_mulDiv_0_dividor__byPassRes_T_7; // @[Mux.scala 27:73]
  assign exe_stage_mulDiv_0_dividor_divRtnArb_io_out_ready = exe_stage_mulDiv_0_dividor_io_deq_ready; // @[Mul.scala 560:10]
  assign exe_stage_mulDiv_0_iwbArb_io_in_0_ready = exe_stage_mulDiv_0_iwbArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_mulDiv_0_iwbArb_io_in_1_ready = exe_stage_mulDiv_0_iwbArb_grant_1 &
    exe_stage_mulDiv_0_iwbArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign exe_stage_mulDiv_0_iwbArb_io_out_valid = exe_stage_mulDiv_0_iwbArb__io_out_valid_T |
    exe_stage_mulDiv_0_iwbArb_io_in_1_valid; // @[Arbiter.scala 147:31]
  assign exe_stage_mulDiv_0_iwbArb_io_out_bits_rd0 = exe_stage_mulDiv_0_iwbArb_io_in_0_valid ?
    exe_stage_mulDiv_0_iwbArb_io_in_0_bits_rd0 : exe_stage_mulDiv_0_iwbArb_io_in_1_bits_rd0; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_mulDiv_0_iwbArb_io_out_bits_res = exe_stage_mulDiv_0_iwbArb_io_in_0_valid ?
    exe_stage_mulDiv_0_iwbArb_io_in_0_bits_res : exe_stage_mulDiv_0_iwbArb_io_in_1_bits_res; // @[Arbiter.scala 136:15 138:26 140:19]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_ready = exe_stage_mulDiv_0__multiplier_io_enq_valid_T_3 ?
    exe_stage_mulDiv_0_multiplier_io_enq_ready : exe_stage_mulDiv_0_dividor_io_enq_ready; // @[Mul.scala 123:8]
  assign exe_stage_mulDiv_0_io_mul_exe_iwb_valid = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_valid; // @[Mul.scala 42:18]
  assign exe_stage_mulDiv_0_io_mul_exe_iwb_bits_rd0 = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_bits_rd0; // @[Mul.scala 42:18]
  assign exe_stage_mulDiv_0_io_mul_exe_iwb_bits_res = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_bits_res; // @[Mul.scala 42:18]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_clock = exe_stage_mulDiv_0_clock;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_reset = exe_stage_mulDiv_0_reset | exe_stage_mulDiv_0_io_flush; // @[Mul.scala 41:42]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_valid = exe_stage_mulDiv_0_iwbArb_io_out_valid; // @[Mul.scala 139:27]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_bits_rd0 = exe_stage_mulDiv_0_iwbArb_io_out_bits_rd0; // @[Mul.scala 139:27]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_bits_res = exe_stage_mulDiv_0_iwbArb_io_out_bits_res; // @[Mul.scala 139:27]
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_deq_ready = exe_stage_mulDiv_0_io_mul_exe_iwb_ready; // @[Mul.scala 42:18]
  assign exe_stage_mulDiv_0_multiplier_io_enq_valid = exe_stage_mulDiv_0_io_mul_iss_exe_valid &
    exe_stage_mulDiv_0__multiplier_io_enq_valid_T_3; // @[Mul.scala 84:51]
  assign exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mul = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mul; // @[Mul.scala 87:26]
  assign exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulh = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulh; // @[Mul.scala 87:26]
  assign exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulhsu = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulhsu; // @[Mul.scala 87:26]
  assign exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulhu = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulhu; // @[Mul.scala 87:26]
  assign exe_stage_mulDiv_0_multiplier_io_enq_bits_fun_mulw = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw; // @[Mul.scala 87:26]
  assign exe_stage_mulDiv_0_multiplier_io_enq_bits_param_rd0 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_rd0; // @[Mul.scala 87:26]
  assign exe_stage_mulDiv_0_multiplier_io_deq_ready = exe_stage_mulDiv_0_iwbArb_io_in_0_ready; // @[Mul.scala 130:27]
  assign exe_stage_mulDiv_0_multiplier_io_op1 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw ?
    exe_stage_mulDiv_0__mul_op1_T_3 : exe_stage_mulDiv_0__mul_op1_T_4; // @[Mul.scala 65:8]
  assign exe_stage_mulDiv_0_multiplier_io_op2 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw ?
    exe_stage_mulDiv_0__mul_op2_T_3 : exe_stage_mulDiv_0__mul_op2_T_4; // @[Mul.scala 72:8]
  assign exe_stage_mulDiv_0_dividor_clock = exe_stage_mulDiv_0_clock;
  assign exe_stage_mulDiv_0_dividor_reset = exe_stage_mulDiv_0_reset;
  assign exe_stage_mulDiv_0_dividor_io_enq_valid = exe_stage_mulDiv_0__dividor_io_enq_valid_T_6 &
    exe_stage_mulDiv_0_io_mul_iss_exe_valid; // @[Mul.scala 107:57]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_fun_div = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_div; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divu = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divu; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_fun_rem = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_rem; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remu = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remu; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divw = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divw; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_fun_divuw = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divuw; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remw = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remw; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_fun_remuw = exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remuw; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_param_rd0 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_rd0; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op1 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op1; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2 = exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op2; // @[Mul.scala 106:24]
  assign exe_stage_mulDiv_0_dividor_io_deq_ready = exe_stage_mulDiv_0_iwbArb_io_in_1_ready; // @[Mul.scala 135:19]
  assign exe_stage_mulDiv_0_dividor_io_flush = exe_stage_mulDiv_0_io_flush; // @[Mul.scala 109:20]
  assign exe_stage_mulDiv_0_iwbArb_io_in_0_valid = exe_stage_mulDiv_0_multiplier_io_deq_valid; // @[Mul.scala 131:25]
  assign exe_stage_mulDiv_0_iwbArb_io_in_0_bits_rd0 = exe_stage_mulDiv_0_multiplier_io_deq_bits_param_rd0; // @[Mul.scala 132:28]
  assign exe_stage_mulDiv_0_iwbArb_io_in_0_bits_res = exe_stage_mulDiv_0__mulRes_T_16 | exe_stage_mulDiv_0__mulRes_T_13; // @[Mux.scala 27:73]
  assign exe_stage_mulDiv_0_iwbArb_io_in_1_valid = exe_stage_mulDiv_0_dividor_io_deq_valid; // @[Mul.scala 135:19]
  assign exe_stage_mulDiv_0_iwbArb_io_in_1_bits_rd0 = exe_stage_mulDiv_0_dividor_io_deq_bits_rd0; // @[Mul.scala 135:19]
  assign exe_stage_mulDiv_0_iwbArb_io_in_1_bits_res = exe_stage_mulDiv_0_dividor_io_deq_bits_res; // @[Mul.scala 135:19]
  assign exe_stage_mulDiv_0_iwbArb_io_out_ready = exe_stage_mulDiv_0_mul_exe_iwb_fifo_io_enq_ready; // @[Mul.scala 139:27]
  assign exe_stage_fpu_0_io_fpu_exe_iwb_valid = 1'h0; // @[FAlu.scala 271:24]
  assign exe_stage_fpu_0_io_fpu_exe_iwb_bits_rd0 = 6'h0; // @[FAlu.scala 272:{39,39}]
  assign exe_stage_fpu_0_io_fpu_exe_iwb_bits_res = 65'h0; // @[FAlu.scala 272:{39,39}]
  assign exe_stage_fpu_0_io_fpu_exe_fwb_valid = 1'h0; // @[FAlu.scala 274:24]
  assign exe_stage_fpu_0_io_fcsr_cmm_op_0_valid = 1'h0; // @[FAlu.scala 278:29]
  assign exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_addr = 12'h0; // @[FAlu.scala 279:{44,44}]
  assign exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_dat_i = 64'h0; // @[FAlu.scala 279:{44,44}]
  assign exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rw = 1'h0; // @[FAlu.scala 279:{44,44}]
  assign exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rs = 1'h0; // @[FAlu.scala 279:{44,44}]
  assign exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rc = 1'h0; // @[FAlu.scala 279:{44,44}]
  assign exe_stage_io_alu_iss_exe_0_ready = exe_stage_alu_0_io_alu_iss_exe_ready; // @[Execute.scala 185:27]
  assign exe_stage_io_alu_exe_iwb_0_valid = exe_stage_alu_0_io_alu_exe_iwb_valid; // @[Execute.scala 186:27]
  assign exe_stage_io_alu_exe_iwb_0_bits_rd0 = exe_stage_alu_0_io_alu_exe_iwb_bits_rd0; // @[Execute.scala 186:27]
  assign exe_stage_io_alu_exe_iwb_0_bits_res = exe_stage_alu_0_io_alu_exe_iwb_bits_res; // @[Execute.scala 186:27]
  assign exe_stage_io_bru_iss_exe_ready = exe_stage_bru_io_bru_iss_exe_ready; // @[Execute.scala 191:22]
  assign exe_stage_io_bru_exe_iwb_valid = exe_stage_bru_io_bru_exe_iwb_valid; // @[Execute.scala 192:22]
  assign exe_stage_io_bru_exe_iwb_bits_rd0 = exe_stage_bru_io_bru_exe_iwb_bits_rd0; // @[Execute.scala 192:22]
  assign exe_stage_io_bru_exe_iwb_bits_res = exe_stage_bru_io_bru_exe_iwb_bits_res; // @[Execute.scala 192:22]
  assign exe_stage_io_csr_iss_exe_ready = exe_stage_csr_io_csr_iss_exe_ready; // @[Execute.scala 204:22]
  assign exe_stage_io_csr_exe_iwb_valid = exe_stage_csr_io_csr_exe_iwb_valid; // @[Execute.scala 205:22]
  assign exe_stage_io_csr_exe_iwb_bits_rd0 = exe_stage_csr_io_csr_exe_iwb_bits_rd0; // @[Execute.scala 205:22]
  assign exe_stage_io_csr_exe_iwb_bits_res = exe_stage_csr_io_csr_exe_iwb_bits_res; // @[Execute.scala 205:22]
  assign exe_stage_io_lsu_iss_exe_ready = exe_stage_lsu_io_lsu_iss_exe_ready; // @[Execute.scala 103:24]
  assign exe_stage_io_lsu_exe_iwb_valid = exe_stage_lsu_io_lsu_exe_iwb_valid; // @[Execute.scala 104:24]
  assign exe_stage_io_lsu_exe_iwb_bits_rd0 = exe_stage_lsu_io_lsu_exe_iwb_bits_rd0; // @[Execute.scala 104:24]
  assign exe_stage_io_lsu_exe_iwb_bits_res = exe_stage_lsu_io_lsu_exe_iwb_bits_res; // @[Execute.scala 104:24]
  assign exe_stage_io_lsu_exe_fwb_valid = exe_stage_lsu_io_lsu_exe_fwb_valid; // @[Execute.scala 105:24]
  assign exe_stage_io_mul_iss_exe_0_ready = exe_stage_mulDiv_0_io_mul_iss_exe_ready; // @[Execute.scala 212:30]
  assign exe_stage_io_mul_exe_iwb_0_valid = exe_stage_mulDiv_0_io_mul_exe_iwb_valid; // @[Execute.scala 213:30]
  assign exe_stage_io_mul_exe_iwb_0_bits_rd0 = exe_stage_mulDiv_0_io_mul_exe_iwb_bits_rd0; // @[Execute.scala 213:30]
  assign exe_stage_io_mul_exe_iwb_0_bits_res = exe_stage_mulDiv_0_io_mul_exe_iwb_bits_res; // @[Execute.scala 213:30]
  assign exe_stage_io_fpu_exe_iwb_0_valid = exe_stage_fpu_0_io_fpu_exe_iwb_valid; // @[Execute.scala 177:27]
  assign exe_stage_io_fpu_exe_iwb_0_bits_rd0 = exe_stage_fpu_0_io_fpu_exe_iwb_bits_rd0; // @[Execute.scala 177:27]
  assign exe_stage_io_fpu_exe_iwb_0_bits_res = exe_stage_fpu_0_io_fpu_exe_iwb_bits_res[63:0]; // @[Execute.scala 177:27]
  assign exe_stage_io_fpu_exe_fwb_0_valid = exe_stage_fpu_0_io_fpu_exe_fwb_valid; // @[Execute.scala 178:27]
  assign exe_stage_io_fcsr_cmm_op_0_valid = exe_stage_fpu_0_io_fcsr_cmm_op_0_valid; // @[Execute.scala 181:27]
  assign exe_stage_io_fcsr_cmm_op_0_bits_addr = exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_addr; // @[Execute.scala 181:27]
  assign exe_stage_io_fcsr_cmm_op_0_bits_dat_i = exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_dat_i; // @[Execute.scala 181:27]
  assign exe_stage_io_fcsr_cmm_op_0_bits_op_rw = exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rw; // @[Execute.scala 181:27]
  assign exe_stage_io_fcsr_cmm_op_0_bits_op_rs = exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rs; // @[Execute.scala 181:27]
  assign exe_stage_io_fcsr_cmm_op_0_bits_op_rc = exe_stage_fpu_0_io_fcsr_cmm_op_0_bits_op_rc; // @[Execute.scala 181:27]
  assign exe_stage_io_bftq_ready = exe_stage_bru_io_bftq_ready; // @[Execute.scala 195:15]
  assign exe_stage_io_jftq_ready = exe_stage_bru_io_jftq_ready; // @[Execute.scala 196:15]
  assign exe_stage_io_bctq_valid = exe_stage_bru_io_bctq_valid; // @[Execute.scala 198:11]
  assign exe_stage_io_bctq_bits_isPredictTaken = exe_stage_bru_io_bctq_bits_isPredictTaken; // @[Execute.scala 198:11]
  assign exe_stage_io_bctq_bits_isFinalTaken = exe_stage_bru_io_bctq_bits_isFinalTaken; // @[Execute.scala 198:11]
  assign exe_stage_io_bctq_bits_finalTarget = exe_stage_bru_io_bctq_bits_finalTarget; // @[Execute.scala 198:11]
  assign exe_stage_io_jctq_valid = exe_stage_bru_io_jctq_valid; // @[Execute.scala 199:11]
  assign exe_stage_io_jctq_bits_btbResp_target = exe_stage_bru_io_jctq_bits_btbResp_target; // @[Execute.scala 199:11]
  assign exe_stage_io_jctq_bits_rasResp_target = exe_stage_bru_io_jctq_bits_rasResp_target; // @[Execute.scala 199:11]
  assign exe_stage_io_jctq_bits_isRas = exe_stage_bru_io_jctq_bits_isRas; // @[Execute.scala 199:11]
  assign exe_stage_io_jctq_bits_finalTarget = exe_stage_bru_io_jctq_bits_finalTarget; // @[Execute.scala 199:11]
  assign exe_stage_io_bcmm_update_valid = exe_stage_bru_io_bcmm_update_valid; // @[Execute.scala 201:18]
  assign exe_stage_io_bcmm_update_bits_pc = exe_stage_bru_io_bcmm_update_bits_pc; // @[Execute.scala 201:18]
  assign exe_stage_io_bcmm_update_bits_bimResp_bim_p = exe_stage_bru_io_bcmm_update_bits_bimResp_bim_p; // @[Execute.scala 201:18]
  assign exe_stage_io_bcmm_update_bits_bimResp_bim_h = exe_stage_bru_io_bcmm_update_bits_bimResp_bim_h; // @[Execute.scala 201:18]
  assign exe_stage_io_bcmm_update_bits_isFinalTaken = exe_stage_bru_io_bcmm_update_bits_isFinalTaken; // @[Execute.scala 201:18]
  assign exe_stage_io_jcmm_update_valid = exe_stage_bru_io_jcmm_update_valid; // @[Execute.scala 202:18]
  assign exe_stage_io_jcmm_update_bits_pc = exe_stage_bru_io_jcmm_update_bits_pc; // @[Execute.scala 202:18]
  assign exe_stage_io_jcmm_update_bits_finalTarget = exe_stage_bru_io_jcmm_update_bits_finalTarget; // @[Execute.scala 202:18]
  assign exe_stage_io_csr_addr_valid = exe_stage_csr_io_csr_addr_valid; // @[Execute.scala 206:19]
  assign exe_stage_io_csr_addr_bits = exe_stage_csr_io_csr_addr_bits; // @[Execute.scala 206:19]
  assign exe_stage_io_csr_cmm_op_valid = exe_stage_csr_io_csr_cmm_op_valid; // @[Execute.scala 208:21]
  assign exe_stage_io_csr_cmm_op_bits_addr = exe_stage_csr_io_csr_cmm_op_bits_addr; // @[Execute.scala 208:21]
  assign exe_stage_io_csr_cmm_op_bits_dat_i = exe_stage_csr_io_csr_cmm_op_bits_dat_i; // @[Execute.scala 208:21]
  assign exe_stage_io_csr_cmm_op_bits_op_rw = exe_stage_csr_io_csr_cmm_op_bits_op_rw; // @[Execute.scala 208:21]
  assign exe_stage_io_csr_cmm_op_bits_op_rs = exe_stage_csr_io_csr_cmm_op_bits_op_rs; // @[Execute.scala 208:21]
  assign exe_stage_io_csr_cmm_op_bits_op_rc = exe_stage_csr_io_csr_cmm_op_bits_op_rc; // @[Execute.scala 208:21]
  assign exe_stage_io_lsu_mmu_valid = exe_stage_lsu_io_lsu_mmu_valid; // @[Execute.scala 107:20]
  assign exe_stage_io_lsu_mmu_bits_is_X = exe_stage_lsu_io_lsu_mmu_bits_is_X; // @[Execute.scala 107:20]
  assign exe_stage_io_lsu_mmu_bits_is_W = exe_stage_lsu_io_lsu_mmu_bits_is_W; // @[Execute.scala 107:20]
  assign exe_stage_io_lsu_mmu_bits_is_R = exe_stage_lsu_io_lsu_mmu_bits_is_R; // @[Execute.scala 107:20]
  assign exe_stage_io_lsu_mmu_bits_vaddr = exe_stage_lsu_io_lsu_mmu_bits_vaddr; // @[Execute.scala 107:20]
  assign exe_stage_io_mmu_lsu_ready = exe_stage_lsu_io_mmu_lsu_ready; // @[Execute.scala 108:20]
  assign exe_stage_io_lsu_cmm_is_access_fault = exe_stage_lsu_io_lsu_cmm_is_access_fault; // @[Execute.scala 111:20]
  assign exe_stage_io_lsu_cmm_is_paging_fault = exe_stage_lsu_io_lsu_cmm_is_paging_fault; // @[Execute.scala 111:20]
  assign exe_stage_io_lsu_cmm_is_misAlign = exe_stage_lsu_io_lsu_cmm_is_misAlign; // @[Execute.scala 111:20]
  assign exe_stage_io_lsu_cmm_trap_addr = exe_stage_lsu_io_lsu_cmm_trap_addr; // @[Execute.scala 111:20]
  assign exe_stage_io_missUnit_dcache_acquire_valid = exe_stage_lsu_io_missUnit_dcache_acquire_valid; // @[Execute.scala 114:42]
  assign exe_stage_io_missUnit_dcache_acquire_bits_opcode = exe_stage_lsu_io_missUnit_dcache_acquire_bits_opcode; // @[Execute.scala 115:42]
  assign exe_stage_io_missUnit_dcache_acquire_bits_param = exe_stage_lsu_io_missUnit_dcache_acquire_bits_param; // @[Execute.scala 115:42]
  assign exe_stage_io_missUnit_dcache_acquire_bits_size = exe_stage_lsu_io_missUnit_dcache_acquire_bits_size; // @[Execute.scala 115:42]
  assign exe_stage_io_missUnit_dcache_acquire_bits_source = exe_stage_lsu_io_missUnit_dcache_acquire_bits_source; // @[Execute.scala 115:42]
  assign exe_stage_io_missUnit_dcache_acquire_bits_address = exe_stage_lsu_io_missUnit_dcache_acquire_bits_address; // @[Execute.scala 115:42]
  assign exe_stage_io_missUnit_dcache_acquire_bits_mask = exe_stage_lsu_io_missUnit_dcache_acquire_bits_mask; // @[Execute.scala 115:42]
  assign exe_stage_io_missUnit_dcache_acquire_bits_data = exe_stage_lsu_io_missUnit_dcache_acquire_bits_data; // @[Execute.scala 115:42]
  assign exe_stage_io_missUnit_dcache_acquire_bits_corrupt = exe_stage_lsu_io_missUnit_dcache_acquire_bits_corrupt; // @[Execute.scala 115:42]
  assign exe_stage_io_missUnit_dcache_grant_ready = exe_stage_lsu_io_missUnit_dcache_grant_ready; // @[Execute.scala 120:40]
  assign exe_stage_io_missUnit_dcache_grantAck_valid = exe_stage_lsu_io_missUnit_dcache_grantAck_valid; // @[Execute.scala 122:43]
  assign exe_stage_io_missUnit_dcache_grantAck_bits_sink = exe_stage_lsu_io_missUnit_dcache_grantAck_bits_sink; // @[Execute.scala 123:42]
  assign exe_stage_io_probeUnit_dcache_probe_ready = exe_stage_lsu_io_probeUnit_dcache_probe_ready; // @[Execute.scala 128:41]
  assign exe_stage_io_writeBackUnit_dcache_release_valid = exe_stage_lsu_io_writeBackUnit_dcache_release_valid; // @[Execute.scala 130:47]
  assign exe_stage_io_writeBackUnit_dcache_release_bits_opcode =
    exe_stage_lsu_io_writeBackUnit_dcache_release_bits_opcode; // @[Execute.scala 131:46]
  assign exe_stage_io_writeBackUnit_dcache_release_bits_param = exe_stage_lsu_io_writeBackUnit_dcache_release_bits_param
    ; // @[Execute.scala 131:46]
  assign exe_stage_io_writeBackUnit_dcache_release_bits_size = exe_stage_lsu_io_writeBackUnit_dcache_release_bits_size; // @[Execute.scala 131:46]
  assign exe_stage_io_writeBackUnit_dcache_release_bits_source =
    exe_stage_lsu_io_writeBackUnit_dcache_release_bits_source; // @[Execute.scala 131:46]
  assign exe_stage_io_writeBackUnit_dcache_release_bits_address =
    exe_stage_lsu_io_writeBackUnit_dcache_release_bits_address; // @[Execute.scala 131:46]
  assign exe_stage_io_writeBackUnit_dcache_release_bits_data = exe_stage_lsu_io_writeBackUnit_dcache_release_bits_data; // @[Execute.scala 131:46]
  assign exe_stage_io_writeBackUnit_dcache_release_bits_corrupt =
    exe_stage_lsu_io_writeBackUnit_dcache_release_bits_corrupt; // @[Execute.scala 131:46]
  assign exe_stage_io_writeBackUnit_dcache_grant_ready = exe_stage_lsu_io_writeBackUnit_dcache_grant_ready; // @[Execute.scala 136:45]
  assign exe_stage_io_system_getPut_valid = exe_stage_lsu_io_system_getPut_valid; // @[Execute.scala 149:28]
  assign exe_stage_io_system_getPut_bits_opcode = exe_stage_lsu_io_system_getPut_bits_opcode; // @[Execute.scala 150:27]
  assign exe_stage_io_system_getPut_bits_param = exe_stage_lsu_io_system_getPut_bits_param; // @[Execute.scala 150:27]
  assign exe_stage_io_system_getPut_bits_size = exe_stage_lsu_io_system_getPut_bits_size; // @[Execute.scala 150:27]
  assign exe_stage_io_system_getPut_bits_source = exe_stage_lsu_io_system_getPut_bits_source; // @[Execute.scala 150:27]
  assign exe_stage_io_system_getPut_bits_address = exe_stage_lsu_io_system_getPut_bits_address; // @[Execute.scala 150:27]
  assign exe_stage_io_system_getPut_bits_mask = exe_stage_lsu_io_system_getPut_bits_mask; // @[Execute.scala 150:27]
  assign exe_stage_io_system_getPut_bits_data = exe_stage_lsu_io_system_getPut_bits_data; // @[Execute.scala 150:27]
  assign exe_stage_io_system_getPut_bits_corrupt = exe_stage_lsu_io_system_getPut_bits_corrupt; // @[Execute.scala 150:27]
  assign exe_stage_io_system_access_ready = exe_stage_lsu_io_system_access_ready; // @[Execute.scala 154:28]
  assign exe_stage_io_periph_getPut_valid = exe_stage_lsu_io_periph_getPut_valid; // @[Execute.scala 156:28]
  assign exe_stage_io_periph_getPut_bits_opcode = exe_stage_lsu_io_periph_getPut_bits_opcode; // @[Execute.scala 157:27]
  assign exe_stage_io_periph_getPut_bits_param = exe_stage_lsu_io_periph_getPut_bits_param; // @[Execute.scala 157:27]
  assign exe_stage_io_periph_getPut_bits_size = exe_stage_lsu_io_periph_getPut_bits_size; // @[Execute.scala 157:27]
  assign exe_stage_io_periph_getPut_bits_source = exe_stage_lsu_io_periph_getPut_bits_source; // @[Execute.scala 157:27]
  assign exe_stage_io_periph_getPut_bits_address = exe_stage_lsu_io_periph_getPut_bits_address; // @[Execute.scala 157:27]
  assign exe_stage_io_periph_getPut_bits_mask = exe_stage_lsu_io_periph_getPut_bits_mask; // @[Execute.scala 157:27]
  assign exe_stage_io_periph_getPut_bits_data = exe_stage_lsu_io_periph_getPut_bits_data; // @[Execute.scala 157:27]
  assign exe_stage_io_periph_getPut_bits_corrupt = exe_stage_lsu_io_periph_getPut_bits_corrupt; // @[Execute.scala 157:27]
  assign exe_stage_io_periph_access_ready = exe_stage_lsu_io_periph_access_ready; // @[Execute.scala 161:28]
  assign exe_stage_alu_0_clock = exe_stage_clock;
  assign exe_stage_alu_0_reset = exe_stage_reset;
  assign exe_stage_alu_0_io_alu_iss_exe_valid = exe_stage_io_alu_iss_exe_0_valid; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_fun_add = exe_stage_io_alu_iss_exe_0_bits_fun_add; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_fun_slt = exe_stage_io_alu_iss_exe_0_bits_fun_slt; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_fun_xor = exe_stage_io_alu_iss_exe_0_bits_fun_xor; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_fun_or = exe_stage_io_alu_iss_exe_0_bits_fun_or; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_fun_and = exe_stage_io_alu_iss_exe_0_bits_fun_and; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_fun_sll = exe_stage_io_alu_iss_exe_0_bits_fun_sll; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_fun_srl = exe_stage_io_alu_iss_exe_0_bits_fun_srl; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_fun_sra = exe_stage_io_alu_iss_exe_0_bits_fun_sra; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_param_rd0 = exe_stage_io_alu_iss_exe_0_bits_param_rd0; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_param_is_32w = exe_stage_io_alu_iss_exe_0_bits_param_is_32w; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_param_is_usi = exe_stage_io_alu_iss_exe_0_bits_param_is_usi; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op1 = exe_stage_io_alu_iss_exe_0_bits_param_dat_op1; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_iss_exe_bits_param_dat_op2 = exe_stage_io_alu_iss_exe_0_bits_param_dat_op2; // @[Execute.scala 185:27]
  assign exe_stage_alu_0_io_alu_exe_iwb_ready = exe_stage_io_alu_exe_iwb_0_ready; // @[Execute.scala 186:27]
  assign exe_stage_alu_0_io_flush = exe_stage_io_flush; // @[Execute.scala 187:21]
  assign exe_stage_bru_clock = exe_stage_clock;
  assign exe_stage_bru_reset = exe_stage_reset;
  assign exe_stage_bru_io_bru_iss_exe_valid = exe_stage_io_bru_iss_exe_valid; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_fun_jalr = exe_stage_io_bru_iss_exe_bits_fun_jalr; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_fun_beq = exe_stage_io_bru_iss_exe_bits_fun_beq; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_fun_bne = exe_stage_io_bru_iss_exe_bits_fun_bne; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_fun_blt = exe_stage_io_bru_iss_exe_bits_fun_blt; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_fun_bge = exe_stage_io_bru_iss_exe_bits_fun_bge; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_fun_bltu = exe_stage_io_bru_iss_exe_bits_fun_bltu; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_fun_bgeu = exe_stage_io_bru_iss_exe_bits_fun_bgeu; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_param_rd0 = exe_stage_io_bru_iss_exe_bits_param_rd0; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_param_is_rvc = exe_stage_io_bru_iss_exe_bits_param_is_rvc; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_param_pc = exe_stage_io_bru_iss_exe_bits_param_pc; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_param_imm = exe_stage_io_bru_iss_exe_bits_param_imm; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_param_dat_op1 = exe_stage_io_bru_iss_exe_bits_param_dat_op1; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_iss_exe_bits_param_dat_op2 = exe_stage_io_bru_iss_exe_bits_param_dat_op2; // @[Execute.scala 191:22]
  assign exe_stage_bru_io_bru_exe_iwb_ready = exe_stage_io_bru_exe_iwb_ready; // @[Execute.scala 192:22]
  assign exe_stage_bru_io_bftq_valid = exe_stage_io_bftq_valid; // @[Execute.scala 195:15]
  assign exe_stage_bru_io_bftq_bits_pc = exe_stage_io_bftq_bits_pc; // @[Execute.scala 195:15]
  assign exe_stage_bru_io_bftq_bits_bimResp_bim_p = exe_stage_io_bftq_bits_bimResp_bim_p; // @[Execute.scala 195:15]
  assign exe_stage_bru_io_bftq_bits_bimResp_bim_h = exe_stage_io_bftq_bits_bimResp_bim_h; // @[Execute.scala 195:15]
  assign exe_stage_bru_io_bftq_bits_isPredictTaken = exe_stage_io_bftq_bits_isPredictTaken; // @[Execute.scala 195:15]
  assign exe_stage_bru_io_jftq_valid = exe_stage_io_jftq_valid; // @[Execute.scala 196:15]
  assign exe_stage_bru_io_jftq_bits_pc = exe_stage_io_jftq_bits_pc; // @[Execute.scala 196:15]
  assign exe_stage_bru_io_jftq_bits_btbResp_target = exe_stage_io_jftq_bits_btbResp_target; // @[Execute.scala 196:15]
  assign exe_stage_bru_io_jftq_bits_rasResp_target = exe_stage_io_jftq_bits_rasResp_target; // @[Execute.scala 196:15]
  assign exe_stage_bru_io_jftq_bits_isRas = exe_stage_io_jftq_bits_isRas; // @[Execute.scala 196:15]
  assign exe_stage_bru_io_bctq_ready = exe_stage_io_bctq_ready; // @[Execute.scala 198:11]
  assign exe_stage_bru_io_jctq_ready = exe_stage_io_jctq_ready; // @[Execute.scala 199:11]
  assign exe_stage_bru_io_flush = exe_stage_io_flush; // @[Execute.scala 193:16]
  assign exe_stage_lsu_clock = exe_stage_clock;
  assign exe_stage_lsu_reset = exe_stage_reset;
  assign exe_stage_lsu_io_lsu_iss_exe_valid = exe_stage_io_lsu_iss_exe_valid; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_lb = exe_stage_io_lsu_iss_exe_bits_fun_lb; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_lh = exe_stage_io_lsu_iss_exe_bits_fun_lh; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_lw = exe_stage_io_lsu_iss_exe_bits_fun_lw; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_ld = exe_stage_io_lsu_iss_exe_bits_fun_ld; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_lbu = exe_stage_io_lsu_iss_exe_bits_fun_lbu; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_lhu = exe_stage_io_lsu_iss_exe_bits_fun_lhu; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_lwu = exe_stage_io_lsu_iss_exe_bits_fun_lwu; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_sb = exe_stage_io_lsu_iss_exe_bits_fun_sb; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_sh = exe_stage_io_lsu_iss_exe_bits_fun_sh; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_sw = exe_stage_io_lsu_iss_exe_bits_fun_sw; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_sd = exe_stage_io_lsu_iss_exe_bits_fun_sd; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_fence = exe_stage_io_lsu_iss_exe_bits_fun_fence; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_fence_i = exe_stage_io_lsu_iss_exe_bits_fun_fence_i; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_sfence_vma = exe_stage_io_lsu_iss_exe_bits_fun_sfence_vma; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_w = exe_stage_io_lsu_iss_exe_bits_fun_lr_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_w = exe_stage_io_lsu_iss_exe_bits_fun_sc_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_w = exe_stage_io_lsu_iss_exe_bits_fun_amoswap_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_w = exe_stage_io_lsu_iss_exe_bits_fun_amoadd_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_w = exe_stage_io_lsu_iss_exe_bits_fun_amoxor_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_w = exe_stage_io_lsu_iss_exe_bits_fun_amoand_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_w = exe_stage_io_lsu_iss_exe_bits_fun_amoor_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_w = exe_stage_io_lsu_iss_exe_bits_fun_amomin_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_w = exe_stage_io_lsu_iss_exe_bits_fun_amomax_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_w = exe_stage_io_lsu_iss_exe_bits_fun_amominu_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_w = exe_stage_io_lsu_iss_exe_bits_fun_amomaxu_w; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_lr_d = exe_stage_io_lsu_iss_exe_bits_fun_lr_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_sc_d = exe_stage_io_lsu_iss_exe_bits_fun_sc_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoswap_d = exe_stage_io_lsu_iss_exe_bits_fun_amoswap_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoadd_d = exe_stage_io_lsu_iss_exe_bits_fun_amoadd_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoxor_d = exe_stage_io_lsu_iss_exe_bits_fun_amoxor_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoand_d = exe_stage_io_lsu_iss_exe_bits_fun_amoand_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amoor_d = exe_stage_io_lsu_iss_exe_bits_fun_amoor_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomin_d = exe_stage_io_lsu_iss_exe_bits_fun_amomin_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomax_d = exe_stage_io_lsu_iss_exe_bits_fun_amomax_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amominu_d = exe_stage_io_lsu_iss_exe_bits_fun_amominu_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_amomaxu_d = exe_stage_io_lsu_iss_exe_bits_fun_amomaxu_d; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_flw = exe_stage_io_lsu_iss_exe_bits_fun_flw; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsw = exe_stage_io_lsu_iss_exe_bits_fun_fsw; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_fld = exe_stage_io_lsu_iss_exe_bits_fun_fld; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_fun_fsd = exe_stage_io_lsu_iss_exe_bits_fun_fsd; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0 = exe_stage_io_lsu_iss_exe_bits_param_rd0; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op1 = exe_stage_io_lsu_iss_exe_bits_param_dat_op1; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op2 = exe_stage_io_lsu_iss_exe_bits_param_dat_op2; // @[Execute.scala 103:24]
  assign exe_stage_lsu_io_lsu_exe_iwb_ready = exe_stage_io_lsu_exe_iwb_ready; // @[Execute.scala 104:24]
  assign exe_stage_lsu_io_lsu_exe_fwb_ready = exe_stage_io_lsu_exe_fwb_ready; // @[Execute.scala 105:24]
  assign exe_stage_lsu_io_cmm_lsu_is_amo_pending = exe_stage_io_cmm_lsu_is_amo_pending; // @[Execute.scala 110:20]
  assign exe_stage_lsu_io_cmm_lsu_is_store_commit_0 = exe_stage_io_cmm_lsu_is_store_commit_0; // @[Execute.scala 110:20]
  assign exe_stage_lsu_io_lsu_mmu_ready = exe_stage_io_lsu_mmu_ready; // @[Execute.scala 107:20]
  assign exe_stage_lsu_io_mmu_lsu_valid = exe_stage_io_mmu_lsu_valid; // @[Execute.scala 108:20]
  assign exe_stage_lsu_io_mmu_lsu_bits_paddr = exe_stage_io_mmu_lsu_bits_paddr; // @[Execute.scala 108:20]
  assign exe_stage_lsu_io_mmu_lsu_bits_is_paging_fault = exe_stage_io_mmu_lsu_bits_is_paging_fault; // @[Execute.scala 108:20]
  assign exe_stage_lsu_io_mmu_lsu_bits_is_access_fault = exe_stage_io_mmu_lsu_bits_is_access_fault; // @[Execute.scala 108:20]
  assign exe_stage_lsu_io_missUnit_dcache_acquire_ready = exe_stage_io_missUnit_dcache_acquire_ready; // @[Execute.scala 116:46]
  assign exe_stage_lsu_io_missUnit_dcache_grant_valid = exe_stage_io_missUnit_dcache_grant_valid; // @[Execute.scala 118:44]
  assign exe_stage_lsu_io_missUnit_dcache_grant_bits_opcode = exe_stage_io_missUnit_dcache_grant_bits_opcode; // @[Execute.scala 119:44]
  assign exe_stage_lsu_io_missUnit_dcache_grant_bits_size = exe_stage_io_missUnit_dcache_grant_bits_size; // @[Execute.scala 119:44]
  assign exe_stage_lsu_io_missUnit_dcache_grant_bits_source = exe_stage_io_missUnit_dcache_grant_bits_source; // @[Execute.scala 119:44]
  assign exe_stage_lsu_io_missUnit_dcache_grant_bits_sink = exe_stage_io_missUnit_dcache_grant_bits_sink; // @[Execute.scala 119:44]
  assign exe_stage_lsu_io_missUnit_dcache_grant_bits_data = exe_stage_io_missUnit_dcache_grant_bits_data; // @[Execute.scala 119:44]
  assign exe_stage_lsu_io_missUnit_dcache_grantAck_ready = exe_stage_io_missUnit_dcache_grantAck_ready; // @[Execute.scala 124:47]
  assign exe_stage_lsu_io_probeUnit_dcache_probe_valid = exe_stage_io_probeUnit_dcache_probe_valid; // @[Execute.scala 126:45]
  assign exe_stage_lsu_io_probeUnit_dcache_probe_bits_address = exe_stage_io_probeUnit_dcache_probe_bits_address; // @[Execute.scala 127:44]
  assign exe_stage_lsu_io_writeBackUnit_dcache_release_ready = exe_stage_io_writeBackUnit_dcache_release_ready; // @[Execute.scala 132:51]
  assign exe_stage_lsu_io_writeBackUnit_dcache_grant_valid = exe_stage_io_writeBackUnit_dcache_grant_valid; // @[Execute.scala 134:49]
  assign exe_stage_lsu_io_writeBackUnit_dcache_grant_bits_source = exe_stage_io_writeBackUnit_dcache_grant_bits_source; // @[Execute.scala 135:48]
  assign exe_stage_lsu_io_system_getPut_ready = exe_stage_io_system_getPut_ready; // @[Execute.scala 151:32]
  assign exe_stage_lsu_io_system_access_valid = exe_stage_io_system_access_valid; // @[Execute.scala 152:32]
  assign exe_stage_lsu_io_system_access_bits_opcode = exe_stage_io_system_access_bits_opcode; // @[Execute.scala 153:31]
  assign exe_stage_lsu_io_system_access_bits_data = exe_stage_io_system_access_bits_data; // @[Execute.scala 153:31]
  assign exe_stage_lsu_io_periph_getPut_ready = exe_stage_io_periph_getPut_ready; // @[Execute.scala 158:32]
  assign exe_stage_lsu_io_periph_access_valid = exe_stage_io_periph_access_valid; // @[Execute.scala 159:32]
  assign exe_stage_lsu_io_periph_access_bits_opcode = exe_stage_io_periph_access_bits_opcode; // @[Execute.scala 160:31]
  assign exe_stage_lsu_io_periph_access_bits_data = exe_stage_io_periph_access_bits_data; // @[Execute.scala 160:31]
  assign exe_stage_lsu_io_flush = exe_stage_io_flush; // @[Execute.scala 165:18]
  assign exe_stage_csr_clock = exe_stage_clock;
  assign exe_stage_csr_reset = exe_stage_reset;
  assign exe_stage_csr_io_csr_iss_exe_valid = exe_stage_io_csr_iss_exe_valid; // @[Execute.scala 204:22]
  assign exe_stage_csr_io_csr_iss_exe_bits_fun_rw = exe_stage_io_csr_iss_exe_bits_fun_rw; // @[Execute.scala 204:22]
  assign exe_stage_csr_io_csr_iss_exe_bits_fun_rs = exe_stage_io_csr_iss_exe_bits_fun_rs; // @[Execute.scala 204:22]
  assign exe_stage_csr_io_csr_iss_exe_bits_fun_rc = exe_stage_io_csr_iss_exe_bits_fun_rc; // @[Execute.scala 204:22]
  assign exe_stage_csr_io_csr_iss_exe_bits_param_rd0 = exe_stage_io_csr_iss_exe_bits_param_rd0; // @[Execute.scala 204:22]
  assign exe_stage_csr_io_csr_iss_exe_bits_param_dat_op1 = exe_stage_io_csr_iss_exe_bits_param_dat_op1; // @[Execute.scala 204:22]
  assign exe_stage_csr_io_csr_iss_exe_bits_param_dat_op2 = exe_stage_io_csr_iss_exe_bits_param_dat_op2; // @[Execute.scala 204:22]
  assign exe_stage_csr_io_csr_exe_iwb_ready = exe_stage_io_csr_exe_iwb_ready; // @[Execute.scala 205:22]
  assign exe_stage_csr_io_csr_data_valid = exe_stage_io_csr_data_valid; // @[Execute.scala 207:19]
  assign exe_stage_csr_io_csr_data_bits = exe_stage_io_csr_data_bits; // @[Execute.scala 207:19]
  assign exe_stage_csr_io_csr_cmm_op_ready = exe_stage_io_csr_cmm_op_ready; // @[Execute.scala 208:21]
  assign exe_stage_csr_io_flush = exe_stage_io_flush; // @[Execute.scala 209:16]
  assign exe_stage_mulDiv_0_clock = exe_stage_clock;
  assign exe_stage_mulDiv_0_reset = exe_stage_reset;
  assign exe_stage_mulDiv_0_io_mul_iss_exe_valid = exe_stage_io_mul_iss_exe_0_valid; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mul = exe_stage_io_mul_iss_exe_0_bits_fun_mul; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulh = exe_stage_io_mul_iss_exe_0_bits_fun_mulh; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulhsu = exe_stage_io_mul_iss_exe_0_bits_fun_mulhsu; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulhu = exe_stage_io_mul_iss_exe_0_bits_fun_mulhu; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_div = exe_stage_io_mul_iss_exe_0_bits_fun_div; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divu = exe_stage_io_mul_iss_exe_0_bits_fun_divu; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_rem = exe_stage_io_mul_iss_exe_0_bits_fun_rem; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remu = exe_stage_io_mul_iss_exe_0_bits_fun_remu; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_mulw = exe_stage_io_mul_iss_exe_0_bits_fun_mulw; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divw = exe_stage_io_mul_iss_exe_0_bits_fun_divw; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_divuw = exe_stage_io_mul_iss_exe_0_bits_fun_divuw; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remw = exe_stage_io_mul_iss_exe_0_bits_fun_remw; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_fun_remuw = exe_stage_io_mul_iss_exe_0_bits_fun_remuw; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_rd0 = exe_stage_io_mul_iss_exe_0_bits_param_rd0; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op1 = exe_stage_io_mul_iss_exe_0_bits_param_dat_op1; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_iss_exe_bits_param_dat_op2 = exe_stage_io_mul_iss_exe_0_bits_param_dat_op2; // @[Execute.scala 212:30]
  assign exe_stage_mulDiv_0_io_mul_exe_iwb_ready = exe_stage_io_mul_exe_iwb_0_ready; // @[Execute.scala 213:30]
  assign exe_stage_mulDiv_0_io_flush = exe_stage_io_flush; // @[Execute.scala 214:24]
  assign exe_stage_fpu_0_clock = exe_stage_clock;
  assign exe_stage_fpu_0_reset = exe_stage_reset;
  assign exe_stage_fpu_0_io_fpu_iss_exe_valid = exe_stage_io_fpu_iss_exe_0_valid; // @[Execute.scala 176:27]
  assign iwb_stage_iReg_io_lookup_0_rsp_rs1 = iwb_stage_iReg__io_lookup_0_rsp_rs1_T ? 6'h21 : iwb_stage_iReg__GEN_3000; // @[Regfiles.scala 258:34]
  assign iwb_stage_iReg_io_lookup_0_rsp_rs2 = iwb_stage_iReg__io_lookup_0_rsp_rs2_T ? 6'h21 : iwb_stage_iReg__GEN_3032; // @[Regfiles.scala 259:34]
  assign iwb_stage_iReg_io_rename_0_rsp_rd0 = iwb_stage_iReg__T_33 ? 6'h0 : iwb_stage_iReg__GEN_1120; // @[Regfiles.scala 150:{46,62}]
  assign iwb_stage_iReg_io_rename_0_req_ready = iwb_stage_iReg__io_rename_0_req_ready_T_98 > 6'h0; // @[Regfiles.scala 165:70]
  assign iwb_stage_iReg_io_rgLog_0 = iwb_stage_iReg_log_reg_0; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_1 = iwb_stage_iReg_log_reg_1; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_2 = iwb_stage_iReg_log_reg_2; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_3 = iwb_stage_iReg_log_reg_3; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_4 = iwb_stage_iReg_log_reg_4; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_5 = iwb_stage_iReg_log_reg_5; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_6 = iwb_stage_iReg_log_reg_6; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_7 = iwb_stage_iReg_log_reg_7; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_8 = iwb_stage_iReg_log_reg_8; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_9 = iwb_stage_iReg_log_reg_9; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_10 = iwb_stage_iReg_log_reg_10; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_11 = iwb_stage_iReg_log_reg_11; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_12 = iwb_stage_iReg_log_reg_12; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_13 = iwb_stage_iReg_log_reg_13; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_14 = iwb_stage_iReg_log_reg_14; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_15 = iwb_stage_iReg_log_reg_15; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_16 = iwb_stage_iReg_log_reg_16; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_17 = iwb_stage_iReg_log_reg_17; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_18 = iwb_stage_iReg_log_reg_18; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_19 = iwb_stage_iReg_log_reg_19; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_20 = iwb_stage_iReg_log_reg_20; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_21 = iwb_stage_iReg_log_reg_21; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_22 = iwb_stage_iReg_log_reg_22; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_23 = iwb_stage_iReg_log_reg_23; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_24 = iwb_stage_iReg_log_reg_24; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_25 = iwb_stage_iReg_log_reg_25; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_26 = iwb_stage_iReg_log_reg_26; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_27 = iwb_stage_iReg_log_reg_27; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_28 = iwb_stage_iReg_log_reg_28; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_29 = iwb_stage_iReg_log_reg_29; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_30 = iwb_stage_iReg_log_reg_30; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_31 = iwb_stage_iReg_log_reg_31; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_32 = iwb_stage_iReg_log_reg_32; // @[Regfiles.scala 104:19 105:50]
  assign iwb_stage_iReg_io_rgLog_33 = 2'h3; // @[Regfiles.scala 104:19 106:19]
  assign iwb_stage_iReg_io_rgRsp_0_valid = iwb_stage_iReg_io_rgRsp_0_valid_REG; // @[Regfiles.scala 191:26]
  assign iwb_stage_iReg_io_rgRsp_0_bits_phy = iwb_stage_iReg_io_rgRsp_0_bits_phy_r; // @[Regfiles.scala 192:26]
  assign iwb_stage_iReg_io_rgRsp_0_bits_op = iwb_stage_iReg_io_rgRsp_0_bits_op_r; // @[Regfiles.scala 193:26]
  assign iwb_stage_iReg_io_exe_writeBack_0_ready = 1'h1; // @[Regfiles.scala 207:31]
  assign iwb_stage_iReg_io_commit_0_is_writeback = iwb_stage_iReg__GEN_1619 == 2'h3; // @[Regfiles.scala 219:46]
  assign iwb_stage_fReg_io_lookup_0_rsp_rs1 = 6'h0; // @[Regfiles.scala 310:{37,37}]
  assign iwb_stage_fReg_io_lookup_0_rsp_rs2 = 6'h0; // @[Regfiles.scala 310:{37,37}]
  assign iwb_stage_fReg_io_lookup_0_rsp_rs3 = 6'h0; // @[Regfiles.scala 310:{37,37}]
  assign iwb_stage_fReg_io_rename_0_rsp_rd0 = 6'h0; // @[Regfiles.scala 311:{37,37}]
  assign iwb_stage_fReg_io_rename_0_req_ready = 1'h1; // @[Regfiles.scala 312:28]
  assign iwb_stage_fReg_io_rgLog_0 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_1 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_2 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_3 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_4 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_5 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_6 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_7 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_8 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_9 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_10 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_11 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_12 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_13 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_14 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_15 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_16 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_17 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_18 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_19 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_20 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_21 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_22 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_23 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_24 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_25 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_26 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_27 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_28 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_29 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_30 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_31 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_32 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_rgLog_33 = 2'h3; // @[Regfiles.scala 315:42]
  assign iwb_stage_fReg_io_exe_writeBack_0_ready = 1'h1; // @[Regfiles.scala 323:31]
  assign iwb_stage_fReg_io_commit_0_is_writeback = 1'h0; // @[Regfiles.scala 328:31]
  assign iwb_stage_iwriteBack_arb_io_enq_0_ready = iwb_stage_iwriteBack_arb__T_16 & iwb_stage_iwriteBack_arb__GEN_18; // @[XArbiter.scala 50:51 53:76]
  assign iwb_stage_iwriteBack_arb_io_enq_1_ready = iwb_stage_iwriteBack_arb__T_16 & iwb_stage_iwriteBack_arb__GEN_19; // @[XArbiter.scala 50:51 53:76]
  assign iwb_stage_iwriteBack_arb_io_enq_2_ready = iwb_stage_iwriteBack_arb__T_16 & iwb_stage_iwriteBack_arb__GEN_20; // @[XArbiter.scala 50:51 53:76]
  assign iwb_stage_iwriteBack_arb_io_enq_3_ready = iwb_stage_iwriteBack_arb__T_16 & iwb_stage_iwriteBack_arb__GEN_21; // @[XArbiter.scala 50:51 53:76]
  assign iwb_stage_iwriteBack_arb_io_enq_4_ready = iwb_stage_iwriteBack_arb__T_16 & iwb_stage_iwriteBack_arb__GEN_22; // @[XArbiter.scala 50:51 53:76]
  assign iwb_stage_iwriteBack_arb_io_deq_0_valid = iwb_stage_iwriteBack_arb__T_14 > 3'h0; // @[XArbiter.scala 53:68]
  assign iwb_stage_iwriteBack_arb_io_deq_0_bits_rd0 = 3'h5 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_5_bits_rd0 : iwb_stage_iwriteBack_arb__GEN_10; // @[XArbiter.scala 55:{22,22}]
  assign iwb_stage_iwriteBack_arb_io_deq_0_bits_res = 3'h5 == iwb_stage_iwriteBack_arb_io_chosen_0 ?
    iwb_stage_iwriteBack_arb_io_enq_5_bits_res : iwb_stage_iwriteBack_arb__GEN_16; // @[XArbiter.scala 55:{22,22}]
  assign iwb_stage_iwriteBack_arb_io_chosen_0 = iwb_stage_iwriteBack_arb_io_enq_0_valid ? 3'h0 :
    iwb_stage_iwriteBack_arb__GEN_4; // @[XArbiter.scala 36:31 37:38]
  assign iwb_stage_io_xLookup_0_rsp_rs1 = iwb_stage_iReg_io_lookup_0_rsp_rs1; // @[WriteBack.scala 78:23]
  assign iwb_stage_io_xLookup_0_rsp_rs2 = iwb_stage_iReg_io_lookup_0_rsp_rs2; // @[WriteBack.scala 78:23]
  assign iwb_stage_io_fLookup_0_rsp_rs1 = iwb_stage_fReg_io_lookup_0_rsp_rs1; // @[WriteBack.scala 79:23]
  assign iwb_stage_io_fLookup_0_rsp_rs2 = iwb_stage_fReg_io_lookup_0_rsp_rs2; // @[WriteBack.scala 79:23]
  assign iwb_stage_io_fLookup_0_rsp_rs3 = iwb_stage_fReg_io_lookup_0_rsp_rs3; // @[WriteBack.scala 79:23]
  assign iwb_stage_io_xRename_0_rsp_rd0 = iwb_stage_iReg_io_rename_0_rsp_rd0; // @[WriteBack.scala 76:23]
  assign iwb_stage_io_xRename_0_req_ready = iwb_stage_iReg_io_rename_0_req_ready; // @[WriteBack.scala 76:23]
  assign iwb_stage_io_fRename_0_rsp_rd0 = iwb_stage_fReg_io_rename_0_rsp_rd0; // @[WriteBack.scala 77:23]
  assign iwb_stage_io_fRename_0_req_ready = iwb_stage_fReg_io_rename_0_req_ready; // @[WriteBack.scala 77:23]
  assign iwb_stage_io_irgLog_0 = iwb_stage_iReg_io_rgLog_0; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_1 = iwb_stage_iReg_io_rgLog_1; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_2 = iwb_stage_iReg_io_rgLog_2; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_3 = iwb_stage_iReg_io_rgLog_3; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_4 = iwb_stage_iReg_io_rgLog_4; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_5 = iwb_stage_iReg_io_rgLog_5; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_6 = iwb_stage_iReg_io_rgLog_6; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_7 = iwb_stage_iReg_io_rgLog_7; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_8 = iwb_stage_iReg_io_rgLog_8; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_9 = iwb_stage_iReg_io_rgLog_9; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_10 = iwb_stage_iReg_io_rgLog_10; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_11 = iwb_stage_iReg_io_rgLog_11; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_12 = iwb_stage_iReg_io_rgLog_12; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_13 = iwb_stage_iReg_io_rgLog_13; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_14 = iwb_stage_iReg_io_rgLog_14; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_15 = iwb_stage_iReg_io_rgLog_15; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_16 = iwb_stage_iReg_io_rgLog_16; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_17 = iwb_stage_iReg_io_rgLog_17; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_18 = iwb_stage_iReg_io_rgLog_18; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_19 = iwb_stage_iReg_io_rgLog_19; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_20 = iwb_stage_iReg_io_rgLog_20; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_21 = iwb_stage_iReg_io_rgLog_21; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_22 = iwb_stage_iReg_io_rgLog_22; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_23 = iwb_stage_iReg_io_rgLog_23; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_24 = iwb_stage_iReg_io_rgLog_24; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_25 = iwb_stage_iReg_io_rgLog_25; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_26 = iwb_stage_iReg_io_rgLog_26; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_27 = iwb_stage_iReg_io_rgLog_27; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_28 = iwb_stage_iReg_io_rgLog_28; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_29 = iwb_stage_iReg_io_rgLog_29; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_30 = iwb_stage_iReg_io_rgLog_30; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_31 = iwb_stage_iReg_io_rgLog_31; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_32 = iwb_stage_iReg_io_rgLog_32; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_irgLog_33 = iwb_stage_iReg_io_rgLog_33; // @[WriteBack.scala 118:13]
  assign iwb_stage_io_frgLog_0 = iwb_stage_fReg_io_rgLog_0; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_1 = iwb_stage_fReg_io_rgLog_1; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_2 = iwb_stage_fReg_io_rgLog_2; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_3 = iwb_stage_fReg_io_rgLog_3; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_4 = iwb_stage_fReg_io_rgLog_4; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_5 = iwb_stage_fReg_io_rgLog_5; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_6 = iwb_stage_fReg_io_rgLog_6; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_7 = iwb_stage_fReg_io_rgLog_7; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_8 = iwb_stage_fReg_io_rgLog_8; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_9 = iwb_stage_fReg_io_rgLog_9; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_10 = iwb_stage_fReg_io_rgLog_10; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_11 = iwb_stage_fReg_io_rgLog_11; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_12 = iwb_stage_fReg_io_rgLog_12; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_13 = iwb_stage_fReg_io_rgLog_13; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_14 = iwb_stage_fReg_io_rgLog_14; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_15 = iwb_stage_fReg_io_rgLog_15; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_16 = iwb_stage_fReg_io_rgLog_16; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_17 = iwb_stage_fReg_io_rgLog_17; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_18 = iwb_stage_fReg_io_rgLog_18; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_19 = iwb_stage_fReg_io_rgLog_19; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_20 = iwb_stage_fReg_io_rgLog_20; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_21 = iwb_stage_fReg_io_rgLog_21; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_22 = iwb_stage_fReg_io_rgLog_22; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_23 = iwb_stage_fReg_io_rgLog_23; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_24 = iwb_stage_fReg_io_rgLog_24; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_25 = iwb_stage_fReg_io_rgLog_25; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_26 = iwb_stage_fReg_io_rgLog_26; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_27 = iwb_stage_fReg_io_rgLog_27; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_28 = iwb_stage_fReg_io_rgLog_28; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_29 = iwb_stage_fReg_io_rgLog_29; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_30 = iwb_stage_fReg_io_rgLog_30; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_31 = iwb_stage_fReg_io_rgLog_31; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_32 = iwb_stage_fReg_io_rgLog_32; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_frgLog_33 = iwb_stage_fReg_io_rgLog_33; // @[WriteBack.scala 119:13]
  assign iwb_stage_io_irgRsp_0_valid = iwb_stage_iReg_io_rgRsp_0_valid; // @[WriteBack.scala 113:13]
  assign iwb_stage_io_irgRsp_0_bits_phy = iwb_stage_iReg_io_rgRsp_0_bits_phy; // @[WriteBack.scala 113:13]
  assign iwb_stage_io_irgRsp_0_bits_op = iwb_stage_iReg_io_rgRsp_0_bits_op; // @[WriteBack.scala 113:13]
  assign iwb_stage_io_alu_iWriteBack_0_ready = iwb_stage_iwriteBack_arb_io_enq_0_ready; // @[WriteBack.scala 129:16]
  assign iwb_stage_io_bru_iWriteBack_ready = iwb_stage_iwriteBack_arb_io_enq_1_ready; // @[WriteBack.scala 129:16]
  assign iwb_stage_io_csr_iWriteBack_ready = iwb_stage_iwriteBack_arb_io_enq_2_ready; // @[WriteBack.scala 129:16]
  assign iwb_stage_io_mem_iWriteBack_ready = iwb_stage_iwriteBack_arb_io_enq_3_ready; // @[WriteBack.scala 129:16]
  assign iwb_stage_io_mul_iWriteBack_0_ready = iwb_stage_iwriteBack_arb_io_enq_4_ready; // @[WriteBack.scala 129:16]
  assign iwb_stage_io_mem_fWriteBack_ready = iwb_stage_fReg_io_exe_writeBack_0_ready; // @[WriteBack.scala 141:28]
  assign iwb_stage_io_commit_0_is_writeback = iwb_stage_io_commit_0_toX ? iwb_stage_iReg_io_commit_0_is_writeback :
    iwb_stage__GEN_7; // @[WriteBack.scala 102:{41,60}]
  assign iwb_stage_iReg_clock = iwb_stage_clock;
  assign iwb_stage_iReg_reset = iwb_stage_reset;
  assign iwb_stage_iReg_io_lookup_0_req_rs1 = iwb_stage_io_xLookup_0_req_rs1; // @[WriteBack.scala 78:23]
  assign iwb_stage_iReg_io_lookup_0_req_rs2 = iwb_stage_io_xLookup_0_req_rs2; // @[WriteBack.scala 78:23]
  assign iwb_stage_iReg_io_rename_0_req_valid = iwb_stage_io_xRename_0_req_valid; // @[WriteBack.scala 76:23]
  assign iwb_stage_iReg_io_rename_0_req_bits_rd0 = iwb_stage_io_xRename_0_req_bits_rd0; // @[WriteBack.scala 76:23]
  assign iwb_stage_iReg_io_rgReq_0_valid = iwb_stage_io_irgReq_0_valid; // @[WriteBack.scala 112:17]
  assign iwb_stage_iReg_io_rgReq_0_bits = iwb_stage_io_irgReq_0_bits; // @[WriteBack.scala 112:17]
  assign iwb_stage_iReg_io_exe_writeBack_0_valid = iwb_stage_iwriteBack_arb_io_deq_0_valid; // @[WriteBack.scala 136:16]
  assign iwb_stage_iReg_io_exe_writeBack_0_bits_rd0 = iwb_stage_iwriteBack_arb_io_deq_0_bits_rd0; // @[WriteBack.scala 136:16]
  assign iwb_stage_iReg_io_exe_writeBack_0_bits_res = iwb_stage_iwriteBack_arb_io_deq_0_bits_res; // @[WriteBack.scala 136:16]
  assign iwb_stage_iReg_io_commit_0_is_comfirm = iwb_stage_io_commit_0_toX & iwb_stage_io_commit_0_is_comfirm; // @[WriteBack.scala 102:{41,60} 84:37]
  assign iwb_stage_iReg_io_commit_0_is_MisPredict = iwb_stage_io_commit_0_is_MisPredict; // @[WriteBack.scala 102:{41,60} 85:37]
  assign iwb_stage_iReg_io_commit_0_is_abort = iwb_stage_io_commit_0_is_abort; // @[WriteBack.scala 102:{41,60} 86:37]
  assign iwb_stage_iReg_io_commit_0_raw = iwb_stage_io_commit_0_toX ? iwb_stage_io_commit_0_raw : 5'h0; // @[WriteBack.scala 102:{41,60} 87:37]
  assign iwb_stage_iReg_io_commit_0_phy = iwb_stage_io_commit_0_toX ? iwb_stage_io_commit_0_phy : 6'h0; // @[WriteBack.scala 102:{41,60} 88:37]
  assign iwb_stage_fReg_clock = iwb_stage_clock;
  assign iwb_stage_fReg_reset = iwb_stage_reset;
  assign iwb_stage_fReg_io_exe_writeBack_0_valid = iwb_stage_io_mem_fWriteBack_valid; // @[WriteBack.scala 141:28]
  assign iwb_stage_fReg_io_exe_writeBack_1_valid = iwb_stage_io_fpu_fWriteBack_0_valid; // @[WriteBack.scala 142:28]
  assign iwb_stage_iwriteBack_arb_io_enq_0_valid = iwb_stage_io_alu_iWriteBack_0_valid; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_0_bits_rd0 = iwb_stage_io_alu_iWriteBack_0_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_0_bits_res = iwb_stage_io_alu_iWriteBack_0_bits_res; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_1_valid = iwb_stage_io_bru_iWriteBack_valid; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_1_bits_rd0 = iwb_stage_io_bru_iWriteBack_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_1_bits_res = iwb_stage_io_bru_iWriteBack_bits_res; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_2_valid = iwb_stage_io_csr_iWriteBack_valid; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_2_bits_rd0 = iwb_stage_io_csr_iWriteBack_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_2_bits_res = iwb_stage_io_csr_iWriteBack_bits_res; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_3_valid = iwb_stage_io_mem_iWriteBack_valid; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_3_bits_rd0 = iwb_stage_io_mem_iWriteBack_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_3_bits_res = iwb_stage_io_mem_iWriteBack_bits_res; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_4_valid = iwb_stage_io_mul_iWriteBack_0_valid; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_4_bits_rd0 = iwb_stage_io_mul_iWriteBack_0_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_4_bits_res = iwb_stage_io_mul_iWriteBack_0_bits_res; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_5_valid = iwb_stage_io_fpu_iWriteBack_0_valid; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_5_bits_rd0 = iwb_stage_io_fpu_iWriteBack_0_bits_rd0; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_enq_5_bits_res = iwb_stage_io_fpu_iWriteBack_0_bits_res; // @[WriteBack.scala 129:16]
  assign iwb_stage_iwriteBack_arb_io_deq_0_ready = iwb_stage_iReg_io_exe_writeBack_0_ready; // @[WriteBack.scala 136:16]
  assign cmm_stage_bctq_mdl_io_enq_0_ready = cmm_stage_bctq_mdl_io_mapper_0 & cmm_stage_bctq_mdl_io_deq_0_ready; // @[RePort.scala 161:22 180:{28,40}]
  assign cmm_stage_bctq_mdl_io_deq_0_valid = cmm_stage_bctq_mdl_io_mapper_0 & cmm_stage_bctq_mdl_io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign cmm_stage_bctq_mdl_io_deq_0_bits_isPredictTaken = cmm_stage_bctq_mdl_io_mapper_0 &
    cmm_stage_bctq_mdl_io_enq_0_bits_isPredictTaken; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_bctq_mdl_io_deq_0_bits_isFinalTaken = cmm_stage_bctq_mdl_io_mapper_0 &
    cmm_stage_bctq_mdl_io_enq_0_bits_isFinalTaken; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_bctq_mdl_io_deq_0_bits_finalTarget = cmm_stage_bctq_mdl_io_mapper_0 ?
    cmm_stage_bctq_mdl_io_enq_0_bits_finalTarget : 64'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_jctq_mdl_io_enq_0_ready = cmm_stage_jctq_mdl_io_mapper_0 & cmm_stage_jctq_mdl_io_deq_0_ready; // @[RePort.scala 161:22 180:{28,40}]
  assign cmm_stage_jctq_mdl_io_deq_0_valid = cmm_stage_jctq_mdl_io_mapper_0 & cmm_stage_jctq_mdl_io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign cmm_stage_jctq_mdl_io_deq_0_bits_btbResp_target = cmm_stage_jctq_mdl_io_mapper_0 ?
    cmm_stage_jctq_mdl_io_enq_0_bits_btbResp_target : 39'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_jctq_mdl_io_deq_0_bits_rasResp_target = cmm_stage_jctq_mdl_io_mapper_0 ?
    cmm_stage_jctq_mdl_io_enq_0_bits_rasResp_target : 39'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_jctq_mdl_io_deq_0_bits_isRas = cmm_stage_jctq_mdl_io_mapper_0 &
    cmm_stage_jctq_mdl_io_enq_0_bits_isRas; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_jctq_mdl_io_deq_0_bits_finalTarget = cmm_stage_jctq_mdl_io_mapper_0 ?
    cmm_stage_jctq_mdl_io_enq_0_bits_finalTarget : 64'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_csrExe_mdl_io_enq_0_ready = cmm_stage_csrExe_mdl_io_mapper_0 & cmm_stage_csrExe_mdl_io_deq_0_ready; // @[RePort.scala 161:22 180:{28,40}]
  assign cmm_stage_csrExe_mdl_io_deq_0_valid = cmm_stage_csrExe_mdl_io_mapper_0 & cmm_stage_csrExe_mdl_io_enq_0_valid; // @[RePort.scala 159:21 180:{28,40}]
  assign cmm_stage_csrExe_mdl_io_deq_0_bits_addr = cmm_stage_csrExe_mdl_io_mapper_0 ?
    cmm_stage_csrExe_mdl_io_enq_0_bits_addr : 12'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_csrExe_mdl_io_deq_0_bits_dat_i = cmm_stage_csrExe_mdl_io_mapper_0 ?
    cmm_stage_csrExe_mdl_io_enq_0_bits_dat_i : 64'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_csrExe_mdl_io_deq_0_bits_op_rw = cmm_stage_csrExe_mdl_io_mapper_0 &
    cmm_stage_csrExe_mdl_io_enq_0_bits_op_rw; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_csrExe_mdl_io_deq_0_bits_op_rs = cmm_stage_csrExe_mdl_io_mapper_0 &
    cmm_stage_csrExe_mdl_io_enq_0_bits_op_rs; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_csrExe_mdl_io_deq_0_bits_op_rc = cmm_stage_csrExe_mdl_io_mapper_0 &
    cmm_stage_csrExe_mdl_io_enq_0_bits_op_rc; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_fcsrExe_mdl_io_deq_0_valid = cmm_stage_fcsrExe_mdl_io_mapper_0 & cmm_stage_fcsrExe_mdl_io_enq_0_valid
    ; // @[RePort.scala 159:21 180:{28,40}]
  assign cmm_stage_fcsrExe_mdl_io_deq_0_bits_addr = cmm_stage_fcsrExe_mdl_io_mapper_0 ?
    cmm_stage_fcsrExe_mdl_io_enq_0_bits_addr : 12'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_fcsrExe_mdl_io_deq_0_bits_dat_i = cmm_stage_fcsrExe_mdl_io_mapper_0 ?
    cmm_stage_fcsrExe_mdl_io_enq_0_bits_dat_i : 64'h0; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rw = cmm_stage_fcsrExe_mdl_io_mapper_0 &
    cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rw; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rs = cmm_stage_fcsrExe_mdl_io_mapper_0 &
    cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rs; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_fcsrExe_mdl_io_deq_0_bits_op_rc = cmm_stage_fcsrExe_mdl_io_mapper_0 &
    cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rc; // @[RePort.scala 160:21 180:{28,40}]
  assign cmm_stage_io_cm_op_0_is_comfirm = cmm_stage__GEN_467 == 2'h3; // @[Commit.scala 324:87]
  assign cmm_stage_io_cm_op_0_is_MisPredict = cmm_stage__GEN_467 == 2'h2; // @[Commit.scala 325:87]
  assign cmm_stage_io_cm_op_0_is_abort = cmm_stage__GEN_467 == 2'h1; // @[Commit.scala 326:87]
  assign cmm_stage_io_cm_op_0_raw = cmm_stage_io_rod_0_bits_rd0_raw; // @[Commit.scala 541:21]
  assign cmm_stage_io_cm_op_0_phy = cmm_stage_io_rod_0_bits_rd0_phy; // @[Commit.scala 540:21]
  assign cmm_stage_io_cm_op_0_toX = cmm_stage_io_rod_0_bits_is_xcmm; // @[Commit.scala 542:21]
  assign cmm_stage_io_cm_op_0_toF = cmm_stage_io_rod_0_bits_is_fcmm; // @[Commit.scala 543:21]
  assign cmm_stage_io_rod_0_ready = cmm_stage_is_retired_0 | cmm_stage_commit_state_is_abort_0; // @[Commit.scala 691:39]
  assign cmm_stage_io_cmm_lsu_is_amo_pending = cmm_stage__io_cmm_lsu_is_amo_pending_T &
    cmm_stage__is_trap_is_exception_is_csr_illegal_T_1; // @[Commit.scala 547:45]
  assign cmm_stage_io_cmm_lsu_is_store_commit_0 = cmm_stage_io_rod_0_bits_is_su & cmm_stage_commit_state_is_comfirm_0; // @[Commit.scala 696:59]
  assign cmm_stage_io_csr_data_valid = cmm_stage_io_csr_addr_valid & cmm_stage__io_csr_data_valid_T_121; // @[Commit.scala 798:42]
  assign cmm_stage_io_csr_data_bits = cmm_stage__io_csr_data_bits_T_177 | cmm_stage__io_csr_data_bits_T_133; // @[Mux.scala 27:73]
  assign cmm_stage_io_csr_cmm_op_ready = cmm_stage_csrExe_mdl_io_enq_0_ready; // @[Commit.scala 337:19 RePort.scala 190:9]
  assign cmm_stage_io_bctq_ready = cmm_stage_bctq_mdl_io_enq_0_ready; // @[Commit.scala 344:19 RePort.scala 190:9]
  assign cmm_stage_io_jctq_ready = cmm_stage_jctq_mdl_io_enq_0_ready; // @[Commit.scala 351:19 RePort.scala 190:9]
  assign cmm_stage_io_cmmRedirect_valid = cmm_stage_commit_state_is_abort_0 ? cmm_stage__GEN_1002 : cmm_stage__GEN_936; // @[Commit.scala 723:38]
  assign cmm_stage_io_cmmRedirect_bits_pc = cmm_stage_commit_state_is_abort_0 ? cmm_stage__GEN_1003 : cmm_stage__GEN_937
    ; // @[Commit.scala 723:38]
  assign cmm_stage_io_ifence = cmm_stage_commit_state_is_abort_0 & cmm_stage_is_fence_i; // @[Commit.scala 841:30]
  assign cmm_stage_io_cmm_mmu_satp = {cmm_stage_csr_state_0_csrfiles_satp_hi,cmm_stage_csrfiles_satp_ppn}; // @[Commit.scala 827:36]
  assign cmm_stage_io_cmm_mmu_priv_lvl_if = cmm_stage_csrfiles_priv_lvl; // @[Commit.scala 830:28]
  assign cmm_stage_io_cmm_mmu_priv_lvl_ls = cmm_stage_csrfiles_mstatus_mprv ? cmm_stage_csrfiles_mstatus_mpp :
    cmm_stage_csrfiles_priv_lvl; // @[Commit.scala 831:34]
  assign cmm_stage_io_cmm_mmu_mstatus = {cmm_stage_csr_state_0_csrfiles_mstatus_hi,
    cmm_stage_csr_state_0_csrfiles_mstatus_lo}; // @[Commit.scala 832:45]
  assign cmm_stage_io_cmm_mmu_sstatus = {cmm_stage_io_csr_data_bits_hi_2,cmm_stage_io_csr_data_bits_lo_2}; // @[Commit.scala 833:45]
  assign cmm_stage_io_cmm_mmu_sfence_vma = cmm_stage_commit_state_is_abort_0 & cmm_stage_is_sfence_vma; // @[Commit.scala 835:30]
  assign cmm_stage_io_dm_hartIsInReset = cmm_stage_emu_reset; // @[Commit.scala 366:23]
  assign cmm_stage_bctq_mdl_io_enq_0_valid = cmm_stage_io_bctq_valid; // @[Commit.scala 344:19 346:12]
  assign cmm_stage_bctq_mdl_io_enq_0_bits_isPredictTaken = cmm_stage_io_bctq_bits_isPredictTaken; // @[Commit.scala 344:19 346:12]
  assign cmm_stage_bctq_mdl_io_enq_0_bits_isFinalTaken = cmm_stage_io_bctq_bits_isFinalTaken; // @[Commit.scala 344:19 346:12]
  assign cmm_stage_bctq_mdl_io_enq_0_bits_finalTarget = cmm_stage_io_bctq_bits_finalTarget; // @[Commit.scala 344:19 346:12]
  assign cmm_stage_bctq_mdl_io_deq_0_ready = cmm_stage_is_retired_0 & cmm_stage_io_rod_0_bits_is_branch; // @[Commit.scala 679:36]
  assign cmm_stage_bctq_mdl_io_mapper_0 = cmm_stage_io_rod_0_bits_is_branch; // @[Commit.scala 357:{42,42}]
  assign cmm_stage_jctq_mdl_io_enq_0_valid = cmm_stage_io_jctq_valid; // @[Commit.scala 351:19 353:12]
  assign cmm_stage_jctq_mdl_io_enq_0_bits_btbResp_target = cmm_stage_io_jctq_bits_btbResp_target; // @[Commit.scala 351:19 353:12]
  assign cmm_stage_jctq_mdl_io_enq_0_bits_rasResp_target = cmm_stage_io_jctq_bits_rasResp_target; // @[Commit.scala 351:19 353:12]
  assign cmm_stage_jctq_mdl_io_enq_0_bits_isRas = cmm_stage_io_jctq_bits_isRas; // @[Commit.scala 351:19 353:12]
  assign cmm_stage_jctq_mdl_io_enq_0_bits_finalTarget = cmm_stage_io_jctq_bits_finalTarget; // @[Commit.scala 351:19 353:12]
  assign cmm_stage_jctq_mdl_io_deq_0_ready = cmm_stage_is_retired_0 & cmm_stage_io_rod_0_bits_is_jalr; // @[Commit.scala 685:36]
  assign cmm_stage_jctq_mdl_io_mapper_0 = cmm_stage_io_rod_0_bits_is_jalr; // @[Commit.scala 358:{42,42}]
  assign cmm_stage_csrExe_mdl_io_enq_0_valid = cmm_stage_io_csr_cmm_op_valid; // @[Commit.scala 337:19 339:12]
  assign cmm_stage_csrExe_mdl_io_enq_0_bits_addr = cmm_stage_io_csr_cmm_op_bits_addr; // @[Commit.scala 337:19 339:12]
  assign cmm_stage_csrExe_mdl_io_enq_0_bits_dat_i = cmm_stage_io_csr_cmm_op_bits_dat_i; // @[Commit.scala 337:19 339:12]
  assign cmm_stage_csrExe_mdl_io_enq_0_bits_op_rw = cmm_stage_io_csr_cmm_op_bits_op_rw; // @[Commit.scala 337:19 339:12]
  assign cmm_stage_csrExe_mdl_io_enq_0_bits_op_rs = cmm_stage_io_csr_cmm_op_bits_op_rs; // @[Commit.scala 337:19 339:12]
  assign cmm_stage_csrExe_mdl_io_enq_0_bits_op_rc = cmm_stage_io_csr_cmm_op_bits_op_rc; // @[Commit.scala 337:19 339:12]
  assign cmm_stage_csrExe_mdl_io_deq_0_ready = cmm_stage_commit_state_is_comfirm_0 & cmm_stage_io_rod_0_bits_is_csr; // @[Commit.scala 802:51]
  assign cmm_stage_csrExe_mdl_io_mapper_0 = cmm_stage_io_rod_0_bits_is_csr; // @[Commit.scala 360:{48,48}]
  assign cmm_stage_fcsrExe_mdl_io_enq_0_valid = cmm_stage_io_fcsr_cmm_op_0_valid; // @[RePort.scala 190:9]
  assign cmm_stage_fcsrExe_mdl_io_enq_0_bits_addr = cmm_stage_io_fcsr_cmm_op_0_bits_addr; // @[RePort.scala 190:9]
  assign cmm_stage_fcsrExe_mdl_io_enq_0_bits_dat_i = cmm_stage_io_fcsr_cmm_op_0_bits_dat_i; // @[RePort.scala 190:9]
  assign cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rw = cmm_stage_io_fcsr_cmm_op_0_bits_op_rw; // @[RePort.scala 190:9]
  assign cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rs = cmm_stage_io_fcsr_cmm_op_0_bits_op_rs; // @[RePort.scala 190:9]
  assign cmm_stage_fcsrExe_mdl_io_enq_0_bits_op_rc = cmm_stage_io_fcsr_cmm_op_0_bits_op_rc; // @[RePort.scala 190:9]
  assign cmm_stage_fcsrExe_mdl_io_deq_0_ready = cmm_stage_commit_state_is_comfirm_0 & cmm_stage_io_rod_0_bits_is_fcsr; // @[Commit.scala 812:34]
  assign cmm_stage_fcsrExe_mdl_io_mapper_0 = cmm_stage_io_rod_0_bits_is_fcsr; // @[Commit.scala 361:{50,50}]
  assign i_mmu_itlb_random_idx_prng_io_out_0 = i_mmu_itlb_random_idx_prng_state_0; // @[PRNG.scala 78:10]
  assign i_mmu_itlb_random_idx_prng_io_out_1 = i_mmu_itlb_random_idx_prng_state_1; // @[PRNG.scala 78:10]
  assign i_mmu_itlb_random_idx_prng_1_io_out_0 = i_mmu_itlb_random_idx_prng_1_state_0; // @[PRNG.scala 78:10]
  assign i_mmu_itlb_random_idx_prng_1_io_out_1 = i_mmu_itlb_random_idx_prng_1_state_1; // @[PRNG.scala 78:10]
  assign i_mmu_itlb_random_idx_prng_2_io_out_0 = i_mmu_itlb_random_idx_prng_2_state_0; // @[PRNG.scala 78:10]
  assign i_mmu_itlb_random_idx_prng_2_io_out_1 = i_mmu_itlb_random_idx_prng_2_state_1; // @[PRNG.scala 78:10]
  assign i_mmu_itlb_random_idx_prng_3_io_out_0 = i_mmu_itlb_random_idx_prng_3_state_0; // @[PRNG.scala 78:10]
  assign i_mmu_itlb_random_idx_prng_3_io_out_1 = i_mmu_itlb_random_idx_prng_3_state_1; // @[PRNG.scala 78:10]
  assign i_mmu_itlb_io_pte_o_value = i_mmu_itlb__io_pte_o_T_9 | i_mmu_itlb__io_pte_o_T_10; // @[Mux.scala 27:73]
  assign i_mmu_itlb_io_pte_o_is_giga_page = i_mmu_itlb__io_pte_o_T_3 | i_mmu_itlb__io_pte_o_T_4; // @[Mux.scala 27:73]
  assign i_mmu_itlb_io_pte_o_is_mega_page = i_mmu_itlb__io_pte_o_T | i_mmu_itlb__io_pte_o_T_1; // @[Mux.scala 27:73]
  assign i_mmu_itlb_io_is_hit = i_mmu_itlb__io_is_hit_T_3 & i_mmu_itlb_io_req_valid; // @[TLB.scala 113:41]
  assign i_mmu_itlb_random_idx_prng_clock = i_mmu_itlb_clock;
  assign i_mmu_itlb_random_idx_prng_reset = i_mmu_itlb_reset;
  assign i_mmu_itlb_random_idx_prng_1_clock = i_mmu_itlb_clock;
  assign i_mmu_itlb_random_idx_prng_1_reset = i_mmu_itlb_reset;
  assign i_mmu_itlb_random_idx_prng_2_clock = i_mmu_itlb_clock;
  assign i_mmu_itlb_random_idx_prng_2_reset = i_mmu_itlb_reset;
  assign i_mmu_itlb_random_idx_prng_3_clock = i_mmu_itlb_clock;
  assign i_mmu_itlb_random_idx_prng_3_reset = i_mmu_itlb_reset;
  assign i_mmu_dtlb_random_idx_prng_io_out_0 = i_mmu_dtlb_random_idx_prng_state_0; // @[PRNG.scala 78:10]
  assign i_mmu_dtlb_random_idx_prng_io_out_1 = i_mmu_dtlb_random_idx_prng_state_1; // @[PRNG.scala 78:10]
  assign i_mmu_dtlb_random_idx_prng_1_io_out_0 = i_mmu_dtlb_random_idx_prng_1_state_0; // @[PRNG.scala 78:10]
  assign i_mmu_dtlb_random_idx_prng_1_io_out_1 = i_mmu_dtlb_random_idx_prng_1_state_1; // @[PRNG.scala 78:10]
  assign i_mmu_dtlb_random_idx_prng_2_io_out_0 = i_mmu_dtlb_random_idx_prng_2_state_0; // @[PRNG.scala 78:10]
  assign i_mmu_dtlb_random_idx_prng_2_io_out_1 = i_mmu_dtlb_random_idx_prng_2_state_1; // @[PRNG.scala 78:10]
  assign i_mmu_dtlb_random_idx_prng_3_io_out_0 = i_mmu_dtlb_random_idx_prng_3_state_0; // @[PRNG.scala 78:10]
  assign i_mmu_dtlb_random_idx_prng_3_io_out_1 = i_mmu_dtlb_random_idx_prng_3_state_1; // @[PRNG.scala 78:10]
  assign i_mmu_dtlb_io_pte_o_value = i_mmu_dtlb__io_pte_o_T_9 | i_mmu_dtlb__io_pte_o_T_10; // @[Mux.scala 27:73]
  assign i_mmu_dtlb_io_pte_o_is_giga_page = i_mmu_dtlb__io_pte_o_T_3 | i_mmu_dtlb__io_pte_o_T_4; // @[Mux.scala 27:73]
  assign i_mmu_dtlb_io_pte_o_is_mega_page = i_mmu_dtlb__io_pte_o_T | i_mmu_dtlb__io_pte_o_T_1; // @[Mux.scala 27:73]
  assign i_mmu_dtlb_io_is_hit = i_mmu_dtlb__io_is_hit_T_3 & i_mmu_dtlb_io_req_valid; // @[TLB.scala 113:41]
  assign i_mmu_dtlb_random_idx_prng_clock = i_mmu_dtlb_clock;
  assign i_mmu_dtlb_random_idx_prng_reset = i_mmu_dtlb_reset;
  assign i_mmu_dtlb_random_idx_prng_1_clock = i_mmu_dtlb_clock;
  assign i_mmu_dtlb_random_idx_prng_1_reset = i_mmu_dtlb_reset;
  assign i_mmu_dtlb_random_idx_prng_2_clock = i_mmu_dtlb_clock;
  assign i_mmu_dtlb_random_idx_prng_2_reset = i_mmu_dtlb_reset;
  assign i_mmu_dtlb_random_idx_prng_3_clock = i_mmu_dtlb_clock;
  assign i_mmu_dtlb_random_idx_prng_3_reset = i_mmu_dtlb_reset;
  assign i_mmu_iptw_walkRspBits_is_access_fault_mdl_io_is_fault = 1'h0; // @[PMP.scala 56:36]
  assign i_mmu_iptw_io_ptw_i_ready = i_mmu_iptw__io_ptw_i_ready_T_4 & i_mmu_iptw__io_ptw_o_valid_T; // @[PTW.scala 393:94]
  assign i_mmu_iptw_io_ptw_o_valid = i_mmu_iptw_walkRspValid & i_mmu_iptw__io_ptw_o_valid_T; // @[PTW.scala 390:34]
  assign i_mmu_iptw_io_ptw_o_bits_is_X = i_mmu_iptw_walkRspBits_is_X; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_renew_value = i_mmu_iptw_walkRspBits_renew_value; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_renew_is_giga_page = i_mmu_iptw_walkRspBits_renew_is_giga_page; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_renew_is_mega_page = i_mmu_iptw_walkRspBits_renew_is_mega_page; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_renew_asid = i_mmu_iptw_walkRspBits_renew_asid; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_renew_vpn_0 = i_mmu_iptw_walkRspBits_renew_vpn_0; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_renew_vpn_1 = i_mmu_iptw_walkRspBits_renew_vpn_1; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_renew_vpn_2 = i_mmu_iptw_walkRspBits_renew_vpn_2; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_is_ptw_fail = i_mmu_iptw_walkRspBits_is_ptw_fail; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_o_bits_is_access_fault = i_mmu_iptw_walkRspBits_is_access_fault; // @[PTW.scala 389:18]
  assign i_mmu_iptw_io_ptw_get_valid = i_mmu_iptw_ptw_get_valid; // @[PTW.scala 345:20]
  assign i_mmu_iptw_io_ptw_get_bits_opcode = 3'h4; // @[Edges.scala 447:17 448:15]
  assign i_mmu_iptw_io_ptw_get_bits_param = 3'h0; // @[Edges.scala 447:17 449:15]
  assign i_mmu_iptw_io_ptw_get_bits_size = 3'h4; // @[Edges.scala 447:17 450:15]
  assign i_mmu_iptw_io_ptw_get_bits_source = 1'h0; // @[Edges.scala 447:17 451:15]
  assign i_mmu_iptw_io_ptw_get_bits_address = i_mmu_iptw__io_ptw_get_bits_T_1[31:0]; // @[Edges.scala 447:17 452:15]
  assign i_mmu_iptw_io_ptw_get_bits_mask = 8'hff; // @[Cat.scala 33:92]
  assign i_mmu_iptw_io_ptw_get_bits_data = 64'h0; // @[Edges.scala 447:17 454:15]
  assign i_mmu_iptw_io_ptw_get_bits_corrupt = 1'h0; // @[Edges.scala 447:17 455:15]
  assign i_mmu_iptw_io_ptw_access_ready = i_mmu_iptw_ptw_access_ready; // @[PTW.scala 346:23]
  assign i_mmu_dptw_walkRspBits_is_access_fault_mdl_io_is_fault = 1'h0; // @[PMP.scala 56:36]
  assign i_mmu_dptw_io_ptw_i_ready = i_mmu_dptw__io_ptw_i_ready_T_4 & i_mmu_dptw__io_ptw_o_valid_T; // @[PTW.scala 393:94]
  assign i_mmu_dptw_io_ptw_o_valid = i_mmu_dptw_walkRspValid & i_mmu_dptw__io_ptw_o_valid_T; // @[PTW.scala 390:34]
  assign i_mmu_dptw_io_ptw_o_bits_is_X = i_mmu_dptw_walkRspBits_is_X; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_renew_value = i_mmu_dptw_walkRspBits_renew_value; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_renew_is_giga_page = i_mmu_dptw_walkRspBits_renew_is_giga_page; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_renew_is_mega_page = i_mmu_dptw_walkRspBits_renew_is_mega_page; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_renew_asid = i_mmu_dptw_walkRspBits_renew_asid; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_renew_vpn_0 = i_mmu_dptw_walkRspBits_renew_vpn_0; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_renew_vpn_1 = i_mmu_dptw_walkRspBits_renew_vpn_1; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_renew_vpn_2 = i_mmu_dptw_walkRspBits_renew_vpn_2; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_is_ptw_fail = i_mmu_dptw_walkRspBits_is_ptw_fail; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_o_bits_is_access_fault = i_mmu_dptw_walkRspBits_is_access_fault; // @[PTW.scala 389:18]
  assign i_mmu_dptw_io_ptw_get_valid = i_mmu_dptw_ptw_get_valid; // @[PTW.scala 345:20]
  assign i_mmu_dptw_io_ptw_get_bits_opcode = 3'h4; // @[Edges.scala 447:17 448:15]
  assign i_mmu_dptw_io_ptw_get_bits_param = 3'h0; // @[Edges.scala 447:17 449:15]
  assign i_mmu_dptw_io_ptw_get_bits_size = 3'h4; // @[Edges.scala 447:17 450:15]
  assign i_mmu_dptw_io_ptw_get_bits_source = 1'h1; // @[Edges.scala 447:17 451:15]
  assign i_mmu_dptw_io_ptw_get_bits_address = i_mmu_dptw__io_ptw_get_bits_T_1[31:0]; // @[Edges.scala 447:17 452:15]
  assign i_mmu_dptw_io_ptw_get_bits_mask = 8'hff; // @[Cat.scala 33:92]
  assign i_mmu_dptw_io_ptw_get_bits_data = 64'h0; // @[Edges.scala 447:17 454:15]
  assign i_mmu_dptw_io_ptw_get_bits_corrupt = 1'h0; // @[Edges.scala 447:17 455:15]
  assign i_mmu_dptw_io_ptw_access_ready = i_mmu_dptw_ptw_access_ready; // @[PTW.scala 346:23]
  assign i_mmu_io_mmu_if_bits_is_access_fault_mdl_io_is_fault = 1'h0; // @[PMP.scala 56:36]
  assign i_mmu_io_mmu_lsu_bits_is_access_fault_mdl_io_is_fault = 1'h0; // @[PMP.scala 56:36]
  assign i_mmu_ptwGetArb_io_in_0_ready = i_mmu_ptwGetArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign i_mmu_ptwGetArb_io_in_1_ready = i_mmu_ptwGetArb_grant_1 & i_mmu_ptwGetArb_io_out_ready; // @[Arbiter.scala 146:19]
  assign i_mmu_ptwGetArb_io_out_valid = i_mmu_ptwGetArb__io_out_valid_T | i_mmu_ptwGetArb_io_in_1_valid; // @[Arbiter.scala 147:31]
  assign i_mmu_ptwGetArb_io_out_bits_opcode = i_mmu_ptwGetArb_io_in_0_valid ? i_mmu_ptwGetArb_io_in_0_bits_opcode :
    i_mmu_ptwGetArb_io_in_1_bits_opcode; // @[Arbiter.scala 136:15 138:26 140:19]
  assign i_mmu_ptwGetArb_io_out_bits_param = i_mmu_ptwGetArb_io_in_0_valid ? i_mmu_ptwGetArb_io_in_0_bits_param :
    i_mmu_ptwGetArb_io_in_1_bits_param; // @[Arbiter.scala 136:15 138:26 140:19]
  assign i_mmu_ptwGetArb_io_out_bits_size = i_mmu_ptwGetArb_io_in_0_valid ? i_mmu_ptwGetArb_io_in_0_bits_size :
    i_mmu_ptwGetArb_io_in_1_bits_size; // @[Arbiter.scala 136:15 138:26 140:19]
  assign i_mmu_ptwGetArb_io_out_bits_source = i_mmu_ptwGetArb_io_in_0_valid ? i_mmu_ptwGetArb_io_in_0_bits_source :
    i_mmu_ptwGetArb_io_in_1_bits_source; // @[Arbiter.scala 136:15 138:26 140:19]
  assign i_mmu_ptwGetArb_io_out_bits_address = i_mmu_ptwGetArb_io_in_0_valid ? i_mmu_ptwGetArb_io_in_0_bits_address :
    i_mmu_ptwGetArb_io_in_1_bits_address; // @[Arbiter.scala 136:15 138:26 140:19]
  assign i_mmu_ptwGetArb_io_out_bits_mask = i_mmu_ptwGetArb_io_in_0_valid ? i_mmu_ptwGetArb_io_in_0_bits_mask :
    i_mmu_ptwGetArb_io_in_1_bits_mask; // @[Arbiter.scala 136:15 138:26 140:19]
  assign i_mmu_ptwGetArb_io_out_bits_data = i_mmu_ptwGetArb_io_in_0_valid ? i_mmu_ptwGetArb_io_in_0_bits_data :
    i_mmu_ptwGetArb_io_in_1_bits_data; // @[Arbiter.scala 136:15 138:26 140:19]
  assign i_mmu_ptwGetArb_io_out_bits_corrupt = i_mmu_ptwGetArb_io_in_0_valid ? i_mmu_ptwGetArb_io_in_0_bits_corrupt :
    i_mmu_ptwGetArb_io_in_1_bits_corrupt; // @[Arbiter.scala 136:15 138:26 140:19]
  assign i_mmu_io_if_mmu_ready = i_mmu__io_if_mmu_ready_T_2 & i_mmu__io_if_mmu_ready_T_3; // @[MMU.scala 160:35]
  assign i_mmu_io_mmu_if_valid = i_mmu__io_if_mmu_ready_T_3 & i_mmu__io_mmu_if_valid_T_6; // @[MMU.scala 214:18]
  assign i_mmu_io_mmu_if_bits_vaddr = i_mmu_io_if_mmu_bits_vaddr; // @[MMU.scala 198:26]
  assign i_mmu_io_mmu_if_bits_paddr = i_mmu_is_bypass_if ? i_mmu_io_if_mmu_bits_vaddr : i_mmu_ipaddr_paddr; // @[MMU.scala 196:21]
  assign i_mmu_io_mmu_if_bits_is_paging_fault = i_mmu__iptw_io_ptw_i_valid_T_2 &
    i_mmu__io_mmu_if_bits_is_paging_fault_T_7; // @[MMU.scala 207:21]
  assign i_mmu_io_mmu_if_bits_is_access_fault = i_mmu__io_mmu_if_bits_is_access_fault_T_3 |
    i_mmu__io_mmu_if_bits_is_access_fault_T_5; // @[MMU.scala 203:92]
  assign i_mmu_io_lsu_mmu_ready = i_mmu__io_lsu_mmu_ready_T_2 & i_mmu__io_lsu_mmu_ready_T_3; // @[MMU.scala 168:37]
  assign i_mmu_io_mmu_lsu_valid = i_mmu__io_mmu_lsu_valid_T_2 & i_mmu__io_mmu_lsu_valid_T_9; // @[MMU.scala 245:34]
  assign i_mmu_io_mmu_lsu_bits_paddr = i_mmu_is_bypass_ls ? i_mmu_io_lsu_mmu_bits_vaddr : i_mmu_dpaddr_paddr; // @[MMU.scala 228:21]
  assign i_mmu_io_mmu_lsu_bits_is_paging_fault = i_mmu__dptw_io_ptw_i_valid_T_2 &
    i_mmu__io_mmu_lsu_bits_is_paging_fault_T_9; // @[MMU.scala 239:21]
  assign i_mmu_io_mmu_lsu_bits_is_access_fault = i_mmu__io_mmu_lsu_bits_is_access_fault_T_4 |
    i_mmu__io_mmu_lsu_bits_is_access_fault_T_6; // @[MMU.scala 235:95]
  assign i_mmu_io_ptw_get_valid = i_mmu_ptwGetArb_io_out_valid; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_get_bits_opcode = i_mmu_ptwGetArb_io_out_bits_opcode; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_get_bits_param = i_mmu_ptwGetArb_io_out_bits_param; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_get_bits_size = i_mmu_ptwGetArb_io_out_bits_size; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_get_bits_source = i_mmu_ptwGetArb_io_out_bits_source; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_get_bits_address = i_mmu_ptwGetArb_io_out_bits_address; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_get_bits_mask = i_mmu_ptwGetArb_io_out_bits_mask; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_get_bits_data = i_mmu_ptwGetArb_io_out_bits_data; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_get_bits_corrupt = i_mmu_ptwGetArb_io_out_bits_corrupt; // @[MMU.scala 289:14]
  assign i_mmu_io_ptw_access_ready = i_mmu__T_23 ? i_mmu_iptw_io_ptw_access_ready : i_mmu__GEN_4; // @[MMU.scala 292:45 293:24]
  assign i_mmu_itlb_clock = i_mmu_clock;
  assign i_mmu_itlb_reset = i_mmu_reset;
  assign i_mmu_itlb_io_req_valid = i_mmu_io_if_mmu_valid; // @[MMU.scala 156:21]
  assign i_mmu_itlb_io_req_bits_vaddr = i_mmu_io_if_mmu_bits_vaddr; // @[MMU.scala 157:21]
  assign i_mmu_itlb_io_asid_i = i_mmu_io_cmm_mmu_satp[59:44]; // @[MMU.scala 158:37]
  assign i_mmu_itlb_io_tlb_renew_valid = i_mmu__itlb_io_tlb_renew_valid_T_3 & i_mmu__io_if_mmu_ready_T_3; // @[MMU.scala 268:110]
  assign i_mmu_itlb_io_tlb_renew_bits_value = i_mmu_iptw_io_ptw_o_bits_renew_value; // @[MMU.scala 265:26]
  assign i_mmu_itlb_io_tlb_renew_bits_is_giga_page = i_mmu_iptw_io_ptw_o_bits_renew_is_giga_page; // @[MMU.scala 265:26]
  assign i_mmu_itlb_io_tlb_renew_bits_is_mega_page = i_mmu_iptw_io_ptw_o_bits_renew_is_mega_page; // @[MMU.scala 265:26]
  assign i_mmu_itlb_io_tlb_renew_bits_asid = i_mmu_iptw_io_ptw_o_bits_renew_asid; // @[MMU.scala 265:26]
  assign i_mmu_itlb_io_tlb_renew_bits_vpn_0 = i_mmu_iptw_io_ptw_o_bits_renew_vpn_0; // @[MMU.scala 265:26]
  assign i_mmu_itlb_io_tlb_renew_bits_vpn_1 = i_mmu_iptw_io_ptw_o_bits_renew_vpn_1; // @[MMU.scala 265:26]
  assign i_mmu_itlb_io_tlb_renew_bits_vpn_2 = i_mmu_iptw_io_ptw_o_bits_renew_vpn_2; // @[MMU.scala 265:26]
  assign i_mmu_itlb_io_sfence_vma = i_mmu_io_cmm_mmu_sfence_vma; // @[MMU.scala 298:22]
  assign i_mmu_dtlb_clock = i_mmu_clock;
  assign i_mmu_dtlb_reset = i_mmu_reset;
  assign i_mmu_dtlb_io_req_valid = i_mmu_io_lsu_mmu_valid; // @[MMU.scala 164:21]
  assign i_mmu_dtlb_io_req_bits_vaddr = i_mmu_io_lsu_mmu_bits_vaddr; // @[MMU.scala 165:21]
  assign i_mmu_dtlb_io_asid_i = i_mmu_io_cmm_mmu_satp[59:44]; // @[MMU.scala 166:37]
  assign i_mmu_dtlb_io_tlb_renew_valid = i_mmu__dtlb_io_tlb_renew_valid_T_4 & i_mmu__io_lsu_mmu_ready_T_3; // @[MMU.scala 269:110]
  assign i_mmu_dtlb_io_tlb_renew_bits_value = i_mmu_dptw_io_ptw_o_bits_renew_value; // @[MMU.scala 266:26]
  assign i_mmu_dtlb_io_tlb_renew_bits_is_giga_page = i_mmu_dptw_io_ptw_o_bits_renew_is_giga_page; // @[MMU.scala 266:26]
  assign i_mmu_dtlb_io_tlb_renew_bits_is_mega_page = i_mmu_dptw_io_ptw_o_bits_renew_is_mega_page; // @[MMU.scala 266:26]
  assign i_mmu_dtlb_io_tlb_renew_bits_asid = i_mmu_dptw_io_ptw_o_bits_renew_asid; // @[MMU.scala 266:26]
  assign i_mmu_dtlb_io_tlb_renew_bits_vpn_0 = i_mmu_dptw_io_ptw_o_bits_renew_vpn_0; // @[MMU.scala 266:26]
  assign i_mmu_dtlb_io_tlb_renew_bits_vpn_1 = i_mmu_dptw_io_ptw_o_bits_renew_vpn_1; // @[MMU.scala 266:26]
  assign i_mmu_dtlb_io_tlb_renew_bits_vpn_2 = i_mmu_dptw_io_ptw_o_bits_renew_vpn_2; // @[MMU.scala 266:26]
  assign i_mmu_dtlb_io_sfence_vma = i_mmu_io_cmm_mmu_sfence_vma; // @[MMU.scala 299:22]
  assign i_mmu_iptw_clock = i_mmu_clock;
  assign i_mmu_iptw_reset = i_mmu_reset;
  assign i_mmu_iptw_io_ptw_i_valid = i_mmu__iptw_io_ptw_i_valid_T_3 & i_mmu__io_if_mmu_ready_T_3; // @[MMU.scala 180:76]
  assign i_mmu_iptw_io_ptw_i_bits_is_X = i_mmu_io_if_mmu_bits_is_X; // @[MMU.scala 181:23]
  assign i_mmu_iptw_io_ptw_i_bits_vaddr = i_mmu_io_if_mmu_bits_vaddr; // @[MMU.scala 181:23]
  assign i_mmu_iptw_io_ptw_o_ready = i_mmu__iptw_io_ptw_o_ready_T | i_mmu_io_if_flush; // @[MMU.scala 259:55]
  assign i_mmu_iptw_io_cmm_mmu_satp = i_mmu_io_cmm_mmu_satp; // @[MMU.scala 174:19]
  assign i_mmu_iptw_io_cmm_mmu_sfence_vma = i_mmu_io_cmm_mmu_sfence_vma; // @[MMU.scala 174:19]
  assign i_mmu_iptw_io_ptw_get_ready = i_mmu_ptwGetArb_io_in_0_ready; // @[MMU.scala 287:22]
  assign i_mmu_iptw_io_ptw_access_valid = i_mmu__T_23 & i_mmu_io_ptw_access_valid; // @[MMU.scala 292:45 293:24 279:28]
  assign i_mmu_iptw_io_ptw_access_bits_opcode = i_mmu__T_23 ? i_mmu_io_ptw_access_bits_opcode : 3'h0; // @[MMU.scala 292:45 293:24 281:27]
  assign i_mmu_iptw_io_ptw_access_bits_size = i_mmu__T_23 ? i_mmu_io_ptw_access_bits_size : 3'h0; // @[MMU.scala 292:45 293:24 281:27]
  assign i_mmu_iptw_io_ptw_access_bits_data = i_mmu__T_23 ? i_mmu_io_ptw_access_bits_data : 64'h0; // @[MMU.scala 292:45 293:24 281:27]
  assign i_mmu_dptw_clock = i_mmu_clock;
  assign i_mmu_dptw_reset = i_mmu_reset;
  assign i_mmu_dptw_io_ptw_i_valid = i_mmu__dptw_io_ptw_i_valid_T_3 & i_mmu__io_lsu_mmu_ready_T_3; // @[MMU.scala 183:77]
  assign i_mmu_dptw_io_ptw_i_bits_is_X = i_mmu_io_lsu_mmu_bits_is_X; // @[MMU.scala 184:23]
  assign i_mmu_dptw_io_ptw_i_bits_vaddr = i_mmu_io_lsu_mmu_bits_vaddr; // @[MMU.scala 184:23]
  assign i_mmu_dptw_io_ptw_o_ready = i_mmu__dptw_io_ptw_o_ready_T | i_mmu_io_lsu_flush; // @[MMU.scala 262:55]
  assign i_mmu_dptw_io_cmm_mmu_satp = i_mmu_io_cmm_mmu_satp; // @[MMU.scala 175:19]
  assign i_mmu_dptw_io_cmm_mmu_sfence_vma = i_mmu_io_cmm_mmu_sfence_vma; // @[MMU.scala 175:19]
  assign i_mmu_dptw_io_ptw_get_ready = i_mmu_ptwGetArb_io_in_1_ready; // @[MMU.scala 288:22]
  assign i_mmu_dptw_io_ptw_access_valid = i_mmu__T_23 ? 1'h0 : i_mmu__GEN_5; // @[MMU.scala 280:28 292:45]
  assign i_mmu_dptw_io_ptw_access_bits_opcode = i_mmu__T_23 ? 3'h0 : i_mmu__GEN_6; // @[MMU.scala 282:27 292:45]
  assign i_mmu_dptw_io_ptw_access_bits_size = i_mmu__T_23 ? 3'h0 : i_mmu__GEN_8; // @[MMU.scala 282:27 292:45]
  assign i_mmu_dptw_io_ptw_access_bits_data = i_mmu__T_23 ? 64'h0 : i_mmu__GEN_12; // @[MMU.scala 282:27 292:45]
  assign i_mmu_ptwGetArb_io_in_0_valid = i_mmu_iptw_io_ptw_get_valid; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_0_bits_opcode = i_mmu_iptw_io_ptw_get_bits_opcode; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_0_bits_param = i_mmu_iptw_io_ptw_get_bits_param; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_0_bits_size = i_mmu_iptw_io_ptw_get_bits_size; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_0_bits_source = i_mmu_iptw_io_ptw_get_bits_source; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_0_bits_address = i_mmu_iptw_io_ptw_get_bits_address; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_0_bits_mask = i_mmu_iptw_io_ptw_get_bits_mask; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_0_bits_data = i_mmu_iptw_io_ptw_get_bits_data; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_0_bits_corrupt = i_mmu_iptw_io_ptw_get_bits_corrupt; // @[MMU.scala 287:22]
  assign i_mmu_ptwGetArb_io_in_1_valid = i_mmu_dptw_io_ptw_get_valid; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_in_1_bits_opcode = i_mmu_dptw_io_ptw_get_bits_opcode; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_in_1_bits_param = i_mmu_dptw_io_ptw_get_bits_param; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_in_1_bits_size = i_mmu_dptw_io_ptw_get_bits_size; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_in_1_bits_source = i_mmu_dptw_io_ptw_get_bits_source; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_in_1_bits_address = i_mmu_dptw_io_ptw_get_bits_address; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_in_1_bits_mask = i_mmu_dptw_io_ptw_get_bits_mask; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_in_1_bits_data = i_mmu_dptw_io_ptw_get_bits_data; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_in_1_bits_corrupt = i_mmu_dptw_io_ptw_get_bits_corrupt; // @[MMU.scala 288:22]
  assign i_mmu_ptwGetArb_io_out_ready = i_mmu_io_ptw_get_ready; // @[MMU.scala 289:14]
  assign prefetcher_io_intent_valid = 1'h0; // @[PreFetcher.scala 70:21]
  assign prefetcher_io_intent_bits_opcode = 3'h0; // @[PreFetcher.scala 71:{35,35}]
  assign prefetcher_io_intent_bits_param = 3'h0; // @[PreFetcher.scala 71:{35,35}]
  assign prefetcher_io_intent_bits_size = 3'h0; // @[PreFetcher.scala 71:{35,35}]
  assign prefetcher_io_intent_bits_source = 1'h0; // @[PreFetcher.scala 71:{35,35}]
  assign prefetcher_io_intent_bits_address = 32'h0; // @[PreFetcher.scala 71:{35,35}]
  assign prefetcher_io_intent_bits_mask = 8'h0; // @[PreFetcher.scala 71:{35,35}]
  assign prefetcher_io_intent_bits_data = 64'h0; // @[PreFetcher.scala 71:{35,35}]
  assign prefetcher_io_intent_bits_corrupt = 1'h0; // @[PreFetcher.scala 71:{35,35}]
  assign prefetcher_io_hintAck_ready = 1'h1; // @[PreFetcher.scala 98:20]
  assign auto_prefetch_clinet_out_a_valid = prefetcher_io_intent_valid; // @[Nodes.scala 1207:84 rift2Core.scala 343:24]
  assign auto_prefetch_clinet_out_a_bits_opcode = prefetcher_io_intent_bits_opcode; // @[Nodes.scala 1207:84 rift2Core.scala 344:23]
  assign auto_prefetch_clinet_out_a_bits_param = prefetcher_io_intent_bits_param; // @[Nodes.scala 1207:84 rift2Core.scala 344:23]
  assign auto_prefetch_clinet_out_a_bits_size = prefetcher_io_intent_bits_size; // @[Nodes.scala 1207:84 rift2Core.scala 344:23]
  assign auto_prefetch_clinet_out_a_bits_source = prefetcher_io_intent_bits_source; // @[Nodes.scala 1207:84 rift2Core.scala 344:23]
  assign auto_prefetch_clinet_out_a_bits_address = prefetcher_io_intent_bits_address; // @[Nodes.scala 1207:84 rift2Core.scala 344:23]
  assign auto_prefetch_clinet_out_a_bits_mask = prefetcher_io_intent_bits_mask; // @[Nodes.scala 1207:84 rift2Core.scala 344:23]
  assign auto_prefetch_clinet_out_a_bits_data = prefetcher_io_intent_bits_data; // @[Nodes.scala 1207:84 rift2Core.scala 344:23]
  assign auto_prefetch_clinet_out_a_bits_corrupt = prefetcher_io_intent_bits_corrupt; // @[Nodes.scala 1207:84 rift2Core.scala 344:23]
  assign auto_prefetch_clinet_out_d_ready = prefetcher_io_hintAck_ready; // @[Nodes.scala 1207:84 rift2Core.scala 346:24]
  assign auto_mmu_client_out_a_valid = i_mmu_io_ptw_get_valid; // @[Nodes.scala 1207:84 rift2Core.scala 331:19]
  assign auto_mmu_client_out_a_bits_opcode = i_mmu_io_ptw_get_bits_opcode; // @[Nodes.scala 1207:84 rift2Core.scala 332:18]
  assign auto_mmu_client_out_a_bits_param = i_mmu_io_ptw_get_bits_param; // @[Nodes.scala 1207:84 rift2Core.scala 332:18]
  assign auto_mmu_client_out_a_bits_size = i_mmu_io_ptw_get_bits_size; // @[Nodes.scala 1207:84 rift2Core.scala 332:18]
  assign auto_mmu_client_out_a_bits_source = i_mmu_io_ptw_get_bits_source; // @[Nodes.scala 1207:84 rift2Core.scala 332:18]
  assign auto_mmu_client_out_a_bits_address = i_mmu_io_ptw_get_bits_address; // @[Nodes.scala 1207:84 rift2Core.scala 332:18]
  assign auto_mmu_client_out_a_bits_mask = i_mmu_io_ptw_get_bits_mask; // @[Nodes.scala 1207:84 rift2Core.scala 332:18]
  assign auto_mmu_client_out_a_bits_data = i_mmu_io_ptw_get_bits_data; // @[Nodes.scala 1207:84 rift2Core.scala 332:18]
  assign auto_mmu_client_out_a_bits_corrupt = i_mmu_io_ptw_get_bits_corrupt; // @[Nodes.scala 1207:84 rift2Core.scala 332:18]
  assign auto_mmu_client_out_d_ready = i_mmu_io_ptw_access_ready; // @[Nodes.scala 1207:84 rift2Core.scala 334:19]
  assign auto_periph_client_out_a_valid = exe_stage_io_periph_getPut_valid; // @[Nodes.scala 1207:84 rift2Core.scala 327:22]
  assign auto_periph_client_out_a_bits_opcode = exe_stage_io_periph_getPut_bits_opcode; // @[Nodes.scala 1207:84 rift2Core.scala 328:22]
  assign auto_periph_client_out_a_bits_param = exe_stage_io_periph_getPut_bits_param; // @[Nodes.scala 1207:84 rift2Core.scala 328:22]
  assign auto_periph_client_out_a_bits_size = exe_stage_io_periph_getPut_bits_size; // @[Nodes.scala 1207:84 rift2Core.scala 328:22]
  assign auto_periph_client_out_a_bits_source = exe_stage_io_periph_getPut_bits_source; // @[Nodes.scala 1207:84 rift2Core.scala 328:22]
  assign auto_periph_client_out_a_bits_address = exe_stage_io_periph_getPut_bits_address; // @[Nodes.scala 1207:84 rift2Core.scala 328:22]
  assign auto_periph_client_out_a_bits_mask = exe_stage_io_periph_getPut_bits_mask; // @[Nodes.scala 1207:84 rift2Core.scala 328:22]
  assign auto_periph_client_out_a_bits_data = exe_stage_io_periph_getPut_bits_data; // @[Nodes.scala 1207:84 rift2Core.scala 328:22]
  assign auto_periph_client_out_a_bits_corrupt = exe_stage_io_periph_getPut_bits_corrupt; // @[Nodes.scala 1207:84 rift2Core.scala 328:22]
  assign auto_periph_client_out_d_ready = exe_stage_io_periph_access_ready; // @[Nodes.scala 1207:84 rift2Core.scala 326:22]
  assign auto_system_client_out_a_valid = exe_stage_io_system_getPut_valid; // @[Nodes.scala 1207:84 rift2Core.scala 320:22]
  assign auto_system_client_out_a_bits_opcode = exe_stage_io_system_getPut_bits_opcode; // @[Nodes.scala 1207:84 rift2Core.scala 321:22]
  assign auto_system_client_out_a_bits_param = exe_stage_io_system_getPut_bits_param; // @[Nodes.scala 1207:84 rift2Core.scala 321:22]
  assign auto_system_client_out_a_bits_size = exe_stage_io_system_getPut_bits_size; // @[Nodes.scala 1207:84 rift2Core.scala 321:22]
  assign auto_system_client_out_a_bits_source = exe_stage_io_system_getPut_bits_source; // @[Nodes.scala 1207:84 rift2Core.scala 321:22]
  assign auto_system_client_out_a_bits_address = exe_stage_io_system_getPut_bits_address; // @[Nodes.scala 1207:84 rift2Core.scala 321:22]
  assign auto_system_client_out_a_bits_mask = exe_stage_io_system_getPut_bits_mask; // @[Nodes.scala 1207:84 rift2Core.scala 321:22]
  assign auto_system_client_out_a_bits_data = exe_stage_io_system_getPut_bits_data; // @[Nodes.scala 1207:84 rift2Core.scala 321:22]
  assign auto_system_client_out_a_bits_corrupt = exe_stage_io_system_getPut_bits_corrupt; // @[Nodes.scala 1207:84 rift2Core.scala 321:22]
  assign auto_system_client_out_d_ready = exe_stage_io_system_access_ready; // @[Nodes.scala 1207:84 rift2Core.scala 319:22]
  assign auto_dcache_client_out_a_valid = exe_stage_io_missUnit_dcache_acquire_valid; // @[Nodes.scala 1207:84 rift2Core.scala 285:24]
  assign auto_dcache_client_out_a_bits_opcode = exe_stage_io_missUnit_dcache_acquire_bits_opcode; // @[Nodes.scala 1207:84 rift2Core.scala 286:24]
  assign auto_dcache_client_out_a_bits_param = exe_stage_io_missUnit_dcache_acquire_bits_param; // @[Nodes.scala 1207:84 rift2Core.scala 286:24]
  assign auto_dcache_client_out_a_bits_size = exe_stage_io_missUnit_dcache_acquire_bits_size; // @[Nodes.scala 1207:84 rift2Core.scala 286:24]
  assign auto_dcache_client_out_a_bits_source = exe_stage_io_missUnit_dcache_acquire_bits_source; // @[Nodes.scala 1207:84 rift2Core.scala 286:24]
  assign auto_dcache_client_out_a_bits_address = exe_stage_io_missUnit_dcache_acquire_bits_address; // @[Nodes.scala 1207:84 rift2Core.scala 286:24]
  assign auto_dcache_client_out_a_bits_mask = exe_stage_io_missUnit_dcache_acquire_bits_mask; // @[Nodes.scala 1207:84 rift2Core.scala 286:24]
  assign auto_dcache_client_out_a_bits_data = exe_stage_io_missUnit_dcache_acquire_bits_data; // @[Nodes.scala 1207:84 rift2Core.scala 286:24]
  assign auto_dcache_client_out_a_bits_corrupt = exe_stage_io_missUnit_dcache_acquire_bits_corrupt; // @[Nodes.scala 1207:84 rift2Core.scala 286:24]
  assign auto_dcache_client_out_b_ready = exe_stage_io_probeUnit_dcache_probe_ready; // @[Nodes.scala 1207:84 rift2Core.scala 291:24]
  assign auto_dcache_client_out_c_valid = exe_stage_io_writeBackUnit_dcache_release_valid; // @[Nodes.scala 1207:84 rift2Core.scala 293:24]
  assign auto_dcache_client_out_c_bits_opcode = exe_stage_io_writeBackUnit_dcache_release_bits_opcode; // @[Nodes.scala 1207:84 rift2Core.scala 294:24]
  assign auto_dcache_client_out_c_bits_param = exe_stage_io_writeBackUnit_dcache_release_bits_param; // @[Nodes.scala 1207:84 rift2Core.scala 294:24]
  assign auto_dcache_client_out_c_bits_size = exe_stage_io_writeBackUnit_dcache_release_bits_size; // @[Nodes.scala 1207:84 rift2Core.scala 294:24]
  assign auto_dcache_client_out_c_bits_source = exe_stage_io_writeBackUnit_dcache_release_bits_source; // @[Nodes.scala 1207:84 rift2Core.scala 294:24]
  assign auto_dcache_client_out_c_bits_address = exe_stage_io_writeBackUnit_dcache_release_bits_address; // @[Nodes.scala 1207:84 rift2Core.scala 294:24]
  assign auto_dcache_client_out_c_bits_data = exe_stage_io_writeBackUnit_dcache_release_bits_data; // @[Nodes.scala 1207:84 rift2Core.scala 294:24]
  assign auto_dcache_client_out_c_bits_corrupt = exe_stage_io_writeBackUnit_dcache_release_bits_corrupt; // @[Nodes.scala 1207:84 rift2Core.scala 294:24]
  assign auto_dcache_client_out_d_ready = _exe_stage_io_missUnit_dcache_grant_valid_T_2 &
    exe_stage_io_missUnit_dcache_grant_ready | _exe_stage_io_writeBackUnit_dcache_grant_valid_T &
    exe_stage_io_writeBackUnit_dcache_grant_ready; // @[Mux.scala 27:73]
  assign auto_dcache_client_out_e_valid = exe_stage_io_missUnit_dcache_grantAck_valid; // @[Nodes.scala 1207:84 rift2Core.scala 297:24]
  assign auto_dcache_client_out_e_bits_sink = exe_stage_io_missUnit_dcache_grantAck_bits_sink; // @[Nodes.scala 1207:84 rift2Core.scala 298:24]
  assign auto_icache_client_out_a_valid = if2_io_icache_get_valid; // @[Nodes.scala 1207:84 rift2Core.scala 265:22]
  assign auto_icache_client_out_a_bits_opcode = if2_io_icache_get_bits_opcode; // @[Nodes.scala 1207:84 rift2Core.scala 266:21]
  assign auto_icache_client_out_a_bits_param = if2_io_icache_get_bits_param; // @[Nodes.scala 1207:84 rift2Core.scala 266:21]
  assign auto_icache_client_out_a_bits_size = if2_io_icache_get_bits_size; // @[Nodes.scala 1207:84 rift2Core.scala 266:21]
  assign auto_icache_client_out_a_bits_source = if2_io_icache_get_bits_source; // @[Nodes.scala 1207:84 rift2Core.scala 266:21]
  assign auto_icache_client_out_a_bits_address = if2_io_icache_get_bits_address; // @[Nodes.scala 1207:84 rift2Core.scala 266:21]
  assign auto_icache_client_out_a_bits_mask = if2_io_icache_get_bits_mask; // @[Nodes.scala 1207:84 rift2Core.scala 266:21]
  assign auto_icache_client_out_a_bits_data = if2_io_icache_get_bits_data; // @[Nodes.scala 1207:84 rift2Core.scala 266:21]
  assign auto_icache_client_out_a_bits_corrupt = if2_io_icache_get_bits_corrupt; // @[Nodes.scala 1207:84 rift2Core.scala 266:21]
  assign auto_icache_client_out_d_ready = if2_io_icache_access_ready; // @[Nodes.scala 1207:84 rift2Core.scala 263:22]
  assign io_dm_hartIsInReset = cmm_stage_io_dm_hartIsInReset; // @[rift2Core.scala 254:37]
  assign if1_clock = clock;
  assign if1_reset = reset;
  assign if1_io_if4Redirect_valid = if4_io_if4Redirect_valid; // @[rift2Core.scala 118:22]
  assign if1_io_if4Redirect_bits_target = if4_io_if4Redirect_bits_target; // @[rift2Core.scala 118:22]
  assign if1_io_cmmRedirect_valid = cmm_stage_io_cmmRedirect_valid; // @[rift2Core.scala 246:28]
  assign if1_io_cmmRedirect_bits_pc = cmm_stage_io_cmmRedirect_bits_pc; // @[rift2Core.scala 246:28]
  assign if1_io_pc_gen_ready = if2_io_if2_req_ready; // @[rift2Core.scala 120:17]
  assign if2_clock = clock;
  assign if2_reset = reset;
  assign if2_io_if2_req_valid = if1_io_pc_gen_valid; // @[rift2Core.scala 120:17]
  assign if2_io_if2_req_bits_isActive_0 = if1_io_pc_gen_bits_isActive_0; // @[rift2Core.scala 120:17]
  assign if2_io_if2_req_bits_isActive_1 = if1_io_pc_gen_bits_isActive_1; // @[rift2Core.scala 120:17]
  assign if2_io_if2_req_bits_isActive_2 = if1_io_pc_gen_bits_isActive_2; // @[rift2Core.scala 120:17]
  assign if2_io_if2_req_bits_isActive_3 = if1_io_pc_gen_bits_isActive_3; // @[rift2Core.scala 120:17]
  assign if2_io_if2_req_bits_pc = if1_io_pc_gen_bits_pc; // @[rift2Core.scala 120:17]
  assign if2_io_if2_resp_0_ready = if3_io_if3_req_0_ready; // @[rift2Core.scala 121:19]
  assign if2_io_if2_resp_1_ready = if3_io_if3_req_1_ready; // @[rift2Core.scala 121:19]
  assign if2_io_if2_resp_2_ready = if3_io_if3_req_2_ready; // @[rift2Core.scala 121:19]
  assign if2_io_if2_resp_3_ready = if3_io_if3_req_3_ready; // @[rift2Core.scala 121:19]
  assign if2_io_if_mmu_ready = i_mmu_io_if_mmu_ready; // @[rift2Core.scala 198:19]
  assign if2_io_mmu_if_valid = i_mmu_io_mmu_if_valid; // @[rift2Core.scala 199:19]
  assign if2_io_mmu_if_bits_vaddr = i_mmu_io_mmu_if_bits_vaddr; // @[rift2Core.scala 199:19]
  assign if2_io_mmu_if_bits_paddr = i_mmu_io_mmu_if_bits_paddr; // @[rift2Core.scala 199:19]
  assign if2_io_mmu_if_bits_is_paging_fault = i_mmu_io_mmu_if_bits_is_paging_fault; // @[rift2Core.scala 199:19]
  assign if2_io_mmu_if_bits_is_access_fault = i_mmu_io_mmu_if_bits_is_access_fault; // @[rift2Core.scala 199:19]
  assign if2_io_icache_get_ready = auto_icache_client_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign if2_io_icache_access_valid = auto_icache_client_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign if2_io_icache_access_bits_opcode = auto_icache_client_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign if2_io_icache_access_bits_size = auto_icache_client_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign if2_io_icache_access_bits_data = auto_icache_client_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign if2_io_flush = cmm_stage_io_cmmRedirect_valid | if4_io_if4Redirect_valid; // @[rift2Core.scala 225:49]
  assign if2_io_ifence = cmm_stage_io_ifence; // @[rift2Core.scala 250:17]
  assign if3_clock = clock;
  assign if3_reset = reset;
  assign if3_io_if3_req_0_valid = if2_io_if2_resp_0_valid; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_0_bits_pc = if2_io_if2_resp_0_bits_pc; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_0_bits_instr = if2_io_if2_resp_0_bits_instr; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_0_bits_isRedirect = if2_io_if2_resp_0_bits_isRedirect; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_1_valid = if2_io_if2_resp_1_valid; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_1_bits_pc = if2_io_if2_resp_1_bits_pc; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_1_bits_instr = if2_io_if2_resp_1_bits_instr; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_1_bits_isFault = if2_io_if2_resp_1_bits_isFault; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_1_bits_isRedirect = if2_io_if2_resp_1_bits_isRedirect; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_2_valid = if2_io_if2_resp_2_valid; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_2_bits_pc = if2_io_if2_resp_2_bits_pc; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_2_bits_instr = if2_io_if2_resp_2_bits_instr; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_2_bits_isFault = if2_io_if2_resp_2_bits_isFault; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_2_bits_isRedirect = if2_io_if2_resp_2_bits_isRedirect; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_3_valid = if2_io_if2_resp_3_valid; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_3_bits_pc = if2_io_if2_resp_3_bits_pc; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_3_bits_instr = if2_io_if2_resp_3_bits_instr; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_3_bits_isFault = if2_io_if2_resp_3_bits_isFault; // @[rift2Core.scala 121:19]
  assign if3_io_if3_req_3_bits_isRedirect = if2_io_if2_resp_3_bits_isRedirect; // @[rift2Core.scala 121:19]
  assign if3_io_if3_resp_0_ready = if4_io_if4_req_0_ready; // @[rift2Core.scala 122:19]
  assign if3_io_btbResp_0_ready = if4_io_btbResp_0_ready; // @[rift2Core.scala 128:19]
  assign if3_io_bimResp_0_ready = if4_io_bimResp_0_ready; // @[rift2Core.scala 129:19]
  assign if3_io_tageResp_0_ready = if4_io_tageResp_0_ready; // @[rift2Core.scala 130:19]
  assign if3_io_jcmm_update_valid = exe_stage_io_jcmm_update_valid; // @[rift2Core.scala 209:24]
  assign if3_io_jcmm_update_bits_pc = exe_stage_io_jcmm_update_bits_pc; // @[rift2Core.scala 209:24]
  assign if3_io_jcmm_update_bits_finalTarget = exe_stage_io_jcmm_update_bits_finalTarget; // @[rift2Core.scala 209:24]
  assign if3_io_bcmm_update_valid = exe_stage_io_bcmm_update_valid; // @[rift2Core.scala 210:24]
  assign if3_io_bcmm_update_bits_pc = exe_stage_io_bcmm_update_bits_pc; // @[rift2Core.scala 210:24]
  assign if3_io_bcmm_update_bits_bimResp_bim_p = exe_stage_io_bcmm_update_bits_bimResp_bim_p; // @[rift2Core.scala 210:24]
  assign if3_io_bcmm_update_bits_bimResp_bim_h = exe_stage_io_bcmm_update_bits_bimResp_bim_h; // @[rift2Core.scala 210:24]
  assign if3_io_bcmm_update_bits_isFinalTaken = exe_stage_io_bcmm_update_bits_isFinalTaken; // @[rift2Core.scala 210:24]
  assign if3_io_if4Redirect_valid = if4_io_if4Redirect_valid; // @[rift2Core.scala 134:22]
  assign if3_io_flush = cmm_stage_io_cmmRedirect_valid; // @[rift2Core.scala 226:16]
  assign if4_clock = clock;
  assign if4_reset = reset;
  assign if4_io_if4_req_0_valid = if3_io_if3_resp_0_valid; // @[rift2Core.scala 122:19]
  assign if4_io_if4_req_0_bits_isRVC = if3_io_if3_resp_0_bits_isRVC; // @[rift2Core.scala 122:19]
  assign if4_io_if4_req_0_bits_instr = if3_io_if3_resp_0_bits_instr; // @[rift2Core.scala 122:19]
  assign if4_io_if4_req_0_bits_pc = if3_io_if3_resp_0_bits_pc; // @[rift2Core.scala 122:19]
  assign if4_io_if4_req_0_bits_isRedirect = if3_io_if3_resp_0_bits_isRedirect; // @[rift2Core.scala 122:19]
  assign if4_io_if4_req_0_bits_target = if3_io_if3_resp_0_bits_target; // @[rift2Core.scala 122:19]
  assign if4_io_btbResp_0_valid = if3_io_btbResp_0_valid; // @[rift2Core.scala 128:19]
  assign if4_io_btbResp_0_bits_target = if3_io_btbResp_0_bits_target; // @[rift2Core.scala 128:19]
  assign if4_io_bimResp_0_valid = if3_io_bimResp_0_valid; // @[rift2Core.scala 129:19]
  assign if4_io_bimResp_0_bits_bim_p = if3_io_bimResp_0_bits_bim_p; // @[rift2Core.scala 129:19]
  assign if4_io_bimResp_0_bits_bim_h = if3_io_bimResp_0_bits_bim_h; // @[rift2Core.scala 129:19]
  assign if4_io_if4_resp_0_ready = rnm_stage_io_rnReq_0_ready; // @[rift2Core.scala 139:18]
  assign if4_io_bftq_ready = exe_stage_io_bftq_ready; // @[rift2Core.scala 216:23]
  assign if4_io_jftq_ready = exe_stage_io_jftq_ready; // @[rift2Core.scala 217:23]
  assign if4_io_flush = cmm_stage_io_cmmRedirect_valid; // @[rift2Core.scala 227:16]
  assign rnm_stage_clock = clock;
  assign rnm_stage_reset = cmm_stage_io_cmmRedirect_valid | reset; // @[rift2Core.scala 229:52]
  assign rnm_stage_io_rnReq_0_valid = if4_io_if4_resp_0_valid; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_lui = if4_io_if4_resp_0_bits_alu_isa_lui; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_auipc = if4_io_if4_resp_0_bits_alu_isa_auipc; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_addi = if4_io_if4_resp_0_bits_alu_isa_addi; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_addiw = if4_io_if4_resp_0_bits_alu_isa_addiw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_slti = if4_io_if4_resp_0_bits_alu_isa_slti; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_sltiu = if4_io_if4_resp_0_bits_alu_isa_sltiu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_xori = if4_io_if4_resp_0_bits_alu_isa_xori; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_ori = if4_io_if4_resp_0_bits_alu_isa_ori; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_andi = if4_io_if4_resp_0_bits_alu_isa_andi; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_slli = if4_io_if4_resp_0_bits_alu_isa_slli; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_slliw = if4_io_if4_resp_0_bits_alu_isa_slliw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_srli = if4_io_if4_resp_0_bits_alu_isa_srli; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_srliw = if4_io_if4_resp_0_bits_alu_isa_srliw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_srai = if4_io_if4_resp_0_bits_alu_isa_srai; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_sraiw = if4_io_if4_resp_0_bits_alu_isa_sraiw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_add = if4_io_if4_resp_0_bits_alu_isa_add; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_addw = if4_io_if4_resp_0_bits_alu_isa_addw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_sub = if4_io_if4_resp_0_bits_alu_isa_sub; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_subw = if4_io_if4_resp_0_bits_alu_isa_subw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_sll = if4_io_if4_resp_0_bits_alu_isa_sll; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_sllw = if4_io_if4_resp_0_bits_alu_isa_sllw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_slt = if4_io_if4_resp_0_bits_alu_isa_slt; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_sltu = if4_io_if4_resp_0_bits_alu_isa_sltu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_xor = if4_io_if4_resp_0_bits_alu_isa_xor; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_srl = if4_io_if4_resp_0_bits_alu_isa_srl; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_srlw = if4_io_if4_resp_0_bits_alu_isa_srlw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_sra = if4_io_if4_resp_0_bits_alu_isa_sra; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_sraw = if4_io_if4_resp_0_bits_alu_isa_sraw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_or = if4_io_if4_resp_0_bits_alu_isa_or; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_and = if4_io_if4_resp_0_bits_alu_isa_and; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_alu_isa_wfi = if4_io_if4_resp_0_bits_alu_isa_wfi; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_bru_isa_jal = if4_io_if4_resp_0_bits_bru_isa_jal; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_bru_isa_jalr = if4_io_if4_resp_0_bits_bru_isa_jalr; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_bru_isa_beq = if4_io_if4_resp_0_bits_bru_isa_beq; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_bru_isa_bne = if4_io_if4_resp_0_bits_bru_isa_bne; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_bru_isa_blt = if4_io_if4_resp_0_bits_bru_isa_blt; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_bru_isa_bge = if4_io_if4_resp_0_bits_bru_isa_bge; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_bru_isa_bltu = if4_io_if4_resp_0_bits_bru_isa_bltu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_bru_isa_bgeu = if4_io_if4_resp_0_bits_bru_isa_bgeu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_lb = if4_io_if4_resp_0_bits_lsu_isa_lb; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_lh = if4_io_if4_resp_0_bits_lsu_isa_lh; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_lw = if4_io_if4_resp_0_bits_lsu_isa_lw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_ld = if4_io_if4_resp_0_bits_lsu_isa_ld; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_lbu = if4_io_if4_resp_0_bits_lsu_isa_lbu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_lhu = if4_io_if4_resp_0_bits_lsu_isa_lhu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_lwu = if4_io_if4_resp_0_bits_lsu_isa_lwu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_sb = if4_io_if4_resp_0_bits_lsu_isa_sb; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_sh = if4_io_if4_resp_0_bits_lsu_isa_sh; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_sw = if4_io_if4_resp_0_bits_lsu_isa_sw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_sd = if4_io_if4_resp_0_bits_lsu_isa_sd; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_fence = if4_io_if4_resp_0_bits_lsu_isa_fence; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_fence_i = if4_io_if4_resp_0_bits_lsu_isa_fence_i; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_sfence_vma = if4_io_if4_resp_0_bits_lsu_isa_sfence_vma; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_lr_w = if4_io_if4_resp_0_bits_lsu_isa_lr_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_sc_w = if4_io_if4_resp_0_bits_lsu_isa_sc_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoswap_w = if4_io_if4_resp_0_bits_lsu_isa_amoswap_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoadd_w = if4_io_if4_resp_0_bits_lsu_isa_amoadd_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoxor_w = if4_io_if4_resp_0_bits_lsu_isa_amoxor_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoand_w = if4_io_if4_resp_0_bits_lsu_isa_amoand_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoor_w = if4_io_if4_resp_0_bits_lsu_isa_amoor_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amomin_w = if4_io_if4_resp_0_bits_lsu_isa_amomin_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amomax_w = if4_io_if4_resp_0_bits_lsu_isa_amomax_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amominu_w = if4_io_if4_resp_0_bits_lsu_isa_amominu_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amomaxu_w = if4_io_if4_resp_0_bits_lsu_isa_amomaxu_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_lr_d = if4_io_if4_resp_0_bits_lsu_isa_lr_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_sc_d = if4_io_if4_resp_0_bits_lsu_isa_sc_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoswap_d = if4_io_if4_resp_0_bits_lsu_isa_amoswap_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoadd_d = if4_io_if4_resp_0_bits_lsu_isa_amoadd_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoxor_d = if4_io_if4_resp_0_bits_lsu_isa_amoxor_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoand_d = if4_io_if4_resp_0_bits_lsu_isa_amoand_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amoor_d = if4_io_if4_resp_0_bits_lsu_isa_amoor_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amomin_d = if4_io_if4_resp_0_bits_lsu_isa_amomin_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amomax_d = if4_io_if4_resp_0_bits_lsu_isa_amomax_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amominu_d = if4_io_if4_resp_0_bits_lsu_isa_amominu_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_amomaxu_d = if4_io_if4_resp_0_bits_lsu_isa_amomaxu_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_flw = if4_io_if4_resp_0_bits_lsu_isa_flw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_fsw = if4_io_if4_resp_0_bits_lsu_isa_fsw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_fld = if4_io_if4_resp_0_bits_lsu_isa_fld; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_lsu_isa_fsd = if4_io_if4_resp_0_bits_lsu_isa_fsd; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_csr_isa_rw = if4_io_if4_resp_0_bits_csr_isa_rw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_csr_isa_rs = if4_io_if4_resp_0_bits_csr_isa_rs; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_csr_isa_rc = if4_io_if4_resp_0_bits_csr_isa_rc; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_csr_isa_rwi = if4_io_if4_resp_0_bits_csr_isa_rwi; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_csr_isa_rsi = if4_io_if4_resp_0_bits_csr_isa_rsi; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_csr_isa_rci = if4_io_if4_resp_0_bits_csr_isa_rci; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_mul = if4_io_if4_resp_0_bits_mul_isa_mul; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_mulh = if4_io_if4_resp_0_bits_mul_isa_mulh; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_mulhsu = if4_io_if4_resp_0_bits_mul_isa_mulhsu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_mulhu = if4_io_if4_resp_0_bits_mul_isa_mulhu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_div = if4_io_if4_resp_0_bits_mul_isa_div; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_divu = if4_io_if4_resp_0_bits_mul_isa_divu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_rem = if4_io_if4_resp_0_bits_mul_isa_rem; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_remu = if4_io_if4_resp_0_bits_mul_isa_remu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_mulw = if4_io_if4_resp_0_bits_mul_isa_mulw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_divw = if4_io_if4_resp_0_bits_mul_isa_divw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_divuw = if4_io_if4_resp_0_bits_mul_isa_divuw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_remw = if4_io_if4_resp_0_bits_mul_isa_remw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_mul_isa_remuw = if4_io_if4_resp_0_bits_mul_isa_remuw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_ecall = if4_io_if4_resp_0_bits_privil_isa_ecall; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_ebreak = if4_io_if4_resp_0_bits_privil_isa_ebreak; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_mret = if4_io_if4_resp_0_bits_privil_isa_mret; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_uret = if4_io_if4_resp_0_bits_privil_isa_uret; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_sret = if4_io_if4_resp_0_bits_privil_isa_sret; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_dret = if4_io_if4_resp_0_bits_privil_isa_dret; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hfence_vvma = if4_io_if4_resp_0_bits_privil_isa_hfence_vvma; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hfence_gvma = if4_io_if4_resp_0_bits_privil_isa_hfence_gvma; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlv_b = if4_io_if4_resp_0_bits_privil_isa_hlv_b; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlv_bu = if4_io_if4_resp_0_bits_privil_isa_hlv_bu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlv_h = if4_io_if4_resp_0_bits_privil_isa_hlv_h; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlv_hu = if4_io_if4_resp_0_bits_privil_isa_hlv_hu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlvx_hu = if4_io_if4_resp_0_bits_privil_isa_hlvx_hu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlv_w = if4_io_if4_resp_0_bits_privil_isa_hlv_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlvx_wu = if4_io_if4_resp_0_bits_privil_isa_hlvx_wu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hsv_b = if4_io_if4_resp_0_bits_privil_isa_hsv_b; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hsv_h = if4_io_if4_resp_0_bits_privil_isa_hsv_h; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hsv_w = if4_io_if4_resp_0_bits_privil_isa_hsv_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlv_wu = if4_io_if4_resp_0_bits_privil_isa_hlv_wu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hlv_d = if4_io_if4_resp_0_bits_privil_isa_hlv_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_hsv_d = if4_io_if4_resp_0_bits_privil_isa_hsv_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_is_access_fault = if4_io_if4_resp_0_bits_privil_isa_is_access_fault; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_privil_isa_is_paging_fault = if4_io_if4_resp_0_bits_privil_isa_is_paging_fault; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_s = if4_io_if4_resp_0_bits_fpu_isa_fmadd_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_s = if4_io_if4_resp_0_bits_fpu_isa_fmsub_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_s = if4_io_if4_resp_0_bits_fpu_isa_fnmsub_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_s = if4_io_if4_resp_0_bits_fpu_isa_fnmadd_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_s = if4_io_if4_resp_0_bits_fpu_isa_fadd_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_s = if4_io_if4_resp_0_bits_fpu_isa_fsub_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_s = if4_io_if4_resp_0_bits_fpu_isa_fmul_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_s = if4_io_if4_resp_0_bits_fpu_isa_fdiv_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_s = if4_io_if4_resp_0_bits_fpu_isa_fsqrt_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_s = if4_io_if4_resp_0_bits_fpu_isa_fsgnj_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_s = if4_io_if4_resp_0_bits_fpu_isa_fsgnjn_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_s = if4_io_if4_resp_0_bits_fpu_isa_fsgnjx_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_s = if4_io_if4_resp_0_bits_fpu_isa_fmin_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_s = if4_io_if4_resp_0_bits_fpu_isa_fmax_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_s = if4_io_if4_resp_0_bits_fpu_isa_fcvt_w_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_s = if4_io_if4_resp_0_bits_fpu_isa_fcvt_wu_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_w = if4_io_if4_resp_0_bits_fpu_isa_fmv_x_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_feq_s = if4_io_if4_resp_0_bits_fpu_isa_feq_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_flt_s = if4_io_if4_resp_0_bits_fpu_isa_flt_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fle_s = if4_io_if4_resp_0_bits_fpu_isa_fle_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_s = if4_io_if4_resp_0_bits_fpu_isa_fclass_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_w = if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_wu = if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_wu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_w_x = if4_io_if4_resp_0_bits_fpu_isa_fmv_w_x; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_s = if4_io_if4_resp_0_bits_fpu_isa_fcvt_l_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_s = if4_io_if4_resp_0_bits_fpu_isa_fcvt_lu_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_l = if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_l; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_lu = if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_lu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmadd_d = if4_io_if4_resp_0_bits_fpu_isa_fmadd_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmsub_d = if4_io_if4_resp_0_bits_fpu_isa_fmsub_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fnmsub_d = if4_io_if4_resp_0_bits_fpu_isa_fnmsub_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fnmadd_d = if4_io_if4_resp_0_bits_fpu_isa_fnmadd_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fadd_d = if4_io_if4_resp_0_bits_fpu_isa_fadd_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsub_d = if4_io_if4_resp_0_bits_fpu_isa_fsub_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmul_d = if4_io_if4_resp_0_bits_fpu_isa_fmul_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fdiv_d = if4_io_if4_resp_0_bits_fpu_isa_fdiv_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsqrt_d = if4_io_if4_resp_0_bits_fpu_isa_fsqrt_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnj_d = if4_io_if4_resp_0_bits_fpu_isa_fsgnj_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjn_d = if4_io_if4_resp_0_bits_fpu_isa_fsgnjn_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fsgnjx_d = if4_io_if4_resp_0_bits_fpu_isa_fsgnjx_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmin_d = if4_io_if4_resp_0_bits_fpu_isa_fmin_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmax_d = if4_io_if4_resp_0_bits_fpu_isa_fmax_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_s_d = if4_io_if4_resp_0_bits_fpu_isa_fcvt_s_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_s = if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_s; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_feq_d = if4_io_if4_resp_0_bits_fpu_isa_feq_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_flt_d = if4_io_if4_resp_0_bits_fpu_isa_flt_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fle_d = if4_io_if4_resp_0_bits_fpu_isa_fle_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fclass_d = if4_io_if4_resp_0_bits_fpu_isa_fclass_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_w_d = if4_io_if4_resp_0_bits_fpu_isa_fcvt_w_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_wu_d = if4_io_if4_resp_0_bits_fpu_isa_fcvt_wu_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_w = if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_w; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_wu = if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_wu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_l_d = if4_io_if4_resp_0_bits_fpu_isa_fcvt_l_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_lu_d = if4_io_if4_resp_0_bits_fpu_isa_fcvt_lu_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_x_d = if4_io_if4_resp_0_bits_fpu_isa_fmv_x_d; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_l = if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_l; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcvt_d_lu = if4_io_if4_resp_0_bits_fpu_isa_fcvt_d_lu; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fmv_d_x = if4_io_if4_resp_0_bits_fpu_isa_fmv_d_x; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rw = if4_io_if4_resp_0_bits_fpu_isa_fcsr_rw; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rs = if4_io_if4_resp_0_bits_fpu_isa_fcsr_rs; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rc = if4_io_if4_resp_0_bits_fpu_isa_fcsr_rc; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rwi = if4_io_if4_resp_0_bits_fpu_isa_fcsr_rwi; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rsi = if4_io_if4_resp_0_bits_fpu_isa_fcsr_rsi; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_fpu_isa_fcsr_rci = if4_io_if4_resp_0_bits_fpu_isa_fcsr_rci; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_param_is_rvc = if4_io_if4_resp_0_bits_param_is_rvc; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_param_pc = if4_io_if4_resp_0_bits_param_pc; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_param_imm = if4_io_if4_resp_0_bits_param_imm; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_param_raw_rs1 = if4_io_if4_resp_0_bits_param_raw_rs1; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_param_raw_rs2 = if4_io_if4_resp_0_bits_param_raw_rs2; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnReq_0_bits_param_raw_rd0 = if4_io_if4_resp_0_bits_param_raw_rd0; // @[rift2Core.scala 139:18]
  assign rnm_stage_io_rnRsp_0_ready = iss_stage_io_dptReq_0_ready; // @[rift2Core.scala 147:19]
  assign rnm_stage_io_xLookup_0_rsp_rs1 = iwb_stage_io_xLookup_0_rsp_rs1; // @[rift2Core.scala 166:20]
  assign rnm_stage_io_xLookup_0_rsp_rs2 = iwb_stage_io_xLookup_0_rsp_rs2; // @[rift2Core.scala 166:20]
  assign rnm_stage_io_fLookup_0_rsp_rs1 = iwb_stage_io_fLookup_0_rsp_rs1; // @[rift2Core.scala 167:20]
  assign rnm_stage_io_fLookup_0_rsp_rs2 = iwb_stage_io_fLookup_0_rsp_rs2; // @[rift2Core.scala 167:20]
  assign rnm_stage_io_fLookup_0_rsp_rs3 = iwb_stage_io_fLookup_0_rsp_rs3; // @[rift2Core.scala 167:20]
  assign rnm_stage_io_xRename_0_rsp_rd0 = iwb_stage_io_xRename_0_rsp_rd0; // @[rift2Core.scala 168:20]
  assign rnm_stage_io_xRename_0_req_ready = iwb_stage_io_xRename_0_req_ready; // @[rift2Core.scala 168:20]
  assign rnm_stage_io_fRename_0_rsp_rd0 = iwb_stage_io_fRename_0_rsp_rd0; // @[rift2Core.scala 169:20]
  assign rnm_stage_io_fRename_0_req_ready = iwb_stage_io_fRename_0_req_ready; // @[rift2Core.scala 169:20]
  assign rnm_stage_io_rod_i_0_ready = cmm_stage_io_rod_0_ready; // @[rift2Core.scala 236:20]
  assign iss_stage_clock = clock;
  assign iss_stage_reset = reset;
  assign iss_stage_io_dptReq_0_valid = rnm_stage_io_rnRsp_0_valid; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_lui = rnm_stage_io_rnRsp_0_bits_alu_isa_lui; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_auipc = rnm_stage_io_rnRsp_0_bits_alu_isa_auipc; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_addi = rnm_stage_io_rnRsp_0_bits_alu_isa_addi; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_addiw = rnm_stage_io_rnRsp_0_bits_alu_isa_addiw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_slti = rnm_stage_io_rnRsp_0_bits_alu_isa_slti; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_sltiu = rnm_stage_io_rnRsp_0_bits_alu_isa_sltiu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_xori = rnm_stage_io_rnRsp_0_bits_alu_isa_xori; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_ori = rnm_stage_io_rnRsp_0_bits_alu_isa_ori; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_andi = rnm_stage_io_rnRsp_0_bits_alu_isa_andi; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_slli = rnm_stage_io_rnRsp_0_bits_alu_isa_slli; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_slliw = rnm_stage_io_rnRsp_0_bits_alu_isa_slliw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_srli = rnm_stage_io_rnRsp_0_bits_alu_isa_srli; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_srliw = rnm_stage_io_rnRsp_0_bits_alu_isa_srliw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_srai = rnm_stage_io_rnRsp_0_bits_alu_isa_srai; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_sraiw = rnm_stage_io_rnRsp_0_bits_alu_isa_sraiw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_add = rnm_stage_io_rnRsp_0_bits_alu_isa_add; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_addw = rnm_stage_io_rnRsp_0_bits_alu_isa_addw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_sub = rnm_stage_io_rnRsp_0_bits_alu_isa_sub; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_subw = rnm_stage_io_rnRsp_0_bits_alu_isa_subw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_sll = rnm_stage_io_rnRsp_0_bits_alu_isa_sll; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_sllw = rnm_stage_io_rnRsp_0_bits_alu_isa_sllw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_slt = rnm_stage_io_rnRsp_0_bits_alu_isa_slt; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_sltu = rnm_stage_io_rnRsp_0_bits_alu_isa_sltu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_xor = rnm_stage_io_rnRsp_0_bits_alu_isa_xor; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_srl = rnm_stage_io_rnRsp_0_bits_alu_isa_srl; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_srlw = rnm_stage_io_rnRsp_0_bits_alu_isa_srlw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_sra = rnm_stage_io_rnRsp_0_bits_alu_isa_sra; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_sraw = rnm_stage_io_rnRsp_0_bits_alu_isa_sraw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_or = rnm_stage_io_rnRsp_0_bits_alu_isa_or; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_and = rnm_stage_io_rnRsp_0_bits_alu_isa_and; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_alu_isa_wfi = rnm_stage_io_rnRsp_0_bits_alu_isa_wfi; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_bru_isa_jal = rnm_stage_io_rnRsp_0_bits_bru_isa_jal; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_bru_isa_jalr = rnm_stage_io_rnRsp_0_bits_bru_isa_jalr; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_bru_isa_beq = rnm_stage_io_rnRsp_0_bits_bru_isa_beq; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_bru_isa_bne = rnm_stage_io_rnRsp_0_bits_bru_isa_bne; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_bru_isa_blt = rnm_stage_io_rnRsp_0_bits_bru_isa_blt; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_bru_isa_bge = rnm_stage_io_rnRsp_0_bits_bru_isa_bge; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_bru_isa_bltu = rnm_stage_io_rnRsp_0_bits_bru_isa_bltu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_bru_isa_bgeu = rnm_stage_io_rnRsp_0_bits_bru_isa_bgeu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_lb = rnm_stage_io_rnRsp_0_bits_lsu_isa_lb; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_lh = rnm_stage_io_rnRsp_0_bits_lsu_isa_lh; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_lw = rnm_stage_io_rnRsp_0_bits_lsu_isa_lw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_ld = rnm_stage_io_rnRsp_0_bits_lsu_isa_ld; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_lbu = rnm_stage_io_rnRsp_0_bits_lsu_isa_lbu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_lhu = rnm_stage_io_rnRsp_0_bits_lsu_isa_lhu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_lwu = rnm_stage_io_rnRsp_0_bits_lsu_isa_lwu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_sb = rnm_stage_io_rnRsp_0_bits_lsu_isa_sb; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_sh = rnm_stage_io_rnRsp_0_bits_lsu_isa_sh; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_sw = rnm_stage_io_rnRsp_0_bits_lsu_isa_sw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_sd = rnm_stage_io_rnRsp_0_bits_lsu_isa_sd; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_fence = rnm_stage_io_rnRsp_0_bits_lsu_isa_fence; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_fence_i = rnm_stage_io_rnRsp_0_bits_lsu_isa_fence_i; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_sfence_vma = rnm_stage_io_rnRsp_0_bits_lsu_isa_sfence_vma; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_lr_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_lr_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_sc_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_sc_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoswap_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoswap_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoadd_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoadd_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoxor_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoxor_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoand_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoand_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoor_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoor_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amomin_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amomin_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amomax_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amomax_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amominu_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amominu_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amomaxu_w = rnm_stage_io_rnRsp_0_bits_lsu_isa_amomaxu_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_lr_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_lr_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_sc_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_sc_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoswap_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoswap_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoadd_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoadd_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoxor_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoxor_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoand_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoand_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amoor_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amoor_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amomin_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amomin_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amomax_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amomax_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amominu_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amominu_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_amomaxu_d = rnm_stage_io_rnRsp_0_bits_lsu_isa_amomaxu_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_flw = rnm_stage_io_rnRsp_0_bits_lsu_isa_flw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_fsw = rnm_stage_io_rnRsp_0_bits_lsu_isa_fsw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_fld = rnm_stage_io_rnRsp_0_bits_lsu_isa_fld; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_lsu_isa_fsd = rnm_stage_io_rnRsp_0_bits_lsu_isa_fsd; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_csr_isa_rw = rnm_stage_io_rnRsp_0_bits_csr_isa_rw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_csr_isa_rs = rnm_stage_io_rnRsp_0_bits_csr_isa_rs; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_csr_isa_rc = rnm_stage_io_rnRsp_0_bits_csr_isa_rc; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_csr_isa_rwi = rnm_stage_io_rnRsp_0_bits_csr_isa_rwi; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_csr_isa_rsi = rnm_stage_io_rnRsp_0_bits_csr_isa_rsi; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_csr_isa_rci = rnm_stage_io_rnRsp_0_bits_csr_isa_rci; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_mul = rnm_stage_io_rnRsp_0_bits_mul_isa_mul; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_mulh = rnm_stage_io_rnRsp_0_bits_mul_isa_mulh; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_mulhsu = rnm_stage_io_rnRsp_0_bits_mul_isa_mulhsu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_mulhu = rnm_stage_io_rnRsp_0_bits_mul_isa_mulhu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_div = rnm_stage_io_rnRsp_0_bits_mul_isa_div; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_divu = rnm_stage_io_rnRsp_0_bits_mul_isa_divu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_rem = rnm_stage_io_rnRsp_0_bits_mul_isa_rem; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_remu = rnm_stage_io_rnRsp_0_bits_mul_isa_remu; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_mulw = rnm_stage_io_rnRsp_0_bits_mul_isa_mulw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_divw = rnm_stage_io_rnRsp_0_bits_mul_isa_divw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_divuw = rnm_stage_io_rnRsp_0_bits_mul_isa_divuw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_remw = rnm_stage_io_rnRsp_0_bits_mul_isa_remw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_mul_isa_remuw = rnm_stage_io_rnRsp_0_bits_mul_isa_remuw; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmadd_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmadd_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmsub_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmsub_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fnmsub_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmsub_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fnmadd_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmadd_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fadd_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fadd_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsub_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsub_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmul_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmul_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fdiv_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fdiv_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsqrt_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsqrt_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsgnj_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnj_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjn_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjn_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjx_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjx_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmin_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmin_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmax_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmax_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_w_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_w_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_wu_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_wu_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmv_x_w = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmv_x_w; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_feq_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_feq_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_flt_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_flt_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fle_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fle_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fclass_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fclass_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_l_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_l_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_lu_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_lu_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmadd_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmadd_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmsub_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmsub_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fnmsub_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmsub_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fnmadd_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fnmadd_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fadd_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fadd_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsub_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsub_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmul_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmul_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fdiv_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fdiv_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsqrt_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsqrt_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsgnj_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnj_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjn_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjn_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fsgnjx_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fsgnjx_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmin_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmin_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmax_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmax_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_s_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_s_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_d_s = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_d_s; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_feq_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_feq_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_flt_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_flt_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fle_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fle_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fclass_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fclass_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_w_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_w_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_wu_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_wu_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_l_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_l_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fcvt_lu_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fcvt_lu_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_fpu_isa_fmv_x_d = rnm_stage_io_rnRsp_0_bits_fpu_isa_fmv_x_d; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_param_is_rvc = rnm_stage_io_rnRsp_0_bits_param_is_rvc; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_param_pc = rnm_stage_io_rnRsp_0_bits_param_pc; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_param_imm = rnm_stage_io_rnRsp_0_bits_param_imm; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_param_raw_rs1 = rnm_stage_io_rnRsp_0_bits_param_raw_rs1; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_phy_rs1 = rnm_stage_io_rnRsp_0_bits_phy_rs1; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_phy_rs2 = rnm_stage_io_rnRsp_0_bits_phy_rs2; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_phy_rs3 = rnm_stage_io_rnRsp_0_bits_phy_rs3; // @[rift2Core.scala 147:19]
  assign iss_stage_io_dptReq_0_bits_phy_rd0 = rnm_stage_io_rnRsp_0_bits_phy_rd0; // @[rift2Core.scala 147:19]
  assign iss_stage_io_alu_iss_exe_0_ready = exe_stage_io_alu_iss_exe_0_ready; // @[rift2Core.scala 154:30]
  assign iss_stage_io_mul_iss_exe_0_ready = exe_stage_io_mul_iss_exe_0_ready; // @[rift2Core.scala 158:30]
  assign iss_stage_io_bru_iss_exe_ready = exe_stage_io_bru_iss_exe_ready; // @[rift2Core.scala 155:30]
  assign iss_stage_io_csr_iss_exe_ready = exe_stage_io_csr_iss_exe_ready; // @[rift2Core.scala 157:30]
  assign iss_stage_io_lsu_iss_exe_ready = exe_stage_io_lsu_iss_exe_ready; // @[rift2Core.scala 156:30]
  assign iss_stage_io_irgLog_0 = iwb_stage_io_irgLog_0; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_1 = iwb_stage_io_irgLog_1; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_2 = iwb_stage_io_irgLog_2; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_3 = iwb_stage_io_irgLog_3; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_4 = iwb_stage_io_irgLog_4; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_5 = iwb_stage_io_irgLog_5; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_6 = iwb_stage_io_irgLog_6; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_7 = iwb_stage_io_irgLog_7; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_8 = iwb_stage_io_irgLog_8; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_9 = iwb_stage_io_irgLog_9; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_10 = iwb_stage_io_irgLog_10; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_11 = iwb_stage_io_irgLog_11; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_12 = iwb_stage_io_irgLog_12; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_13 = iwb_stage_io_irgLog_13; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_14 = iwb_stage_io_irgLog_14; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_15 = iwb_stage_io_irgLog_15; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_16 = iwb_stage_io_irgLog_16; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_17 = iwb_stage_io_irgLog_17; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_18 = iwb_stage_io_irgLog_18; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_19 = iwb_stage_io_irgLog_19; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_20 = iwb_stage_io_irgLog_20; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_21 = iwb_stage_io_irgLog_21; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_22 = iwb_stage_io_irgLog_22; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_23 = iwb_stage_io_irgLog_23; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_24 = iwb_stage_io_irgLog_24; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_25 = iwb_stage_io_irgLog_25; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_26 = iwb_stage_io_irgLog_26; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_27 = iwb_stage_io_irgLog_27; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_28 = iwb_stage_io_irgLog_28; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_29 = iwb_stage_io_irgLog_29; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_30 = iwb_stage_io_irgLog_30; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_31 = iwb_stage_io_irgLog_31; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_32 = iwb_stage_io_irgLog_32; // @[rift2Core.scala 171:25]
  assign iss_stage_io_irgLog_33 = iwb_stage_io_irgLog_33; // @[rift2Core.scala 171:25]
  assign iss_stage_io_frgLog_0 = iwb_stage_io_frgLog_0; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_1 = iwb_stage_io_frgLog_1; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_2 = iwb_stage_io_frgLog_2; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_3 = iwb_stage_io_frgLog_3; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_4 = iwb_stage_io_frgLog_4; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_5 = iwb_stage_io_frgLog_5; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_6 = iwb_stage_io_frgLog_6; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_7 = iwb_stage_io_frgLog_7; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_8 = iwb_stage_io_frgLog_8; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_9 = iwb_stage_io_frgLog_9; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_10 = iwb_stage_io_frgLog_10; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_11 = iwb_stage_io_frgLog_11; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_12 = iwb_stage_io_frgLog_12; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_13 = iwb_stage_io_frgLog_13; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_14 = iwb_stage_io_frgLog_14; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_15 = iwb_stage_io_frgLog_15; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_16 = iwb_stage_io_frgLog_16; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_17 = iwb_stage_io_frgLog_17; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_18 = iwb_stage_io_frgLog_18; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_19 = iwb_stage_io_frgLog_19; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_20 = iwb_stage_io_frgLog_20; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_21 = iwb_stage_io_frgLog_21; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_22 = iwb_stage_io_frgLog_22; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_23 = iwb_stage_io_frgLog_23; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_24 = iwb_stage_io_frgLog_24; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_25 = iwb_stage_io_frgLog_25; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_26 = iwb_stage_io_frgLog_26; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_27 = iwb_stage_io_frgLog_27; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_28 = iwb_stage_io_frgLog_28; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_29 = iwb_stage_io_frgLog_29; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_30 = iwb_stage_io_frgLog_30; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_31 = iwb_stage_io_frgLog_31; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_32 = iwb_stage_io_frgLog_32; // @[rift2Core.scala 172:25]
  assign iss_stage_io_frgLog_33 = iwb_stage_io_frgLog_33; // @[rift2Core.scala 172:25]
  assign iss_stage_io_irgRsp_0_valid = iwb_stage_io_irgRsp_0_valid; // @[rift2Core.scala 175:25]
  assign iss_stage_io_irgRsp_0_bits_phy = iwb_stage_io_irgRsp_0_bits_phy; // @[rift2Core.scala 175:25]
  assign iss_stage_io_irgRsp_0_bits_op = iwb_stage_io_irgRsp_0_bits_op; // @[rift2Core.scala 175:25]
  assign iss_stage_io_flush = cmm_stage_io_cmmRedirect_valid; // @[rift2Core.scala 230:22]
  assign exe_stage_clock = clock;
  assign exe_stage_reset = reset;
  assign exe_stage_io_alu_iss_exe_0_valid = iss_stage_io_alu_iss_exe_0_valid; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_fun_add = iss_stage_io_alu_iss_exe_0_bits_fun_add; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_fun_slt = iss_stage_io_alu_iss_exe_0_bits_fun_slt; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_fun_xor = iss_stage_io_alu_iss_exe_0_bits_fun_xor; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_fun_or = iss_stage_io_alu_iss_exe_0_bits_fun_or; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_fun_and = iss_stage_io_alu_iss_exe_0_bits_fun_and; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_fun_sll = iss_stage_io_alu_iss_exe_0_bits_fun_sll; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_fun_srl = iss_stage_io_alu_iss_exe_0_bits_fun_srl; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_fun_sra = iss_stage_io_alu_iss_exe_0_bits_fun_sra; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_param_rd0 = iss_stage_io_alu_iss_exe_0_bits_param_rd0; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_param_is_32w = iss_stage_io_alu_iss_exe_0_bits_param_is_32w; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_param_is_usi = iss_stage_io_alu_iss_exe_0_bits_param_is_usi; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_param_dat_op1 = iss_stage_io_alu_iss_exe_0_bits_param_dat_op1; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_iss_exe_0_bits_param_dat_op2 = iss_stage_io_alu_iss_exe_0_bits_param_dat_op2; // @[rift2Core.scala 154:30]
  assign exe_stage_io_alu_exe_iwb_0_ready = iwb_stage_io_alu_iWriteBack_0_ready; // @[rift2Core.scala 179:27]
  assign exe_stage_io_bru_iss_exe_valid = iss_stage_io_bru_iss_exe_valid; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_fun_jalr = iss_stage_io_bru_iss_exe_bits_fun_jalr; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_fun_beq = iss_stage_io_bru_iss_exe_bits_fun_beq; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_fun_bne = iss_stage_io_bru_iss_exe_bits_fun_bne; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_fun_blt = iss_stage_io_bru_iss_exe_bits_fun_blt; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_fun_bge = iss_stage_io_bru_iss_exe_bits_fun_bge; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_fun_bltu = iss_stage_io_bru_iss_exe_bits_fun_bltu; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_fun_bgeu = iss_stage_io_bru_iss_exe_bits_fun_bgeu; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_param_rd0 = iss_stage_io_bru_iss_exe_bits_param_rd0; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_param_is_rvc = iss_stage_io_bru_iss_exe_bits_param_is_rvc; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_param_pc = iss_stage_io_bru_iss_exe_bits_param_pc; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_param_imm = iss_stage_io_bru_iss_exe_bits_param_imm; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_param_dat_op1 = iss_stage_io_bru_iss_exe_bits_param_dat_op1; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_iss_exe_bits_param_dat_op2 = iss_stage_io_bru_iss_exe_bits_param_dat_op2; // @[rift2Core.scala 155:30]
  assign exe_stage_io_bru_exe_iwb_ready = iwb_stage_io_bru_iWriteBack_ready; // @[rift2Core.scala 180:27]
  assign exe_stage_io_csr_iss_exe_valid = iss_stage_io_csr_iss_exe_valid; // @[rift2Core.scala 157:30]
  assign exe_stage_io_csr_iss_exe_bits_fun_rw = iss_stage_io_csr_iss_exe_bits_fun_rw; // @[rift2Core.scala 157:30]
  assign exe_stage_io_csr_iss_exe_bits_fun_rs = iss_stage_io_csr_iss_exe_bits_fun_rs; // @[rift2Core.scala 157:30]
  assign exe_stage_io_csr_iss_exe_bits_fun_rc = iss_stage_io_csr_iss_exe_bits_fun_rc; // @[rift2Core.scala 157:30]
  assign exe_stage_io_csr_iss_exe_bits_param_rd0 = iss_stage_io_csr_iss_exe_bits_param_rd0; // @[rift2Core.scala 157:30]
  assign exe_stage_io_csr_iss_exe_bits_param_dat_op1 = iss_stage_io_csr_iss_exe_bits_param_dat_op1; // @[rift2Core.scala 157:30]
  assign exe_stage_io_csr_iss_exe_bits_param_dat_op2 = iss_stage_io_csr_iss_exe_bits_param_dat_op2; // @[rift2Core.scala 157:30]
  assign exe_stage_io_csr_exe_iwb_ready = iwb_stage_io_csr_iWriteBack_ready; // @[rift2Core.scala 181:27]
  assign exe_stage_io_lsu_iss_exe_valid = iss_stage_io_lsu_iss_exe_valid; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_lb = iss_stage_io_lsu_iss_exe_bits_fun_lb; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_lh = iss_stage_io_lsu_iss_exe_bits_fun_lh; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_lw = iss_stage_io_lsu_iss_exe_bits_fun_lw; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_ld = iss_stage_io_lsu_iss_exe_bits_fun_ld; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_lbu = iss_stage_io_lsu_iss_exe_bits_fun_lbu; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_lhu = iss_stage_io_lsu_iss_exe_bits_fun_lhu; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_lwu = iss_stage_io_lsu_iss_exe_bits_fun_lwu; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_sb = iss_stage_io_lsu_iss_exe_bits_fun_sb; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_sh = iss_stage_io_lsu_iss_exe_bits_fun_sh; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_sw = iss_stage_io_lsu_iss_exe_bits_fun_sw; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_sd = iss_stage_io_lsu_iss_exe_bits_fun_sd; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_fence = iss_stage_io_lsu_iss_exe_bits_fun_fence; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_fence_i = iss_stage_io_lsu_iss_exe_bits_fun_fence_i; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_sfence_vma = iss_stage_io_lsu_iss_exe_bits_fun_sfence_vma; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_lr_w = iss_stage_io_lsu_iss_exe_bits_fun_lr_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_sc_w = iss_stage_io_lsu_iss_exe_bits_fun_sc_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoswap_w = iss_stage_io_lsu_iss_exe_bits_fun_amoswap_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoadd_w = iss_stage_io_lsu_iss_exe_bits_fun_amoadd_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoxor_w = iss_stage_io_lsu_iss_exe_bits_fun_amoxor_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoand_w = iss_stage_io_lsu_iss_exe_bits_fun_amoand_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoor_w = iss_stage_io_lsu_iss_exe_bits_fun_amoor_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amomin_w = iss_stage_io_lsu_iss_exe_bits_fun_amomin_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amomax_w = iss_stage_io_lsu_iss_exe_bits_fun_amomax_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amominu_w = iss_stage_io_lsu_iss_exe_bits_fun_amominu_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amomaxu_w = iss_stage_io_lsu_iss_exe_bits_fun_amomaxu_w; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_lr_d = iss_stage_io_lsu_iss_exe_bits_fun_lr_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_sc_d = iss_stage_io_lsu_iss_exe_bits_fun_sc_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoswap_d = iss_stage_io_lsu_iss_exe_bits_fun_amoswap_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoadd_d = iss_stage_io_lsu_iss_exe_bits_fun_amoadd_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoxor_d = iss_stage_io_lsu_iss_exe_bits_fun_amoxor_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoand_d = iss_stage_io_lsu_iss_exe_bits_fun_amoand_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amoor_d = iss_stage_io_lsu_iss_exe_bits_fun_amoor_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amomin_d = iss_stage_io_lsu_iss_exe_bits_fun_amomin_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amomax_d = iss_stage_io_lsu_iss_exe_bits_fun_amomax_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amominu_d = iss_stage_io_lsu_iss_exe_bits_fun_amominu_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_amomaxu_d = iss_stage_io_lsu_iss_exe_bits_fun_amomaxu_d; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_flw = iss_stage_io_lsu_iss_exe_bits_fun_flw; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_fsw = iss_stage_io_lsu_iss_exe_bits_fun_fsw; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_fld = iss_stage_io_lsu_iss_exe_bits_fun_fld; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_fun_fsd = iss_stage_io_lsu_iss_exe_bits_fun_fsd; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_param_rd0 = iss_stage_io_lsu_iss_exe_bits_param_rd0; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_param_dat_op1 = iss_stage_io_lsu_iss_exe_bits_param_dat_op1; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_iss_exe_bits_param_dat_op2 = iss_stage_io_lsu_iss_exe_bits_param_dat_op2; // @[rift2Core.scala 156:30]
  assign exe_stage_io_lsu_exe_iwb_ready = iwb_stage_io_mem_iWriteBack_ready; // @[rift2Core.scala 182:27]
  assign exe_stage_io_lsu_exe_fwb_ready = iwb_stage_io_mem_fWriteBack_ready; // @[rift2Core.scala 183:27]
  assign exe_stage_io_mul_iss_exe_0_valid = iss_stage_io_mul_iss_exe_0_valid; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_mul = iss_stage_io_mul_iss_exe_0_bits_fun_mul; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_mulh = iss_stage_io_mul_iss_exe_0_bits_fun_mulh; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_mulhsu = iss_stage_io_mul_iss_exe_0_bits_fun_mulhsu; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_mulhu = iss_stage_io_mul_iss_exe_0_bits_fun_mulhu; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_div = iss_stage_io_mul_iss_exe_0_bits_fun_div; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_divu = iss_stage_io_mul_iss_exe_0_bits_fun_divu; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_rem = iss_stage_io_mul_iss_exe_0_bits_fun_rem; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_remu = iss_stage_io_mul_iss_exe_0_bits_fun_remu; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_mulw = iss_stage_io_mul_iss_exe_0_bits_fun_mulw; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_divw = iss_stage_io_mul_iss_exe_0_bits_fun_divw; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_divuw = iss_stage_io_mul_iss_exe_0_bits_fun_divuw; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_remw = iss_stage_io_mul_iss_exe_0_bits_fun_remw; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_fun_remuw = iss_stage_io_mul_iss_exe_0_bits_fun_remuw; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_param_rd0 = iss_stage_io_mul_iss_exe_0_bits_param_rd0; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_param_dat_op1 = iss_stage_io_mul_iss_exe_0_bits_param_dat_op1; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_iss_exe_0_bits_param_dat_op2 = iss_stage_io_mul_iss_exe_0_bits_param_dat_op2; // @[rift2Core.scala 158:30]
  assign exe_stage_io_mul_exe_iwb_0_ready = iwb_stage_io_mul_iWriteBack_0_ready; // @[rift2Core.scala 184:27]
  assign exe_stage_io_fpu_iss_exe_0_valid = iss_stage_io_fpu_iss_exe_0_valid; // @[rift2Core.scala 159:30]
  assign exe_stage_io_bftq_valid = if4_io_bftq_valid; // @[rift2Core.scala 216:23]
  assign exe_stage_io_bftq_bits_pc = if4_io_bftq_bits_pc; // @[rift2Core.scala 216:23]
  assign exe_stage_io_bftq_bits_bimResp_bim_p = if4_io_bftq_bits_bimResp_bim_p; // @[rift2Core.scala 216:23]
  assign exe_stage_io_bftq_bits_bimResp_bim_h = if4_io_bftq_bits_bimResp_bim_h; // @[rift2Core.scala 216:23]
  assign exe_stage_io_bftq_bits_isPredictTaken = if4_io_bftq_bits_isPredictTaken; // @[rift2Core.scala 216:23]
  assign exe_stage_io_jftq_valid = if4_io_jftq_valid; // @[rift2Core.scala 217:23]
  assign exe_stage_io_jftq_bits_pc = if4_io_jftq_bits_pc; // @[rift2Core.scala 217:23]
  assign exe_stage_io_jftq_bits_btbResp_target = if4_io_jftq_bits_btbResp_target; // @[rift2Core.scala 217:23]
  assign exe_stage_io_jftq_bits_rasResp_target = if4_io_jftq_bits_rasResp_target; // @[rift2Core.scala 217:23]
  assign exe_stage_io_jftq_bits_isRas = if4_io_jftq_bits_isRas; // @[rift2Core.scala 217:23]
  assign exe_stage_io_bctq_ready = cmm_stage_io_bctq_ready; // @[rift2Core.scala 244:21]
  assign exe_stage_io_jctq_ready = cmm_stage_io_jctq_ready; // @[rift2Core.scala 245:21]
  assign exe_stage_io_csr_data_valid = cmm_stage_io_csr_data_valid; // @[rift2Core.scala 240:25]
  assign exe_stage_io_csr_data_bits = cmm_stage_io_csr_data_bits; // @[rift2Core.scala 240:25]
  assign exe_stage_io_csr_cmm_op_ready = cmm_stage_io_csr_cmm_op_ready; // @[rift2Core.scala 241:27]
  assign exe_stage_io_lsu_mmu_ready = i_mmu_io_lsu_mmu_ready; // @[rift2Core.scala 200:20]
  assign exe_stage_io_mmu_lsu_valid = i_mmu_io_mmu_lsu_valid; // @[rift2Core.scala 201:20]
  assign exe_stage_io_mmu_lsu_bits_paddr = i_mmu_io_mmu_lsu_bits_paddr; // @[rift2Core.scala 201:20]
  assign exe_stage_io_mmu_lsu_bits_is_paging_fault = i_mmu_io_mmu_lsu_bits_is_paging_fault; // @[rift2Core.scala 201:20]
  assign exe_stage_io_mmu_lsu_bits_is_access_fault = i_mmu_io_mmu_lsu_bits_is_access_fault; // @[rift2Core.scala 201:20]
  assign exe_stage_io_cmm_lsu_is_amo_pending = cmm_stage_io_cmm_lsu_is_amo_pending; // @[rift2Core.scala 237:24]
  assign exe_stage_io_cmm_lsu_is_store_commit_0 = cmm_stage_io_cmm_lsu_is_store_commit_0; // @[rift2Core.scala 237:24]
  assign exe_stage_io_missUnit_dcache_acquire_ready = auto_dcache_client_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_missUnit_dcache_grant_valid = auto_dcache_client_out_d_valid & (
    auto_dcache_client_out_d_bits_opcode == 3'h4 | auto_dcache_client_out_d_bits_opcode == 3'h5); // @[rift2Core.scala 274:72]
  assign exe_stage_io_missUnit_dcache_grant_bits_opcode = auto_dcache_client_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_missUnit_dcache_grant_bits_size = auto_dcache_client_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_missUnit_dcache_grant_bits_source = auto_dcache_client_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_missUnit_dcache_grant_bits_sink = auto_dcache_client_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_missUnit_dcache_grant_bits_data = auto_dcache_client_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_missUnit_dcache_grantAck_ready = auto_dcache_client_out_e_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_probeUnit_dcache_probe_valid = auto_dcache_client_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_probeUnit_dcache_probe_bits_address = auto_dcache_client_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_writeBackUnit_dcache_release_ready = auto_dcache_client_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_writeBackUnit_dcache_grant_valid = auto_dcache_client_out_d_valid &
    auto_dcache_client_out_d_bits_opcode == 3'h6; // @[rift2Core.scala 277:77]
  assign exe_stage_io_writeBackUnit_dcache_grant_bits_source = auto_dcache_client_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_system_getPut_ready = auto_system_client_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_system_access_valid = auto_system_client_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_system_access_bits_opcode = auto_system_client_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_system_access_bits_data = auto_system_client_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_periph_getPut_ready = auto_periph_client_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_periph_access_valid = auto_periph_client_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_periph_access_bits_opcode = auto_periph_client_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_periph_access_bits_data = auto_periph_client_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign exe_stage_io_flush = cmm_stage_io_cmmRedirect_valid; // @[rift2Core.scala 231:22]
  assign iwb_stage_clock = clock;
  assign iwb_stage_reset = reset;
  assign iwb_stage_io_xLookup_0_req_rs1 = rnm_stage_io_xLookup_0_req_rs1; // @[rift2Core.scala 166:20]
  assign iwb_stage_io_xLookup_0_req_rs2 = rnm_stage_io_xLookup_0_req_rs2; // @[rift2Core.scala 166:20]
  assign iwb_stage_io_xRename_0_req_valid = rnm_stage_io_xRename_0_req_valid; // @[rift2Core.scala 168:20]
  assign iwb_stage_io_xRename_0_req_bits_rd0 = rnm_stage_io_xRename_0_req_bits_rd0; // @[rift2Core.scala 168:20]
  assign iwb_stage_io_irgReq_0_valid = iss_stage_io_irgReq_0_valid; // @[rift2Core.scala 173:19]
  assign iwb_stage_io_irgReq_0_bits = iss_stage_io_irgReq_0_bits; // @[rift2Core.scala 173:19]
  assign iwb_stage_io_alu_iWriteBack_0_valid = exe_stage_io_alu_exe_iwb_0_valid; // @[rift2Core.scala 179:27]
  assign iwb_stage_io_alu_iWriteBack_0_bits_rd0 = exe_stage_io_alu_exe_iwb_0_bits_rd0; // @[rift2Core.scala 179:27]
  assign iwb_stage_io_alu_iWriteBack_0_bits_res = exe_stage_io_alu_exe_iwb_0_bits_res; // @[rift2Core.scala 179:27]
  assign iwb_stage_io_bru_iWriteBack_valid = exe_stage_io_bru_exe_iwb_valid; // @[rift2Core.scala 180:27]
  assign iwb_stage_io_bru_iWriteBack_bits_rd0 = exe_stage_io_bru_exe_iwb_bits_rd0; // @[rift2Core.scala 180:27]
  assign iwb_stage_io_bru_iWriteBack_bits_res = exe_stage_io_bru_exe_iwb_bits_res; // @[rift2Core.scala 180:27]
  assign iwb_stage_io_csr_iWriteBack_valid = exe_stage_io_csr_exe_iwb_valid; // @[rift2Core.scala 181:27]
  assign iwb_stage_io_csr_iWriteBack_bits_rd0 = exe_stage_io_csr_exe_iwb_bits_rd0; // @[rift2Core.scala 181:27]
  assign iwb_stage_io_csr_iWriteBack_bits_res = exe_stage_io_csr_exe_iwb_bits_res; // @[rift2Core.scala 181:27]
  assign iwb_stage_io_mem_iWriteBack_valid = exe_stage_io_lsu_exe_iwb_valid; // @[rift2Core.scala 182:27]
  assign iwb_stage_io_mem_iWriteBack_bits_rd0 = exe_stage_io_lsu_exe_iwb_bits_rd0; // @[rift2Core.scala 182:27]
  assign iwb_stage_io_mem_iWriteBack_bits_res = exe_stage_io_lsu_exe_iwb_bits_res; // @[rift2Core.scala 182:27]
  assign iwb_stage_io_mul_iWriteBack_0_valid = exe_stage_io_mul_exe_iwb_0_valid; // @[rift2Core.scala 184:27]
  assign iwb_stage_io_mul_iWriteBack_0_bits_rd0 = exe_stage_io_mul_exe_iwb_0_bits_rd0; // @[rift2Core.scala 184:27]
  assign iwb_stage_io_mul_iWriteBack_0_bits_res = exe_stage_io_mul_exe_iwb_0_bits_res; // @[rift2Core.scala 184:27]
  assign iwb_stage_io_fpu_iWriteBack_0_valid = exe_stage_io_fpu_exe_iwb_0_valid; // @[rift2Core.scala 185:27]
  assign iwb_stage_io_fpu_iWriteBack_0_bits_rd0 = exe_stage_io_fpu_exe_iwb_0_bits_rd0; // @[rift2Core.scala 185:27]
  assign iwb_stage_io_fpu_iWriteBack_0_bits_res = exe_stage_io_fpu_exe_iwb_0_bits_res; // @[rift2Core.scala 185:27]
  assign iwb_stage_io_mem_fWriteBack_valid = exe_stage_io_lsu_exe_fwb_valid; // @[rift2Core.scala 183:27]
  assign iwb_stage_io_fpu_fWriteBack_0_valid = exe_stage_io_fpu_exe_fwb_0_valid; // @[rift2Core.scala 186:27]
  assign iwb_stage_io_commit_0_is_comfirm = cmm_stage_io_cm_op_0_is_comfirm; // @[rift2Core.scala 235:22]
  assign iwb_stage_io_commit_0_is_MisPredict = cmm_stage_io_cm_op_0_is_MisPredict; // @[rift2Core.scala 235:22]
  assign iwb_stage_io_commit_0_is_abort = cmm_stage_io_cm_op_0_is_abort; // @[rift2Core.scala 235:22]
  assign iwb_stage_io_commit_0_raw = cmm_stage_io_cm_op_0_raw; // @[rift2Core.scala 235:22]
  assign iwb_stage_io_commit_0_phy = cmm_stage_io_cm_op_0_phy; // @[rift2Core.scala 235:22]
  assign iwb_stage_io_commit_0_toX = cmm_stage_io_cm_op_0_toX; // @[rift2Core.scala 235:22]
  assign iwb_stage_io_commit_0_toF = cmm_stage_io_cm_op_0_toF; // @[rift2Core.scala 235:22]
  assign cmm_stage_clock = clock;
  assign cmm_stage_reset = reset;
  assign cmm_stage_io_cm_op_0_is_writeback = iwb_stage_io_commit_0_is_writeback; // @[rift2Core.scala 235:22]
  assign cmm_stage_io_rod_0_valid = rnm_stage_io_rod_i_0_valid; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_pc = rnm_stage_io_rod_i_0_bits_pc; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_rd0_raw = rnm_stage_io_rod_i_0_bits_rd0_raw; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_rd0_phy = rnm_stage_io_rod_i_0_bits_rd0_phy; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_branch = rnm_stage_io_rod_i_0_bits_is_branch; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_jalr = rnm_stage_io_rod_i_0_bits_is_jalr; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_lu = rnm_stage_io_rod_i_0_bits_is_lu; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_su = rnm_stage_io_rod_i_0_bits_is_su; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_amo = rnm_stage_io_rod_i_0_bits_is_amo; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_fence_i = rnm_stage_io_rod_i_0_bits_is_fence_i; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_sfence_vma = rnm_stage_io_rod_i_0_bits_is_sfence_vma; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_wfi = rnm_stage_io_rod_i_0_bits_is_wfi; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_csr = rnm_stage_io_rod_i_0_bits_is_csr; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_fpu = rnm_stage_io_rod_i_0_bits_is_fpu; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_fcsr = rnm_stage_io_rod_i_0_bits_is_fcsr; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_xcmm = rnm_stage_io_rod_i_0_bits_is_xcmm; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_fcmm = rnm_stage_io_rod_i_0_bits_is_fcmm; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_privil_ecall = rnm_stage_io_rod_i_0_bits_privil_ecall; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_privil_ebreak = rnm_stage_io_rod_i_0_bits_privil_ebreak; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_privil_mret = rnm_stage_io_rod_i_0_bits_privil_mret; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_privil_sret = rnm_stage_io_rod_i_0_bits_privil_sret; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_privil_dret = rnm_stage_io_rod_i_0_bits_privil_dret; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_privil_is_access_fault = rnm_stage_io_rod_i_0_bits_privil_is_access_fault; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_privil_is_paging_fault = rnm_stage_io_rod_i_0_bits_privil_is_paging_fault; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_rod_0_bits_is_illeage = rnm_stage_io_rod_i_0_bits_is_illeage; // @[rift2Core.scala 236:20]
  assign cmm_stage_io_lsu_cmm_is_access_fault = exe_stage_io_lsu_cmm_is_access_fault; // @[rift2Core.scala 238:24]
  assign cmm_stage_io_lsu_cmm_is_paging_fault = exe_stage_io_lsu_cmm_is_paging_fault; // @[rift2Core.scala 238:24]
  assign cmm_stage_io_lsu_cmm_is_misAlign = exe_stage_io_lsu_cmm_is_misAlign; // @[rift2Core.scala 238:24]
  assign cmm_stage_io_lsu_cmm_trap_addr = exe_stage_io_lsu_cmm_trap_addr; // @[rift2Core.scala 238:24]
  assign cmm_stage_io_csr_addr_valid = exe_stage_io_csr_addr_valid; // @[rift2Core.scala 239:25]
  assign cmm_stage_io_csr_addr_bits = exe_stage_io_csr_addr_bits; // @[rift2Core.scala 239:25]
  assign cmm_stage_io_csr_cmm_op_valid = exe_stage_io_csr_cmm_op_valid; // @[rift2Core.scala 241:27]
  assign cmm_stage_io_csr_cmm_op_bits_addr = exe_stage_io_csr_cmm_op_bits_addr; // @[rift2Core.scala 241:27]
  assign cmm_stage_io_csr_cmm_op_bits_dat_i = exe_stage_io_csr_cmm_op_bits_dat_i; // @[rift2Core.scala 241:27]
  assign cmm_stage_io_csr_cmm_op_bits_op_rw = exe_stage_io_csr_cmm_op_bits_op_rw; // @[rift2Core.scala 241:27]
  assign cmm_stage_io_csr_cmm_op_bits_op_rs = exe_stage_io_csr_cmm_op_bits_op_rs; // @[rift2Core.scala 241:27]
  assign cmm_stage_io_csr_cmm_op_bits_op_rc = exe_stage_io_csr_cmm_op_bits_op_rc; // @[rift2Core.scala 241:27]
  assign cmm_stage_io_bctq_valid = exe_stage_io_bctq_valid; // @[rift2Core.scala 244:21]
  assign cmm_stage_io_bctq_bits_isPredictTaken = exe_stage_io_bctq_bits_isPredictTaken; // @[rift2Core.scala 244:21]
  assign cmm_stage_io_bctq_bits_isFinalTaken = exe_stage_io_bctq_bits_isFinalTaken; // @[rift2Core.scala 244:21]
  assign cmm_stage_io_bctq_bits_finalTarget = exe_stage_io_bctq_bits_finalTarget; // @[rift2Core.scala 244:21]
  assign cmm_stage_io_jctq_valid = exe_stage_io_jctq_valid; // @[rift2Core.scala 245:21]
  assign cmm_stage_io_jctq_bits_btbResp_target = exe_stage_io_jctq_bits_btbResp_target; // @[rift2Core.scala 245:21]
  assign cmm_stage_io_jctq_bits_rasResp_target = exe_stage_io_jctq_bits_rasResp_target; // @[rift2Core.scala 245:21]
  assign cmm_stage_io_jctq_bits_isRas = exe_stage_io_jctq_bits_isRas; // @[rift2Core.scala 245:21]
  assign cmm_stage_io_jctq_bits_finalTarget = exe_stage_io_jctq_bits_finalTarget; // @[rift2Core.scala 245:21]
  assign cmm_stage_io_if_cmm_ill_vaddr = if2_io_if_cmm_ill_vaddr; // @[rift2Core.scala 247:23]
  assign cmm_stage_io_fcsr_cmm_op_0_valid = exe_stage_io_fcsr_cmm_op_0_valid; // @[rift2Core.scala 243:28]
  assign cmm_stage_io_fcsr_cmm_op_0_bits_addr = exe_stage_io_fcsr_cmm_op_0_bits_addr; // @[rift2Core.scala 243:28]
  assign cmm_stage_io_fcsr_cmm_op_0_bits_dat_i = exe_stage_io_fcsr_cmm_op_0_bits_dat_i; // @[rift2Core.scala 243:28]
  assign cmm_stage_io_fcsr_cmm_op_0_bits_op_rw = exe_stage_io_fcsr_cmm_op_0_bits_op_rw; // @[rift2Core.scala 243:28]
  assign cmm_stage_io_fcsr_cmm_op_0_bits_op_rs = exe_stage_io_fcsr_cmm_op_0_bits_op_rs; // @[rift2Core.scala 243:28]
  assign cmm_stage_io_fcsr_cmm_op_0_bits_op_rc = exe_stage_io_fcsr_cmm_op_0_bits_op_rc; // @[rift2Core.scala 243:28]
  assign cmm_stage_io_dm_hartResetReq = io_dm_hartResetReq; // @[rift2Core.scala 254:37]
  assign cmm_stage_io_dm_hartHaltReq = io_dm_hartHaltReq; // @[rift2Core.scala 254:37]
  assign cmm_stage_io_rtc_clock = io_rtc_clock; // @[rift2Core.scala 253:26]
  assign cmm_stage_io_aclint_msi = io_aclint_msi; // @[rift2Core.scala 248:23]
  assign cmm_stage_io_aclint_mti = io_aclint_mti; // @[rift2Core.scala 248:23]
  assign cmm_stage_io_aclint_ssi = io_aclint_ssi; // @[rift2Core.scala 248:23]
  assign cmm_stage_io_aclint_sti = io_aclint_sti; // @[rift2Core.scala 248:23]
  assign cmm_stage_io_plic_mei = io_plic_mei; // @[rift2Core.scala 249:21]
  assign cmm_stage_io_plic_sei = io_plic_sei; // @[rift2Core.scala 249:21]
  assign i_mmu_clock = clock;
  assign i_mmu_reset = reset;
  assign i_mmu_io_if_mmu_valid = if2_io_if_mmu_valid; // @[rift2Core.scala 198:19]
  assign i_mmu_io_if_mmu_bits_is_X = if2_io_if_mmu_bits_is_X; // @[rift2Core.scala 198:19]
  assign i_mmu_io_if_mmu_bits_vaddr = if2_io_if_mmu_bits_vaddr; // @[rift2Core.scala 198:19]
  assign i_mmu_io_mmu_if_ready = if2_io_mmu_if_ready; // @[rift2Core.scala 199:19]
  assign i_mmu_io_if_flush = if2_io_flush; // @[rift2Core.scala 222:21]
  assign i_mmu_io_lsu_mmu_valid = exe_stage_io_lsu_mmu_valid; // @[rift2Core.scala 200:20]
  assign i_mmu_io_lsu_mmu_bits_is_X = exe_stage_io_lsu_mmu_bits_is_X; // @[rift2Core.scala 200:20]
  assign i_mmu_io_lsu_mmu_bits_is_W = exe_stage_io_lsu_mmu_bits_is_W; // @[rift2Core.scala 200:20]
  assign i_mmu_io_lsu_mmu_bits_is_R = exe_stage_io_lsu_mmu_bits_is_R; // @[rift2Core.scala 200:20]
  assign i_mmu_io_lsu_mmu_bits_vaddr = exe_stage_io_lsu_mmu_bits_vaddr; // @[rift2Core.scala 200:20]
  assign i_mmu_io_mmu_lsu_ready = exe_stage_io_mmu_lsu_ready; // @[rift2Core.scala 201:20]
  assign i_mmu_io_lsu_flush = exe_stage_io_flush; // @[rift2Core.scala 223:22]
  assign i_mmu_io_cmm_mmu_satp = cmm_stage_io_cmm_mmu_satp; // @[rift2Core.scala 202:20]
  assign i_mmu_io_cmm_mmu_priv_lvl_if = cmm_stage_io_cmm_mmu_priv_lvl_if; // @[rift2Core.scala 202:20]
  assign i_mmu_io_cmm_mmu_priv_lvl_ls = cmm_stage_io_cmm_mmu_priv_lvl_ls; // @[rift2Core.scala 202:20]
  assign i_mmu_io_cmm_mmu_mstatus = cmm_stage_io_cmm_mmu_mstatus; // @[rift2Core.scala 202:20]
  assign i_mmu_io_cmm_mmu_sstatus = cmm_stage_io_cmm_mmu_sstatus; // @[rift2Core.scala 202:20]
  assign i_mmu_io_cmm_mmu_sfence_vma = cmm_stage_io_cmm_mmu_sfence_vma; // @[rift2Core.scala 202:20]
  assign i_mmu_io_ptw_get_ready = auto_mmu_client_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign i_mmu_io_ptw_access_valid = auto_mmu_client_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign i_mmu_io_ptw_access_bits_opcode = auto_mmu_client_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign i_mmu_io_ptw_access_bits_size = auto_mmu_client_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign i_mmu_io_ptw_access_bits_source = auto_mmu_client_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign i_mmu_io_ptw_access_bits_data = auto_mmu_client_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign if2_datRAM_0_datMem_0_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_1_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_2_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_3_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_4_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_5_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_6_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_7_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_8_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_9_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_10_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_11_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_12_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_13_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_14_clock = if2_datRAM_0_clock;
  assign if2_datRAM_0_datMem_15_clock = if2_datRAM_0_clock;
  assign if2_tagRAM_0_tagMem_clock = if2_tagRAM_0_clock;
  assign if3_btb_bypassFifo_ram_target_clock = if3_btb_bypassFifo_clock;
  assign if3_btb_btb_table_target_clock = if3_btb_clock;
  assign if3_bim_bim_P_clock = if3_bim_clock;
  assign if3_bim_bim_H_clock = if3_bim_clock;
  assign if3_bim_bypassFifo_ram_0_clock = if3_bim_bypassFifo_clock;
  assign if3_bim_bypassFifo_ram_1_clock = if3_bim_bypassFifo_clock;
  assign if4_ras_buf_target_clock = if4_ras_clock;
  assign iss_stage_aluIssFifo_0_ram_fun_add_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_fun_slt_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_fun_xor_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_fun_or_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_fun_and_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_fun_sll_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_fun_srl_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_fun_sra_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_param_rd0_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_param_is_32w_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_param_is_usi_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op1_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_aluIssFifo_0_ram_param_dat_op2_clock = iss_stage_aluIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_mul_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_mulh_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhsu_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_mulhu_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_div_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_divu_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_rem_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_remu_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_mulw_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_divw_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_divuw_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_remw_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_fun_remuw_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_param_rd0_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op1_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_mulIssFifo_0_ram_param_dat_op2_clock = iss_stage_mulIssFifo_0_clock;
  assign iss_stage_bruIssFifo_ram_fun_jalr_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_fun_beq_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_fun_bne_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_fun_blt_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_fun_bge_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_fun_bltu_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_fun_bgeu_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_param_rd0_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_param_is_rvc_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_param_pc_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_param_imm_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_param_dat_op1_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_bruIssFifo_ram_param_dat_op2_clock = iss_stage_bruIssFifo_clock;
  assign iss_stage_csrIssFifo_ram_fun_rw_clock = iss_stage_csrIssFifo_clock;
  assign iss_stage_csrIssFifo_ram_fun_rs_clock = iss_stage_csrIssFifo_clock;
  assign iss_stage_csrIssFifo_ram_fun_rc_clock = iss_stage_csrIssFifo_clock;
  assign iss_stage_csrIssFifo_ram_param_rd0_clock = iss_stage_csrIssFifo_clock;
  assign iss_stage_csrIssFifo_ram_param_dat_op1_clock = iss_stage_csrIssFifo_clock;
  assign iss_stage_csrIssFifo_ram_param_dat_op2_clock = iss_stage_csrIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_lb_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_lh_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_lw_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_ld_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_lbu_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_lhu_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_lwu_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_sb_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_sh_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_sw_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_sd_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_fence_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_fence_i_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_sfence_vma_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_lr_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_sc_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_w_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_lr_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_sc_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoswap_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoadd_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoxor_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoand_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amoor_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amomin_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amomax_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amominu_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_amomaxu_d_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_flw_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_fsw_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_fld_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_fun_fsd_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_param_rd0_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_param_dat_op1_clock = iss_stage_lsuIssFifo_clock;
  assign iss_stage_lsuIssFifo_ram_param_dat_op2_clock = iss_stage_lsuIssFifo_clock;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_clock = exe_stage_alu_0_alu_exe_iwb_fifo_clock;
  assign exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_clock = exe_stage_alu_0_alu_exe_iwb_fifo_clock;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_clock = exe_stage_bru_bru_exe_iwb_fifo_clock;
  assign exe_stage_bru_bru_exe_iwb_fifo_ram_res_clock = exe_stage_bru_bru_exe_iwb_fifo_clock;
  assign exe_stage_bru_bctq_ram_pc_clock = exe_stage_bru_bctq_clock;
  assign exe_stage_bru_bctq_ram_bimResp_bim_p_clock = exe_stage_bru_bctq_clock;
  assign exe_stage_bru_bctq_ram_bimResp_bim_h_clock = exe_stage_bru_bctq_clock;
  assign exe_stage_bru_bctq_ram_isPredictTaken_clock = exe_stage_bru_bctq_clock;
  assign exe_stage_bru_bctq_ram_isFinalTaken_clock = exe_stage_bru_bctq_clock;
  assign exe_stage_bru_bctq_ram_finalTarget_clock = exe_stage_bru_bctq_clock;
  assign exe_stage_bru_jctq_ram_pc_clock = exe_stage_bru_jctq_clock;
  assign exe_stage_bru_jctq_ram_btbResp_target_clock = exe_stage_bru_jctq_clock;
  assign exe_stage_bru_jctq_ram_rasResp_target_clock = exe_stage_bru_jctq_clock;
  assign exe_stage_bru_jctq_ram_isRas_clock = exe_stage_bru_jctq_clock;
  assign exe_stage_bru_jctq_ram_finalTarget_clock = exe_stage_bru_jctq_clock;
  assign exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_clock = exe_stage_lsu_cache_0_probeUnit_probe_fifo_clock;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_clock = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock
    ;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_clock = exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_clock =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_clock =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_clock =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock;
  assign exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_clock =
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_paddr_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wdata_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_wstrb_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_clock = exe_stage_lsu_cache_0_lsEntry_clock;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_clock = exe_stage_lsu_cache_0_rtn_fifo_clock;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_clock = exe_stage_lsu_cache_0_rtn_fifo_clock;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_clock = exe_stage_lsu_cache_0_rtn_fifo_clock;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_clock = exe_stage_lsu_cache_0_rtn_fifo_clock;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_clock = exe_stage_lsu_cache_0_rtn_fifo_clock;
  assign exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_clock = exe_stage_lsu_cache_0_rtn_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_paddr_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wdata_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_clock = exe_stage_lsu_cache_0_reload_fifo_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_clock = exe_stage_lsu_cache_0_stage_datRAM_0_clock;
  assign exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_clock = exe_stage_lsu_cache_0_stage_tagRAM_0_clock;
  assign exe_stage_lsu_lu_wb_fifo_ram_rd0_clock = exe_stage_lsu_lu_wb_fifo_clock;
  assign exe_stage_lsu_lu_wb_fifo_ram_res_clock = exe_stage_lsu_lu_wb_fifo_clock;
  assign exe_stage_lsu_su_wb_fifo_ram_rd0_clock = exe_stage_lsu_su_wb_fifo_clock;
  assign exe_stage_lsu_su_wb_fifo_ram_res_clock = exe_stage_lsu_su_wb_fifo_clock;
  assign exe_stage_lsu_fe_wb_fifo_ram_rd0_clock = exe_stage_lsu_fe_wb_fifo_clock;
  assign exe_stage_lsu_fe_wb_fifo_ram_res_clock = exe_stage_lsu_fe_wb_fifo_clock;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_clock = exe_stage_csr_csr_exe_iwb_fifo_clock;
  assign exe_stage_csr_csr_exe_iwb_fifo_ram_res_clock = exe_stage_csr_csr_exe_iwb_fifo_clock;
  assign exe_stage_csr_csr_op_fifo_ram_addr_clock = exe_stage_csr_csr_op_fifo_clock;
  assign exe_stage_csr_csr_op_fifo_ram_dat_i_clock = exe_stage_csr_csr_op_fifo_clock;
  assign exe_stage_csr_csr_op_fifo_ram_op_rw_clock = exe_stage_csr_csr_op_fifo_clock;
  assign exe_stage_csr_csr_op_fifo_ram_op_rs_clock = exe_stage_csr_csr_op_fifo_clock;
  assign exe_stage_csr_csr_op_fifo_ram_op_rc_clock = exe_stage_csr_csr_op_fifo_clock;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_clock = exe_stage_mulDiv_0_mul_exe_iwb_fifo_clock;
  assign exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_clock = exe_stage_mulDiv_0_mul_exe_iwb_fifo_clock;
  always @(posedge if1_clock) begin
    if (if1_reset) begin // @[IF1.scala 42:24]
      if1_pc_qout <= 64'h80000000; // @[IF1.scala 42:24]
    end else if (if1_reset) begin // @[IF1.scala 113:21]
      if1_pc_qout <= 64'h80000000; // @[IF1.scala 113:31]
    end else if (if1_io_cmmRedirect_valid) begin // @[IF1.scala 114:36]
      if1_pc_qout <= if1_io_cmmRedirect_bits_pc; // @[IF1.scala 114:46]
    end else if (if1_io_if4Redirect_valid) begin // @[IF1.scala 115:36]
      if1_pc_qout <= if1__pc_qout_v64_T_4; // @[IF1.scala 115:46]
    end else begin
      if1_pc_qout <= if1__GEN_0;
    end
  end
  always @(posedge if2_ibuf_clock) begin
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_0_pc <= if2_ibuf__GEN_1480;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_0_instr <= if2_ibuf__GEN_1488;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_0_isFault <= if2_ibuf__GEN_1496;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h0 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_0_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_0_isRedirect <= if2_ibuf__GEN_1504;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_1_pc <= if2_ibuf__GEN_1481;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_1_instr <= if2_ibuf__GEN_1489;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_1_isFault <= if2_ibuf__GEN_1497;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h1 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_1_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_1_isRedirect <= if2_ibuf__GEN_1505;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_2_pc <= if2_ibuf__GEN_1482;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_2_instr <= if2_ibuf__GEN_1490;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_2_isFault <= if2_ibuf__GEN_1498;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h2 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_2_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_2_isRedirect <= if2_ibuf__GEN_1506;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_3_pc <= if2_ibuf__GEN_1483;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_3_instr <= if2_ibuf__GEN_1491;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_3_isFault <= if2_ibuf__GEN_1499;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h3 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_3_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_3_isRedirect <= if2_ibuf__GEN_1507;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_4_pc <= if2_ibuf__GEN_1484;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_4_instr <= if2_ibuf__GEN_1492;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_4_isFault <= if2_ibuf__GEN_1500;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h4 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_4_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_4_isRedirect <= if2_ibuf__GEN_1508;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_5_pc <= if2_ibuf__GEN_1485;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_5_instr <= if2_ibuf__GEN_1493;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_5_isFault <= if2_ibuf__GEN_1501;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h5 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_5_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_5_isRedirect <= if2_ibuf__GEN_1509;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_6_pc <= if2_ibuf__GEN_1486;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_6_instr <= if2_ibuf__GEN_1494;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_6_isFault <= if2_ibuf__GEN_1502;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h6 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_6_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_6_isRedirect <= if2_ibuf__GEN_1510;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_pc <= if2_ibuf__buf_T_25_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_7_pc <= if2_ibuf__GEN_1487;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_instr <= if2_ibuf__buf_T_25_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_7_instr <= if2_ibuf__GEN_1495;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_isFault <= if2_ibuf__buf_T_25_isFault; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_7_isFault <= if2_ibuf__GEN_1503;
      end
    end
    if (!(if2_ibuf_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else if (3'h7 == if2_ibuf__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if2_ibuf_buf_7_isRedirect <= if2_ibuf__buf_T_25_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if2_ibuf_buf_7_isRedirect <= if2_ibuf__GEN_1511;
      end
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 58:30]
      if2_ibuf_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if2_ibuf__T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h0 == if2_ibuf__io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if2_ibuf_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if2_ibuf_buf_valid_0 <= if2_ibuf__GEN_1752;
      end
    end else begin
      if2_ibuf_buf_valid_0 <= if2_ibuf__GEN_1752;
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 58:30]
      if2_ibuf_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if2_ibuf__T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h1 == if2_ibuf__io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if2_ibuf_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if2_ibuf_buf_valid_1 <= if2_ibuf__GEN_1753;
      end
    end else begin
      if2_ibuf_buf_valid_1 <= if2_ibuf__GEN_1753;
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 58:30]
      if2_ibuf_buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if2_ibuf__T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h2 == if2_ibuf__io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if2_ibuf_buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if2_ibuf_buf_valid_2 <= if2_ibuf__GEN_1754;
      end
    end else begin
      if2_ibuf_buf_valid_2 <= if2_ibuf__GEN_1754;
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 58:30]
      if2_ibuf_buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if2_ibuf__T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h3 == if2_ibuf__io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if2_ibuf_buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if2_ibuf_buf_valid_3 <= if2_ibuf__GEN_1755;
      end
    end else begin
      if2_ibuf_buf_valid_3 <= if2_ibuf__GEN_1755;
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 58:30]
      if2_ibuf_buf_valid_4 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_buf_valid_4 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if2_ibuf__T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h4 == if2_ibuf__io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if2_ibuf_buf_valid_4 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if2_ibuf_buf_valid_4 <= if2_ibuf__GEN_1756;
      end
    end else begin
      if2_ibuf_buf_valid_4 <= if2_ibuf__GEN_1756;
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 58:30]
      if2_ibuf_buf_valid_5 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_buf_valid_5 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if2_ibuf__T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h5 == if2_ibuf__io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if2_ibuf_buf_valid_5 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if2_ibuf_buf_valid_5 <= if2_ibuf__GEN_1757;
      end
    end else begin
      if2_ibuf_buf_valid_5 <= if2_ibuf__GEN_1757;
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 58:30]
      if2_ibuf_buf_valid_6 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_buf_valid_6 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if2_ibuf__T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h6 == if2_ibuf__io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if2_ibuf_buf_valid_6 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if2_ibuf_buf_valid_6 <= if2_ibuf__GEN_1758;
      end
    end else begin
      if2_ibuf_buf_valid_6 <= if2_ibuf__GEN_1758;
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 58:30]
      if2_ibuf_buf_valid_7 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_buf_valid_7 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if2_ibuf__T_7) begin // @[MultiPortFifo.scala 98:34]
      if (3'h7 == if2_ibuf__io_deq_3_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if2_ibuf_buf_valid_7 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if2_ibuf_buf_valid_7 <= if2_ibuf__GEN_1759;
      end
    end else begin
      if2_ibuf_buf_valid_7 <= if2_ibuf__GEN_1759;
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 60:27]
      if2_ibuf_rd_ptr <= 3'h0; // @[MultiPortFifo.scala 60:27]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_rd_ptr <= 3'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      if2_ibuf_rd_ptr <= if2_ibuf__rd_ptr_T_5; // @[MultiPortFifo.scala 106:16]
    end
    if (if2_ibuf_reset) begin // @[MultiPortFifo.scala 61:27]
      if2_ibuf_wr_ptr <= 3'h0; // @[MultiPortFifo.scala 61:27]
    end else if (if2_ibuf_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if2_ibuf_wr_ptr <= 3'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      if2_ibuf_wr_ptr <= if2_ibuf__wr_ptr_T_5; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_40) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_37 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_73 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_85) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_82 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_112) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_109 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_121) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_118 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_130) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_127 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_148) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_145 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_157) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_154 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_166) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_163 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_175) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_172 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_184) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_181 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_220) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_217 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_229) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_226 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_256) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_253 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_265) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_262 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_274) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_271 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_292) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_289 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_298 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_310) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_307 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_39 & if2_ibuf__T_319) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_316 & if2_ibuf__T_39) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_8 & if2_ibuf__T_39 & if2_ibuf__T_325) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T & (if2_ibuf__T_8 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_16 & if2_ibuf__T_39 & if2_ibuf__T_325) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T & (if2_ibuf__T_16 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_16 & if2_ibuf__T_39 & if2_ibuf__T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_8 & (if2_ibuf__T_16 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_24 & if2_ibuf__T_39 & if2_ibuf__T_325) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T & (if2_ibuf__T_24 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_24 & if2_ibuf__T_39 & if2_ibuf__T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_8 & (if2_ibuf__T_24 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_24 & if2_ibuf__T_39 & if2_ibuf__T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_16 & (if2_ibuf__T_24 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_3 & if2_ibuf__T_39 & if2_ibuf__T_353) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_1 & (if2_ibuf__T_3 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_5 & if2_ibuf__T_39 & if2_ibuf__T_353) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_1 & (if2_ibuf__T_5 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_5 & if2_ibuf__T_39 & if2_ibuf__T_362) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_3 & (if2_ibuf__T_5 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_7 & if2_ibuf__T_39 & if2_ibuf__T_353) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_1 & (if2_ibuf__T_7 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_7 & if2_ibuf__T_39 & if2_ibuf__T_362) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_3 & (if2_ibuf__T_7 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_ibuf__T_7 & if2_ibuf__T_39 & if2_ibuf__T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:177 assert( io.deq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 177:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_ibuf__T_5 & (if2_ibuf__T_7 & if2_ibuf__T_39)) begin
          $fatal; // @[MultiPortFifo.scala 177:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if2_datRAM_0_datMem_0_clock) begin
    if (if2_datRAM_0_datMem_0_MPORT_1_en & if2_datRAM_0_datMem_0_MPORT_1_mask) begin
      if2_datRAM_0_datMem_0[if2_datRAM_0_datMem_0_MPORT_1_addr] <= if2_datRAM_0_datMem_0_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_0_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_0_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_1_clock) begin
    if (if2_datRAM_0_datMem_1_MPORT_1_en & if2_datRAM_0_datMem_1_MPORT_1_mask) begin
      if2_datRAM_0_datMem_1[if2_datRAM_0_datMem_1_MPORT_1_addr] <= if2_datRAM_0_datMem_1_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_1_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_1_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_2_clock) begin
    if (if2_datRAM_0_datMem_2_MPORT_1_en & if2_datRAM_0_datMem_2_MPORT_1_mask) begin
      if2_datRAM_0_datMem_2[if2_datRAM_0_datMem_2_MPORT_1_addr] <= if2_datRAM_0_datMem_2_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_2_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_2_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_3_clock) begin
    if (if2_datRAM_0_datMem_3_MPORT_1_en & if2_datRAM_0_datMem_3_MPORT_1_mask) begin
      if2_datRAM_0_datMem_3[if2_datRAM_0_datMem_3_MPORT_1_addr] <= if2_datRAM_0_datMem_3_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_3_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_3_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_4_clock) begin
    if (if2_datRAM_0_datMem_4_MPORT_1_en & if2_datRAM_0_datMem_4_MPORT_1_mask) begin
      if2_datRAM_0_datMem_4[if2_datRAM_0_datMem_4_MPORT_1_addr] <= if2_datRAM_0_datMem_4_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_4_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_4_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_5_clock) begin
    if (if2_datRAM_0_datMem_5_MPORT_1_en & if2_datRAM_0_datMem_5_MPORT_1_mask) begin
      if2_datRAM_0_datMem_5[if2_datRAM_0_datMem_5_MPORT_1_addr] <= if2_datRAM_0_datMem_5_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_5_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_5_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_6_clock) begin
    if (if2_datRAM_0_datMem_6_MPORT_1_en & if2_datRAM_0_datMem_6_MPORT_1_mask) begin
      if2_datRAM_0_datMem_6[if2_datRAM_0_datMem_6_MPORT_1_addr] <= if2_datRAM_0_datMem_6_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_6_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_6_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_7_clock) begin
    if (if2_datRAM_0_datMem_7_MPORT_1_en & if2_datRAM_0_datMem_7_MPORT_1_mask) begin
      if2_datRAM_0_datMem_7[if2_datRAM_0_datMem_7_MPORT_1_addr] <= if2_datRAM_0_datMem_7_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_7_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_7_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_8_clock) begin
    if (if2_datRAM_0_datMem_8_MPORT_1_en & if2_datRAM_0_datMem_8_MPORT_1_mask) begin
      if2_datRAM_0_datMem_8[if2_datRAM_0_datMem_8_MPORT_1_addr] <= if2_datRAM_0_datMem_8_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_8_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_8_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_9_clock) begin
    if (if2_datRAM_0_datMem_9_MPORT_1_en & if2_datRAM_0_datMem_9_MPORT_1_mask) begin
      if2_datRAM_0_datMem_9[if2_datRAM_0_datMem_9_MPORT_1_addr] <= if2_datRAM_0_datMem_9_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_9_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_9_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_10_clock) begin
    if (if2_datRAM_0_datMem_10_MPORT_1_en & if2_datRAM_0_datMem_10_MPORT_1_mask) begin
      if2_datRAM_0_datMem_10[if2_datRAM_0_datMem_10_MPORT_1_addr] <= if2_datRAM_0_datMem_10_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_10_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_10_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_11_clock) begin
    if (if2_datRAM_0_datMem_11_MPORT_1_en & if2_datRAM_0_datMem_11_MPORT_1_mask) begin
      if2_datRAM_0_datMem_11[if2_datRAM_0_datMem_11_MPORT_1_addr] <= if2_datRAM_0_datMem_11_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_11_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_11_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_12_clock) begin
    if (if2_datRAM_0_datMem_12_MPORT_1_en & if2_datRAM_0_datMem_12_MPORT_1_mask) begin
      if2_datRAM_0_datMem_12[if2_datRAM_0_datMem_12_MPORT_1_addr] <= if2_datRAM_0_datMem_12_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_12_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_12_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_13_clock) begin
    if (if2_datRAM_0_datMem_13_MPORT_1_en & if2_datRAM_0_datMem_13_MPORT_1_mask) begin
      if2_datRAM_0_datMem_13[if2_datRAM_0_datMem_13_MPORT_1_addr] <= if2_datRAM_0_datMem_13_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_13_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_13_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_14_clock) begin
    if (if2_datRAM_0_datMem_14_MPORT_1_en & if2_datRAM_0_datMem_14_MPORT_1_mask) begin
      if2_datRAM_0_datMem_14[if2_datRAM_0_datMem_14_MPORT_1_addr] <= if2_datRAM_0_datMem_14_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_14_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_14_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_datRAM_0_datMem_15_clock) begin
    if (if2_datRAM_0_datMem_15_MPORT_1_en & if2_datRAM_0_datMem_15_MPORT_1_mask) begin
      if2_datRAM_0_datMem_15[if2_datRAM_0_datMem_15_MPORT_1_addr] <= if2_datRAM_0_datMem_15_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    if2_datRAM_0_datMem_15_MPORT_en_pipe_0 <= if2_datRAM_0_io_enr;
    if (if2_datRAM_0_io_enr) begin
      if2_datRAM_0_datMem_15_MPORT_addr_pipe_0 <= if2_datRAM_0_io_addrr;
    end
  end
  always @(posedge if2_tagRAM_0_tagMem_clock) begin
    if (if2_tagRAM_0_tagMem_MPORT_en & if2_tagRAM_0_tagMem_MPORT_mask) begin
      if2_tagRAM_0_tagMem[if2_tagRAM_0_tagMem_MPORT_addr] <= if2_tagRAM_0_tagMem_MPORT_data; // @[CacheRAM.scala 152:27]
    end
    if2_tagRAM_0_tagMem_io_datar_MPORT_en_pipe_0 <= if2_tagRAM_0_io_enr;
    if (if2_tagRAM_0_io_enr) begin
      if2_tagRAM_0_tagMem_io_datar_MPORT_addr_pipe_0 <= if2_tagRAM_0_io_addrr;
    end
  end
  always @(posedge if2_clock) begin
    if (if2_reset) begin // @[Edges.scala 228:27]
      if2_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (if2__T) begin // @[Edges.scala 234:17]
      if (if2_first) begin // @[Edges.scala 235:21]
        if2_counter <= if2_beats1;
      end else begin
        if2_counter <= if2_counter1;
      end
    end
    if (if2__T_43) begin // @[IF2.scala 292:49]
      if2_icache_access_data_lo_0 <= if2_io_icache_access_bits_data; // @[IF2.scala 293:37]
    end
    if (if2_reset) begin // @[IF2.scala 71:27]
      if2_kill_trans <= 1'h0; // @[IF2.scala 71:27]
    end else begin
      if2_kill_trans <= if2__GEN_21;
    end
    if (if2_reset) begin // @[IF2.scala 180:25]
      if2_is_valid_1_0 <= 1'h0; // @[IF2.scala 180:25]
    end else if (if2_io_ifence) begin // @[IF2.scala 270:23]
      if2_is_valid_1_0 <= 1'h0; // @[IF2.scala 271:23]
    end else if (if2__datRAM_0_io_enw_T_8) begin // @[IF2.scala 265:91]
      if2_is_valid_1_0 <= if2__GEN_6;
    end
    if (if2_reset) begin // @[IF2.scala 180:25]
      if2_is_valid_0_0 <= 1'h0; // @[IF2.scala 180:25]
    end else if (if2_io_ifence) begin // @[IF2.scala 270:23]
      if2_is_valid_0_0 <= 1'h0; // @[IF2.scala 271:23]
    end else if (if2__datRAM_0_io_enw_T_8) begin // @[IF2.scala 265:91]
      if2_is_valid_0_0 <= if2__GEN_5;
    end
    if (if2_reset) begin // @[IF2.scala 98:34]
      if2_icache_state_qout <= 4'h0; // @[IF2.scala 98:34]
    end else begin
      if2_icache_state_qout <= if2_icache_state_dnxt; // @[IF2.scala 98:34]
    end
    if (if2_reset) begin // @[IF2.scala 100:27]
      if2_fault_lock <= 1'h0; // @[IF2.scala 100:27]
    end else if (if2_io_flush) begin // @[IF2.scala 120:20]
      if2_fault_lock <= 1'h0; // @[IF2.scala 120:33]
    end else begin
      if2_fault_lock <= if2__GEN_1;
    end
    if2_REG <= if2_io_mmu_if_bits_paddr; // @[IF2.scala 300:21]
    if2_REG_1 <= if2_kill_trans; // @[IF2.scala 300:108]
    if2_REG_2 <= if2_io_flush; // @[IF2.scala 300:131]
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2__T_10 & if2__T_11) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IF2.scala:123 assert( ~(is_access_fault & is_paging_fault) )\n"
            ); // @[IF2.scala 123:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2__T_8 & if2__T_10) begin
          $fatal; // @[IF2.scala 123:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (if2__icache_state_dnxt_T_10 & if2__T_10)) begin
          $fatal; // @[IF2.scala 193:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2__T_10 & if2__T_54) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, req paddr cannot change without flush.\n    at IF2.scala:300 assert( ~((RegNext(io.mmu_if.bits.paddr) =/= io.mmu_if.bits.paddr) & icache_state_qout === 2.U & ~RegNext(kill_trans) & ~RegNext(io.flush)), \"Assert Failed, req paddr cannot change without flush.\" )\n"
            ); // @[IF2.scala 300:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2__T_51 & if2__T_10) begin
          $fatal; // @[IF2.scala 300:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if2_io_ifence & if2__T_10 & if2__T_3) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IF2.scala:377 when( io.ifence ) { assert(io.flush) }\n"); // @[IF2.scala 377:29]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if2_io_flush & (if2_io_ifence & if2__T_10)) begin
          $fatal; // @[IF2.scala 377:29]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_combPDT_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_combPDT__T_22 & if3_combPDT__T_23) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_combPDT__T_20 & if3_combPDT__T_22) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_btb_bypassFifo_ram_target_clock) begin
    if (if3_btb_bypassFifo_ram_target_MPORT_en & if3_btb_bypassFifo_ram_target_MPORT_mask) begin
      if3_btb_bypassFifo_ram_target[if3_btb_bypassFifo_ram_target_MPORT_addr] <=
        if3_btb_bypassFifo_ram_target_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge if3_btb_bypassFifo_clock) begin
    if (if3_btb_bypassFifo_reset) begin // @[Decoupled.scala 278:27]
      if3_btb_bypassFifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (if3_btb_bypassFifo__T) begin // @[Decoupled.scala 295:27]
      if (if3_btb_bypassFifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (if3_btb_bypassFifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          if3_btb_bypassFifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          if3_btb_bypassFifo_maybe_full <= if3_btb_bypassFifo__do_enq_T;
        end
      end else begin
        if3_btb_bypassFifo_maybe_full <= if3_btb_bypassFifo__do_enq_T;
      end
    end
  end
  always @(posedge if3_btb_btb_table_target_clock) begin
    if (if3_btb_btb_table_target_MPORT_en & if3_btb_btb_table_target_MPORT_mask) begin
      if3_btb_btb_table_target[if3_btb_btb_table_target_MPORT_addr] <= if3_btb_btb_table_target_MPORT_data; // @[BTB.scala 54:32]
    end
    if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_en_pipe_0 <= 1'h1;
    if (1'h1) begin
      if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_addr_pipe_0 <= if3_btb__rd_cl_sel_out_out_out_out_out_T_3[1:
        0];
    end
  end
  always @(posedge if3_btb_clock) begin
    if3_btb_por_reset <= if3_btb_reset | if3_btb__GEN_4; // @[BTB.scala 46:{28,28}]
    if (if3_btb_reset) begin // @[Counter.scala 61:40]
      if3_btb_reset_cl <= 2'h0; // @[Counter.scala 61:40]
    end else if (if3_btb_por_reset) begin // @[Counter.scala 136:24]
      if3_btb_reset_cl <= if3_btb__wrap_value_T_1; // @[Counter.scala 77:15]
    end
    if3_btb_bypassFifo_io_enq_valid_REG <= if3_btb_io_req_ready & if3_btb_io_req_valid; // @[Decoupled.scala 52:35]
  end
  always @(posedge if3_bim_bim_P_clock) begin
    if (if3_bim_bim_P_MPORT_en & if3_bim_bim_P_MPORT_mask) begin
      if3_bim_bim_P[if3_bim_bim_P_MPORT_addr] <= if3_bim_bim_P_MPORT_data; // @[BIM.scala 46:26]
    end
    if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_en_pipe_0 <= 1'h1;
    if (1'h1) begin
      if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_addr_pipe_0 <= if3_bim__rd_cl_out_out_out_out_T_3[2:0];
    end
  end
  always @(posedge if3_bim_bim_H_clock) begin
    if (if3_bim_bim_H_MPORT_1_en & if3_bim_bim_H_MPORT_1_mask) begin
      if3_bim_bim_H[if3_bim_bim_H_MPORT_1_addr] <= if3_bim_bim_H_MPORT_1_data; // @[BIM.scala 52:26]
    end
    if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_en_pipe_0 <= 1'h1;
    if (1'h1) begin
      if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_addr_pipe_0 <= if3_bim__rd_cl_out_out_out_out_T_3[2:0];
    end
  end
  always @(posedge if3_bim_bypassFifo_ram_0_clock) begin
    if (if3_bim_bypassFifo_ram_0_MPORT_en & if3_bim_bypassFifo_ram_0_MPORT_mask) begin
      if3_bim_bypassFifo_ram_0[if3_bim_bypassFifo_ram_0_MPORT_addr] <= if3_bim_bypassFifo_ram_0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge if3_bim_bypassFifo_ram_1_clock) begin
    if (if3_bim_bypassFifo_ram_1_MPORT_en & if3_bim_bypassFifo_ram_1_MPORT_mask) begin
      if3_bim_bypassFifo_ram_1[if3_bim_bypassFifo_ram_1_MPORT_addr] <= if3_bim_bypassFifo_ram_1_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge if3_bim_bypassFifo_clock) begin
    if (if3_bim_bypassFifo_reset) begin // @[Decoupled.scala 278:27]
      if3_bim_bypassFifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (if3_bim_bypassFifo__T) begin // @[Decoupled.scala 295:27]
      if (if3_bim_bypassFifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (if3_bim_bypassFifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          if3_bim_bypassFifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          if3_bim_bypassFifo_maybe_full <= if3_bim_bypassFifo__do_enq_T;
        end
      end else begin
        if3_bim_bypassFifo_maybe_full <= if3_bim_bypassFifo__do_enq_T;
      end
    end
  end
  always @(posedge if3_bim_clock) begin
    if3_bim_por_reset <= if3_bim_reset | if3_bim__GEN_4; // @[BIM.scala 37:{26,26}]
    if (if3_bim_reset) begin // @[Counter.scala 61:40]
      if3_bim_reset_cl <= 3'h0; // @[Counter.scala 61:40]
    end else if (if3_bim_por_reset) begin // @[Counter.scala 136:24]
      if3_bim_reset_cl <= if3_bim__wrap_value_T_1; // @[Counter.scala 77:15]
    end
    if3_bim_bypassFifo_io_enq_valid_REG <= if3_bim_io_req_ready & if3_bim_io_req_valid; // @[Decoupled.scala 52:35]
  end
  always @(posedge if3_btbFifo_fifo_clock) begin
    if (!(if3_btbFifo_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if3_btbFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_btbFifo_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if3_btbFifo_fifo_buf_0_target <= if3_btbFifo_fifo_io_enq_0_bits_target;
        end else if (if3_btbFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_btbFifo_fifo_buf_0_target <= if3_btbFifo_fifo_buf_1_target; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if3_btbFifo_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if3_btbFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_btbFifo_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if3_btbFifo_fifo_buf_1_target <= if3_btbFifo_fifo_io_enq_0_bits_target;
        end else if (!(if3_btbFifo_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if3_btbFifo_fifo_buf_1_target <= if3_btbFifo_fifo_buf_0_target;
        end
      end
    end
    if (if3_btbFifo_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_btbFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_btbFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_btbFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_btbFifo_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~if3_btbFifo_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_btbFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_btbFifo_fifo_buf_valid_0 <= if3_btbFifo_fifo__GEN_6;
      end
    end else begin
      if3_btbFifo_fifo_buf_valid_0 <= if3_btbFifo_fifo__GEN_6;
    end
    if (if3_btbFifo_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_btbFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_btbFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_btbFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_btbFifo_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (if3_btbFifo_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_btbFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_btbFifo_fifo_buf_valid_1 <= if3_btbFifo_fifo__GEN_7;
      end
    end else begin
      if3_btbFifo_fifo_buf_valid_1 <= if3_btbFifo_fifo__GEN_7;
    end
    if (if3_btbFifo_fifo_reset) begin // @[MultiPortFifo.scala 60:27]
      if3_btbFifo_fifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (if3_btbFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_btbFifo_fifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      if3_btbFifo_fifo_rd_ptr <= if3_btbFifo_fifo__rd_ptr_T_2; // @[MultiPortFifo.scala 106:16]
    end
    if (if3_btbFifo_fifo_reset) begin // @[MultiPortFifo.scala 61:27]
      if3_btbFifo_fifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (if3_btbFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_btbFifo_fifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      if3_btbFifo_fifo_wr_ptr <= if3_btbFifo_fifo__wr_ptr_T_2; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_btbFifo_fifo__T_9 & if3_btbFifo_fifo__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_btbFifo_fifo__T_7 & if3_btbFifo_fifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_btbFifo_fifo__T_9 & if3_btbFifo_fifo__T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_btbFifo_fifo__T_16 & if3_btbFifo_fifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_btbFifo_rePortIn_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_btbFifo_rePortIn__T_4 & if3_btbFifo_rePortIn__T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_btbFifo_rePortIn__T_2 & if3_btbFifo_rePortIn__T_4) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_btbFifo_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_btbFifo__T_8 & if3_btbFifo__T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_btbFifo__T_6 & if3_btbFifo__T_8) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_btbFifo__T_8 & if3_btbFifo__T_18) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_btbFifo__T_15 & if3_btbFifo__T_8) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_bimFifo_fifo_clock) begin
    if (!(if3_bimFifo_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if3_bimFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_bimFifo_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if3_bimFifo_fifo_buf_0_bim_p <= if3_bimFifo_fifo_io_enq_0_bits_bim_p;
        end else if (if3_bimFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_bimFifo_fifo_buf_0_bim_p <= if3_bimFifo_fifo_buf_1_bim_p; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if3_bimFifo_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if3_bimFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_bimFifo_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if3_bimFifo_fifo_buf_0_bim_h <= if3_bimFifo_fifo_io_enq_0_bits_bim_h;
        end else if (if3_bimFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_bimFifo_fifo_buf_0_bim_h <= if3_bimFifo_fifo_buf_1_bim_h; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if3_bimFifo_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if3_bimFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_bimFifo_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if3_bimFifo_fifo_buf_1_bim_p <= if3_bimFifo_fifo_io_enq_0_bits_bim_p;
        end else if (!(if3_bimFifo_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if3_bimFifo_fifo_buf_1_bim_p <= if3_bimFifo_fifo_buf_0_bim_p;
        end
      end
    end
    if (!(if3_bimFifo_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if3_bimFifo_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_bimFifo_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if3_bimFifo_fifo_buf_1_bim_h <= if3_bimFifo_fifo_io_enq_0_bits_bim_h;
        end else if (!(if3_bimFifo_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if3_bimFifo_fifo_buf_1_bim_h <= if3_bimFifo_fifo_buf_0_bim_h;
        end
      end
    end
    if (if3_bimFifo_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_bimFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_bimFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_bimFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_bimFifo_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~if3_bimFifo_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_bimFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_bimFifo_fifo_buf_valid_0 <= if3_bimFifo_fifo__GEN_6;
      end
    end else begin
      if3_bimFifo_fifo_buf_valid_0 <= if3_bimFifo_fifo__GEN_6;
    end
    if (if3_bimFifo_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_bimFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_bimFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_bimFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_bimFifo_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (if3_bimFifo_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_bimFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_bimFifo_fifo_buf_valid_1 <= if3_bimFifo_fifo__GEN_7;
      end
    end else begin
      if3_bimFifo_fifo_buf_valid_1 <= if3_bimFifo_fifo__GEN_7;
    end
    if (if3_bimFifo_fifo_reset) begin // @[MultiPortFifo.scala 60:27]
      if3_bimFifo_fifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (if3_bimFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_bimFifo_fifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      if3_bimFifo_fifo_rd_ptr <= if3_bimFifo_fifo__rd_ptr_T_2; // @[MultiPortFifo.scala 106:16]
    end
    if (if3_bimFifo_fifo_reset) begin // @[MultiPortFifo.scala 61:27]
      if3_bimFifo_fifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (if3_bimFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_bimFifo_fifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      if3_bimFifo_fifo_wr_ptr <= if3_bimFifo_fifo__wr_ptr_T_2; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_bimFifo_fifo__T_9 & if3_bimFifo_fifo__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_bimFifo_fifo__T_7 & if3_bimFifo_fifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_bimFifo_fifo__T_9 & if3_bimFifo_fifo__T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_bimFifo_fifo__T_16 & if3_bimFifo_fifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_bimFifo_rePortIn_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_bimFifo_rePortIn__T_4 & if3_bimFifo_rePortIn__T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_bimFifo_rePortIn__T_2 & if3_bimFifo_rePortIn__T_4) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_bimFifo_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_bimFifo__T_8 & if3_bimFifo__T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_bimFifo__T_6 & if3_bimFifo__T_8) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_bimFifo__T_8 & if3_bimFifo__T_18) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_bimFifo__T_15 & if3_bimFifo__T_8) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_tageFifo_fifo_clock) begin
    if (if3_tageFifo_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_tageFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_tageFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_tageFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_tageFifo_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~if3_tageFifo_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_tageFifo_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_tageFifo_fifo_buf_valid_0 <= if3_tageFifo_fifo__GEN_6;
      end
    end else begin
      if3_tageFifo_fifo_buf_valid_0 <= if3_tageFifo_fifo__GEN_6;
    end
    if (if3_tageFifo_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_tageFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_tageFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_tageFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_tageFifo_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (if3_tageFifo_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_tageFifo_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_tageFifo_fifo_buf_valid_1 <= if3_tageFifo_fifo__GEN_7;
      end
    end else begin
      if3_tageFifo_fifo_buf_valid_1 <= if3_tageFifo_fifo__GEN_7;
    end
    if (if3_tageFifo_fifo_reset) begin // @[MultiPortFifo.scala 60:27]
      if3_tageFifo_fifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (if3_tageFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_tageFifo_fifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      if3_tageFifo_fifo_rd_ptr <= if3_tageFifo_fifo__rd_ptr_T_2; // @[MultiPortFifo.scala 106:16]
    end
    if (if3_tageFifo_fifo_reset) begin // @[MultiPortFifo.scala 61:27]
      if3_tageFifo_fifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (if3_tageFifo_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_tageFifo_fifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      if3_tageFifo_fifo_wr_ptr <= if3_tageFifo_fifo__wr_ptr_T_2; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_tageFifo_fifo__T_9 & if3_tageFifo_fifo__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_tageFifo_fifo__T_7 & if3_tageFifo_fifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_tageFifo_fifo__T_9 & if3_tageFifo_fifo__T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_tageFifo_fifo__T_16 & if3_tageFifo_fifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_tageFifo_rePortIn_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_tageFifo_rePortIn__T_4 & if3_tageFifo_rePortIn__T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_tageFifo_rePortIn__T_2 & if3_tageFifo_rePortIn__T_4) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_tageFifo_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_tageFifo__T_8 & if3_tageFifo__T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_tageFifo__T_6 & if3_tageFifo__T_8) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_tageFifo__T_8 & if3_tageFifo__T_18) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_tageFifo__T_15 & if3_tageFifo__T_8) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_if3_resp_fifo_clock) begin
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h0 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_isRVC <= if3_if3_resp_fifo_io_enq_3_bits_isRVC;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_isRVC <= if3_if3_resp_fifo_buf_3_isRVC; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_0_isRVC <= if3_if3_resp_fifo__GEN_474;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_isRVC <= if3_if3_resp_fifo_io_enq_2_bits_isRVC;
        end else begin
          if3_if3_resp_fifo_buf_0_isRVC <= if3_if3_resp_fifo__GEN_353;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_0_isRVC <= if3_if3_resp_fifo__buf_T_3_isRVC; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_0_isRVC <= if3_if3_resp_fifo__GEN_96;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h0 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_instr <= if3_if3_resp_fifo_io_enq_3_bits_instr;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_instr <= if3_if3_resp_fifo_buf_3_instr; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_0_instr <= if3_if3_resp_fifo__GEN_484;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_instr <= if3_if3_resp_fifo_io_enq_2_bits_instr;
        end else begin
          if3_if3_resp_fifo_buf_0_instr <= if3_if3_resp_fifo__GEN_363;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_0_instr <= if3_if3_resp_fifo__buf_T_3_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_0_instr <= if3_if3_resp_fifo__GEN_136;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h0 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_pc <= if3_if3_resp_fifo_io_enq_3_bits_pc;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_pc <= if3_if3_resp_fifo_buf_3_pc; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_0_pc <= if3_if3_resp_fifo__GEN_485;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_pc <= if3_if3_resp_fifo_io_enq_2_bits_pc;
        end else begin
          if3_if3_resp_fifo_buf_0_pc <= if3_if3_resp_fifo__GEN_364;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_0_pc <= if3_if3_resp_fifo__buf_T_3_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_0_pc <= if3_if3_resp_fifo__GEN_140;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h0 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_isRedirect <= if3_if3_resp_fifo_io_enq_3_bits_isRedirect;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_isRedirect <= if3_if3_resp_fifo_buf_3_isRedirect; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_0_isRedirect <= if3_if3_resp_fifo__GEN_487;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_isRedirect <= if3_if3_resp_fifo_io_enq_2_bits_isRedirect;
        end else begin
          if3_if3_resp_fifo_buf_0_isRedirect <= if3_if3_resp_fifo__GEN_366;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_0_isRedirect <= if3_if3_resp_fifo__buf_T_3_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_0_isRedirect <= if3_if3_resp_fifo__GEN_148;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h0 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_target <= if3_if3_resp_fifo_io_enq_3_bits_target;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_target <= if3_if3_resp_fifo_buf_3_target; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_0_target <= if3_if3_resp_fifo__GEN_488;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_0_target <= if3_if3_resp_fifo_io_enq_2_bits_target;
        end else begin
          if3_if3_resp_fifo_buf_0_target <= if3_if3_resp_fifo__GEN_367;
        end
      end else if (2'h0 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_0_target <= if3_if3_resp_fifo__buf_T_3_target; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_0_target <= if3_if3_resp_fifo__GEN_152;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_isRVC <= if3_if3_resp_fifo_io_enq_3_bits_isRVC;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_isRVC <= if3_if3_resp_fifo_buf_3_isRVC; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_1_isRVC <= if3_if3_resp_fifo__GEN_474;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_isRVC <= if3_if3_resp_fifo_io_enq_2_bits_isRVC;
        end else begin
          if3_if3_resp_fifo_buf_1_isRVC <= if3_if3_resp_fifo__GEN_353;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_1_isRVC <= if3_if3_resp_fifo__buf_T_3_isRVC; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_1_isRVC <= if3_if3_resp_fifo__GEN_97;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_instr <= if3_if3_resp_fifo_io_enq_3_bits_instr;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_instr <= if3_if3_resp_fifo_buf_3_instr; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_1_instr <= if3_if3_resp_fifo__GEN_484;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_instr <= if3_if3_resp_fifo_io_enq_2_bits_instr;
        end else begin
          if3_if3_resp_fifo_buf_1_instr <= if3_if3_resp_fifo__GEN_363;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_1_instr <= if3_if3_resp_fifo__buf_T_3_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_1_instr <= if3_if3_resp_fifo__GEN_137;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_pc <= if3_if3_resp_fifo_io_enq_3_bits_pc;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_pc <= if3_if3_resp_fifo_buf_3_pc; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_1_pc <= if3_if3_resp_fifo__GEN_485;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_pc <= if3_if3_resp_fifo_io_enq_2_bits_pc;
        end else begin
          if3_if3_resp_fifo_buf_1_pc <= if3_if3_resp_fifo__GEN_364;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_1_pc <= if3_if3_resp_fifo__buf_T_3_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_1_pc <= if3_if3_resp_fifo__GEN_141;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_isRedirect <= if3_if3_resp_fifo_io_enq_3_bits_isRedirect;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_isRedirect <= if3_if3_resp_fifo_buf_3_isRedirect; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_1_isRedirect <= if3_if3_resp_fifo__GEN_487;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_isRedirect <= if3_if3_resp_fifo_io_enq_2_bits_isRedirect;
        end else begin
          if3_if3_resp_fifo_buf_1_isRedirect <= if3_if3_resp_fifo__GEN_366;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_1_isRedirect <= if3_if3_resp_fifo__buf_T_3_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_1_isRedirect <= if3_if3_resp_fifo__GEN_149;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h1 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_target <= if3_if3_resp_fifo_io_enq_3_bits_target;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_target <= if3_if3_resp_fifo_buf_3_target; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_1_target <= if3_if3_resp_fifo__GEN_488;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_1_target <= if3_if3_resp_fifo_io_enq_2_bits_target;
        end else begin
          if3_if3_resp_fifo_buf_1_target <= if3_if3_resp_fifo__GEN_367;
        end
      end else if (2'h1 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_1_target <= if3_if3_resp_fifo__buf_T_3_target; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_1_target <= if3_if3_resp_fifo__GEN_153;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_isRVC <= if3_if3_resp_fifo_io_enq_3_bits_isRVC;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_isRVC <= if3_if3_resp_fifo_buf_3_isRVC; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_2_isRVC <= if3_if3_resp_fifo__GEN_474;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_isRVC <= if3_if3_resp_fifo_io_enq_2_bits_isRVC;
        end else begin
          if3_if3_resp_fifo_buf_2_isRVC <= if3_if3_resp_fifo__GEN_353;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_2_isRVC <= if3_if3_resp_fifo__buf_T_3_isRVC; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_2_isRVC <= if3_if3_resp_fifo__GEN_98;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_instr <= if3_if3_resp_fifo_io_enq_3_bits_instr;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_instr <= if3_if3_resp_fifo_buf_3_instr; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_2_instr <= if3_if3_resp_fifo__GEN_484;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_instr <= if3_if3_resp_fifo_io_enq_2_bits_instr;
        end else begin
          if3_if3_resp_fifo_buf_2_instr <= if3_if3_resp_fifo__GEN_363;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_2_instr <= if3_if3_resp_fifo__buf_T_3_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_2_instr <= if3_if3_resp_fifo__GEN_138;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_pc <= if3_if3_resp_fifo_io_enq_3_bits_pc;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_pc <= if3_if3_resp_fifo_buf_3_pc; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_2_pc <= if3_if3_resp_fifo__GEN_485;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_pc <= if3_if3_resp_fifo_io_enq_2_bits_pc;
        end else begin
          if3_if3_resp_fifo_buf_2_pc <= if3_if3_resp_fifo__GEN_364;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_2_pc <= if3_if3_resp_fifo__buf_T_3_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_2_pc <= if3_if3_resp_fifo__GEN_142;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_isRedirect <= if3_if3_resp_fifo_io_enq_3_bits_isRedirect;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_isRedirect <= if3_if3_resp_fifo_buf_3_isRedirect; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_2_isRedirect <= if3_if3_resp_fifo__GEN_487;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_isRedirect <= if3_if3_resp_fifo_io_enq_2_bits_isRedirect;
        end else begin
          if3_if3_resp_fifo_buf_2_isRedirect <= if3_if3_resp_fifo__GEN_366;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_2_isRedirect <= if3_if3_resp_fifo__buf_T_3_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_2_isRedirect <= if3_if3_resp_fifo__GEN_150;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h2 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_target <= if3_if3_resp_fifo_io_enq_3_bits_target;
        end else if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_target <= if3_if3_resp_fifo_buf_3_target; // @[MultiPortFifo.scala 101:33]
        end else begin
          if3_if3_resp_fifo_buf_2_target <= if3_if3_resp_fifo__GEN_488;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_2_target <= if3_if3_resp_fifo_io_enq_2_bits_target;
        end else begin
          if3_if3_resp_fifo_buf_2_target <= if3_if3_resp_fifo__GEN_367;
        end
      end else if (2'h2 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_2_target <= if3_if3_resp_fifo__buf_T_3_target; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_2_target <= if3_if3_resp_fifo__GEN_154;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_isRVC <= if3_if3_resp_fifo_io_enq_3_bits_isRVC;
        end else if (!(2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_isRVC <= if3_if3_resp_fifo__GEN_474;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_isRVC <= if3_if3_resp_fifo_io_enq_2_bits_isRVC;
        end else begin
          if3_if3_resp_fifo_buf_3_isRVC <= if3_if3_resp_fifo__GEN_353;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_3_isRVC <= if3_if3_resp_fifo__buf_T_3_isRVC; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_3_isRVC <= if3_if3_resp_fifo__GEN_99;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_instr <= if3_if3_resp_fifo_io_enq_3_bits_instr;
        end else if (!(2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_instr <= if3_if3_resp_fifo__GEN_484;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_instr <= if3_if3_resp_fifo_io_enq_2_bits_instr;
        end else begin
          if3_if3_resp_fifo_buf_3_instr <= if3_if3_resp_fifo__GEN_363;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_3_instr <= if3_if3_resp_fifo__buf_T_3_instr; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_3_instr <= if3_if3_resp_fifo__GEN_139;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_pc <= if3_if3_resp_fifo_io_enq_3_bits_pc;
        end else if (!(2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_pc <= if3_if3_resp_fifo__GEN_485;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_pc <= if3_if3_resp_fifo_io_enq_2_bits_pc;
        end else begin
          if3_if3_resp_fifo_buf_3_pc <= if3_if3_resp_fifo__GEN_364;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_3_pc <= if3_if3_resp_fifo__buf_T_3_pc; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_3_pc <= if3_if3_resp_fifo__GEN_143;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_isRedirect <= if3_if3_resp_fifo_io_enq_3_bits_isRedirect;
        end else if (!(2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_isRedirect <= if3_if3_resp_fifo__GEN_487;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_isRedirect <= if3_if3_resp_fifo_io_enq_2_bits_isRedirect;
        end else begin
          if3_if3_resp_fifo_buf_3_isRedirect <= if3_if3_resp_fifo__GEN_366;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_3_isRedirect <= if3_if3_resp_fifo__buf_T_3_isRedirect; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_3_isRedirect <= if3_if3_resp_fifo__GEN_151;
      end
    end
    if (!(if3_if3_resp_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_6) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_target <= if3_if3_resp_fifo_io_enq_3_bits_target;
        end else if (!(2'h3 == if3_if3_resp_fifo__io_enq_3_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_target <= if3_if3_resp_fifo__GEN_488;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_2_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if3_if3_resp_fifo__T_4) begin // @[MultiPortFifo.scala 101:33]
          if3_if3_resp_fifo_buf_3_target <= if3_if3_resp_fifo_io_enq_2_bits_target;
        end else begin
          if3_if3_resp_fifo_buf_3_target <= if3_if3_resp_fifo__GEN_367;
        end
      end else if (2'h3 == if3_if3_resp_fifo__io_enq_1_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if3_if3_resp_fifo_buf_3_target <= if3_if3_resp_fifo__buf_T_3_target; // @[MultiPortFifo.scala 101:27]
      end else begin
        if3_if3_resp_fifo_buf_3_target <= if3_if3_resp_fifo__GEN_155;
      end
    end
    if (if3_if3_resp_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_if3_resp_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_if3_resp_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_if3_resp_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_if3_resp_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (2'h0 == if3_if3_resp_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_if3_resp_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_if3_resp_fifo_buf_valid_0 <= if3_if3_resp_fifo__GEN_432;
      end
    end else begin
      if3_if3_resp_fifo_buf_valid_0 <= if3_if3_resp_fifo__GEN_432;
    end
    if (if3_if3_resp_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_if3_resp_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_if3_resp_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_if3_resp_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_if3_resp_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (2'h1 == if3_if3_resp_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_if3_resp_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_if3_resp_fifo_buf_valid_1 <= if3_if3_resp_fifo__GEN_433;
      end
    end else begin
      if3_if3_resp_fifo_buf_valid_1 <= if3_if3_resp_fifo__GEN_433;
    end
    if (if3_if3_resp_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_if3_resp_fifo_buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_if3_resp_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_if3_resp_fifo_buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_if3_resp_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (2'h2 == if3_if3_resp_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_if3_resp_fifo_buf_valid_2 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_if3_resp_fifo_buf_valid_2 <= if3_if3_resp_fifo__GEN_434;
      end
    end else begin
      if3_if3_resp_fifo_buf_valid_2 <= if3_if3_resp_fifo__GEN_434;
    end
    if (if3_if3_resp_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if3_if3_resp_fifo_buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if3_if3_resp_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_if3_resp_fifo_buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if3_if3_resp_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (2'h3 == if3_if3_resp_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if3_if3_resp_fifo_buf_valid_3 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if3_if3_resp_fifo_buf_valid_3 <= if3_if3_resp_fifo__GEN_435;
      end
    end else begin
      if3_if3_resp_fifo_buf_valid_3 <= if3_if3_resp_fifo__GEN_435;
    end
    if (if3_if3_resp_fifo_reset) begin // @[MultiPortFifo.scala 60:27]
      if3_if3_resp_fifo_rd_ptr <= 2'h0; // @[MultiPortFifo.scala 60:27]
    end else if (if3_if3_resp_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if3_if3_resp_fifo_rd_ptr <= 2'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      if3_if3_resp_fifo_rd_ptr <= if3_if3_resp_fifo__rd_ptr_T_2; // @[MultiPortFifo.scala 106:16]
    end
    if3_if3_resp_fifo_wr_ptr <= _GEN_175[1:0]; // @[MultiPortFifo.scala 61:{27,27}]
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_16) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_13 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_52) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_49 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_61) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_58 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_88) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_85 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_97) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_94 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_106) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_103 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_124) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_121 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_133) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_130 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_142) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_139 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_151) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_148 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_157 & if3_if3_resp_fifo__T_15) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_2 & if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_166) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T & (if3_if3_resp_fifo__T_2 & if3_if3_resp_fifo__T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_4 & if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_166) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T & (if3_if3_resp_fifo__T_4 & if3_if3_resp_fifo__T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_4 & if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_175) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_2 & (if3_if3_resp_fifo__T_4 & if3_if3_resp_fifo__T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_6 & if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_166) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T & (if3_if3_resp_fifo__T_6 & if3_if3_resp_fifo__T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_6 & if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_175) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_2 & (if3_if3_resp_fifo__T_6 & if3_if3_resp_fifo__T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_if3_resp_fifo__T_6 & if3_if3_resp_fifo__T_15 & if3_if3_resp_fifo__T_188) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, illegal multi-port-fifo behavior\n    at MultiPortFifo.scala:169 assert( io.enq(j).fire, \"Assert Failed, illegal multi-port-fifo behavior\" )\n"
            ); // @[MultiPortFifo.scala 169:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3_if3_resp_fifo__T_4 & (if3_if3_resp_fifo__T_6 & if3_if3_resp_fifo__T_15)) begin
          $fatal; // @[MultiPortFifo.scala 169:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if3_clock) begin
    if (if3_reset) begin // @[IF3.scala 54:29]
      if3_pipeLineLock <= 1'h0; // @[IF3.scala 54:29]
    end else if (if3__btb_io_req_valid_T) begin // @[IF3.scala 328:42]
      if3_pipeLineLock <= 1'h0; // @[IF3.scala 328:57]
    end else begin
      if3_pipeLineLock <= if3__GEN_401;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3_is_instr32_0 & if3__T_15 & if3__T_16) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF3.scala:132 assert(io.if3_req(i).fire === io.if3_req(i+1).fire)\n"); // @[IF3.scala 132:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__T_13 & (if3_is_instr32_0 & if3__T_15)) begin
          $fatal; // @[IF3.scala 132:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__T_19 & if3__T_15 & if3__T_23) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\n    at IF3.scala:160 when( io.if3_req(i).fire  & io.if3_req(i).bits.isRedirect ) { assert(io.if3_req(i+1).fire, \"Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\") }\n"
            ); // @[IF3.scala 160:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__reAlign_0_valid_T_1 & (if3__T_19 & if3__T_15)) begin
          $fatal; // @[IF3.scala 160:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__T_24 & if3__T_15 & if3__T_29) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, No succession isRedirect will appear\n    at IF3.scala:161 when( io.if3_req(i).valid & io.if3_req(i).bits.isRedirect ) { assert( ~(io.if3_req(i+1).valid & io.if3_req(i+1).bits.isRedirect), \"Assert Failed at IF3, No succession isRedirect will appear\" ) }\n"
            ); // @[IF3.scala 161:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__T_26 & (if3__T_24 & if3__T_15)) begin
          $fatal; // @[IF3.scala 161:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__T_3 & if3_is_instr32_1 & if3__T_15 & if3__T_37) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF3.scala:132 assert(io.if3_req(i).fire === io.if3_req(i+1).fire)\n"); // @[IF3.scala 132:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__T_34 & (if3__T_3 & if3_is_instr32_1 & if3__T_15)) begin
          $fatal; // @[IF3.scala 132:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__T_40 & if3__T_15 & if3__T_44) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\n    at IF3.scala:160 when( io.if3_req(i).fire  & io.if3_req(i).bits.isRedirect ) { assert(io.if3_req(i+1).fire, \"Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\") }\n"
            ); // @[IF3.scala 160:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__reAlign_1_valid_T_1 & (if3__T_40 & if3__T_15)) begin
          $fatal; // @[IF3.scala 160:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__T_25 & if3__T_15 & if3__T_50) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, No succession isRedirect will appear\n    at IF3.scala:161 when( io.if3_req(i).valid & io.if3_req(i).bits.isRedirect ) { assert( ~(io.if3_req(i+1).valid & io.if3_req(i+1).bits.isRedirect), \"Assert Failed at IF3, No succession isRedirect will appear\" ) }\n"
            ); // @[IF3.scala 161:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__T_47 & (if3__T_25 & if3__T_15)) begin
          $fatal; // @[IF3.scala 161:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__T_6 & if3_is_instr32_2 & if3__T_15 & if3__T_58) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF3.scala:132 assert(io.if3_req(i).fire === io.if3_req(i+1).fire)\n"); // @[IF3.scala 132:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__T_55 & (if3__T_6 & if3_is_instr32_2 & if3__T_15)) begin
          $fatal; // @[IF3.scala 132:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__T_61 & if3__T_15 & if3__T_65) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\n    at IF3.scala:160 when( io.if3_req(i).fire  & io.if3_req(i).bits.isRedirect ) { assert(io.if3_req(i+1).fire, \"Assert Failed at IF3, Redirect will pop next-entry either by rv32 or force-pop!\") }\n"
            ); // @[IF3.scala 160:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__reAlign_2_valid_T_1 & (if3__T_61 & if3__T_15)) begin
          $fatal; // @[IF3.scala 160:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__T_46 & if3__T_15 & if3__T_71) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, No succession isRedirect will appear\n    at IF3.scala:161 when( io.if3_req(i).valid & io.if3_req(i).bits.isRedirect ) { assert( ~(io.if3_req(i+1).valid & io.if3_req(i+1).bits.isRedirect), \"Assert Failed at IF3, No succession isRedirect will appear\" ) }\n"
            ); // @[IF3.scala 161:75]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__T_68 & (if3__T_46 & if3__T_15)) begin
          $fatal; // @[IF3.scala 161:75]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if3__reAlign_2_valid_T_1 & if3__T_15 & if3__T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IF3, never Redirect at last-entry!\n    at IF3.scala:163 when( io.if3_req(i).fire ) { assert( ~io.if3_req(i).bits.isRedirect, \"Assert Failed at IF3, never Redirect at last-entry!\" ) }\n"
            ); // @[IF3.scala 163:42]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if3__T_75 & (if3__reAlign_2_valid_T_1 & if3__T_15)) begin
          $fatal; // @[IF3.scala 163:42]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if4_ras_buf_target_clock) begin
    if (if4_ras_buf_target_MPORT_en & if4_ras_buf_target_MPORT_mask) begin
      if4_ras_buf_target[if4_ras_buf_target_MPORT_addr] <= if4_ras_buf_target_MPORT_data; // @[RAS.scala 43:18]
    end
  end
  always @(posedge if4_ras_clock) begin
    if (if4_ras_reset) begin // @[RAS.scala 44:26]
      if4_ras_btm_ptr <= 3'h0; // @[RAS.scala 44:26]
    end else if (if4_ras_io_flush) begin // @[RAS.scala 59:20]
      if4_ras_btm_ptr <= 3'h0; // @[RAS.scala 60:15]
    end else if (if4_ras_io_enq_valid) begin // @[RAS.scala 64:27]
      if (if4_ras_is_full) begin // @[RAS.scala 65:23]
        if4_ras_btm_ptr <= if4_ras__btm_ptr_T_1; // @[RAS.scala 66:19]
      end
    end
    if (if4_ras_reset) begin // @[RAS.scala 45:26]
      if4_ras_top_ptr <= 3'h0; // @[RAS.scala 45:26]
    end else if (if4_ras_io_flush) begin // @[RAS.scala 59:20]
      if4_ras_top_ptr <= 3'h0; // @[RAS.scala 61:15]
    end else if (if4_ras__T) begin // @[RAS.scala 70:27]
      if4_ras_top_ptr <= if4_ras__top_ptr_T_3; // @[RAS.scala 71:17]
    end else if (if4_ras_io_enq_valid) begin // @[RAS.scala 64:27]
      if4_ras_top_ptr <= if4_ras__top_ptr_T_1; // @[RAS.scala 68:17]
    end
    if4_ras_io_deq_bits_REG_target <= if4_ras_buf_target_io_deq_bits_MPORT_data; // @[RAS.scala 76:29]
  end
  always @(posedge if4_instr_fifo_clock) begin
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_lui <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_lui;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_lui <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_lui;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_lui <= if4_instr_fifo_buf_1_alu_isa_lui; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_auipc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_auipc;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_auipc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_auipc;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_auipc <= if4_instr_fifo_buf_1_alu_isa_auipc; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_addi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addi;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_addi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addi;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_addi <= if4_instr_fifo_buf_1_alu_isa_addi; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_addiw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addiw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_addiw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addiw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_addiw <= if4_instr_fifo_buf_1_alu_isa_addiw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_slti <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slti;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_slti <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slti;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_slti <= if4_instr_fifo_buf_1_alu_isa_slti; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_sltiu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sltiu;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_sltiu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sltiu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_sltiu <= if4_instr_fifo_buf_1_alu_isa_sltiu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_xori <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_xori;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_xori <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_xori;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_xori <= if4_instr_fifo_buf_1_alu_isa_xori; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_ori <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_ori;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_ori <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_ori;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_ori <= if4_instr_fifo_buf_1_alu_isa_ori; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_andi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_andi;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_andi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_andi;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_andi <= if4_instr_fifo_buf_1_alu_isa_andi; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_slli <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slli;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_slli <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slli;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_slli <= if4_instr_fifo_buf_1_alu_isa_slli; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_slliw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slliw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_slliw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slliw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_slliw <= if4_instr_fifo_buf_1_alu_isa_slliw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_srli <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srli;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_srli <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srli;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_srli <= if4_instr_fifo_buf_1_alu_isa_srli; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_srliw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srliw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_srliw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srliw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_srliw <= if4_instr_fifo_buf_1_alu_isa_srliw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_srai <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srai;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_srai <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srai;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_srai <= if4_instr_fifo_buf_1_alu_isa_srai; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_sraiw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sraiw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_sraiw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sraiw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_sraiw <= if4_instr_fifo_buf_1_alu_isa_sraiw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_add <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_add;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_add <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_add;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_add <= if4_instr_fifo_buf_1_alu_isa_add; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_addw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_addw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_addw <= if4_instr_fifo_buf_1_alu_isa_addw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_sub <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sub;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_sub <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sub;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_sub <= if4_instr_fifo_buf_1_alu_isa_sub; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_subw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_subw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_subw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_subw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_subw <= if4_instr_fifo_buf_1_alu_isa_subw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_sll <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sll;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_sll <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sll;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_sll <= if4_instr_fifo_buf_1_alu_isa_sll; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_sllw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sllw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_sllw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sllw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_sllw <= if4_instr_fifo_buf_1_alu_isa_sllw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_slt <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slt;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_slt <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slt;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_slt <= if4_instr_fifo_buf_1_alu_isa_slt; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_sltu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sltu;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_sltu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sltu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_sltu <= if4_instr_fifo_buf_1_alu_isa_sltu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_xor <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_xor;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_xor <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_xor;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_xor <= if4_instr_fifo_buf_1_alu_isa_xor; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_srl <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srl;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_srl <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srl;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_srl <= if4_instr_fifo_buf_1_alu_isa_srl; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_srlw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srlw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_srlw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srlw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_srlw <= if4_instr_fifo_buf_1_alu_isa_srlw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_sra <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sra;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_sra <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sra;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_sra <= if4_instr_fifo_buf_1_alu_isa_sra; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_sraw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sraw;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_sraw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sraw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_sraw <= if4_instr_fifo_buf_1_alu_isa_sraw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_or <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_or;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_or <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_or;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_or <= if4_instr_fifo_buf_1_alu_isa_or; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_and <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_and;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_and <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_and;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_and <= if4_instr_fifo_buf_1_alu_isa_and; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_alu_isa_wfi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_wfi;
          end else begin
            if4_instr_fifo_buf_0_alu_isa_wfi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_wfi;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_alu_isa_wfi <= if4_instr_fifo_buf_1_alu_isa_wfi; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_bru_isa_jal <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_jal;
          end else begin
            if4_instr_fifo_buf_0_bru_isa_jal <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_jal;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_bru_isa_jal <= if4_instr_fifo_buf_1_bru_isa_jal; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_bru_isa_jalr <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_jalr;
          end else begin
            if4_instr_fifo_buf_0_bru_isa_jalr <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_jalr;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_bru_isa_jalr <= if4_instr_fifo_buf_1_bru_isa_jalr; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_bru_isa_beq <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_beq;
          end else begin
            if4_instr_fifo_buf_0_bru_isa_beq <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_beq;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_bru_isa_beq <= if4_instr_fifo_buf_1_bru_isa_beq; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_bru_isa_bne <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bne;
          end else begin
            if4_instr_fifo_buf_0_bru_isa_bne <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bne;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_bru_isa_bne <= if4_instr_fifo_buf_1_bru_isa_bne; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_bru_isa_blt <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_blt;
          end else begin
            if4_instr_fifo_buf_0_bru_isa_blt <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_blt;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_bru_isa_blt <= if4_instr_fifo_buf_1_bru_isa_blt; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_bru_isa_bge <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bge;
          end else begin
            if4_instr_fifo_buf_0_bru_isa_bge <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bge;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_bru_isa_bge <= if4_instr_fifo_buf_1_bru_isa_bge; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_bru_isa_bltu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bltu;
          end else begin
            if4_instr_fifo_buf_0_bru_isa_bltu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bltu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_bru_isa_bltu <= if4_instr_fifo_buf_1_bru_isa_bltu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_bru_isa_bgeu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bgeu;
          end else begin
            if4_instr_fifo_buf_0_bru_isa_bgeu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bgeu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_bru_isa_bgeu <= if4_instr_fifo_buf_1_bru_isa_bgeu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_lb <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lb;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_lb <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lb;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_lb <= if4_instr_fifo_buf_1_lsu_isa_lb; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_lh <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lh;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_lh <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lh;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_lh <= if4_instr_fifo_buf_1_lsu_isa_lh; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_lw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lw;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_lw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_lw <= if4_instr_fifo_buf_1_lsu_isa_lw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_ld <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_ld;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_ld <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_ld;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_ld <= if4_instr_fifo_buf_1_lsu_isa_ld; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_lbu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lbu;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_lbu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lbu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_lbu <= if4_instr_fifo_buf_1_lsu_isa_lbu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_lhu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lhu;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_lhu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lhu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_lhu <= if4_instr_fifo_buf_1_lsu_isa_lhu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_lwu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lwu;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_lwu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lwu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_lwu <= if4_instr_fifo_buf_1_lsu_isa_lwu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_sb <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sb;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_sb <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sb;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_sb <= if4_instr_fifo_buf_1_lsu_isa_sb; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_sh <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sh;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_sh <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sh;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_sh <= if4_instr_fifo_buf_1_lsu_isa_sh; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_sw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sw;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_sw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_sw <= if4_instr_fifo_buf_1_lsu_isa_sw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_sd <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sd;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_sd <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sd;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_sd <= if4_instr_fifo_buf_1_lsu_isa_sd; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_fence <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fence;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_fence <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fence;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_fence <= if4_instr_fifo_buf_1_lsu_isa_fence; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_fence_i <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fence_i;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_fence_i <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fence_i;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_fence_i <= if4_instr_fifo_buf_1_lsu_isa_fence_i; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_sfence_vma <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sfence_vma;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_sfence_vma <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sfence_vma;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_sfence_vma <= if4_instr_fifo_buf_1_lsu_isa_sfence_vma; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_lr_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lr_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_lr_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lr_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_lr_w <= if4_instr_fifo_buf_1_lsu_isa_lr_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_sc_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sc_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_sc_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sc_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_sc_w <= if4_instr_fifo_buf_1_lsu_isa_sc_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoswap_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoswap_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoswap_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoswap_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoswap_w <= if4_instr_fifo_buf_1_lsu_isa_amoswap_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoadd_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoadd_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoadd_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoadd_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoadd_w <= if4_instr_fifo_buf_1_lsu_isa_amoadd_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoxor_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoxor_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoxor_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoxor_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoxor_w <= if4_instr_fifo_buf_1_lsu_isa_amoxor_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoand_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoand_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoand_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoand_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoand_w <= if4_instr_fifo_buf_1_lsu_isa_amoand_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoor_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoor_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoor_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoor_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoor_w <= if4_instr_fifo_buf_1_lsu_isa_amoor_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amomin_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomin_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amomin_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomin_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amomin_w <= if4_instr_fifo_buf_1_lsu_isa_amomin_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amomax_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomax_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amomax_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomax_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amomax_w <= if4_instr_fifo_buf_1_lsu_isa_amomax_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amominu_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amominu_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amominu_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amominu_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amominu_w <= if4_instr_fifo_buf_1_lsu_isa_amominu_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amomaxu_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomaxu_w;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amomaxu_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomaxu_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amomaxu_w <= if4_instr_fifo_buf_1_lsu_isa_amomaxu_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_lr_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lr_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_lr_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lr_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_lr_d <= if4_instr_fifo_buf_1_lsu_isa_lr_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_sc_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sc_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_sc_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sc_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_sc_d <= if4_instr_fifo_buf_1_lsu_isa_sc_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoswap_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoswap_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoswap_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoswap_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoswap_d <= if4_instr_fifo_buf_1_lsu_isa_amoswap_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoadd_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoadd_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoadd_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoadd_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoadd_d <= if4_instr_fifo_buf_1_lsu_isa_amoadd_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoxor_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoxor_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoxor_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoxor_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoxor_d <= if4_instr_fifo_buf_1_lsu_isa_amoxor_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoand_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoand_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoand_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoand_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoand_d <= if4_instr_fifo_buf_1_lsu_isa_amoand_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amoor_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoor_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amoor_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoor_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amoor_d <= if4_instr_fifo_buf_1_lsu_isa_amoor_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amomin_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomin_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amomin_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomin_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amomin_d <= if4_instr_fifo_buf_1_lsu_isa_amomin_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amomax_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomax_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amomax_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomax_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amomax_d <= if4_instr_fifo_buf_1_lsu_isa_amomax_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amominu_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amominu_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amominu_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amominu_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amominu_d <= if4_instr_fifo_buf_1_lsu_isa_amominu_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_amomaxu_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomaxu_d;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_amomaxu_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomaxu_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_amomaxu_d <= if4_instr_fifo_buf_1_lsu_isa_amomaxu_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_flw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_flw;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_flw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_flw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_flw <= if4_instr_fifo_buf_1_lsu_isa_flw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_fsw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fsw;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_fsw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fsw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_fsw <= if4_instr_fifo_buf_1_lsu_isa_fsw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_fld <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fld;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_fld <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fld;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_fld <= if4_instr_fifo_buf_1_lsu_isa_fld; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_lsu_isa_fsd <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fsd;
          end else begin
            if4_instr_fifo_buf_0_lsu_isa_fsd <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fsd;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_lsu_isa_fsd <= if4_instr_fifo_buf_1_lsu_isa_fsd; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_csr_isa_rw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rw;
          end else begin
            if4_instr_fifo_buf_0_csr_isa_rw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_csr_isa_rw <= if4_instr_fifo_buf_1_csr_isa_rw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_csr_isa_rs <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rs;
          end else begin
            if4_instr_fifo_buf_0_csr_isa_rs <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rs;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_csr_isa_rs <= if4_instr_fifo_buf_1_csr_isa_rs; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_csr_isa_rc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rc;
          end else begin
            if4_instr_fifo_buf_0_csr_isa_rc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rc;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_csr_isa_rc <= if4_instr_fifo_buf_1_csr_isa_rc; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_csr_isa_rwi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rwi;
          end else begin
            if4_instr_fifo_buf_0_csr_isa_rwi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rwi;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_csr_isa_rwi <= if4_instr_fifo_buf_1_csr_isa_rwi; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_csr_isa_rsi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rsi;
          end else begin
            if4_instr_fifo_buf_0_csr_isa_rsi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rsi;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_csr_isa_rsi <= if4_instr_fifo_buf_1_csr_isa_rsi; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_csr_isa_rci <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rci;
          end else begin
            if4_instr_fifo_buf_0_csr_isa_rci <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rci;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_csr_isa_rci <= if4_instr_fifo_buf_1_csr_isa_rci; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_mul <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mul;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_mul <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mul;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_mul <= if4_instr_fifo_buf_1_mul_isa_mul; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_mulh <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulh;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_mulh <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulh;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_mulh <= if4_instr_fifo_buf_1_mul_isa_mulh; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_mulhsu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulhsu;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_mulhsu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulhsu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_mulhsu <= if4_instr_fifo_buf_1_mul_isa_mulhsu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_mulhu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulhu;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_mulhu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulhu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_mulhu <= if4_instr_fifo_buf_1_mul_isa_mulhu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_div <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_div;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_div <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_div;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_div <= if4_instr_fifo_buf_1_mul_isa_div; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_divu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divu;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_divu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_divu <= if4_instr_fifo_buf_1_mul_isa_divu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_rem <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_rem;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_rem <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_rem;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_rem <= if4_instr_fifo_buf_1_mul_isa_rem; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_remu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remu;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_remu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_remu <= if4_instr_fifo_buf_1_mul_isa_remu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_mulw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulw;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_mulw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_mulw <= if4_instr_fifo_buf_1_mul_isa_mulw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_divw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divw;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_divw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_divw <= if4_instr_fifo_buf_1_mul_isa_divw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_divuw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divuw;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_divuw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divuw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_divuw <= if4_instr_fifo_buf_1_mul_isa_divuw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_remw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remw;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_remw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_remw <= if4_instr_fifo_buf_1_mul_isa_remw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_mul_isa_remuw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remuw;
          end else begin
            if4_instr_fifo_buf_0_mul_isa_remuw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remuw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_mul_isa_remuw <= if4_instr_fifo_buf_1_mul_isa_remuw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_ecall <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_ecall;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_ecall <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_ecall;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_ecall <= if4_instr_fifo_buf_1_privil_isa_ecall; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_ebreak <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_ebreak;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_ebreak <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_ebreak;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_ebreak <= if4_instr_fifo_buf_1_privil_isa_ebreak; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_mret <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_mret;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_mret <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_mret;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_mret <= if4_instr_fifo_buf_1_privil_isa_mret; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_uret <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_uret;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_uret <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_uret;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_uret <= if4_instr_fifo_buf_1_privil_isa_uret; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_sret <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_sret;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_sret <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_sret;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_sret <= if4_instr_fifo_buf_1_privil_isa_sret; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_dret <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_dret;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_dret <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_dret;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_dret <= if4_instr_fifo_buf_1_privil_isa_dret; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hfence_vvma <=
              if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hfence_vvma;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hfence_vvma <=
              if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hfence_vvma;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hfence_vvma <= if4_instr_fifo_buf_1_privil_isa_hfence_vvma; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hfence_gvma <=
              if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hfence_gvma;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hfence_gvma <=
              if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hfence_gvma;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hfence_gvma <= if4_instr_fifo_buf_1_privil_isa_hfence_gvma; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlv_b <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_b;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlv_b <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_b;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlv_b <= if4_instr_fifo_buf_1_privil_isa_hlv_b; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlv_bu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_bu;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlv_bu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_bu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlv_bu <= if4_instr_fifo_buf_1_privil_isa_hlv_bu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlv_h <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_h;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlv_h <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_h;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlv_h <= if4_instr_fifo_buf_1_privil_isa_hlv_h; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlv_hu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_hu;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlv_hu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_hu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlv_hu <= if4_instr_fifo_buf_1_privil_isa_hlv_hu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlvx_hu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlvx_hu;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlvx_hu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlvx_hu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlvx_hu <= if4_instr_fifo_buf_1_privil_isa_hlvx_hu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlv_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_w;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlv_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlv_w <= if4_instr_fifo_buf_1_privil_isa_hlv_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlvx_wu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlvx_wu;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlvx_wu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlvx_wu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlvx_wu <= if4_instr_fifo_buf_1_privil_isa_hlvx_wu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hsv_b <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_b;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hsv_b <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_b;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hsv_b <= if4_instr_fifo_buf_1_privil_isa_hsv_b; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hsv_h <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_h;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hsv_h <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_h;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hsv_h <= if4_instr_fifo_buf_1_privil_isa_hsv_h; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hsv_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_w;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hsv_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hsv_w <= if4_instr_fifo_buf_1_privil_isa_hsv_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlv_wu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_wu;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlv_wu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_wu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlv_wu <= if4_instr_fifo_buf_1_privil_isa_hlv_wu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hlv_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_d;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hlv_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hlv_d <= if4_instr_fifo_buf_1_privil_isa_hlv_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_hsv_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_d;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_hsv_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_hsv_d <= if4_instr_fifo_buf_1_privil_isa_hsv_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_is_access_fault <=
              if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_is_access_fault;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_is_access_fault <=
              if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_is_access_fault;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_is_access_fault <= if4_instr_fifo_buf_1_privil_isa_is_access_fault; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_privil_isa_is_paging_fault <=
              if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_is_paging_fault;
          end else begin
            if4_instr_fifo_buf_0_privil_isa_is_paging_fault <=
              if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_is_paging_fault;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_privil_isa_is_paging_fault <= if4_instr_fifo_buf_1_privil_isa_is_paging_fault; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmadd_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmadd_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmadd_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmadd_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmadd_s <= if4_instr_fifo_buf_1_fpu_isa_fmadd_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmsub_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmsub_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmsub_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmsub_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmsub_s <= if4_instr_fifo_buf_1_fpu_isa_fmsub_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fnmsub_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmsub_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fnmsub_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmsub_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fnmsub_s <= if4_instr_fifo_buf_1_fpu_isa_fnmsub_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fnmadd_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmadd_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fnmadd_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmadd_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fnmadd_s <= if4_instr_fifo_buf_1_fpu_isa_fnmadd_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fadd_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fadd_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fadd_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fadd_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fadd_s <= if4_instr_fifo_buf_1_fpu_isa_fadd_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsub_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsub_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsub_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsub_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsub_s <= if4_instr_fifo_buf_1_fpu_isa_fsub_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmul_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmul_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmul_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmul_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmul_s <= if4_instr_fifo_buf_1_fpu_isa_fmul_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fdiv_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fdiv_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fdiv_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fdiv_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fdiv_s <= if4_instr_fifo_buf_1_fpu_isa_fdiv_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsqrt_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsqrt_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsqrt_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsqrt_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsqrt_s <= if4_instr_fifo_buf_1_fpu_isa_fsqrt_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsgnj_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnj_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsgnj_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnj_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsgnj_s <= if4_instr_fifo_buf_1_fpu_isa_fsgnj_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsgnjn_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjn_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsgnjn_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjn_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsgnjn_s <= if4_instr_fifo_buf_1_fpu_isa_fsgnjn_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsgnjx_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjx_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsgnjx_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjx_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsgnjx_s <= if4_instr_fifo_buf_1_fpu_isa_fsgnjx_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmin_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmin_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmin_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmin_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmin_s <= if4_instr_fifo_buf_1_fpu_isa_fmin_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmax_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmax_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmax_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmax_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmax_s <= if4_instr_fifo_buf_1_fpu_isa_fmax_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_w_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_w_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_w_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_w_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_w_s <= if4_instr_fifo_buf_1_fpu_isa_fcvt_w_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_wu_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_wu_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_s <= if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmv_x_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_x_w;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmv_x_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_x_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmv_x_w <= if4_instr_fifo_buf_1_fpu_isa_fmv_x_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_feq_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_feq_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_feq_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_feq_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_feq_s <= if4_instr_fifo_buf_1_fpu_isa_feq_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_flt_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_flt_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_flt_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_flt_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_flt_s <= if4_instr_fifo_buf_1_fpu_isa_flt_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fle_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fle_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fle_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fle_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fle_s <= if4_instr_fifo_buf_1_fpu_isa_fle_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fclass_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fclass_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fclass_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fclass_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fclass_s <= if4_instr_fifo_buf_1_fpu_isa_fclass_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_w;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_s_w <= if4_instr_fifo_buf_1_fpu_isa_fcvt_s_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_wu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_wu;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_wu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_wu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_s_wu <= if4_instr_fifo_buf_1_fpu_isa_fcvt_s_wu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmv_w_x <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_w_x;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmv_w_x <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_w_x;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmv_w_x <= if4_instr_fifo_buf_1_fpu_isa_fmv_w_x; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_l_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_l_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_l_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_l_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_l_s <= if4_instr_fifo_buf_1_fpu_isa_fcvt_l_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_lu_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_lu_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_s <= if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_l <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_l;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_l <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_l;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_s_l <= if4_instr_fifo_buf_1_fpu_isa_fcvt_s_l; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_lu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_lu;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_lu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_lu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_s_lu <= if4_instr_fifo_buf_1_fpu_isa_fcvt_s_lu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmadd_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmadd_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmadd_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmadd_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmadd_d <= if4_instr_fifo_buf_1_fpu_isa_fmadd_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmsub_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmsub_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmsub_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmsub_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmsub_d <= if4_instr_fifo_buf_1_fpu_isa_fmsub_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fnmsub_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmsub_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fnmsub_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmsub_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fnmsub_d <= if4_instr_fifo_buf_1_fpu_isa_fnmsub_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fnmadd_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmadd_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fnmadd_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmadd_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fnmadd_d <= if4_instr_fifo_buf_1_fpu_isa_fnmadd_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fadd_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fadd_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fadd_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fadd_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fadd_d <= if4_instr_fifo_buf_1_fpu_isa_fadd_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsub_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsub_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsub_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsub_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsub_d <= if4_instr_fifo_buf_1_fpu_isa_fsub_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmul_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmul_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmul_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmul_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmul_d <= if4_instr_fifo_buf_1_fpu_isa_fmul_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fdiv_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fdiv_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fdiv_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fdiv_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fdiv_d <= if4_instr_fifo_buf_1_fpu_isa_fdiv_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsqrt_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsqrt_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsqrt_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsqrt_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsqrt_d <= if4_instr_fifo_buf_1_fpu_isa_fsqrt_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsgnj_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnj_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsgnj_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnj_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsgnj_d <= if4_instr_fifo_buf_1_fpu_isa_fsgnj_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsgnjn_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjn_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsgnjn_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjn_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsgnjn_d <= if4_instr_fifo_buf_1_fpu_isa_fsgnjn_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fsgnjx_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjx_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fsgnjx_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjx_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fsgnjx_d <= if4_instr_fifo_buf_1_fpu_isa_fsgnjx_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmin_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmin_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmin_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmin_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmin_d <= if4_instr_fifo_buf_1_fpu_isa_fmin_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmax_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmax_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmax_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmax_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmax_d <= if4_instr_fifo_buf_1_fpu_isa_fmax_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_s_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_s_d <= if4_instr_fifo_buf_1_fpu_isa_fcvt_s_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_s;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_s;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_d_s <= if4_instr_fifo_buf_1_fpu_isa_fcvt_d_s; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_feq_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_feq_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_feq_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_feq_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_feq_d <= if4_instr_fifo_buf_1_fpu_isa_feq_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_flt_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_flt_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_flt_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_flt_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_flt_d <= if4_instr_fifo_buf_1_fpu_isa_flt_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fle_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fle_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fle_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fle_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fle_d <= if4_instr_fifo_buf_1_fpu_isa_fle_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fclass_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fclass_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fclass_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fclass_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fclass_d <= if4_instr_fifo_buf_1_fpu_isa_fclass_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_w_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_w_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_w_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_w_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_w_d <= if4_instr_fifo_buf_1_fpu_isa_fcvt_w_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_wu_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_wu_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_d <= if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_w;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_w;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_d_w <= if4_instr_fifo_buf_1_fpu_isa_fcvt_d_w; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_wu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_wu;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_wu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_wu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_d_wu <= if4_instr_fifo_buf_1_fpu_isa_fcvt_d_wu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_l_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_l_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_l_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_l_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_l_d <= if4_instr_fifo_buf_1_fpu_isa_fcvt_l_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_lu_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_lu_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_d <= if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmv_x_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_x_d;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmv_x_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_x_d;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmv_x_d <= if4_instr_fifo_buf_1_fpu_isa_fmv_x_d; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_l <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_l;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_l <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_l;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_d_l <= if4_instr_fifo_buf_1_fpu_isa_fcvt_d_l; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_lu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_lu;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcvt_d_lu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_lu;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcvt_d_lu <= if4_instr_fifo_buf_1_fpu_isa_fcvt_d_lu; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fmv_d_x <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_d_x;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fmv_d_x <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_d_x;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fmv_d_x <= if4_instr_fifo_buf_1_fpu_isa_fmv_d_x; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rw;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rw;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcsr_rw <= if4_instr_fifo_buf_1_fpu_isa_fcsr_rw; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rs <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rs;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rs <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rs;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcsr_rs <= if4_instr_fifo_buf_1_fpu_isa_fcsr_rs; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rc;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rc;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcsr_rc <= if4_instr_fifo_buf_1_fpu_isa_fcsr_rc; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rwi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rwi;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rwi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rwi;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcsr_rwi <= if4_instr_fifo_buf_1_fpu_isa_fcsr_rwi; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rsi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rsi;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rsi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rsi;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcsr_rsi <= if4_instr_fifo_buf_1_fpu_isa_fcsr_rsi; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rci <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rci;
          end else begin
            if4_instr_fifo_buf_0_fpu_isa_fcsr_rci <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rci;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_fpu_isa_fcsr_rci <= if4_instr_fifo_buf_1_fpu_isa_fcsr_rci; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_param_is_rvc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_is_rvc;
          end else begin
            if4_instr_fifo_buf_0_param_is_rvc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_is_rvc;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_param_is_rvc <= if4_instr_fifo_buf_1_param_is_rvc; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_param_pc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_pc;
          end else begin
            if4_instr_fifo_buf_0_param_pc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_pc;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_param_pc <= if4_instr_fifo_buf_1_param_pc; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_param_imm <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_imm;
          end else begin
            if4_instr_fifo_buf_0_param_imm <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_imm;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_param_imm <= if4_instr_fifo_buf_1_param_imm; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_param_raw_rs1 <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rs1;
          end else begin
            if4_instr_fifo_buf_0_param_raw_rs1 <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rs1;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_param_raw_rs1 <= if4_instr_fifo_buf_1_param_raw_rs1; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_param_raw_rs2 <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rs2;
          end else begin
            if4_instr_fifo_buf_0_param_raw_rs2 <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rs2;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_param_raw_rs2 <= if4_instr_fifo_buf_1_param_raw_rs2; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_0_param_raw_rd0 <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rd0;
          end else begin
            if4_instr_fifo_buf_0_param_raw_rd0 <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rd0;
          end
        end else if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_0_param_raw_rd0 <= if4_instr_fifo_buf_1_param_raw_rd0; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_lui <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_lui;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_lui <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_lui;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_lui <= if4_instr_fifo_buf_0_alu_isa_lui;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_auipc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_auipc;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_auipc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_auipc;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_auipc <= if4_instr_fifo_buf_0_alu_isa_auipc;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_addi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addi;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_addi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addi;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_addi <= if4_instr_fifo_buf_0_alu_isa_addi;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_addiw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addiw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_addiw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addiw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_addiw <= if4_instr_fifo_buf_0_alu_isa_addiw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_slti <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slti;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_slti <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slti;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_slti <= if4_instr_fifo_buf_0_alu_isa_slti;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_sltiu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sltiu;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_sltiu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sltiu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_sltiu <= if4_instr_fifo_buf_0_alu_isa_sltiu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_xori <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_xori;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_xori <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_xori;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_xori <= if4_instr_fifo_buf_0_alu_isa_xori;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_ori <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_ori;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_ori <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_ori;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_ori <= if4_instr_fifo_buf_0_alu_isa_ori;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_andi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_andi;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_andi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_andi;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_andi <= if4_instr_fifo_buf_0_alu_isa_andi;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_slli <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slli;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_slli <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slli;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_slli <= if4_instr_fifo_buf_0_alu_isa_slli;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_slliw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slliw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_slliw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slliw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_slliw <= if4_instr_fifo_buf_0_alu_isa_slliw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_srli <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srli;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_srli <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srli;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_srli <= if4_instr_fifo_buf_0_alu_isa_srli;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_srliw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srliw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_srliw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srliw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_srliw <= if4_instr_fifo_buf_0_alu_isa_srliw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_srai <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srai;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_srai <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srai;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_srai <= if4_instr_fifo_buf_0_alu_isa_srai;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_sraiw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sraiw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_sraiw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sraiw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_sraiw <= if4_instr_fifo_buf_0_alu_isa_sraiw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_add <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_add;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_add <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_add;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_add <= if4_instr_fifo_buf_0_alu_isa_add;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_addw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_addw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_addw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_addw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_addw <= if4_instr_fifo_buf_0_alu_isa_addw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_sub <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sub;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_sub <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sub;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_sub <= if4_instr_fifo_buf_0_alu_isa_sub;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_subw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_subw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_subw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_subw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_subw <= if4_instr_fifo_buf_0_alu_isa_subw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_sll <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sll;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_sll <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sll;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_sll <= if4_instr_fifo_buf_0_alu_isa_sll;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_sllw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sllw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_sllw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sllw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_sllw <= if4_instr_fifo_buf_0_alu_isa_sllw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_slt <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_slt;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_slt <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_slt;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_slt <= if4_instr_fifo_buf_0_alu_isa_slt;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_sltu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sltu;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_sltu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sltu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_sltu <= if4_instr_fifo_buf_0_alu_isa_sltu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_xor <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_xor;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_xor <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_xor;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_xor <= if4_instr_fifo_buf_0_alu_isa_xor;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_srl <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srl;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_srl <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srl;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_srl <= if4_instr_fifo_buf_0_alu_isa_srl;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_srlw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_srlw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_srlw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_srlw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_srlw <= if4_instr_fifo_buf_0_alu_isa_srlw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_sra <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sra;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_sra <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sra;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_sra <= if4_instr_fifo_buf_0_alu_isa_sra;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_sraw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_sraw;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_sraw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_sraw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_sraw <= if4_instr_fifo_buf_0_alu_isa_sraw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_or <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_or;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_or <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_or;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_or <= if4_instr_fifo_buf_0_alu_isa_or;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_and <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_and;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_and <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_and;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_and <= if4_instr_fifo_buf_0_alu_isa_and;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_alu_isa_wfi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_alu_isa_wfi;
          end else begin
            if4_instr_fifo_buf_1_alu_isa_wfi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_alu_isa_wfi;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_alu_isa_wfi <= if4_instr_fifo_buf_0_alu_isa_wfi;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_bru_isa_jal <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_jal;
          end else begin
            if4_instr_fifo_buf_1_bru_isa_jal <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_jal;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_bru_isa_jal <= if4_instr_fifo_buf_0_bru_isa_jal;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_bru_isa_jalr <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_jalr;
          end else begin
            if4_instr_fifo_buf_1_bru_isa_jalr <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_jalr;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_bru_isa_jalr <= if4_instr_fifo_buf_0_bru_isa_jalr;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_bru_isa_beq <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_beq;
          end else begin
            if4_instr_fifo_buf_1_bru_isa_beq <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_beq;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_bru_isa_beq <= if4_instr_fifo_buf_0_bru_isa_beq;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_bru_isa_bne <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bne;
          end else begin
            if4_instr_fifo_buf_1_bru_isa_bne <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bne;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_bru_isa_bne <= if4_instr_fifo_buf_0_bru_isa_bne;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_bru_isa_blt <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_blt;
          end else begin
            if4_instr_fifo_buf_1_bru_isa_blt <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_blt;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_bru_isa_blt <= if4_instr_fifo_buf_0_bru_isa_blt;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_bru_isa_bge <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bge;
          end else begin
            if4_instr_fifo_buf_1_bru_isa_bge <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bge;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_bru_isa_bge <= if4_instr_fifo_buf_0_bru_isa_bge;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_bru_isa_bltu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bltu;
          end else begin
            if4_instr_fifo_buf_1_bru_isa_bltu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bltu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_bru_isa_bltu <= if4_instr_fifo_buf_0_bru_isa_bltu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_bru_isa_bgeu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_bru_isa_bgeu;
          end else begin
            if4_instr_fifo_buf_1_bru_isa_bgeu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_bru_isa_bgeu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_bru_isa_bgeu <= if4_instr_fifo_buf_0_bru_isa_bgeu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_lb <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lb;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_lb <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lb;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_lb <= if4_instr_fifo_buf_0_lsu_isa_lb;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_lh <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lh;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_lh <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lh;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_lh <= if4_instr_fifo_buf_0_lsu_isa_lh;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_lw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lw;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_lw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_lw <= if4_instr_fifo_buf_0_lsu_isa_lw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_ld <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_ld;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_ld <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_ld;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_ld <= if4_instr_fifo_buf_0_lsu_isa_ld;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_lbu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lbu;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_lbu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lbu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_lbu <= if4_instr_fifo_buf_0_lsu_isa_lbu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_lhu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lhu;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_lhu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lhu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_lhu <= if4_instr_fifo_buf_0_lsu_isa_lhu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_lwu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lwu;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_lwu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lwu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_lwu <= if4_instr_fifo_buf_0_lsu_isa_lwu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_sb <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sb;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_sb <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sb;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_sb <= if4_instr_fifo_buf_0_lsu_isa_sb;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_sh <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sh;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_sh <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sh;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_sh <= if4_instr_fifo_buf_0_lsu_isa_sh;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_sw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sw;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_sw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_sw <= if4_instr_fifo_buf_0_lsu_isa_sw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_sd <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sd;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_sd <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sd;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_sd <= if4_instr_fifo_buf_0_lsu_isa_sd;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_fence <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fence;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_fence <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fence;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_fence <= if4_instr_fifo_buf_0_lsu_isa_fence;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_fence_i <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fence_i;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_fence_i <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fence_i;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_fence_i <= if4_instr_fifo_buf_0_lsu_isa_fence_i;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_sfence_vma <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sfence_vma;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_sfence_vma <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sfence_vma;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_sfence_vma <= if4_instr_fifo_buf_0_lsu_isa_sfence_vma;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_lr_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lr_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_lr_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lr_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_lr_w <= if4_instr_fifo_buf_0_lsu_isa_lr_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_sc_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sc_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_sc_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sc_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_sc_w <= if4_instr_fifo_buf_0_lsu_isa_sc_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoswap_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoswap_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoswap_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoswap_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoswap_w <= if4_instr_fifo_buf_0_lsu_isa_amoswap_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoadd_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoadd_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoadd_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoadd_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoadd_w <= if4_instr_fifo_buf_0_lsu_isa_amoadd_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoxor_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoxor_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoxor_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoxor_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoxor_w <= if4_instr_fifo_buf_0_lsu_isa_amoxor_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoand_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoand_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoand_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoand_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoand_w <= if4_instr_fifo_buf_0_lsu_isa_amoand_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoor_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoor_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoor_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoor_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoor_w <= if4_instr_fifo_buf_0_lsu_isa_amoor_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amomin_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomin_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amomin_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomin_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amomin_w <= if4_instr_fifo_buf_0_lsu_isa_amomin_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amomax_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomax_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amomax_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomax_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amomax_w <= if4_instr_fifo_buf_0_lsu_isa_amomax_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amominu_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amominu_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amominu_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amominu_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amominu_w <= if4_instr_fifo_buf_0_lsu_isa_amominu_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amomaxu_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomaxu_w;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amomaxu_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomaxu_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amomaxu_w <= if4_instr_fifo_buf_0_lsu_isa_amomaxu_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_lr_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_lr_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_lr_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_lr_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_lr_d <= if4_instr_fifo_buf_0_lsu_isa_lr_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_sc_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_sc_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_sc_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_sc_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_sc_d <= if4_instr_fifo_buf_0_lsu_isa_sc_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoswap_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoswap_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoswap_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoswap_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoswap_d <= if4_instr_fifo_buf_0_lsu_isa_amoswap_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoadd_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoadd_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoadd_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoadd_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoadd_d <= if4_instr_fifo_buf_0_lsu_isa_amoadd_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoxor_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoxor_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoxor_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoxor_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoxor_d <= if4_instr_fifo_buf_0_lsu_isa_amoxor_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoand_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoand_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoand_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoand_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoand_d <= if4_instr_fifo_buf_0_lsu_isa_amoand_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amoor_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amoor_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amoor_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amoor_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amoor_d <= if4_instr_fifo_buf_0_lsu_isa_amoor_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amomin_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomin_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amomin_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomin_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amomin_d <= if4_instr_fifo_buf_0_lsu_isa_amomin_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amomax_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomax_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amomax_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomax_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amomax_d <= if4_instr_fifo_buf_0_lsu_isa_amomax_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amominu_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amominu_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amominu_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amominu_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amominu_d <= if4_instr_fifo_buf_0_lsu_isa_amominu_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_amomaxu_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_amomaxu_d;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_amomaxu_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_amomaxu_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_amomaxu_d <= if4_instr_fifo_buf_0_lsu_isa_amomaxu_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_flw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_flw;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_flw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_flw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_flw <= if4_instr_fifo_buf_0_lsu_isa_flw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_fsw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fsw;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_fsw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fsw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_fsw <= if4_instr_fifo_buf_0_lsu_isa_fsw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_fld <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fld;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_fld <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fld;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_fld <= if4_instr_fifo_buf_0_lsu_isa_fld;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_lsu_isa_fsd <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_lsu_isa_fsd;
          end else begin
            if4_instr_fifo_buf_1_lsu_isa_fsd <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_lsu_isa_fsd;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_lsu_isa_fsd <= if4_instr_fifo_buf_0_lsu_isa_fsd;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_csr_isa_rw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rw;
          end else begin
            if4_instr_fifo_buf_1_csr_isa_rw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_csr_isa_rw <= if4_instr_fifo_buf_0_csr_isa_rw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_csr_isa_rs <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rs;
          end else begin
            if4_instr_fifo_buf_1_csr_isa_rs <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rs;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_csr_isa_rs <= if4_instr_fifo_buf_0_csr_isa_rs;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_csr_isa_rc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rc;
          end else begin
            if4_instr_fifo_buf_1_csr_isa_rc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rc;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_csr_isa_rc <= if4_instr_fifo_buf_0_csr_isa_rc;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_csr_isa_rwi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rwi;
          end else begin
            if4_instr_fifo_buf_1_csr_isa_rwi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rwi;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_csr_isa_rwi <= if4_instr_fifo_buf_0_csr_isa_rwi;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_csr_isa_rsi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rsi;
          end else begin
            if4_instr_fifo_buf_1_csr_isa_rsi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rsi;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_csr_isa_rsi <= if4_instr_fifo_buf_0_csr_isa_rsi;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_csr_isa_rci <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_csr_isa_rci;
          end else begin
            if4_instr_fifo_buf_1_csr_isa_rci <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_csr_isa_rci;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_csr_isa_rci <= if4_instr_fifo_buf_0_csr_isa_rci;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_mul <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mul;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_mul <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mul;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_mul <= if4_instr_fifo_buf_0_mul_isa_mul;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_mulh <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulh;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_mulh <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulh;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_mulh <= if4_instr_fifo_buf_0_mul_isa_mulh;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_mulhsu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulhsu;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_mulhsu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulhsu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_mulhsu <= if4_instr_fifo_buf_0_mul_isa_mulhsu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_mulhu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulhu;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_mulhu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulhu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_mulhu <= if4_instr_fifo_buf_0_mul_isa_mulhu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_div <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_div;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_div <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_div;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_div <= if4_instr_fifo_buf_0_mul_isa_div;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_divu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divu;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_divu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_divu <= if4_instr_fifo_buf_0_mul_isa_divu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_rem <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_rem;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_rem <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_rem;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_rem <= if4_instr_fifo_buf_0_mul_isa_rem;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_remu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remu;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_remu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_remu <= if4_instr_fifo_buf_0_mul_isa_remu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_mulw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_mulw;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_mulw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_mulw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_mulw <= if4_instr_fifo_buf_0_mul_isa_mulw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_divw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divw;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_divw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_divw <= if4_instr_fifo_buf_0_mul_isa_divw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_divuw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_divuw;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_divuw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_divuw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_divuw <= if4_instr_fifo_buf_0_mul_isa_divuw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_remw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remw;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_remw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_remw <= if4_instr_fifo_buf_0_mul_isa_remw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_mul_isa_remuw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_mul_isa_remuw;
          end else begin
            if4_instr_fifo_buf_1_mul_isa_remuw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_mul_isa_remuw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_mul_isa_remuw <= if4_instr_fifo_buf_0_mul_isa_remuw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_ecall <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_ecall;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_ecall <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_ecall;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_ecall <= if4_instr_fifo_buf_0_privil_isa_ecall;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_ebreak <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_ebreak;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_ebreak <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_ebreak;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_ebreak <= if4_instr_fifo_buf_0_privil_isa_ebreak;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_mret <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_mret;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_mret <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_mret;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_mret <= if4_instr_fifo_buf_0_privil_isa_mret;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_uret <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_uret;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_uret <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_uret;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_uret <= if4_instr_fifo_buf_0_privil_isa_uret;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_sret <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_sret;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_sret <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_sret;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_sret <= if4_instr_fifo_buf_0_privil_isa_sret;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_dret <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_dret;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_dret <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_dret;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_dret <= if4_instr_fifo_buf_0_privil_isa_dret;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hfence_vvma <=
              if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hfence_vvma;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hfence_vvma <=
              if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hfence_vvma;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hfence_vvma <= if4_instr_fifo_buf_0_privil_isa_hfence_vvma;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hfence_gvma <=
              if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hfence_gvma;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hfence_gvma <=
              if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hfence_gvma;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hfence_gvma <= if4_instr_fifo_buf_0_privil_isa_hfence_gvma;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlv_b <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_b;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlv_b <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_b;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlv_b <= if4_instr_fifo_buf_0_privil_isa_hlv_b;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlv_bu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_bu;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlv_bu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_bu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlv_bu <= if4_instr_fifo_buf_0_privil_isa_hlv_bu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlv_h <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_h;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlv_h <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_h;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlv_h <= if4_instr_fifo_buf_0_privil_isa_hlv_h;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlv_hu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_hu;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlv_hu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_hu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlv_hu <= if4_instr_fifo_buf_0_privil_isa_hlv_hu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlvx_hu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlvx_hu;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlvx_hu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlvx_hu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlvx_hu <= if4_instr_fifo_buf_0_privil_isa_hlvx_hu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlv_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_w;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlv_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlv_w <= if4_instr_fifo_buf_0_privil_isa_hlv_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlvx_wu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlvx_wu;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlvx_wu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlvx_wu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlvx_wu <= if4_instr_fifo_buf_0_privil_isa_hlvx_wu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hsv_b <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_b;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hsv_b <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_b;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hsv_b <= if4_instr_fifo_buf_0_privil_isa_hsv_b;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hsv_h <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_h;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hsv_h <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_h;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hsv_h <= if4_instr_fifo_buf_0_privil_isa_hsv_h;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hsv_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_w;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hsv_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hsv_w <= if4_instr_fifo_buf_0_privil_isa_hsv_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlv_wu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_wu;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlv_wu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_wu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlv_wu <= if4_instr_fifo_buf_0_privil_isa_hlv_wu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hlv_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hlv_d;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hlv_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hlv_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hlv_d <= if4_instr_fifo_buf_0_privil_isa_hlv_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_hsv_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_hsv_d;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_hsv_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_hsv_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_hsv_d <= if4_instr_fifo_buf_0_privil_isa_hsv_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_is_access_fault <=
              if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_is_access_fault;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_is_access_fault <=
              if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_is_access_fault;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_is_access_fault <= if4_instr_fifo_buf_0_privil_isa_is_access_fault;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_privil_isa_is_paging_fault <=
              if4_instr_fifo_io_enq_0_bits_dec16_io_info_privil_isa_is_paging_fault;
          end else begin
            if4_instr_fifo_buf_1_privil_isa_is_paging_fault <=
              if4_instr_fifo_io_enq_0_bits_dec32_io_info_privil_isa_is_paging_fault;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_privil_isa_is_paging_fault <= if4_instr_fifo_buf_0_privil_isa_is_paging_fault;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmadd_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmadd_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmadd_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmadd_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmadd_s <= if4_instr_fifo_buf_0_fpu_isa_fmadd_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmsub_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmsub_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmsub_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmsub_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmsub_s <= if4_instr_fifo_buf_0_fpu_isa_fmsub_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fnmsub_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmsub_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fnmsub_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmsub_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fnmsub_s <= if4_instr_fifo_buf_0_fpu_isa_fnmsub_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fnmadd_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmadd_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fnmadd_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmadd_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fnmadd_s <= if4_instr_fifo_buf_0_fpu_isa_fnmadd_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fadd_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fadd_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fadd_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fadd_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fadd_s <= if4_instr_fifo_buf_0_fpu_isa_fadd_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsub_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsub_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsub_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsub_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsub_s <= if4_instr_fifo_buf_0_fpu_isa_fsub_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmul_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmul_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmul_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmul_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmul_s <= if4_instr_fifo_buf_0_fpu_isa_fmul_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fdiv_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fdiv_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fdiv_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fdiv_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fdiv_s <= if4_instr_fifo_buf_0_fpu_isa_fdiv_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsqrt_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsqrt_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsqrt_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsqrt_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsqrt_s <= if4_instr_fifo_buf_0_fpu_isa_fsqrt_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsgnj_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnj_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsgnj_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnj_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsgnj_s <= if4_instr_fifo_buf_0_fpu_isa_fsgnj_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsgnjn_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjn_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsgnjn_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjn_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsgnjn_s <= if4_instr_fifo_buf_0_fpu_isa_fsgnjn_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsgnjx_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjx_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsgnjx_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjx_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsgnjx_s <= if4_instr_fifo_buf_0_fpu_isa_fsgnjx_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmin_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmin_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmin_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmin_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmin_s <= if4_instr_fifo_buf_0_fpu_isa_fmin_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmax_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmax_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmax_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmax_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmax_s <= if4_instr_fifo_buf_0_fpu_isa_fmax_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_w_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_w_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_w_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_w_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_w_s <= if4_instr_fifo_buf_0_fpu_isa_fcvt_w_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_wu_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_wu_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_s <= if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmv_x_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_x_w;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmv_x_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_x_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmv_x_w <= if4_instr_fifo_buf_0_fpu_isa_fmv_x_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_feq_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_feq_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_feq_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_feq_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_feq_s <= if4_instr_fifo_buf_0_fpu_isa_feq_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_flt_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_flt_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_flt_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_flt_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_flt_s <= if4_instr_fifo_buf_0_fpu_isa_flt_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fle_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fle_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fle_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fle_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fle_s <= if4_instr_fifo_buf_0_fpu_isa_fle_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fclass_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fclass_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fclass_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fclass_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fclass_s <= if4_instr_fifo_buf_0_fpu_isa_fclass_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_w;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_s_w <= if4_instr_fifo_buf_0_fpu_isa_fcvt_s_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_wu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_wu;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_wu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_wu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_s_wu <= if4_instr_fifo_buf_0_fpu_isa_fcvt_s_wu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmv_w_x <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_w_x;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmv_w_x <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_w_x;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmv_w_x <= if4_instr_fifo_buf_0_fpu_isa_fmv_w_x;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_l_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_l_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_l_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_l_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_l_s <= if4_instr_fifo_buf_0_fpu_isa_fcvt_l_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_lu_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_lu_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_s <= if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_l <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_l;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_l <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_l;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_s_l <= if4_instr_fifo_buf_0_fpu_isa_fcvt_s_l;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_lu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_lu;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_lu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_lu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_s_lu <= if4_instr_fifo_buf_0_fpu_isa_fcvt_s_lu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmadd_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmadd_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmadd_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmadd_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmadd_d <= if4_instr_fifo_buf_0_fpu_isa_fmadd_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmsub_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmsub_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmsub_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmsub_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmsub_d <= if4_instr_fifo_buf_0_fpu_isa_fmsub_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fnmsub_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmsub_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fnmsub_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmsub_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fnmsub_d <= if4_instr_fifo_buf_0_fpu_isa_fnmsub_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fnmadd_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fnmadd_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fnmadd_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fnmadd_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fnmadd_d <= if4_instr_fifo_buf_0_fpu_isa_fnmadd_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fadd_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fadd_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fadd_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fadd_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fadd_d <= if4_instr_fifo_buf_0_fpu_isa_fadd_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsub_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsub_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsub_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsub_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsub_d <= if4_instr_fifo_buf_0_fpu_isa_fsub_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmul_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmul_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmul_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmul_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmul_d <= if4_instr_fifo_buf_0_fpu_isa_fmul_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fdiv_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fdiv_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fdiv_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fdiv_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fdiv_d <= if4_instr_fifo_buf_0_fpu_isa_fdiv_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsqrt_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsqrt_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsqrt_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsqrt_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsqrt_d <= if4_instr_fifo_buf_0_fpu_isa_fsqrt_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsgnj_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnj_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsgnj_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnj_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsgnj_d <= if4_instr_fifo_buf_0_fpu_isa_fsgnj_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsgnjn_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjn_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsgnjn_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjn_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsgnjn_d <= if4_instr_fifo_buf_0_fpu_isa_fsgnjn_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fsgnjx_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fsgnjx_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fsgnjx_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fsgnjx_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fsgnjx_d <= if4_instr_fifo_buf_0_fpu_isa_fsgnjx_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmin_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmin_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmin_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmin_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmin_d <= if4_instr_fifo_buf_0_fpu_isa_fmin_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmax_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmax_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmax_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmax_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmax_d <= if4_instr_fifo_buf_0_fpu_isa_fmax_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_s_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_s_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_s_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_s_d <= if4_instr_fifo_buf_0_fpu_isa_fcvt_s_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_s <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_s;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_s <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_s;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_d_s <= if4_instr_fifo_buf_0_fpu_isa_fcvt_d_s;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_feq_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_feq_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_feq_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_feq_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_feq_d <= if4_instr_fifo_buf_0_fpu_isa_feq_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_flt_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_flt_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_flt_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_flt_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_flt_d <= if4_instr_fifo_buf_0_fpu_isa_flt_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fle_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fle_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fle_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fle_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fle_d <= if4_instr_fifo_buf_0_fpu_isa_fle_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fclass_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fclass_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fclass_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fclass_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fclass_d <= if4_instr_fifo_buf_0_fpu_isa_fclass_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_w_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_w_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_w_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_w_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_w_d <= if4_instr_fifo_buf_0_fpu_isa_fcvt_w_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_wu_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_wu_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_d <= if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_w <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_w;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_w <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_w;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_d_w <= if4_instr_fifo_buf_0_fpu_isa_fcvt_d_w;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_wu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_wu;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_wu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_wu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_d_wu <= if4_instr_fifo_buf_0_fpu_isa_fcvt_d_wu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_l_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_l_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_l_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_l_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_l_d <= if4_instr_fifo_buf_0_fpu_isa_fcvt_l_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_lu_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_lu_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_d <= if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmv_x_d <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_x_d;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmv_x_d <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_x_d;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmv_x_d <= if4_instr_fifo_buf_0_fpu_isa_fmv_x_d;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_l <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_l;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_l <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_l;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_d_l <= if4_instr_fifo_buf_0_fpu_isa_fcvt_d_l;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_lu <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcvt_d_lu;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcvt_d_lu <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcvt_d_lu;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcvt_d_lu <= if4_instr_fifo_buf_0_fpu_isa_fcvt_d_lu;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fmv_d_x <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fmv_d_x;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fmv_d_x <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fmv_d_x;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fmv_d_x <= if4_instr_fifo_buf_0_fpu_isa_fmv_d_x;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rw <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rw;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rw <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rw;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcsr_rw <= if4_instr_fifo_buf_0_fpu_isa_fcsr_rw;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rs <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rs;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rs <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rs;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcsr_rs <= if4_instr_fifo_buf_0_fpu_isa_fcsr_rs;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rc;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rc;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcsr_rc <= if4_instr_fifo_buf_0_fpu_isa_fcsr_rc;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rwi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rwi;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rwi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rwi;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcsr_rwi <= if4_instr_fifo_buf_0_fpu_isa_fcsr_rwi;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rsi <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rsi;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rsi <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rsi;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcsr_rsi <= if4_instr_fifo_buf_0_fpu_isa_fcsr_rsi;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rci <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_fpu_isa_fcsr_rci;
          end else begin
            if4_instr_fifo_buf_1_fpu_isa_fcsr_rci <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_fpu_isa_fcsr_rci;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_fpu_isa_fcsr_rci <= if4_instr_fifo_buf_0_fpu_isa_fcsr_rci;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_param_is_rvc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_is_rvc;
          end else begin
            if4_instr_fifo_buf_1_param_is_rvc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_is_rvc;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_param_is_rvc <= if4_instr_fifo_buf_0_param_is_rvc;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_param_pc <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_pc;
          end else begin
            if4_instr_fifo_buf_1_param_pc <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_pc;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_param_pc <= if4_instr_fifo_buf_0_param_pc;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_param_imm <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_imm;
          end else begin
            if4_instr_fifo_buf_1_param_imm <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_imm;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_param_imm <= if4_instr_fifo_buf_0_param_imm;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_param_raw_rs1 <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rs1;
          end else begin
            if4_instr_fifo_buf_1_param_raw_rs1 <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rs1;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_param_raw_rs1 <= if4_instr_fifo_buf_0_param_raw_rs1;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_param_raw_rs2 <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rs2;
          end else begin
            if4_instr_fifo_buf_1_param_raw_rs2 <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rs2;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_param_raw_rs2 <= if4_instr_fifo_buf_0_param_raw_rs2;
        end
      end
    end
    if (!(if4_instr_fifo_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_instr_fifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_instr_fifo__T) begin // @[MultiPortFifo.scala 101:33]
          if (if4_io_if4_req_0_bits_isRVC) begin // @[IF4.scala 93:10]
            if4_instr_fifo_buf_1_param_raw_rd0 <= if4_instr_fifo_io_enq_0_bits_dec16_io_info_param_raw_rd0;
          end else begin
            if4_instr_fifo_buf_1_param_raw_rd0 <= if4_instr_fifo_io_enq_0_bits_dec32_io_info_param_raw_rd0;
          end
        end else if (!(if4_instr_fifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_instr_fifo_buf_1_param_raw_rd0 <= if4_instr_fifo_buf_0_param_raw_rd0;
        end
      end
    end
    if (if4_instr_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if4_instr_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if4_instr_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_instr_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if4_instr_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~if4_instr_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if4_instr_fifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if4_instr_fifo_buf_valid_0 <= if4_instr_fifo__GEN_6;
      end
    end else begin
      if4_instr_fifo_buf_valid_0 <= if4_instr_fifo__GEN_6;
    end
    if (if4_instr_fifo_reset) begin // @[MultiPortFifo.scala 58:30]
      if4_instr_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if4_instr_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_instr_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if4_instr_fifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (if4_instr_fifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if4_instr_fifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if4_instr_fifo_buf_valid_1 <= if4_instr_fifo__GEN_7;
      end
    end else begin
      if4_instr_fifo_buf_valid_1 <= if4_instr_fifo__GEN_7;
    end
    if (if4_instr_fifo_reset) begin // @[MultiPortFifo.scala 60:27]
      if4_instr_fifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (if4_instr_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_instr_fifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      if4_instr_fifo_rd_ptr <= if4_instr_fifo__rd_ptr_T_2; // @[MultiPortFifo.scala 106:16]
    end
    if (if4_instr_fifo_reset) begin // @[MultiPortFifo.scala 61:27]
      if4_instr_fifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (if4_instr_fifo_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_instr_fifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      if4_instr_fifo_wr_ptr <= if4_instr_fifo__wr_ptr_T_2; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4_instr_fifo__T_9 & if4_instr_fifo__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4_instr_fifo__T_7 & if4_instr_fifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4_instr_fifo__T_9 & if4_instr_fifo__T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4_instr_fifo__T_16 & if4_instr_fifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if4_bftq_clock) begin
    if (!(if4_bftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_bftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_0_pc <= if4_bftq_io_enq_0_bits_pc;
        end else if (if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_0_pc <= if4_bftq_buf_1_pc; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_bftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_bftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_0_bimResp_bim_p <= if4_bftq_io_enq_0_bits_bimResp_bim_p;
        end else if (if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_0_bimResp_bim_p <= if4_bftq_buf_1_bimResp_bim_p; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_bftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_bftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_0_bimResp_bim_h <= if4_bftq_io_enq_0_bits_bimResp_bim_h;
        end else if (if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_0_bimResp_bim_h <= if4_bftq_buf_1_bimResp_bim_h; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_bftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_bftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_0_isPredictTaken <= if4_bftq_io_enq_0_bits_isPredictTaken;
        end else if (if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_0_isPredictTaken <= if4_bftq_buf_1_isPredictTaken; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_bftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_bftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_1_pc <= if4_bftq_io_enq_0_bits_pc;
        end else if (!(if4_bftq__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_1_pc <= if4_bftq_buf_0_pc;
        end
      end
    end
    if (!(if4_bftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_bftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_1_bimResp_bim_p <= if4_bftq_io_enq_0_bits_bimResp_bim_p;
        end else if (!(if4_bftq__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_1_bimResp_bim_p <= if4_bftq_buf_0_bimResp_bim_p;
        end
      end
    end
    if (!(if4_bftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_bftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_1_bimResp_bim_h <= if4_bftq_io_enq_0_bits_bimResp_bim_h;
        end else if (!(if4_bftq__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_1_bimResp_bim_h <= if4_bftq_buf_0_bimResp_bim_h;
        end
      end
    end
    if (!(if4_bftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_bftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_bftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_1_isPredictTaken <= if4_bftq_io_enq_0_bits_isPredictTaken;
        end else if (!(if4_bftq__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_bftq_buf_1_isPredictTaken <= if4_bftq_buf_0_isPredictTaken;
        end
      end
    end
    if (if4_bftq_reset) begin // @[MultiPortFifo.scala 58:30]
      if4_bftq_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if4_bftq_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_bftq_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if4_bftq__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~if4_bftq__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if4_bftq_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if4_bftq_buf_valid_0 <= if4_bftq__GEN_6;
      end
    end else begin
      if4_bftq_buf_valid_0 <= if4_bftq__GEN_6;
    end
    if (if4_bftq_reset) begin // @[MultiPortFifo.scala 58:30]
      if4_bftq_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if4_bftq_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_bftq_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if4_bftq__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (if4_bftq__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if4_bftq_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if4_bftq_buf_valid_1 <= if4_bftq__GEN_7;
      end
    end else begin
      if4_bftq_buf_valid_1 <= if4_bftq__GEN_7;
    end
    if (if4_bftq_reset) begin // @[MultiPortFifo.scala 60:27]
      if4_bftq_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (if4_bftq_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_bftq_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      if4_bftq_rd_ptr <= if4_bftq__rd_ptr_T_2; // @[MultiPortFifo.scala 106:16]
    end
    if (if4_bftq_reset) begin // @[MultiPortFifo.scala 61:27]
      if4_bftq_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (if4_bftq_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_bftq_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      if4_bftq_wr_ptr <= if4_bftq__wr_ptr_T_2; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4_bftq__T_9 & if4_bftq__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4_bftq__T_7 & if4_bftq__T_9) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4_bftq__T_9 & if4_bftq__T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4_bftq__T_16 & if4_bftq__T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if4_jftq_clock) begin
    if (!(if4_jftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_jftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_0_pc <= if4_jftq_io_enq_0_bits_pc;
        end else if (if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_0_pc <= if4_jftq_buf_1_pc; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_jftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_jftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_0_btbResp_target <= if4_jftq_io_enq_0_bits_btbResp_target;
        end else if (if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_0_btbResp_target <= if4_jftq_buf_1_btbResp_target; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_jftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_jftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_0_rasResp_target <= if4_jftq_io_enq_0_bits_rasResp_target;
        end else if (if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_0_rasResp_target <= if4_jftq_buf_1_rasResp_target; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_jftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (~if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_jftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_0_isRas <= if4_jftq_io_enq_0_bits_isRas;
        end else if (if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_0_isRas <= if4_jftq_buf_1_isRas; // @[MultiPortFifo.scala 101:33]
        end
      end
    end
    if (!(if4_jftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_jftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_1_pc <= if4_jftq_io_enq_0_bits_pc;
        end else if (!(if4_jftq__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_1_pc <= if4_jftq_buf_0_pc;
        end
      end
    end
    if (!(if4_jftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_jftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_1_btbResp_target <= if4_jftq_io_enq_0_bits_btbResp_target;
        end else if (!(if4_jftq__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_1_btbResp_target <= if4_jftq_buf_0_btbResp_target;
        end
      end
    end
    if (!(if4_jftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_jftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_1_rasResp_target <= if4_jftq_io_enq_0_bits_rasResp_target;
        end else if (!(if4_jftq__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_1_rasResp_target <= if4_jftq_buf_0_rasResp_target;
        end
      end
    end
    if (!(if4_jftq_io_flush)) begin // @[MultiPortFifo.scala 87:23]
      if (if4_jftq__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
        if (if4_jftq__T) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_1_isRas <= if4_jftq_io_enq_0_bits_isRas;
        end else if (!(if4_jftq__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
          if4_jftq_buf_1_isRas <= if4_jftq_buf_0_isRas;
        end
      end
    end
    if (if4_jftq_reset) begin // @[MultiPortFifo.scala 58:30]
      if4_jftq_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if4_jftq_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_jftq_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if4_jftq__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~if4_jftq__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if4_jftq_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if4_jftq_buf_valid_0 <= if4_jftq__GEN_6;
      end
    end else begin
      if4_jftq_buf_valid_0 <= if4_jftq__GEN_6;
    end
    if (if4_jftq_reset) begin // @[MultiPortFifo.scala 58:30]
      if4_jftq_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (if4_jftq_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_jftq_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 88:54]
    end else if (if4_jftq__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (if4_jftq__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        if4_jftq_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        if4_jftq_buf_valid_1 <= if4_jftq__GEN_7;
      end
    end else begin
      if4_jftq_buf_valid_1 <= if4_jftq__GEN_7;
    end
    if (if4_jftq_reset) begin // @[MultiPortFifo.scala 60:27]
      if4_jftq_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else if (if4_jftq_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_jftq_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 89:16]
    end else begin
      if4_jftq_rd_ptr <= if4_jftq__rd_ptr_T_2; // @[MultiPortFifo.scala 106:16]
    end
    if (if4_jftq_reset) begin // @[MultiPortFifo.scala 61:27]
      if4_jftq_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else if (if4_jftq_io_flush) begin // @[MultiPortFifo.scala 87:23]
      if4_jftq_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 90:16]
    end else begin
      if4_jftq_wr_ptr <= if4_jftq__wr_ptr_T_2; // @[MultiPortFifo.scala 107:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4_jftq__T_9 & if4_jftq__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4_jftq__T_7 & if4_jftq__T_9) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4_jftq__T_9 & if4_jftq__T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4_jftq__T_16 & if4_jftq__T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if4_bRePort_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4_bRePort__T_4 & if4_bRePort__T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4_bRePort__T_2 & if4_bRePort__T_4) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if4_jRePort_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4_jRePort__T_4 & if4_jRePort__T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4_jRePort__T_2 & if4_jRePort__T_4) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge if4_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__tage_decode_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at TAGE.scala:262 assert( resp.isAltpred(i) === (resp.isProvider(i) ^ isTableSel(i)) )\n"
            ); // @[TAGE.scala 262:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__tage_decode_T_1 & if4__tage_decode_T_3) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__tage_decode_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at TAGE.scala:262 assert( resp.isAltpred(i) === (resp.isProvider(i) ^ isTableSel(i)) )\n"
            ); // @[TAGE.scala 262:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__tage_decode_T_6 & if4__tage_decode_T_3) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__tage_decode_T_14) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at TAGE.scala:262 assert( resp.isAltpred(i) === (resp.isProvider(i) ^ isTableSel(i)) )\n"
            ); // @[TAGE.scala 262:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__tage_decode_T_11 & if4__tage_decode_T_3) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__tage_decode_T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at TAGE.scala:262 assert( resp.isAltpred(i) === (resp.isProvider(i) ^ isTableSel(i)) )\n"
            ); // @[TAGE.scala 262:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__tage_decode_T_16 & if4__tage_decode_T_3) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__tage_decode_T_24) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at TAGE.scala:262 assert( resp.isAltpred(i) === (resp.isProvider(i) ^ isTableSel(i)) )\n"
            ); // @[TAGE.scala 262:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__tage_decode_T_21 & if4__tage_decode_T_3) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__tage_decode_T_29) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at TAGE.scala:262 assert( resp.isAltpred(i) === (resp.isProvider(i) ^ isTableSel(i)) )\n"
            ); // @[TAGE.scala 262:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__tage_decode_T_26 & if4__tage_decode_T_3) begin
          $fatal; // @[TAGE.scala 262:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__tage_decode_T_43) begin
          $fwrite(32'h80000002,"Assertion failed\n    at TAGE.scala:264 assert( PopCount( resp.isProvider ) <= 1.U )\n"
            ); // @[TAGE.scala 264:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__tage_decode_T_40 & if4__tage_decode_T_3) begin
          $fatal; // @[TAGE.scala 264:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__T & if4__tage_decode_T_3 & if4__T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF4.scala:173 when( ~isRedirect(i) ) { assert( redirectTarget(i) === 0.U ) }\n"); // @[IF4.scala 173:36]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__T_1 & (if4__T & if4__tage_decode_T_3)) begin
          $fatal; // @[IF4.scala 173:36]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__T_6 & if4__tage_decode_T_3 & if4__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF4.scala:174 when( io.if4_req(i).valid & ~io.if4_req(i).bits.isRedirect ) { assert( io.if4_req(i).bits.target === 0.U ) }\n"
            ); // @[IF4.scala 174:74]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__T_7 & (if4__T_6 & if4__tage_decode_T_3)) begin
          $fatal; // @[IF4.scala 174:74]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__T_16) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF4.scala:224 assert( ~(btbRedirect(i).ready  & ~btbRedirect(i).valid) )\n"); // @[IF4.scala 224:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__T_13 & if4__tage_decode_T_3) begin
          $fatal; // @[IF4.scala 224:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (if4__tage_decode_T_3 & if4__T_22) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IF4.scala:225 assert( ~(bimRedirect(i).ready  & ~bimRedirect(i).valid) )\n"); // @[IF4.scala 225:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~if4__T_19 & if4__tage_decode_T_3) begin
          $fatal; // @[IF4.scala 225:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge rnm_stage_rnRspReport_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (rnm_stage_rnRspReport__T_4 & rnm_stage_rnRspReport__T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at RePort! enq-fire should equal to deq-fire!\n    at RePort.scala:32 assert ( PopCount( io.enq.map(_.fire) ) === PopCount( io.deq.map(_.fire) ), \"Assert Failed at RePort! enq-fire should equal to deq-fire!\"  )\n"
            ); // @[RePort.scala 32:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rnm_stage_rnRspReport__T_2 & rnm_stage_rnRspReport__T_4) begin
          $fatal; // @[RePort.scala 32:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge rnm_stage_rnRspFifo_clock) begin
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_lui <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_lui;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_lui <= rnm_stage_rnRspFifo_buf_1_alu_isa_lui; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_auipc <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_auipc;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_auipc <= rnm_stage_rnRspFifo_buf_1_alu_isa_auipc; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_addi <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addi;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_addi <= rnm_stage_rnRspFifo_buf_1_alu_isa_addi; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_addiw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addiw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_addiw <= rnm_stage_rnRspFifo_buf_1_alu_isa_addiw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_slti <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slti;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_slti <= rnm_stage_rnRspFifo_buf_1_alu_isa_slti; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sltiu <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sltiu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sltiu <= rnm_stage_rnRspFifo_buf_1_alu_isa_sltiu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_xori <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_xori;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_xori <= rnm_stage_rnRspFifo_buf_1_alu_isa_xori; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_ori <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_ori;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_ori <= rnm_stage_rnRspFifo_buf_1_alu_isa_ori; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_andi <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_andi;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_andi <= rnm_stage_rnRspFifo_buf_1_alu_isa_andi; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_slli <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slli;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_slli <= rnm_stage_rnRspFifo_buf_1_alu_isa_slli; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_slliw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slliw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_slliw <= rnm_stage_rnRspFifo_buf_1_alu_isa_slliw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srli <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srli;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srli <= rnm_stage_rnRspFifo_buf_1_alu_isa_srli; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srliw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srliw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srliw <= rnm_stage_rnRspFifo_buf_1_alu_isa_srliw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srai <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srai;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srai <= rnm_stage_rnRspFifo_buf_1_alu_isa_srai; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sraiw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sraiw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sraiw <= rnm_stage_rnRspFifo_buf_1_alu_isa_sraiw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_add <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_add;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_add <= rnm_stage_rnRspFifo_buf_1_alu_isa_add; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_addw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_addw <= rnm_stage_rnRspFifo_buf_1_alu_isa_addw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sub <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sub;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sub <= rnm_stage_rnRspFifo_buf_1_alu_isa_sub; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_subw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_subw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_subw <= rnm_stage_rnRspFifo_buf_1_alu_isa_subw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sll <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sll;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sll <= rnm_stage_rnRspFifo_buf_1_alu_isa_sll; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sllw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sllw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sllw <= rnm_stage_rnRspFifo_buf_1_alu_isa_sllw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_slt <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slt;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_slt <= rnm_stage_rnRspFifo_buf_1_alu_isa_slt; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sltu <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sltu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sltu <= rnm_stage_rnRspFifo_buf_1_alu_isa_sltu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_xor <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_xor;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_xor <= rnm_stage_rnRspFifo_buf_1_alu_isa_xor; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srl <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srl;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srl <= rnm_stage_rnRspFifo_buf_1_alu_isa_srl; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srlw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srlw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_srlw <= rnm_stage_rnRspFifo_buf_1_alu_isa_srlw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sra <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sra;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sra <= rnm_stage_rnRspFifo_buf_1_alu_isa_sra; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sraw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sraw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_sraw <= rnm_stage_rnRspFifo_buf_1_alu_isa_sraw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_or <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_or;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_or <= rnm_stage_rnRspFifo_buf_1_alu_isa_or; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_and <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_and;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_and <= rnm_stage_rnRspFifo_buf_1_alu_isa_and; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_wfi <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_wfi;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_alu_isa_wfi <= rnm_stage_rnRspFifo_buf_1_alu_isa_wfi; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_jal <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_jal;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_jal <= rnm_stage_rnRspFifo_buf_1_bru_isa_jal; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_jalr <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_jalr;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_jalr <= rnm_stage_rnRspFifo_buf_1_bru_isa_jalr; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_beq <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_beq;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_beq <= rnm_stage_rnRspFifo_buf_1_bru_isa_beq; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_bne <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bne;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_bne <= rnm_stage_rnRspFifo_buf_1_bru_isa_bne; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_blt <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_blt;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_blt <= rnm_stage_rnRspFifo_buf_1_bru_isa_blt; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_bge <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bge;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_bge <= rnm_stage_rnRspFifo_buf_1_bru_isa_bge; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_bltu <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bltu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_bltu <= rnm_stage_rnRspFifo_buf_1_bru_isa_bltu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_bgeu <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bgeu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_bru_isa_bgeu <= rnm_stage_rnRspFifo_buf_1_bru_isa_bgeu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lb <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lb;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lb <= rnm_stage_rnRspFifo_buf_1_lsu_isa_lb; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lh <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lh;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lh <= rnm_stage_rnRspFifo_buf_1_lsu_isa_lh; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lw <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lw <= rnm_stage_rnRspFifo_buf_1_lsu_isa_lw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_ld <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_ld;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_ld <= rnm_stage_rnRspFifo_buf_1_lsu_isa_ld; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lbu <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lbu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lbu <= rnm_stage_rnRspFifo_buf_1_lsu_isa_lbu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lhu <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lhu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lhu <= rnm_stage_rnRspFifo_buf_1_lsu_isa_lhu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lwu <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lwu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lwu <= rnm_stage_rnRspFifo_buf_1_lsu_isa_lwu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sb <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sb;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sb <= rnm_stage_rnRspFifo_buf_1_lsu_isa_sb; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sh <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sh;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sh <= rnm_stage_rnRspFifo_buf_1_lsu_isa_sh; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sw <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sw <= rnm_stage_rnRspFifo_buf_1_lsu_isa_sw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sd <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sd;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sd <= rnm_stage_rnRspFifo_buf_1_lsu_isa_sd; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fence <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fence;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fence <= rnm_stage_rnRspFifo_buf_1_lsu_isa_fence; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fence_i <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fence_i;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fence_i <= rnm_stage_rnRspFifo_buf_1_lsu_isa_fence_i; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sfence_vma <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sfence_vma;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sfence_vma <= rnm_stage_rnRspFifo_buf_1_lsu_isa_sfence_vma; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lr_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sc_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoswap_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoadd_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoxor_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoand_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoor_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomin_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomax_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amominu_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomaxu_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_w <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lr_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sc_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoswap_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoadd_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoxor_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoand_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoor_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomin_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomax_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amominu_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomaxu_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_d <= rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_flw <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_flw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_flw <= rnm_stage_rnRspFifo_buf_1_lsu_isa_flw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fsw <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fsw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fsw <= rnm_stage_rnRspFifo_buf_1_lsu_isa_fsw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fld <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fld;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fld <= rnm_stage_rnRspFifo_buf_1_lsu_isa_fld; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fsd <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fsd;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_lsu_isa_fsd <= rnm_stage_rnRspFifo_buf_1_lsu_isa_fsd; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rw <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rw <= rnm_stage_rnRspFifo_buf_1_csr_isa_rw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rs <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rs;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rs <= rnm_stage_rnRspFifo_buf_1_csr_isa_rs; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rc <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rc;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rc <= rnm_stage_rnRspFifo_buf_1_csr_isa_rc; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rwi <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rwi;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rwi <= rnm_stage_rnRspFifo_buf_1_csr_isa_rwi; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rsi <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rsi;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rsi <= rnm_stage_rnRspFifo_buf_1_csr_isa_rsi; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rci <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rci;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_csr_isa_rci <= rnm_stage_rnRspFifo_buf_1_csr_isa_rci; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mul <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mul;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mul <= rnm_stage_rnRspFifo_buf_1_mul_isa_mul; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mulh <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulh;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mulh <= rnm_stage_rnRspFifo_buf_1_mul_isa_mulh; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mulhsu <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulhsu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mulhsu <= rnm_stage_rnRspFifo_buf_1_mul_isa_mulhsu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mulhu <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulhu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mulhu <= rnm_stage_rnRspFifo_buf_1_mul_isa_mulhu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_div <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_div;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_div <= rnm_stage_rnRspFifo_buf_1_mul_isa_div; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_divu <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_divu <= rnm_stage_rnRspFifo_buf_1_mul_isa_divu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_rem <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_rem;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_rem <= rnm_stage_rnRspFifo_buf_1_mul_isa_rem; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_remu <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remu;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_remu <= rnm_stage_rnRspFifo_buf_1_mul_isa_remu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mulw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_mulw <= rnm_stage_rnRspFifo_buf_1_mul_isa_mulw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_divw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_divw <= rnm_stage_rnRspFifo_buf_1_mul_isa_divw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_divuw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divuw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_divuw <= rnm_stage_rnRspFifo_buf_1_mul_isa_divuw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_remw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_remw <= rnm_stage_rnRspFifo_buf_1_mul_isa_remw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_remuw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remuw;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_mul_isa_remuw <= rnm_stage_rnRspFifo_buf_1_mul_isa_remuw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmadd_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmsub_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmsub_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmadd_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fadd_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsub_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmul_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fdiv_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsqrt_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnj_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjn_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjx_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmin_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmax_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_w_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_wu_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_w <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmv_x_w;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_w <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_w; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_feq_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_flt_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fle_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fclass_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_l_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_lu_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmadd_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmsub_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmsub_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmadd_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fadd_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsub_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmul_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fdiv_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsqrt_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnj_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjn_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjx_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmin_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmax_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_s_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_s_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_s_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_s_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_d_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_d_s;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_d_s <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_d_s; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_feq_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_flt_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fle_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fclass_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_w_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_wu_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_l_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_lu_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmv_x_d;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_d <= rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_d; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_param_is_rvc <= rnm_stage_rnRspFifo_io_enq_0_bits_param_is_rvc;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_param_is_rvc <= rnm_stage_rnRspFifo_buf_1_param_is_rvc; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_param_pc <= rnm_stage_rnRspFifo_io_enq_0_bits_param_pc;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_param_pc <= rnm_stage_rnRspFifo_buf_1_param_pc; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_param_imm <= rnm_stage_rnRspFifo_io_enq_0_bits_param_imm;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_param_imm <= rnm_stage_rnRspFifo_buf_1_param_imm; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_param_raw_rs1 <= rnm_stage_rnRspFifo_io_enq_0_bits_param_raw_rs1;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_param_raw_rs1 <= rnm_stage_rnRspFifo_buf_1_param_raw_rs1; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_phy_rs1 <= rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs1;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_phy_rs1 <= rnm_stage_rnRspFifo_buf_1_phy_rs1; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_phy_rs2 <= rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs2;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_phy_rs2 <= rnm_stage_rnRspFifo_buf_1_phy_rs2; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_phy_rs3 <= rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs3;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_phy_rs3 <= rnm_stage_rnRspFifo_buf_1_phy_rs3; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_phy_rd0 <= rnm_stage_rnRspFifo_io_enq_0_bits_phy_rd0;
      end else if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_0_phy_rd0 <= rnm_stage_rnRspFifo_buf_1_phy_rd0; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_lui <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_lui;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_lui <= rnm_stage_rnRspFifo_buf_0_alu_isa_lui;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_auipc <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_auipc;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_auipc <= rnm_stage_rnRspFifo_buf_0_alu_isa_auipc;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_addi <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addi;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_addi <= rnm_stage_rnRspFifo_buf_0_alu_isa_addi;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_addiw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addiw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_addiw <= rnm_stage_rnRspFifo_buf_0_alu_isa_addiw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_slti <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slti;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_slti <= rnm_stage_rnRspFifo_buf_0_alu_isa_slti;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sltiu <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sltiu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sltiu <= rnm_stage_rnRspFifo_buf_0_alu_isa_sltiu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_xori <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_xori;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_xori <= rnm_stage_rnRspFifo_buf_0_alu_isa_xori;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_ori <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_ori;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_ori <= rnm_stage_rnRspFifo_buf_0_alu_isa_ori;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_andi <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_andi;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_andi <= rnm_stage_rnRspFifo_buf_0_alu_isa_andi;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_slli <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slli;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_slli <= rnm_stage_rnRspFifo_buf_0_alu_isa_slli;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_slliw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slliw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_slliw <= rnm_stage_rnRspFifo_buf_0_alu_isa_slliw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srli <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srli;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srli <= rnm_stage_rnRspFifo_buf_0_alu_isa_srli;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srliw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srliw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srliw <= rnm_stage_rnRspFifo_buf_0_alu_isa_srliw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srai <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srai;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srai <= rnm_stage_rnRspFifo_buf_0_alu_isa_srai;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sraiw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sraiw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sraiw <= rnm_stage_rnRspFifo_buf_0_alu_isa_sraiw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_add <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_add;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_add <= rnm_stage_rnRspFifo_buf_0_alu_isa_add;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_addw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_addw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_addw <= rnm_stage_rnRspFifo_buf_0_alu_isa_addw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sub <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sub;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sub <= rnm_stage_rnRspFifo_buf_0_alu_isa_sub;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_subw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_subw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_subw <= rnm_stage_rnRspFifo_buf_0_alu_isa_subw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sll <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sll;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sll <= rnm_stage_rnRspFifo_buf_0_alu_isa_sll;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sllw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sllw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sllw <= rnm_stage_rnRspFifo_buf_0_alu_isa_sllw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_slt <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_slt;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_slt <= rnm_stage_rnRspFifo_buf_0_alu_isa_slt;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sltu <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sltu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sltu <= rnm_stage_rnRspFifo_buf_0_alu_isa_sltu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_xor <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_xor;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_xor <= rnm_stage_rnRspFifo_buf_0_alu_isa_xor;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srl <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srl;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srl <= rnm_stage_rnRspFifo_buf_0_alu_isa_srl;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srlw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_srlw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_srlw <= rnm_stage_rnRspFifo_buf_0_alu_isa_srlw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sra <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sra;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sra <= rnm_stage_rnRspFifo_buf_0_alu_isa_sra;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sraw <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_sraw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_sraw <= rnm_stage_rnRspFifo_buf_0_alu_isa_sraw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_or <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_or;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_or <= rnm_stage_rnRspFifo_buf_0_alu_isa_or;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_and <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_and;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_and <= rnm_stage_rnRspFifo_buf_0_alu_isa_and;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_wfi <= rnm_stage_rnRspFifo_io_enq_0_bits_alu_isa_wfi;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_alu_isa_wfi <= rnm_stage_rnRspFifo_buf_0_alu_isa_wfi;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_jal <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_jal;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_jal <= rnm_stage_rnRspFifo_buf_0_bru_isa_jal;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_jalr <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_jalr;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_jalr <= rnm_stage_rnRspFifo_buf_0_bru_isa_jalr;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_beq <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_beq;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_beq <= rnm_stage_rnRspFifo_buf_0_bru_isa_beq;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_bne <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bne;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_bne <= rnm_stage_rnRspFifo_buf_0_bru_isa_bne;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_blt <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_blt;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_blt <= rnm_stage_rnRspFifo_buf_0_bru_isa_blt;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_bge <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bge;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_bge <= rnm_stage_rnRspFifo_buf_0_bru_isa_bge;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_bltu <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bltu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_bltu <= rnm_stage_rnRspFifo_buf_0_bru_isa_bltu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_bgeu <= rnm_stage_rnRspFifo_io_enq_0_bits_bru_isa_bgeu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_bru_isa_bgeu <= rnm_stage_rnRspFifo_buf_0_bru_isa_bgeu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lb <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lb;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lb <= rnm_stage_rnRspFifo_buf_0_lsu_isa_lb;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lh <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lh;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lh <= rnm_stage_rnRspFifo_buf_0_lsu_isa_lh;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lw <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lw <= rnm_stage_rnRspFifo_buf_0_lsu_isa_lw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_ld <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_ld;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_ld <= rnm_stage_rnRspFifo_buf_0_lsu_isa_ld;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lbu <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lbu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lbu <= rnm_stage_rnRspFifo_buf_0_lsu_isa_lbu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lhu <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lhu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lhu <= rnm_stage_rnRspFifo_buf_0_lsu_isa_lhu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lwu <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lwu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lwu <= rnm_stage_rnRspFifo_buf_0_lsu_isa_lwu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sb <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sb;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sb <= rnm_stage_rnRspFifo_buf_0_lsu_isa_sb;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sh <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sh;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sh <= rnm_stage_rnRspFifo_buf_0_lsu_isa_sh;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sw <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sw <= rnm_stage_rnRspFifo_buf_0_lsu_isa_sw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sd <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sd;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sd <= rnm_stage_rnRspFifo_buf_0_lsu_isa_sd;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fence <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fence;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fence <= rnm_stage_rnRspFifo_buf_0_lsu_isa_fence;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fence_i <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fence_i;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fence_i <= rnm_stage_rnRspFifo_buf_0_lsu_isa_fence_i;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sfence_vma <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sfence_vma;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sfence_vma <= rnm_stage_rnRspFifo_buf_0_lsu_isa_sfence_vma;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lr_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sc_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoswap_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoadd_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoxor_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoand_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoor_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomin_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomax_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amominu_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_w <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomaxu_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_w <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_lr_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_sc_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoswap_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoadd_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoxor_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoand_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amoor_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomin_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomax_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amominu_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_d <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_amomaxu_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_d <= rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_flw <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_flw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_flw <= rnm_stage_rnRspFifo_buf_0_lsu_isa_flw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fsw <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fsw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fsw <= rnm_stage_rnRspFifo_buf_0_lsu_isa_fsw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fld <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fld;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fld <= rnm_stage_rnRspFifo_buf_0_lsu_isa_fld;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fsd <= rnm_stage_rnRspFifo_io_enq_0_bits_lsu_isa_fsd;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_lsu_isa_fsd <= rnm_stage_rnRspFifo_buf_0_lsu_isa_fsd;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rw <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rw <= rnm_stage_rnRspFifo_buf_0_csr_isa_rw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rs <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rs;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rs <= rnm_stage_rnRspFifo_buf_0_csr_isa_rs;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rc <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rc;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rc <= rnm_stage_rnRspFifo_buf_0_csr_isa_rc;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rwi <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rwi;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rwi <= rnm_stage_rnRspFifo_buf_0_csr_isa_rwi;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rsi <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rsi;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rsi <= rnm_stage_rnRspFifo_buf_0_csr_isa_rsi;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rci <= rnm_stage_rnRspFifo_io_enq_0_bits_csr_isa_rci;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_csr_isa_rci <= rnm_stage_rnRspFifo_buf_0_csr_isa_rci;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mul <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mul;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mul <= rnm_stage_rnRspFifo_buf_0_mul_isa_mul;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mulh <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulh;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mulh <= rnm_stage_rnRspFifo_buf_0_mul_isa_mulh;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mulhsu <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulhsu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mulhsu <= rnm_stage_rnRspFifo_buf_0_mul_isa_mulhsu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mulhu <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulhu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mulhu <= rnm_stage_rnRspFifo_buf_0_mul_isa_mulhu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_div <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_div;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_div <= rnm_stage_rnRspFifo_buf_0_mul_isa_div;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_divu <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_divu <= rnm_stage_rnRspFifo_buf_0_mul_isa_divu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_rem <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_rem;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_rem <= rnm_stage_rnRspFifo_buf_0_mul_isa_rem;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_remu <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remu;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_remu <= rnm_stage_rnRspFifo_buf_0_mul_isa_remu;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mulw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_mulw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_mulw <= rnm_stage_rnRspFifo_buf_0_mul_isa_mulw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_divw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_divw <= rnm_stage_rnRspFifo_buf_0_mul_isa_divw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_divuw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_divuw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_divuw <= rnm_stage_rnRspFifo_buf_0_mul_isa_divuw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_remw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_remw <= rnm_stage_rnRspFifo_buf_0_mul_isa_remw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_remuw <= rnm_stage_rnRspFifo_io_enq_0_bits_mul_isa_remuw;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_mul_isa_remuw <= rnm_stage_rnRspFifo_buf_0_mul_isa_remuw;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmadd_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmsub_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmsub_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmadd_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fadd_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsub_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmul_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fdiv_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsqrt_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnj_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjn_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjx_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmin_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmax_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_w_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_wu_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_w <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmv_x_w;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_w <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_w;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_feq_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_flt_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fle_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fclass_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_l_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_lu_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmadd_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmsub_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmsub_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fnmadd_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fadd_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsub_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmul_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fdiv_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsqrt_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnj_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjn_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fsgnjx_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmin_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmax_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_s_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_s_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_s_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_s_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_d_s <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_d_s;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_d_s <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_d_s;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_feq_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_flt_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fle_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fclass_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_w_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_wu_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_l_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fcvt_lu_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_d <= rnm_stage_rnRspFifo_io_enq_0_bits_fpu_isa_fmv_x_d;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_d <= rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_d;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_param_is_rvc <= rnm_stage_rnRspFifo_io_enq_0_bits_param_is_rvc;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_param_is_rvc <= rnm_stage_rnRspFifo_buf_0_param_is_rvc;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_param_pc <= rnm_stage_rnRspFifo_io_enq_0_bits_param_pc;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_param_pc <= rnm_stage_rnRspFifo_buf_0_param_pc;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_param_imm <= rnm_stage_rnRspFifo_io_enq_0_bits_param_imm;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_param_imm <= rnm_stage_rnRspFifo_buf_0_param_imm;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_param_raw_rs1 <= rnm_stage_rnRspFifo_io_enq_0_bits_param_raw_rs1;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_param_raw_rs1 <= rnm_stage_rnRspFifo_buf_0_param_raw_rs1;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_phy_rs1 <= rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs1;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_phy_rs1 <= rnm_stage_rnRspFifo_buf_0_phy_rs1;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_phy_rs2 <= rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs2;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_phy_rs2 <= rnm_stage_rnRspFifo_buf_0_phy_rs2;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_phy_rs3 <= rnm_stage_rnRspFifo_io_enq_0_bits_phy_rs3;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_phy_rs3 <= rnm_stage_rnRspFifo_buf_0_phy_rs3;
      end
    end
    if (rnm_stage_rnRspFifo__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_rnRspFifo__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_phy_rd0 <= rnm_stage_rnRspFifo_io_enq_0_bits_phy_rd0;
      end else if (!(rnm_stage_rnRspFifo__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_rnRspFifo_buf_1_phy_rd0 <= rnm_stage_rnRspFifo_buf_0_phy_rd0;
      end
    end
    if (rnm_stage_rnRspFifo_reset) begin // @[MultiPortFifo.scala 58:30]
      rnm_stage_rnRspFifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (rnm_stage_rnRspFifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~rnm_stage_rnRspFifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        rnm_stage_rnRspFifo_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        rnm_stage_rnRspFifo_buf_valid_0 <= rnm_stage_rnRspFifo__GEN_6;
      end
    end else begin
      rnm_stage_rnRspFifo_buf_valid_0 <= rnm_stage_rnRspFifo__GEN_6;
    end
    if (rnm_stage_rnRspFifo_reset) begin // @[MultiPortFifo.scala 58:30]
      rnm_stage_rnRspFifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (rnm_stage_rnRspFifo__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (rnm_stage_rnRspFifo__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        rnm_stage_rnRspFifo_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        rnm_stage_rnRspFifo_buf_valid_1 <= rnm_stage_rnRspFifo__GEN_7;
      end
    end else begin
      rnm_stage_rnRspFifo_buf_valid_1 <= rnm_stage_rnRspFifo__GEN_7;
    end
    if (rnm_stage_rnRspFifo_reset) begin // @[MultiPortFifo.scala 60:27]
      rnm_stage_rnRspFifo_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else begin
      rnm_stage_rnRspFifo_rd_ptr <= rnm_stage_rnRspFifo__rd_ptr_T_2;
    end
    if (rnm_stage_rnRspFifo_reset) begin // @[MultiPortFifo.scala 61:27]
      rnm_stage_rnRspFifo_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else begin
      rnm_stage_rnRspFifo_wr_ptr <= rnm_stage_rnRspFifo__wr_ptr_T_2;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (rnm_stage_rnRspFifo__T_9 & rnm_stage_rnRspFifo__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rnm_stage_rnRspFifo__T_7 & rnm_stage_rnRspFifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (rnm_stage_rnRspFifo__T_9 & rnm_stage_rnRspFifo__T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rnm_stage_rnRspFifo__T_16 & rnm_stage_rnRspFifo__T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge rnm_stage_reOrder_fifo_i_clock) begin
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_pc <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_pc;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_pc <= rnm_stage_reOrder_fifo_i_buf_1_pc; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_rd0_raw <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_rd0_raw;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_rd0_raw <= rnm_stage_reOrder_fifo_i_buf_1_rd0_raw; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_rd0_phy <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_rd0_phy;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_rd0_phy <= rnm_stage_reOrder_fifo_i_buf_1_rd0_phy; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_branch <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_branch;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_branch <= rnm_stage_reOrder_fifo_i_buf_1_is_branch; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_jalr <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_jalr;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_jalr <= rnm_stage_reOrder_fifo_i_buf_1_is_jalr; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_lu <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_lu;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_lu <= rnm_stage_reOrder_fifo_i_buf_1_is_lu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_su <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_su;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_su <= rnm_stage_reOrder_fifo_i_buf_1_is_su; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_amo <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_amo;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_amo <= rnm_stage_reOrder_fifo_i_buf_1_is_amo; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_fence_i <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fence_i;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_fence_i <= rnm_stage_reOrder_fifo_i_buf_1_is_fence_i; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_sfence_vma <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_sfence_vma;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_sfence_vma <= rnm_stage_reOrder_fifo_i_buf_1_is_sfence_vma; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_wfi <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_wfi;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_wfi <= rnm_stage_reOrder_fifo_i_buf_1_is_wfi; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_csr <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_csr;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_csr <= rnm_stage_reOrder_fifo_i_buf_1_is_csr; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_fpu <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fpu;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_fpu <= rnm_stage_reOrder_fifo_i_buf_1_is_fpu; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_fcsr <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fcsr;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_fcsr <= rnm_stage_reOrder_fifo_i_buf_1_is_fcsr; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_xcmm <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_xcmm;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_xcmm <= rnm_stage_reOrder_fifo_i_buf_1_is_xcmm; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_fcmm <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fcmm;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_fcmm <= rnm_stage_reOrder_fifo_i_buf_1_is_fcmm; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_ecall <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_ecall;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_ecall <= rnm_stage_reOrder_fifo_i_buf_1_privil_ecall; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_ebreak <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_ebreak;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_ebreak <= rnm_stage_reOrder_fifo_i_buf_1_privil_ebreak; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_mret <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_mret;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_mret <= rnm_stage_reOrder_fifo_i_buf_1_privil_mret; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_sret <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_sret;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_sret <= rnm_stage_reOrder_fifo_i_buf_1_privil_sret; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_dret <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_dret;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_dret <= rnm_stage_reOrder_fifo_i_buf_1_privil_dret; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_is_access_fault <=
          rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_is_access_fault;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_is_access_fault <= rnm_stage_reOrder_fifo_i_buf_1_privil_is_access_fault; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_is_paging_fault <=
          rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_is_paging_fault;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_privil_is_paging_fault <= rnm_stage_reOrder_fifo_i_buf_1_privil_is_paging_fault; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (~rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_illeage <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_illeage;
      end else if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_0_is_illeage <= rnm_stage_reOrder_fifo_i_buf_1_is_illeage; // @[MultiPortFifo.scala 101:33]
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_pc <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_pc;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_pc <= rnm_stage_reOrder_fifo_i_buf_0_pc;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_rd0_raw <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_rd0_raw;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_rd0_raw <= rnm_stage_reOrder_fifo_i_buf_0_rd0_raw;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_rd0_phy <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_rd0_phy;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_rd0_phy <= rnm_stage_reOrder_fifo_i_buf_0_rd0_phy;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_branch <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_branch;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_branch <= rnm_stage_reOrder_fifo_i_buf_0_is_branch;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_jalr <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_jalr;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_jalr <= rnm_stage_reOrder_fifo_i_buf_0_is_jalr;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_lu <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_lu;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_lu <= rnm_stage_reOrder_fifo_i_buf_0_is_lu;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_su <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_su;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_su <= rnm_stage_reOrder_fifo_i_buf_0_is_su;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_amo <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_amo;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_amo <= rnm_stage_reOrder_fifo_i_buf_0_is_amo;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_fence_i <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fence_i;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_fence_i <= rnm_stage_reOrder_fifo_i_buf_0_is_fence_i;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_sfence_vma <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_sfence_vma;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_sfence_vma <= rnm_stage_reOrder_fifo_i_buf_0_is_sfence_vma;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_wfi <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_wfi;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_wfi <= rnm_stage_reOrder_fifo_i_buf_0_is_wfi;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_csr <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_csr;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_csr <= rnm_stage_reOrder_fifo_i_buf_0_is_csr;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_fpu <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fpu;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_fpu <= rnm_stage_reOrder_fifo_i_buf_0_is_fpu;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_fcsr <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fcsr;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_fcsr <= rnm_stage_reOrder_fifo_i_buf_0_is_fcsr;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_xcmm <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_xcmm;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_xcmm <= rnm_stage_reOrder_fifo_i_buf_0_is_xcmm;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_fcmm <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_fcmm;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_fcmm <= rnm_stage_reOrder_fifo_i_buf_0_is_fcmm;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_ecall <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_ecall;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_ecall <= rnm_stage_reOrder_fifo_i_buf_0_privil_ecall;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_ebreak <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_ebreak;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_ebreak <= rnm_stage_reOrder_fifo_i_buf_0_privil_ebreak;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_mret <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_mret;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_mret <= rnm_stage_reOrder_fifo_i_buf_0_privil_mret;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_sret <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_sret;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_sret <= rnm_stage_reOrder_fifo_i_buf_0_privil_sret;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_dret <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_dret;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_dret <= rnm_stage_reOrder_fifo_i_buf_0_privil_dret;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_is_access_fault <=
          rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_is_access_fault;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_is_access_fault <= rnm_stage_reOrder_fifo_i_buf_0_privil_is_access_fault;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_is_paging_fault <=
          rnm_stage_reOrder_fifo_i_io_enq_0_bits_privil_is_paging_fault;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_privil_is_paging_fault <= rnm_stage_reOrder_fifo_i_buf_0_privil_is_paging_fault;
      end
    end
    if (rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1) begin // @[MultiPortFifo.scala 101:27]
      if (rnm_stage_reOrder_fifo_i__T) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_illeage <= rnm_stage_reOrder_fifo_i_io_enq_0_bits_is_illeage;
      end else if (!(rnm_stage_reOrder_fifo_i__io_enq_0_ready_T_1)) begin // @[MultiPortFifo.scala 101:33]
        rnm_stage_reOrder_fifo_i_buf_1_is_illeage <= rnm_stage_reOrder_fifo_i_buf_0_is_illeage;
      end
    end
    if (rnm_stage_reOrder_fifo_i_reset) begin // @[MultiPortFifo.scala 58:30]
      rnm_stage_reOrder_fifo_i_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (rnm_stage_reOrder_fifo_i__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (~rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        rnm_stage_reOrder_fifo_i_buf_valid_0 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        rnm_stage_reOrder_fifo_i_buf_valid_0 <= rnm_stage_reOrder_fifo_i__GEN_6;
      end
    end else begin
      rnm_stage_reOrder_fifo_i_buf_valid_0 <= rnm_stage_reOrder_fifo_i__GEN_6;
    end
    if (rnm_stage_reOrder_fifo_i_reset) begin // @[MultiPortFifo.scala 58:30]
      rnm_stage_reOrder_fifo_i_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 58:30]
    end else if (rnm_stage_reOrder_fifo_i__T_1) begin // @[MultiPortFifo.scala 98:34]
      if (rnm_stage_reOrder_fifo_i__io_deq_0_valid_T_1) begin // @[MultiPortFifo.scala 98:57]
        rnm_stage_reOrder_fifo_i_buf_valid_1 <= 1'h0; // @[MultiPortFifo.scala 98:57]
      end else begin
        rnm_stage_reOrder_fifo_i_buf_valid_1 <= rnm_stage_reOrder_fifo_i__GEN_7;
      end
    end else begin
      rnm_stage_reOrder_fifo_i_buf_valid_1 <= rnm_stage_reOrder_fifo_i__GEN_7;
    end
    if (rnm_stage_reOrder_fifo_i_reset) begin // @[MultiPortFifo.scala 60:27]
      rnm_stage_reOrder_fifo_i_rd_ptr <= 1'h0; // @[MultiPortFifo.scala 60:27]
    end else begin
      rnm_stage_reOrder_fifo_i_rd_ptr <= rnm_stage_reOrder_fifo_i__rd_ptr_T_2;
    end
    if (rnm_stage_reOrder_fifo_i_reset) begin // @[MultiPortFifo.scala 61:27]
      rnm_stage_reOrder_fifo_i_wr_ptr <= 1'h0; // @[MultiPortFifo.scala 61:27]
    end else begin
      rnm_stage_reOrder_fifo_i_wr_ptr <= rnm_stage_reOrder_fifo_i__wr_ptr_T_2;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (rnm_stage_reOrder_fifo_i__T_9 & rnm_stage_reOrder_fifo_i__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! in port illegal\n    at MultiPortFifo.scala:161 assert( !(io.enq(i).valid === true.B && io.enq(j).valid === false.B && i.U >= j.U), \"Assert Fail! in port illegal\")\n"
            ); // @[MultiPortFifo.scala 161:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rnm_stage_reOrder_fifo_i__T_7 & rnm_stage_reOrder_fifo_i__T_9) begin
          $fatal; // @[MultiPortFifo.scala 161:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (rnm_stage_reOrder_fifo_i__T_9 & rnm_stage_reOrder_fifo_i__T_19) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail! out port illegal\n    at MultiPortFifo.scala:164 assert( !(io.deq(i).valid === true.B && io.deq(j).valid === false.B && i.U >= j.U), \"Assert Fail! out port illegal\")\n"
            ); // @[MultiPortFifo.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rnm_stage_reOrder_fifo_i__T_16 & rnm_stage_reOrder_fifo_i__T_9) begin
          $fatal; // @[MultiPortFifo.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge rnm_stage_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (rnm_stage__T_6 & rnm_stage__T_7) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, rename should be one-hot\n    at Rename.scala:84 for ( j <- 0 until rnChn ) { assert( PopCount( Seq(io.fRename(j).req.fire, io.xRename(j).req.fire)) <= 1.U, \"Assert Failed, rename should be one-hot\" ) }\n"
            ); // @[Rename.scala 84:40]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rnm_stage__T_4 & rnm_stage__T_6) begin
          $fatal; // @[Rename.scala 84:40]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (rnm_stage__rnRspReport_io_enq_0_valid_T & rnm_stage__T_6 & rnm_stage__T_75) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Rename.scala:157 assert(io.rnReq(i).bits.fpu_isa.is_fpu === false.B)\n"); // @[Rename.scala 157:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rnm_stage__T_72 & (rnm_stage__rnRspReport_io_enq_0_valid_T & rnm_stage__T_6)) begin
          $fatal; // @[Rename.scala 157:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_222 & rnm_stage__T_120) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Rename.scala:158 assert(io.rnReq(i).bits.is_fwb === false.B)\n"
            ); // @[Rename.scala 158:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~rnm_stage__io_xRename_0_req_valid_T_42 & (rnm_stage__rnRspReport_io_enq_0_valid_T & rnm_stage__T_6)) begin
          $fatal; // @[Rename.scala 158:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_fun_add_clock) begin
    if (iss_stage_aluIssFifo_0_ram_fun_add_MPORT_en & iss_stage_aluIssFifo_0_ram_fun_add_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_fun_add[iss_stage_aluIssFifo_0_ram_fun_add_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_fun_add_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_fun_slt_clock) begin
    if (iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_en & iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_fun_slt[iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_fun_slt_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_fun_xor_clock) begin
    if (iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_en & iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_fun_xor[iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_fun_xor_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_fun_or_clock) begin
    if (iss_stage_aluIssFifo_0_ram_fun_or_MPORT_en & iss_stage_aluIssFifo_0_ram_fun_or_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_fun_or[iss_stage_aluIssFifo_0_ram_fun_or_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_fun_or_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_fun_and_clock) begin
    if (iss_stage_aluIssFifo_0_ram_fun_and_MPORT_en & iss_stage_aluIssFifo_0_ram_fun_and_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_fun_and[iss_stage_aluIssFifo_0_ram_fun_and_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_fun_and_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_fun_sll_clock) begin
    if (iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_en & iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_fun_sll[iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_fun_sll_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_fun_srl_clock) begin
    if (iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_en & iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_fun_srl[iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_fun_srl_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_fun_sra_clock) begin
    if (iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_en & iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_fun_sra[iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_fun_sra_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_param_rd0_clock) begin
    if (iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_en & iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_param_rd0[iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_param_is_32w_clock) begin
    if (iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_en & iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_param_is_32w[iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_param_is_32w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_param_is_usi_clock) begin
    if (iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_en & iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_param_is_usi[iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_param_is_usi_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_param_dat_op1_clock) begin
    if (iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_en & iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_param_dat_op1[iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_ram_param_dat_op2_clock) begin
    if (iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_en & iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_mask) begin
      iss_stage_aluIssFifo_0_ram_param_dat_op2[iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_addr] <=
        iss_stage_aluIssFifo_0_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_aluIssFifo_0_clock) begin
    if (iss_stage_aluIssFifo_0_reset) begin // @[Decoupled.scala 278:27]
      iss_stage_aluIssFifo_0_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (iss_stage_aluIssFifo_0__T) begin // @[Decoupled.scala 295:27]
      if (iss_stage_aluIssFifo_0__empty_T) begin // @[Decoupled.scala 317:17]
        if (iss_stage_aluIssFifo_0_io_deq_ready) begin // @[Decoupled.scala 320:26]
          iss_stage_aluIssFifo_0_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          iss_stage_aluIssFifo_0_maybe_full <= iss_stage_aluIssFifo_0__do_enq_T;
        end
      end else begin
        iss_stage_aluIssFifo_0_maybe_full <= iss_stage_aluIssFifo_0__do_enq_T;
      end
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_mul_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_mul[iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_mul_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_mulh_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_mulh[iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_mulh_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_mulhsu_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_mulhsu[iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_mulhsu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_mulhu_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_mulhu[iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_mulhu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_div_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_div_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_div_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_div[iss_stage_mulIssFifo_0_ram_fun_div_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_div_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_divu_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_divu[iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_divu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_rem_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_rem[iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_rem_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_remu_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_remu[iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_remu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_mulw_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_mulw[iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_mulw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_divw_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_divw[iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_divw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_divuw_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_divuw[iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_divuw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_remw_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_remw[iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_remw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_fun_remuw_clock) begin
    if (iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_en & iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_fun_remuw[iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_fun_remuw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_param_rd0_clock) begin
    if (iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_en & iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_param_rd0[iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_param_dat_op1_clock) begin
    if (iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_en & iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_param_dat_op1[iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_ram_param_dat_op2_clock) begin
    if (iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_en & iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_mask) begin
      iss_stage_mulIssFifo_0_ram_param_dat_op2[iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_addr] <=
        iss_stage_mulIssFifo_0_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_mulIssFifo_0_clock) begin
    if (iss_stage_mulIssFifo_0_reset) begin // @[Decoupled.scala 278:27]
      iss_stage_mulIssFifo_0_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (iss_stage_mulIssFifo_0__T) begin // @[Decoupled.scala 295:27]
      if (iss_stage_mulIssFifo_0__empty_T) begin // @[Decoupled.scala 317:17]
        if (iss_stage_mulIssFifo_0_io_deq_ready) begin // @[Decoupled.scala 320:26]
          iss_stage_mulIssFifo_0_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          iss_stage_mulIssFifo_0_maybe_full <= iss_stage_mulIssFifo_0__do_enq_T;
        end
      end else begin
        iss_stage_mulIssFifo_0_maybe_full <= iss_stage_mulIssFifo_0__do_enq_T;
      end
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_fun_jalr_clock) begin
    if (iss_stage_bruIssFifo_ram_fun_jalr_MPORT_en & iss_stage_bruIssFifo_ram_fun_jalr_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_fun_jalr[iss_stage_bruIssFifo_ram_fun_jalr_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_fun_jalr_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_fun_beq_clock) begin
    if (iss_stage_bruIssFifo_ram_fun_beq_MPORT_en & iss_stage_bruIssFifo_ram_fun_beq_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_fun_beq[iss_stage_bruIssFifo_ram_fun_beq_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_fun_beq_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_fun_bne_clock) begin
    if (iss_stage_bruIssFifo_ram_fun_bne_MPORT_en & iss_stage_bruIssFifo_ram_fun_bne_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_fun_bne[iss_stage_bruIssFifo_ram_fun_bne_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_fun_bne_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_fun_blt_clock) begin
    if (iss_stage_bruIssFifo_ram_fun_blt_MPORT_en & iss_stage_bruIssFifo_ram_fun_blt_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_fun_blt[iss_stage_bruIssFifo_ram_fun_blt_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_fun_blt_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_fun_bge_clock) begin
    if (iss_stage_bruIssFifo_ram_fun_bge_MPORT_en & iss_stage_bruIssFifo_ram_fun_bge_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_fun_bge[iss_stage_bruIssFifo_ram_fun_bge_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_fun_bge_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_fun_bltu_clock) begin
    if (iss_stage_bruIssFifo_ram_fun_bltu_MPORT_en & iss_stage_bruIssFifo_ram_fun_bltu_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_fun_bltu[iss_stage_bruIssFifo_ram_fun_bltu_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_fun_bltu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_fun_bgeu_clock) begin
    if (iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_en & iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_fun_bgeu[iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_fun_bgeu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_param_rd0_clock) begin
    if (iss_stage_bruIssFifo_ram_param_rd0_MPORT_en & iss_stage_bruIssFifo_ram_param_rd0_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_param_rd0[iss_stage_bruIssFifo_ram_param_rd0_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_param_is_rvc_clock) begin
    if (iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_en & iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_param_is_rvc[iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_param_is_rvc_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_param_pc_clock) begin
    if (iss_stage_bruIssFifo_ram_param_pc_MPORT_en & iss_stage_bruIssFifo_ram_param_pc_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_param_pc[iss_stage_bruIssFifo_ram_param_pc_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_param_pc_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_param_imm_clock) begin
    if (iss_stage_bruIssFifo_ram_param_imm_MPORT_en & iss_stage_bruIssFifo_ram_param_imm_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_param_imm[iss_stage_bruIssFifo_ram_param_imm_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_param_imm_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_param_dat_op1_clock) begin
    if (iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_en & iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_param_dat_op1[iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_ram_param_dat_op2_clock) begin
    if (iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_en & iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_mask) begin
      iss_stage_bruIssFifo_ram_param_dat_op2[iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_addr] <=
        iss_stage_bruIssFifo_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_bruIssFifo_clock) begin
    if (iss_stage_bruIssFifo_reset) begin // @[Decoupled.scala 278:27]
      iss_stage_bruIssFifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (iss_stage_bruIssFifo__T) begin // @[Decoupled.scala 295:27]
      if (iss_stage_bruIssFifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (iss_stage_bruIssFifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          iss_stage_bruIssFifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          iss_stage_bruIssFifo_maybe_full <= iss_stage_bruIssFifo__do_enq_T;
        end
      end else begin
        iss_stage_bruIssFifo_maybe_full <= iss_stage_bruIssFifo__do_enq_T;
      end
    end
  end
  always @(posedge iss_stage_csrIssFifo_ram_fun_rw_clock) begin
    if (iss_stage_csrIssFifo_ram_fun_rw_MPORT_en & iss_stage_csrIssFifo_ram_fun_rw_MPORT_mask) begin
      iss_stage_csrIssFifo_ram_fun_rw[iss_stage_csrIssFifo_ram_fun_rw_MPORT_addr] <=
        iss_stage_csrIssFifo_ram_fun_rw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_csrIssFifo_ram_fun_rs_clock) begin
    if (iss_stage_csrIssFifo_ram_fun_rs_MPORT_en & iss_stage_csrIssFifo_ram_fun_rs_MPORT_mask) begin
      iss_stage_csrIssFifo_ram_fun_rs[iss_stage_csrIssFifo_ram_fun_rs_MPORT_addr] <=
        iss_stage_csrIssFifo_ram_fun_rs_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_csrIssFifo_ram_fun_rc_clock) begin
    if (iss_stage_csrIssFifo_ram_fun_rc_MPORT_en & iss_stage_csrIssFifo_ram_fun_rc_MPORT_mask) begin
      iss_stage_csrIssFifo_ram_fun_rc[iss_stage_csrIssFifo_ram_fun_rc_MPORT_addr] <=
        iss_stage_csrIssFifo_ram_fun_rc_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_csrIssFifo_ram_param_rd0_clock) begin
    if (iss_stage_csrIssFifo_ram_param_rd0_MPORT_en & iss_stage_csrIssFifo_ram_param_rd0_MPORT_mask) begin
      iss_stage_csrIssFifo_ram_param_rd0[iss_stage_csrIssFifo_ram_param_rd0_MPORT_addr] <=
        iss_stage_csrIssFifo_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_csrIssFifo_ram_param_dat_op1_clock) begin
    if (iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_en & iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_mask) begin
      iss_stage_csrIssFifo_ram_param_dat_op1[iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_addr] <=
        iss_stage_csrIssFifo_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_csrIssFifo_ram_param_dat_op2_clock) begin
    if (iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_en & iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_mask) begin
      iss_stage_csrIssFifo_ram_param_dat_op2[iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_addr] <=
        iss_stage_csrIssFifo_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_csrIssFifo_clock) begin
    if (iss_stage_csrIssFifo_reset) begin // @[Decoupled.scala 278:27]
      iss_stage_csrIssFifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (iss_stage_csrIssFifo__T) begin // @[Decoupled.scala 295:27]
      if (iss_stage_csrIssFifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (iss_stage_csrIssFifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          iss_stage_csrIssFifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          iss_stage_csrIssFifo_maybe_full <= iss_stage_csrIssFifo__do_enq_T;
        end
      end else begin
        iss_stage_csrIssFifo_maybe_full <= iss_stage_csrIssFifo__do_enq_T;
      end
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_lb_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_lb_MPORT_en & iss_stage_lsuIssFifo_ram_fun_lb_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_lb[iss_stage_lsuIssFifo_ram_fun_lb_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_lh_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_lh_MPORT_en & iss_stage_lsuIssFifo_ram_fun_lh_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_lh[iss_stage_lsuIssFifo_ram_fun_lh_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_lw_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_lw_MPORT_en & iss_stage_lsuIssFifo_ram_fun_lw_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_lw[iss_stage_lsuIssFifo_ram_fun_lw_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_ld_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_ld_MPORT_en & iss_stage_lsuIssFifo_ram_fun_ld_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_ld[iss_stage_lsuIssFifo_ram_fun_ld_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_lbu_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_en & iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_lbu[iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_lhu_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_en & iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_lhu[iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_lwu_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_en & iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_lwu[iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_sb_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_sb_MPORT_en & iss_stage_lsuIssFifo_ram_fun_sb_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_sb[iss_stage_lsuIssFifo_ram_fun_sb_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_sh_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_sh_MPORT_en & iss_stage_lsuIssFifo_ram_fun_sh_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_sh[iss_stage_lsuIssFifo_ram_fun_sh_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_sw_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_sw_MPORT_en & iss_stage_lsuIssFifo_ram_fun_sw_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_sw[iss_stage_lsuIssFifo_ram_fun_sw_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_sd_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_sd_MPORT_en & iss_stage_lsuIssFifo_ram_fun_sd_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_sd[iss_stage_lsuIssFifo_ram_fun_sd_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_fence_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_fence_MPORT_en & iss_stage_lsuIssFifo_ram_fun_fence_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_fence[iss_stage_lsuIssFifo_ram_fun_fence_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_fence_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_fence_i_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_en & iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_fence_i[iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_fence_i_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_sfence_vma_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_en & iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_sfence_vma[iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_sfence_vma_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_lr_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_lr_w[iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_sc_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_sc_w[iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoswap_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoswap_w[iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoadd_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoadd_w[iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoxor_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoxor_w[iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoand_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoand_w[iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoor_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoor_w[iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amomin_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amomin_w[iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amomax_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amomax_w[iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amominu_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amominu_w[iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amomaxu_w_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amomaxu_w[iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_lr_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_lr_d[iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_sc_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_sc_d[iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoswap_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoswap_d[iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoadd_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoadd_d[iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoxor_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoxor_d[iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoand_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoand_d[iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amoor_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amoor_d[iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amomin_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amomin_d[iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amomax_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amomax_d[iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amominu_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amominu_d[iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_amomaxu_d_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_en & iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_amomaxu_d[iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_flw_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_flw_MPORT_en & iss_stage_lsuIssFifo_ram_fun_flw_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_flw[iss_stage_lsuIssFifo_ram_fun_flw_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_fsw_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_en & iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_fsw[iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_fld_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_fld_MPORT_en & iss_stage_lsuIssFifo_ram_fun_fld_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_fld[iss_stage_lsuIssFifo_ram_fun_fld_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_fun_fsd_clock) begin
    if (iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_en & iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_fun_fsd[iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_param_rd0_clock) begin
    if (iss_stage_lsuIssFifo_ram_param_rd0_MPORT_en & iss_stage_lsuIssFifo_ram_param_rd0_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_param_rd0[iss_stage_lsuIssFifo_ram_param_rd0_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_param_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_param_dat_op1_clock) begin
    if (iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_en & iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_param_dat_op1[iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_param_dat_op1_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_ram_param_dat_op2_clock) begin
    if (iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_en & iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_mask) begin
      iss_stage_lsuIssFifo_ram_param_dat_op2[iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_addr] <=
        iss_stage_lsuIssFifo_ram_param_dat_op2_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge iss_stage_lsuIssFifo_clock) begin
    if (iss_stage_lsuIssFifo_reset) begin // @[Decoupled.scala 278:27]
      iss_stage_lsuIssFifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (iss_stage_lsuIssFifo__T) begin // @[Decoupled.scala 295:27]
      if (iss_stage_lsuIssFifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (iss_stage_lsuIssFifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          iss_stage_lsuIssFifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          iss_stage_lsuIssFifo_maybe_full <= iss_stage_lsuIssFifo__do_enq_T;
        end
      end else begin
        iss_stage_lsuIssFifo_maybe_full <= iss_stage_lsuIssFifo__do_enq_T;
      end
    end
  end
  always @(posedge iss_stage_clock) begin
    if (iss_stage_reset) begin // @[Issue.scala 61:29]
      iss_stage_bufValid_0 <= 1'h0; // @[Issue.scala 61:29]
    end else if (iss_stage__T_630) begin // @[Issue.scala 900:56]
      iss_stage_bufValid_0 <= 1'h0; // @[Issue.scala 901:19]
    end else if (iss_stage__T_569) begin // @[Issue.scala 837:56]
      iss_stage_bufValid_0 <= 1'h0; // @[Issue.scala 838:19]
    end else if (iss_stage__T_504) begin // @[Issue.scala 771:56]
      iss_stage_bufValid_0 <= 1'h0; // @[Issue.scala 772:19]
    end else begin
      iss_stage_bufValid_0 <= iss_stage__GEN_1806;
    end
    if (iss_stage_reset) begin // @[Issue.scala 61:29]
      iss_stage_bufValid_1 <= 1'h0; // @[Issue.scala 61:29]
    end else if (iss_stage__T_684) begin // @[Issue.scala 900:56]
      iss_stage_bufValid_1 <= 1'h0; // @[Issue.scala 901:19]
    end else if (iss_stage__T_587) begin // @[Issue.scala 837:56]
      iss_stage_bufValid_1 <= 1'h0; // @[Issue.scala 838:19]
    end else if (iss_stage__T_524) begin // @[Issue.scala 771:56]
      iss_stage_bufValid_1 <= 1'h0; // @[Issue.scala 772:19]
    end else begin
      iss_stage_bufValid_1 <= iss_stage__GEN_1807;
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_lui <= iss_stage_io_dptReq_0_bits_alu_isa_lui; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_auipc <= iss_stage_io_dptReq_0_bits_alu_isa_auipc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_addi <= iss_stage_io_dptReq_0_bits_alu_isa_addi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_addiw <= iss_stage_io_dptReq_0_bits_alu_isa_addiw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_slti <= iss_stage_io_dptReq_0_bits_alu_isa_slti; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_sltiu <= iss_stage_io_dptReq_0_bits_alu_isa_sltiu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_xori <= iss_stage_io_dptReq_0_bits_alu_isa_xori; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_ori <= iss_stage_io_dptReq_0_bits_alu_isa_ori; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_andi <= iss_stage_io_dptReq_0_bits_alu_isa_andi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_slli <= iss_stage_io_dptReq_0_bits_alu_isa_slli; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_slliw <= iss_stage_io_dptReq_0_bits_alu_isa_slliw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_srli <= iss_stage_io_dptReq_0_bits_alu_isa_srli; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_srliw <= iss_stage_io_dptReq_0_bits_alu_isa_srliw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_srai <= iss_stage_io_dptReq_0_bits_alu_isa_srai; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_sraiw <= iss_stage_io_dptReq_0_bits_alu_isa_sraiw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_add <= iss_stage_io_dptReq_0_bits_alu_isa_add; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_addw <= iss_stage_io_dptReq_0_bits_alu_isa_addw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_sub <= iss_stage_io_dptReq_0_bits_alu_isa_sub; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_subw <= iss_stage_io_dptReq_0_bits_alu_isa_subw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_sll <= iss_stage_io_dptReq_0_bits_alu_isa_sll; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_sllw <= iss_stage_io_dptReq_0_bits_alu_isa_sllw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_slt <= iss_stage_io_dptReq_0_bits_alu_isa_slt; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_sltu <= iss_stage_io_dptReq_0_bits_alu_isa_sltu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_xor <= iss_stage_io_dptReq_0_bits_alu_isa_xor; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_srl <= iss_stage_io_dptReq_0_bits_alu_isa_srl; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_srlw <= iss_stage_io_dptReq_0_bits_alu_isa_srlw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_sra <= iss_stage_io_dptReq_0_bits_alu_isa_sra; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_sraw <= iss_stage_io_dptReq_0_bits_alu_isa_sraw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_or <= iss_stage_io_dptReq_0_bits_alu_isa_or; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_and <= iss_stage_io_dptReq_0_bits_alu_isa_and; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_alu_isa_wfi <= iss_stage_io_dptReq_0_bits_alu_isa_wfi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_bru_isa_jal <= iss_stage_io_dptReq_0_bits_bru_isa_jal; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_bru_isa_jalr <= iss_stage_io_dptReq_0_bits_bru_isa_jalr; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_bru_isa_beq <= iss_stage_io_dptReq_0_bits_bru_isa_beq; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_bru_isa_bne <= iss_stage_io_dptReq_0_bits_bru_isa_bne; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_bru_isa_blt <= iss_stage_io_dptReq_0_bits_bru_isa_blt; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_bru_isa_bge <= iss_stage_io_dptReq_0_bits_bru_isa_bge; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_bru_isa_bltu <= iss_stage_io_dptReq_0_bits_bru_isa_bltu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_bru_isa_bgeu <= iss_stage_io_dptReq_0_bits_bru_isa_bgeu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_lb <= iss_stage_io_dptReq_0_bits_lsu_isa_lb; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_lh <= iss_stage_io_dptReq_0_bits_lsu_isa_lh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_lw <= iss_stage_io_dptReq_0_bits_lsu_isa_lw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_ld <= iss_stage_io_dptReq_0_bits_lsu_isa_ld; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_lbu <= iss_stage_io_dptReq_0_bits_lsu_isa_lbu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_lhu <= iss_stage_io_dptReq_0_bits_lsu_isa_lhu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_lwu <= iss_stage_io_dptReq_0_bits_lsu_isa_lwu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_sb <= iss_stage_io_dptReq_0_bits_lsu_isa_sb; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_sh <= iss_stage_io_dptReq_0_bits_lsu_isa_sh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_sw <= iss_stage_io_dptReq_0_bits_lsu_isa_sw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_sd <= iss_stage_io_dptReq_0_bits_lsu_isa_sd; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_fence <= iss_stage_io_dptReq_0_bits_lsu_isa_fence; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_fence_i <= iss_stage_io_dptReq_0_bits_lsu_isa_fence_i; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_sfence_vma <= iss_stage_io_dptReq_0_bits_lsu_isa_sfence_vma; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_lr_w <= iss_stage_io_dptReq_0_bits_lsu_isa_lr_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_sc_w <= iss_stage_io_dptReq_0_bits_lsu_isa_sc_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoswap_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoswap_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoadd_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoadd_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoxor_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoxor_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoand_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoand_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoor_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoor_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amomin_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amomin_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amomax_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amomax_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amominu_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amominu_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amomaxu_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amomaxu_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_lr_d <= iss_stage_io_dptReq_0_bits_lsu_isa_lr_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_sc_d <= iss_stage_io_dptReq_0_bits_lsu_isa_sc_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoswap_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoswap_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoadd_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoadd_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoxor_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoxor_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoand_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoand_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amoor_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoor_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amomin_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amomin_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amomax_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amomax_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amominu_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amominu_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_amomaxu_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amomaxu_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_flw <= iss_stage_io_dptReq_0_bits_lsu_isa_flw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_fsw <= iss_stage_io_dptReq_0_bits_lsu_isa_fsw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_fld <= iss_stage_io_dptReq_0_bits_lsu_isa_fld; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_lsu_isa_fsd <= iss_stage_io_dptReq_0_bits_lsu_isa_fsd; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_csr_isa_rw <= iss_stage_io_dptReq_0_bits_csr_isa_rw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_csr_isa_rs <= iss_stage_io_dptReq_0_bits_csr_isa_rs; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_csr_isa_rc <= iss_stage_io_dptReq_0_bits_csr_isa_rc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_csr_isa_rwi <= iss_stage_io_dptReq_0_bits_csr_isa_rwi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_csr_isa_rsi <= iss_stage_io_dptReq_0_bits_csr_isa_rsi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_csr_isa_rci <= iss_stage_io_dptReq_0_bits_csr_isa_rci; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_mul <= iss_stage_io_dptReq_0_bits_mul_isa_mul; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_mulh <= iss_stage_io_dptReq_0_bits_mul_isa_mulh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_mulhsu <= iss_stage_io_dptReq_0_bits_mul_isa_mulhsu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_mulhu <= iss_stage_io_dptReq_0_bits_mul_isa_mulhu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_div <= iss_stage_io_dptReq_0_bits_mul_isa_div; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_divu <= iss_stage_io_dptReq_0_bits_mul_isa_divu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_rem <= iss_stage_io_dptReq_0_bits_mul_isa_rem; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_remu <= iss_stage_io_dptReq_0_bits_mul_isa_remu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_mulw <= iss_stage_io_dptReq_0_bits_mul_isa_mulw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_divw <= iss_stage_io_dptReq_0_bits_mul_isa_divw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_divuw <= iss_stage_io_dptReq_0_bits_mul_isa_divuw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_remw <= iss_stage_io_dptReq_0_bits_mul_isa_remw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_mul_isa_remuw <= iss_stage_io_dptReq_0_bits_mul_isa_remuw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_param_is_rvc <= iss_stage_io_dptReq_0_bits_param_is_rvc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_param_pc <= iss_stage_io_dptReq_0_bits_param_pc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_param_imm <= iss_stage_io_dptReq_0_bits_param_imm; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_param_raw_rs1 <= iss_stage_io_dptReq_0_bits_param_raw_rs1; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_phy_rs1 <= iss_stage_io_dptReq_0_bits_phy_rs1; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_phy_rs2 <= iss_stage_io_dptReq_0_bits_phy_rs2; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (~iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_0_phy_rd0 <= iss_stage_io_dptReq_0_bits_phy_rd0; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_lui <= iss_stage_io_dptReq_0_bits_alu_isa_lui; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_auipc <= iss_stage_io_dptReq_0_bits_alu_isa_auipc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_addi <= iss_stage_io_dptReq_0_bits_alu_isa_addi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_addiw <= iss_stage_io_dptReq_0_bits_alu_isa_addiw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_slti <= iss_stage_io_dptReq_0_bits_alu_isa_slti; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_sltiu <= iss_stage_io_dptReq_0_bits_alu_isa_sltiu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_xori <= iss_stage_io_dptReq_0_bits_alu_isa_xori; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_ori <= iss_stage_io_dptReq_0_bits_alu_isa_ori; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_andi <= iss_stage_io_dptReq_0_bits_alu_isa_andi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_slli <= iss_stage_io_dptReq_0_bits_alu_isa_slli; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_slliw <= iss_stage_io_dptReq_0_bits_alu_isa_slliw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_srli <= iss_stage_io_dptReq_0_bits_alu_isa_srli; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_srliw <= iss_stage_io_dptReq_0_bits_alu_isa_srliw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_srai <= iss_stage_io_dptReq_0_bits_alu_isa_srai; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_sraiw <= iss_stage_io_dptReq_0_bits_alu_isa_sraiw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_add <= iss_stage_io_dptReq_0_bits_alu_isa_add; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_addw <= iss_stage_io_dptReq_0_bits_alu_isa_addw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_sub <= iss_stage_io_dptReq_0_bits_alu_isa_sub; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_subw <= iss_stage_io_dptReq_0_bits_alu_isa_subw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_sll <= iss_stage_io_dptReq_0_bits_alu_isa_sll; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_sllw <= iss_stage_io_dptReq_0_bits_alu_isa_sllw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_slt <= iss_stage_io_dptReq_0_bits_alu_isa_slt; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_sltu <= iss_stage_io_dptReq_0_bits_alu_isa_sltu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_xor <= iss_stage_io_dptReq_0_bits_alu_isa_xor; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_srl <= iss_stage_io_dptReq_0_bits_alu_isa_srl; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_srlw <= iss_stage_io_dptReq_0_bits_alu_isa_srlw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_sra <= iss_stage_io_dptReq_0_bits_alu_isa_sra; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_sraw <= iss_stage_io_dptReq_0_bits_alu_isa_sraw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_or <= iss_stage_io_dptReq_0_bits_alu_isa_or; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_and <= iss_stage_io_dptReq_0_bits_alu_isa_and; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_alu_isa_wfi <= iss_stage_io_dptReq_0_bits_alu_isa_wfi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_bru_isa_jal <= iss_stage_io_dptReq_0_bits_bru_isa_jal; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_bru_isa_jalr <= iss_stage_io_dptReq_0_bits_bru_isa_jalr; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_bru_isa_beq <= iss_stage_io_dptReq_0_bits_bru_isa_beq; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_bru_isa_bne <= iss_stage_io_dptReq_0_bits_bru_isa_bne; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_bru_isa_blt <= iss_stage_io_dptReq_0_bits_bru_isa_blt; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_bru_isa_bge <= iss_stage_io_dptReq_0_bits_bru_isa_bge; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_bru_isa_bltu <= iss_stage_io_dptReq_0_bits_bru_isa_bltu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_bru_isa_bgeu <= iss_stage_io_dptReq_0_bits_bru_isa_bgeu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_lb <= iss_stage_io_dptReq_0_bits_lsu_isa_lb; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_lh <= iss_stage_io_dptReq_0_bits_lsu_isa_lh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_lw <= iss_stage_io_dptReq_0_bits_lsu_isa_lw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_ld <= iss_stage_io_dptReq_0_bits_lsu_isa_ld; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_lbu <= iss_stage_io_dptReq_0_bits_lsu_isa_lbu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_lhu <= iss_stage_io_dptReq_0_bits_lsu_isa_lhu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_lwu <= iss_stage_io_dptReq_0_bits_lsu_isa_lwu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_sb <= iss_stage_io_dptReq_0_bits_lsu_isa_sb; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_sh <= iss_stage_io_dptReq_0_bits_lsu_isa_sh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_sw <= iss_stage_io_dptReq_0_bits_lsu_isa_sw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_sd <= iss_stage_io_dptReq_0_bits_lsu_isa_sd; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_fence <= iss_stage_io_dptReq_0_bits_lsu_isa_fence; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_fence_i <= iss_stage_io_dptReq_0_bits_lsu_isa_fence_i; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_sfence_vma <= iss_stage_io_dptReq_0_bits_lsu_isa_sfence_vma; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_lr_w <= iss_stage_io_dptReq_0_bits_lsu_isa_lr_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_sc_w <= iss_stage_io_dptReq_0_bits_lsu_isa_sc_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoswap_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoswap_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoadd_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoadd_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoxor_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoxor_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoand_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoand_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoor_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amoor_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amomin_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amomin_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amomax_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amomax_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amominu_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amominu_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amomaxu_w <= iss_stage_io_dptReq_0_bits_lsu_isa_amomaxu_w; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_lr_d <= iss_stage_io_dptReq_0_bits_lsu_isa_lr_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_sc_d <= iss_stage_io_dptReq_0_bits_lsu_isa_sc_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoswap_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoswap_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoadd_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoadd_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoxor_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoxor_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoand_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoand_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amoor_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amoor_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amomin_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amomin_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amomax_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amomax_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amominu_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amominu_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_amomaxu_d <= iss_stage_io_dptReq_0_bits_lsu_isa_amomaxu_d; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_flw <= iss_stage_io_dptReq_0_bits_lsu_isa_flw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_fsw <= iss_stage_io_dptReq_0_bits_lsu_isa_fsw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_fld <= iss_stage_io_dptReq_0_bits_lsu_isa_fld; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_lsu_isa_fsd <= iss_stage_io_dptReq_0_bits_lsu_isa_fsd; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_csr_isa_rw <= iss_stage_io_dptReq_0_bits_csr_isa_rw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_csr_isa_rs <= iss_stage_io_dptReq_0_bits_csr_isa_rs; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_csr_isa_rc <= iss_stage_io_dptReq_0_bits_csr_isa_rc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_csr_isa_rwi <= iss_stage_io_dptReq_0_bits_csr_isa_rwi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_csr_isa_rsi <= iss_stage_io_dptReq_0_bits_csr_isa_rsi; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_csr_isa_rci <= iss_stage_io_dptReq_0_bits_csr_isa_rci; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_mul <= iss_stage_io_dptReq_0_bits_mul_isa_mul; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_mulh <= iss_stage_io_dptReq_0_bits_mul_isa_mulh; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_mulhsu <= iss_stage_io_dptReq_0_bits_mul_isa_mulhsu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_mulhu <= iss_stage_io_dptReq_0_bits_mul_isa_mulhu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_div <= iss_stage_io_dptReq_0_bits_mul_isa_div; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_divu <= iss_stage_io_dptReq_0_bits_mul_isa_divu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_rem <= iss_stage_io_dptReq_0_bits_mul_isa_rem; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_remu <= iss_stage_io_dptReq_0_bits_mul_isa_remu; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_mulw <= iss_stage_io_dptReq_0_bits_mul_isa_mulw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_divw <= iss_stage_io_dptReq_0_bits_mul_isa_divw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_divuw <= iss_stage_io_dptReq_0_bits_mul_isa_divuw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_remw <= iss_stage_io_dptReq_0_bits_mul_isa_remw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_mul_isa_remuw <= iss_stage_io_dptReq_0_bits_mul_isa_remuw; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_param_is_rvc <= iss_stage_io_dptReq_0_bits_param_is_rvc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_param_pc <= iss_stage_io_dptReq_0_bits_param_pc; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_param_imm <= iss_stage_io_dptReq_0_bits_param_imm; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_param_raw_rs1 <= iss_stage_io_dptReq_0_bits_param_raw_rs1; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_phy_rs1 <= iss_stage_io_dptReq_0_bits_phy_rs1; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_phy_rs2 <= iss_stage_io_dptReq_0_bits_phy_rs2; // @[Issue.scala 90:28]
        end
      end
    end
    if (!(iss_stage_io_flush)) begin // @[Issue.scala 86:22]
      if (iss_stage__T) begin // @[Issue.scala 88:38]
        if (iss_stage_entrySel_0) begin // @[Issue.scala 90:28]
          iss_stage_bufInfo_1_phy_rd0 <= iss_stage_io_dptReq_0_bits_phy_rd0; // @[Issue.scala 90:28]
        end
      end
    end
    if (iss_stage_io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      iss_stage_isOpReady_0_0 <= iss_stage__GEN_1764;
    end else if (iss_stage__T) begin // @[Issue.scala 120:31]
      if (iss_stage__T_3) begin // @[Issue.scala 121:58]
        iss_stage_isOpReady_0_0 <= iss_stage__GEN_1200;
      end else if (~iss_stage_entrySel_0) begin // @[Issue.scala 125:36]
        iss_stage_isOpReady_0_0 <= 1'h0; // @[Issue.scala 125:36]
      end
    end
    if (iss_stage_io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      iss_stage_isOpReady_0_1 <= iss_stage__GEN_1766;
    end else if (iss_stage__T) begin // @[Issue.scala 120:31]
      if (iss_stage__T_4) begin // @[Issue.scala 127:58]
        iss_stage_isOpReady_0_1 <= iss_stage__GEN_1210;
      end else if (~iss_stage_entrySel_0) begin // @[Issue.scala 131:36]
        iss_stage_isOpReady_0_1 <= 1'h0; // @[Issue.scala 131:36]
      end
    end
    if (iss_stage_io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      iss_stage_isOpReady_1_0 <= iss_stage__GEN_1768;
    end else if (iss_stage__T) begin // @[Issue.scala 120:31]
      if (iss_stage__T_3) begin // @[Issue.scala 121:58]
        iss_stage_isOpReady_1_0 <= iss_stage__GEN_1201;
      end else if (iss_stage_entrySel_0) begin // @[Issue.scala 125:36]
        iss_stage_isOpReady_1_0 <= 1'h0; // @[Issue.scala 125:36]
      end
    end
    if (iss_stage_io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      iss_stage_isOpReady_1_1 <= iss_stage__GEN_1770;
    end else if (iss_stage__T) begin // @[Issue.scala 120:31]
      if (iss_stage__T_4) begin // @[Issue.scala 127:58]
        iss_stage_isOpReady_1_1 <= iss_stage__GEN_1211;
      end else if (iss_stage_entrySel_0) begin // @[Issue.scala 131:36]
        iss_stage_isOpReady_1_1 <= 1'h0; // @[Issue.scala 131:36]
      end
    end
    if (iss_stage_io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      if (iss_stage__T_248) begin // @[Issue.scala 489:98]
        iss_stage_bufOperator_0_0 <= {{1'd0}, iss_stage_io_irgRsp_0_bits_op}; // @[Issue.scala 492:32]
      end else begin
        iss_stage_bufOperator_0_0 <= iss_stage__GEN_1232;
      end
    end else begin
      iss_stage_bufOperator_0_0 <= iss_stage__GEN_1232;
    end
    if (iss_stage_io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      if (iss_stage__T_253) begin // @[Issue.scala 489:98]
        iss_stage_bufOperator_0_1 <= {{1'd0}, iss_stage_io_irgRsp_0_bits_op}; // @[Issue.scala 492:32]
      end else begin
        iss_stage_bufOperator_0_1 <= iss_stage__GEN_1236;
      end
    end else begin
      iss_stage_bufOperator_0_1 <= iss_stage__GEN_1236;
    end
    if (iss_stage_io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      if (iss_stage__T_258) begin // @[Issue.scala 489:98]
        iss_stage_bufOperator_1_0 <= {{1'd0}, iss_stage_io_irgRsp_0_bits_op}; // @[Issue.scala 492:32]
      end else begin
        iss_stage_bufOperator_1_0 <= iss_stage__GEN_1233;
      end
    end else begin
      iss_stage_bufOperator_1_0 <= iss_stage__GEN_1233;
    end
    if (iss_stage_io_irgRsp_0_valid) begin // @[Issue.scala 486:33]
      if (iss_stage__T_263) begin // @[Issue.scala 489:98]
        iss_stage_bufOperator_1_1 <= {{1'd0}, iss_stage_io_irgRsp_0_bits_op}; // @[Issue.scala 492:32]
      end else begin
        iss_stage_bufOperator_1_1 <= iss_stage__GEN_1237;
      end
    end else begin
      iss_stage_bufOperator_1_1 <= iss_stage__GEN_1237;
    end
    if (iss_stage__T) begin // @[Issue.scala 170:31]
      if (~iss_stage_entrySel_0) begin // @[Issue.scala 172:44]
        iss_stage_ageMatrixW_0_0 <= 1'h0; // @[Issue.scala 172:44]
      end else begin
        iss_stage_ageMatrixW_0_0 <= iss_stage__GEN_1242;
      end
    end
    if (iss_stage__T) begin // @[Issue.scala 170:31]
      if (iss_stage_entrySel_0) begin // @[Issue.scala 172:44]
        iss_stage_ageMatrixW_0_1 <= 1'h0; // @[Issue.scala 172:44]
      end else begin
        iss_stage_ageMatrixW_0_1 <= iss_stage__GEN_1244;
      end
    end
    if (iss_stage__T) begin // @[Issue.scala 170:31]
      if (iss_stage_entrySel_0) begin // @[Issue.scala 172:44]
        iss_stage_ageMatrixW_1_1 <= 1'h0; // @[Issue.scala 172:44]
      end else begin
        iss_stage_ageMatrixW_1_1 <= iss_stage__GEN_1245;
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_54) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:276 assert(\n"); // @[Issue.scala 276:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_51 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 276:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_102) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:281 assert(\n"); // @[Issue.scala 281:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_99 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 281:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_150) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:412 assert(\n"); // @[Issue.scala 412:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_147 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 412:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_198) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:417 assert(\n"); // @[Issue.scala 417:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_195 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 417:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_246) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:422 assert(\n"); // @[Issue.scala 422:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_243 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 422:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_315) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:627 assert(\n"); // @[Issue.scala 627:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_312 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 627:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_318 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:642 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 642:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_0_T_33 & (iss_stage__T_318 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 642:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_258 & iss_stage__entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:643 assert( bufValid(i) )\n"); // @[Issue.scala 643:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_0 & (iss_stage__T_318 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 643:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_258 & iss_stage__maskCondAluIss_0_0_T_31) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:644 assert( bufInfo(i).alu_isa.is_alu )\n"); // @[Issue.scala 644:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_0_T_30 & (iss_stage__T_318 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 644:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_361 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:642 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 642:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_1_T_33 & (iss_stage__T_361 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 642:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_261 & iss_stage__io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:643 assert( bufValid(i) )\n"); // @[Issue.scala 643:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_1 & (iss_stage__T_361 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 643:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_261 & iss_stage__maskCondAluIss_0_1_T_31) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:644 assert( bufInfo(i).alu_isa.is_alu )\n"); // @[Issue.scala 644:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_1_T_30 & (iss_stage__T_361 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 644:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_426) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:692 assert(\n"); // @[Issue.scala 692:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_423 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 692:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_429 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:707 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 707:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_0_T_33 & (iss_stage__T_429 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 707:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_264 & iss_stage__entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:708 assert( bufValid(i) )\n"); // @[Issue.scala 708:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_0 & (iss_stage__T_429 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 708:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_264 & iss_stage__maskCondMulIss_0_0_T_13) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:709 assert( bufInfo(i).mul_isa.is_mulDiv )\n"); // @[Issue.scala 709:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondMulIss_0_0_T_12 & (iss_stage__T_429 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 709:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_454 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:707 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 707:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_1_T_33 & (iss_stage__T_454 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 707:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_267 & iss_stage__io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:708 assert( bufValid(i) )\n"); // @[Issue.scala 708:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_1 & (iss_stage__T_454 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 708:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_267 & iss_stage__maskCondMulIss_0_1_T_13) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:709 assert( bufInfo(i).mul_isa.is_mulDiv )\n"); // @[Issue.scala 709:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondMulIss_0_1_T_12 & (iss_stage__T_454 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 709:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_501) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:757 assert(\n"); // @[Issue.scala 757:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_498 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 757:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_504 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:773 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 773:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_0_T_33 & (iss_stage__T_504 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 773:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_270 & iss_stage__entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:774 assert( bufValid(i) )\n"); // @[Issue.scala 774:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_0 & (iss_stage__T_504 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 774:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_270 & iss_stage__maskCondBruIss_0_T_8) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:775 assert( bufInfo(i).bru_isa.is_bru )\n"); // @[Issue.scala 775:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondBruIss_0_T_7 & (iss_stage__T_504 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 775:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_524 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:773 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 773:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_1_T_33 & (iss_stage__T_524 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 773:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_273 & iss_stage__io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:774 assert( bufValid(i) )\n"); // @[Issue.scala 774:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_1 & (iss_stage__T_524 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 774:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_273 & iss_stage__maskCondBruIss_1_T_8) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:775 assert( bufInfo(i).bru_isa.is_bru )\n"); // @[Issue.scala 775:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondBruIss_1_T_7 & (iss_stage__T_524 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 775:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_566) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:823 assert(\n"); // @[Issue.scala 823:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_563 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 823:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_569 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:839 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 839:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_0_T_33 & (iss_stage__T_569 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 839:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_276 & iss_stage__entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:840 assert( bufValid(i) )\n"); // @[Issue.scala 840:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_0 & (iss_stage__T_569 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 840:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_276 & iss_stage__maskCondCsrIss_0_T_6) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:841 assert( bufInfo(i).csr_isa.is_csr )\n"); // @[Issue.scala 841:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondCsrIss_0_T_5 & (iss_stage__T_569 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 841:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_587 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:839 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 839:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_1_T_33 & (iss_stage__T_587 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 839:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_279 & iss_stage__io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:840 assert( bufValid(i) )\n"); // @[Issue.scala 840:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_1 & (iss_stage__T_587 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 840:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_279 & iss_stage__maskCondCsrIss_1_T_6) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:841 assert( bufInfo(i).csr_isa.is_csr )\n"); // @[Issue.scala 841:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondCsrIss_1_T_5 & (iss_stage__T_587 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 841:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_53 & iss_stage__T_627) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:886 assert(\n"); // @[Issue.scala 886:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__T_624 & iss_stage__T_53) begin
          $fatal; // @[Issue.scala 886:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_630 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_0_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:902 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 902:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_0_T_33 & (iss_stage__T_630 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 902:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_282 & iss_stage__entrySel_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:903 assert( bufValid(i) )\n"); // @[Issue.scala 903:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_0 & (iss_stage__T_630 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 903:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_282 & iss_stage__maskCondLsuIss_0_T_42) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:904 assert( bufInfo(i).lsu_isa.is_lsu )\n"); // @[Issue.scala 904:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondLsuIss_0_T_41 & (iss_stage__T_630 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 904:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iss_stage__T_684 & iss_stage__T_53 & iss_stage__maskCondAluIss_0_1_T_34) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Issue.scala:902 assert( postIsOpReady(i)(0) & postIsOpReady(i)(1) )\n"); // @[Issue.scala 902:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondAluIss_0_1_T_33 & (iss_stage__T_684 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 902:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_285 & iss_stage__io_dptReq_0_ready_T_1) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:903 assert( bufValid(i) )\n"); // @[Issue.scala 903:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage_bufValid_1 & (iss_stage__T_684 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 903:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_285 & iss_stage__maskCondLsuIss_1_T_42) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Issue.scala:904 assert( bufInfo(i).lsu_isa.is_lsu )\n"); // @[Issue.scala 904:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iss_stage__maskCondLsuIss_1_T_41 & (iss_stage__T_684 & iss_stage__T_53)) begin
          $fatal; // @[Issue.scala 904:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_clock) begin
    if (exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_en & exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_mask) begin
      exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0[exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_addr] <=
        exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_clock) begin
    if (exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_en & exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_mask) begin
      exe_stage_alu_0_alu_exe_iwb_fifo_ram_res[exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_addr] <=
        exe_stage_alu_0_alu_exe_iwb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_alu_0_alu_exe_iwb_fifo_clock) begin
    if (exe_stage_alu_0_alu_exe_iwb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_alu_0_alu_exe_iwb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_alu_0_alu_exe_iwb_fifo__T) begin // @[Decoupled.scala 295:27]
      exe_stage_alu_0_alu_exe_iwb_fifo_maybe_full <= exe_stage_alu_0_alu_exe_iwb_fifo__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_clock) begin
    if (exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_en & exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_mask) begin
      exe_stage_bru_bru_exe_iwb_fifo_ram_rd0[exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_addr] <=
        exe_stage_bru_bru_exe_iwb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_bru_exe_iwb_fifo_ram_res_clock) begin
    if (exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_en & exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_mask) begin
      exe_stage_bru_bru_exe_iwb_fifo_ram_res[exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_addr] <=
        exe_stage_bru_bru_exe_iwb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_bru_exe_iwb_fifo_clock) begin
    if (exe_stage_bru_bru_exe_iwb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_bru_bru_exe_iwb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_bru_bru_exe_iwb_fifo__T) begin // @[Decoupled.scala 295:27]
      exe_stage_bru_bru_exe_iwb_fifo_maybe_full <= exe_stage_bru_bru_exe_iwb_fifo__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_bru_bctq_ram_pc_clock) begin
    if (exe_stage_bru_bctq_ram_pc_MPORT_en & exe_stage_bru_bctq_ram_pc_MPORT_mask) begin
      exe_stage_bru_bctq_ram_pc[exe_stage_bru_bctq_ram_pc_MPORT_addr] <= exe_stage_bru_bctq_ram_pc_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_bctq_ram_bimResp_bim_p_clock) begin
    if (exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_en & exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_mask) begin
      exe_stage_bru_bctq_ram_bimResp_bim_p[exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_addr] <=
        exe_stage_bru_bctq_ram_bimResp_bim_p_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_bctq_ram_bimResp_bim_h_clock) begin
    if (exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_en & exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_mask) begin
      exe_stage_bru_bctq_ram_bimResp_bim_h[exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_addr] <=
        exe_stage_bru_bctq_ram_bimResp_bim_h_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_bctq_ram_isPredictTaken_clock) begin
    if (exe_stage_bru_bctq_ram_isPredictTaken_MPORT_en & exe_stage_bru_bctq_ram_isPredictTaken_MPORT_mask) begin
      exe_stage_bru_bctq_ram_isPredictTaken[exe_stage_bru_bctq_ram_isPredictTaken_MPORT_addr] <=
        exe_stage_bru_bctq_ram_isPredictTaken_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_bctq_ram_isFinalTaken_clock) begin
    if (exe_stage_bru_bctq_ram_isFinalTaken_MPORT_en & exe_stage_bru_bctq_ram_isFinalTaken_MPORT_mask) begin
      exe_stage_bru_bctq_ram_isFinalTaken[exe_stage_bru_bctq_ram_isFinalTaken_MPORT_addr] <=
        exe_stage_bru_bctq_ram_isFinalTaken_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_bctq_ram_finalTarget_clock) begin
    if (exe_stage_bru_bctq_ram_finalTarget_MPORT_en & exe_stage_bru_bctq_ram_finalTarget_MPORT_mask) begin
      exe_stage_bru_bctq_ram_finalTarget[exe_stage_bru_bctq_ram_finalTarget_MPORT_addr] <=
        exe_stage_bru_bctq_ram_finalTarget_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_bctq_clock) begin
    if (exe_stage_bru_bctq_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_bru_bctq_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_bru_bctq__T) begin // @[Decoupled.scala 295:27]
      exe_stage_bru_bctq_maybe_full <= exe_stage_bru_bctq__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_bru_jctq_ram_pc_clock) begin
    if (exe_stage_bru_jctq_ram_pc_MPORT_en & exe_stage_bru_jctq_ram_pc_MPORT_mask) begin
      exe_stage_bru_jctq_ram_pc[exe_stage_bru_jctq_ram_pc_MPORT_addr] <= exe_stage_bru_jctq_ram_pc_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_jctq_ram_btbResp_target_clock) begin
    if (exe_stage_bru_jctq_ram_btbResp_target_MPORT_en & exe_stage_bru_jctq_ram_btbResp_target_MPORT_mask) begin
      exe_stage_bru_jctq_ram_btbResp_target[exe_stage_bru_jctq_ram_btbResp_target_MPORT_addr] <=
        exe_stage_bru_jctq_ram_btbResp_target_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_jctq_ram_rasResp_target_clock) begin
    if (exe_stage_bru_jctq_ram_rasResp_target_MPORT_en & exe_stage_bru_jctq_ram_rasResp_target_MPORT_mask) begin
      exe_stage_bru_jctq_ram_rasResp_target[exe_stage_bru_jctq_ram_rasResp_target_MPORT_addr] <=
        exe_stage_bru_jctq_ram_rasResp_target_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_jctq_ram_isRas_clock) begin
    if (exe_stage_bru_jctq_ram_isRas_MPORT_en & exe_stage_bru_jctq_ram_isRas_MPORT_mask) begin
      exe_stage_bru_jctq_ram_isRas[exe_stage_bru_jctq_ram_isRas_MPORT_addr] <= exe_stage_bru_jctq_ram_isRas_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_jctq_ram_finalTarget_clock) begin
    if (exe_stage_bru_jctq_ram_finalTarget_MPORT_en & exe_stage_bru_jctq_ram_finalTarget_MPORT_mask) begin
      exe_stage_bru_jctq_ram_finalTarget[exe_stage_bru_jctq_ram_finalTarget_MPORT_addr] <=
        exe_stage_bru_jctq_ram_finalTarget_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_bru_jctq_clock) begin
    if (exe_stage_bru_jctq_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_bru_jctq_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_bru_jctq__T) begin // @[Decoupled.scala 295:27]
      exe_stage_bru_jctq_maybe_full <= exe_stage_bru_jctq__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_bru_clock) begin
    if (exe_stage_bru_reset) begin // @[Bru.scala 50:34]
      exe_stage_bru_misPredict_locker <= 1'h0; // @[Bru.scala 50:34]
    end else if (exe_stage_bru_io_flush) begin // @[Bru.scala 95:20]
      exe_stage_bru_misPredict_locker <= 1'h0; // @[Bru.scala 96:23]
    end else begin
      exe_stage_bru_misPredict_locker <= exe_stage_bru__GEN_0;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_bru__T_14 & exe_stage_bru__T_15) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Bru.scala:124 assert( jctq.io.enq.fire === (io.bru_iss_exe.fire & io.bru_iss_exe.bits.fun.jalr) )\n"
            ); // @[Bru.scala 124:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_bru__T_12 & exe_stage_bru__T_14) begin
          $fatal; // @[Bru.scala 124:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_bru__T_14 & exe_stage_bru__T_21) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Bru.scala:125 assert( io.jftq.fire === jctq.io.enq.fire )\n"); // @[Bru.scala 125:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_bru__T_18 & exe_stage_bru__T_14) begin
          $fatal; // @[Bru.scala 125:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_bru__T_14 & exe_stage_bru__T_33) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Bru.scala:126 assert( bctq.io.enq.fire === (io.bru_iss_exe.fire & io.bru_iss_exe.bits.fun.is_branch)  )\n"
            ); // @[Bru.scala 126:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_bru__T_30 & exe_stage_bru__T_14) begin
          $fatal; // @[Bru.scala 126:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_bru__T_14 & exe_stage_bru__T_39) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Bru.scala:127 assert( io.bftq.fire === bctq.io.enq.fire )\n"); // @[Bru.scala 127:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_bru__T_36 & exe_stage_bru__T_14) begin
          $fatal; // @[Bru.scala 127:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_bru__T_14 & exe_stage_bru__T_45) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Bru.scala:128 assert( io.bru_iss_exe.fire === bru_exe_iwb_fifo.io.enq.fire )\n"); // @[Bru.scala 128:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_bru__T_42 & exe_stage_bru__T_14) begin
          $fatal; // @[Bru.scala 128:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_lsu_stQueue_clock) begin
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_lb <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_lb <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_lb <= exe_stage_lsu_stQueue__GEN_270;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_lb <= exe_stage_lsu_stQueue__GEN_270;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_lh <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_lh <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_lh <= exe_stage_lsu_stQueue__GEN_272;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_lh <= exe_stage_lsu_stQueue__GEN_272;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_lw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_lw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_lw <= exe_stage_lsu_stQueue__GEN_274;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_lw <= exe_stage_lsu_stQueue__GEN_274;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_ld <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_ld <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_ld <= exe_stage_lsu_stQueue__GEN_276;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_ld <= exe_stage_lsu_stQueue__GEN_276;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_lbu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_lbu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_lbu <= exe_stage_lsu_stQueue__GEN_278;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_lbu <= exe_stage_lsu_stQueue__GEN_278;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_lhu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_lhu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_lhu <= exe_stage_lsu_stQueue__GEN_280;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_lhu <= exe_stage_lsu_stQueue__GEN_280;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_lwu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_lwu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_lwu <= exe_stage_lsu_stQueue__GEN_282;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_lwu <= exe_stage_lsu_stQueue__GEN_282;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_sb <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_sb <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_sb <= exe_stage_lsu_stQueue__GEN_284;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_sb <= exe_stage_lsu_stQueue__GEN_284;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_sh <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_sh <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_sh <= exe_stage_lsu_stQueue__GEN_286;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_sh <= exe_stage_lsu_stQueue__GEN_286;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_sw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_sw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_sw <= exe_stage_lsu_stQueue__GEN_288;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_sw <= exe_stage_lsu_stQueue__GEN_288;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_sd <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_sd <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_sd <= exe_stage_lsu_stQueue__GEN_290;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_sd <= exe_stage_lsu_stQueue__GEN_290;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_lr_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_lr_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_lr_w <= exe_stage_lsu_stQueue__GEN_298;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_lr_w <= exe_stage_lsu_stQueue__GEN_298;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_sc_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_sc_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_sc_w <= exe_stage_lsu_stQueue__GEN_300;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_sc_w <= exe_stage_lsu_stQueue__GEN_300;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoswap_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoswap_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoswap_w <= exe_stage_lsu_stQueue__GEN_302;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoswap_w <= exe_stage_lsu_stQueue__GEN_302;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoadd_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoadd_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoadd_w <= exe_stage_lsu_stQueue__GEN_304;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoadd_w <= exe_stage_lsu_stQueue__GEN_304;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoxor_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoxor_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoxor_w <= exe_stage_lsu_stQueue__GEN_306;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoxor_w <= exe_stage_lsu_stQueue__GEN_306;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoand_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoand_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoand_w <= exe_stage_lsu_stQueue__GEN_308;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoand_w <= exe_stage_lsu_stQueue__GEN_308;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoor_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoor_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoor_w <= exe_stage_lsu_stQueue__GEN_310;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoor_w <= exe_stage_lsu_stQueue__GEN_310;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amomin_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amomin_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amomin_w <= exe_stage_lsu_stQueue__GEN_312;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amomin_w <= exe_stage_lsu_stQueue__GEN_312;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amomax_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amomax_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amomax_w <= exe_stage_lsu_stQueue__GEN_314;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amomax_w <= exe_stage_lsu_stQueue__GEN_314;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amominu_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amominu_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amominu_w <= exe_stage_lsu_stQueue__GEN_316;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amominu_w <= exe_stage_lsu_stQueue__GEN_316;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w <= exe_stage_lsu_stQueue__GEN_318;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w <= exe_stage_lsu_stQueue__GEN_318;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_lr_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_lr_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_lr_d <= exe_stage_lsu_stQueue__GEN_320;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_lr_d <= exe_stage_lsu_stQueue__GEN_320;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_sc_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_sc_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_sc_d <= exe_stage_lsu_stQueue__GEN_322;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_sc_d <= exe_stage_lsu_stQueue__GEN_322;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoswap_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoswap_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoswap_d <= exe_stage_lsu_stQueue__GEN_324;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoswap_d <= exe_stage_lsu_stQueue__GEN_324;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoadd_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoadd_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoadd_d <= exe_stage_lsu_stQueue__GEN_326;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoadd_d <= exe_stage_lsu_stQueue__GEN_326;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoxor_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoxor_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoxor_d <= exe_stage_lsu_stQueue__GEN_328;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoxor_d <= exe_stage_lsu_stQueue__GEN_328;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoand_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoand_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoand_d <= exe_stage_lsu_stQueue__GEN_330;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoand_d <= exe_stage_lsu_stQueue__GEN_330;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amoor_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amoor_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amoor_d <= exe_stage_lsu_stQueue__GEN_332;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amoor_d <= exe_stage_lsu_stQueue__GEN_332;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amomin_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amomin_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amomin_d <= exe_stage_lsu_stQueue__GEN_334;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amomin_d <= exe_stage_lsu_stQueue__GEN_334;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amomax_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amomax_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amomax_d <= exe_stage_lsu_stQueue__GEN_336;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amomax_d <= exe_stage_lsu_stQueue__GEN_336;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amominu_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amominu_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amominu_d <= exe_stage_lsu_stQueue__GEN_338;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amominu_d <= exe_stage_lsu_stQueue__GEN_338;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d <= exe_stage_lsu_stQueue__GEN_340;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d <= exe_stage_lsu_stQueue__GEN_340;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_flw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_flw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_flw <= exe_stage_lsu_stQueue__GEN_342;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_flw <= exe_stage_lsu_stQueue__GEN_342;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_fsw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_fsw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_fsw <= exe_stage_lsu_stQueue__GEN_344;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_fsw <= exe_stage_lsu_stQueue__GEN_344;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_fld <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_fld <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_fld <= exe_stage_lsu_stQueue__GEN_346;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_fld <= exe_stage_lsu_stQueue__GEN_346;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_fun_fsd <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_fun_fsd <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_fun_fsd <= exe_stage_lsu_stQueue__GEN_348;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_fun_fsd <= exe_stage_lsu_stQueue__GEN_348;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_param_rd0 <= 6'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_param_rd0 <= 6'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_param_rd0 <= exe_stage_lsu_stQueue__GEN_350;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_param_rd0 <= exe_stage_lsu_stQueue__GEN_350;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_param_dat_op1 <= 64'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_param_dat_op1 <= 64'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_param_dat_op1 <= exe_stage_lsu_stQueue__GEN_352;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_param_dat_op1 <= exe_stage_lsu_stQueue__GEN_352;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_0_param_dat_op2 <= 64'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (~exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_0_param_dat_op2 <= 64'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_0_param_dat_op2 <= exe_stage_lsu_stQueue__GEN_354;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_0_param_dat_op2 <= exe_stage_lsu_stQueue__GEN_354;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_lb <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_lb <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_lb <= exe_stage_lsu_stQueue__GEN_271;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_lb <= exe_stage_lsu_stQueue__GEN_271;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_lh <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_lh <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_lh <= exe_stage_lsu_stQueue__GEN_273;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_lh <= exe_stage_lsu_stQueue__GEN_273;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_lw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_lw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_lw <= exe_stage_lsu_stQueue__GEN_275;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_lw <= exe_stage_lsu_stQueue__GEN_275;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_ld <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_ld <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_ld <= exe_stage_lsu_stQueue__GEN_277;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_ld <= exe_stage_lsu_stQueue__GEN_277;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_lbu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_lbu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_lbu <= exe_stage_lsu_stQueue__GEN_279;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_lbu <= exe_stage_lsu_stQueue__GEN_279;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_lhu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_lhu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_lhu <= exe_stage_lsu_stQueue__GEN_281;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_lhu <= exe_stage_lsu_stQueue__GEN_281;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_lwu <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_lwu <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_lwu <= exe_stage_lsu_stQueue__GEN_283;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_lwu <= exe_stage_lsu_stQueue__GEN_283;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_sb <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_sb <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_sb <= exe_stage_lsu_stQueue__GEN_285;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_sb <= exe_stage_lsu_stQueue__GEN_285;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_sh <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_sh <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_sh <= exe_stage_lsu_stQueue__GEN_287;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_sh <= exe_stage_lsu_stQueue__GEN_287;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_sw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_sw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_sw <= exe_stage_lsu_stQueue__GEN_289;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_sw <= exe_stage_lsu_stQueue__GEN_289;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_sd <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_sd <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_sd <= exe_stage_lsu_stQueue__GEN_291;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_sd <= exe_stage_lsu_stQueue__GEN_291;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_lr_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_lr_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_lr_w <= exe_stage_lsu_stQueue__GEN_299;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_lr_w <= exe_stage_lsu_stQueue__GEN_299;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_sc_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_sc_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_sc_w <= exe_stage_lsu_stQueue__GEN_301;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_sc_w <= exe_stage_lsu_stQueue__GEN_301;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoswap_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoswap_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoswap_w <= exe_stage_lsu_stQueue__GEN_303;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoswap_w <= exe_stage_lsu_stQueue__GEN_303;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoadd_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoadd_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoadd_w <= exe_stage_lsu_stQueue__GEN_305;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoadd_w <= exe_stage_lsu_stQueue__GEN_305;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoxor_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoxor_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoxor_w <= exe_stage_lsu_stQueue__GEN_307;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoxor_w <= exe_stage_lsu_stQueue__GEN_307;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoand_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoand_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoand_w <= exe_stage_lsu_stQueue__GEN_309;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoand_w <= exe_stage_lsu_stQueue__GEN_309;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoor_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoor_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoor_w <= exe_stage_lsu_stQueue__GEN_311;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoor_w <= exe_stage_lsu_stQueue__GEN_311;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amomin_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amomin_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amomin_w <= exe_stage_lsu_stQueue__GEN_313;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amomin_w <= exe_stage_lsu_stQueue__GEN_313;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amomax_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amomax_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amomax_w <= exe_stage_lsu_stQueue__GEN_315;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amomax_w <= exe_stage_lsu_stQueue__GEN_315;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amominu_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amominu_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amominu_w <= exe_stage_lsu_stQueue__GEN_317;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amominu_w <= exe_stage_lsu_stQueue__GEN_317;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w <= exe_stage_lsu_stQueue__GEN_319;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w <= exe_stage_lsu_stQueue__GEN_319;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_lr_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_lr_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_lr_d <= exe_stage_lsu_stQueue__GEN_321;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_lr_d <= exe_stage_lsu_stQueue__GEN_321;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_sc_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_sc_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_sc_d <= exe_stage_lsu_stQueue__GEN_323;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_sc_d <= exe_stage_lsu_stQueue__GEN_323;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoswap_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoswap_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoswap_d <= exe_stage_lsu_stQueue__GEN_325;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoswap_d <= exe_stage_lsu_stQueue__GEN_325;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoadd_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoadd_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoadd_d <= exe_stage_lsu_stQueue__GEN_327;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoadd_d <= exe_stage_lsu_stQueue__GEN_327;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoxor_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoxor_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoxor_d <= exe_stage_lsu_stQueue__GEN_329;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoxor_d <= exe_stage_lsu_stQueue__GEN_329;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoand_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoand_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoand_d <= exe_stage_lsu_stQueue__GEN_331;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoand_d <= exe_stage_lsu_stQueue__GEN_331;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amoor_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amoor_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amoor_d <= exe_stage_lsu_stQueue__GEN_333;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amoor_d <= exe_stage_lsu_stQueue__GEN_333;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amomin_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amomin_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amomin_d <= exe_stage_lsu_stQueue__GEN_335;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amomin_d <= exe_stage_lsu_stQueue__GEN_335;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amomax_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amomax_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amomax_d <= exe_stage_lsu_stQueue__GEN_337;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amomax_d <= exe_stage_lsu_stQueue__GEN_337;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amominu_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amominu_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amominu_d <= exe_stage_lsu_stQueue__GEN_339;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amominu_d <= exe_stage_lsu_stQueue__GEN_339;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d <= exe_stage_lsu_stQueue__GEN_341;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d <= exe_stage_lsu_stQueue__GEN_341;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_flw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_flw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_flw <= exe_stage_lsu_stQueue__GEN_343;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_flw <= exe_stage_lsu_stQueue__GEN_343;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_fsw <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_fsw <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_fsw <= exe_stage_lsu_stQueue__GEN_345;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_fsw <= exe_stage_lsu_stQueue__GEN_345;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_fld <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_fld <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_fld <= exe_stage_lsu_stQueue__GEN_347;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_fld <= exe_stage_lsu_stQueue__GEN_347;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_fun_fsd <= 1'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_fun_fsd <= 1'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_fun_fsd <= exe_stage_lsu_stQueue__GEN_349;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_fun_fsd <= exe_stage_lsu_stQueue__GEN_349;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_param_rd0 <= 6'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_param_rd0 <= 6'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_param_rd0 <= exe_stage_lsu_stQueue__GEN_351;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_param_rd0 <= exe_stage_lsu_stQueue__GEN_351;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_param_dat_op1 <= 64'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_param_dat_op1 <= 64'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_param_dat_op1 <= exe_stage_lsu_stQueue__GEN_353;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_param_dat_op1 <= exe_stage_lsu_stQueue__GEN_353;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 54:21]
      exe_stage_lsu_stQueue_buff_1_param_dat_op2 <= 64'h0; // @[Store_queue.scala 54:21]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      if (exe_stage_lsu_stQueue_rd_ptr) begin // @[Store_queue.scala 113:18]
        exe_stage_lsu_stQueue_buff_1_param_dat_op2 <= 64'h0; // @[Store_queue.scala 113:18]
      end else begin
        exe_stage_lsu_stQueue_buff_1_param_dat_op2 <= exe_stage_lsu_stQueue__GEN_355;
      end
    end else begin
      exe_stage_lsu_stQueue_buff_1_param_dat_op2 <= exe_stage_lsu_stQueue__GEN_355;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 56:27]
      exe_stage_lsu_stQueue_cm_ptr_reg <= 2'h0; // @[Store_queue.scala 56:27]
    end else if (exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0) begin // @[Store_queue.scala 127:31]
      exe_stage_lsu_stQueue_cm_ptr_reg <= exe_stage_lsu_stQueue__wr_ptr_reg_T_1; // @[Store_queue.scala 128:18]
    end else if (exe_stage_lsu_stQueue__T_1) begin // @[Store_queue.scala 131:44]
      exe_stage_lsu_stQueue_cm_ptr_reg <= exe_stage_lsu_stQueue__wr_ptr_reg_T_1; // @[Store_queue.scala 132:18]
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 57:27]
      exe_stage_lsu_stQueue_wr_ptr_reg <= 2'h0; // @[Store_queue.scala 57:27]
    end else if (exe_stage_lsu_stQueue_io_flush) begin // @[Store_queue.scala 94:20]
      if (exe_stage_lsu_stQueue__T_4) begin // @[Store_queue.scala 100:59]
        exe_stage_lsu_stQueue_wr_ptr_reg <= exe_stage_lsu_stQueue__wr_ptr_reg_T_1; // @[Store_queue.scala 100:72]
      end else begin
        exe_stage_lsu_stQueue_wr_ptr_reg <= exe_stage_lsu_stQueue_cm_ptr_reg; // @[Store_queue.scala 101:30]
      end
    end else if (exe_stage_lsu_stQueue__T_5) begin // @[Store_queue.scala 106:30]
      exe_stage_lsu_stQueue_wr_ptr_reg <= exe_stage_lsu_stQueue__wr_ptr_reg_T_3; // @[Store_queue.scala 108:16]
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 58:27]
      exe_stage_lsu_stQueue_rd_ptr_reg <= 2'h0; // @[Store_queue.scala 58:27]
    end else if (exe_stage_lsu_stQueue__T_6) begin // @[Store_queue.scala 111:23]
      exe_stage_lsu_stQueue_rd_ptr_reg <= exe_stage_lsu_stQueue__rd_ptr_reg_T_1; // @[Store_queue.scala 112:16]
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 69:23]
      exe_stage_lsu_stQueue_is_amo <= 1'h0; // @[Store_queue.scala 69:23]
    end else if (exe_stage_lsu_stQueue_io_flush) begin // @[Store_queue.scala 78:22]
      exe_stage_lsu_stQueue_is_amo <= 1'h0; // @[Store_queue.scala 79:14]
    end else begin
      exe_stage_lsu_stQueue_is_amo <= exe_stage_lsu_stQueue__GEN_1;
    end
    if (exe_stage_lsu_stQueue_reset) begin // @[Store_queue.scala 76:29]
      exe_stage_lsu_stQueue_is_amo_pre <= 1'h0; // @[Store_queue.scala 76:29]
    end else begin
      exe_stage_lsu_stQueue_is_amo_pre <= exe_stage_lsu_stQueue_io_cmm_lsu_is_amo_pending; // @[Store_queue.scala 76:29]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 & exe_stage_lsu_stQueue__T_9 &
          exe_stage_lsu_stQueue__T_10) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:129 assert( ~is_amo )\n"); // @[Store_queue.scala 129:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_stQueue__T_7 & (exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 &
          exe_stage_lsu_stQueue__T_9)) begin
          $fatal; // @[Store_queue.scala 129:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_298 & exe_stage_lsu_stQueue__T_14) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:130 assert( cm_ptr_reg =/= wr_ptr_reg )\n"); // @[Store_queue.scala 130:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_stQueue__T_11 & (exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 &
          exe_stage_lsu_stQueue__T_9)) begin
          $fatal; // @[Store_queue.scala 130:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 & exe_stage_lsu_stQueue__T_1 &
          exe_stage_lsu_stQueue__T_9 & exe_stage_lsu_stQueue__T_23) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, is_amo only launch at chn 0!\n\n    at Store_queue.scala:133 assert( ~((is_st_commited(0)) & (is_amo & ~io.is_empty)), \"Assert Failed, is_amo only launch at chn 0!\\n\" )\n"
            ); // @[Store_queue.scala 133:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_stQueue__T_20 & (~exe_stage_lsu_stQueue_io_cmm_lsu_is_store_commit_0 &
          exe_stage_lsu_stQueue__T_1 & exe_stage_lsu_stQueue__T_9)) begin
          $fatal; // @[Store_queue.scala 133:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_302 & exe_stage_lsu_stQueue__T_14) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:134 assert( cm_ptr_reg =/= wr_ptr_reg )\n"); // @[Store_queue.scala 134:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_stQueue__T_11 & (_GEN_301 & exe_stage_lsu_stQueue__T_9)) begin
          $fatal; // @[Store_queue.scala 134:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_stQueue__T_30 & exe_stage_lsu_stQueue__T_9 & exe_stage_lsu_stQueue__T_34) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:149 assert( rd_ptr >= wr_ptr )\n"); // @[Store_queue.scala 149:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_stQueue__T_31 & (exe_stage_lsu_stQueue__T_30 & exe_stage_lsu_stQueue__T_9)) begin
          $fatal; // @[Store_queue.scala 149:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~exe_stage_lsu_stQueue__T_30 & exe_stage_lsu_stQueue__T_9 & exe_stage_lsu_stQueue__T_90) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Store_queue.scala:162 assert( rd_ptr <= wr_ptr )\n"); // @[Store_queue.scala 162:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_stQueue__T_87 & (~exe_stage_lsu_stQueue__T_30 & exe_stage_lsu_stQueue__T_9)) begin
          $fatal; // @[Store_queue.scala 162:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_lsu_system_clock) begin
    if (exe_stage_lsu_system_reset) begin // @[IO_Lsu.scala 45:27]
      exe_stage_lsu_system_is_busy <= 1'h0; // @[IO_Lsu.scala 45:27]
    end else begin
      exe_stage_lsu_system_is_busy <= exe_stage_lsu_system__GEN_74;
    end
    if (exe_stage_lsu_system_reset) begin // @[IO_Lsu.scala 46:27]
      exe_stage_lsu_system_isTransing <= 1'h0; // @[IO_Lsu.scala 46:27]
    end else if (!(exe_stage_lsu_system__T_24)) begin // @[IO_Lsu.scala 84:23]
      if (exe_stage_lsu_system__T_35) begin // @[IO_Lsu.scala 89:50]
        exe_stage_lsu_system_isTransing <= 1'h0; // @[IO_Lsu.scala 91:16]
      end else begin
        exe_stage_lsu_system_isTransing <= exe_stage_lsu_system__GEN_26;
      end
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_lb <= exe_stage_lsu_system_io_enq_bits_fun_lb; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_lh <= exe_stage_lsu_system_io_enq_bits_fun_lh; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_lw <= exe_stage_lsu_system_io_enq_bits_fun_lw; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_ld <= exe_stage_lsu_system_io_enq_bits_fun_ld; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_lbu <= exe_stage_lsu_system_io_enq_bits_fun_lbu; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_lhu <= exe_stage_lsu_system_io_enq_bits_fun_lhu; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_lwu <= exe_stage_lsu_system_io_enq_bits_fun_lwu; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_sb <= exe_stage_lsu_system_io_enq_bits_fun_sb; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_sh <= exe_stage_lsu_system_io_enq_bits_fun_sh; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_sw <= exe_stage_lsu_system_io_enq_bits_fun_sw; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_sd <= exe_stage_lsu_system_io_enq_bits_fun_sd; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_lr_w <= exe_stage_lsu_system_io_enq_bits_fun_lr_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_sc_w <= exe_stage_lsu_system_io_enq_bits_fun_sc_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoswap_w <= exe_stage_lsu_system_io_enq_bits_fun_amoswap_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoadd_w <= exe_stage_lsu_system_io_enq_bits_fun_amoadd_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoxor_w <= exe_stage_lsu_system_io_enq_bits_fun_amoxor_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoand_w <= exe_stage_lsu_system_io_enq_bits_fun_amoand_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoor_w <= exe_stage_lsu_system_io_enq_bits_fun_amoor_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amomin_w <= exe_stage_lsu_system_io_enq_bits_fun_amomin_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amomax_w <= exe_stage_lsu_system_io_enq_bits_fun_amomax_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amominu_w <= exe_stage_lsu_system_io_enq_bits_fun_amominu_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amomaxu_w <= exe_stage_lsu_system_io_enq_bits_fun_amomaxu_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_lr_d <= exe_stage_lsu_system_io_enq_bits_fun_lr_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_sc_d <= exe_stage_lsu_system_io_enq_bits_fun_sc_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoswap_d <= exe_stage_lsu_system_io_enq_bits_fun_amoswap_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoadd_d <= exe_stage_lsu_system_io_enq_bits_fun_amoadd_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoxor_d <= exe_stage_lsu_system_io_enq_bits_fun_amoxor_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoand_d <= exe_stage_lsu_system_io_enq_bits_fun_amoand_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amoor_d <= exe_stage_lsu_system_io_enq_bits_fun_amoor_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amomin_d <= exe_stage_lsu_system_io_enq_bits_fun_amomin_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amomax_d <= exe_stage_lsu_system_io_enq_bits_fun_amomax_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amominu_d <= exe_stage_lsu_system_io_enq_bits_fun_amominu_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_amomaxu_d <= exe_stage_lsu_system_io_enq_bits_fun_amomaxu_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_flw <= exe_stage_lsu_system_io_enq_bits_fun_flw; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_fsw <= exe_stage_lsu_system_io_enq_bits_fun_fsw; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_fld <= exe_stage_lsu_system_io_enq_bits_fun_fld; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_system_pending_fun_fsd <= exe_stage_lsu_system_io_enq_bits_fun_fsd; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      if (exe_stage_lsu__T_35) begin // @[Lsu.scala 237:23]
        if (exe_stage_lsu_ls_arb_io_in_0_valid) begin // @[Arbiter.scala 138:26]
          if (exe_stage_lsu__T_9) begin // @[Lsu.scala 162:38]
            exe_stage_lsu_system_pending_param_rd0 <= exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0; // @[Lsu.scala 164:23]
          end else begin
            exe_stage_lsu_system_pending_param_rd0 <= 6'h0; // @[Lsu.scala 168:18]
          end
        end else begin
          exe_stage_lsu_system_pending_param_rd0 <= exe_stage_lsu_ls_arb_io_in_1_bits_param_rd0; // @[Arbiter.scala 136:15]
        end
      end else begin
        exe_stage_lsu_system_pending_param_rd0 <= 6'h0; // @[Lsu.scala 243:26]
      end
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      if (exe_stage_lsu__T_35) begin // @[Lsu.scala 237:23]
        if (exe_stage_lsu_ls_arb_io_in_0_valid) begin // @[Arbiter.scala 138:26]
          if (exe_stage_lsu__T_9) begin // @[Lsu.scala 162:38]
            exe_stage_lsu_system_pending_param_dat_op1 <= exe_stage_lsu_io_mmu_lsu_bits_paddr; // @[Lsu.scala 164:23]
          end else begin
            exe_stage_lsu_system_pending_param_dat_op1 <= 64'h0; // @[Lsu.scala 168:18]
          end
        end else begin
          exe_stage_lsu_system_pending_param_dat_op1 <= exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op1; // @[Arbiter.scala 136:15]
        end
      end else begin
        exe_stage_lsu_system_pending_param_dat_op1 <= 64'h0; // @[Lsu.scala 243:26]
      end
    end
    if (exe_stage_lsu_system__T_24) begin // @[IO_Lsu.scala 84:23]
      if (exe_stage_lsu__T_35) begin // @[Lsu.scala 237:23]
        if (exe_stage_lsu_ls_arb_io_in_0_valid) begin // @[Arbiter.scala 138:26]
          if (exe_stage_lsu__T_9) begin // @[Lsu.scala 162:38]
            exe_stage_lsu_system_pending_param_dat_op2 <= exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op2; // @[Lsu.scala 164:23]
          end else begin
            exe_stage_lsu_system_pending_param_dat_op2 <= 64'h0; // @[Lsu.scala 168:18]
          end
        end else begin
          exe_stage_lsu_system_pending_param_dat_op2 <= exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op2; // @[Arbiter.scala 136:15]
        end
      end else begin
        exe_stage_lsu_system_pending_param_dat_op2 <= 64'h0; // @[Lsu.scala 243:26]
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_system_is_busy & ~exe_stage_lsu_system__T_12 & ~exe_stage_lsu_system__T_20 &
          exe_stage_lsu_system__T_22) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IO_Lsu, RISCV-A is not support at IO region\n    at IO_Lsu.scala:73 assert(false.B, \"Assert Failed at IO_Lsu, RISCV-A is not support at IO region\")\n"
            ); // @[IO_Lsu.scala 73:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (exe_stage_lsu_system_is_busy & ~exe_stage_lsu_system__T_12 & ~exe_stage_lsu_system__T_20 &
          exe_stage_lsu_system__T_22)) begin
          $fatal; // @[IO_Lsu.scala 73:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_system__T_24 & exe_stage_lsu_system__T_22 & exe_stage_lsu_system__T_28) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:85 assert( is_busy === false.B  )\n"); // @[IO_Lsu.scala 85:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_system__io_is_empty_T & (exe_stage_lsu_system__T_24 & exe_stage_lsu_system__T_22)) begin
          $fatal; // @[IO_Lsu.scala 85:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_327 & exe_stage_lsu_system__T_32) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:86 assert( isTransing === false.B  )\n"); // @[IO_Lsu.scala 86:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_system__io_getPut_valid_T & (exe_stage_lsu_system__T_24 & exe_stage_lsu_system__T_22)) begin
          $fatal; // @[IO_Lsu.scala 86:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~exe_stage_lsu_system__T_24 & exe_stage_lsu_system__T_35 & exe_stage_lsu_system__T_22) begin
          $fwrite(32'h80000002,"Warning! Accessing a Non-define Region."); // @[IO_Lsu.scala 92:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_329 & ~exe_stage_lsu_system__T_35 & exe_stage_lsu_system__T_33 & exe_stage_lsu_system__T_22 &
          exe_stage_lsu_system__io_is_empty_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:94 assert( is_busy === true.B )\n"); // @[IO_Lsu.scala 94:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_system_is_busy & (_GEN_329 & ~exe_stage_lsu_system__T_35 & exe_stage_lsu_system__T_33 &
          exe_stage_lsu_system__T_22)) begin
          $fatal; // @[IO_Lsu.scala 94:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_333 & ~exe_stage_lsu_system__T_33 & exe_stage_lsu_system__T_34 & exe_stage_lsu_system__T_22 &
          exe_stage_lsu_system__io_is_empty_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:97 assert( is_busy === true.B  )\n"); // @[IO_Lsu.scala 97:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_system_is_busy & (_GEN_333 & ~exe_stage_lsu_system__T_33 & exe_stage_lsu_system__T_34 &
          exe_stage_lsu_system__T_22)) begin
          $fatal; // @[IO_Lsu.scala 97:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_lsu_periph_clock) begin
    if (exe_stage_lsu_periph_reset) begin // @[IO_Lsu.scala 45:27]
      exe_stage_lsu_periph_is_busy <= 1'h0; // @[IO_Lsu.scala 45:27]
    end else begin
      exe_stage_lsu_periph_is_busy <= exe_stage_lsu_periph__GEN_74;
    end
    if (exe_stage_lsu_periph_reset) begin // @[IO_Lsu.scala 46:27]
      exe_stage_lsu_periph_isTransing <= 1'h0; // @[IO_Lsu.scala 46:27]
    end else if (!(exe_stage_lsu_periph__T_24)) begin // @[IO_Lsu.scala 84:23]
      if (exe_stage_lsu_periph__T_35) begin // @[IO_Lsu.scala 89:50]
        exe_stage_lsu_periph_isTransing <= 1'h0; // @[IO_Lsu.scala 91:16]
      end else begin
        exe_stage_lsu_periph_isTransing <= exe_stage_lsu_periph__GEN_26;
      end
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_lb <= exe_stage_lsu_periph_io_enq_bits_fun_lb; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_lh <= exe_stage_lsu_periph_io_enq_bits_fun_lh; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_lw <= exe_stage_lsu_periph_io_enq_bits_fun_lw; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_ld <= exe_stage_lsu_periph_io_enq_bits_fun_ld; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_lbu <= exe_stage_lsu_periph_io_enq_bits_fun_lbu; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_lhu <= exe_stage_lsu_periph_io_enq_bits_fun_lhu; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_lwu <= exe_stage_lsu_periph_io_enq_bits_fun_lwu; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_sb <= exe_stage_lsu_periph_io_enq_bits_fun_sb; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_sh <= exe_stage_lsu_periph_io_enq_bits_fun_sh; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_sw <= exe_stage_lsu_periph_io_enq_bits_fun_sw; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_sd <= exe_stage_lsu_periph_io_enq_bits_fun_sd; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_lr_w <= exe_stage_lsu_periph_io_enq_bits_fun_lr_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_sc_w <= exe_stage_lsu_periph_io_enq_bits_fun_sc_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoswap_w <= exe_stage_lsu_periph_io_enq_bits_fun_amoswap_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoadd_w <= exe_stage_lsu_periph_io_enq_bits_fun_amoadd_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoxor_w <= exe_stage_lsu_periph_io_enq_bits_fun_amoxor_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoand_w <= exe_stage_lsu_periph_io_enq_bits_fun_amoand_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoor_w <= exe_stage_lsu_periph_io_enq_bits_fun_amoor_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amomin_w <= exe_stage_lsu_periph_io_enq_bits_fun_amomin_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amomax_w <= exe_stage_lsu_periph_io_enq_bits_fun_amomax_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amominu_w <= exe_stage_lsu_periph_io_enq_bits_fun_amominu_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amomaxu_w <= exe_stage_lsu_periph_io_enq_bits_fun_amomaxu_w; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_lr_d <= exe_stage_lsu_periph_io_enq_bits_fun_lr_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_sc_d <= exe_stage_lsu_periph_io_enq_bits_fun_sc_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoswap_d <= exe_stage_lsu_periph_io_enq_bits_fun_amoswap_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoadd_d <= exe_stage_lsu_periph_io_enq_bits_fun_amoadd_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoxor_d <= exe_stage_lsu_periph_io_enq_bits_fun_amoxor_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoand_d <= exe_stage_lsu_periph_io_enq_bits_fun_amoand_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amoor_d <= exe_stage_lsu_periph_io_enq_bits_fun_amoor_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amomin_d <= exe_stage_lsu_periph_io_enq_bits_fun_amomin_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amomax_d <= exe_stage_lsu_periph_io_enq_bits_fun_amomax_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amominu_d <= exe_stage_lsu_periph_io_enq_bits_fun_amominu_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_amomaxu_d <= exe_stage_lsu_periph_io_enq_bits_fun_amomaxu_d; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_flw <= exe_stage_lsu_periph_io_enq_bits_fun_flw; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_fsw <= exe_stage_lsu_periph_io_enq_bits_fun_fsw; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_fld <= exe_stage_lsu_periph_io_enq_bits_fun_fld; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      exe_stage_lsu_periph_pending_fun_fsd <= exe_stage_lsu_periph_io_enq_bits_fun_fsd; // @[IO_Lsu.scala 87:13]
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      if (exe_stage_lsu__T_34) begin // @[Lsu.scala 228:23]
        if (exe_stage_lsu_ls_arb_io_in_0_valid) begin // @[Arbiter.scala 138:26]
          if (exe_stage_lsu__T_9) begin // @[Lsu.scala 162:38]
            exe_stage_lsu_periph_pending_param_rd0 <= exe_stage_lsu_io_lsu_iss_exe_bits_param_rd0; // @[Lsu.scala 164:23]
          end else begin
            exe_stage_lsu_periph_pending_param_rd0 <= 6'h0; // @[Lsu.scala 168:18]
          end
        end else begin
          exe_stage_lsu_periph_pending_param_rd0 <= exe_stage_lsu_ls_arb_io_in_1_bits_param_rd0; // @[Arbiter.scala 136:15]
        end
      end else begin
        exe_stage_lsu_periph_pending_param_rd0 <= 6'h0; // @[Lsu.scala 234:26]
      end
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      if (exe_stage_lsu__T_34) begin // @[Lsu.scala 228:23]
        if (exe_stage_lsu_ls_arb_io_in_0_valid) begin // @[Arbiter.scala 138:26]
          if (exe_stage_lsu__T_9) begin // @[Lsu.scala 162:38]
            exe_stage_lsu_periph_pending_param_dat_op1 <= exe_stage_lsu_io_mmu_lsu_bits_paddr; // @[Lsu.scala 164:23]
          end else begin
            exe_stage_lsu_periph_pending_param_dat_op1 <= 64'h0; // @[Lsu.scala 168:18]
          end
        end else begin
          exe_stage_lsu_periph_pending_param_dat_op1 <= exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op1; // @[Arbiter.scala 136:15]
        end
      end else begin
        exe_stage_lsu_periph_pending_param_dat_op1 <= 64'h0; // @[Lsu.scala 234:26]
      end
    end
    if (exe_stage_lsu_periph__T_24) begin // @[IO_Lsu.scala 84:23]
      if (exe_stage_lsu__T_34) begin // @[Lsu.scala 228:23]
        if (exe_stage_lsu_ls_arb_io_in_0_valid) begin // @[Arbiter.scala 138:26]
          if (exe_stage_lsu__T_9) begin // @[Lsu.scala 162:38]
            exe_stage_lsu_periph_pending_param_dat_op2 <= exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op2; // @[Lsu.scala 164:23]
          end else begin
            exe_stage_lsu_periph_pending_param_dat_op2 <= 64'h0; // @[Lsu.scala 168:18]
          end
        end else begin
          exe_stage_lsu_periph_pending_param_dat_op2 <= exe_stage_lsu_ls_arb_io_in_1_bits_param_dat_op2; // @[Arbiter.scala 136:15]
        end
      end else begin
        exe_stage_lsu_periph_pending_param_dat_op2 <= 64'h0; // @[Lsu.scala 234:26]
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_periph_is_busy & ~exe_stage_lsu_periph__T_12 & ~exe_stage_lsu_periph__T_20 &
          exe_stage_lsu_periph__T_22) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at IO_Lsu, RISCV-A is not support at IO region\n    at IO_Lsu.scala:73 assert(false.B, \"Assert Failed at IO_Lsu, RISCV-A is not support at IO region\")\n"
            ); // @[IO_Lsu.scala 73:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (exe_stage_lsu_periph_is_busy & ~exe_stage_lsu_periph__T_12 & ~exe_stage_lsu_periph__T_20 &
          exe_stage_lsu_periph__T_22)) begin
          $fatal; // @[IO_Lsu.scala 73:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_periph__T_24 & exe_stage_lsu_periph__T_22 & exe_stage_lsu_periph__T_28) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:85 assert( is_busy === false.B  )\n"); // @[IO_Lsu.scala 85:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_periph__io_is_empty_T & (exe_stage_lsu_periph__T_24 & exe_stage_lsu_periph__T_22)) begin
          $fatal; // @[IO_Lsu.scala 85:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_366 & exe_stage_lsu_periph__T_32) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:86 assert( isTransing === false.B  )\n"); // @[IO_Lsu.scala 86:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_periph__io_getPut_valid_T & (exe_stage_lsu_periph__T_24 & exe_stage_lsu_periph__T_22)) begin
          $fatal; // @[IO_Lsu.scala 86:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~exe_stage_lsu_periph__T_24 & exe_stage_lsu_periph__T_35 & exe_stage_lsu_periph__T_22) begin
          $fwrite(32'h80000002,"Warning! Accessing a Non-define Region."); // @[IO_Lsu.scala 92:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_368 & ~exe_stage_lsu_periph__T_35 & exe_stage_lsu_periph__T_33 & exe_stage_lsu_periph__T_22 &
          exe_stage_lsu_periph__io_is_empty_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:94 assert( is_busy === true.B )\n"); // @[IO_Lsu.scala 94:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_periph_is_busy & (_GEN_368 & ~exe_stage_lsu_periph__T_35 & exe_stage_lsu_periph__T_33 &
          exe_stage_lsu_periph__T_22)) begin
          $fatal; // @[IO_Lsu.scala 94:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_372 & ~exe_stage_lsu_periph__T_33 & exe_stage_lsu_periph__T_34 & exe_stage_lsu_periph__T_22 &
          exe_stage_lsu_periph__io_is_empty_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IO_Lsu.scala:97 assert( is_busy === true.B  )\n"); // @[IO_Lsu.scala 97:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_periph_is_busy & (_GEN_372 & ~exe_stage_lsu_periph__T_33 & exe_stage_lsu_periph__T_34 &
          exe_stage_lsu_periph__T_22)) begin
          $fatal; // @[IO_Lsu.scala 97:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_lsu_cache_0_missUnit_clock) begin
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 56:27]
      exe_stage_lsu_cache_0_missUnit_miss_queue_0_paddr <= 32'h0; // @[MissUnit.scala 56:27]
    end else if (exe_stage_lsu_cache_0_missUnit_io_req_valid) begin // @[MissUnit.scala 183:21]
      if (exe_stage_lsu_cache_0_missUnit__T_36) begin // @[MissUnit.scala 184:44]
        if (~exe_stage_lsu_cache_0_missUnit_load_sel) begin // @[MissUnit.scala 185:28]
          exe_stage_lsu_cache_0_missUnit_miss_queue_0_paddr <= exe_stage_lsu_cache_0_missUnit_io_req_bits_paddr; // @[MissUnit.scala 185:28]
        end
      end
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 56:27]
      exe_stage_lsu_cache_0_missUnit_miss_queue_1_paddr <= 32'h0; // @[MissUnit.scala 56:27]
    end else if (exe_stage_lsu_cache_0_missUnit_io_req_valid) begin // @[MissUnit.scala 183:21]
      if (exe_stage_lsu_cache_0_missUnit__T_36) begin // @[MissUnit.scala 184:44]
        if (exe_stage_lsu_cache_0_missUnit_load_sel) begin // @[MissUnit.scala 185:28]
          exe_stage_lsu_cache_0_missUnit_miss_queue_1_paddr <= exe_stage_lsu_cache_0_missUnit_io_req_bits_paddr; // @[MissUnit.scala 185:28]
        end
      end
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 59:27]
      exe_stage_lsu_cache_0_missUnit_miss_valid_0 <= 1'h0; // @[MissUnit.scala 59:27]
    end else if (exe_stage_lsu_cache_0_missUnit_io_req_valid) begin // @[MissUnit.scala 183:21]
      if (exe_stage_lsu_cache_0_missUnit__T_36) begin // @[MissUnit.scala 184:44]
        exe_stage_lsu_cache_0_missUnit_miss_valid_0 <= exe_stage_lsu_cache_0_missUnit__GEN_33;
      end else begin
        exe_stage_lsu_cache_0_missUnit_miss_valid_0 <= exe_stage_lsu_cache_0_missUnit__GEN_29;
      end
    end else begin
      exe_stage_lsu_cache_0_missUnit_miss_valid_0 <= exe_stage_lsu_cache_0_missUnit__GEN_29;
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 59:27]
      exe_stage_lsu_cache_0_missUnit_miss_valid_1 <= 1'h0; // @[MissUnit.scala 59:27]
    end else if (exe_stage_lsu_cache_0_missUnit_io_req_valid) begin // @[MissUnit.scala 183:21]
      if (exe_stage_lsu_cache_0_missUnit__T_36) begin // @[MissUnit.scala 184:44]
        exe_stage_lsu_cache_0_missUnit_miss_valid_1 <= exe_stage_lsu_cache_0_missUnit__GEN_34;
      end else begin
        exe_stage_lsu_cache_0_missUnit_miss_valid_1 <= exe_stage_lsu_cache_0_missUnit__GEN_30;
      end
    end else begin
      exe_stage_lsu_cache_0_missUnit_miss_valid_1 <= exe_stage_lsu_cache_0_missUnit__GEN_30;
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 62:25]
      exe_stage_lsu_cache_0_missUnit_miss_rsp_0 <= 64'h0; // @[MissUnit.scala 62:25]
    end else if (exe_stage_lsu_cache_0_missUnit__T) begin // @[MissUnit.scala 140:31]
      if (~exe_stage_lsu_cache_0_missUnit_transCnt) begin // @[MissUnit.scala 141:25]
        exe_stage_lsu_cache_0_missUnit_miss_rsp_0 <= exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_data; // @[MissUnit.scala 141:25]
      end
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 62:25]
      exe_stage_lsu_cache_0_missUnit_miss_rsp_1 <= 64'h0; // @[MissUnit.scala 62:25]
    end else if (exe_stage_lsu_cache_0_missUnit__T) begin // @[MissUnit.scala 140:31]
      if (exe_stage_lsu_cache_0_missUnit_transCnt) begin // @[MissUnit.scala 141:25]
        exe_stage_lsu_cache_0_missUnit_miss_rsp_1 <= exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_data; // @[MissUnit.scala 141:25]
      end
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 65:32]
      exe_stage_lsu_cache_0_missUnit_mshr_state_qout <= 3'h0; // @[MissUnit.scala 65:32]
    end else begin
      exe_stage_lsu_cache_0_missUnit_mshr_state_qout <= exe_stage_lsu_cache_0_missUnit_mshr_state_dnxt; // @[MissUnit.scala 65:32]
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[Edges.scala 228:27]
      exe_stage_lsu_cache_0_missUnit_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (exe_stage_lsu_cache_0_missUnit__T) begin // @[Edges.scala 234:17]
      if (exe_stage_lsu_cache_0_missUnit_first) begin // @[Edges.scala 235:21]
        exe_stage_lsu_cache_0_missUnit_counter <= exe_stage_lsu_cache_0_missUnit_beats1;
      end else begin
        exe_stage_lsu_cache_0_missUnit_counter <= exe_stage_lsu_cache_0_missUnit_counter1;
      end
    end
    if (exe_stage_lsu_cache_0_missUnit__acquire_sel_T_3) begin // @[Reg.scala 20:18]
      if (exe_stage_lsu_cache_0_missUnit_miss_valid_0) begin // @[MissUnit.scala 75:36]
        exe_stage_lsu_cache_0_missUnit_acquire_sel_r <= 1'h0;
      end else begin
        exe_stage_lsu_cache_0_missUnit_acquire_sel_r <= 1'h1;
      end
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 81:37]
      exe_stage_lsu_cache_0_missUnit_cache_acquire_vaild <= 1'h0; // @[MissUnit.scala 81:37]
    end else begin
      exe_stage_lsu_cache_0_missUnit_cache_acquire_vaild <= exe_stage_lsu_cache_0_missUnit__GEN_11;
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 87:37]
      exe_stage_lsu_cache_0_missUnit_cache_grantAck_valid <= 1'h0; // @[MissUnit.scala 87:37]
    end else if (!(exe_stage_lsu_cache_0_missUnit__T_23)) begin // @[MissUnit.scala 145:61]
      exe_stage_lsu_cache_0_missUnit_cache_grantAck_valid <= exe_stage_lsu_cache_0_missUnit__GEN_24;
    end
    if (exe_stage_lsu_cache_0_missUnit_reset) begin // @[MissUnit.scala 90:26]
      exe_stage_lsu_cache_0_missUnit_rsp_valid <= 1'h0; // @[MissUnit.scala 90:26]
    end else begin
      exe_stage_lsu_cache_0_missUnit_rsp_valid <= exe_stage_lsu_cache_0_missUnit__GEN_27;
    end
    if (exe_stage_lsu_cache_0_missUnit__T) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_missUnit_cache_grant_reg_sink <= exe_stage_lsu_cache_0_missUnit_io_cache_grant_bits_sink; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_missUnit__T_6 & exe_stage_lsu_cache_0_missUnit__T_7) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at missUnit, source-id of grant mis-match\n    at MissUnit.scala:93 assert( ~(io.cache_grant.fire & io.cache_grant.bits.source =/= id.U), \"Assert Failed at missUnit, source-id of grant mis-match\"  )\n"
            ); // @[MissUnit.scala 93:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_missUnit__T_4 & exe_stage_lsu_cache_0_missUnit__T_6) begin
          $fatal; // @[MissUnit.scala 93:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_missUnit__acquire_sel_T_3 & exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_9 &
          exe_stage_lsu_cache_0_missUnit__T_6 & exe_stage_lsu_cache_0_missUnit__T_15) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MissUnit.scala:113 assert(mshr_state_qout === 1.U)\n"); // @[MissUnit.scala 113:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_8 & (~exe_stage_lsu_cache_0_missUnit__acquire_sel_T_3 &
          exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_9 & exe_stage_lsu_cache_0_missUnit__T_6)) begin
          $fatal; // @[MissUnit.scala 113:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_missUnit__T & exe_stage_lsu_cache_0_missUnit__T_6 &
          exe_stage_lsu_cache_0_missUnit__T_20) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MissUnit.scala:142 assert( mshr_state_qout === 2.U )\n"); // @[MissUnit.scala 142:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_11 & (exe_stage_lsu_cache_0_missUnit__T &
          exe_stage_lsu_cache_0_missUnit__T_6)) begin
          $fatal; // @[MissUnit.scala 142:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_missUnit__T_23 & exe_stage_lsu_cache_0_missUnit__T_24 &
          exe_stage_lsu_cache_0_missUnit__T_6 & exe_stage_lsu_cache_0_missUnit__T_28) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MissUnit.scala:150 assert(mshr_state_qout === 3.U)\n"); // @[MissUnit.scala 150:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_13 & (~exe_stage_lsu_cache_0_missUnit__T_23 &
          exe_stage_lsu_cache_0_missUnit__T_24 & exe_stage_lsu_cache_0_missUnit__T_6)) begin
          $fatal; // @[MissUnit.scala 150:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_401 & ~exe_stage_lsu_cache_0_missUnit__T_24 & exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_14 &
          exe_stage_lsu_cache_0_missUnit__T_6 & exe_stage_lsu_cache_0_missUnit__T_28) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MissUnit.scala:154 assert(mshr_state_qout === 3.U)\n"); // @[MissUnit.scala 154:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_13 & (_GEN_401 & ~exe_stage_lsu_cache_0_missUnit__T_24 &
          exe_stage_lsu_cache_0_missUnit__mshr_state_dnxt_T_14 & exe_stage_lsu_cache_0_missUnit__T_6)) begin
          $fatal; // @[MissUnit.scala 154:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_missUnit_io_req_valid & exe_stage_lsu_cache_0_missUnit__T_6 &
          exe_stage_lsu_cache_0_missUnit__T_51) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at MissUnit, the Miss-Entry is equal to SB-Entry, which hints that missUnit never full!\n    at MissUnit.scala:193 assert(\n"
            ); // @[MissUnit.scala 193:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_missUnit__T_48 & (exe_stage_lsu_cache_0_missUnit_io_req_valid &
          exe_stage_lsu_cache_0_missUnit__T_6)) begin
          $fatal; // @[MissUnit.scala 193:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_clock) begin
    if (exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_en &
      exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_mask) begin
      exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram[exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_addr] <=
        exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_probeUnit_probe_fifo_clock) begin
    if (exe_stage_lsu_cache_0_probeUnit_probe_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_cache_0_probeUnit_probe_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_cache_0_probeUnit_probe_fifo__T) begin // @[Decoupled.scala 295:27]
      exe_stage_lsu_cache_0_probeUnit_probe_fifo_maybe_full <= exe_stage_lsu_cache_0_probeUnit_probe_fifo__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_clock) begin
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_en &
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_mask) begin

        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_addr]
         <= exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_clock) begin
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_en &
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_mask) begin

        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_addr]
         <= exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_clock) begin
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_en &
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_mask) begin

        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_addr]
         <= exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_clock) begin
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_en &
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_mask) begin

        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_addr]
         <= exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_clock) begin
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_en &
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_mask) begin

        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_addr]
         <= exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_clock) begin
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_en &
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_mask) begin

        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData[exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_addr]
         <= exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_clock) begin
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_reset) begin // @[Counter.scala 61:40]
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_25) begin // @[Decoupled.scala 288:16]
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value <=
        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__value_T_1; // @[Counter.scala 77:15]
    end
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_reset) begin // @[Counter.scala 61:40]
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__GEN_24) begin // @[Decoupled.scala 292:16]
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value <=
        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__value_T_3; // @[Counter.scala 77:15]
    end
    if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__T) begin // @[Decoupled.scala 295:27]
      if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_empty) begin // @[Decoupled.scala 317:17]
        if (exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_maybe_full <=
            exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T;
        end
      end else begin
        exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_maybe_full <= exe_stage_lsu_cache_0_writeBackUnit_wb_fifo__do_enq_T;
      end
    end
  end
  always @(posedge exe_stage_lsu_cache_0_writeBackUnit_clock) begin
    if (exe_stage_lsu_cache_0_writeBackUnit_reset) begin // @[wrtieBackUnit.scala 70:30]
      exe_stage_lsu_cache_0_writeBackUnit_wb_state_qout <= 2'h0; // @[wrtieBackUnit.scala 70:30]
    end else begin
      exe_stage_lsu_cache_0_writeBackUnit_wb_state_qout <= exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_20; // @[wrtieBackUnit.scala 70:30]
    end
    if (exe_stage_lsu_cache_0_writeBackUnit_reset) begin // @[Edges.scala 228:27]
      exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (exe_stage_lsu_cache_0_writeBackUnit__is_release_done_T) begin // @[Edges.scala 234:17]
      if (exe_stage_lsu_cache_0_writeBackUnit_is_release_done_first) begin // @[Edges.scala 235:21]
        exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter <=
          exe_stage_lsu_cache_0_writeBackUnit_is_release_done_beats1;
      end else begin
        exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter <=
          exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter1;
      end
    end
    if (exe_stage_lsu_cache_0_writeBackUnit_reset) begin // @[wrtieBackUnit.scala 76:36]
      exe_stage_lsu_cache_0_writeBackUnit_cache_release_valid <= 1'h0; // @[wrtieBackUnit.scala 76:36]
    end else if (exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_8) begin // @[wrtieBackUnit.scala 104:33]
      if (exe_stage_lsu_cache_0_writeBackUnit__is_release_done_T) begin // @[wrtieBackUnit.scala 105:35]
        exe_stage_lsu_cache_0_writeBackUnit_cache_release_valid <= 1'h0; // @[wrtieBackUnit.scala 105:57]
      end else begin
        exe_stage_lsu_cache_0_writeBackUnit_cache_release_valid <= exe_stage_lsu_cache_0_writeBackUnit__GEN_3;
      end
    end
    if (exe_stage_lsu_cache_0_writeBackUnit_reset) begin // @[wrtieBackUnit.scala 79:36]
      exe_stage_lsu_cache_0_writeBackUnit_cache_grant_ready <= 1'h0; // @[wrtieBackUnit.scala 79:36]
    end else begin
      exe_stage_lsu_cache_0_writeBackUnit_cache_grant_ready <= exe_stage_lsu_cache_0_writeBackUnit__GEN_7;
    end
    if (exe_stage_lsu_cache_0_writeBackUnit_reset) begin // @[wrtieBackUnit.scala 100:24]
      exe_stage_lsu_cache_0_writeBackUnit_beatCnt <= 1'h0; // @[wrtieBackUnit.scala 100:24]
    end else if (exe_stage_lsu_cache_0_writeBackUnit__T_2) begin // @[wrtieBackUnit.scala 101:57]
      exe_stage_lsu_cache_0_writeBackUnit_beatCnt <= 1'h0; // @[wrtieBackUnit.scala 101:67]
    end else if (exe_stage_lsu_cache_0_writeBackUnit__is_release_done_T) begin // @[wrtieBackUnit.scala 102:38]
      exe_stage_lsu_cache_0_writeBackUnit_beatCnt <= exe_stage_lsu_cache_0_writeBackUnit__beatCnt_T_1; // @[wrtieBackUnit.scala 102:48]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_writeBackUnit__T_8 & exe_stage_lsu_cache_0_writeBackUnit__T_11 &
          exe_stage_lsu_cache_0_writeBackUnit__T_12) begin
          $fwrite(32'h80000002,"Assertion failed\n    at wrtieBackUnit.scala:162 assert( wb_state_qout === 2.U )\n"); // @[wrtieBackUnit.scala 162:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_13 & (exe_stage_lsu_cache_0_writeBackUnit__T_8 &
          exe_stage_lsu_cache_0_writeBackUnit__T_11)) begin
          $fatal; // @[wrtieBackUnit.scala 162:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_writeBackUnit__T_8 & exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_ready &
          exe_stage_lsu_cache_0_writeBackUnit__T_11 & exe_stage_lsu_cache_0_writeBackUnit__T_12) begin
          $fwrite(32'h80000002,"Assertion failed\n    at wrtieBackUnit.scala:165 assert( wb_state_qout === 2.U )\n"); // @[wrtieBackUnit.scala 165:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_writeBackUnit__wb_state_dnxt_T_13 & (~exe_stage_lsu_cache_0_writeBackUnit__T_8 &
          exe_stage_lsu_cache_0_writeBackUnit_io_cache_grant_ready & exe_stage_lsu_cache_0_writeBackUnit__T_11)) begin
          $fatal; // @[wrtieBackUnit.scala 165:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_writeBackUnit__T_11 & exe_stage_lsu_cache_0_writeBackUnit__T_23) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at writeBack-Unit, grant-id mis-match\n    at wrtieBackUnit.scala:167 assert( ~(io.cache_grant.fire & io.cache_grant.bits.source =/= id.U), \"Assert Failed at writeBack-Unit, grant-id mis-match\" )\n"
            ); // @[wrtieBackUnit.scala 167:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_writeBackUnit__T_20 & exe_stage_lsu_cache_0_writeBackUnit__T_11) begin
          $fatal; // @[wrtieBackUnit.scala 167:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_writeBackUnit__T_24 & exe_stage_lsu_cache_0_writeBackUnit__T_11 &
          exe_stage_lsu_cache_0_writeBackUnit__T_28) begin
          $fwrite(32'h80000002,
            "Assertion failed: When WriteBack Unit is busy, no new acquire will be emitted, and there is no wb request!\n    at wrtieBackUnit.scala:176 assert(~io.wb_req.valid, \"When WriteBack Unit is busy, no new acquire will be emitted, and there is no wb request!\")\n"
            ); // @[wrtieBackUnit.scala 176:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_writeBackUnit__T_25 & (exe_stage_lsu_cache_0_writeBackUnit__T_24 &
          exe_stage_lsu_cache_0_writeBackUnit__T_11)) begin
          $fatal; // @[wrtieBackUnit.scala 176:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_chkIdx[exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_paddr_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_paddr[exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_wdata_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_wdata[exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_wdata_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_wstrb_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_wstrb[exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_wstrb_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_lb[exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_lh[exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_lw[exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_ld[exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu[exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu[exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu[exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_sb[exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_sh[exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_sw[exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_sd[exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_en &
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d[exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_flw[exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw[exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_fld[exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd[exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_probe[exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_probe_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_grant[exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_grant_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_lsEntry_ram_fun_preft[exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_fun_preft_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_en & exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_mask) begin
      exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0[exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_addr] <=
        exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_lsEntry_clock) begin
    if (exe_stage_lsu_cache_0_lsEntry_reset) begin // @[Counter.scala 61:40]
      exe_stage_lsu_cache_0_lsEntry_enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (exe_stage_lsu_cache_0_lsEntry__GEN_109) begin // @[Decoupled.scala 288:16]
      exe_stage_lsu_cache_0_lsEntry_enq_ptr_value <= exe_stage_lsu_cache_0_lsEntry__value_T_1; // @[Counter.scala 77:15]
    end
    if (exe_stage_lsu_cache_0_lsEntry_reset) begin // @[Counter.scala 61:40]
      exe_stage_lsu_cache_0_lsEntry_deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (exe_stage_lsu_cache_0_lsEntry__GEN_108) begin // @[Decoupled.scala 292:16]
      exe_stage_lsu_cache_0_lsEntry_deq_ptr_value <= exe_stage_lsu_cache_0_lsEntry__value_T_3; // @[Counter.scala 77:15]
    end
    if (exe_stage_lsu_cache_0_lsEntry_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_cache_0_lsEntry_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_cache_0_lsEntry__T) begin // @[Decoupled.scala 295:27]
      if (exe_stage_lsu_cache_0_lsEntry_empty) begin // @[Decoupled.scala 317:17]
        if (exe_stage_lsu_cache_0_lsEntry_io_deq_ready) begin // @[Decoupled.scala 320:26]
          exe_stage_lsu_cache_0_lsEntry_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          exe_stage_lsu_cache_0_lsEntry_maybe_full <= exe_stage_lsu_cache_0_lsEntry__do_enq_T;
        end
      end else begin
        exe_stage_lsu_cache_0_lsEntry_maybe_full <= exe_stage_lsu_cache_0_lsEntry__do_enq_T;
      end
    end
  end
  always @(posedge exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_clock) begin
    if (exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_en & exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_mask) begin
      exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx[exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_addr] <=
        exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_clock) begin
    if (exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_en & exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_mask) begin
      exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0[exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_addr] <=
        exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_clock) begin
    if (exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_en & exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_mask) begin
      exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res[exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_addr] <=
        exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_clock) begin
    if (exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_en &
      exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_mask) begin
      exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo[exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_addr] <=
        exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_clock) begin
    if (exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_en & exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_mask) begin
      exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw[exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_addr] <=
        exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_clock) begin
    if (exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_en & exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_mask) begin
      exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld[exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_addr] <=
        exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_rtn_fifo_clock) begin
    if (exe_stage_lsu_cache_0_rtn_fifo_reset) begin // @[Counter.scala 61:40]
      exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (exe_stage_lsu_cache_0_rtn_fifo__GEN_25) begin // @[Decoupled.scala 288:16]
      exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value <= exe_stage_lsu_cache_0_rtn_fifo__value_T_1; // @[Counter.scala 77:15]
    end
    if (exe_stage_lsu_cache_0_rtn_fifo_reset) begin // @[Counter.scala 61:40]
      exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (exe_stage_lsu_cache_0_rtn_fifo__GEN_24) begin // @[Decoupled.scala 292:16]
      exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value <= exe_stage_lsu_cache_0_rtn_fifo__value_T_3; // @[Counter.scala 77:15]
    end
    if (exe_stage_lsu_cache_0_rtn_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_cache_0_rtn_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_cache_0_rtn_fifo__T) begin // @[Decoupled.scala 295:27]
      if (exe_stage_lsu_cache_0_rtn_fifo_empty) begin // @[Decoupled.scala 317:17]
        if (exe_stage_lsu_cache_0_rtn_fifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          exe_stage_lsu_cache_0_rtn_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          exe_stage_lsu_cache_0_rtn_fifo_maybe_full <= exe_stage_lsu_cache_0_rtn_fifo__do_enq_T;
        end
      end else begin
        exe_stage_lsu_cache_0_rtn_fifo_maybe_full <= exe_stage_lsu_cache_0_rtn_fifo__do_enq_T;
      end
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx[exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_paddr_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_paddr[exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_paddr_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_wdata_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_wdata[exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_wdata_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_wstrb[exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_wstrb_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld[exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_mask) begin

        exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_mask) begin

        exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_mask) begin

        exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_mask) begin

        exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_mask) begin

        exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_mask) begin

        exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d[exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_addr]
         <= exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw[exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw[exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld[exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd[exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe[exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant[exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_en &
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_mask) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft[exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_en & exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0[exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_addr] <=
        exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_reload_fifo_clock) begin
    if (exe_stage_lsu_cache_0_reload_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_cache_0_reload_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_cache_0_reload_fifo__T) begin // @[Decoupled.scala 295:27]
      exe_stage_lsu_cache_0_reload_fifo_maybe_full <= exe_stage_lsu_cache_0_reload_fifo__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_clock) begin
    if (exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_en &
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_mask) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15[exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_addr] <=
        exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_1_data; // @[CacheRAM.scala 46:27]
    end
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_datRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_addr_pipe_0 <= exe_stage_lsu_cache_0_stage_datRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_clock) begin
    if (exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_en & exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_mask
      ) begin
      exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem[exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_addr] <=
        exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_MPORT_data; // @[CacheRAM.scala 152:27]
    end
    exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_en_pipe_0 <= exe_stage_lsu_cache_0_stage_tagRAM_0_io_enr;
    if (exe_stage_lsu_cache_0_stage_tagRAM_0_io_enr) begin
      exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_addr_pipe_0 <=
        exe_stage_lsu_cache_0_stage_tagRAM_0_io_addrr;
    end
  end
  always @(posedge exe_stage_lsu_cache_0_stage_clock) begin
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 71:32]
      exe_stage_lsu_cache_0_stage_pipeStage1Valid <= 1'h0; // @[DcacheStage.scala 71:32]
    end else begin
      exe_stage_lsu_cache_0_stage_pipeStage1Valid <= exe_stage_lsu_cache_0_stage__pipeStage1Valid_T; // @[DcacheStage.scala 71:32]
    end
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_chkIdx <= exe_stage_lsu_cache_0_stage_io_enq_bits_chkIdx; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr <= exe_stage_lsu_cache_0_stage_io_enq_bits_paddr; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata <= exe_stage_lsu_cache_0_stage_io_enq_bits_wdata; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb <= exe_stage_lsu_cache_0_stage_io_enq_bits_wstrb; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lb <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lb; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lh <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lh; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lw <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lw; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_ld <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_ld; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lbu <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lbu; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lhu <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lhu; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lwu <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lwu; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sb <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sb; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sh <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sh; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sw <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sw; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sd <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sd; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lr_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sc_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoswap_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoadd_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoxor_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoand_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoor_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomin_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomax_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amominu_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_w <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomaxu_w; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_lr_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_sc_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoswap_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoadd_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoxor_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoand_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amoor_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomin_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomax_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amominu_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_d <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_amomaxu_d; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_flw <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_flw; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsw <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fsw; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fld <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fld; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsd <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_fsd; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_probe <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_probe; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_grant; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_preft <= exe_stage_lsu_cache_0_stage_io_enq_bits_fun_preft; // @[DcacheStage.scala 72:32]
    exe_stage_lsu_cache_0_stage_pipeStage1Bits_rd_rd0 <= exe_stage_lsu_cache_0_stage_io_enq_bits_rd_rd0; // @[DcacheStage.scala 72:32]
    if (exe_stage_lsu_cache_0_stage__pipeStage1Valid_T) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_isTagBypass <= exe_stage_lsu_cache_0_stage__isTagBypass_T_1; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__tagBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_tagBypassData <= exe_stage_lsu_cache_0_stage__tagInfoW_T; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 84:26]
      exe_stage_lsu_cache_0_stage_isCBValid_1_0 <= 1'h0; // @[DcacheStage.scala 84:26]
    end else if (exe_stage_lsu_cache_0_stage_pipeStage1Valid) begin // @[DcacheStage.scala 226:27]
      if (exe_stage_lsu_cache_0_stage__T_248) begin // @[DcacheStage.scala 235:46]
        if (exe_stage_lsu_cache_0_stage__addrSelW_T) begin // @[DcacheStage.scala 236:34]
          exe_stage_lsu_cache_0_stage_isCBValid_1_0 <= 1'h0; // @[DcacheStage.scala 236:34]
        end else begin
          exe_stage_lsu_cache_0_stage_isCBValid_1_0 <= exe_stage_lsu_cache_0_stage__GEN_56;
        end
      end else begin
        exe_stage_lsu_cache_0_stage_isCBValid_1_0 <= exe_stage_lsu_cache_0_stage__GEN_56;
      end
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 84:26]
      exe_stage_lsu_cache_0_stage_isCBValid_0_0 <= 1'h0; // @[DcacheStage.scala 84:26]
    end else if (exe_stage_lsu_cache_0_stage_pipeStage1Valid) begin // @[DcacheStage.scala 226:27]
      if (exe_stage_lsu_cache_0_stage__T_248) begin // @[DcacheStage.scala 235:46]
        if (~exe_stage_lsu_cache_0_stage__addrSelW_T) begin // @[DcacheStage.scala 236:34]
          exe_stage_lsu_cache_0_stage_isCBValid_0_0 <= 1'h0; // @[DcacheStage.scala 236:34]
        end else begin
          exe_stage_lsu_cache_0_stage_isCBValid_0_0 <= exe_stage_lsu_cache_0_stage__GEN_55;
        end
      end else begin
        exe_stage_lsu_cache_0_stage_isCBValid_0_0 <= exe_stage_lsu_cache_0_stage__GEN_55;
      end
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 86:26]
      exe_stage_lsu_cache_0_stage_isCBDirty_0_0 <= 1'h0; // @[DcacheStage.scala 86:26]
    end else if (exe_stage_lsu_cache_0_stage_pipeStage1Valid) begin // @[DcacheStage.scala 226:27]
      if (exe_stage_lsu_cache_0_stage__datEnW_0_T_28) begin // @[DcacheStage.scala 231:42]
        exe_stage_lsu_cache_0_stage_isCBDirty_0_0 <= exe_stage_lsu_cache_0_stage__GEN_59;
      end else if (exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant) begin // @[DcacheStage.scala 227:38]
        exe_stage_lsu_cache_0_stage_isCBDirty_0_0 <= exe_stage_lsu_cache_0_stage__GEN_53;
      end
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 86:26]
      exe_stage_lsu_cache_0_stage_isCBDirty_1_0 <= 1'h0; // @[DcacheStage.scala 86:26]
    end else if (exe_stage_lsu_cache_0_stage_pipeStage1Valid) begin // @[DcacheStage.scala 226:27]
      if (exe_stage_lsu_cache_0_stage__datEnW_0_T_28) begin // @[DcacheStage.scala 231:42]
        exe_stage_lsu_cache_0_stage_isCBDirty_1_0 <= exe_stage_lsu_cache_0_stage__GEN_60;
      end else if (exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant) begin // @[DcacheStage.scala 227:38]
        exe_stage_lsu_cache_0_stage_isCBDirty_1_0 <= exe_stage_lsu_cache_0_stage__GEN_54;
      end
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 147:30]
      exe_stage_lsu_cache_0_stage_is_pending_lr <= 1'h0; // @[DcacheStage.scala 147:30]
    end else if (exe_stage_lsu_cache_0_stage__T_92) begin // @[DcacheStage.scala 157:32]
      exe_stage_lsu_cache_0_stage_is_pending_lr <= 1'h0; // @[DcacheStage.scala 158:19]
    end else if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 159:73]
      exe_stage_lsu_cache_0_stage_is_pending_lr <= exe_stage_lsu_cache_0_stage__GEN_38;
    end else if (exe_stage_lsu_cache_0_stage__T_202) begin // @[DcacheStage.scala 172:61]
      exe_stage_lsu_cache_0_stage_is_pending_lr <= exe_stage_lsu_cache_0_stage__GEN_35;
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 148:29]
      exe_stage_lsu_cache_0_stage_is_lr_64_32n <= 1'h0; // @[DcacheStage.scala 148:29]
    end else if (!(exe_stage_lsu_cache_0_stage__T_92)) begin // @[DcacheStage.scala 157:32]
      if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 159:73]
        if (exe_stage_lsu_cache_0_stage__datEnW_0_T_58) begin // @[DcacheStage.scala 160:38]
          exe_stage_lsu_cache_0_stage_is_lr_64_32n <= exe_stage_lsu_cache_0_stage__is_sc_fail_T_32; // @[DcacheStage.scala 162:20]
        end
      end
    end
    if (!(exe_stage_lsu_cache_0_stage__T_92)) begin // @[DcacheStage.scala 157:32]
      if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 159:73]
        if (exe_stage_lsu_cache_0_stage__datEnW_0_T_58) begin // @[DcacheStage.scala 160:38]
          exe_stage_lsu_cache_0_stage_lr_addr <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr; // @[DcacheStage.scala 163:15]
        end
      end
    end
    if (exe_stage_lsu_cache_0_stage__pipeStage1Valid_T) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_isDatBypass <= exe_stage_lsu_cache_0_stage__isDatBypass_T_1; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_0 <= exe_stage_lsu_cache_0_stage__T_205; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_1 <= exe_stage_lsu_cache_0_stage__T_206; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_2 <= exe_stage_lsu_cache_0_stage__T_207; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_3 <= exe_stage_lsu_cache_0_stage__T_208; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_4 <= exe_stage_lsu_cache_0_stage__T_209; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_5 <= exe_stage_lsu_cache_0_stage__T_210; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_6 <= exe_stage_lsu_cache_0_stage__T_211; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_7 <= exe_stage_lsu_cache_0_stage__T_212; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_8 <= exe_stage_lsu_cache_0_stage__T_213; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_9 <= exe_stage_lsu_cache_0_stage__T_214; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_10 <= exe_stage_lsu_cache_0_stage__T_215; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_11 <= exe_stage_lsu_cache_0_stage__T_216; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_12 <= exe_stage_lsu_cache_0_stage__T_217; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_13 <= exe_stage_lsu_cache_0_stage__T_218; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_14 <= exe_stage_lsu_cache_0_stage__T_219; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassData_15 <= exe_stage_lsu_cache_0_stage__T_220; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_15 <= exe_stage_lsu_cache_0_stage__T_59; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_14 <= exe_stage_lsu_cache_0_stage__T_58; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_13 <= exe_stage_lsu_cache_0_stage__T_57; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_12 <= exe_stage_lsu_cache_0_stage__T_56; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_11 <= exe_stage_lsu_cache_0_stage__T_55; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_10 <= exe_stage_lsu_cache_0_stage__T_54; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_9 <= exe_stage_lsu_cache_0_stage__T_53; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_8 <= exe_stage_lsu_cache_0_stage__T_52; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_7 <= exe_stage_lsu_cache_0_stage__T_51; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_6 <= exe_stage_lsu_cache_0_stage__T_50; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_5 <= exe_stage_lsu_cache_0_stage__T_49; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_4 <= exe_stage_lsu_cache_0_stage__T_48; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_3 <= exe_stage_lsu_cache_0_stage__T_47; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_2 <= exe_stage_lsu_cache_0_stage__T_46; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_1 <= exe_stage_lsu_cache_0_stage__T_45; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage__datBypassData_T_3) begin // @[Reg.scala 20:18]
      exe_stage_lsu_cache_0_stage_datBypassWM_0 <= exe_stage_lsu_cache_0_stage__T_44; // @[Reg.scala 20:22]
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 146:26]
      exe_stage_lsu_cache_0_stage_killTrans <= 1'h0; // @[DcacheStage.scala 146:26]
    end else begin
      exe_stage_lsu_cache_0_stage_killTrans <= exe_stage_lsu_cache_0_stage__GEN_50;
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 291:33]
      exe_stage_lsu_cache_0_stage_missUnitReqValid <= 1'h0; // @[DcacheStage.scala 291:33]
    end else begin
      exe_stage_lsu_cache_0_stage_missUnitReqValid <= exe_stage_lsu_cache_0_stage__T_299;
    end
    exe_stage_lsu_cache_0_stage_missUnitReqPaddr <= exe_stage_lsu_cache_0_stage__GEN_74[31:0];
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 307:27]
      exe_stage_lsu_cache_0_stage_wbReqValid <= 1'h0; // @[DcacheStage.scala 307:27]
    end else begin
      exe_stage_lsu_cache_0_stage_wbReqValid <= exe_stage_lsu_cache_0_stage__GEN_82;
    end
    exe_stage_lsu_cache_0_stage_wbReqPaddr <= exe_stage_lsu_cache_0_stage__GEN_83[31:0];
    if (exe_stage_lsu_cache_0_stage__T_304) begin // @[DcacheStage.scala 322:99]
      exe_stage_lsu_cache_0_stage_wbReqData <= exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_T; // @[DcacheStage.scala 325:17]
    end else if (exe_stage_lsu_cache_0_stage__T_202) begin // @[DcacheStage.scala 328:60]
      exe_stage_lsu_cache_0_stage_wbReqData <= exe_stage_lsu_cache_0_stage__amo_reAlign_64_b_T; // @[DcacheStage.scala 331:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_304) begin // @[DcacheStage.scala 322:99]
      if (exe_stage_lsu_cache_0_stage__addrSelW_T) begin // @[DcacheStage.scala 326:17]
        exe_stage_lsu_cache_0_stage_wbReqisData <= exe_stage_lsu_cache_0_stage_isCBDirty_1_0; // @[DcacheStage.scala 326:17]
      end else begin
        exe_stage_lsu_cache_0_stage_wbReqisData <= exe_stage_lsu_cache_0_stage_isCBDirty_0_0;
      end
    end else if (exe_stage_lsu_cache_0_stage__T_202) begin // @[DcacheStage.scala 328:60]
      exe_stage_lsu_cache_0_stage_wbReqisData <= exe_stage_lsu_cache_0_stage__wbReqisData_T; // @[DcacheStage.scala 332:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_304) begin // @[DcacheStage.scala 322:99]
      exe_stage_lsu_cache_0_stage_isPb <= 1'h0; // @[DcacheStage.scala 327:17]
    end else begin
      exe_stage_lsu_cache_0_stage_isPb <= exe_stage_lsu_cache_0_stage__GEN_81;
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 347:28]
      exe_stage_lsu_cache_0_stage_reloadValid <= 1'h0; // @[DcacheStage.scala 347:28]
    end else begin
      exe_stage_lsu_cache_0_stage_reloadValid <= exe_stage_lsu_cache_0_stage__T_348;
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_chkIdx <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_chkIdx; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_paddr <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_wdata <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_wstrb <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_lb <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lb; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_lh <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lh; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_lw <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lw; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_ld <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_ld; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_lbu <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lbu; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_lhu <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lhu; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_lwu <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lwu; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_sb <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sb; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_sh <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sh; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_sw <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sw; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_sd <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sd; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_lr_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_sc_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoswap_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoadd_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoxor_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoand_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoor_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amomin_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amomax_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amominu_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amomaxu_w <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_w; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_lr_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_sc_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoswap_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoadd_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoxor_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoand_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amoor_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amomin_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amomax_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amominu_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_amomaxu_d <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_d; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_flw <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_flw; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_fsw <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsw; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_fld <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fld; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_fsd <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsd; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_probe <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_probe; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_grant <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_fun_preft <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_preft; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage__T_348) begin // @[DcacheStage.scala 350:67]
      exe_stage_lsu_cache_0_stage_reloadBits_rd_rd0 <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_rd_rd0; // @[DcacheStage.scala 352:17]
    end
    if (exe_stage_lsu_cache_0_stage_reset) begin // @[DcacheStage.scala 362:25]
      exe_stage_lsu_cache_0_stage_deqValid <= 1'h0; // @[DcacheStage.scala 362:25]
    end else begin
      exe_stage_lsu_cache_0_stage_deqValid <= exe_stage_lsu_cache_0_stage__T_134;
    end
    if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 368:66]
      exe_stage_lsu_cache_0_stage_deqBits_chkIdx <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_chkIdx; // @[DcacheStage.scala 395:24]
    end
    if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 368:66]
      exe_stage_lsu_cache_0_stage_deqBits_wb_rd0 <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_rd_rd0; // @[DcacheStage.scala 394:25]
    end
    if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 368:66]
      if (exe_stage_lsu_cache_0_stage__datEnW_0_T_19) begin // @[DcacheStage.scala 386:20]
        exe_stage_lsu_cache_0_stage_deqBits_wb_res <= {{63'd0}, exe_stage_lsu_cache_0_stage__is_sc_fail_T_36};
      end else begin
        exe_stage_lsu_cache_0_stage_deqBits_wb_res <= exe_stage_lsu_cache_0_stage__deqBits_wb_res_res_pre_res_T_63;
      end
    end
    if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 368:66]
      exe_stage_lsu_cache_0_stage_deqBits_is_load_amo <= exe_stage_lsu_cache_0_stage__deqBits_is_load_amo_T_31; // @[DcacheStage.scala 396:25]
    end
    if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 368:66]
      exe_stage_lsu_cache_0_stage_deqBits_is_flw <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_flw; // @[DcacheStage.scala 397:25]
    end
    if (exe_stage_lsu_cache_0_stage__T_134) begin // @[DcacheStage.scala 368:66]
      exe_stage_lsu_cache_0_stage_deqBits_is_fld <= exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fld; // @[DcacheStage.scala 398:25]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_stage__T_92 & exe_stage_lsu_cache_0_stage__T_134 &
          exe_stage_lsu_cache_0_stage__datEnW_0_T_58 & exe_stage_lsu_cache_0_stage__T_167 &
          exe_stage_lsu_cache_0_stage__T_168) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at DcacheStage.scala:164 assert( pipeStage1Bits.fun.is_dubl | pipeStage1Bits.fun.is_word )\n"
            ); // @[DcacheStage.scala 164:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_stage__T_165 & (~exe_stage_lsu_cache_0_stage__T_92 &
          exe_stage_lsu_cache_0_stage__T_134 & exe_stage_lsu_cache_0_stage__datEnW_0_T_58 &
          exe_stage_lsu_cache_0_stage__T_167)) begin
          $fatal; // @[DcacheStage.scala 164:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (exe_stage_lsu_cache_0_stage_pipeStage1Valid & exe_stage_lsu_cache_0_stage__T_167)) begin
          $fatal; // @[DcacheStage.scala 242:36]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_stage__T_202 & exe_stage_lsu_cache_0_stage__T_253 & exe_stage_lsu_cache_0_stage__T_167
          ) begin
          $fwrite(32'h80000002,"Warning, l2 will never request a empty probe, is it in writeback unit?\n"); // @[DcacheStage.scala 283:63]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_lsu_cache_0_clock) begin
    if (exe_stage_lsu_cache_0_reset) begin // @[Dcache.scala 138:23]
      exe_stage_lsu_cache_0_sbBuff_0_paddr <= 32'h0; // @[Dcache.scala 138:23]
    end else if (exe_stage_lsu_cache_0__T_1) begin // @[Dcache.scala 155:23]
      if (~exe_stage_lsu_cache_0_io_deq_bits_chkIdx) begin // @[Dcache.scala 156:33]
        exe_stage_lsu_cache_0_sbBuff_0_paddr <= 32'h0; // @[Dcache.scala 156:33]
      end else begin
        exe_stage_lsu_cache_0_sbBuff_0_paddr <= exe_stage_lsu_cache_0__GEN_100;
      end
    end else begin
      exe_stage_lsu_cache_0_sbBuff_0_paddr <= exe_stage_lsu_cache_0__GEN_100;
    end
    if (exe_stage_lsu_cache_0_reset) begin // @[Dcache.scala 138:23]
      exe_stage_lsu_cache_0_sbBuff_1_paddr <= 32'h0; // @[Dcache.scala 138:23]
    end else if (exe_stage_lsu_cache_0__T_1) begin // @[Dcache.scala 155:23]
      if (exe_stage_lsu_cache_0_io_deq_bits_chkIdx) begin // @[Dcache.scala 156:33]
        exe_stage_lsu_cache_0_sbBuff_1_paddr <= 32'h0; // @[Dcache.scala 156:33]
      end else begin
        exe_stage_lsu_cache_0_sbBuff_1_paddr <= exe_stage_lsu_cache_0__GEN_101;
      end
    end else begin
      exe_stage_lsu_cache_0_sbBuff_1_paddr <= exe_stage_lsu_cache_0__GEN_101;
    end
    if (exe_stage_lsu_cache_0_reset) begin // @[Dcache.scala 139:24]
      exe_stage_lsu_cache_0_sbValid_0 <= 1'h0; // @[Dcache.scala 139:24]
    end else if (exe_stage_lsu_cache_0__T_1) begin // @[Dcache.scala 155:23]
      if (~exe_stage_lsu_cache_0_io_deq_bits_chkIdx) begin // @[Dcache.scala 157:33]
        exe_stage_lsu_cache_0_sbValid_0 <= 1'h0; // @[Dcache.scala 157:33]
      end else begin
        exe_stage_lsu_cache_0_sbValid_0 <= exe_stage_lsu_cache_0__GEN_194;
      end
    end else begin
      exe_stage_lsu_cache_0_sbValid_0 <= exe_stage_lsu_cache_0__GEN_194;
    end
    if (exe_stage_lsu_cache_0_reset) begin // @[Dcache.scala 139:24]
      exe_stage_lsu_cache_0_sbValid_1 <= 1'h0; // @[Dcache.scala 139:24]
    end else if (exe_stage_lsu_cache_0__T_1) begin // @[Dcache.scala 155:23]
      if (exe_stage_lsu_cache_0_io_deq_bits_chkIdx) begin // @[Dcache.scala 157:33]
        exe_stage_lsu_cache_0_sbValid_1 <= 1'h0; // @[Dcache.scala 157:33]
      end else begin
        exe_stage_lsu_cache_0_sbValid_1 <= exe_stage_lsu_cache_0__GEN_195;
      end
    end else begin
      exe_stage_lsu_cache_0_sbValid_1 <= exe_stage_lsu_cache_0__GEN_195;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0__T_1 & exe_stage_lsu_cache_0__T_5 & exe_stage_lsu_cache_0__T_6) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Dcache.scala:161 when( io.deq.fire ) { assert(~isSBEmpty) }\n"
            ); // @[Dcache.scala 161:31]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0__T_3 & (exe_stage_lsu_cache_0__T_1 & exe_stage_lsu_cache_0__T_5)) begin
          $fatal; // @[Dcache.scala 161:31]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_sbValid_0 & exe_stage_lsu_cache_0__T_5 & exe_stage_lsu_cache_0__T_15) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Dcache.scala:168 assert( sbBuff.count( (x: Dcache_Enq_Bundle) => (x.paddr === sbBuff(i).paddr) ) === 1.U )\n"
            ); // @[Dcache.scala 168:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0__T_12 & (exe_stage_lsu_cache_0_sbValid_0 & exe_stage_lsu_cache_0__T_5)) begin
          $fatal; // @[Dcache.scala 168:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_sbValid_1 & exe_stage_lsu_cache_0__T_5 & exe_stage_lsu_cache_0__T_24) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Dcache.scala:168 assert( sbBuff.count( (x: Dcache_Enq_Bundle) => (x.paddr === sbBuff(i).paddr) ) === 1.U )\n"
            ); // @[Dcache.scala 168:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0__T_21 & (exe_stage_lsu_cache_0_sbValid_1 & exe_stage_lsu_cache_0__T_5)) begin
          $fatal; // @[Dcache.scala 168:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_reload_fifo_io_enq_valid & exe_stage_lsu_cache_0__T_5 & exe_stage_lsu_cache_0__T_27
          ) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at Dcache, Pipeline stuck!\n    at Dcache.scala:281 when(reload_fifo.io.enq.valid) {assert(reload_fifo.io.enq.ready, \"Assert Failed at Dcache, Pipeline stuck!\")}\n"
            ); // @[Dcache.scala 281:41]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_reload_fifo_io_enq_ready & (exe_stage_lsu_cache_0_reload_fifo_io_enq_valid &
          exe_stage_lsu_cache_0__T_5)) begin
          $fatal; // @[Dcache.scala 281:41]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_rtn_fifo_io_enq_valid & exe_stage_lsu_cache_0__T_5 & exe_stage_lsu_cache_0__T_30
          ) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed at Dcache, Pipeline stuck!\n    at Dcache.scala:282 when(rtn_fifo.io.enq.valid) {assert(rtn_fifo.io.enq.ready, \"Assert Failed at Dcache, Pipeline stuck!\")}\n"
            ); // @[Dcache.scala 282:38]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu_cache_0_rtn_fifo_io_enq_ready & (exe_stage_lsu_cache_0_rtn_fifo_io_enq_valid &
          exe_stage_lsu_cache_0__T_5)) begin
          $fatal; // @[Dcache.scala 282:38]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_lsu_lu_wb_fifo_ram_rd0_clock) begin
    if (exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_en & exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_mask) begin
      exe_stage_lsu_lu_wb_fifo_ram_rd0[exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_addr] <=
        exe_stage_lsu_lu_wb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_lu_wb_fifo_ram_res_clock) begin
    if (exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_en & exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_mask) begin
      exe_stage_lsu_lu_wb_fifo_ram_res[exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_addr] <=
        exe_stage_lsu_lu_wb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_lu_wb_fifo_clock) begin
    if (exe_stage_lsu_lu_wb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_lu_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_lu_wb_fifo__T) begin // @[Decoupled.scala 295:27]
      if (exe_stage_lsu_lu_wb_fifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (exe_stage_lsu_lu_wb_fifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          exe_stage_lsu_lu_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          exe_stage_lsu_lu_wb_fifo_maybe_full <= exe_stage_lsu_lu_wb_fifo__do_enq_T;
        end
      end else begin
        exe_stage_lsu_lu_wb_fifo_maybe_full <= exe_stage_lsu_lu_wb_fifo__do_enq_T;
      end
    end
  end
  always @(posedge exe_stage_lsu_flu_wb_fifo_clock) begin
    if (exe_stage_lsu_flu_wb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_flu_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_flu_wb_fifo__T) begin // @[Decoupled.scala 295:27]
      if (exe_stage_lsu_flu_wb_fifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (exe_stage_lsu_flu_wb_fifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          exe_stage_lsu_flu_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          exe_stage_lsu_flu_wb_fifo_maybe_full <= exe_stage_lsu_flu_wb_fifo__do_enq_T;
        end
      end else begin
        exe_stage_lsu_flu_wb_fifo_maybe_full <= exe_stage_lsu_flu_wb_fifo__do_enq_T;
      end
    end
  end
  always @(posedge exe_stage_lsu_su_wb_fifo_ram_rd0_clock) begin
    if (exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_en & exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_mask) begin
      exe_stage_lsu_su_wb_fifo_ram_rd0[exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_addr] <=
        exe_stage_lsu_su_wb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_su_wb_fifo_ram_res_clock) begin
    if (exe_stage_lsu_su_wb_fifo_ram_res_MPORT_en & exe_stage_lsu_su_wb_fifo_ram_res_MPORT_mask) begin
      exe_stage_lsu_su_wb_fifo_ram_res[exe_stage_lsu_su_wb_fifo_ram_res_MPORT_addr] <=
        exe_stage_lsu_su_wb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_su_wb_fifo_clock) begin
    if (exe_stage_lsu_su_wb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_su_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_su_wb_fifo__T) begin // @[Decoupled.scala 295:27]
      if (exe_stage_lsu_su_wb_fifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (exe_stage_lsu_su_wb_fifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          exe_stage_lsu_su_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          exe_stage_lsu_su_wb_fifo_maybe_full <= exe_stage_lsu_su_wb_fifo__do_enq_T;
        end
      end else begin
        exe_stage_lsu_su_wb_fifo_maybe_full <= exe_stage_lsu_su_wb_fifo__do_enq_T;
      end
    end
  end
  always @(posedge exe_stage_lsu_fe_wb_fifo_ram_rd0_clock) begin
    if (exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_en & exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_mask) begin
      exe_stage_lsu_fe_wb_fifo_ram_rd0[exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_addr] <=
        exe_stage_lsu_fe_wb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_fe_wb_fifo_ram_res_clock) begin
    if (exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_en & exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_mask) begin
      exe_stage_lsu_fe_wb_fifo_ram_res[exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_addr] <=
        exe_stage_lsu_fe_wb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_lsu_fe_wb_fifo_clock) begin
    if (exe_stage_lsu_fe_wb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_lsu_fe_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_lsu_fe_wb_fifo__T) begin // @[Decoupled.scala 295:27]
      if (exe_stage_lsu_fe_wb_fifo__empty_T) begin // @[Decoupled.scala 317:17]
        if (exe_stage_lsu_fe_wb_fifo_io_deq_ready) begin // @[Decoupled.scala 320:26]
          exe_stage_lsu_fe_wb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          exe_stage_lsu_fe_wb_fifo_maybe_full <= exe_stage_lsu_fe_wb_fifo__do_enq_T;
        end
      end else begin
        exe_stage_lsu_fe_wb_fifo_maybe_full <= exe_stage_lsu_fe_wb_fifo__do_enq_T;
      end
    end
  end
  always @(posedge exe_stage_lsu_clock) begin
    if (exe_stage_lsu_reset) begin // @[Lsu.scala 73:27]
      exe_stage_lsu_trans_kill <= 1'h0; // @[Lsu.scala 73:27]
    end else begin
      exe_stage_lsu_trans_kill <= exe_stage_lsu__GEN_378;
    end
    if (exe_stage_lsu_reset) begin // @[Lsu.scala 325:33]
      exe_stage_lsu_is_chnc_busy_0 <= 1'h0; // @[Lsu.scala 325:33]
    end else if (exe_stage_lsu__is_release_done_T) begin // @[Lsu.scala 328:67]
      if (exe_stage_lsu_is_release_done_0) begin // @[Lsu.scala 328:91]
        exe_stage_lsu_is_chnc_busy_0 <= 1'h0;
      end else begin
        exe_stage_lsu_is_chnc_busy_0 <= 1'h1;
      end
    end
    if (exe_stage_lsu_reset) begin // @[Edges.scala 228:27]
      exe_stage_lsu_is_release_done_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (exe_stage_lsu__is_release_done_T) begin // @[Edges.scala 234:17]
      if (exe_stage_lsu_is_release_done_first) begin // @[Edges.scala 235:21]
        exe_stage_lsu_is_release_done_counter <= exe_stage_lsu_is_release_done_beats1;
      end else begin
        exe_stage_lsu_is_release_done_counter <= exe_stage_lsu_is_release_done_counter1;
      end
    end
    if (exe_stage_lsu_reset) begin // @[Lsu.scala 485:33]
      exe_stage_lsu_isAccessFaultReg <= 1'h0; // @[Lsu.scala 485:33]
    end else if (exe_stage_lsu_io_flush) begin // @[Lsu.scala 490:20]
      exe_stage_lsu_isAccessFaultReg <= 1'h0; // @[Lsu.scala 491:22]
    end else if (exe_stage_lsu__T_67) begin // @[Lsu.scala 494:46]
      exe_stage_lsu_isAccessFaultReg <= exe_stage_lsu_io_mmu_lsu_bits_is_access_fault; // @[Lsu.scala 495:22]
    end
    if (exe_stage_lsu_reset) begin // @[Lsu.scala 486:33]
      exe_stage_lsu_isPagingFault <= 1'h0; // @[Lsu.scala 486:33]
    end else if (exe_stage_lsu_io_flush) begin // @[Lsu.scala 490:20]
      exe_stage_lsu_isPagingFault <= 1'h0; // @[Lsu.scala 492:22]
    end else if (exe_stage_lsu__T_67) begin // @[Lsu.scala 494:46]
      exe_stage_lsu_isPagingFault <= exe_stage_lsu_io_mmu_lsu_bits_is_paging_fault; // @[Lsu.scala 496:22]
    end
    if (exe_stage_lsu_reset) begin // @[Lsu.scala 487:27]
      exe_stage_lsu_isMisAlign <= 1'h0; // @[Lsu.scala 487:27]
    end else if (exe_stage_lsu_io_flush) begin // @[Lsu.scala 490:20]
      exe_stage_lsu_isMisAlign <= 1'h0; // @[Lsu.scala 493:22]
    end else if (exe_stage_lsu__T_67) begin // @[Lsu.scala 494:46]
      exe_stage_lsu_isMisAlign <= exe_stage_lsu__addrTransIO_valid_T_44; // @[Lsu.scala 497:22]
    end
    if (!(exe_stage_lsu_io_flush)) begin // @[Lsu.scala 490:20]
      if (exe_stage_lsu__T_67) begin // @[Lsu.scala 494:46]
        exe_stage_lsu_trapAddrReg <= exe_stage_lsu_io_lsu_iss_exe_bits_param_dat_op1; // @[Lsu.scala 498:22]
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & exe_stage_lsu__T_47) begin
          $fatal; // @[Lsu.scala 342:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_cache_0_io_deq_bits_is_load_amo & exe_stage_lsu__T_47 & exe_stage_lsu__T_54) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Lsu.scala:422 when( cache(i).io.deq.bits.is_load_amo ) { assert(cache(i).io.deq.fire === lu_wb_arb.io.in(i).fire) }\n"
            ); // @[Lsu.scala 422:54]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu__T_51 & (exe_stage_lsu_cache_0_io_deq_bits_is_load_amo & exe_stage_lsu__T_47)) begin
          $fatal; // @[Lsu.scala 422:54]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_system_io_deq_bits_is_load_amo & exe_stage_lsu__T_47 & exe_stage_lsu__T_60) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Lsu.scala:428 when( system.io.deq.bits.is_load_amo ) { assert(system.io.deq.fire === lu_wb_arb.io.in(bk).fire) }\n"
            ); // @[Lsu.scala 428:50]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu__T_57 & (exe_stage_lsu_system_io_deq_bits_is_load_amo & exe_stage_lsu__T_47)) begin
          $fatal; // @[Lsu.scala 428:50]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_lsu_periph_io_deq_bits_is_load_amo & exe_stage_lsu__T_47 & exe_stage_lsu__T_66) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Lsu.scala:433 when( periph.io.deq.bits.is_load_amo ) { assert(periph.io.deq.fire === lu_wb_arb.io.in(bk+1).fire) }\n"
            ); // @[Lsu.scala 433:50]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_lsu__T_63 & (exe_stage_lsu_periph_io_deq_bits_is_load_amo & exe_stage_lsu__T_47)) begin
          $fatal; // @[Lsu.scala 433:50]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_clock) begin
    if (exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_en & exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_mask) begin
      exe_stage_csr_csr_exe_iwb_fifo_ram_rd0[exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_addr] <=
        exe_stage_csr_csr_exe_iwb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_csr_csr_exe_iwb_fifo_ram_res_clock) begin
    if (exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_en & exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_mask) begin
      exe_stage_csr_csr_exe_iwb_fifo_ram_res[exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_addr] <=
        exe_stage_csr_csr_exe_iwb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_csr_csr_exe_iwb_fifo_clock) begin
    if (exe_stage_csr_csr_exe_iwb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_csr_csr_exe_iwb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_csr_csr_exe_iwb_fifo__T) begin // @[Decoupled.scala 295:27]
      exe_stage_csr_csr_exe_iwb_fifo_maybe_full <= exe_stage_csr_csr_exe_iwb_fifo__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_csr_csr_op_fifo_ram_addr_clock) begin
    if (exe_stage_csr_csr_op_fifo_ram_addr_MPORT_en & exe_stage_csr_csr_op_fifo_ram_addr_MPORT_mask) begin
      exe_stage_csr_csr_op_fifo_ram_addr[exe_stage_csr_csr_op_fifo_ram_addr_MPORT_addr] <=
        exe_stage_csr_csr_op_fifo_ram_addr_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_csr_csr_op_fifo_ram_dat_i_clock) begin
    if (exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_en & exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_mask) begin
      exe_stage_csr_csr_op_fifo_ram_dat_i[exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_addr] <=
        exe_stage_csr_csr_op_fifo_ram_dat_i_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_csr_csr_op_fifo_ram_op_rw_clock) begin
    if (exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_en & exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_mask) begin
      exe_stage_csr_csr_op_fifo_ram_op_rw[exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_addr] <=
        exe_stage_csr_csr_op_fifo_ram_op_rw_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_csr_csr_op_fifo_ram_op_rs_clock) begin
    if (exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_en & exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_mask) begin
      exe_stage_csr_csr_op_fifo_ram_op_rs[exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_addr] <=
        exe_stage_csr_csr_op_fifo_ram_op_rs_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_csr_csr_op_fifo_ram_op_rc_clock) begin
    if (exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_en & exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_mask) begin
      exe_stage_csr_csr_op_fifo_ram_op_rc[exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_addr] <=
        exe_stage_csr_csr_op_fifo_ram_op_rc_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_csr_csr_op_fifo_clock) begin
    if (exe_stage_csr_csr_op_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_csr_csr_op_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_csr_csr_op_fifo__T) begin // @[Decoupled.scala 295:27]
      exe_stage_csr_csr_op_fifo_maybe_full <= exe_stage_csr_csr_op_fifo__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_clock) begin
    if (exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_en & exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_mask
      ) begin
      exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0[exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_addr] <=
        exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_clock) begin
    if (exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_en & exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_mask
      ) begin
      exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res[exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_addr] <=
        exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res_MPORT_data; // @[Decoupled.scala 275:95]
    end
  end
  always @(posedge exe_stage_mulDiv_0_mul_exe_iwb_fifo_clock) begin
    if (exe_stage_mulDiv_0_mul_exe_iwb_fifo_reset) begin // @[Decoupled.scala 278:27]
      exe_stage_mulDiv_0_mul_exe_iwb_fifo_maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (exe_stage_mulDiv_0_mul_exe_iwb_fifo__T) begin // @[Decoupled.scala 295:27]
      exe_stage_mulDiv_0_mul_exe_iwb_fifo_maybe_full <= exe_stage_mulDiv_0_mul_exe_iwb_fifo__do_enq_T; // @[Decoupled.scala 296:16]
    end
  end
  always @(posedge exe_stage_mulDiv_0_dividor_algDivider_clock) begin
    if (exe_stage_mulDiv_0_dividor_algDivider_reset) begin // @[Mul.scala 582:26]
      exe_stage_mulDiv_0_dividor_algDivider_isDivBusy <= 1'h0; // @[Mul.scala 582:26]
    end else if (exe_stage_mulDiv_0_dividor_algDivider__T_5) begin // @[Mul.scala 596:34]
      exe_stage_mulDiv_0_dividor_algDivider_isDivBusy <= 1'h0; // @[Mul.scala 597:15]
    end else begin
      exe_stage_mulDiv_0_dividor_algDivider_isDivBusy <= exe_stage_mulDiv_0_dividor_algDivider__GEN_2;
    end
    if (exe_stage_mulDiv_0_dividor_algDivider_reset) begin // @[Mul.scala 584:20]
      exe_stage_mulDiv_0_dividor_algDivider_cnt <= 7'h0; // @[Mul.scala 584:20]
    end else if (exe_stage_mulDiv_0_dividor_algDivider__T_1) begin // @[Mul.scala 585:34]
      exe_stage_mulDiv_0_dividor_algDivider_cnt <= 7'h0; // @[Mul.scala 586:9]
    end else if (exe_stage_mulDiv_0_dividor_algDivider__T_3) begin // @[Mul.scala 587:43]
      exe_stage_mulDiv_0_dividor_algDivider_cnt <= exe_stage_mulDiv_0_dividor_algDivider__cnt_T_1; // @[Mul.scala 588:9]
    end
    exe_stage_mulDiv_0_dividor_algDivider_dividend <= exe_stage_mulDiv_0_dividor_algDivider__GEN_4[127:0];
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Mul.scala 616:23]
      if (exe_stage_mulDiv_0_dividor_isUsiPre) begin // @[Mul.scala 459:8]
        if (exe_stage_mulDiv_0_dividor_is32wPre) begin // @[Mul.scala 461:10]
          exe_stage_mulDiv_0_dividor_algDivider_divisor <= {{32'd0}, exe_stage_mulDiv_0_dividor__divisor_load_T};
        end else begin
          exe_stage_mulDiv_0_dividor_algDivider_divisor <= exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2;
        end
      end else if (exe_stage_mulDiv_0_dividor_is32wPre) begin // @[Mul.scala 462:10]
        exe_stage_mulDiv_0_dividor_algDivider_divisor <= exe_stage_mulDiv_0_dividor__divisor_load_T_10;
      end else if (exe_stage_mulDiv_0_dividor__divisor_load_T_11) begin // @[Mul.scala 465:12]
        exe_stage_mulDiv_0_dividor_algDivider_divisor <= exe_stage_mulDiv_0_dividor__divisor_load_T_14;
      end else begin
        exe_stage_mulDiv_0_dividor_algDivider_divisor <= exe_stage_mulDiv_0_dividor_io_enq_bits_param_dat_op2;
      end
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_div <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_div; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divu <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divu; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_rem <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_rem; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remu <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remu; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divw <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divw; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divuw <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_divuw; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remw <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remw; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remuw <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_fun_remuw; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_rd0 <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_rd0; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_dat_op1 <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_dat_op1; // @[Reg.scala 20:22]
    end
    if (exe_stage_mulDiv_0_dividor_algDivider__T) begin // @[Reg.scala 20:18]
      exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_dat_op2 <=
        exe_stage_mulDiv_0_dividor_algDivider_io_enq_bits_param_dat_op2; // @[Reg.scala 20:22]
    end
  end
  always @(posedge exe_stage_mulDiv_0_dividor_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_mulDiv_0_dividor__T & exe_stage_mulDiv_0_dividor__T_9 & exe_stage_mulDiv_0_dividor__T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Mul.scala:430 when( io.enq.fire ) { assert( io.enq.bits.fun.isDiv ) }\n"); // @[Mul.scala 430:31]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_mulDiv_0_dividor__T_7 & (exe_stage_mulDiv_0_dividor__T & exe_stage_mulDiv_0_dividor__T_9)) begin
          $fatal; // @[Mul.scala 430:31]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge exe_stage_fpu_0_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (exe_stage_fpu_0__T_2 & exe_stage_fpu_0__T_3) begin
          $fwrite(32'h80000002,"Assertion failed\n    at FAlu.scala:282 assert( ~io.fpu_iss_exe.valid )\n"); // @[FAlu.scala 282:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~exe_stage_fpu_0__T & exe_stage_fpu_0__T_2) begin
          $fatal; // @[FAlu.scala 282:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge iwb_stage_iReg_clock) begin
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_0 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h0 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_0 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_118) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_0 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_0 <= iwb_stage_iReg__GEN_1620;
      end
    end else begin
      iwb_stage_iReg_log_reg_0 <= iwb_stage_iReg__GEN_1620;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_1 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h1 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_1 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_119) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_1 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_1 <= iwb_stage_iReg__GEN_1621;
      end
    end else begin
      iwb_stage_iReg_log_reg_1 <= iwb_stage_iReg__GEN_1621;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_2 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h2 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_2 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_120) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_2 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_2 <= iwb_stage_iReg__GEN_1622;
      end
    end else begin
      iwb_stage_iReg_log_reg_2 <= iwb_stage_iReg__GEN_1622;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_3 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h3 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_3 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_121) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_3 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_3 <= iwb_stage_iReg__GEN_1623;
      end
    end else begin
      iwb_stage_iReg_log_reg_3 <= iwb_stage_iReg__GEN_1623;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_4 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h4 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_4 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_122) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_4 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_4 <= iwb_stage_iReg__GEN_1624;
      end
    end else begin
      iwb_stage_iReg_log_reg_4 <= iwb_stage_iReg__GEN_1624;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_5 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h5 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_5 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_123) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_5 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_5 <= iwb_stage_iReg__GEN_1625;
      end
    end else begin
      iwb_stage_iReg_log_reg_5 <= iwb_stage_iReg__GEN_1625;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_6 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h6 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_6 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_124) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_6 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_6 <= iwb_stage_iReg__GEN_1626;
      end
    end else begin
      iwb_stage_iReg_log_reg_6 <= iwb_stage_iReg__GEN_1626;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_7 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h7 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_7 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_125) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_7 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_7 <= iwb_stage_iReg__GEN_1627;
      end
    end else begin
      iwb_stage_iReg_log_reg_7 <= iwb_stage_iReg__GEN_1627;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_8 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h8 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_8 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_126) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_8 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_8 <= iwb_stage_iReg__GEN_1628;
      end
    end else begin
      iwb_stage_iReg_log_reg_8 <= iwb_stage_iReg__GEN_1628;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_9 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h9 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_9 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_127) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_9 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_9 <= iwb_stage_iReg__GEN_1629;
      end
    end else begin
      iwb_stage_iReg_log_reg_9 <= iwb_stage_iReg__GEN_1629;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_10 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'ha == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_10 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_128) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_10 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_10 <= iwb_stage_iReg__GEN_1630;
      end
    end else begin
      iwb_stage_iReg_log_reg_10 <= iwb_stage_iReg__GEN_1630;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_11 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'hb == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_11 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_129) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_11 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_11 <= iwb_stage_iReg__GEN_1631;
      end
    end else begin
      iwb_stage_iReg_log_reg_11 <= iwb_stage_iReg__GEN_1631;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_12 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'hc == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_12 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_130) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_12 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_12 <= iwb_stage_iReg__GEN_1632;
      end
    end else begin
      iwb_stage_iReg_log_reg_12 <= iwb_stage_iReg__GEN_1632;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_13 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'hd == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_13 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_131) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_13 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_13 <= iwb_stage_iReg__GEN_1633;
      end
    end else begin
      iwb_stage_iReg_log_reg_13 <= iwb_stage_iReg__GEN_1633;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_14 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'he == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_14 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_132) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_14 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_14 <= iwb_stage_iReg__GEN_1634;
      end
    end else begin
      iwb_stage_iReg_log_reg_14 <= iwb_stage_iReg__GEN_1634;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_15 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'hf == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_15 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_133) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_15 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_15 <= iwb_stage_iReg__GEN_1635;
      end
    end else begin
      iwb_stage_iReg_log_reg_15 <= iwb_stage_iReg__GEN_1635;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_16 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h10 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_16 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_134) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_16 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_16 <= iwb_stage_iReg__GEN_1636;
      end
    end else begin
      iwb_stage_iReg_log_reg_16 <= iwb_stage_iReg__GEN_1636;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_17 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h11 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_17 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_135) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_17 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_17 <= iwb_stage_iReg__GEN_1637;
      end
    end else begin
      iwb_stage_iReg_log_reg_17 <= iwb_stage_iReg__GEN_1637;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_18 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h12 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_18 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_136) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_18 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_18 <= iwb_stage_iReg__GEN_1638;
      end
    end else begin
      iwb_stage_iReg_log_reg_18 <= iwb_stage_iReg__GEN_1638;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_19 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h13 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_19 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_137) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_19 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_19 <= iwb_stage_iReg__GEN_1639;
      end
    end else begin
      iwb_stage_iReg_log_reg_19 <= iwb_stage_iReg__GEN_1639;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_20 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h14 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_20 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_138) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_20 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_20 <= iwb_stage_iReg__GEN_1640;
      end
    end else begin
      iwb_stage_iReg_log_reg_20 <= iwb_stage_iReg__GEN_1640;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_21 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h15 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_21 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_139) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_21 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_21 <= iwb_stage_iReg__GEN_1641;
      end
    end else begin
      iwb_stage_iReg_log_reg_21 <= iwb_stage_iReg__GEN_1641;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_22 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h16 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_22 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_140) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_22 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_22 <= iwb_stage_iReg__GEN_1642;
      end
    end else begin
      iwb_stage_iReg_log_reg_22 <= iwb_stage_iReg__GEN_1642;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_23 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h17 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_23 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_141) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_23 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_23 <= iwb_stage_iReg__GEN_1643;
      end
    end else begin
      iwb_stage_iReg_log_reg_23 <= iwb_stage_iReg__GEN_1643;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_24 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h18 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_24 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_142) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_24 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_24 <= iwb_stage_iReg__GEN_1644;
      end
    end else begin
      iwb_stage_iReg_log_reg_24 <= iwb_stage_iReg__GEN_1644;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_25 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h19 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_25 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_143) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_25 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_25 <= iwb_stage_iReg__GEN_1645;
      end
    end else begin
      iwb_stage_iReg_log_reg_25 <= iwb_stage_iReg__GEN_1645;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_26 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h1a == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_26 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_144) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_26 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_26 <= iwb_stage_iReg__GEN_1646;
      end
    end else begin
      iwb_stage_iReg_log_reg_26 <= iwb_stage_iReg__GEN_1646;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_27 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h1b == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_27 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_145) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_27 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_27 <= iwb_stage_iReg__GEN_1647;
      end
    end else begin
      iwb_stage_iReg_log_reg_27 <= iwb_stage_iReg__GEN_1647;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_28 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h1c == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_28 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_146) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_28 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_28 <= iwb_stage_iReg__GEN_1648;
      end
    end else begin
      iwb_stage_iReg_log_reg_28 <= iwb_stage_iReg__GEN_1648;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_29 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h1d == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_29 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_147) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_29 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_29 <= iwb_stage_iReg__GEN_1649;
      end
    end else begin
      iwb_stage_iReg_log_reg_29 <= iwb_stage_iReg__GEN_1649;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_30 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h1e == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_30 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_148) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_30 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_30 <= iwb_stage_iReg__GEN_1650;
      end
    end else begin
      iwb_stage_iReg_log_reg_30 <= iwb_stage_iReg__GEN_1650;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_31 <= 2'h3; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h1f == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_31 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_149) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_31 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_31 <= iwb_stage_iReg__GEN_1651;
      end
    end else begin
      iwb_stage_iReg_log_reg_31 <= iwb_stage_iReg__GEN_1651;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 101:12]
      iwb_stage_iReg_log_reg_32 <= 2'h0; // @[Regfiles.scala 101:12]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 225:66]
      if (6'h20 == iwb_stage_iReg_io_commit_0_phy) begin // @[Regfiles.scala 232:23]
        iwb_stage_iReg_log_reg_32 <= 2'h3; // @[Regfiles.scala 232:23]
      end else if (iwb_stage_iReg__T_150) begin // @[Regfiles.scala 229:35]
        iwb_stage_iReg_log_reg_32 <= 2'h0; // @[Regfiles.scala 229:47]
      end else begin
        iwb_stage_iReg_log_reg_32 <= iwb_stage_iReg__GEN_1652;
      end
    end else begin
      iwb_stage_iReg_log_reg_32 <= iwb_stage_iReg__GEN_1652;
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_0 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h0 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_0 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_1 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h1 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_1 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_2 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h2 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_2 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_3 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h3 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_3 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_4 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h4 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_4 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_5 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h5 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_5 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_6 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h6 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_6 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_7 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h7 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_7 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_8 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h8 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_8 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_9 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h9 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_9 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_10 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'ha == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_10 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_11 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'hb == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_11 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_12 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'hc == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_12 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_13 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'hd == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_13 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_14 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'he == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_14 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_15 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'hf == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_15 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_16 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h10 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_16 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_17 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h11 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_17 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_18 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h12 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_18 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_19 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h13 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_19 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_20 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h14 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_20 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_21 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h15 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_21 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_22 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h16 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_22 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_23 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h17 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_23 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_24 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h18 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_24 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_25 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h19 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_25 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_26 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h1a == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_26 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_27 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h1b == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_27 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_28 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h1c == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_28 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_29 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h1d == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_29 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_30 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h1e == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_30 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_31 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h1f == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_31 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 114:26]
      iwb_stage_iReg_files_reg_32 <= 64'h0; // @[Regfiles.scala 114:26]
    end else if (iwb_stage_iReg__T_108) begin // @[Regfiles.scala 201:38]
      if (6'h20 == iwb_stage_iReg_io_exe_writeBack_0_bits_rd0) begin // @[Regfiles.scala 205:22]
        iwb_stage_iReg_files_reg_32 <= iwb_stage_iReg_io_exe_writeBack_0_bits_res; // @[Regfiles.scala 205:22]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_0 <= 6'h0; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_41) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_0 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_0 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_0 <= iwb_stage_iReg_archit_ptr_0; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h0 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_0 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_1 <= 6'h1; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_43) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_1 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_1 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_1 <= iwb_stage_iReg_archit_ptr_1; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h1 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_1 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_2 <= 6'h2; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_45) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_2 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_2 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_2 <= iwb_stage_iReg_archit_ptr_2; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h2 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_2 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_3 <= 6'h3; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_47) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_3 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_3 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_3 <= iwb_stage_iReg_archit_ptr_3; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h3 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_3 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_4 <= 6'h4; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_49) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_4 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_4 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_4 <= iwb_stage_iReg_archit_ptr_4; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h4 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_4 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_5 <= 6'h5; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_51) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_5 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_5 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_5 <= iwb_stage_iReg_archit_ptr_5; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h5 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_5 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_6 <= 6'h6; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_53) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_6 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_6 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_6 <= iwb_stage_iReg_archit_ptr_6; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h6 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_6 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_7 <= 6'h7; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_55) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_7 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_7 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_7 <= iwb_stage_iReg_archit_ptr_7; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h7 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_7 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_8 <= 6'h8; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_57) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_8 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_8 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_8 <= iwb_stage_iReg_archit_ptr_8; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h8 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_8 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_9 <= 6'h9; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_59) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_9 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_9 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_9 <= iwb_stage_iReg_archit_ptr_9; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h9 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_9 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_10 <= 6'ha; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_61) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_10 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_10 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_10 <= iwb_stage_iReg_archit_ptr_10; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'ha == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_10 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_11 <= 6'hb; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_63) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_11 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_11 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_11 <= iwb_stage_iReg_archit_ptr_11; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'hb == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_11 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_12 <= 6'hc; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_65) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_12 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_12 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_12 <= iwb_stage_iReg_archit_ptr_12; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'hc == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_12 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_13 <= 6'hd; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_67) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_13 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_13 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_13 <= iwb_stage_iReg_archit_ptr_13; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'hd == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_13 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_14 <= 6'he; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_69) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_14 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_14 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_14 <= iwb_stage_iReg_archit_ptr_14; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'he == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_14 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_15 <= 6'hf; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_71) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_15 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_15 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_15 <= iwb_stage_iReg_archit_ptr_15; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'hf == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_15 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_16 <= 6'h10; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_73) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_16 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_16 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_16 <= iwb_stage_iReg_archit_ptr_16; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h10 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_16 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_17 <= 6'h11; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_75) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_17 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_17 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_17 <= iwb_stage_iReg_archit_ptr_17; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h11 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_17 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_18 <= 6'h12; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_77) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_18 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_18 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_18 <= iwb_stage_iReg_archit_ptr_18; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h12 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_18 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_19 <= 6'h13; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_79) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_19 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_19 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_19 <= iwb_stage_iReg_archit_ptr_19; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h13 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_19 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_20 <= 6'h14; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_81) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_20 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_20 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_20 <= iwb_stage_iReg_archit_ptr_20; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h14 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_20 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_21 <= 6'h15; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_83) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_21 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_21 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_21 <= iwb_stage_iReg_archit_ptr_21; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h15 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_21 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_22 <= 6'h16; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_85) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_22 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_22 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_22 <= iwb_stage_iReg_archit_ptr_22; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h16 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_22 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_23 <= 6'h17; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_87) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_23 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_23 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_23 <= iwb_stage_iReg_archit_ptr_23; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h17 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_23 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_24 <= 6'h18; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_89) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_24 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_24 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_24 <= iwb_stage_iReg_archit_ptr_24; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h18 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_24 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_25 <= 6'h19; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_91) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_25 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_25 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_25 <= iwb_stage_iReg_archit_ptr_25; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h19 == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_25 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_26 <= 6'h1a; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_93) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_26 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_26 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_26 <= iwb_stage_iReg_archit_ptr_26; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h1a == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_26 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_27 <= 6'h1b; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_95) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_27 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_27 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_27 <= iwb_stage_iReg_archit_ptr_27; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h1b == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_27 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_28 <= 6'h1c; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_97) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_28 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_28 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_28 <= iwb_stage_iReg_archit_ptr_28; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h1c == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_28 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_29 <= 6'h1d; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_99) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_29 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_29 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_29 <= iwb_stage_iReg_archit_ptr_29; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h1d == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_29 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_30 <= 6'h1e; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_101) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_30 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_30 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_30 <= iwb_stage_iReg_archit_ptr_30; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h1e == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_30 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 125:27]
      iwb_stage_iReg_rename_ptr_31 <= 6'h1f; // @[Regfiles.scala 125:27]
    end else if (iwb_stage_iReg__T_39) begin // @[Regfiles.scala 172:65]
      if (iwb_stage_iReg__T_103) begin // @[Regfiles.scala 180:61]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_rename_ptr_31 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_rename_ptr_31 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end else begin
        iwb_stage_iReg_rename_ptr_31 <= iwb_stage_iReg_archit_ptr_31; // @[Regfiles.scala 174:23]
      end
    end else if (iwb_stage_iReg__T_34) begin // @[Regfiles.scala 158:35]
      if (5'h1f == iwb_stage_iReg_io_rename_0_req_bits_rd0) begin // @[Regfiles.scala 162:23]
        iwb_stage_iReg_rename_ptr_31 <= iwb_stage_iReg__GEN_1121; // @[Regfiles.scala 162:23]
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_0 <= 6'h0; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h0 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_0 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_0 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_1 <= 6'h1; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_1 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_1 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_2 <= 6'h2; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h2 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_2 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_2 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_3 <= 6'h3; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h3 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_3 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_3 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_4 <= 6'h4; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h4 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_4 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_4 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_5 <= 6'h5; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h5 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_5 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_5 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_6 <= 6'h6; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h6 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_6 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_6 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_7 <= 6'h7; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h7 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_7 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_7 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_8 <= 6'h8; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h8 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_8 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_8 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_9 <= 6'h9; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h9 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_9 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_9 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_10 <= 6'ha; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'ha == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_10 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_10 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_11 <= 6'hb; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'hb == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_11 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_11 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_12 <= 6'hc; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'hc == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_12 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_12 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_13 <= 6'hd; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'hd == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_13 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_13 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_14 <= 6'he; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'he == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_14 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_14 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_15 <= 6'hf; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'hf == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_15 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_15 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_16 <= 6'h10; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h10 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_16 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_16 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_17 <= 6'h11; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h11 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_17 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_17 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_18 <= 6'h12; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h12 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_18 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_18 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_19 <= 6'h13; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h13 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_19 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_19 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_20 <= 6'h14; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h14 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_20 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_20 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_21 <= 6'h15; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h15 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_21 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_21 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_22 <= 6'h16; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h16 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_22 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_22 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_23 <= 6'h17; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h17 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_23 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_23 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_24 <= 6'h18; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h18 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_24 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_24 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_25 <= 6'h19; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h19 == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_25 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_25 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_26 <= 6'h1a; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1a == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_26 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_26 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_27 <= 6'h1b; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1b == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_27 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_27 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_28 <= 6'h1c; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1c == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_28 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_28 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_29 <= 6'h1d; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1d == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_29 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_29 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_30 <= 6'h1e; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1e == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_30 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_30 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 130:27]
      iwb_stage_iReg_archit_ptr_31 <= 6'h1f; // @[Regfiles.scala 130:27]
    end else if (iwb_stage_iReg__T_114) begin // @[Regfiles.scala 235:66]
      if (5'h1f == iwb_stage_iReg_io_commit_0_raw) begin // @[Regfiles.scala 236:26]
        if (iwb_stage_io_commit_0_toX) begin // @[WriteBack.scala 102:41]
          iwb_stage_iReg_archit_ptr_31 <= iwb_stage_io_commit_0_phy; // @[WriteBack.scala 102:60]
        end else begin
          iwb_stage_iReg_archit_ptr_31 <= 6'h0; // @[WriteBack.scala 88:37]
        end
      end
    end
    if (iwb_stage_iReg_reset) begin // @[Regfiles.scala 191:36]
      iwb_stage_iReg_io_rgRsp_0_valid_REG <= 1'h0; // @[Regfiles.scala 191:36]
    end else begin
      iwb_stage_iReg_io_rgRsp_0_valid_REG <= iwb_stage_iReg_io_rgReq_0_valid; // @[Regfiles.scala 191:36]
    end
    if (iwb_stage_iReg_io_rgReq_0_valid) begin // @[Reg.scala 20:18]
      iwb_stage_iReg_io_rgRsp_0_bits_phy_r <= iwb_stage_iReg_io_rgReq_0_bits; // @[Reg.scala 20:22]
    end
    if (iwb_stage_iReg_io_rgReq_0_valid) begin // @[Reg.scala 20:18]
      if (6'h21 == iwb_stage_iReg_io_rgReq_0_bits) begin // @[Reg.scala 20:22]
        iwb_stage_iReg_io_rgRsp_0_bits_op_r <= 64'h0; // @[Reg.scala 20:22]
      end else if (6'h20 == iwb_stage_iReg_io_rgReq_0_bits) begin // @[Reg.scala 20:22]
        iwb_stage_iReg_io_rgRsp_0_bits_op_r <= iwb_stage_iReg_files_reg_32; // @[Reg.scala 20:22]
      end else if (6'h1f == iwb_stage_iReg_io_rgReq_0_bits) begin // @[Reg.scala 20:22]
        iwb_stage_iReg_io_rgRsp_0_bits_op_r <= iwb_stage_iReg_files_reg_31; // @[Reg.scala 20:22]
      end else begin
        iwb_stage_iReg_io_rgRsp_0_bits_op_r <= iwb_stage_iReg__GEN_1381;
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_34 & iwb_stage_iReg__T_37 & iwb_stage_iReg__T_38) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Regfiles.scala:160 assert( log(molloc_idx(i)) === \"b00\".U )\n"); // @[Regfiles.scala 160:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_35 & (iwb_stage_iReg__T_34 & iwb_stage_iReg__T_37)) begin
          $fatal; // @[Regfiles.scala 160:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg_io_rgRsp_0_valid & iwb_stage_iReg__T_37 & iwb_stage_iReg__T_107) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed while reading operator, log is not ready!\n    at Regfiles.scala:194 when( io.rgRsp(i).valid ) {  assert( log(io.rgReq(i).bits) === \"b11\".U, \"Assert Failed while reading operator, log is not ready!\" ) }\n"
            ); // @[Regfiles.scala 194:40]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_104 & (iwb_stage_iReg_io_rgRsp_0_valid & iwb_stage_iReg__T_37)) begin
          $fatal; // @[Regfiles.scala 194:40]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_108 & iwb_stage_iReg__T_37 & iwb_stage_iReg__T_112) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed when writeback at chn0, log(XRegFiles.io.exe_writeBack[0].bits.rd0: IO[UInt<6>])\n    at Regfiles.scala:203 assert( log(idx) === \"b01\".U, \"Assert Failed when writeback at chn\" + i + \", log(\" + idx + \")\" )\n"
            ); // @[Regfiles.scala 203:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_109 & (iwb_stage_iReg__T_108 & iwb_stage_iReg__T_37)) begin
          $fatal; // @[Regfiles.scala 203:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_114 & iwb_stage_iReg__T_37 & iwb_stage_iReg__T_117) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Regfiles.scala:227 assert( io.commit(m).is_writeback )\n"); // @[Regfiles.scala 227:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg_io_commit_0_is_writeback & (iwb_stage_iReg__T_114 & iwb_stage_iReg__T_37)) begin
          $fatal; // @[Regfiles.scala 227:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_461 & iwb_stage_iReg__T_154) begin
          $fwrite(32'h80000002,
            "Assertion failed: log_reg which going to commit to will be overrided to \"b11\" if there is an abort in-front.\n    at Regfiles.scala:231 assert( log_reg(phy(m)) === \"b11\".U, \"log_reg which going to commit to will be overrided to \\\"b11\\\" if there is an abort in-front.\" )\n"
            ); // @[Regfiles.scala 231:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_151 & (iwb_stage_iReg__T_114 & iwb_stage_iReg__T_37)) begin
          $fatal; // @[Regfiles.scala 231:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_159) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[0]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_156 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_163) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[1]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_160 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_167) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[2]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_164 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[3]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_168 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_175) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[4]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_172 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[5]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_176 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[6]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_180 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[7]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_184 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_191) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[8]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_188 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[9]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_192 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_199) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[10]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_196 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_203) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[11]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_200 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_207) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[12]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_204 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[13]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_208 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[14]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_212 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_219) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[15]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_216 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_223) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[16]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_220 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_227) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[17]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_224 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_231) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[18]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_228 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_235) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[19]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_232 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_239) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[20]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_236 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_243) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[21]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_240 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_247) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[22]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_244 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[23]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_248 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[24]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_252 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_259) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[25]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_256 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_263) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[26]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_260 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_267) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[27]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_264 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_271) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[28]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_268 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[29]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_272 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_279) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[30]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_276 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_iReg__T_37 & iwb_stage_iReg__T_283) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, archit point to should be b11.U! i = XRegFiles.archit_ptr[31]: Reg[UInt<6>]\n\n    at Regfiles.scala:242 i => assert( log(i) === \"b11\".U, \"Assert Failed, archit point to should be b11.U! i = \"+i+\"\\n\")\n"
            ); // @[Regfiles.scala 242:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_iReg__T_280 & iwb_stage_iReg__T_37) begin
          $fatal; // @[Regfiles.scala 242:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge iwb_stage_fReg_clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_fReg__T_2 & iwb_stage_fReg__T_3) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Regfiles.scala:324 assert( ~io.exe_writeBack(i).valid )\n"); // @[Regfiles.scala 324:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_fReg__T & iwb_stage_fReg__T_2) begin
          $fatal; // @[Regfiles.scala 324:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (iwb_stage_fReg__T_2 & iwb_stage_fReg__T_7) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Regfiles.scala:324 assert( ~io.exe_writeBack(i).valid )\n"); // @[Regfiles.scala 324:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~iwb_stage_fReg__T_4 & iwb_stage_fReg__T_2) begin
          $fatal; // @[Regfiles.scala 324:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge cmm_stage_clock) begin
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_priv_lvl <= 2'h3; // @[Commit.scala 449:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csrfiles_DMode) begin // @[CsrFiles.scala 709:31]
        if (cmm_stage_is_xRet_is_dRet) begin // @[CsrFiles.scala 710:24]
          cmm_stage_csrfiles_priv_lvl <= cmm_stage_csrfiles_dcsr_prv; // @[CsrFiles.scala 710:35]
        end else begin
          cmm_stage_csrfiles_priv_lvl <= cmm_stage__GEN_469;
        end
      end else if (cmm_stage_is_trap_is_exception_is_store_pagingFault) begin // @[CsrFiles.scala 736:41]
        cmm_stage_csrfiles_priv_lvl <= cmm_stage__csr_state_0_csrfiles_priv_lvl_priv_lvl_T_75; // @[CsrFiles.scala 736:52]
      end else begin
        cmm_stage_csrfiles_priv_lvl <= cmm_stage__GEN_491;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_DMode <= 1'h0; // @[Commit.scala 450:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_DMode <= cmm_stage__GEN_495; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_fcsr_frm <= 3'h0; // @[Commit.scala 451:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_fcsr_frm <= cmm_stage_csr_state_0_csrfiles_fcsr_fcsr_frm; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_fcsr_fflags <= 5'h0; // @[Commit.scala 451:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_fcsr_fflags <= cmm_stage_csr_state_0_csrfiles_fcsr_fcsr_fflags; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_time <= 64'h0; // @[Commit.scala 453:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_time <= 64'h0; // @[Commit.scala 398:100]
    end else if (cmm_stage__T) begin // @[Commit.scala 396:87]
      cmm_stage_csrfiles_time <= cmm_stage__csrfiles_time_T_1; // @[Commit.scala 396:103]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_stvec_base <= 62'h0; // @[Commit.scala 455:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_stvec_enable) begin // @[CsrFiles.scala 1322:18]
        cmm_stage_csrfiles_stvec_base <= cmm_stage__csr_state_0_csrfiles_stvec_stvec_base_T; // @[CsrFiles.scala 1322:31]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_scounteren_hpm <= 32'h0; // @[Commit.scala 456:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_scounteren_hpm <= cmm_stage_csr_state_0_csrfiles_scounteren_scounteren_hpm; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_sscratch <= 64'h0; // @[Commit.scala 457:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_sscratch_enable) begin // @[CsrFiles.scala 1358:18]
        cmm_stage_csrfiles_sscratch <= cmm_stage__csr_state_0_csrfiles_sscratch_dnxt_T_7; // @[CsrFiles.scala 1358:29]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_sepc <= 64'h0; // @[Commit.scala 458:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_sepc_T_10) begin // @[CsrFiles.scala 1373:79]
        cmm_stage_csrfiles_sepc <= cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_4; // @[CsrFiles.scala 1373:86]
      end else if (cmm_stage_csr_state_0_csrfiles_sepc_enable) begin // @[CsrFiles.scala 1374:23]
        cmm_stage_csrfiles_sepc <= cmm_stage__csr_state_0_csrfiles_sepc_dnxt_T_7; // @[CsrFiles.scala 1374:30]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_scause_interrupt <= 1'h0; // @[Commit.scala 459:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_scause_interrupt <= cmm_stage__GEN_583; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_scause_exception_code <= 63'h0; // @[Commit.scala 459:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_scause_T_12) begin // @[CsrFiles.scala 1388:128]
        cmm_stage_csrfiles_scause_exception_code <= {{59'd0},
          cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_16}; // @[CsrFiles.scala 1390:29]
      end else if (cmm_stage__csr_state_0_csrfiles_scause_T_23) begin // @[CsrFiles.scala 1399:89]
        cmm_stage_csrfiles_scause_exception_code <= {{59'd0},
          cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_44}; // @[CsrFiles.scala 1401:29]
      end else begin
        cmm_stage_csrfiles_scause_exception_code <= cmm_stage__GEN_580;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_stval <= 64'h0; // @[Commit.scala 460:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_sepc_T_10) begin // @[CsrFiles.scala 1436:79]
        cmm_stage_csrfiles_stval <= cmm_stage__csr_state_0_csrfiles_stval_stval_T_19; // @[CsrFiles.scala 1437:13]
      end else if (cmm_stage_csr_state_0_csrfiles_stval_enable) begin // @[CsrFiles.scala 1450:23]
        cmm_stage_csrfiles_stval <= cmm_stage__csr_state_0_csrfiles_stval_dnxt_T_7; // @[CsrFiles.scala 1450:31]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_satp_mode <= 4'h0; // @[Commit.scala 462:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_satp_enable) begin // @[CsrFiles.scala 1495:18]
        cmm_stage_csrfiles_satp_mode <= cmm_stage__csr_state_0_csrfiles_satp_satp_mode_T_1; // @[CsrFiles.scala 1497:17]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_satp_asid <= 16'h0; // @[Commit.scala 462:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_satp_enable) begin // @[CsrFiles.scala 1495:18]
        cmm_stage_csrfiles_satp_asid <= cmm_stage__csr_state_0_csrfiles_satp_satp_asid_T; // @[CsrFiles.scala 1498:17]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_satp_ppn <= 44'h0; // @[Commit.scala 462:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_satp_enable) begin // @[CsrFiles.scala 1495:18]
        cmm_stage_csrfiles_satp_ppn <= cmm_stage__csr_state_0_csrfiles_satp_satp_ppn_T; // @[CsrFiles.scala 1499:17]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_marchid <= 64'h0; // @[Commit.scala 464:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_marchid <= 64'h1d; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_sd <= 1'h0; // @[Commit.scala 487:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mstatus_sd <= cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_sd_T_1; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_tsr <= 1'h0; // @[Commit.scala 472:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_3)) begin // @[CsrFiles.scala 758:45]
        if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_21)) begin // @[CsrFiles.scala 770:50]
          cmm_stage_csrfiles_mstatus_tsr <= cmm_stage__GEN_749;
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_tw <= 1'h0; // @[Commit.scala 473:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_3)) begin // @[CsrFiles.scala 758:45]
        if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_21)) begin // @[CsrFiles.scala 770:50]
          cmm_stage_csrfiles_mstatus_tw <= cmm_stage__GEN_750;
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_tvm <= 1'h0; // @[Commit.scala 474:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_3)) begin // @[CsrFiles.scala 758:45]
        if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_21)) begin // @[CsrFiles.scala 770:50]
          cmm_stage_csrfiles_mstatus_tvm <= cmm_stage__GEN_751;
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_mxr <= 1'h0; // @[Commit.scala 475:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_3)) begin // @[CsrFiles.scala 758:45]
        if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_21)) begin // @[CsrFiles.scala 770:50]
          cmm_stage_csrfiles_mstatus_mxr <= cmm_stage__GEN_745;
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_sum <= 1'h0; // @[Commit.scala 476:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_3)) begin // @[CsrFiles.scala 758:45]
        if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_21)) begin // @[CsrFiles.scala 770:50]
          cmm_stage_csrfiles_mstatus_sum <= cmm_stage__GEN_746;
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_mprv <= 1'h0; // @[Commit.scala 477:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_3)) begin // @[CsrFiles.scala 758:45]
        if (cmm_stage__csr_state_0_csrfiles_mstatus_T_21) begin // @[CsrFiles.scala 770:50]
          cmm_stage_csrfiles_mstatus_mprv <= cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_mprv_T_8; // @[CsrFiles.scala 775:20]
        end else begin
          cmm_stage_csrfiles_mstatus_mprv <= cmm_stage__GEN_744;
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_fs <= 2'h0; // @[Commit.scala 479:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mstatus_T_25) begin // @[CsrFiles.scala 808:67]
        cmm_stage_csrfiles_mstatus_fs <= 2'h3; // @[CsrFiles.scala 809:18]
      end else if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_3)) begin // @[CsrFiles.scala 758:45]
        cmm_stage_csrfiles_mstatus_fs <= cmm_stage__GEN_763;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_mpp <= 2'h3; // @[Commit.scala 480:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mstatus_T_3) begin // @[CsrFiles.scala 758:45]
        if (cmm_stage__csr_state_0_csrfiles_mstatus_T_11) begin // @[CsrFiles.scala 759:47]
          cmm_stage_csrfiles_mstatus_mpp <= cmm_stage_csrfiles_priv_lvl; // @[CsrFiles.scala 762:22]
        end
      end else if (cmm_stage__csr_state_0_csrfiles_mstatus_T_21) begin // @[CsrFiles.scala 770:50]
        cmm_stage_csrfiles_mstatus_mpp <= 2'h0; // @[CsrFiles.scala 773:20]
      end else begin
        cmm_stage_csrfiles_mstatus_mpp <= cmm_stage__GEN_752;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_spp <= 1'h0; // @[Commit.scala 481:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mstatus_T_3) begin // @[CsrFiles.scala 758:45]
        if (cmm_stage__csr_state_0_csrfiles_sepc_T_7) begin // @[CsrFiles.scala 764:47]
          cmm_stage_csrfiles_mstatus_spp <= cmm_stage__csr_state_0_csrfiles_mstatus_mstatus_spp_T_1; // @[CsrFiles.scala 765:22]
        end
      end else if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_21)) begin // @[CsrFiles.scala 770:50]
        cmm_stage_csrfiles_mstatus_spp <= cmm_stage__GEN_748;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_mpie <= 1'h0; // @[Commit.scala 482:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mstatus_T_3) begin // @[CsrFiles.scala 758:45]
        if (cmm_stage__csr_state_0_csrfiles_mstatus_T_11) begin // @[CsrFiles.scala 759:47]
          cmm_stage_csrfiles_mstatus_mpie <= cmm_stage_csrfiles_mstatus_mie; // @[CsrFiles.scala 760:22]
        end
      end else begin
        cmm_stage_csrfiles_mstatus_mpie <= cmm_stage__GEN_756;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_spie <= 1'h0; // @[Commit.scala 484:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mstatus_T_3) begin // @[CsrFiles.scala 758:45]
        if (cmm_stage__csr_state_0_csrfiles_sepc_T_7) begin // @[CsrFiles.scala 764:47]
          cmm_stage_csrfiles_mstatus_spie <= cmm_stage_csrfiles_mstatus_sie; // @[CsrFiles.scala 766:22]
        end
      end else if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_21)) begin // @[CsrFiles.scala 770:50]
        cmm_stage_csrfiles_mstatus_spie <= cmm_stage__GEN_742;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_mie <= 1'h0; // @[Commit.scala 485:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mstatus_T_3) begin // @[CsrFiles.scala 758:45]
        if (cmm_stage__csr_state_0_csrfiles_mstatus_T_11) begin // @[CsrFiles.scala 759:47]
          cmm_stage_csrfiles_mstatus_mie <= 1'h0; // @[CsrFiles.scala 761:22]
        end
      end else if (cmm_stage__csr_state_0_csrfiles_mstatus_T_21) begin // @[CsrFiles.scala 770:50]
        cmm_stage_csrfiles_mstatus_mie <= cmm_stage_csrfiles_mstatus_mpie; // @[CsrFiles.scala 771:20]
      end else begin
        cmm_stage_csrfiles_mstatus_mie <= cmm_stage__GEN_754;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mstatus_sie <= 1'h0; // @[Commit.scala 486:27]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mstatus_T_3) begin // @[CsrFiles.scala 758:45]
        if (cmm_stage__csr_state_0_csrfiles_sepc_T_7) begin // @[CsrFiles.scala 764:47]
          cmm_stage_csrfiles_mstatus_sie <= 1'h0; // @[CsrFiles.scala 767:22]
        end
      end else if (!(cmm_stage__csr_state_0_csrfiles_mstatus_T_21)) begin // @[CsrFiles.scala 770:50]
        cmm_stage_csrfiles_mstatus_sie <= cmm_stage__GEN_743;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_misa <= 64'h800000000014112d; // @[Commit.scala 489:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_misa <= 64'h8000000000141105; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_medeleg <= 64'h0; // @[Commit.scala 490:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_medeleg_enable) begin // @[CsrFiles.scala 850:18]
        cmm_stage_csrfiles_medeleg <= cmm_stage__csr_state_0_csrfiles_medeleg_dnxt_T_7; // @[CsrFiles.scala 850:28]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mideleg <= 64'h0; // @[Commit.scala 491:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mideleg_enable) begin // @[CsrFiles.scala 862:18]
        cmm_stage_csrfiles_mideleg <= cmm_stage__csr_state_0_csrfiles_mideleg_dnxt_T_7; // @[CsrFiles.scala 862:28]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mie_mei <= 1'h0; // @[Commit.scala 492:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        cmm_stage_csrfiles_mie_mei <= cmm_stage__csr_state_0_csrfiles_mie_mie_mei_T; // @[CsrFiles.scala 883:15]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mie_sei <= 1'h0; // @[Commit.scala 492:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        cmm_stage_csrfiles_mie_sei <= cmm_stage__csr_state_0_csrfiles_mie_mie_sei_T; // @[CsrFiles.scala 884:15]
      end else if (cmm_stage_csr_state_0_csrfiles_mie_enable1) begin // @[CsrFiles.scala 890:24]
        cmm_stage_csrfiles_mie_sei <= cmm_stage__csr_state_0_csrfiles_mie_mie_sei_T; // @[CsrFiles.scala 891:15]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mie_mti <= 1'h0; // @[Commit.scala 492:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        cmm_stage_csrfiles_mie_mti <= cmm_stage__csr_state_0_csrfiles_mie_mie_mti_T; // @[CsrFiles.scala 885:15]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mie_sti <= 1'h0; // @[Commit.scala 492:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        cmm_stage_csrfiles_mie_sti <= cmm_stage__csr_state_0_csrfiles_mie_mie_sti_T; // @[CsrFiles.scala 886:15]
      end else if (cmm_stage_csr_state_0_csrfiles_mie_enable1) begin // @[CsrFiles.scala 890:24]
        cmm_stage_csrfiles_mie_sti <= cmm_stage__csr_state_0_csrfiles_mie_mie_sti_T; // @[CsrFiles.scala 892:15]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mie_msi <= 1'h0; // @[Commit.scala 492:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        cmm_stage_csrfiles_mie_msi <= cmm_stage__csr_state_0_csrfiles_mie_mie_msi_T; // @[CsrFiles.scala 887:15]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mie_ssi <= 1'h0; // @[Commit.scala 492:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mie_enable0) begin // @[CsrFiles.scala 882:19]
        cmm_stage_csrfiles_mie_ssi <= cmm_stage__csr_state_0_csrfiles_mie_mie_ssi_T; // @[CsrFiles.scala 888:15]
      end else if (cmm_stage_csr_state_0_csrfiles_mie_enable1) begin // @[CsrFiles.scala 890:24]
        cmm_stage_csrfiles_mie_ssi <= cmm_stage__csr_state_0_csrfiles_mie_mie_ssi_T; // @[CsrFiles.scala 893:15]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mtvec_base <= 62'h0; // @[Commit.scala 493:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mtvec_enable) begin // @[CsrFiles.scala 912:18]
        cmm_stage_csrfiles_mtvec_base <= cmm_stage__csr_state_0_csrfiles_mtvec_mtvec_base_T; // @[CsrFiles.scala 912:31]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mcounteren_hpm <= 32'h0; // @[Commit.scala 494:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mcounteren_hpm <= cmm_stage_csr_state_0_csrfiles_mcounteren_mcounteren_hpm; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mscratch <= 64'h0; // @[Commit.scala 495:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mscratch_enable) begin // @[CsrFiles.scala 947:18]
        cmm_stage_csrfiles_mscratch <= cmm_stage__csr_state_0_csrfiles_mscratch_dnxt_T_7; // @[CsrFiles.scala 947:29]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mepc <= 64'h0; // @[Commit.scala 496:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mepc_T_10) begin // @[CsrFiles.scala 962:78]
        cmm_stage_csrfiles_mepc <= cmm_stage__csr_state_0_csrfiles_sepc_sepc_commit_pc_v64_T_4; // @[CsrFiles.scala 962:85]
      end else if (cmm_stage_csr_state_0_csrfiles_mepc_enable) begin // @[CsrFiles.scala 963:23]
        cmm_stage_csrfiles_mepc <= cmm_stage__csr_state_0_csrfiles_mepc_dnxt_T_7; // @[CsrFiles.scala 963:30]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mcause_interrupt <= 1'h0; // @[Commit.scala 497:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mcause_interrupt <= cmm_stage__GEN_874; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mcause_exception_code <= 63'h0; // @[Commit.scala 497:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mcause_T_11) begin // @[CsrFiles.scala 978:95]
        cmm_stage_csrfiles_mcause_exception_code <= {{59'd0},
          cmm_stage__csr_state_0_csrfiles_mcause_mcause_exception_code_T_7}; // @[CsrFiles.scala 980:29]
      end else if (cmm_stage__csr_state_0_csrfiles_mcause_T_22) begin // @[CsrFiles.scala 989:89]
        cmm_stage_csrfiles_mcause_exception_code <= {{59'd0},
          cmm_stage__csr_state_0_csrfiles_scause_scause_exception_code_T_44}; // @[CsrFiles.scala 991:29]
      end else begin
        cmm_stage_csrfiles_mcause_exception_code <= cmm_stage__GEN_871;
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mtval <= 64'h0; // @[Commit.scala 498:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage__csr_state_0_csrfiles_mepc_T_10) begin // @[CsrFiles.scala 1027:79]
        cmm_stage_csrfiles_mtval <= cmm_stage__csr_state_0_csrfiles_stval_stval_T_19; // @[CsrFiles.scala 1028:13]
      end else if (cmm_stage_csr_state_0_csrfiles_mtval_enable) begin // @[CsrFiles.scala 1041:23]
        cmm_stage_csrfiles_mtval <= cmm_stage__csr_state_0_csrfiles_mtval_dnxt_T_7; // @[CsrFiles.scala 1041:31]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mip_mei <= 1'h0; // @[Commit.scala 499:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mip_mei <= cmm_stage_io_plic_mei; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mip_sei <= 1'h0; // @[Commit.scala 499:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mip_sei <= cmm_stage_io_plic_sei; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mip_mti <= 1'h0; // @[Commit.scala 499:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mip_mti <= cmm_stage_io_aclint_mti; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mip_sti <= 1'h0; // @[Commit.scala 499:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mip_sti <= cmm_stage_io_aclint_sti; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mip_msi <= 1'h0; // @[Commit.scala 499:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mip_msi <= cmm_stage_io_aclint_msi; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mip_ssi <= 1'h0; // @[Commit.scala 499:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      cmm_stage_csrfiles_mip_ssi <= cmm_stage_io_aclint_ssi; // @[Commit.scala 398:100]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mtinst <= 64'h0; // @[Commit.scala 500:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mtinst_enable) begin // @[CsrFiles.scala 1077:18]
        cmm_stage_csrfiles_mtinst <= cmm_stage__csr_state_0_csrfiles_mtinst_dnxt_T_7; // @[CsrFiles.scala 1077:27]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mtval2 <= 64'h0; // @[Commit.scala 501:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mtval2_enable) begin // @[CsrFiles.scala 1085:18]
        cmm_stage_csrfiles_mtval2 <= cmm_stage__csr_state_0_csrfiles_mtval2_dnxt_T_7; // @[CsrFiles.scala 1085:27]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_mcycle <= 64'h0; // @[Commit.scala 502:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_mcycle_enable) begin // @[CsrFiles.scala 1143:20]
        cmm_stage_csrfiles_mcycle <= cmm_stage__csr_state_0_csrfiles_mcycle_dnxt_T_7; // @[CsrFiles.scala 1143:29]
      end else begin
        cmm_stage_csrfiles_mcycle <= cmm_stage__csrfiles_mcycle_T_1; // @[CsrFiles.scala 1144:26]
      end
    end else begin
      cmm_stage_csrfiles_mcycle <= cmm_stage__csrfiles_mcycle_T_1; // @[Commit.scala 395:19]
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_minstret <= 64'h0; // @[Commit.scala 503:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_minstret_enable) begin // @[CsrFiles.scala 1158:18]
        cmm_stage_csrfiles_minstret <= cmm_stage__csr_state_0_csrfiles_minstret_dnxt_T_7; // @[CsrFiles.scala 1158:29]
      end else begin
        cmm_stage_csrfiles_minstret <= cmm_stage__csr_state_0_csrfiles_minstret_minstret_T_1; // @[CsrFiles.scala 1159:27]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_tselect <= 64'h0; // @[Commit.scala 505:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_tselect_enable) begin // @[CsrFiles.scala 1746:20]
        cmm_stage_csrfiles_tselect <= cmm_stage__csr_state_0_csrfiles_tselect_tselect_T_1; // @[CsrFiles.scala 1746:30]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_tdata1 <= 64'h0; // @[Commit.scala 506:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_tdata1_enable) begin // @[CsrFiles.scala 1757:20]
        cmm_stage_csrfiles_tdata1 <= cmm_stage__csr_state_0_csrfiles_tdata1_dnxt_T_7; // @[CsrFiles.scala 1757:29]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_tdata2 <= 64'h0; // @[Commit.scala 507:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_tdata2_enable) begin // @[CsrFiles.scala 1767:20]
        cmm_stage_csrfiles_tdata2 <= cmm_stage__csr_state_0_csrfiles_tdata2_dnxt_T_7; // @[CsrFiles.scala 1767:29]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_tdata3 <= 64'h0; // @[Commit.scala 508:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_tdata3_enable) begin // @[CsrFiles.scala 1777:20]
        cmm_stage_csrfiles_tdata3 <= cmm_stage__csr_state_0_csrfiles_tdata3_dnxt_T_7; // @[CsrFiles.scala 1777:29]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dcsr_ebreakm <= 1'h0; // @[Commit.scala 511:29]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt)) begin // @[CsrFiles.scala 1796:41]
        if (cmm_stage_csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
          cmm_stage_csrfiles_dcsr_ebreakm <= cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_ebreakm_T; // @[CsrFiles.scala 1809:24]
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dcsr_ebreaks <= 1'h0; // @[Commit.scala 512:29]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt)) begin // @[CsrFiles.scala 1796:41]
        if (cmm_stage_csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
          cmm_stage_csrfiles_dcsr_ebreaks <= cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_ebreaks_T; // @[CsrFiles.scala 1810:24]
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dcsr_ebreaku <= 1'h0; // @[Commit.scala 513:29]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt)) begin // @[CsrFiles.scala 1796:41]
        if (cmm_stage_csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
          cmm_stage_csrfiles_dcsr_ebreaku <= cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_ebreaku_T; // @[CsrFiles.scala 1811:24]
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dcsr_cause <= 3'h0; // @[Commit.scala 517:29]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt) begin // @[CsrFiles.scala 1796:41]
        if (cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt_is_ebreak_dm) begin // @[Mux.scala 101:16]
          cmm_stage_csrfiles_dcsr_cause <= 3'h1;
        end else begin
          cmm_stage_csrfiles_dcsr_cause <= cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_cause_T_1;
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dcsr_step <= 1'h0; // @[Commit.scala 520:29]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (!(cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt)) begin // @[CsrFiles.scala 1796:41]
        if (cmm_stage_csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
          cmm_stage_csrfiles_dcsr_step <= cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_step_T; // @[CsrFiles.scala 1812:19]
        end
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dcsr_prv <= 2'h3; // @[Commit.scala 521:29]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_is_trap_is_interrupt_is_nomask_interrupt_is_debug_interrupt) begin // @[CsrFiles.scala 1796:41]
        cmm_stage_csrfiles_dcsr_prv <= cmm_stage_csrfiles_priv_lvl; // @[CsrFiles.scala 1797:18]
      end else if (cmm_stage_csr_state_0_csrfiles_dcsr_enable) begin // @[CsrFiles.scala 1808:25]
        cmm_stage_csrfiles_dcsr_prv <= cmm_stage__csr_state_0_csrfiles_dcsr_dcsr_prv_T; // @[CsrFiles.scala 1813:19]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dpc <= 64'h0; // @[Commit.scala 523:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_dpc_enable) begin // @[CsrFiles.scala 1825:20]
        cmm_stage_csrfiles_dpc <= cmm_stage__csr_state_0_csrfiles_dpc_dnxt_T_7; // @[CsrFiles.scala 1825:26]
      end else if (cmm_stage__csr_state_0_csrfiles_dpc_T_2) begin // @[CsrFiles.scala 1827:84]
        cmm_stage_csrfiles_dpc <= cmm_stage__csr_state_0_csrfiles_dpc_dpc_T_6; // @[CsrFiles.scala 1828:13]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dscratch0 <= 64'h0; // @[Commit.scala 524:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_dscratch0_enable) begin // @[CsrFiles.scala 1845:20]
        cmm_stage_csrfiles_dscratch0 <= cmm_stage__csr_state_0_csrfiles_dscratch0_dnxt_T_7; // @[CsrFiles.scala 1845:32]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dscratch1 <= 64'h0; // @[Commit.scala 525:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_dscratch1_enable) begin // @[CsrFiles.scala 1854:20]
        cmm_stage_csrfiles_dscratch1 <= cmm_stage__csr_state_0_csrfiles_dscratch1_dnxt_T_7; // @[CsrFiles.scala 1854:32]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 399:24]
      cmm_stage_csrfiles_dscratch2 <= 64'h0; // @[Commit.scala 526:28]
    end else if (cmm_stage__T_1) begin // @[Commit.scala 398:89]
      if (cmm_stage_csr_state_0_csrfiles_dscratch2_enable) begin // @[CsrFiles.scala 1863:20]
        cmm_stage_csrfiles_dscratch2 <= cmm_stage__csr_state_0_csrfiles_dscratch2_dnxt_T_7; // @[CsrFiles.scala 1863:32]
      end
    end
    if (cmm_stage_reset) begin // @[Commit.scala 404:31]
      cmm_stage_is_single_step <= 1'h0; // @[Commit.scala 404:31]
    end else begin
      cmm_stage_is_single_step <= cmm_stage__GEN_461;
    end
    if (cmm_stage_reset) begin // @[Commit.scala 363:26]
      cmm_stage_emu_reset <= 1'h0; // @[Commit.scala 363:26]
    end else begin
      cmm_stage_emu_reset <= cmm_stage__GEN_1;
    end
    if (cmm_stage_reset) begin // @[Reg.scala 35:20]
      cmm_stage_rtc_0 <= 1'h0; // @[Reg.scala 35:20]
    end else begin
      cmm_stage_rtc_0 <= cmm_stage_io_rtc_clock;
    end
    if (cmm_stage_reset) begin // @[Reg.scala 35:20]
      cmm_stage_rtc_1 <= 1'h0; // @[Reg.scala 35:20]
    end else begin
      cmm_stage_rtc_1 <= cmm_stage_rtc_0;
    end
    if (cmm_stage_reset) begin // @[Reg.scala 35:20]
      cmm_stage_rtc_2 <= 1'h0; // @[Reg.scala 35:20]
    end else begin
      cmm_stage_rtc_2 <= cmm_stage_rtc_1;
    end
    if (cmm_stage_reset) begin // @[Reg.scala 35:20]
      cmm_stage_rtc_3 <= 1'h0; // @[Reg.scala 35:20]
    end else begin
      cmm_stage_rtc_3 <= cmm_stage_rtc_2;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cmm_stage__T_38 & cmm_stage__T_39) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:680 assert( bctq(i).fire === (is_retired(i) & io.rod(i).bits.is_branch) )\n"
            ); // @[Commit.scala 680:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~cmm_stage__T_36 & cmm_stage__T_38) begin
          $fatal; // @[Commit.scala 680:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cmm_stage__T_38 & cmm_stage__T_45) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:681 assert( bctq.map{_.fire}.reduce(_|_) === io.bctq.fire )\n"); // @[Commit.scala 681:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~cmm_stage__T_42 & cmm_stage__T_38) begin
          $fatal; // @[Commit.scala 681:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cmm_stage__T_38 & cmm_stage__T_51) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:686 assert( jctq(i).fire === (is_retired(i) & io.rod(i).bits.is_jalr) )\n"
            ); // @[Commit.scala 686:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~cmm_stage__T_48 & cmm_stage__T_38) begin
          $fatal; // @[Commit.scala 686:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cmm_stage__T_38 & cmm_stage__T_57) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:687 assert( jctq.map{_.fire}.reduce(_|_) === io.jctq.fire )\n"); // @[Commit.scala 687:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~cmm_stage__T_54 & cmm_stage__T_38) begin
          $fatal; // @[Commit.scala 687:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cmm_stage_commit_state_is_abort_0 & cmm_stage_csrfiles_DMode & cmm_stage_is_trap_is_interrupt &
          cmm_stage__T_38) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed, All interrupts (including NMI) are masked in Dmode! Page-39\n    at Commit.scala:730 assert(false.B, \"Assert Failed, All interrupts (including NMI) are masked in Dmode! Page-39\")\n"
            ); // @[Commit.scala 730:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (cmm_stage_commit_state_is_abort_0 & cmm_stage_csrfiles_DMode & cmm_stage_is_trap_is_interrupt &
          cmm_stage__T_38)) begin
          $fatal; // @[Commit.scala 730:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cmm_stage_commit_state_is_abort_0 & cmm_stage__is_trap_is_interrupt_T_2 & cmm_stage__T_38 & cmm_stage__T_86
          ) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:768 assert( PopCount(Seq( cmm_state(i).is_xRet, cmm_state(i).is_trap, cmm_state(i).is_fence_i, cmm_state(i).is_sfence_vma)) <= 1.U )\n"
            ); // @[Commit.scala 768:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~cmm_stage__T_83 & (cmm_stage_commit_state_is_abort_0 & cmm_stage__is_trap_is_interrupt_T_2 &
          cmm_stage__T_38)) begin
          $fatal; // @[Commit.scala 768:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cmm_stage__T_38 & cmm_stage__T_92) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:803 assert( ~(csrExe(i).ready & ~csrExe(i).valid) )\n"); // @[Commit.scala 803:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~cmm_stage__T_89 & cmm_stage__T_38) begin
          $fatal; // @[Commit.scala 803:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (cmm_stage__T_38 & cmm_stage__T_98) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Commit.scala:814 assert( ~(fcsrExe(i).ready & ~fcsrExe(i).valid) )\n"); // @[Commit.scala 814:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~cmm_stage__T_95 & cmm_stage__T_38) begin
          $fatal; // @[Commit.scala 814:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge i_mmu_itlb_random_idx_prng_clock) begin
    i_mmu_itlb_random_idx_prng_state_0 <= i_mmu_itlb_random_idx_prng_reset | i_mmu_itlb_random_idx_prng__T; // @[PRNG.scala 55:{49,49}]
    if (i_mmu_itlb_random_idx_prng_reset) begin // @[PRNG.scala 55:49]
      i_mmu_itlb_random_idx_prng_state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      i_mmu_itlb_random_idx_prng_state_1 <= i_mmu_itlb_random_idx_prng_state_0;
    end
  end
  always @(posedge i_mmu_itlb_random_idx_prng_1_clock) begin
    i_mmu_itlb_random_idx_prng_1_state_0 <= i_mmu_itlb_random_idx_prng_1_reset | i_mmu_itlb_random_idx_prng_1__T; // @[PRNG.scala 55:{49,49}]
    if (i_mmu_itlb_random_idx_prng_1_reset) begin // @[PRNG.scala 55:49]
      i_mmu_itlb_random_idx_prng_1_state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      i_mmu_itlb_random_idx_prng_1_state_1 <= i_mmu_itlb_random_idx_prng_1_state_0;
    end
  end
  always @(posedge i_mmu_itlb_random_idx_prng_2_clock) begin
    i_mmu_itlb_random_idx_prng_2_state_0 <= i_mmu_itlb_random_idx_prng_2_reset | i_mmu_itlb_random_idx_prng_2__T; // @[PRNG.scala 55:{49,49}]
    if (i_mmu_itlb_random_idx_prng_2_reset) begin // @[PRNG.scala 55:49]
      i_mmu_itlb_random_idx_prng_2_state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      i_mmu_itlb_random_idx_prng_2_state_1 <= i_mmu_itlb_random_idx_prng_2_state_0;
    end
  end
  always @(posedge i_mmu_itlb_random_idx_prng_3_clock) begin
    i_mmu_itlb_random_idx_prng_3_state_0 <= i_mmu_itlb_random_idx_prng_3_reset | i_mmu_itlb_random_idx_prng_3__T; // @[PRNG.scala 55:{49,49}]
    if (i_mmu_itlb_random_idx_prng_3_reset) begin // @[PRNG.scala 55:49]
      i_mmu_itlb_random_idx_prng_3_state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      i_mmu_itlb_random_idx_prng_3_state_1 <= i_mmu_itlb_random_idx_prng_3_state_0;
    end
  end
  always @(posedge i_mmu_itlb_clock) begin
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_0_is_valid <= 1'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_0_is_valid <= 1'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      i_mmu_itlb_tag_0_is_valid <= i_mmu_itlb__GEN_0;
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_0_asid <= 16'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_0_asid <= 16'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~i_mmu_itlb__T_3) begin // @[TLB.scala 69:32]
        i_mmu_itlb_tag_0_asid <= i_mmu_itlb_io_tlb_renew_bits_asid; // @[TLB.scala 69:32]
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_0_vpn_0 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_0_vpn_0 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~i_mmu_itlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_itlb_tag_0_vpn_0 <= i_mmu_itlb_io_tlb_renew_bits_vpn_0; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_0_vpn_1 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_0_vpn_1 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~i_mmu_itlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_itlb_tag_0_vpn_1 <= i_mmu_itlb_io_tlb_renew_bits_vpn_1; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_0_vpn_2 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_0_vpn_2 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~i_mmu_itlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_itlb_tag_0_vpn_2 <= i_mmu_itlb_io_tlb_renew_bits_vpn_2; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_1_is_valid <= 1'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_1_is_valid <= 1'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      i_mmu_itlb_tag_1_is_valid <= i_mmu_itlb__GEN_1;
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_1_asid <= 16'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_1_asid <= 16'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (i_mmu_itlb__T_3) begin // @[TLB.scala 69:32]
        i_mmu_itlb_tag_1_asid <= i_mmu_itlb_io_tlb_renew_bits_asid; // @[TLB.scala 69:32]
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_1_vpn_0 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_1_vpn_0 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (i_mmu_itlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_itlb_tag_1_vpn_0 <= i_mmu_itlb_io_tlb_renew_bits_vpn_0; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_1_vpn_1 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_1_vpn_1 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (i_mmu_itlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_itlb_tag_1_vpn_1 <= i_mmu_itlb_io_tlb_renew_bits_vpn_1; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_itlb_tag_1_vpn_2 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_itlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_itlb_tag_1_vpn_2 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (i_mmu_itlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_itlb_tag_1_vpn_2 <= i_mmu_itlb_io_tlb_renew_bits_vpn_2; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_itlb_pte_0_value <= 64'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_itlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (~i_mmu_itlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_itlb_pte_0_value <= i_mmu_itlb_io_tlb_renew_bits_value; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_itlb_pte_0_is_giga_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_itlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (~i_mmu_itlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_itlb_pte_0_is_giga_page <= i_mmu_itlb_io_tlb_renew_bits_is_giga_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_itlb_pte_0_is_mega_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_itlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (~i_mmu_itlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_itlb_pte_0_is_mega_page <= i_mmu_itlb_io_tlb_renew_bits_is_mega_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_itlb_pte_1_value <= 64'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_itlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (i_mmu_itlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_itlb_pte_1_value <= i_mmu_itlb_io_tlb_renew_bits_value; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_itlb_pte_1_is_giga_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_itlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (i_mmu_itlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_itlb_pte_1_is_giga_page <= i_mmu_itlb_io_tlb_renew_bits_is_giga_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_itlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_itlb_pte_1_is_mega_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_itlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_itlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (i_mmu_itlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_itlb_pte_1_is_mega_page <= i_mmu_itlb_io_tlb_renew_bits_is_mega_page; // @[TLB.scala 71:32]
        end
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (i_mmu_itlb__T_15 & i_mmu_itlb__T_16) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail at tlb, more than 1 entry hit!\n    at TLB.scala:110 assert( PopCount( tlb_hit.asUInt ) <= 1.U, \"Assert Fail at tlb, more than 1 entry hit!\"  )\n"
            ); // @[TLB.scala 110:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~i_mmu_itlb__T_13 & i_mmu_itlb__T_15) begin
          $fatal; // @[TLB.scala 110:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge i_mmu_dtlb_random_idx_prng_clock) begin
    i_mmu_dtlb_random_idx_prng_state_0 <= i_mmu_dtlb_random_idx_prng_reset | i_mmu_dtlb_random_idx_prng__T; // @[PRNG.scala 55:{49,49}]
    if (i_mmu_dtlb_random_idx_prng_reset) begin // @[PRNG.scala 55:49]
      i_mmu_dtlb_random_idx_prng_state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      i_mmu_dtlb_random_idx_prng_state_1 <= i_mmu_dtlb_random_idx_prng_state_0;
    end
  end
  always @(posedge i_mmu_dtlb_random_idx_prng_1_clock) begin
    i_mmu_dtlb_random_idx_prng_1_state_0 <= i_mmu_dtlb_random_idx_prng_1_reset | i_mmu_dtlb_random_idx_prng_1__T; // @[PRNG.scala 55:{49,49}]
    if (i_mmu_dtlb_random_idx_prng_1_reset) begin // @[PRNG.scala 55:49]
      i_mmu_dtlb_random_idx_prng_1_state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      i_mmu_dtlb_random_idx_prng_1_state_1 <= i_mmu_dtlb_random_idx_prng_1_state_0;
    end
  end
  always @(posedge i_mmu_dtlb_random_idx_prng_2_clock) begin
    i_mmu_dtlb_random_idx_prng_2_state_0 <= i_mmu_dtlb_random_idx_prng_2_reset | i_mmu_dtlb_random_idx_prng_2__T; // @[PRNG.scala 55:{49,49}]
    if (i_mmu_dtlb_random_idx_prng_2_reset) begin // @[PRNG.scala 55:49]
      i_mmu_dtlb_random_idx_prng_2_state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      i_mmu_dtlb_random_idx_prng_2_state_1 <= i_mmu_dtlb_random_idx_prng_2_state_0;
    end
  end
  always @(posedge i_mmu_dtlb_random_idx_prng_3_clock) begin
    i_mmu_dtlb_random_idx_prng_3_state_0 <= i_mmu_dtlb_random_idx_prng_3_reset | i_mmu_dtlb_random_idx_prng_3__T; // @[PRNG.scala 55:{49,49}]
    if (i_mmu_dtlb_random_idx_prng_3_reset) begin // @[PRNG.scala 55:49]
      i_mmu_dtlb_random_idx_prng_3_state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else begin
      i_mmu_dtlb_random_idx_prng_3_state_1 <= i_mmu_dtlb_random_idx_prng_3_state_0;
    end
  end
  always @(posedge i_mmu_dtlb_clock) begin
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_0_is_valid <= 1'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_0_is_valid <= 1'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      i_mmu_dtlb_tag_0_is_valid <= i_mmu_dtlb__GEN_0;
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_0_asid <= 16'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_0_asid <= 16'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~i_mmu_dtlb__T_3) begin // @[TLB.scala 69:32]
        i_mmu_dtlb_tag_0_asid <= i_mmu_dtlb_io_tlb_renew_bits_asid; // @[TLB.scala 69:32]
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_0_vpn_0 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_0_vpn_0 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~i_mmu_dtlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_dtlb_tag_0_vpn_0 <= i_mmu_dtlb_io_tlb_renew_bits_vpn_0; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_0_vpn_1 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_0_vpn_1 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~i_mmu_dtlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_dtlb_tag_0_vpn_1 <= i_mmu_dtlb_io_tlb_renew_bits_vpn_1; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_0_vpn_2 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_0_vpn_2 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (~i_mmu_dtlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_dtlb_tag_0_vpn_2 <= i_mmu_dtlb_io_tlb_renew_bits_vpn_2; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_1_is_valid <= 1'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_1_is_valid <= 1'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      i_mmu_dtlb_tag_1_is_valid <= i_mmu_dtlb__GEN_1;
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_1_asid <= 16'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_1_asid <= 16'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (i_mmu_dtlb__T_3) begin // @[TLB.scala 69:32]
        i_mmu_dtlb_tag_1_asid <= i_mmu_dtlb_io_tlb_renew_bits_asid; // @[TLB.scala 69:32]
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_1_vpn_0 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_1_vpn_0 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (i_mmu_dtlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_dtlb_tag_1_vpn_0 <= i_mmu_dtlb_io_tlb_renew_bits_vpn_0; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_1_vpn_1 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_1_vpn_1 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (i_mmu_dtlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_dtlb_tag_1_vpn_1 <= i_mmu_dtlb_io_tlb_renew_bits_vpn_1; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 59:20]
      i_mmu_dtlb_tag_1_vpn_2 <= 9'h0; // @[TLB.scala 59:20]
    end else if (i_mmu_dtlb_io_sfence_vma) begin // @[TLB.scala 64:25]
      i_mmu_dtlb_tag_1_vpn_2 <= 9'h0; // @[TLB.scala 65:47]
    end else if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
      if (i_mmu_dtlb__T_5) begin // @[TLB.scala 70:32]
        i_mmu_dtlb_tag_1_vpn_2 <= i_mmu_dtlb_io_tlb_renew_bits_vpn_2; // @[TLB.scala 70:32]
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_dtlb_pte_0_value <= 64'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_dtlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (~i_mmu_dtlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_dtlb_pte_0_value <= i_mmu_dtlb_io_tlb_renew_bits_value; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_dtlb_pte_0_is_giga_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_dtlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (~i_mmu_dtlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_dtlb_pte_0_is_giga_page <= i_mmu_dtlb_io_tlb_renew_bits_is_giga_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_dtlb_pte_0_is_mega_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_dtlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (~i_mmu_dtlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_dtlb_pte_0_is_mega_page <= i_mmu_dtlb_io_tlb_renew_bits_is_mega_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_dtlb_pte_1_value <= 64'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_dtlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (i_mmu_dtlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_dtlb_pte_1_value <= i_mmu_dtlb_io_tlb_renew_bits_value; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_dtlb_pte_1_is_giga_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_dtlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (i_mmu_dtlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_dtlb_pte_1_is_giga_page <= i_mmu_dtlb_io_tlb_renew_bits_is_giga_page; // @[TLB.scala 71:32]
        end
      end
    end
    if (i_mmu_dtlb_reset) begin // @[TLB.scala 62:20]
      i_mmu_dtlb_pte_1_is_mega_page <= 1'h0; // @[TLB.scala 62:20]
    end else if (!(i_mmu_dtlb_io_sfence_vma)) begin // @[TLB.scala 64:25]
      if (i_mmu_dtlb_io_tlb_renew_valid) begin // @[TLB.scala 67:33]
        if (i_mmu_dtlb__T_7) begin // @[TLB.scala 71:32]
          i_mmu_dtlb_pte_1_is_mega_page <= i_mmu_dtlb_io_tlb_renew_bits_is_mega_page; // @[TLB.scala 71:32]
        end
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (i_mmu_dtlb__T_15 & i_mmu_dtlb__T_16) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Fail at tlb, more than 1 entry hit!\n    at TLB.scala:110 assert( PopCount( tlb_hit.asUInt ) <= 1.U, \"Assert Fail at tlb, more than 1 entry hit!\"  )\n"
            ); // @[TLB.scala 110:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~i_mmu_dtlb__T_13 & i_mmu_dtlb__T_15) begin
          $fatal; // @[TLB.scala 110:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge i_mmu_iptw_clock) begin
    if (i_mmu_iptw_reset) begin // @[PTW.scala 87:26]
      i_mmu_iptw_currState <= 2'h0; // @[PTW.scala 87:26]
    end else if (i_mmu_iptw__T_1) begin // @[PTW.scala 110:23]
      if (i_mmu_iptw__nextState_T) begin // @[PTW.scala 112:23]
        i_mmu_iptw_currState <= 2'h1;
      end else begin
        i_mmu_iptw_currState <= 2'h0;
      end
    end else if (i_mmu_iptw__T_2) begin // @[PTW.scala 110:23]
      if (i_mmu_iptw_is_trans_done) begin // @[PTW.scala 116:12]
        i_mmu_iptw_currState <= i_mmu_iptw__nextState_T_5;
      end else begin
        i_mmu_iptw_currState <= 2'h1;
      end
    end else if (i_mmu_iptw__T_3) begin // @[PTW.scala 110:23]
      i_mmu_iptw_currState <= i_mmu_iptw__nextState_T_11; // @[PTW.scala 123:17]
    end else begin
      i_mmu_iptw_currState <= i_mmu_iptw__GEN_6;
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 89:27]
      i_mmu_iptw_kill_trans <= 1'h0; // @[PTW.scala 89:27]
    end else begin
      i_mmu_iptw_kill_trans <= i_mmu_iptw__GEN_36;
    end
    if (i_mmu_iptw_reset) begin // @[Edges.scala 228:27]
      i_mmu_iptw_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (i_mmu_iptw__T) begin // @[Edges.scala 234:17]
      if (i_mmu_iptw_first) begin // @[Edges.scala 235:21]
        i_mmu_iptw_counter <= i_mmu_iptw_beats1;
      end else begin
        i_mmu_iptw_counter <= i_mmu_iptw_counter1;
      end
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 95:26]
      i_mmu_iptw_addr_qout <= 32'h0; // @[PTW.scala 95:26]
    end else begin
      i_mmu_iptw_addr_qout <= i_mmu_iptw_addr_dnxt; // @[PTW.scala 95:26]
    end
    if (i_mmu_iptw__T_19) begin // @[PTW.scala 243:46]
      if (i_mmu__T_23) begin // @[MMU.scala 292:45]
        i_mmu_iptw_ptw_access_data_lo_0 <= i_mmu_io_ptw_access_bits_data; // @[MMU.scala 293:24]
      end else begin
        i_mmu_iptw_ptw_access_data_lo_0 <= 64'h0; // @[MMU.scala 281:27]
      end
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 234:24]
      i_mmu_iptw_pte_value_value <= 64'h0; // @[PTW.scala 234:24]
    end else if (i_mmu_iptw_is_trans_done) begin // @[PTW.scala 240:8]
      i_mmu_iptw_pte_value_value <= i_mmu_iptw_pte_value_data_sel;
    end
    if (i_mmu_iptw__walkReq_T_2) begin // @[Reg.scala 20:18]
      i_mmu_iptw_walkReq_is_X <= i_mmu_iptw_io_ptw_i_bits_is_X; // @[Reg.scala 20:22]
    end
    if (i_mmu_iptw__walkReq_T_2) begin // @[Reg.scala 20:18]
      i_mmu_iptw_walkReq_vaddr <= i_mmu_iptw_io_ptw_i_bits_vaddr; // @[Reg.scala 20:22]
    end
    if (i_mmu_iptw__walkReq_T_2) begin // @[Reg.scala 20:18]
      i_mmu_iptw_asidReq <= i_mmu_iptw__asidReq_T; // @[Reg.scala 20:22]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_is_X <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_iptw_walkRspBits_is_X <= i_mmu_iptw_walkReq_is_X; // @[PTW.scala 199:22]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_renew_value <= 64'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      if (i_mmu_iptw_is_trans_done) begin // @[PTW.scala 240:8]
        i_mmu_iptw_walkRspBits_renew_value <= i_mmu_iptw_pte_value_data_sel;
      end else begin
        i_mmu_iptw_walkRspBits_renew_value <= i_mmu_iptw_pte_value_value;
      end
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_renew_is_giga_page <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_iptw_walkRspBits_renew_is_giga_page <= i_mmu_iptw__pte_is_giga_page_T_1; // @[PTW.scala 202:58]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_renew_is_mega_page <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_iptw_walkRspBits_renew_is_mega_page <= i_mmu_iptw__pte_is_mega_page_T_1; // @[PTW.scala 202:58]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_renew_asid <= 16'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_iptw_walkRspBits_renew_asid <= i_mmu_iptw_asidReq; // @[PTW.scala 206:30]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_renew_vpn_0 <= 9'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_iptw_walkRspBits_renew_vpn_0 <= i_mmu_iptw__addr_dnxt_T_7; // @[PTW.scala 203:30]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_renew_vpn_1 <= 9'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_iptw_walkRspBits_renew_vpn_1 <= i_mmu_iptw__addr_dnxt_T_4; // @[PTW.scala 204:30]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_renew_vpn_2 <= 9'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_iptw_walkRspBits_renew_vpn_2 <= i_mmu_iptw__walkRspBits_renew_vpn_2_T; // @[PTW.scala 205:30]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_is_ptw_fail <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_iptw_walkRspBits_is_ptw_fail <= i_mmu_iptw__is_ptw_fail_T_36; // @[PTW.scala 198:29]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_iptw_walkRspBits_is_access_fault <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_iptw__T_7) begin // @[PTW.scala 188:73]
      i_mmu_iptw_walkRspBits_is_access_fault <= 1'h0; // @[PTW.scala 189:33]
    end else if (i_mmu_iptw__T_8) begin // @[PTW.scala 191:32]
      i_mmu_iptw_walkRspBits_is_access_fault <= i_mmu_iptw__walkRspBits_is_access_fault_T_1; // @[PTW.scala 192:33]
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 105:29]
      i_mmu_iptw_walkRspValid <= 1'h0; // @[PTW.scala 105:29]
    end else begin
      i_mmu_iptw_walkRspValid <= i_mmu_iptw__GEN_25;
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 342:30]
      i_mmu_iptw_ptw_get_valid <= 1'h0; // @[PTW.scala 342:30]
    end else begin
      i_mmu_iptw_ptw_get_valid <= i_mmu_iptw__GEN_32;
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 343:33]
      i_mmu_iptw_ptw_access_ready <= 1'h0; // @[PTW.scala 343:33]
    end else begin
      i_mmu_iptw_ptw_access_ready <= i_mmu_iptw__GEN_34;
    end
    if (i_mmu_iptw_reset) begin // @[PTW.scala 348:29]
      i_mmu_iptw_is_get_reqed <= 1'h0; // @[PTW.scala 348:29]
    end else begin
      i_mmu_iptw_is_get_reqed <= i_mmu_iptw__GEN_30;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (i_mmu_iptw__T_11 & i_mmu_iptw__T_14 & i_mmu_iptw__T_15) begin
          $fwrite(32'h80000002,"Assertion failed\n    at PTW.scala:210 assert( io.ptw_o.valid === false.B )\n"); // @[PTW.scala 210:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~i_mmu_iptw__T_12 & (i_mmu_iptw__T_11 & i_mmu_iptw__T_14)) begin
          $fatal; // @[PTW.scala 210:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge i_mmu_dptw_clock) begin
    if (i_mmu_dptw_reset) begin // @[PTW.scala 87:26]
      i_mmu_dptw_currState <= 2'h0; // @[PTW.scala 87:26]
    end else if (i_mmu_dptw__T_1) begin // @[PTW.scala 110:23]
      if (i_mmu_dptw__nextState_T) begin // @[PTW.scala 112:23]
        i_mmu_dptw_currState <= 2'h1;
      end else begin
        i_mmu_dptw_currState <= 2'h0;
      end
    end else if (i_mmu_dptw__T_2) begin // @[PTW.scala 110:23]
      if (i_mmu_dptw_is_trans_done) begin // @[PTW.scala 116:12]
        i_mmu_dptw_currState <= i_mmu_dptw__nextState_T_5;
      end else begin
        i_mmu_dptw_currState <= 2'h1;
      end
    end else if (i_mmu_dptw__T_3) begin // @[PTW.scala 110:23]
      i_mmu_dptw_currState <= i_mmu_dptw__nextState_T_11; // @[PTW.scala 123:17]
    end else begin
      i_mmu_dptw_currState <= i_mmu_dptw__GEN_6;
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 89:27]
      i_mmu_dptw_kill_trans <= 1'h0; // @[PTW.scala 89:27]
    end else begin
      i_mmu_dptw_kill_trans <= i_mmu_dptw__GEN_36;
    end
    if (i_mmu_dptw_reset) begin // @[Edges.scala 228:27]
      i_mmu_dptw_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (i_mmu_dptw__T) begin // @[Edges.scala 234:17]
      if (i_mmu_dptw_first) begin // @[Edges.scala 235:21]
        i_mmu_dptw_counter <= i_mmu_dptw_beats1;
      end else begin
        i_mmu_dptw_counter <= i_mmu_dptw_counter1;
      end
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 95:26]
      i_mmu_dptw_addr_qout <= 32'h0; // @[PTW.scala 95:26]
    end else begin
      i_mmu_dptw_addr_qout <= i_mmu_dptw_addr_dnxt; // @[PTW.scala 95:26]
    end
    if (i_mmu_dptw__T_19) begin // @[PTW.scala 243:46]
      if (i_mmu__T_23) begin // @[MMU.scala 292:45]
        i_mmu_dptw_ptw_access_data_lo_0 <= 64'h0; // @[MMU.scala 282:27]
      end else if (i_mmu_io_ptw_access_bits_source) begin // @[MMU.scala 294:52]
        i_mmu_dptw_ptw_access_data_lo_0 <= i_mmu_io_ptw_access_bits_data; // @[MMU.scala 295:24]
      end else begin
        i_mmu_dptw_ptw_access_data_lo_0 <= 64'h0; // @[MMU.scala 282:27]
      end
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 234:24]
      i_mmu_dptw_pte_value_value <= 64'h0; // @[PTW.scala 234:24]
    end else if (i_mmu_dptw_is_trans_done) begin // @[PTW.scala 240:8]
      i_mmu_dptw_pte_value_value <= i_mmu_dptw_pte_value_data_sel;
    end
    if (i_mmu_dptw__walkReq_T_2) begin // @[Reg.scala 20:18]
      i_mmu_dptw_walkReq_is_X <= i_mmu_dptw_io_ptw_i_bits_is_X; // @[Reg.scala 20:22]
    end
    if (i_mmu_dptw__walkReq_T_2) begin // @[Reg.scala 20:18]
      i_mmu_dptw_walkReq_vaddr <= i_mmu_dptw_io_ptw_i_bits_vaddr; // @[Reg.scala 20:22]
    end
    if (i_mmu_dptw__walkReq_T_2) begin // @[Reg.scala 20:18]
      i_mmu_dptw_asidReq <= i_mmu_dptw__asidReq_T; // @[Reg.scala 20:22]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_is_X <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_dptw_walkRspBits_is_X <= i_mmu_dptw_walkReq_is_X; // @[PTW.scala 199:22]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_renew_value <= 64'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      if (i_mmu_dptw_is_trans_done) begin // @[PTW.scala 240:8]
        i_mmu_dptw_walkRspBits_renew_value <= i_mmu_dptw_pte_value_data_sel;
      end else begin
        i_mmu_dptw_walkRspBits_renew_value <= i_mmu_dptw_pte_value_value;
      end
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_renew_is_giga_page <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_dptw_walkRspBits_renew_is_giga_page <= i_mmu_dptw__pte_is_giga_page_T_1; // @[PTW.scala 202:58]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_renew_is_mega_page <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_dptw_walkRspBits_renew_is_mega_page <= i_mmu_dptw__pte_is_mega_page_T_1; // @[PTW.scala 202:58]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_renew_asid <= 16'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_dptw_walkRspBits_renew_asid <= i_mmu_dptw_asidReq; // @[PTW.scala 206:30]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_renew_vpn_0 <= 9'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_dptw_walkRspBits_renew_vpn_0 <= i_mmu_dptw__addr_dnxt_T_7; // @[PTW.scala 203:30]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_renew_vpn_1 <= 9'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_dptw_walkRspBits_renew_vpn_1 <= i_mmu_dptw__addr_dnxt_T_4; // @[PTW.scala 204:30]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_renew_vpn_2 <= 9'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_dptw_walkRspBits_renew_vpn_2 <= i_mmu_dptw__walkRspBits_renew_vpn_2_T; // @[PTW.scala 205:30]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_is_ptw_fail <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_11) begin // @[PTW.scala 197:73]
      i_mmu_dptw_walkRspBits_is_ptw_fail <= i_mmu_dptw__is_ptw_fail_T_36; // @[PTW.scala 198:29]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 104:28]
      i_mmu_dptw_walkRspBits_is_access_fault <= 1'h0; // @[PTW.scala 104:28]
    end else if (i_mmu_dptw__T_7) begin // @[PTW.scala 188:73]
      i_mmu_dptw_walkRspBits_is_access_fault <= 1'h0; // @[PTW.scala 189:33]
    end else if (i_mmu_dptw__T_8) begin // @[PTW.scala 191:32]
      i_mmu_dptw_walkRspBits_is_access_fault <= i_mmu_dptw__walkRspBits_is_access_fault_T_1; // @[PTW.scala 192:33]
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 105:29]
      i_mmu_dptw_walkRspValid <= 1'h0; // @[PTW.scala 105:29]
    end else begin
      i_mmu_dptw_walkRspValid <= i_mmu_dptw__GEN_25;
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 342:30]
      i_mmu_dptw_ptw_get_valid <= 1'h0; // @[PTW.scala 342:30]
    end else begin
      i_mmu_dptw_ptw_get_valid <= i_mmu_dptw__GEN_32;
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 343:33]
      i_mmu_dptw_ptw_access_ready <= 1'h0; // @[PTW.scala 343:33]
    end else begin
      i_mmu_dptw_ptw_access_ready <= i_mmu_dptw__GEN_34;
    end
    if (i_mmu_dptw_reset) begin // @[PTW.scala 348:29]
      i_mmu_dptw_is_get_reqed <= 1'h0; // @[PTW.scala 348:29]
    end else begin
      i_mmu_dptw_is_get_reqed <= i_mmu_dptw__GEN_30;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (i_mmu_dptw__T_11 & i_mmu_dptw__T_14 & i_mmu_dptw__T_15) begin
          $fwrite(32'h80000002,"Assertion failed\n    at PTW.scala:210 assert( io.ptw_o.valid === false.B )\n"); // @[PTW.scala 210:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~i_mmu_dptw__T_12 & (i_mmu_dptw__T_11 & i_mmu_dptw__T_14)) begin
          $fatal; // @[PTW.scala 210:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge i_mmu_clock) begin
    if (i_mmu_reset) begin // @[MMU.scala 141:26]
      i_mmu_kill_iptw <= 1'h0; // @[MMU.scala 141:26]
    end else begin
      i_mmu_kill_iptw <= i_mmu__GEN_1;
    end
    if (i_mmu_reset) begin // @[MMU.scala 142:26]
      i_mmu_kill_dptw <= 1'h0; // @[MMU.scala 142:26]
    end else begin
      i_mmu_kill_dptw <= i_mmu__GEN_3;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (i_mmu__T_4 & i_mmu__T_5) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MMU.scala:170 assert( io.lsu_mmu.fire === io.mmu_lsu.fire )\n"
            ); // @[MMU.scala 170:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~i_mmu__T_2 & i_mmu__T_4) begin
          $fatal; // @[MMU.scala 170:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (i_mmu__T_4 & i_mmu__T_13) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MMU.scala:220 assert( ~((iptw.io.ptw_o.bits.is_X & iptw.io.ptw_o.valid) & itlb.io.is_hit & ~kill_iptw )  )\n"
            ); // @[MMU.scala 220:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~i_mmu__T_10 & i_mmu__T_4) begin
          $fatal; // @[MMU.scala 220:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (i_mmu__T_4 & i_mmu__T_22) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MMU.scala:256 assert( ~((~dptw.io.ptw_o.bits.is_X & dptw.io.ptw_o.valid) & dtlb.io.is_hit & ~kill_dptw)  )\n"
            ); // @[MMU.scala 256:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~i_mmu__T_19 & i_mmu__T_4) begin
          $fatal; // @[MMU.scala 256:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (i_mmu_io_cmm_mmu_sfence_vma & i_mmu__T_4 & i_mmu__T_28) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MMU.scala:338 assert( io.if_flush & io.lsu_flush )\n"); // @[MMU.scala 338:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~i_mmu__T_25 & (i_mmu_io_cmm_mmu_sfence_vma & i_mmu__T_4)) begin
          $fatal; // @[MMU.scala 338:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_43 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_0[initvar] = _RAND_43[7:0];
  _RAND_46 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_1[initvar] = _RAND_46[7:0];
  _RAND_49 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_2[initvar] = _RAND_49[7:0];
  _RAND_52 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_3[initvar] = _RAND_52[7:0];
  _RAND_55 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_4[initvar] = _RAND_55[7:0];
  _RAND_58 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_5[initvar] = _RAND_58[7:0];
  _RAND_61 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_6[initvar] = _RAND_61[7:0];
  _RAND_64 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_7[initvar] = _RAND_64[7:0];
  _RAND_67 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_8[initvar] = _RAND_67[7:0];
  _RAND_70 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_9[initvar] = _RAND_70[7:0];
  _RAND_73 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_10[initvar] = _RAND_73[7:0];
  _RAND_76 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_11[initvar] = _RAND_76[7:0];
  _RAND_79 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_12[initvar] = _RAND_79[7:0];
  _RAND_82 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_13[initvar] = _RAND_82[7:0];
  _RAND_85 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_14[initvar] = _RAND_85[7:0];
  _RAND_88 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_datRAM_0_datMem_15[initvar] = _RAND_88[7:0];
  _RAND_91 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    if2_tagRAM_0_tagMem[initvar] = _RAND_91[26:0];
  _RAND_104 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    if3_btb_bypassFifo_ram_target[initvar] = _RAND_104[38:0];
  _RAND_106 = {2{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    if3_btb_btb_table_target[initvar] = _RAND_106[38:0];
  _RAND_112 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    if3_bim_bim_P[initvar] = _RAND_112[0:0];
  _RAND_115 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    if3_bim_bim_H[initvar] = _RAND_115[0:0];
  _RAND_118 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    if3_bim_bypassFifo_ram_0[initvar] = _RAND_118[0:0];
  _RAND_119 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    if3_bim_bypassFifo_ram_1[initvar] = _RAND_119[0:0];
  _RAND_169 = {2{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    if4_ras_buf_target[initvar] = _RAND_169[38:0];
  _RAND_947 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_fun_add[initvar] = _RAND_947[0:0];
  _RAND_948 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_fun_slt[initvar] = _RAND_948[0:0];
  _RAND_949 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_fun_xor[initvar] = _RAND_949[0:0];
  _RAND_950 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_fun_or[initvar] = _RAND_950[0:0];
  _RAND_951 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_fun_and[initvar] = _RAND_951[0:0];
  _RAND_952 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_fun_sll[initvar] = _RAND_952[0:0];
  _RAND_953 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_fun_srl[initvar] = _RAND_953[0:0];
  _RAND_954 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_fun_sra[initvar] = _RAND_954[0:0];
  _RAND_955 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_param_rd0[initvar] = _RAND_955[5:0];
  _RAND_956 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_param_is_32w[initvar] = _RAND_956[0:0];
  _RAND_957 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_param_is_usi[initvar] = _RAND_957[0:0];
  _RAND_958 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_param_dat_op1[initvar] = _RAND_958[63:0];
  _RAND_959 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_aluIssFifo_0_ram_param_dat_op2[initvar] = _RAND_959[63:0];
  _RAND_961 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_mul[initvar] = _RAND_961[0:0];
  _RAND_962 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_mulh[initvar] = _RAND_962[0:0];
  _RAND_963 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_mulhsu[initvar] = _RAND_963[0:0];
  _RAND_964 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_mulhu[initvar] = _RAND_964[0:0];
  _RAND_965 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_div[initvar] = _RAND_965[0:0];
  _RAND_966 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_divu[initvar] = _RAND_966[0:0];
  _RAND_967 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_rem[initvar] = _RAND_967[0:0];
  _RAND_968 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_remu[initvar] = _RAND_968[0:0];
  _RAND_969 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_mulw[initvar] = _RAND_969[0:0];
  _RAND_970 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_divw[initvar] = _RAND_970[0:0];
  _RAND_971 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_divuw[initvar] = _RAND_971[0:0];
  _RAND_972 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_remw[initvar] = _RAND_972[0:0];
  _RAND_973 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_fun_remuw[initvar] = _RAND_973[0:0];
  _RAND_974 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_param_rd0[initvar] = _RAND_974[5:0];
  _RAND_975 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_param_dat_op1[initvar] = _RAND_975[63:0];
  _RAND_976 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_mulIssFifo_0_ram_param_dat_op2[initvar] = _RAND_976[63:0];
  _RAND_978 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_fun_jalr[initvar] = _RAND_978[0:0];
  _RAND_979 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_fun_beq[initvar] = _RAND_979[0:0];
  _RAND_980 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_fun_bne[initvar] = _RAND_980[0:0];
  _RAND_981 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_fun_blt[initvar] = _RAND_981[0:0];
  _RAND_982 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_fun_bge[initvar] = _RAND_982[0:0];
  _RAND_983 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_fun_bltu[initvar] = _RAND_983[0:0];
  _RAND_984 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_fun_bgeu[initvar] = _RAND_984[0:0];
  _RAND_985 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_param_rd0[initvar] = _RAND_985[5:0];
  _RAND_986 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_param_is_rvc[initvar] = _RAND_986[0:0];
  _RAND_987 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_param_pc[initvar] = _RAND_987[63:0];
  _RAND_988 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_param_imm[initvar] = _RAND_988[63:0];
  _RAND_989 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_param_dat_op1[initvar] = _RAND_989[63:0];
  _RAND_990 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_bruIssFifo_ram_param_dat_op2[initvar] = _RAND_990[63:0];
  _RAND_992 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_csrIssFifo_ram_fun_rw[initvar] = _RAND_992[0:0];
  _RAND_993 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_csrIssFifo_ram_fun_rs[initvar] = _RAND_993[0:0];
  _RAND_994 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_csrIssFifo_ram_fun_rc[initvar] = _RAND_994[0:0];
  _RAND_995 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_csrIssFifo_ram_param_rd0[initvar] = _RAND_995[5:0];
  _RAND_996 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_csrIssFifo_ram_param_dat_op1[initvar] = _RAND_996[63:0];
  _RAND_997 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_csrIssFifo_ram_param_dat_op2[initvar] = _RAND_997[63:0];
  _RAND_999 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_lb[initvar] = _RAND_999[0:0];
  _RAND_1000 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_lh[initvar] = _RAND_1000[0:0];
  _RAND_1001 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_lw[initvar] = _RAND_1001[0:0];
  _RAND_1002 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_ld[initvar] = _RAND_1002[0:0];
  _RAND_1003 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_lbu[initvar] = _RAND_1003[0:0];
  _RAND_1004 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_lhu[initvar] = _RAND_1004[0:0];
  _RAND_1005 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_lwu[initvar] = _RAND_1005[0:0];
  _RAND_1006 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_sb[initvar] = _RAND_1006[0:0];
  _RAND_1007 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_sh[initvar] = _RAND_1007[0:0];
  _RAND_1008 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_sw[initvar] = _RAND_1008[0:0];
  _RAND_1009 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_sd[initvar] = _RAND_1009[0:0];
  _RAND_1010 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_fence[initvar] = _RAND_1010[0:0];
  _RAND_1011 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_fence_i[initvar] = _RAND_1011[0:0];
  _RAND_1012 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_sfence_vma[initvar] = _RAND_1012[0:0];
  _RAND_1013 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_lr_w[initvar] = _RAND_1013[0:0];
  _RAND_1014 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_sc_w[initvar] = _RAND_1014[0:0];
  _RAND_1015 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoswap_w[initvar] = _RAND_1015[0:0];
  _RAND_1016 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoadd_w[initvar] = _RAND_1016[0:0];
  _RAND_1017 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoxor_w[initvar] = _RAND_1017[0:0];
  _RAND_1018 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoand_w[initvar] = _RAND_1018[0:0];
  _RAND_1019 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoor_w[initvar] = _RAND_1019[0:0];
  _RAND_1020 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amomin_w[initvar] = _RAND_1020[0:0];
  _RAND_1021 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amomax_w[initvar] = _RAND_1021[0:0];
  _RAND_1022 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amominu_w[initvar] = _RAND_1022[0:0];
  _RAND_1023 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amomaxu_w[initvar] = _RAND_1023[0:0];
  _RAND_1024 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_lr_d[initvar] = _RAND_1024[0:0];
  _RAND_1025 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_sc_d[initvar] = _RAND_1025[0:0];
  _RAND_1026 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoswap_d[initvar] = _RAND_1026[0:0];
  _RAND_1027 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoadd_d[initvar] = _RAND_1027[0:0];
  _RAND_1028 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoxor_d[initvar] = _RAND_1028[0:0];
  _RAND_1029 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoand_d[initvar] = _RAND_1029[0:0];
  _RAND_1030 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amoor_d[initvar] = _RAND_1030[0:0];
  _RAND_1031 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amomin_d[initvar] = _RAND_1031[0:0];
  _RAND_1032 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amomax_d[initvar] = _RAND_1032[0:0];
  _RAND_1033 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amominu_d[initvar] = _RAND_1033[0:0];
  _RAND_1034 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_amomaxu_d[initvar] = _RAND_1034[0:0];
  _RAND_1035 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_flw[initvar] = _RAND_1035[0:0];
  _RAND_1036 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_fsw[initvar] = _RAND_1036[0:0];
  _RAND_1037 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_fld[initvar] = _RAND_1037[0:0];
  _RAND_1038 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_fun_fsd[initvar] = _RAND_1038[0:0];
  _RAND_1039 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_param_rd0[initvar] = _RAND_1039[5:0];
  _RAND_1040 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_param_dat_op1[initvar] = _RAND_1040[63:0];
  _RAND_1041 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    iss_stage_lsuIssFifo_ram_param_dat_op2[initvar] = _RAND_1041[63:0];
  _RAND_1266 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_alu_0_alu_exe_iwb_fifo_ram_rd0[initvar] = _RAND_1266[5:0];
  _RAND_1267 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_alu_0_alu_exe_iwb_fifo_ram_res[initvar] = _RAND_1267[63:0];
  _RAND_1269 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_bru_exe_iwb_fifo_ram_rd0[initvar] = _RAND_1269[5:0];
  _RAND_1270 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_bru_exe_iwb_fifo_ram_res[initvar] = _RAND_1270[63:0];
  _RAND_1272 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_bctq_ram_pc[initvar] = _RAND_1272[38:0];
  _RAND_1273 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_bctq_ram_bimResp_bim_p[initvar] = _RAND_1273[0:0];
  _RAND_1274 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_bctq_ram_bimResp_bim_h[initvar] = _RAND_1274[0:0];
  _RAND_1275 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_bctq_ram_isPredictTaken[initvar] = _RAND_1275[0:0];
  _RAND_1276 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_bctq_ram_isFinalTaken[initvar] = _RAND_1276[0:0];
  _RAND_1277 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_bctq_ram_finalTarget[initvar] = _RAND_1277[63:0];
  _RAND_1279 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_jctq_ram_pc[initvar] = _RAND_1279[38:0];
  _RAND_1280 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_jctq_ram_btbResp_target[initvar] = _RAND_1280[38:0];
  _RAND_1281 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_jctq_ram_rasResp_target[initvar] = _RAND_1281[38:0];
  _RAND_1282 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_jctq_ram_isRas[initvar] = _RAND_1282[0:0];
  _RAND_1283 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_bru_jctq_ram_finalTarget[initvar] = _RAND_1283[63:0];
  _RAND_1468 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_probeUnit_probe_fifo_ram[initvar] = _RAND_1468[31:0];
  _RAND_1470 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_paddr[initvar] = _RAND_1470[31:0];
  _RAND_1471 = {4{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_data[initvar] = _RAND_1471[127:0];
  _RAND_1472 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_releaseData[initvar] = _RAND_1472[0:0];
  _RAND_1473 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_release[initvar] = _RAND_1473[0:0];
  _RAND_1474 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probe[initvar] = _RAND_1474[0:0];
  _RAND_1475 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_ram_is_probeData[initvar] = _RAND_1475[0:0];
  _RAND_1484 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_chkIdx[initvar] = _RAND_1484[0:0];
  _RAND_1485 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_paddr[initvar] = _RAND_1485[31:0];
  _RAND_1486 = {4{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_wdata[initvar] = _RAND_1486[127:0];
  _RAND_1487 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_wstrb[initvar] = _RAND_1487[15:0];
  _RAND_1488 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lb[initvar] = _RAND_1488[0:0];
  _RAND_1489 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lh[initvar] = _RAND_1489[0:0];
  _RAND_1490 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lw[initvar] = _RAND_1490[0:0];
  _RAND_1491 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_ld[initvar] = _RAND_1491[0:0];
  _RAND_1492 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lbu[initvar] = _RAND_1492[0:0];
  _RAND_1493 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lhu[initvar] = _RAND_1493[0:0];
  _RAND_1494 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lwu[initvar] = _RAND_1494[0:0];
  _RAND_1495 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sb[initvar] = _RAND_1495[0:0];
  _RAND_1496 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sh[initvar] = _RAND_1496[0:0];
  _RAND_1497 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sw[initvar] = _RAND_1497[0:0];
  _RAND_1498 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sd[initvar] = _RAND_1498[0:0];
  _RAND_1499 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_w[initvar] = _RAND_1499[0:0];
  _RAND_1500 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_w[initvar] = _RAND_1500[0:0];
  _RAND_1501 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_w[initvar] = _RAND_1501[0:0];
  _RAND_1502 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_w[initvar] = _RAND_1502[0:0];
  _RAND_1503 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_w[initvar] = _RAND_1503[0:0];
  _RAND_1504 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_w[initvar] = _RAND_1504[0:0];
  _RAND_1505 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_w[initvar] = _RAND_1505[0:0];
  _RAND_1506 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_w[initvar] = _RAND_1506[0:0];
  _RAND_1507 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_w[initvar] = _RAND_1507[0:0];
  _RAND_1508 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_w[initvar] = _RAND_1508[0:0];
  _RAND_1509 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_w[initvar] = _RAND_1509[0:0];
  _RAND_1510 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_lr_d[initvar] = _RAND_1510[0:0];
  _RAND_1511 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_sc_d[initvar] = _RAND_1511[0:0];
  _RAND_1512 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoswap_d[initvar] = _RAND_1512[0:0];
  _RAND_1513 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoadd_d[initvar] = _RAND_1513[0:0];
  _RAND_1514 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoxor_d[initvar] = _RAND_1514[0:0];
  _RAND_1515 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoand_d[initvar] = _RAND_1515[0:0];
  _RAND_1516 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amoor_d[initvar] = _RAND_1516[0:0];
  _RAND_1517 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomin_d[initvar] = _RAND_1517[0:0];
  _RAND_1518 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomax_d[initvar] = _RAND_1518[0:0];
  _RAND_1519 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amominu_d[initvar] = _RAND_1519[0:0];
  _RAND_1520 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_amomaxu_d[initvar] = _RAND_1520[0:0];
  _RAND_1521 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_flw[initvar] = _RAND_1521[0:0];
  _RAND_1522 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_fsw[initvar] = _RAND_1522[0:0];
  _RAND_1523 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_fld[initvar] = _RAND_1523[0:0];
  _RAND_1524 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_fsd[initvar] = _RAND_1524[0:0];
  _RAND_1525 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_probe[initvar] = _RAND_1525[0:0];
  _RAND_1526 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_grant[initvar] = _RAND_1526[0:0];
  _RAND_1527 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_fun_preft[initvar] = _RAND_1527[0:0];
  _RAND_1528 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_lsEntry_ram_rd_rd0[initvar] = _RAND_1528[5:0];
  _RAND_1532 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_rtn_fifo_ram_chkIdx[initvar] = _RAND_1532[0:0];
  _RAND_1533 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_rtn_fifo_ram_wb_rd0[initvar] = _RAND_1533[5:0];
  _RAND_1534 = {2{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_rtn_fifo_ram_wb_res[initvar] = _RAND_1534[63:0];
  _RAND_1535 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_rtn_fifo_ram_is_load_amo[initvar] = _RAND_1535[0:0];
  _RAND_1536 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_rtn_fifo_ram_is_flw[initvar] = _RAND_1536[0:0];
  _RAND_1537 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_rtn_fifo_ram_is_fld[initvar] = _RAND_1537[0:0];
  _RAND_1541 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_chkIdx[initvar] = _RAND_1541[0:0];
  _RAND_1542 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_paddr[initvar] = _RAND_1542[31:0];
  _RAND_1543 = {4{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_wdata[initvar] = _RAND_1543[127:0];
  _RAND_1544 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_wstrb[initvar] = _RAND_1544[15:0];
  _RAND_1545 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lb[initvar] = _RAND_1545[0:0];
  _RAND_1546 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lh[initvar] = _RAND_1546[0:0];
  _RAND_1547 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lw[initvar] = _RAND_1547[0:0];
  _RAND_1548 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_ld[initvar] = _RAND_1548[0:0];
  _RAND_1549 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lbu[initvar] = _RAND_1549[0:0];
  _RAND_1550 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lhu[initvar] = _RAND_1550[0:0];
  _RAND_1551 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lwu[initvar] = _RAND_1551[0:0];
  _RAND_1552 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sb[initvar] = _RAND_1552[0:0];
  _RAND_1553 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sh[initvar] = _RAND_1553[0:0];
  _RAND_1554 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sw[initvar] = _RAND_1554[0:0];
  _RAND_1555 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sd[initvar] = _RAND_1555[0:0];
  _RAND_1556 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_w[initvar] = _RAND_1556[0:0];
  _RAND_1557 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_w[initvar] = _RAND_1557[0:0];
  _RAND_1558 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_w[initvar] = _RAND_1558[0:0];
  _RAND_1559 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_w[initvar] = _RAND_1559[0:0];
  _RAND_1560 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_w[initvar] = _RAND_1560[0:0];
  _RAND_1561 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_w[initvar] = _RAND_1561[0:0];
  _RAND_1562 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_w[initvar] = _RAND_1562[0:0];
  _RAND_1563 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_w[initvar] = _RAND_1563[0:0];
  _RAND_1564 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_w[initvar] = _RAND_1564[0:0];
  _RAND_1565 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_w[initvar] = _RAND_1565[0:0];
  _RAND_1566 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_w[initvar] = _RAND_1566[0:0];
  _RAND_1567 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_lr_d[initvar] = _RAND_1567[0:0];
  _RAND_1568 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_sc_d[initvar] = _RAND_1568[0:0];
  _RAND_1569 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoswap_d[initvar] = _RAND_1569[0:0];
  _RAND_1570 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoadd_d[initvar] = _RAND_1570[0:0];
  _RAND_1571 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoxor_d[initvar] = _RAND_1571[0:0];
  _RAND_1572 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoand_d[initvar] = _RAND_1572[0:0];
  _RAND_1573 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amoor_d[initvar] = _RAND_1573[0:0];
  _RAND_1574 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomin_d[initvar] = _RAND_1574[0:0];
  _RAND_1575 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomax_d[initvar] = _RAND_1575[0:0];
  _RAND_1576 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amominu_d[initvar] = _RAND_1576[0:0];
  _RAND_1577 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_amomaxu_d[initvar] = _RAND_1577[0:0];
  _RAND_1578 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_flw[initvar] = _RAND_1578[0:0];
  _RAND_1579 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsw[initvar] = _RAND_1579[0:0];
  _RAND_1580 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fld[initvar] = _RAND_1580[0:0];
  _RAND_1581 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_fsd[initvar] = _RAND_1581[0:0];
  _RAND_1582 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_probe[initvar] = _RAND_1582[0:0];
  _RAND_1583 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_grant[initvar] = _RAND_1583[0:0];
  _RAND_1584 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_fun_preft[initvar] = _RAND_1584[0:0];
  _RAND_1585 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_cache_0_reload_fifo_ram_rd_rd0[initvar] = _RAND_1585[5:0];
  _RAND_1587 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0[initvar] = _RAND_1587[7:0];
  _RAND_1590 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1[initvar] = _RAND_1590[7:0];
  _RAND_1593 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2[initvar] = _RAND_1593[7:0];
  _RAND_1596 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3[initvar] = _RAND_1596[7:0];
  _RAND_1599 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4[initvar] = _RAND_1599[7:0];
  _RAND_1602 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5[initvar] = _RAND_1602[7:0];
  _RAND_1605 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6[initvar] = _RAND_1605[7:0];
  _RAND_1608 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7[initvar] = _RAND_1608[7:0];
  _RAND_1611 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8[initvar] = _RAND_1611[7:0];
  _RAND_1614 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9[initvar] = _RAND_1614[7:0];
  _RAND_1617 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10[initvar] = _RAND_1617[7:0];
  _RAND_1620 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11[initvar] = _RAND_1620[7:0];
  _RAND_1623 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12[initvar] = _RAND_1623[7:0];
  _RAND_1626 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13[initvar] = _RAND_1626[7:0];
  _RAND_1629 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14[initvar] = _RAND_1629[7:0];
  _RAND_1632 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15[initvar] = _RAND_1632[7:0];
  _RAND_1635 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem[initvar] = _RAND_1635[26:0];
  _RAND_1791 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_lu_wb_fifo_ram_rd0[initvar] = _RAND_1791[5:0];
  _RAND_1792 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_lu_wb_fifo_ram_res[initvar] = _RAND_1792[63:0];
  _RAND_1795 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_su_wb_fifo_ram_rd0[initvar] = _RAND_1795[5:0];
  _RAND_1796 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_su_wb_fifo_ram_res[initvar] = _RAND_1796[63:0];
  _RAND_1798 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_fe_wb_fifo_ram_rd0[initvar] = _RAND_1798[5:0];
  _RAND_1799 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_lsu_fe_wb_fifo_ram_res[initvar] = _RAND_1799[63:0];
  _RAND_1808 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_csr_csr_exe_iwb_fifo_ram_rd0[initvar] = _RAND_1808[5:0];
  _RAND_1809 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_csr_csr_exe_iwb_fifo_ram_res[initvar] = _RAND_1809[63:0];
  _RAND_1811 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_csr_csr_op_fifo_ram_addr[initvar] = _RAND_1811[11:0];
  _RAND_1812 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_csr_csr_op_fifo_ram_dat_i[initvar] = _RAND_1812[63:0];
  _RAND_1813 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_csr_csr_op_fifo_ram_op_rw[initvar] = _RAND_1813[0:0];
  _RAND_1814 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_csr_csr_op_fifo_ram_op_rs[initvar] = _RAND_1814[0:0];
  _RAND_1815 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_csr_csr_op_fifo_ram_op_rc[initvar] = _RAND_1815[0:0];
  _RAND_1817 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_rd0[initvar] = _RAND_1817[5:0];
  _RAND_1818 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    exe_stage_mulDiv_0_mul_exe_iwb_fifo_ram_res[initvar] = _RAND_1818[63:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  if1_pc_qout = _RAND_0[63:0];
  _RAND_1 = {2{`RANDOM}};
  if2_ibuf_buf_0_pc = _RAND_1[38:0];
  _RAND_2 = {1{`RANDOM}};
  if2_ibuf_buf_0_instr = _RAND_2[15:0];
  _RAND_3 = {1{`RANDOM}};
  if2_ibuf_buf_0_isFault = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  if2_ibuf_buf_0_isRedirect = _RAND_4[0:0];
  _RAND_5 = {2{`RANDOM}};
  if2_ibuf_buf_1_pc = _RAND_5[38:0];
  _RAND_6 = {1{`RANDOM}};
  if2_ibuf_buf_1_instr = _RAND_6[15:0];
  _RAND_7 = {1{`RANDOM}};
  if2_ibuf_buf_1_isFault = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  if2_ibuf_buf_1_isRedirect = _RAND_8[0:0];
  _RAND_9 = {2{`RANDOM}};
  if2_ibuf_buf_2_pc = _RAND_9[38:0];
  _RAND_10 = {1{`RANDOM}};
  if2_ibuf_buf_2_instr = _RAND_10[15:0];
  _RAND_11 = {1{`RANDOM}};
  if2_ibuf_buf_2_isFault = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  if2_ibuf_buf_2_isRedirect = _RAND_12[0:0];
  _RAND_13 = {2{`RANDOM}};
  if2_ibuf_buf_3_pc = _RAND_13[38:0];
  _RAND_14 = {1{`RANDOM}};
  if2_ibuf_buf_3_instr = _RAND_14[15:0];
  _RAND_15 = {1{`RANDOM}};
  if2_ibuf_buf_3_isFault = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  if2_ibuf_buf_3_isRedirect = _RAND_16[0:0];
  _RAND_17 = {2{`RANDOM}};
  if2_ibuf_buf_4_pc = _RAND_17[38:0];
  _RAND_18 = {1{`RANDOM}};
  if2_ibuf_buf_4_instr = _RAND_18[15:0];
  _RAND_19 = {1{`RANDOM}};
  if2_ibuf_buf_4_isFault = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  if2_ibuf_buf_4_isRedirect = _RAND_20[0:0];
  _RAND_21 = {2{`RANDOM}};
  if2_ibuf_buf_5_pc = _RAND_21[38:0];
  _RAND_22 = {1{`RANDOM}};
  if2_ibuf_buf_5_instr = _RAND_22[15:0];
  _RAND_23 = {1{`RANDOM}};
  if2_ibuf_buf_5_isFault = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  if2_ibuf_buf_5_isRedirect = _RAND_24[0:0];
  _RAND_25 = {2{`RANDOM}};
  if2_ibuf_buf_6_pc = _RAND_25[38:0];
  _RAND_26 = {1{`RANDOM}};
  if2_ibuf_buf_6_instr = _RAND_26[15:0];
  _RAND_27 = {1{`RANDOM}};
  if2_ibuf_buf_6_isFault = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  if2_ibuf_buf_6_isRedirect = _RAND_28[0:0];
  _RAND_29 = {2{`RANDOM}};
  if2_ibuf_buf_7_pc = _RAND_29[38:0];
  _RAND_30 = {1{`RANDOM}};
  if2_ibuf_buf_7_instr = _RAND_30[15:0];
  _RAND_31 = {1{`RANDOM}};
  if2_ibuf_buf_7_isFault = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  if2_ibuf_buf_7_isRedirect = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  if2_ibuf_buf_valid_0 = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  if2_ibuf_buf_valid_1 = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  if2_ibuf_buf_valid_2 = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  if2_ibuf_buf_valid_3 = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  if2_ibuf_buf_valid_4 = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  if2_ibuf_buf_valid_5 = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  if2_ibuf_buf_valid_6 = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  if2_ibuf_buf_valid_7 = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  if2_ibuf_rd_ptr = _RAND_41[2:0];
  _RAND_42 = {1{`RANDOM}};
  if2_ibuf_wr_ptr = _RAND_42[2:0];
  _RAND_44 = {1{`RANDOM}};
  if2_datRAM_0_datMem_0_MPORT_en_pipe_0 = _RAND_44[0:0];
  _RAND_45 = {1{`RANDOM}};
  if2_datRAM_0_datMem_0_MPORT_addr_pipe_0 = _RAND_45[0:0];
  _RAND_47 = {1{`RANDOM}};
  if2_datRAM_0_datMem_1_MPORT_en_pipe_0 = _RAND_47[0:0];
  _RAND_48 = {1{`RANDOM}};
  if2_datRAM_0_datMem_1_MPORT_addr_pipe_0 = _RAND_48[0:0];
  _RAND_50 = {1{`RANDOM}};
  if2_datRAM_0_datMem_2_MPORT_en_pipe_0 = _RAND_50[0:0];
  _RAND_51 = {1{`RANDOM}};
  if2_datRAM_0_datMem_2_MPORT_addr_pipe_0 = _RAND_51[0:0];
  _RAND_53 = {1{`RANDOM}};
  if2_datRAM_0_datMem_3_MPORT_en_pipe_0 = _RAND_53[0:0];
  _RAND_54 = {1{`RANDOM}};
  if2_datRAM_0_datMem_3_MPORT_addr_pipe_0 = _RAND_54[0:0];
  _RAND_56 = {1{`RANDOM}};
  if2_datRAM_0_datMem_4_MPORT_en_pipe_0 = _RAND_56[0:0];
  _RAND_57 = {1{`RANDOM}};
  if2_datRAM_0_datMem_4_MPORT_addr_pipe_0 = _RAND_57[0:0];
  _RAND_59 = {1{`RANDOM}};
  if2_datRAM_0_datMem_5_MPORT_en_pipe_0 = _RAND_59[0:0];
  _RAND_60 = {1{`RANDOM}};
  if2_datRAM_0_datMem_5_MPORT_addr_pipe_0 = _RAND_60[0:0];
  _RAND_62 = {1{`RANDOM}};
  if2_datRAM_0_datMem_6_MPORT_en_pipe_0 = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  if2_datRAM_0_datMem_6_MPORT_addr_pipe_0 = _RAND_63[0:0];
  _RAND_65 = {1{`RANDOM}};
  if2_datRAM_0_datMem_7_MPORT_en_pipe_0 = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  if2_datRAM_0_datMem_7_MPORT_addr_pipe_0 = _RAND_66[0:0];
  _RAND_68 = {1{`RANDOM}};
  if2_datRAM_0_datMem_8_MPORT_en_pipe_0 = _RAND_68[0:0];
  _RAND_69 = {1{`RANDOM}};
  if2_datRAM_0_datMem_8_MPORT_addr_pipe_0 = _RAND_69[0:0];
  _RAND_71 = {1{`RANDOM}};
  if2_datRAM_0_datMem_9_MPORT_en_pipe_0 = _RAND_71[0:0];
  _RAND_72 = {1{`RANDOM}};
  if2_datRAM_0_datMem_9_MPORT_addr_pipe_0 = _RAND_72[0:0];
  _RAND_74 = {1{`RANDOM}};
  if2_datRAM_0_datMem_10_MPORT_en_pipe_0 = _RAND_74[0:0];
  _RAND_75 = {1{`RANDOM}};
  if2_datRAM_0_datMem_10_MPORT_addr_pipe_0 = _RAND_75[0:0];
  _RAND_77 = {1{`RANDOM}};
  if2_datRAM_0_datMem_11_MPORT_en_pipe_0 = _RAND_77[0:0];
  _RAND_78 = {1{`RANDOM}};
  if2_datRAM_0_datMem_11_MPORT_addr_pipe_0 = _RAND_78[0:0];
  _RAND_80 = {1{`RANDOM}};
  if2_datRAM_0_datMem_12_MPORT_en_pipe_0 = _RAND_80[0:0];
  _RAND_81 = {1{`RANDOM}};
  if2_datRAM_0_datMem_12_MPORT_addr_pipe_0 = _RAND_81[0:0];
  _RAND_83 = {1{`RANDOM}};
  if2_datRAM_0_datMem_13_MPORT_en_pipe_0 = _RAND_83[0:0];
  _RAND_84 = {1{`RANDOM}};
  if2_datRAM_0_datMem_13_MPORT_addr_pipe_0 = _RAND_84[0:0];
  _RAND_86 = {1{`RANDOM}};
  if2_datRAM_0_datMem_14_MPORT_en_pipe_0 = _RAND_86[0:0];
  _RAND_87 = {1{`RANDOM}};
  if2_datRAM_0_datMem_14_MPORT_addr_pipe_0 = _RAND_87[0:0];
  _RAND_89 = {1{`RANDOM}};
  if2_datRAM_0_datMem_15_MPORT_en_pipe_0 = _RAND_89[0:0];
  _RAND_90 = {1{`RANDOM}};
  if2_datRAM_0_datMem_15_MPORT_addr_pipe_0 = _RAND_90[0:0];
  _RAND_92 = {1{`RANDOM}};
  if2_tagRAM_0_tagMem_io_datar_MPORT_en_pipe_0 = _RAND_92[0:0];
  _RAND_93 = {1{`RANDOM}};
  if2_tagRAM_0_tagMem_io_datar_MPORT_addr_pipe_0 = _RAND_93[0:0];
  _RAND_94 = {1{`RANDOM}};
  if2_counter = _RAND_94[0:0];
  _RAND_95 = {2{`RANDOM}};
  if2_icache_access_data_lo_0 = _RAND_95[63:0];
  _RAND_96 = {1{`RANDOM}};
  if2_kill_trans = _RAND_96[0:0];
  _RAND_97 = {1{`RANDOM}};
  if2_is_valid_1_0 = _RAND_97[0:0];
  _RAND_98 = {1{`RANDOM}};
  if2_is_valid_0_0 = _RAND_98[0:0];
  _RAND_99 = {1{`RANDOM}};
  if2_icache_state_qout = _RAND_99[3:0];
  _RAND_100 = {1{`RANDOM}};
  if2_fault_lock = _RAND_100[0:0];
  _RAND_101 = {2{`RANDOM}};
  if2_REG = _RAND_101[63:0];
  _RAND_102 = {1{`RANDOM}};
  if2_REG_1 = _RAND_102[0:0];
  _RAND_103 = {1{`RANDOM}};
  if2_REG_2 = _RAND_103[0:0];
  _RAND_105 = {1{`RANDOM}};
  if3_btb_bypassFifo_maybe_full = _RAND_105[0:0];
  _RAND_107 = {1{`RANDOM}};
  if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_en_pipe_0 = _RAND_107[0:0];
  _RAND_108 = {1{`RANDOM}};
  if3_btb_btb_table_target_bypassFifo_io_enq_bits_MPORT_addr_pipe_0 = _RAND_108[1:0];
  _RAND_109 = {1{`RANDOM}};
  if3_btb_por_reset = _RAND_109[0:0];
  _RAND_110 = {1{`RANDOM}};
  if3_btb_reset_cl = _RAND_110[1:0];
  _RAND_111 = {1{`RANDOM}};
  if3_btb_bypassFifo_io_enq_valid_REG = _RAND_111[0:0];
  _RAND_113 = {1{`RANDOM}};
  if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_en_pipe_0 = _RAND_113[0:0];
  _RAND_114 = {1{`RANDOM}};
  if3_bim_bim_P_bypassFifo_io_enq_bits_0_MPORT_addr_pipe_0 = _RAND_114[2:0];
  _RAND_116 = {1{`RANDOM}};
  if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_en_pipe_0 = _RAND_116[0:0];
  _RAND_117 = {1{`RANDOM}};
  if3_bim_bim_H_bypassFifo_io_enq_bits_1_MPORT_addr_pipe_0 = _RAND_117[2:0];
  _RAND_120 = {1{`RANDOM}};
  if3_bim_bypassFifo_maybe_full = _RAND_120[0:0];
  _RAND_121 = {1{`RANDOM}};
  if3_bim_por_reset = _RAND_121[0:0];
  _RAND_122 = {1{`RANDOM}};
  if3_bim_reset_cl = _RAND_122[2:0];
  _RAND_123 = {1{`RANDOM}};
  if3_bim_bypassFifo_io_enq_valid_REG = _RAND_123[0:0];
  _RAND_124 = {2{`RANDOM}};
  if3_btbFifo_fifo_buf_0_target = _RAND_124[38:0];
  _RAND_125 = {2{`RANDOM}};
  if3_btbFifo_fifo_buf_1_target = _RAND_125[38:0];
  _RAND_126 = {1{`RANDOM}};
  if3_btbFifo_fifo_buf_valid_0 = _RAND_126[0:0];
  _RAND_127 = {1{`RANDOM}};
  if3_btbFifo_fifo_buf_valid_1 = _RAND_127[0:0];
  _RAND_128 = {1{`RANDOM}};
  if3_btbFifo_fifo_rd_ptr = _RAND_128[0:0];
  _RAND_129 = {1{`RANDOM}};
  if3_btbFifo_fifo_wr_ptr = _RAND_129[0:0];
  _RAND_130 = {1{`RANDOM}};
  if3_bimFifo_fifo_buf_0_bim_p = _RAND_130[0:0];
  _RAND_131 = {1{`RANDOM}};
  if3_bimFifo_fifo_buf_0_bim_h = _RAND_131[0:0];
  _RAND_132 = {1{`RANDOM}};
  if3_bimFifo_fifo_buf_1_bim_p = _RAND_132[0:0];
  _RAND_133 = {1{`RANDOM}};
  if3_bimFifo_fifo_buf_1_bim_h = _RAND_133[0:0];
  _RAND_134 = {1{`RANDOM}};
  if3_bimFifo_fifo_buf_valid_0 = _RAND_134[0:0];
  _RAND_135 = {1{`RANDOM}};
  if3_bimFifo_fifo_buf_valid_1 = _RAND_135[0:0];
  _RAND_136 = {1{`RANDOM}};
  if3_bimFifo_fifo_rd_ptr = _RAND_136[0:0];
  _RAND_137 = {1{`RANDOM}};
  if3_bimFifo_fifo_wr_ptr = _RAND_137[0:0];
  _RAND_138 = {1{`RANDOM}};
  if3_tageFifo_fifo_buf_valid_0 = _RAND_138[0:0];
  _RAND_139 = {1{`RANDOM}};
  if3_tageFifo_fifo_buf_valid_1 = _RAND_139[0:0];
  _RAND_140 = {1{`RANDOM}};
  if3_tageFifo_fifo_rd_ptr = _RAND_140[0:0];
  _RAND_141 = {1{`RANDOM}};
  if3_tageFifo_fifo_wr_ptr = _RAND_141[0:0];
  _RAND_142 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_0_isRVC = _RAND_142[0:0];
  _RAND_143 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_0_instr = _RAND_143[31:0];
  _RAND_144 = {2{`RANDOM}};
  if3_if3_resp_fifo_buf_0_pc = _RAND_144[38:0];
  _RAND_145 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_0_isRedirect = _RAND_145[0:0];
  _RAND_146 = {2{`RANDOM}};
  if3_if3_resp_fifo_buf_0_target = _RAND_146[38:0];
  _RAND_147 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_1_isRVC = _RAND_147[0:0];
  _RAND_148 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_1_instr = _RAND_148[31:0];
  _RAND_149 = {2{`RANDOM}};
  if3_if3_resp_fifo_buf_1_pc = _RAND_149[38:0];
  _RAND_150 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_1_isRedirect = _RAND_150[0:0];
  _RAND_151 = {2{`RANDOM}};
  if3_if3_resp_fifo_buf_1_target = _RAND_151[38:0];
  _RAND_152 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_2_isRVC = _RAND_152[0:0];
  _RAND_153 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_2_instr = _RAND_153[31:0];
  _RAND_154 = {2{`RANDOM}};
  if3_if3_resp_fifo_buf_2_pc = _RAND_154[38:0];
  _RAND_155 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_2_isRedirect = _RAND_155[0:0];
  _RAND_156 = {2{`RANDOM}};
  if3_if3_resp_fifo_buf_2_target = _RAND_156[38:0];
  _RAND_157 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_3_isRVC = _RAND_157[0:0];
  _RAND_158 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_3_instr = _RAND_158[31:0];
  _RAND_159 = {2{`RANDOM}};
  if3_if3_resp_fifo_buf_3_pc = _RAND_159[38:0];
  _RAND_160 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_3_isRedirect = _RAND_160[0:0];
  _RAND_161 = {2{`RANDOM}};
  if3_if3_resp_fifo_buf_3_target = _RAND_161[38:0];
  _RAND_162 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_valid_0 = _RAND_162[0:0];
  _RAND_163 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_valid_1 = _RAND_163[0:0];
  _RAND_164 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_valid_2 = _RAND_164[0:0];
  _RAND_165 = {1{`RANDOM}};
  if3_if3_resp_fifo_buf_valid_3 = _RAND_165[0:0];
  _RAND_166 = {1{`RANDOM}};
  if3_if3_resp_fifo_rd_ptr = _RAND_166[1:0];
  _RAND_167 = {1{`RANDOM}};
  if3_if3_resp_fifo_wr_ptr = _RAND_167[1:0];
  _RAND_168 = {1{`RANDOM}};
  if3_pipeLineLock = _RAND_168[0:0];
  _RAND_170 = {1{`RANDOM}};
  if4_ras_btm_ptr = _RAND_170[2:0];
  _RAND_171 = {1{`RANDOM}};
  if4_ras_top_ptr = _RAND_171[2:0];
  _RAND_172 = {2{`RANDOM}};
  if4_ras_io_deq_bits_REG_target = _RAND_172[38:0];
  _RAND_173 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_lui = _RAND_173[0:0];
  _RAND_174 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_auipc = _RAND_174[0:0];
  _RAND_175 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_addi = _RAND_175[0:0];
  _RAND_176 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_addiw = _RAND_176[0:0];
  _RAND_177 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_slti = _RAND_177[0:0];
  _RAND_178 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_sltiu = _RAND_178[0:0];
  _RAND_179 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_xori = _RAND_179[0:0];
  _RAND_180 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_ori = _RAND_180[0:0];
  _RAND_181 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_andi = _RAND_181[0:0];
  _RAND_182 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_slli = _RAND_182[0:0];
  _RAND_183 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_slliw = _RAND_183[0:0];
  _RAND_184 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_srli = _RAND_184[0:0];
  _RAND_185 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_srliw = _RAND_185[0:0];
  _RAND_186 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_srai = _RAND_186[0:0];
  _RAND_187 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_sraiw = _RAND_187[0:0];
  _RAND_188 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_add = _RAND_188[0:0];
  _RAND_189 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_addw = _RAND_189[0:0];
  _RAND_190 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_sub = _RAND_190[0:0];
  _RAND_191 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_subw = _RAND_191[0:0];
  _RAND_192 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_sll = _RAND_192[0:0];
  _RAND_193 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_sllw = _RAND_193[0:0];
  _RAND_194 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_slt = _RAND_194[0:0];
  _RAND_195 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_sltu = _RAND_195[0:0];
  _RAND_196 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_xor = _RAND_196[0:0];
  _RAND_197 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_srl = _RAND_197[0:0];
  _RAND_198 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_srlw = _RAND_198[0:0];
  _RAND_199 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_sra = _RAND_199[0:0];
  _RAND_200 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_sraw = _RAND_200[0:0];
  _RAND_201 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_or = _RAND_201[0:0];
  _RAND_202 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_and = _RAND_202[0:0];
  _RAND_203 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_alu_isa_wfi = _RAND_203[0:0];
  _RAND_204 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_bru_isa_jal = _RAND_204[0:0];
  _RAND_205 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_bru_isa_jalr = _RAND_205[0:0];
  _RAND_206 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_bru_isa_beq = _RAND_206[0:0];
  _RAND_207 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_bru_isa_bne = _RAND_207[0:0];
  _RAND_208 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_bru_isa_blt = _RAND_208[0:0];
  _RAND_209 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_bru_isa_bge = _RAND_209[0:0];
  _RAND_210 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_bru_isa_bltu = _RAND_210[0:0];
  _RAND_211 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_bru_isa_bgeu = _RAND_211[0:0];
  _RAND_212 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_lb = _RAND_212[0:0];
  _RAND_213 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_lh = _RAND_213[0:0];
  _RAND_214 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_lw = _RAND_214[0:0];
  _RAND_215 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_ld = _RAND_215[0:0];
  _RAND_216 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_lbu = _RAND_216[0:0];
  _RAND_217 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_lhu = _RAND_217[0:0];
  _RAND_218 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_lwu = _RAND_218[0:0];
  _RAND_219 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_sb = _RAND_219[0:0];
  _RAND_220 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_sh = _RAND_220[0:0];
  _RAND_221 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_sw = _RAND_221[0:0];
  _RAND_222 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_sd = _RAND_222[0:0];
  _RAND_223 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_fence = _RAND_223[0:0];
  _RAND_224 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_fence_i = _RAND_224[0:0];
  _RAND_225 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_sfence_vma = _RAND_225[0:0];
  _RAND_226 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_lr_w = _RAND_226[0:0];
  _RAND_227 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_sc_w = _RAND_227[0:0];
  _RAND_228 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoswap_w = _RAND_228[0:0];
  _RAND_229 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoadd_w = _RAND_229[0:0];
  _RAND_230 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoxor_w = _RAND_230[0:0];
  _RAND_231 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoand_w = _RAND_231[0:0];
  _RAND_232 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoor_w = _RAND_232[0:0];
  _RAND_233 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amomin_w = _RAND_233[0:0];
  _RAND_234 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amomax_w = _RAND_234[0:0];
  _RAND_235 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amominu_w = _RAND_235[0:0];
  _RAND_236 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amomaxu_w = _RAND_236[0:0];
  _RAND_237 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_lr_d = _RAND_237[0:0];
  _RAND_238 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_sc_d = _RAND_238[0:0];
  _RAND_239 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoswap_d = _RAND_239[0:0];
  _RAND_240 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoadd_d = _RAND_240[0:0];
  _RAND_241 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoxor_d = _RAND_241[0:0];
  _RAND_242 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoand_d = _RAND_242[0:0];
  _RAND_243 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amoor_d = _RAND_243[0:0];
  _RAND_244 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amomin_d = _RAND_244[0:0];
  _RAND_245 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amomax_d = _RAND_245[0:0];
  _RAND_246 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amominu_d = _RAND_246[0:0];
  _RAND_247 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_amomaxu_d = _RAND_247[0:0];
  _RAND_248 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_flw = _RAND_248[0:0];
  _RAND_249 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_fsw = _RAND_249[0:0];
  _RAND_250 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_fld = _RAND_250[0:0];
  _RAND_251 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_lsu_isa_fsd = _RAND_251[0:0];
  _RAND_252 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_csr_isa_rw = _RAND_252[0:0];
  _RAND_253 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_csr_isa_rs = _RAND_253[0:0];
  _RAND_254 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_csr_isa_rc = _RAND_254[0:0];
  _RAND_255 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_csr_isa_rwi = _RAND_255[0:0];
  _RAND_256 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_csr_isa_rsi = _RAND_256[0:0];
  _RAND_257 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_csr_isa_rci = _RAND_257[0:0];
  _RAND_258 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_mul = _RAND_258[0:0];
  _RAND_259 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_mulh = _RAND_259[0:0];
  _RAND_260 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_mulhsu = _RAND_260[0:0];
  _RAND_261 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_mulhu = _RAND_261[0:0];
  _RAND_262 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_div = _RAND_262[0:0];
  _RAND_263 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_divu = _RAND_263[0:0];
  _RAND_264 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_rem = _RAND_264[0:0];
  _RAND_265 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_remu = _RAND_265[0:0];
  _RAND_266 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_mulw = _RAND_266[0:0];
  _RAND_267 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_divw = _RAND_267[0:0];
  _RAND_268 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_divuw = _RAND_268[0:0];
  _RAND_269 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_remw = _RAND_269[0:0];
  _RAND_270 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_mul_isa_remuw = _RAND_270[0:0];
  _RAND_271 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_ecall = _RAND_271[0:0];
  _RAND_272 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_ebreak = _RAND_272[0:0];
  _RAND_273 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_mret = _RAND_273[0:0];
  _RAND_274 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_uret = _RAND_274[0:0];
  _RAND_275 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_sret = _RAND_275[0:0];
  _RAND_276 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_dret = _RAND_276[0:0];
  _RAND_277 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hfence_vvma = _RAND_277[0:0];
  _RAND_278 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hfence_gvma = _RAND_278[0:0];
  _RAND_279 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlv_b = _RAND_279[0:0];
  _RAND_280 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlv_bu = _RAND_280[0:0];
  _RAND_281 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlv_h = _RAND_281[0:0];
  _RAND_282 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlv_hu = _RAND_282[0:0];
  _RAND_283 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlvx_hu = _RAND_283[0:0];
  _RAND_284 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlv_w = _RAND_284[0:0];
  _RAND_285 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlvx_wu = _RAND_285[0:0];
  _RAND_286 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hsv_b = _RAND_286[0:0];
  _RAND_287 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hsv_h = _RAND_287[0:0];
  _RAND_288 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hsv_w = _RAND_288[0:0];
  _RAND_289 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlv_wu = _RAND_289[0:0];
  _RAND_290 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hlv_d = _RAND_290[0:0];
  _RAND_291 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_hsv_d = _RAND_291[0:0];
  _RAND_292 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_is_access_fault = _RAND_292[0:0];
  _RAND_293 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_privil_isa_is_paging_fault = _RAND_293[0:0];
  _RAND_294 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmadd_s = _RAND_294[0:0];
  _RAND_295 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmsub_s = _RAND_295[0:0];
  _RAND_296 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fnmsub_s = _RAND_296[0:0];
  _RAND_297 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fnmadd_s = _RAND_297[0:0];
  _RAND_298 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fadd_s = _RAND_298[0:0];
  _RAND_299 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsub_s = _RAND_299[0:0];
  _RAND_300 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmul_s = _RAND_300[0:0];
  _RAND_301 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fdiv_s = _RAND_301[0:0];
  _RAND_302 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsqrt_s = _RAND_302[0:0];
  _RAND_303 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsgnj_s = _RAND_303[0:0];
  _RAND_304 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsgnjn_s = _RAND_304[0:0];
  _RAND_305 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsgnjx_s = _RAND_305[0:0];
  _RAND_306 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmin_s = _RAND_306[0:0];
  _RAND_307 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmax_s = _RAND_307[0:0];
  _RAND_308 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_w_s = _RAND_308[0:0];
  _RAND_309 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_s = _RAND_309[0:0];
  _RAND_310 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmv_x_w = _RAND_310[0:0];
  _RAND_311 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_feq_s = _RAND_311[0:0];
  _RAND_312 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_flt_s = _RAND_312[0:0];
  _RAND_313 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fle_s = _RAND_313[0:0];
  _RAND_314 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fclass_s = _RAND_314[0:0];
  _RAND_315 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_w = _RAND_315[0:0];
  _RAND_316 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_wu = _RAND_316[0:0];
  _RAND_317 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmv_w_x = _RAND_317[0:0];
  _RAND_318 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_l_s = _RAND_318[0:0];
  _RAND_319 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_s = _RAND_319[0:0];
  _RAND_320 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_l = _RAND_320[0:0];
  _RAND_321 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_lu = _RAND_321[0:0];
  _RAND_322 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmadd_d = _RAND_322[0:0];
  _RAND_323 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmsub_d = _RAND_323[0:0];
  _RAND_324 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fnmsub_d = _RAND_324[0:0];
  _RAND_325 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fnmadd_d = _RAND_325[0:0];
  _RAND_326 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fadd_d = _RAND_326[0:0];
  _RAND_327 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsub_d = _RAND_327[0:0];
  _RAND_328 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmul_d = _RAND_328[0:0];
  _RAND_329 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fdiv_d = _RAND_329[0:0];
  _RAND_330 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsqrt_d = _RAND_330[0:0];
  _RAND_331 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsgnj_d = _RAND_331[0:0];
  _RAND_332 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsgnjn_d = _RAND_332[0:0];
  _RAND_333 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fsgnjx_d = _RAND_333[0:0];
  _RAND_334 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmin_d = _RAND_334[0:0];
  _RAND_335 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmax_d = _RAND_335[0:0];
  _RAND_336 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_s_d = _RAND_336[0:0];
  _RAND_337 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_s = _RAND_337[0:0];
  _RAND_338 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_feq_d = _RAND_338[0:0];
  _RAND_339 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_flt_d = _RAND_339[0:0];
  _RAND_340 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fle_d = _RAND_340[0:0];
  _RAND_341 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fclass_d = _RAND_341[0:0];
  _RAND_342 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_w_d = _RAND_342[0:0];
  _RAND_343 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_wu_d = _RAND_343[0:0];
  _RAND_344 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_w = _RAND_344[0:0];
  _RAND_345 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_wu = _RAND_345[0:0];
  _RAND_346 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_l_d = _RAND_346[0:0];
  _RAND_347 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_lu_d = _RAND_347[0:0];
  _RAND_348 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmv_x_d = _RAND_348[0:0];
  _RAND_349 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_l = _RAND_349[0:0];
  _RAND_350 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcvt_d_lu = _RAND_350[0:0];
  _RAND_351 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fmv_d_x = _RAND_351[0:0];
  _RAND_352 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcsr_rw = _RAND_352[0:0];
  _RAND_353 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcsr_rs = _RAND_353[0:0];
  _RAND_354 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcsr_rc = _RAND_354[0:0];
  _RAND_355 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcsr_rwi = _RAND_355[0:0];
  _RAND_356 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcsr_rsi = _RAND_356[0:0];
  _RAND_357 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_fpu_isa_fcsr_rci = _RAND_357[0:0];
  _RAND_358 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_param_is_rvc = _RAND_358[0:0];
  _RAND_359 = {2{`RANDOM}};
  if4_instr_fifo_buf_0_param_pc = _RAND_359[38:0];
  _RAND_360 = {2{`RANDOM}};
  if4_instr_fifo_buf_0_param_imm = _RAND_360[63:0];
  _RAND_361 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_param_raw_rs1 = _RAND_361[4:0];
  _RAND_362 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_param_raw_rs2 = _RAND_362[4:0];
  _RAND_363 = {1{`RANDOM}};
  if4_instr_fifo_buf_0_param_raw_rd0 = _RAND_363[4:0];
  _RAND_364 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_lui = _RAND_364[0:0];
  _RAND_365 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_auipc = _RAND_365[0:0];
  _RAND_366 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_addi = _RAND_366[0:0];
  _RAND_367 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_addiw = _RAND_367[0:0];
  _RAND_368 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_slti = _RAND_368[0:0];
  _RAND_369 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_sltiu = _RAND_369[0:0];
  _RAND_370 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_xori = _RAND_370[0:0];
  _RAND_371 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_ori = _RAND_371[0:0];
  _RAND_372 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_andi = _RAND_372[0:0];
  _RAND_373 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_slli = _RAND_373[0:0];
  _RAND_374 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_slliw = _RAND_374[0:0];
  _RAND_375 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_srli = _RAND_375[0:0];
  _RAND_376 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_srliw = _RAND_376[0:0];
  _RAND_377 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_srai = _RAND_377[0:0];
  _RAND_378 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_sraiw = _RAND_378[0:0];
  _RAND_379 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_add = _RAND_379[0:0];
  _RAND_380 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_addw = _RAND_380[0:0];
  _RAND_381 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_sub = _RAND_381[0:0];
  _RAND_382 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_subw = _RAND_382[0:0];
  _RAND_383 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_sll = _RAND_383[0:0];
  _RAND_384 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_sllw = _RAND_384[0:0];
  _RAND_385 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_slt = _RAND_385[0:0];
  _RAND_386 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_sltu = _RAND_386[0:0];
  _RAND_387 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_xor = _RAND_387[0:0];
  _RAND_388 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_srl = _RAND_388[0:0];
  _RAND_389 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_srlw = _RAND_389[0:0];
  _RAND_390 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_sra = _RAND_390[0:0];
  _RAND_391 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_sraw = _RAND_391[0:0];
  _RAND_392 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_or = _RAND_392[0:0];
  _RAND_393 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_and = _RAND_393[0:0];
  _RAND_394 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_alu_isa_wfi = _RAND_394[0:0];
  _RAND_395 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_bru_isa_jal = _RAND_395[0:0];
  _RAND_396 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_bru_isa_jalr = _RAND_396[0:0];
  _RAND_397 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_bru_isa_beq = _RAND_397[0:0];
  _RAND_398 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_bru_isa_bne = _RAND_398[0:0];
  _RAND_399 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_bru_isa_blt = _RAND_399[0:0];
  _RAND_400 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_bru_isa_bge = _RAND_400[0:0];
  _RAND_401 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_bru_isa_bltu = _RAND_401[0:0];
  _RAND_402 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_bru_isa_bgeu = _RAND_402[0:0];
  _RAND_403 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_lb = _RAND_403[0:0];
  _RAND_404 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_lh = _RAND_404[0:0];
  _RAND_405 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_lw = _RAND_405[0:0];
  _RAND_406 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_ld = _RAND_406[0:0];
  _RAND_407 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_lbu = _RAND_407[0:0];
  _RAND_408 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_lhu = _RAND_408[0:0];
  _RAND_409 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_lwu = _RAND_409[0:0];
  _RAND_410 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_sb = _RAND_410[0:0];
  _RAND_411 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_sh = _RAND_411[0:0];
  _RAND_412 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_sw = _RAND_412[0:0];
  _RAND_413 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_sd = _RAND_413[0:0];
  _RAND_414 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_fence = _RAND_414[0:0];
  _RAND_415 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_fence_i = _RAND_415[0:0];
  _RAND_416 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_sfence_vma = _RAND_416[0:0];
  _RAND_417 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_lr_w = _RAND_417[0:0];
  _RAND_418 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_sc_w = _RAND_418[0:0];
  _RAND_419 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoswap_w = _RAND_419[0:0];
  _RAND_420 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoadd_w = _RAND_420[0:0];
  _RAND_421 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoxor_w = _RAND_421[0:0];
  _RAND_422 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoand_w = _RAND_422[0:0];
  _RAND_423 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoor_w = _RAND_423[0:0];
  _RAND_424 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amomin_w = _RAND_424[0:0];
  _RAND_425 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amomax_w = _RAND_425[0:0];
  _RAND_426 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amominu_w = _RAND_426[0:0];
  _RAND_427 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amomaxu_w = _RAND_427[0:0];
  _RAND_428 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_lr_d = _RAND_428[0:0];
  _RAND_429 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_sc_d = _RAND_429[0:0];
  _RAND_430 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoswap_d = _RAND_430[0:0];
  _RAND_431 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoadd_d = _RAND_431[0:0];
  _RAND_432 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoxor_d = _RAND_432[0:0];
  _RAND_433 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoand_d = _RAND_433[0:0];
  _RAND_434 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amoor_d = _RAND_434[0:0];
  _RAND_435 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amomin_d = _RAND_435[0:0];
  _RAND_436 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amomax_d = _RAND_436[0:0];
  _RAND_437 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amominu_d = _RAND_437[0:0];
  _RAND_438 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_amomaxu_d = _RAND_438[0:0];
  _RAND_439 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_flw = _RAND_439[0:0];
  _RAND_440 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_fsw = _RAND_440[0:0];
  _RAND_441 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_fld = _RAND_441[0:0];
  _RAND_442 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_lsu_isa_fsd = _RAND_442[0:0];
  _RAND_443 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_csr_isa_rw = _RAND_443[0:0];
  _RAND_444 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_csr_isa_rs = _RAND_444[0:0];
  _RAND_445 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_csr_isa_rc = _RAND_445[0:0];
  _RAND_446 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_csr_isa_rwi = _RAND_446[0:0];
  _RAND_447 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_csr_isa_rsi = _RAND_447[0:0];
  _RAND_448 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_csr_isa_rci = _RAND_448[0:0];
  _RAND_449 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_mul = _RAND_449[0:0];
  _RAND_450 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_mulh = _RAND_450[0:0];
  _RAND_451 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_mulhsu = _RAND_451[0:0];
  _RAND_452 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_mulhu = _RAND_452[0:0];
  _RAND_453 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_div = _RAND_453[0:0];
  _RAND_454 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_divu = _RAND_454[0:0];
  _RAND_455 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_rem = _RAND_455[0:0];
  _RAND_456 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_remu = _RAND_456[0:0];
  _RAND_457 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_mulw = _RAND_457[0:0];
  _RAND_458 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_divw = _RAND_458[0:0];
  _RAND_459 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_divuw = _RAND_459[0:0];
  _RAND_460 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_remw = _RAND_460[0:0];
  _RAND_461 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_mul_isa_remuw = _RAND_461[0:0];
  _RAND_462 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_ecall = _RAND_462[0:0];
  _RAND_463 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_ebreak = _RAND_463[0:0];
  _RAND_464 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_mret = _RAND_464[0:0];
  _RAND_465 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_uret = _RAND_465[0:0];
  _RAND_466 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_sret = _RAND_466[0:0];
  _RAND_467 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_dret = _RAND_467[0:0];
  _RAND_468 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hfence_vvma = _RAND_468[0:0];
  _RAND_469 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hfence_gvma = _RAND_469[0:0];
  _RAND_470 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlv_b = _RAND_470[0:0];
  _RAND_471 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlv_bu = _RAND_471[0:0];
  _RAND_472 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlv_h = _RAND_472[0:0];
  _RAND_473 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlv_hu = _RAND_473[0:0];
  _RAND_474 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlvx_hu = _RAND_474[0:0];
  _RAND_475 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlv_w = _RAND_475[0:0];
  _RAND_476 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlvx_wu = _RAND_476[0:0];
  _RAND_477 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hsv_b = _RAND_477[0:0];
  _RAND_478 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hsv_h = _RAND_478[0:0];
  _RAND_479 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hsv_w = _RAND_479[0:0];
  _RAND_480 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlv_wu = _RAND_480[0:0];
  _RAND_481 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hlv_d = _RAND_481[0:0];
  _RAND_482 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_hsv_d = _RAND_482[0:0];
  _RAND_483 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_is_access_fault = _RAND_483[0:0];
  _RAND_484 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_privil_isa_is_paging_fault = _RAND_484[0:0];
  _RAND_485 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmadd_s = _RAND_485[0:0];
  _RAND_486 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmsub_s = _RAND_486[0:0];
  _RAND_487 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fnmsub_s = _RAND_487[0:0];
  _RAND_488 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fnmadd_s = _RAND_488[0:0];
  _RAND_489 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fadd_s = _RAND_489[0:0];
  _RAND_490 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsub_s = _RAND_490[0:0];
  _RAND_491 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmul_s = _RAND_491[0:0];
  _RAND_492 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fdiv_s = _RAND_492[0:0];
  _RAND_493 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsqrt_s = _RAND_493[0:0];
  _RAND_494 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsgnj_s = _RAND_494[0:0];
  _RAND_495 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsgnjn_s = _RAND_495[0:0];
  _RAND_496 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsgnjx_s = _RAND_496[0:0];
  _RAND_497 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmin_s = _RAND_497[0:0];
  _RAND_498 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmax_s = _RAND_498[0:0];
  _RAND_499 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_w_s = _RAND_499[0:0];
  _RAND_500 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_s = _RAND_500[0:0];
  _RAND_501 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmv_x_w = _RAND_501[0:0];
  _RAND_502 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_feq_s = _RAND_502[0:0];
  _RAND_503 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_flt_s = _RAND_503[0:0];
  _RAND_504 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fle_s = _RAND_504[0:0];
  _RAND_505 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fclass_s = _RAND_505[0:0];
  _RAND_506 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_w = _RAND_506[0:0];
  _RAND_507 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_wu = _RAND_507[0:0];
  _RAND_508 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmv_w_x = _RAND_508[0:0];
  _RAND_509 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_l_s = _RAND_509[0:0];
  _RAND_510 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_s = _RAND_510[0:0];
  _RAND_511 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_l = _RAND_511[0:0];
  _RAND_512 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_lu = _RAND_512[0:0];
  _RAND_513 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmadd_d = _RAND_513[0:0];
  _RAND_514 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmsub_d = _RAND_514[0:0];
  _RAND_515 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fnmsub_d = _RAND_515[0:0];
  _RAND_516 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fnmadd_d = _RAND_516[0:0];
  _RAND_517 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fadd_d = _RAND_517[0:0];
  _RAND_518 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsub_d = _RAND_518[0:0];
  _RAND_519 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmul_d = _RAND_519[0:0];
  _RAND_520 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fdiv_d = _RAND_520[0:0];
  _RAND_521 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsqrt_d = _RAND_521[0:0];
  _RAND_522 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsgnj_d = _RAND_522[0:0];
  _RAND_523 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsgnjn_d = _RAND_523[0:0];
  _RAND_524 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fsgnjx_d = _RAND_524[0:0];
  _RAND_525 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmin_d = _RAND_525[0:0];
  _RAND_526 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmax_d = _RAND_526[0:0];
  _RAND_527 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_s_d = _RAND_527[0:0];
  _RAND_528 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_s = _RAND_528[0:0];
  _RAND_529 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_feq_d = _RAND_529[0:0];
  _RAND_530 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_flt_d = _RAND_530[0:0];
  _RAND_531 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fle_d = _RAND_531[0:0];
  _RAND_532 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fclass_d = _RAND_532[0:0];
  _RAND_533 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_w_d = _RAND_533[0:0];
  _RAND_534 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_wu_d = _RAND_534[0:0];
  _RAND_535 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_w = _RAND_535[0:0];
  _RAND_536 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_wu = _RAND_536[0:0];
  _RAND_537 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_l_d = _RAND_537[0:0];
  _RAND_538 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_lu_d = _RAND_538[0:0];
  _RAND_539 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmv_x_d = _RAND_539[0:0];
  _RAND_540 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_l = _RAND_540[0:0];
  _RAND_541 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcvt_d_lu = _RAND_541[0:0];
  _RAND_542 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fmv_d_x = _RAND_542[0:0];
  _RAND_543 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcsr_rw = _RAND_543[0:0];
  _RAND_544 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcsr_rs = _RAND_544[0:0];
  _RAND_545 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcsr_rc = _RAND_545[0:0];
  _RAND_546 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcsr_rwi = _RAND_546[0:0];
  _RAND_547 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcsr_rsi = _RAND_547[0:0];
  _RAND_548 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_fpu_isa_fcsr_rci = _RAND_548[0:0];
  _RAND_549 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_param_is_rvc = _RAND_549[0:0];
  _RAND_550 = {2{`RANDOM}};
  if4_instr_fifo_buf_1_param_pc = _RAND_550[38:0];
  _RAND_551 = {2{`RANDOM}};
  if4_instr_fifo_buf_1_param_imm = _RAND_551[63:0];
  _RAND_552 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_param_raw_rs1 = _RAND_552[4:0];
  _RAND_553 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_param_raw_rs2 = _RAND_553[4:0];
  _RAND_554 = {1{`RANDOM}};
  if4_instr_fifo_buf_1_param_raw_rd0 = _RAND_554[4:0];
  _RAND_555 = {1{`RANDOM}};
  if4_instr_fifo_buf_valid_0 = _RAND_555[0:0];
  _RAND_556 = {1{`RANDOM}};
  if4_instr_fifo_buf_valid_1 = _RAND_556[0:0];
  _RAND_557 = {1{`RANDOM}};
  if4_instr_fifo_rd_ptr = _RAND_557[0:0];
  _RAND_558 = {1{`RANDOM}};
  if4_instr_fifo_wr_ptr = _RAND_558[0:0];
  _RAND_559 = {2{`RANDOM}};
  if4_bftq_buf_0_pc = _RAND_559[38:0];
  _RAND_560 = {1{`RANDOM}};
  if4_bftq_buf_0_bimResp_bim_p = _RAND_560[0:0];
  _RAND_561 = {1{`RANDOM}};
  if4_bftq_buf_0_bimResp_bim_h = _RAND_561[0:0];
  _RAND_562 = {1{`RANDOM}};
  if4_bftq_buf_0_isPredictTaken = _RAND_562[0:0];
  _RAND_563 = {2{`RANDOM}};
  if4_bftq_buf_1_pc = _RAND_563[38:0];
  _RAND_564 = {1{`RANDOM}};
  if4_bftq_buf_1_bimResp_bim_p = _RAND_564[0:0];
  _RAND_565 = {1{`RANDOM}};
  if4_bftq_buf_1_bimResp_bim_h = _RAND_565[0:0];
  _RAND_566 = {1{`RANDOM}};
  if4_bftq_buf_1_isPredictTaken = _RAND_566[0:0];
  _RAND_567 = {1{`RANDOM}};
  if4_bftq_buf_valid_0 = _RAND_567[0:0];
  _RAND_568 = {1{`RANDOM}};
  if4_bftq_buf_valid_1 = _RAND_568[0:0];
  _RAND_569 = {1{`RANDOM}};
  if4_bftq_rd_ptr = _RAND_569[0:0];
  _RAND_570 = {1{`RANDOM}};
  if4_bftq_wr_ptr = _RAND_570[0:0];
  _RAND_571 = {2{`RANDOM}};
  if4_jftq_buf_0_pc = _RAND_571[38:0];
  _RAND_572 = {2{`RANDOM}};
  if4_jftq_buf_0_btbResp_target = _RAND_572[38:0];
  _RAND_573 = {2{`RANDOM}};
  if4_jftq_buf_0_rasResp_target = _RAND_573[38:0];
  _RAND_574 = {1{`RANDOM}};
  if4_jftq_buf_0_isRas = _RAND_574[0:0];
  _RAND_575 = {2{`RANDOM}};
  if4_jftq_buf_1_pc = _RAND_575[38:0];
  _RAND_576 = {2{`RANDOM}};
  if4_jftq_buf_1_btbResp_target = _RAND_576[38:0];
  _RAND_577 = {2{`RANDOM}};
  if4_jftq_buf_1_rasResp_target = _RAND_577[38:0];
  _RAND_578 = {1{`RANDOM}};
  if4_jftq_buf_1_isRas = _RAND_578[0:0];
  _RAND_579 = {1{`RANDOM}};
  if4_jftq_buf_valid_0 = _RAND_579[0:0];
  _RAND_580 = {1{`RANDOM}};
  if4_jftq_buf_valid_1 = _RAND_580[0:0];
  _RAND_581 = {1{`RANDOM}};
  if4_jftq_rd_ptr = _RAND_581[0:0];
  _RAND_582 = {1{`RANDOM}};
  if4_jftq_wr_ptr = _RAND_582[0:0];
  _RAND_583 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_lui = _RAND_583[0:0];
  _RAND_584 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_auipc = _RAND_584[0:0];
  _RAND_585 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_addi = _RAND_585[0:0];
  _RAND_586 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_addiw = _RAND_586[0:0];
  _RAND_587 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_slti = _RAND_587[0:0];
  _RAND_588 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_sltiu = _RAND_588[0:0];
  _RAND_589 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_xori = _RAND_589[0:0];
  _RAND_590 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_ori = _RAND_590[0:0];
  _RAND_591 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_andi = _RAND_591[0:0];
  _RAND_592 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_slli = _RAND_592[0:0];
  _RAND_593 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_slliw = _RAND_593[0:0];
  _RAND_594 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_srli = _RAND_594[0:0];
  _RAND_595 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_srliw = _RAND_595[0:0];
  _RAND_596 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_srai = _RAND_596[0:0];
  _RAND_597 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_sraiw = _RAND_597[0:0];
  _RAND_598 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_add = _RAND_598[0:0];
  _RAND_599 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_addw = _RAND_599[0:0];
  _RAND_600 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_sub = _RAND_600[0:0];
  _RAND_601 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_subw = _RAND_601[0:0];
  _RAND_602 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_sll = _RAND_602[0:0];
  _RAND_603 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_sllw = _RAND_603[0:0];
  _RAND_604 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_slt = _RAND_604[0:0];
  _RAND_605 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_sltu = _RAND_605[0:0];
  _RAND_606 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_xor = _RAND_606[0:0];
  _RAND_607 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_srl = _RAND_607[0:0];
  _RAND_608 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_srlw = _RAND_608[0:0];
  _RAND_609 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_sra = _RAND_609[0:0];
  _RAND_610 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_sraw = _RAND_610[0:0];
  _RAND_611 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_or = _RAND_611[0:0];
  _RAND_612 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_and = _RAND_612[0:0];
  _RAND_613 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_alu_isa_wfi = _RAND_613[0:0];
  _RAND_614 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_bru_isa_jal = _RAND_614[0:0];
  _RAND_615 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_bru_isa_jalr = _RAND_615[0:0];
  _RAND_616 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_bru_isa_beq = _RAND_616[0:0];
  _RAND_617 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_bru_isa_bne = _RAND_617[0:0];
  _RAND_618 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_bru_isa_blt = _RAND_618[0:0];
  _RAND_619 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_bru_isa_bge = _RAND_619[0:0];
  _RAND_620 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_bru_isa_bltu = _RAND_620[0:0];
  _RAND_621 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_bru_isa_bgeu = _RAND_621[0:0];
  _RAND_622 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_lb = _RAND_622[0:0];
  _RAND_623 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_lh = _RAND_623[0:0];
  _RAND_624 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_lw = _RAND_624[0:0];
  _RAND_625 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_ld = _RAND_625[0:0];
  _RAND_626 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_lbu = _RAND_626[0:0];
  _RAND_627 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_lhu = _RAND_627[0:0];
  _RAND_628 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_lwu = _RAND_628[0:0];
  _RAND_629 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_sb = _RAND_629[0:0];
  _RAND_630 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_sh = _RAND_630[0:0];
  _RAND_631 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_sw = _RAND_631[0:0];
  _RAND_632 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_sd = _RAND_632[0:0];
  _RAND_633 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_fence = _RAND_633[0:0];
  _RAND_634 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_fence_i = _RAND_634[0:0];
  _RAND_635 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_sfence_vma = _RAND_635[0:0];
  _RAND_636 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_w = _RAND_636[0:0];
  _RAND_637 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_w = _RAND_637[0:0];
  _RAND_638 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_w = _RAND_638[0:0];
  _RAND_639 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_w = _RAND_639[0:0];
  _RAND_640 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_w = _RAND_640[0:0];
  _RAND_641 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_w = _RAND_641[0:0];
  _RAND_642 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_w = _RAND_642[0:0];
  _RAND_643 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_w = _RAND_643[0:0];
  _RAND_644 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_w = _RAND_644[0:0];
  _RAND_645 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_w = _RAND_645[0:0];
  _RAND_646 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_w = _RAND_646[0:0];
  _RAND_647 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_lr_d = _RAND_647[0:0];
  _RAND_648 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_sc_d = _RAND_648[0:0];
  _RAND_649 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoswap_d = _RAND_649[0:0];
  _RAND_650 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoadd_d = _RAND_650[0:0];
  _RAND_651 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoxor_d = _RAND_651[0:0];
  _RAND_652 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoand_d = _RAND_652[0:0];
  _RAND_653 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amoor_d = _RAND_653[0:0];
  _RAND_654 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomin_d = _RAND_654[0:0];
  _RAND_655 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomax_d = _RAND_655[0:0];
  _RAND_656 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amominu_d = _RAND_656[0:0];
  _RAND_657 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_amomaxu_d = _RAND_657[0:0];
  _RAND_658 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_flw = _RAND_658[0:0];
  _RAND_659 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_fsw = _RAND_659[0:0];
  _RAND_660 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_fld = _RAND_660[0:0];
  _RAND_661 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_lsu_isa_fsd = _RAND_661[0:0];
  _RAND_662 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_csr_isa_rw = _RAND_662[0:0];
  _RAND_663 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_csr_isa_rs = _RAND_663[0:0];
  _RAND_664 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_csr_isa_rc = _RAND_664[0:0];
  _RAND_665 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_csr_isa_rwi = _RAND_665[0:0];
  _RAND_666 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_csr_isa_rsi = _RAND_666[0:0];
  _RAND_667 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_csr_isa_rci = _RAND_667[0:0];
  _RAND_668 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_mul = _RAND_668[0:0];
  _RAND_669 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_mulh = _RAND_669[0:0];
  _RAND_670 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_mulhsu = _RAND_670[0:0];
  _RAND_671 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_mulhu = _RAND_671[0:0];
  _RAND_672 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_div = _RAND_672[0:0];
  _RAND_673 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_divu = _RAND_673[0:0];
  _RAND_674 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_rem = _RAND_674[0:0];
  _RAND_675 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_remu = _RAND_675[0:0];
  _RAND_676 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_mulw = _RAND_676[0:0];
  _RAND_677 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_divw = _RAND_677[0:0];
  _RAND_678 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_divuw = _RAND_678[0:0];
  _RAND_679 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_remw = _RAND_679[0:0];
  _RAND_680 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_mul_isa_remuw = _RAND_680[0:0];
  _RAND_681 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_s = _RAND_681[0:0];
  _RAND_682 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_s = _RAND_682[0:0];
  _RAND_683 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_s = _RAND_683[0:0];
  _RAND_684 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_s = _RAND_684[0:0];
  _RAND_685 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_s = _RAND_685[0:0];
  _RAND_686 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_s = _RAND_686[0:0];
  _RAND_687 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_s = _RAND_687[0:0];
  _RAND_688 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_s = _RAND_688[0:0];
  _RAND_689 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_s = _RAND_689[0:0];
  _RAND_690 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_s = _RAND_690[0:0];
  _RAND_691 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_s = _RAND_691[0:0];
  _RAND_692 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_s = _RAND_692[0:0];
  _RAND_693 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_s = _RAND_693[0:0];
  _RAND_694 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_s = _RAND_694[0:0];
  _RAND_695 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_s = _RAND_695[0:0];
  _RAND_696 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_s = _RAND_696[0:0];
  _RAND_697 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_w = _RAND_697[0:0];
  _RAND_698 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_s = _RAND_698[0:0];
  _RAND_699 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_s = _RAND_699[0:0];
  _RAND_700 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_s = _RAND_700[0:0];
  _RAND_701 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_s = _RAND_701[0:0];
  _RAND_702 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_s = _RAND_702[0:0];
  _RAND_703 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_s = _RAND_703[0:0];
  _RAND_704 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmadd_d = _RAND_704[0:0];
  _RAND_705 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmsub_d = _RAND_705[0:0];
  _RAND_706 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmsub_d = _RAND_706[0:0];
  _RAND_707 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fnmadd_d = _RAND_707[0:0];
  _RAND_708 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fadd_d = _RAND_708[0:0];
  _RAND_709 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsub_d = _RAND_709[0:0];
  _RAND_710 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmul_d = _RAND_710[0:0];
  _RAND_711 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fdiv_d = _RAND_711[0:0];
  _RAND_712 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsqrt_d = _RAND_712[0:0];
  _RAND_713 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnj_d = _RAND_713[0:0];
  _RAND_714 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjn_d = _RAND_714[0:0];
  _RAND_715 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fsgnjx_d = _RAND_715[0:0];
  _RAND_716 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmin_d = _RAND_716[0:0];
  _RAND_717 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmax_d = _RAND_717[0:0];
  _RAND_718 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_s_d = _RAND_718[0:0];
  _RAND_719 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_d_s = _RAND_719[0:0];
  _RAND_720 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_feq_d = _RAND_720[0:0];
  _RAND_721 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_flt_d = _RAND_721[0:0];
  _RAND_722 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fle_d = _RAND_722[0:0];
  _RAND_723 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fclass_d = _RAND_723[0:0];
  _RAND_724 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_w_d = _RAND_724[0:0];
  _RAND_725 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_wu_d = _RAND_725[0:0];
  _RAND_726 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_l_d = _RAND_726[0:0];
  _RAND_727 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fcvt_lu_d = _RAND_727[0:0];
  _RAND_728 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_fpu_isa_fmv_x_d = _RAND_728[0:0];
  _RAND_729 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_param_is_rvc = _RAND_729[0:0];
  _RAND_730 = {2{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_param_pc = _RAND_730[38:0];
  _RAND_731 = {2{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_param_imm = _RAND_731[63:0];
  _RAND_732 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_param_raw_rs1 = _RAND_732[4:0];
  _RAND_733 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_phy_rs1 = _RAND_733[5:0];
  _RAND_734 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_phy_rs2 = _RAND_734[5:0];
  _RAND_735 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_phy_rs3 = _RAND_735[5:0];
  _RAND_736 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_0_phy_rd0 = _RAND_736[5:0];
  _RAND_737 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_lui = _RAND_737[0:0];
  _RAND_738 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_auipc = _RAND_738[0:0];
  _RAND_739 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_addi = _RAND_739[0:0];
  _RAND_740 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_addiw = _RAND_740[0:0];
  _RAND_741 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_slti = _RAND_741[0:0];
  _RAND_742 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_sltiu = _RAND_742[0:0];
  _RAND_743 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_xori = _RAND_743[0:0];
  _RAND_744 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_ori = _RAND_744[0:0];
  _RAND_745 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_andi = _RAND_745[0:0];
  _RAND_746 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_slli = _RAND_746[0:0];
  _RAND_747 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_slliw = _RAND_747[0:0];
  _RAND_748 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_srli = _RAND_748[0:0];
  _RAND_749 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_srliw = _RAND_749[0:0];
  _RAND_750 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_srai = _RAND_750[0:0];
  _RAND_751 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_sraiw = _RAND_751[0:0];
  _RAND_752 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_add = _RAND_752[0:0];
  _RAND_753 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_addw = _RAND_753[0:0];
  _RAND_754 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_sub = _RAND_754[0:0];
  _RAND_755 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_subw = _RAND_755[0:0];
  _RAND_756 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_sll = _RAND_756[0:0];
  _RAND_757 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_sllw = _RAND_757[0:0];
  _RAND_758 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_slt = _RAND_758[0:0];
  _RAND_759 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_sltu = _RAND_759[0:0];
  _RAND_760 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_xor = _RAND_760[0:0];
  _RAND_761 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_srl = _RAND_761[0:0];
  _RAND_762 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_srlw = _RAND_762[0:0];
  _RAND_763 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_sra = _RAND_763[0:0];
  _RAND_764 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_sraw = _RAND_764[0:0];
  _RAND_765 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_or = _RAND_765[0:0];
  _RAND_766 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_and = _RAND_766[0:0];
  _RAND_767 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_alu_isa_wfi = _RAND_767[0:0];
  _RAND_768 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_bru_isa_jal = _RAND_768[0:0];
  _RAND_769 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_bru_isa_jalr = _RAND_769[0:0];
  _RAND_770 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_bru_isa_beq = _RAND_770[0:0];
  _RAND_771 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_bru_isa_bne = _RAND_771[0:0];
  _RAND_772 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_bru_isa_blt = _RAND_772[0:0];
  _RAND_773 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_bru_isa_bge = _RAND_773[0:0];
  _RAND_774 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_bru_isa_bltu = _RAND_774[0:0];
  _RAND_775 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_bru_isa_bgeu = _RAND_775[0:0];
  _RAND_776 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_lb = _RAND_776[0:0];
  _RAND_777 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_lh = _RAND_777[0:0];
  _RAND_778 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_lw = _RAND_778[0:0];
  _RAND_779 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_ld = _RAND_779[0:0];
  _RAND_780 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_lbu = _RAND_780[0:0];
  _RAND_781 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_lhu = _RAND_781[0:0];
  _RAND_782 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_lwu = _RAND_782[0:0];
  _RAND_783 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_sb = _RAND_783[0:0];
  _RAND_784 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_sh = _RAND_784[0:0];
  _RAND_785 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_sw = _RAND_785[0:0];
  _RAND_786 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_sd = _RAND_786[0:0];
  _RAND_787 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_fence = _RAND_787[0:0];
  _RAND_788 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_fence_i = _RAND_788[0:0];
  _RAND_789 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_sfence_vma = _RAND_789[0:0];
  _RAND_790 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_w = _RAND_790[0:0];
  _RAND_791 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_w = _RAND_791[0:0];
  _RAND_792 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_w = _RAND_792[0:0];
  _RAND_793 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_w = _RAND_793[0:0];
  _RAND_794 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_w = _RAND_794[0:0];
  _RAND_795 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_w = _RAND_795[0:0];
  _RAND_796 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_w = _RAND_796[0:0];
  _RAND_797 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_w = _RAND_797[0:0];
  _RAND_798 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_w = _RAND_798[0:0];
  _RAND_799 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_w = _RAND_799[0:0];
  _RAND_800 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_w = _RAND_800[0:0];
  _RAND_801 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_lr_d = _RAND_801[0:0];
  _RAND_802 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_sc_d = _RAND_802[0:0];
  _RAND_803 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoswap_d = _RAND_803[0:0];
  _RAND_804 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoadd_d = _RAND_804[0:0];
  _RAND_805 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoxor_d = _RAND_805[0:0];
  _RAND_806 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoand_d = _RAND_806[0:0];
  _RAND_807 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amoor_d = _RAND_807[0:0];
  _RAND_808 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomin_d = _RAND_808[0:0];
  _RAND_809 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomax_d = _RAND_809[0:0];
  _RAND_810 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amominu_d = _RAND_810[0:0];
  _RAND_811 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_amomaxu_d = _RAND_811[0:0];
  _RAND_812 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_flw = _RAND_812[0:0];
  _RAND_813 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_fsw = _RAND_813[0:0];
  _RAND_814 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_fld = _RAND_814[0:0];
  _RAND_815 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_lsu_isa_fsd = _RAND_815[0:0];
  _RAND_816 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_csr_isa_rw = _RAND_816[0:0];
  _RAND_817 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_csr_isa_rs = _RAND_817[0:0];
  _RAND_818 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_csr_isa_rc = _RAND_818[0:0];
  _RAND_819 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_csr_isa_rwi = _RAND_819[0:0];
  _RAND_820 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_csr_isa_rsi = _RAND_820[0:0];
  _RAND_821 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_csr_isa_rci = _RAND_821[0:0];
  _RAND_822 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_mul = _RAND_822[0:0];
  _RAND_823 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_mulh = _RAND_823[0:0];
  _RAND_824 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_mulhsu = _RAND_824[0:0];
  _RAND_825 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_mulhu = _RAND_825[0:0];
  _RAND_826 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_div = _RAND_826[0:0];
  _RAND_827 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_divu = _RAND_827[0:0];
  _RAND_828 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_rem = _RAND_828[0:0];
  _RAND_829 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_remu = _RAND_829[0:0];
  _RAND_830 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_mulw = _RAND_830[0:0];
  _RAND_831 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_divw = _RAND_831[0:0];
  _RAND_832 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_divuw = _RAND_832[0:0];
  _RAND_833 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_remw = _RAND_833[0:0];
  _RAND_834 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_mul_isa_remuw = _RAND_834[0:0];
  _RAND_835 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_s = _RAND_835[0:0];
  _RAND_836 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_s = _RAND_836[0:0];
  _RAND_837 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_s = _RAND_837[0:0];
  _RAND_838 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_s = _RAND_838[0:0];
  _RAND_839 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_s = _RAND_839[0:0];
  _RAND_840 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_s = _RAND_840[0:0];
  _RAND_841 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_s = _RAND_841[0:0];
  _RAND_842 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_s = _RAND_842[0:0];
  _RAND_843 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_s = _RAND_843[0:0];
  _RAND_844 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_s = _RAND_844[0:0];
  _RAND_845 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_s = _RAND_845[0:0];
  _RAND_846 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_s = _RAND_846[0:0];
  _RAND_847 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_s = _RAND_847[0:0];
  _RAND_848 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_s = _RAND_848[0:0];
  _RAND_849 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_s = _RAND_849[0:0];
  _RAND_850 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_s = _RAND_850[0:0];
  _RAND_851 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_w = _RAND_851[0:0];
  _RAND_852 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_s = _RAND_852[0:0];
  _RAND_853 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_s = _RAND_853[0:0];
  _RAND_854 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_s = _RAND_854[0:0];
  _RAND_855 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_s = _RAND_855[0:0];
  _RAND_856 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_s = _RAND_856[0:0];
  _RAND_857 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_s = _RAND_857[0:0];
  _RAND_858 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmadd_d = _RAND_858[0:0];
  _RAND_859 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmsub_d = _RAND_859[0:0];
  _RAND_860 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmsub_d = _RAND_860[0:0];
  _RAND_861 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fnmadd_d = _RAND_861[0:0];
  _RAND_862 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fadd_d = _RAND_862[0:0];
  _RAND_863 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsub_d = _RAND_863[0:0];
  _RAND_864 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmul_d = _RAND_864[0:0];
  _RAND_865 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fdiv_d = _RAND_865[0:0];
  _RAND_866 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsqrt_d = _RAND_866[0:0];
  _RAND_867 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnj_d = _RAND_867[0:0];
  _RAND_868 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjn_d = _RAND_868[0:0];
  _RAND_869 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fsgnjx_d = _RAND_869[0:0];
  _RAND_870 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmin_d = _RAND_870[0:0];
  _RAND_871 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmax_d = _RAND_871[0:0];
  _RAND_872 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_s_d = _RAND_872[0:0];
  _RAND_873 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_d_s = _RAND_873[0:0];
  _RAND_874 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_feq_d = _RAND_874[0:0];
  _RAND_875 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_flt_d = _RAND_875[0:0];
  _RAND_876 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fle_d = _RAND_876[0:0];
  _RAND_877 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fclass_d = _RAND_877[0:0];
  _RAND_878 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_w_d = _RAND_878[0:0];
  _RAND_879 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_wu_d = _RAND_879[0:0];
  _RAND_880 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_l_d = _RAND_880[0:0];
  _RAND_881 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fcvt_lu_d = _RAND_881[0:0];
  _RAND_882 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_fpu_isa_fmv_x_d = _RAND_882[0:0];
  _RAND_883 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_param_is_rvc = _RAND_883[0:0];
  _RAND_884 = {2{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_param_pc = _RAND_884[38:0];
  _RAND_885 = {2{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_param_imm = _RAND_885[63:0];
  _RAND_886 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_param_raw_rs1 = _RAND_886[4:0];
  _RAND_887 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_phy_rs1 = _RAND_887[5:0];
  _RAND_888 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_phy_rs2 = _RAND_888[5:0];
  _RAND_889 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_phy_rs3 = _RAND_889[5:0];
  _RAND_890 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_1_phy_rd0 = _RAND_890[5:0];
  _RAND_891 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_valid_0 = _RAND_891[0:0];
  _RAND_892 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_buf_valid_1 = _RAND_892[0:0];
  _RAND_893 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_rd_ptr = _RAND_893[0:0];
  _RAND_894 = {1{`RANDOM}};
  rnm_stage_rnRspFifo_wr_ptr = _RAND_894[0:0];
  _RAND_895 = {2{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_pc = _RAND_895[38:0];
  _RAND_896 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_rd0_raw = _RAND_896[4:0];
  _RAND_897 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_rd0_phy = _RAND_897[5:0];
  _RAND_898 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_branch = _RAND_898[0:0];
  _RAND_899 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_jalr = _RAND_899[0:0];
  _RAND_900 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_lu = _RAND_900[0:0];
  _RAND_901 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_su = _RAND_901[0:0];
  _RAND_902 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_amo = _RAND_902[0:0];
  _RAND_903 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_fence_i = _RAND_903[0:0];
  _RAND_904 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_sfence_vma = _RAND_904[0:0];
  _RAND_905 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_wfi = _RAND_905[0:0];
  _RAND_906 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_csr = _RAND_906[0:0];
  _RAND_907 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_fpu = _RAND_907[0:0];
  _RAND_908 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_fcsr = _RAND_908[0:0];
  _RAND_909 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_xcmm = _RAND_909[0:0];
  _RAND_910 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_fcmm = _RAND_910[0:0];
  _RAND_911 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_privil_ecall = _RAND_911[0:0];
  _RAND_912 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_privil_ebreak = _RAND_912[0:0];
  _RAND_913 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_privil_mret = _RAND_913[0:0];
  _RAND_914 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_privil_sret = _RAND_914[0:0];
  _RAND_915 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_privil_dret = _RAND_915[0:0];
  _RAND_916 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_privil_is_access_fault = _RAND_916[0:0];
  _RAND_917 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_privil_is_paging_fault = _RAND_917[0:0];
  _RAND_918 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_0_is_illeage = _RAND_918[0:0];
  _RAND_919 = {2{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_pc = _RAND_919[38:0];
  _RAND_920 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_rd0_raw = _RAND_920[4:0];
  _RAND_921 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_rd0_phy = _RAND_921[5:0];
  _RAND_922 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_branch = _RAND_922[0:0];
  _RAND_923 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_jalr = _RAND_923[0:0];
  _RAND_924 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_lu = _RAND_924[0:0];
  _RAND_925 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_su = _RAND_925[0:0];
  _RAND_926 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_amo = _RAND_926[0:0];
  _RAND_927 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_fence_i = _RAND_927[0:0];
  _RAND_928 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_sfence_vma = _RAND_928[0:0];
  _RAND_929 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_wfi = _RAND_929[0:0];
  _RAND_930 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_csr = _RAND_930[0:0];
  _RAND_931 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_fpu = _RAND_931[0:0];
  _RAND_932 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_fcsr = _RAND_932[0:0];
  _RAND_933 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_xcmm = _RAND_933[0:0];
  _RAND_934 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_fcmm = _RAND_934[0:0];
  _RAND_935 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_privil_ecall = _RAND_935[0:0];
  _RAND_936 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_privil_ebreak = _RAND_936[0:0];
  _RAND_937 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_privil_mret = _RAND_937[0:0];
  _RAND_938 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_privil_sret = _RAND_938[0:0];
  _RAND_939 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_privil_dret = _RAND_939[0:0];
  _RAND_940 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_privil_is_access_fault = _RAND_940[0:0];
  _RAND_941 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_privil_is_paging_fault = _RAND_941[0:0];
  _RAND_942 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_1_is_illeage = _RAND_942[0:0];
  _RAND_943 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_valid_0 = _RAND_943[0:0];
  _RAND_944 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_buf_valid_1 = _RAND_944[0:0];
  _RAND_945 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_rd_ptr = _RAND_945[0:0];
  _RAND_946 = {1{`RANDOM}};
  rnm_stage_reOrder_fifo_i_wr_ptr = _RAND_946[0:0];
  _RAND_960 = {1{`RANDOM}};
  iss_stage_aluIssFifo_0_maybe_full = _RAND_960[0:0];
  _RAND_977 = {1{`RANDOM}};
  iss_stage_mulIssFifo_0_maybe_full = _RAND_977[0:0];
  _RAND_991 = {1{`RANDOM}};
  iss_stage_bruIssFifo_maybe_full = _RAND_991[0:0];
  _RAND_998 = {1{`RANDOM}};
  iss_stage_csrIssFifo_maybe_full = _RAND_998[0:0];
  _RAND_1042 = {1{`RANDOM}};
  iss_stage_lsuIssFifo_maybe_full = _RAND_1042[0:0];
  _RAND_1043 = {1{`RANDOM}};
  iss_stage_bufValid_0 = _RAND_1043[0:0];
  _RAND_1044 = {1{`RANDOM}};
  iss_stage_bufValid_1 = _RAND_1044[0:0];
  _RAND_1045 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_lui = _RAND_1045[0:0];
  _RAND_1046 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_auipc = _RAND_1046[0:0];
  _RAND_1047 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_addi = _RAND_1047[0:0];
  _RAND_1048 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_addiw = _RAND_1048[0:0];
  _RAND_1049 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_slti = _RAND_1049[0:0];
  _RAND_1050 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_sltiu = _RAND_1050[0:0];
  _RAND_1051 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_xori = _RAND_1051[0:0];
  _RAND_1052 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_ori = _RAND_1052[0:0];
  _RAND_1053 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_andi = _RAND_1053[0:0];
  _RAND_1054 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_slli = _RAND_1054[0:0];
  _RAND_1055 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_slliw = _RAND_1055[0:0];
  _RAND_1056 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_srli = _RAND_1056[0:0];
  _RAND_1057 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_srliw = _RAND_1057[0:0];
  _RAND_1058 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_srai = _RAND_1058[0:0];
  _RAND_1059 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_sraiw = _RAND_1059[0:0];
  _RAND_1060 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_add = _RAND_1060[0:0];
  _RAND_1061 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_addw = _RAND_1061[0:0];
  _RAND_1062 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_sub = _RAND_1062[0:0];
  _RAND_1063 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_subw = _RAND_1063[0:0];
  _RAND_1064 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_sll = _RAND_1064[0:0];
  _RAND_1065 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_sllw = _RAND_1065[0:0];
  _RAND_1066 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_slt = _RAND_1066[0:0];
  _RAND_1067 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_sltu = _RAND_1067[0:0];
  _RAND_1068 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_xor = _RAND_1068[0:0];
  _RAND_1069 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_srl = _RAND_1069[0:0];
  _RAND_1070 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_srlw = _RAND_1070[0:0];
  _RAND_1071 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_sra = _RAND_1071[0:0];
  _RAND_1072 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_sraw = _RAND_1072[0:0];
  _RAND_1073 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_or = _RAND_1073[0:0];
  _RAND_1074 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_and = _RAND_1074[0:0];
  _RAND_1075 = {1{`RANDOM}};
  iss_stage_bufInfo_0_alu_isa_wfi = _RAND_1075[0:0];
  _RAND_1076 = {1{`RANDOM}};
  iss_stage_bufInfo_0_bru_isa_jal = _RAND_1076[0:0];
  _RAND_1077 = {1{`RANDOM}};
  iss_stage_bufInfo_0_bru_isa_jalr = _RAND_1077[0:0];
  _RAND_1078 = {1{`RANDOM}};
  iss_stage_bufInfo_0_bru_isa_beq = _RAND_1078[0:0];
  _RAND_1079 = {1{`RANDOM}};
  iss_stage_bufInfo_0_bru_isa_bne = _RAND_1079[0:0];
  _RAND_1080 = {1{`RANDOM}};
  iss_stage_bufInfo_0_bru_isa_blt = _RAND_1080[0:0];
  _RAND_1081 = {1{`RANDOM}};
  iss_stage_bufInfo_0_bru_isa_bge = _RAND_1081[0:0];
  _RAND_1082 = {1{`RANDOM}};
  iss_stage_bufInfo_0_bru_isa_bltu = _RAND_1082[0:0];
  _RAND_1083 = {1{`RANDOM}};
  iss_stage_bufInfo_0_bru_isa_bgeu = _RAND_1083[0:0];
  _RAND_1084 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_lb = _RAND_1084[0:0];
  _RAND_1085 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_lh = _RAND_1085[0:0];
  _RAND_1086 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_lw = _RAND_1086[0:0];
  _RAND_1087 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_ld = _RAND_1087[0:0];
  _RAND_1088 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_lbu = _RAND_1088[0:0];
  _RAND_1089 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_lhu = _RAND_1089[0:0];
  _RAND_1090 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_lwu = _RAND_1090[0:0];
  _RAND_1091 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_sb = _RAND_1091[0:0];
  _RAND_1092 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_sh = _RAND_1092[0:0];
  _RAND_1093 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_sw = _RAND_1093[0:0];
  _RAND_1094 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_sd = _RAND_1094[0:0];
  _RAND_1095 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_fence = _RAND_1095[0:0];
  _RAND_1096 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_fence_i = _RAND_1096[0:0];
  _RAND_1097 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_sfence_vma = _RAND_1097[0:0];
  _RAND_1098 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_lr_w = _RAND_1098[0:0];
  _RAND_1099 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_sc_w = _RAND_1099[0:0];
  _RAND_1100 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoswap_w = _RAND_1100[0:0];
  _RAND_1101 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoadd_w = _RAND_1101[0:0];
  _RAND_1102 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoxor_w = _RAND_1102[0:0];
  _RAND_1103 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoand_w = _RAND_1103[0:0];
  _RAND_1104 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoor_w = _RAND_1104[0:0];
  _RAND_1105 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amomin_w = _RAND_1105[0:0];
  _RAND_1106 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amomax_w = _RAND_1106[0:0];
  _RAND_1107 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amominu_w = _RAND_1107[0:0];
  _RAND_1108 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amomaxu_w = _RAND_1108[0:0];
  _RAND_1109 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_lr_d = _RAND_1109[0:0];
  _RAND_1110 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_sc_d = _RAND_1110[0:0];
  _RAND_1111 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoswap_d = _RAND_1111[0:0];
  _RAND_1112 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoadd_d = _RAND_1112[0:0];
  _RAND_1113 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoxor_d = _RAND_1113[0:0];
  _RAND_1114 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoand_d = _RAND_1114[0:0];
  _RAND_1115 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amoor_d = _RAND_1115[0:0];
  _RAND_1116 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amomin_d = _RAND_1116[0:0];
  _RAND_1117 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amomax_d = _RAND_1117[0:0];
  _RAND_1118 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amominu_d = _RAND_1118[0:0];
  _RAND_1119 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_amomaxu_d = _RAND_1119[0:0];
  _RAND_1120 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_flw = _RAND_1120[0:0];
  _RAND_1121 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_fsw = _RAND_1121[0:0];
  _RAND_1122 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_fld = _RAND_1122[0:0];
  _RAND_1123 = {1{`RANDOM}};
  iss_stage_bufInfo_0_lsu_isa_fsd = _RAND_1123[0:0];
  _RAND_1124 = {1{`RANDOM}};
  iss_stage_bufInfo_0_csr_isa_rw = _RAND_1124[0:0];
  _RAND_1125 = {1{`RANDOM}};
  iss_stage_bufInfo_0_csr_isa_rs = _RAND_1125[0:0];
  _RAND_1126 = {1{`RANDOM}};
  iss_stage_bufInfo_0_csr_isa_rc = _RAND_1126[0:0];
  _RAND_1127 = {1{`RANDOM}};
  iss_stage_bufInfo_0_csr_isa_rwi = _RAND_1127[0:0];
  _RAND_1128 = {1{`RANDOM}};
  iss_stage_bufInfo_0_csr_isa_rsi = _RAND_1128[0:0];
  _RAND_1129 = {1{`RANDOM}};
  iss_stage_bufInfo_0_csr_isa_rci = _RAND_1129[0:0];
  _RAND_1130 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_mul = _RAND_1130[0:0];
  _RAND_1131 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_mulh = _RAND_1131[0:0];
  _RAND_1132 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_mulhsu = _RAND_1132[0:0];
  _RAND_1133 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_mulhu = _RAND_1133[0:0];
  _RAND_1134 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_div = _RAND_1134[0:0];
  _RAND_1135 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_divu = _RAND_1135[0:0];
  _RAND_1136 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_rem = _RAND_1136[0:0];
  _RAND_1137 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_remu = _RAND_1137[0:0];
  _RAND_1138 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_mulw = _RAND_1138[0:0];
  _RAND_1139 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_divw = _RAND_1139[0:0];
  _RAND_1140 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_divuw = _RAND_1140[0:0];
  _RAND_1141 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_remw = _RAND_1141[0:0];
  _RAND_1142 = {1{`RANDOM}};
  iss_stage_bufInfo_0_mul_isa_remuw = _RAND_1142[0:0];
  _RAND_1143 = {1{`RANDOM}};
  iss_stage_bufInfo_0_param_is_rvc = _RAND_1143[0:0];
  _RAND_1144 = {2{`RANDOM}};
  iss_stage_bufInfo_0_param_pc = _RAND_1144[38:0];
  _RAND_1145 = {2{`RANDOM}};
  iss_stage_bufInfo_0_param_imm = _RAND_1145[63:0];
  _RAND_1146 = {1{`RANDOM}};
  iss_stage_bufInfo_0_param_raw_rs1 = _RAND_1146[4:0];
  _RAND_1147 = {1{`RANDOM}};
  iss_stage_bufInfo_0_phy_rs1 = _RAND_1147[5:0];
  _RAND_1148 = {1{`RANDOM}};
  iss_stage_bufInfo_0_phy_rs2 = _RAND_1148[5:0];
  _RAND_1149 = {1{`RANDOM}};
  iss_stage_bufInfo_0_phy_rd0 = _RAND_1149[5:0];
  _RAND_1150 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_lui = _RAND_1150[0:0];
  _RAND_1151 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_auipc = _RAND_1151[0:0];
  _RAND_1152 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_addi = _RAND_1152[0:0];
  _RAND_1153 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_addiw = _RAND_1153[0:0];
  _RAND_1154 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_slti = _RAND_1154[0:0];
  _RAND_1155 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_sltiu = _RAND_1155[0:0];
  _RAND_1156 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_xori = _RAND_1156[0:0];
  _RAND_1157 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_ori = _RAND_1157[0:0];
  _RAND_1158 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_andi = _RAND_1158[0:0];
  _RAND_1159 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_slli = _RAND_1159[0:0];
  _RAND_1160 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_slliw = _RAND_1160[0:0];
  _RAND_1161 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_srli = _RAND_1161[0:0];
  _RAND_1162 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_srliw = _RAND_1162[0:0];
  _RAND_1163 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_srai = _RAND_1163[0:0];
  _RAND_1164 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_sraiw = _RAND_1164[0:0];
  _RAND_1165 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_add = _RAND_1165[0:0];
  _RAND_1166 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_addw = _RAND_1166[0:0];
  _RAND_1167 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_sub = _RAND_1167[0:0];
  _RAND_1168 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_subw = _RAND_1168[0:0];
  _RAND_1169 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_sll = _RAND_1169[0:0];
  _RAND_1170 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_sllw = _RAND_1170[0:0];
  _RAND_1171 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_slt = _RAND_1171[0:0];
  _RAND_1172 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_sltu = _RAND_1172[0:0];
  _RAND_1173 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_xor = _RAND_1173[0:0];
  _RAND_1174 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_srl = _RAND_1174[0:0];
  _RAND_1175 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_srlw = _RAND_1175[0:0];
  _RAND_1176 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_sra = _RAND_1176[0:0];
  _RAND_1177 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_sraw = _RAND_1177[0:0];
  _RAND_1178 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_or = _RAND_1178[0:0];
  _RAND_1179 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_and = _RAND_1179[0:0];
  _RAND_1180 = {1{`RANDOM}};
  iss_stage_bufInfo_1_alu_isa_wfi = _RAND_1180[0:0];
  _RAND_1181 = {1{`RANDOM}};
  iss_stage_bufInfo_1_bru_isa_jal = _RAND_1181[0:0];
  _RAND_1182 = {1{`RANDOM}};
  iss_stage_bufInfo_1_bru_isa_jalr = _RAND_1182[0:0];
  _RAND_1183 = {1{`RANDOM}};
  iss_stage_bufInfo_1_bru_isa_beq = _RAND_1183[0:0];
  _RAND_1184 = {1{`RANDOM}};
  iss_stage_bufInfo_1_bru_isa_bne = _RAND_1184[0:0];
  _RAND_1185 = {1{`RANDOM}};
  iss_stage_bufInfo_1_bru_isa_blt = _RAND_1185[0:0];
  _RAND_1186 = {1{`RANDOM}};
  iss_stage_bufInfo_1_bru_isa_bge = _RAND_1186[0:0];
  _RAND_1187 = {1{`RANDOM}};
  iss_stage_bufInfo_1_bru_isa_bltu = _RAND_1187[0:0];
  _RAND_1188 = {1{`RANDOM}};
  iss_stage_bufInfo_1_bru_isa_bgeu = _RAND_1188[0:0];
  _RAND_1189 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_lb = _RAND_1189[0:0];
  _RAND_1190 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_lh = _RAND_1190[0:0];
  _RAND_1191 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_lw = _RAND_1191[0:0];
  _RAND_1192 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_ld = _RAND_1192[0:0];
  _RAND_1193 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_lbu = _RAND_1193[0:0];
  _RAND_1194 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_lhu = _RAND_1194[0:0];
  _RAND_1195 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_lwu = _RAND_1195[0:0];
  _RAND_1196 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_sb = _RAND_1196[0:0];
  _RAND_1197 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_sh = _RAND_1197[0:0];
  _RAND_1198 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_sw = _RAND_1198[0:0];
  _RAND_1199 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_sd = _RAND_1199[0:0];
  _RAND_1200 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_fence = _RAND_1200[0:0];
  _RAND_1201 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_fence_i = _RAND_1201[0:0];
  _RAND_1202 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_sfence_vma = _RAND_1202[0:0];
  _RAND_1203 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_lr_w = _RAND_1203[0:0];
  _RAND_1204 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_sc_w = _RAND_1204[0:0];
  _RAND_1205 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoswap_w = _RAND_1205[0:0];
  _RAND_1206 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoadd_w = _RAND_1206[0:0];
  _RAND_1207 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoxor_w = _RAND_1207[0:0];
  _RAND_1208 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoand_w = _RAND_1208[0:0];
  _RAND_1209 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoor_w = _RAND_1209[0:0];
  _RAND_1210 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amomin_w = _RAND_1210[0:0];
  _RAND_1211 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amomax_w = _RAND_1211[0:0];
  _RAND_1212 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amominu_w = _RAND_1212[0:0];
  _RAND_1213 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amomaxu_w = _RAND_1213[0:0];
  _RAND_1214 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_lr_d = _RAND_1214[0:0];
  _RAND_1215 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_sc_d = _RAND_1215[0:0];
  _RAND_1216 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoswap_d = _RAND_1216[0:0];
  _RAND_1217 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoadd_d = _RAND_1217[0:0];
  _RAND_1218 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoxor_d = _RAND_1218[0:0];
  _RAND_1219 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoand_d = _RAND_1219[0:0];
  _RAND_1220 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amoor_d = _RAND_1220[0:0];
  _RAND_1221 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amomin_d = _RAND_1221[0:0];
  _RAND_1222 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amomax_d = _RAND_1222[0:0];
  _RAND_1223 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amominu_d = _RAND_1223[0:0];
  _RAND_1224 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_amomaxu_d = _RAND_1224[0:0];
  _RAND_1225 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_flw = _RAND_1225[0:0];
  _RAND_1226 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_fsw = _RAND_1226[0:0];
  _RAND_1227 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_fld = _RAND_1227[0:0];
  _RAND_1228 = {1{`RANDOM}};
  iss_stage_bufInfo_1_lsu_isa_fsd = _RAND_1228[0:0];
  _RAND_1229 = {1{`RANDOM}};
  iss_stage_bufInfo_1_csr_isa_rw = _RAND_1229[0:0];
  _RAND_1230 = {1{`RANDOM}};
  iss_stage_bufInfo_1_csr_isa_rs = _RAND_1230[0:0];
  _RAND_1231 = {1{`RANDOM}};
  iss_stage_bufInfo_1_csr_isa_rc = _RAND_1231[0:0];
  _RAND_1232 = {1{`RANDOM}};
  iss_stage_bufInfo_1_csr_isa_rwi = _RAND_1232[0:0];
  _RAND_1233 = {1{`RANDOM}};
  iss_stage_bufInfo_1_csr_isa_rsi = _RAND_1233[0:0];
  _RAND_1234 = {1{`RANDOM}};
  iss_stage_bufInfo_1_csr_isa_rci = _RAND_1234[0:0];
  _RAND_1235 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_mul = _RAND_1235[0:0];
  _RAND_1236 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_mulh = _RAND_1236[0:0];
  _RAND_1237 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_mulhsu = _RAND_1237[0:0];
  _RAND_1238 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_mulhu = _RAND_1238[0:0];
  _RAND_1239 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_div = _RAND_1239[0:0];
  _RAND_1240 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_divu = _RAND_1240[0:0];
  _RAND_1241 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_rem = _RAND_1241[0:0];
  _RAND_1242 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_remu = _RAND_1242[0:0];
  _RAND_1243 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_mulw = _RAND_1243[0:0];
  _RAND_1244 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_divw = _RAND_1244[0:0];
  _RAND_1245 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_divuw = _RAND_1245[0:0];
  _RAND_1246 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_remw = _RAND_1246[0:0];
  _RAND_1247 = {1{`RANDOM}};
  iss_stage_bufInfo_1_mul_isa_remuw = _RAND_1247[0:0];
  _RAND_1248 = {1{`RANDOM}};
  iss_stage_bufInfo_1_param_is_rvc = _RAND_1248[0:0];
  _RAND_1249 = {2{`RANDOM}};
  iss_stage_bufInfo_1_param_pc = _RAND_1249[38:0];
  _RAND_1250 = {2{`RANDOM}};
  iss_stage_bufInfo_1_param_imm = _RAND_1250[63:0];
  _RAND_1251 = {1{`RANDOM}};
  iss_stage_bufInfo_1_param_raw_rs1 = _RAND_1251[4:0];
  _RAND_1252 = {1{`RANDOM}};
  iss_stage_bufInfo_1_phy_rs1 = _RAND_1252[5:0];
  _RAND_1253 = {1{`RANDOM}};
  iss_stage_bufInfo_1_phy_rs2 = _RAND_1253[5:0];
  _RAND_1254 = {1{`RANDOM}};
  iss_stage_bufInfo_1_phy_rd0 = _RAND_1254[5:0];
  _RAND_1255 = {1{`RANDOM}};
  iss_stage_isOpReady_0_0 = _RAND_1255[0:0];
  _RAND_1256 = {1{`RANDOM}};
  iss_stage_isOpReady_0_1 = _RAND_1256[0:0];
  _RAND_1257 = {1{`RANDOM}};
  iss_stage_isOpReady_1_0 = _RAND_1257[0:0];
  _RAND_1258 = {1{`RANDOM}};
  iss_stage_isOpReady_1_1 = _RAND_1258[0:0];
  _RAND_1259 = {3{`RANDOM}};
  iss_stage_bufOperator_0_0 = _RAND_1259[64:0];
  _RAND_1260 = {3{`RANDOM}};
  iss_stage_bufOperator_0_1 = _RAND_1260[64:0];
  _RAND_1261 = {3{`RANDOM}};
  iss_stage_bufOperator_1_0 = _RAND_1261[64:0];
  _RAND_1262 = {3{`RANDOM}};
  iss_stage_bufOperator_1_1 = _RAND_1262[64:0];
  _RAND_1263 = {1{`RANDOM}};
  iss_stage_ageMatrixW_0_0 = _RAND_1263[0:0];
  _RAND_1264 = {1{`RANDOM}};
  iss_stage_ageMatrixW_0_1 = _RAND_1264[0:0];
  _RAND_1265 = {1{`RANDOM}};
  iss_stage_ageMatrixW_1_1 = _RAND_1265[0:0];
  _RAND_1268 = {1{`RANDOM}};
  exe_stage_alu_0_alu_exe_iwb_fifo_maybe_full = _RAND_1268[0:0];
  _RAND_1271 = {1{`RANDOM}};
  exe_stage_bru_bru_exe_iwb_fifo_maybe_full = _RAND_1271[0:0];
  _RAND_1278 = {1{`RANDOM}};
  exe_stage_bru_bctq_maybe_full = _RAND_1278[0:0];
  _RAND_1284 = {1{`RANDOM}};
  exe_stage_bru_jctq_maybe_full = _RAND_1284[0:0];
  _RAND_1285 = {1{`RANDOM}};
  exe_stage_bru_misPredict_locker = _RAND_1285[0:0];
  _RAND_1286 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_lb = _RAND_1286[0:0];
  _RAND_1287 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_lh = _RAND_1287[0:0];
  _RAND_1288 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_lw = _RAND_1288[0:0];
  _RAND_1289 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_ld = _RAND_1289[0:0];
  _RAND_1290 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_lbu = _RAND_1290[0:0];
  _RAND_1291 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_lhu = _RAND_1291[0:0];
  _RAND_1292 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_lwu = _RAND_1292[0:0];
  _RAND_1293 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_sb = _RAND_1293[0:0];
  _RAND_1294 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_sh = _RAND_1294[0:0];
  _RAND_1295 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_sw = _RAND_1295[0:0];
  _RAND_1296 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_sd = _RAND_1296[0:0];
  _RAND_1297 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_lr_w = _RAND_1297[0:0];
  _RAND_1298 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_sc_w = _RAND_1298[0:0];
  _RAND_1299 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoswap_w = _RAND_1299[0:0];
  _RAND_1300 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoadd_w = _RAND_1300[0:0];
  _RAND_1301 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoxor_w = _RAND_1301[0:0];
  _RAND_1302 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoand_w = _RAND_1302[0:0];
  _RAND_1303 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoor_w = _RAND_1303[0:0];
  _RAND_1304 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amomin_w = _RAND_1304[0:0];
  _RAND_1305 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amomax_w = _RAND_1305[0:0];
  _RAND_1306 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amominu_w = _RAND_1306[0:0];
  _RAND_1307 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amomaxu_w = _RAND_1307[0:0];
  _RAND_1308 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_lr_d = _RAND_1308[0:0];
  _RAND_1309 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_sc_d = _RAND_1309[0:0];
  _RAND_1310 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoswap_d = _RAND_1310[0:0];
  _RAND_1311 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoadd_d = _RAND_1311[0:0];
  _RAND_1312 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoxor_d = _RAND_1312[0:0];
  _RAND_1313 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoand_d = _RAND_1313[0:0];
  _RAND_1314 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amoor_d = _RAND_1314[0:0];
  _RAND_1315 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amomin_d = _RAND_1315[0:0];
  _RAND_1316 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amomax_d = _RAND_1316[0:0];
  _RAND_1317 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amominu_d = _RAND_1317[0:0];
  _RAND_1318 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_amomaxu_d = _RAND_1318[0:0];
  _RAND_1319 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_flw = _RAND_1319[0:0];
  _RAND_1320 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_fsw = _RAND_1320[0:0];
  _RAND_1321 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_fld = _RAND_1321[0:0];
  _RAND_1322 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_fun_fsd = _RAND_1322[0:0];
  _RAND_1323 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_param_rd0 = _RAND_1323[5:0];
  _RAND_1324 = {2{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_param_dat_op1 = _RAND_1324[63:0];
  _RAND_1325 = {2{`RANDOM}};
  exe_stage_lsu_stQueue_buff_0_param_dat_op2 = _RAND_1325[63:0];
  _RAND_1326 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_lb = _RAND_1326[0:0];
  _RAND_1327 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_lh = _RAND_1327[0:0];
  _RAND_1328 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_lw = _RAND_1328[0:0];
  _RAND_1329 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_ld = _RAND_1329[0:0];
  _RAND_1330 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_lbu = _RAND_1330[0:0];
  _RAND_1331 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_lhu = _RAND_1331[0:0];
  _RAND_1332 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_lwu = _RAND_1332[0:0];
  _RAND_1333 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_sb = _RAND_1333[0:0];
  _RAND_1334 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_sh = _RAND_1334[0:0];
  _RAND_1335 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_sw = _RAND_1335[0:0];
  _RAND_1336 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_sd = _RAND_1336[0:0];
  _RAND_1337 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_lr_w = _RAND_1337[0:0];
  _RAND_1338 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_sc_w = _RAND_1338[0:0];
  _RAND_1339 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoswap_w = _RAND_1339[0:0];
  _RAND_1340 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoadd_w = _RAND_1340[0:0];
  _RAND_1341 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoxor_w = _RAND_1341[0:0];
  _RAND_1342 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoand_w = _RAND_1342[0:0];
  _RAND_1343 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoor_w = _RAND_1343[0:0];
  _RAND_1344 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amomin_w = _RAND_1344[0:0];
  _RAND_1345 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amomax_w = _RAND_1345[0:0];
  _RAND_1346 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amominu_w = _RAND_1346[0:0];
  _RAND_1347 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amomaxu_w = _RAND_1347[0:0];
  _RAND_1348 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_lr_d = _RAND_1348[0:0];
  _RAND_1349 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_sc_d = _RAND_1349[0:0];
  _RAND_1350 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoswap_d = _RAND_1350[0:0];
  _RAND_1351 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoadd_d = _RAND_1351[0:0];
  _RAND_1352 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoxor_d = _RAND_1352[0:0];
  _RAND_1353 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoand_d = _RAND_1353[0:0];
  _RAND_1354 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amoor_d = _RAND_1354[0:0];
  _RAND_1355 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amomin_d = _RAND_1355[0:0];
  _RAND_1356 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amomax_d = _RAND_1356[0:0];
  _RAND_1357 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amominu_d = _RAND_1357[0:0];
  _RAND_1358 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_amomaxu_d = _RAND_1358[0:0];
  _RAND_1359 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_flw = _RAND_1359[0:0];
  _RAND_1360 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_fsw = _RAND_1360[0:0];
  _RAND_1361 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_fld = _RAND_1361[0:0];
  _RAND_1362 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_fun_fsd = _RAND_1362[0:0];
  _RAND_1363 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_param_rd0 = _RAND_1363[5:0];
  _RAND_1364 = {2{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_param_dat_op1 = _RAND_1364[63:0];
  _RAND_1365 = {2{`RANDOM}};
  exe_stage_lsu_stQueue_buff_1_param_dat_op2 = _RAND_1365[63:0];
  _RAND_1366 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_cm_ptr_reg = _RAND_1366[1:0];
  _RAND_1367 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_wr_ptr_reg = _RAND_1367[1:0];
  _RAND_1368 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_rd_ptr_reg = _RAND_1368[1:0];
  _RAND_1369 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_is_amo = _RAND_1369[0:0];
  _RAND_1370 = {1{`RANDOM}};
  exe_stage_lsu_stQueue_is_amo_pre = _RAND_1370[0:0];
  _RAND_1371 = {1{`RANDOM}};
  exe_stage_lsu_system_is_busy = _RAND_1371[0:0];
  _RAND_1372 = {1{`RANDOM}};
  exe_stage_lsu_system_isTransing = _RAND_1372[0:0];
  _RAND_1373 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_lb = _RAND_1373[0:0];
  _RAND_1374 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_lh = _RAND_1374[0:0];
  _RAND_1375 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_lw = _RAND_1375[0:0];
  _RAND_1376 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_ld = _RAND_1376[0:0];
  _RAND_1377 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_lbu = _RAND_1377[0:0];
  _RAND_1378 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_lhu = _RAND_1378[0:0];
  _RAND_1379 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_lwu = _RAND_1379[0:0];
  _RAND_1380 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_sb = _RAND_1380[0:0];
  _RAND_1381 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_sh = _RAND_1381[0:0];
  _RAND_1382 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_sw = _RAND_1382[0:0];
  _RAND_1383 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_sd = _RAND_1383[0:0];
  _RAND_1384 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_lr_w = _RAND_1384[0:0];
  _RAND_1385 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_sc_w = _RAND_1385[0:0];
  _RAND_1386 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoswap_w = _RAND_1386[0:0];
  _RAND_1387 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoadd_w = _RAND_1387[0:0];
  _RAND_1388 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoxor_w = _RAND_1388[0:0];
  _RAND_1389 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoand_w = _RAND_1389[0:0];
  _RAND_1390 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoor_w = _RAND_1390[0:0];
  _RAND_1391 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amomin_w = _RAND_1391[0:0];
  _RAND_1392 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amomax_w = _RAND_1392[0:0];
  _RAND_1393 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amominu_w = _RAND_1393[0:0];
  _RAND_1394 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amomaxu_w = _RAND_1394[0:0];
  _RAND_1395 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_lr_d = _RAND_1395[0:0];
  _RAND_1396 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_sc_d = _RAND_1396[0:0];
  _RAND_1397 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoswap_d = _RAND_1397[0:0];
  _RAND_1398 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoadd_d = _RAND_1398[0:0];
  _RAND_1399 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoxor_d = _RAND_1399[0:0];
  _RAND_1400 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoand_d = _RAND_1400[0:0];
  _RAND_1401 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amoor_d = _RAND_1401[0:0];
  _RAND_1402 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amomin_d = _RAND_1402[0:0];
  _RAND_1403 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amomax_d = _RAND_1403[0:0];
  _RAND_1404 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amominu_d = _RAND_1404[0:0];
  _RAND_1405 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_amomaxu_d = _RAND_1405[0:0];
  _RAND_1406 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_flw = _RAND_1406[0:0];
  _RAND_1407 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_fsw = _RAND_1407[0:0];
  _RAND_1408 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_fld = _RAND_1408[0:0];
  _RAND_1409 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_fun_fsd = _RAND_1409[0:0];
  _RAND_1410 = {1{`RANDOM}};
  exe_stage_lsu_system_pending_param_rd0 = _RAND_1410[5:0];
  _RAND_1411 = {2{`RANDOM}};
  exe_stage_lsu_system_pending_param_dat_op1 = _RAND_1411[63:0];
  _RAND_1412 = {2{`RANDOM}};
  exe_stage_lsu_system_pending_param_dat_op2 = _RAND_1412[63:0];
  _RAND_1413 = {1{`RANDOM}};
  exe_stage_lsu_periph_is_busy = _RAND_1413[0:0];
  _RAND_1414 = {1{`RANDOM}};
  exe_stage_lsu_periph_isTransing = _RAND_1414[0:0];
  _RAND_1415 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_lb = _RAND_1415[0:0];
  _RAND_1416 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_lh = _RAND_1416[0:0];
  _RAND_1417 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_lw = _RAND_1417[0:0];
  _RAND_1418 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_ld = _RAND_1418[0:0];
  _RAND_1419 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_lbu = _RAND_1419[0:0];
  _RAND_1420 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_lhu = _RAND_1420[0:0];
  _RAND_1421 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_lwu = _RAND_1421[0:0];
  _RAND_1422 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_sb = _RAND_1422[0:0];
  _RAND_1423 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_sh = _RAND_1423[0:0];
  _RAND_1424 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_sw = _RAND_1424[0:0];
  _RAND_1425 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_sd = _RAND_1425[0:0];
  _RAND_1426 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_lr_w = _RAND_1426[0:0];
  _RAND_1427 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_sc_w = _RAND_1427[0:0];
  _RAND_1428 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoswap_w = _RAND_1428[0:0];
  _RAND_1429 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoadd_w = _RAND_1429[0:0];
  _RAND_1430 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoxor_w = _RAND_1430[0:0];
  _RAND_1431 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoand_w = _RAND_1431[0:0];
  _RAND_1432 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoor_w = _RAND_1432[0:0];
  _RAND_1433 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amomin_w = _RAND_1433[0:0];
  _RAND_1434 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amomax_w = _RAND_1434[0:0];
  _RAND_1435 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amominu_w = _RAND_1435[0:0];
  _RAND_1436 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amomaxu_w = _RAND_1436[0:0];
  _RAND_1437 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_lr_d = _RAND_1437[0:0];
  _RAND_1438 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_sc_d = _RAND_1438[0:0];
  _RAND_1439 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoswap_d = _RAND_1439[0:0];
  _RAND_1440 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoadd_d = _RAND_1440[0:0];
  _RAND_1441 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoxor_d = _RAND_1441[0:0];
  _RAND_1442 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoand_d = _RAND_1442[0:0];
  _RAND_1443 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amoor_d = _RAND_1443[0:0];
  _RAND_1444 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amomin_d = _RAND_1444[0:0];
  _RAND_1445 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amomax_d = _RAND_1445[0:0];
  _RAND_1446 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amominu_d = _RAND_1446[0:0];
  _RAND_1447 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_amomaxu_d = _RAND_1447[0:0];
  _RAND_1448 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_flw = _RAND_1448[0:0];
  _RAND_1449 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_fsw = _RAND_1449[0:0];
  _RAND_1450 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_fld = _RAND_1450[0:0];
  _RAND_1451 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_fun_fsd = _RAND_1451[0:0];
  _RAND_1452 = {1{`RANDOM}};
  exe_stage_lsu_periph_pending_param_rd0 = _RAND_1452[5:0];
  _RAND_1453 = {2{`RANDOM}};
  exe_stage_lsu_periph_pending_param_dat_op1 = _RAND_1453[63:0];
  _RAND_1454 = {2{`RANDOM}};
  exe_stage_lsu_periph_pending_param_dat_op2 = _RAND_1454[63:0];
  _RAND_1455 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_miss_queue_0_paddr = _RAND_1455[31:0];
  _RAND_1456 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_miss_queue_1_paddr = _RAND_1456[31:0];
  _RAND_1457 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_miss_valid_0 = _RAND_1457[0:0];
  _RAND_1458 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_miss_valid_1 = _RAND_1458[0:0];
  _RAND_1459 = {2{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_miss_rsp_0 = _RAND_1459[63:0];
  _RAND_1460 = {2{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_miss_rsp_1 = _RAND_1460[63:0];
  _RAND_1461 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_mshr_state_qout = _RAND_1461[2:0];
  _RAND_1462 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_counter = _RAND_1462[0:0];
  _RAND_1463 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_acquire_sel_r = _RAND_1463[0:0];
  _RAND_1464 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_cache_acquire_vaild = _RAND_1464[0:0];
  _RAND_1465 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_cache_grantAck_valid = _RAND_1465[0:0];
  _RAND_1466 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_rsp_valid = _RAND_1466[0:0];
  _RAND_1467 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_missUnit_cache_grant_reg_sink = _RAND_1467[4:0];
  _RAND_1469 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_probeUnit_probe_fifo_maybe_full = _RAND_1469[0:0];
  _RAND_1476 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_enq_ptr_value = _RAND_1476[0:0];
  _RAND_1477 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_deq_ptr_value = _RAND_1477[0:0];
  _RAND_1478 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_writeBackUnit_wb_fifo_maybe_full = _RAND_1478[0:0];
  _RAND_1479 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_writeBackUnit_wb_state_qout = _RAND_1479[1:0];
  _RAND_1480 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_writeBackUnit_is_release_done_counter = _RAND_1480[0:0];
  _RAND_1481 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_writeBackUnit_cache_release_valid = _RAND_1481[0:0];
  _RAND_1482 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_writeBackUnit_cache_grant_ready = _RAND_1482[0:0];
  _RAND_1483 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_writeBackUnit_beatCnt = _RAND_1483[0:0];
  _RAND_1529 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_lsEntry_enq_ptr_value = _RAND_1529[0:0];
  _RAND_1530 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_lsEntry_deq_ptr_value = _RAND_1530[0:0];
  _RAND_1531 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_lsEntry_maybe_full = _RAND_1531[0:0];
  _RAND_1538 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_rtn_fifo_enq_ptr_value = _RAND_1538[0:0];
  _RAND_1539 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_rtn_fifo_deq_ptr_value = _RAND_1539[0:0];
  _RAND_1540 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_rtn_fifo_maybe_full = _RAND_1540[0:0];
  _RAND_1586 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_reload_fifo_maybe_full = _RAND_1586[0:0];
  _RAND_1588 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_en_pipe_0 = _RAND_1588[0:0];
  _RAND_1589 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_0_MPORT_addr_pipe_0 = _RAND_1589[0:0];
  _RAND_1591 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_en_pipe_0 = _RAND_1591[0:0];
  _RAND_1592 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_1_MPORT_addr_pipe_0 = _RAND_1592[0:0];
  _RAND_1594 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_en_pipe_0 = _RAND_1594[0:0];
  _RAND_1595 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_2_MPORT_addr_pipe_0 = _RAND_1595[0:0];
  _RAND_1597 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_en_pipe_0 = _RAND_1597[0:0];
  _RAND_1598 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_3_MPORT_addr_pipe_0 = _RAND_1598[0:0];
  _RAND_1600 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_en_pipe_0 = _RAND_1600[0:0];
  _RAND_1601 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_4_MPORT_addr_pipe_0 = _RAND_1601[0:0];
  _RAND_1603 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_en_pipe_0 = _RAND_1603[0:0];
  _RAND_1604 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_5_MPORT_addr_pipe_0 = _RAND_1604[0:0];
  _RAND_1606 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_en_pipe_0 = _RAND_1606[0:0];
  _RAND_1607 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_6_MPORT_addr_pipe_0 = _RAND_1607[0:0];
  _RAND_1609 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_en_pipe_0 = _RAND_1609[0:0];
  _RAND_1610 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_7_MPORT_addr_pipe_0 = _RAND_1610[0:0];
  _RAND_1612 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_en_pipe_0 = _RAND_1612[0:0];
  _RAND_1613 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_8_MPORT_addr_pipe_0 = _RAND_1613[0:0];
  _RAND_1615 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_en_pipe_0 = _RAND_1615[0:0];
  _RAND_1616 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_9_MPORT_addr_pipe_0 = _RAND_1616[0:0];
  _RAND_1618 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_en_pipe_0 = _RAND_1618[0:0];
  _RAND_1619 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_10_MPORT_addr_pipe_0 = _RAND_1619[0:0];
  _RAND_1621 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_en_pipe_0 = _RAND_1621[0:0];
  _RAND_1622 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_11_MPORT_addr_pipe_0 = _RAND_1622[0:0];
  _RAND_1624 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_en_pipe_0 = _RAND_1624[0:0];
  _RAND_1625 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_12_MPORT_addr_pipe_0 = _RAND_1625[0:0];
  _RAND_1627 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_en_pipe_0 = _RAND_1627[0:0];
  _RAND_1628 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_13_MPORT_addr_pipe_0 = _RAND_1628[0:0];
  _RAND_1630 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_en_pipe_0 = _RAND_1630[0:0];
  _RAND_1631 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_14_MPORT_addr_pipe_0 = _RAND_1631[0:0];
  _RAND_1633 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_en_pipe_0 = _RAND_1633[0:0];
  _RAND_1634 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datRAM_0_datMem_15_MPORT_addr_pipe_0 = _RAND_1634[0:0];
  _RAND_1636 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_en_pipe_0 = _RAND_1636[0:0];
  _RAND_1637 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_tagRAM_0_tagMem_io_datar_MPORT_addr_pipe_0 = _RAND_1637[0:0];
  _RAND_1638 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Valid = _RAND_1638[0:0];
  _RAND_1639 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_chkIdx = _RAND_1639[0:0];
  _RAND_1640 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_paddr = _RAND_1640[31:0];
  _RAND_1641 = {4{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_wdata = _RAND_1641[127:0];
  _RAND_1642 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_wstrb = _RAND_1642[15:0];
  _RAND_1643 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lb = _RAND_1643[0:0];
  _RAND_1644 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lh = _RAND_1644[0:0];
  _RAND_1645 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lw = _RAND_1645[0:0];
  _RAND_1646 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_ld = _RAND_1646[0:0];
  _RAND_1647 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lbu = _RAND_1647[0:0];
  _RAND_1648 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lhu = _RAND_1648[0:0];
  _RAND_1649 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lwu = _RAND_1649[0:0];
  _RAND_1650 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sb = _RAND_1650[0:0];
  _RAND_1651 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sh = _RAND_1651[0:0];
  _RAND_1652 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sw = _RAND_1652[0:0];
  _RAND_1653 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sd = _RAND_1653[0:0];
  _RAND_1654 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_w = _RAND_1654[0:0];
  _RAND_1655 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_w = _RAND_1655[0:0];
  _RAND_1656 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_w = _RAND_1656[0:0];
  _RAND_1657 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_w = _RAND_1657[0:0];
  _RAND_1658 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_w = _RAND_1658[0:0];
  _RAND_1659 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_w = _RAND_1659[0:0];
  _RAND_1660 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_w = _RAND_1660[0:0];
  _RAND_1661 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_w = _RAND_1661[0:0];
  _RAND_1662 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_w = _RAND_1662[0:0];
  _RAND_1663 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_w = _RAND_1663[0:0];
  _RAND_1664 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_w = _RAND_1664[0:0];
  _RAND_1665 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_lr_d = _RAND_1665[0:0];
  _RAND_1666 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_sc_d = _RAND_1666[0:0];
  _RAND_1667 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoswap_d = _RAND_1667[0:0];
  _RAND_1668 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoadd_d = _RAND_1668[0:0];
  _RAND_1669 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoxor_d = _RAND_1669[0:0];
  _RAND_1670 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoand_d = _RAND_1670[0:0];
  _RAND_1671 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amoor_d = _RAND_1671[0:0];
  _RAND_1672 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomin_d = _RAND_1672[0:0];
  _RAND_1673 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomax_d = _RAND_1673[0:0];
  _RAND_1674 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amominu_d = _RAND_1674[0:0];
  _RAND_1675 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_amomaxu_d = _RAND_1675[0:0];
  _RAND_1676 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_flw = _RAND_1676[0:0];
  _RAND_1677 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsw = _RAND_1677[0:0];
  _RAND_1678 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fld = _RAND_1678[0:0];
  _RAND_1679 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_fsd = _RAND_1679[0:0];
  _RAND_1680 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_probe = _RAND_1680[0:0];
  _RAND_1681 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_grant = _RAND_1681[0:0];
  _RAND_1682 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_fun_preft = _RAND_1682[0:0];
  _RAND_1683 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_pipeStage1Bits_rd_rd0 = _RAND_1683[5:0];
  _RAND_1684 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_isTagBypass = _RAND_1684[0:0];
  _RAND_1685 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_tagBypassData = _RAND_1685[26:0];
  _RAND_1686 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_isCBValid_1_0 = _RAND_1686[0:0];
  _RAND_1687 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_isCBValid_0_0 = _RAND_1687[0:0];
  _RAND_1688 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_isCBDirty_0_0 = _RAND_1688[0:0];
  _RAND_1689 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_isCBDirty_1_0 = _RAND_1689[0:0];
  _RAND_1690 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_is_pending_lr = _RAND_1690[0:0];
  _RAND_1691 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_is_lr_64_32n = _RAND_1691[0:0];
  _RAND_1692 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_lr_addr = _RAND_1692[31:0];
  _RAND_1693 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_isDatBypass = _RAND_1693[0:0];
  _RAND_1694 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_0 = _RAND_1694[7:0];
  _RAND_1695 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_1 = _RAND_1695[7:0];
  _RAND_1696 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_2 = _RAND_1696[7:0];
  _RAND_1697 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_3 = _RAND_1697[7:0];
  _RAND_1698 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_4 = _RAND_1698[7:0];
  _RAND_1699 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_5 = _RAND_1699[7:0];
  _RAND_1700 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_6 = _RAND_1700[7:0];
  _RAND_1701 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_7 = _RAND_1701[7:0];
  _RAND_1702 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_8 = _RAND_1702[7:0];
  _RAND_1703 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_9 = _RAND_1703[7:0];
  _RAND_1704 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_10 = _RAND_1704[7:0];
  _RAND_1705 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_11 = _RAND_1705[7:0];
  _RAND_1706 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_12 = _RAND_1706[7:0];
  _RAND_1707 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_13 = _RAND_1707[7:0];
  _RAND_1708 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_14 = _RAND_1708[7:0];
  _RAND_1709 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassData_15 = _RAND_1709[7:0];
  _RAND_1710 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_15 = _RAND_1710[0:0];
  _RAND_1711 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_14 = _RAND_1711[0:0];
  _RAND_1712 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_13 = _RAND_1712[0:0];
  _RAND_1713 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_12 = _RAND_1713[0:0];
  _RAND_1714 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_11 = _RAND_1714[0:0];
  _RAND_1715 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_10 = _RAND_1715[0:0];
  _RAND_1716 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_9 = _RAND_1716[0:0];
  _RAND_1717 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_8 = _RAND_1717[0:0];
  _RAND_1718 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_7 = _RAND_1718[0:0];
  _RAND_1719 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_6 = _RAND_1719[0:0];
  _RAND_1720 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_5 = _RAND_1720[0:0];
  _RAND_1721 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_4 = _RAND_1721[0:0];
  _RAND_1722 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_3 = _RAND_1722[0:0];
  _RAND_1723 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_2 = _RAND_1723[0:0];
  _RAND_1724 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_1 = _RAND_1724[0:0];
  _RAND_1725 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_datBypassWM_0 = _RAND_1725[0:0];
  _RAND_1726 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_killTrans = _RAND_1726[0:0];
  _RAND_1727 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_missUnitReqValid = _RAND_1727[0:0];
  _RAND_1728 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_missUnitReqPaddr = _RAND_1728[31:0];
  _RAND_1729 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_wbReqValid = _RAND_1729[0:0];
  _RAND_1730 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_wbReqPaddr = _RAND_1730[31:0];
  _RAND_1731 = {4{`RANDOM}};
  exe_stage_lsu_cache_0_stage_wbReqData = _RAND_1731[127:0];
  _RAND_1732 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_wbReqisData = _RAND_1732[0:0];
  _RAND_1733 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_isPb = _RAND_1733[0:0];
  _RAND_1734 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadValid = _RAND_1734[0:0];
  _RAND_1735 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_chkIdx = _RAND_1735[0:0];
  _RAND_1736 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_paddr = _RAND_1736[31:0];
  _RAND_1737 = {4{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_wdata = _RAND_1737[127:0];
  _RAND_1738 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_wstrb = _RAND_1738[15:0];
  _RAND_1739 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_lb = _RAND_1739[0:0];
  _RAND_1740 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_lh = _RAND_1740[0:0];
  _RAND_1741 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_lw = _RAND_1741[0:0];
  _RAND_1742 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_ld = _RAND_1742[0:0];
  _RAND_1743 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_lbu = _RAND_1743[0:0];
  _RAND_1744 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_lhu = _RAND_1744[0:0];
  _RAND_1745 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_lwu = _RAND_1745[0:0];
  _RAND_1746 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_sb = _RAND_1746[0:0];
  _RAND_1747 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_sh = _RAND_1747[0:0];
  _RAND_1748 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_sw = _RAND_1748[0:0];
  _RAND_1749 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_sd = _RAND_1749[0:0];
  _RAND_1750 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_lr_w = _RAND_1750[0:0];
  _RAND_1751 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_sc_w = _RAND_1751[0:0];
  _RAND_1752 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoswap_w = _RAND_1752[0:0];
  _RAND_1753 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoadd_w = _RAND_1753[0:0];
  _RAND_1754 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoxor_w = _RAND_1754[0:0];
  _RAND_1755 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoand_w = _RAND_1755[0:0];
  _RAND_1756 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoor_w = _RAND_1756[0:0];
  _RAND_1757 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomin_w = _RAND_1757[0:0];
  _RAND_1758 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomax_w = _RAND_1758[0:0];
  _RAND_1759 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amominu_w = _RAND_1759[0:0];
  _RAND_1760 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomaxu_w = _RAND_1760[0:0];
  _RAND_1761 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_lr_d = _RAND_1761[0:0];
  _RAND_1762 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_sc_d = _RAND_1762[0:0];
  _RAND_1763 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoswap_d = _RAND_1763[0:0];
  _RAND_1764 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoadd_d = _RAND_1764[0:0];
  _RAND_1765 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoxor_d = _RAND_1765[0:0];
  _RAND_1766 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoand_d = _RAND_1766[0:0];
  _RAND_1767 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amoor_d = _RAND_1767[0:0];
  _RAND_1768 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomin_d = _RAND_1768[0:0];
  _RAND_1769 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomax_d = _RAND_1769[0:0];
  _RAND_1770 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amominu_d = _RAND_1770[0:0];
  _RAND_1771 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_amomaxu_d = _RAND_1771[0:0];
  _RAND_1772 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_flw = _RAND_1772[0:0];
  _RAND_1773 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_fsw = _RAND_1773[0:0];
  _RAND_1774 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_fld = _RAND_1774[0:0];
  _RAND_1775 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_fsd = _RAND_1775[0:0];
  _RAND_1776 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_probe = _RAND_1776[0:0];
  _RAND_1777 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_grant = _RAND_1777[0:0];
  _RAND_1778 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_fun_preft = _RAND_1778[0:0];
  _RAND_1779 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_reloadBits_rd_rd0 = _RAND_1779[5:0];
  _RAND_1780 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_deqValid = _RAND_1780[0:0];
  _RAND_1781 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_deqBits_chkIdx = _RAND_1781[0:0];
  _RAND_1782 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_deqBits_wb_rd0 = _RAND_1782[5:0];
  _RAND_1783 = {2{`RANDOM}};
  exe_stage_lsu_cache_0_stage_deqBits_wb_res = _RAND_1783[63:0];
  _RAND_1784 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_deqBits_is_load_amo = _RAND_1784[0:0];
  _RAND_1785 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_deqBits_is_flw = _RAND_1785[0:0];
  _RAND_1786 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_stage_deqBits_is_fld = _RAND_1786[0:0];
  _RAND_1787 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_sbBuff_0_paddr = _RAND_1787[31:0];
  _RAND_1788 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_sbBuff_1_paddr = _RAND_1788[31:0];
  _RAND_1789 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_sbValid_0 = _RAND_1789[0:0];
  _RAND_1790 = {1{`RANDOM}};
  exe_stage_lsu_cache_0_sbValid_1 = _RAND_1790[0:0];
  _RAND_1793 = {1{`RANDOM}};
  exe_stage_lsu_lu_wb_fifo_maybe_full = _RAND_1793[0:0];
  _RAND_1794 = {1{`RANDOM}};
  exe_stage_lsu_flu_wb_fifo_maybe_full = _RAND_1794[0:0];
  _RAND_1797 = {1{`RANDOM}};
  exe_stage_lsu_su_wb_fifo_maybe_full = _RAND_1797[0:0];
  _RAND_1800 = {1{`RANDOM}};
  exe_stage_lsu_fe_wb_fifo_maybe_full = _RAND_1800[0:0];
  _RAND_1801 = {1{`RANDOM}};
  exe_stage_lsu_trans_kill = _RAND_1801[0:0];
  _RAND_1802 = {1{`RANDOM}};
  exe_stage_lsu_is_chnc_busy_0 = _RAND_1802[0:0];
  _RAND_1803 = {1{`RANDOM}};
  exe_stage_lsu_is_release_done_counter = _RAND_1803[0:0];
  _RAND_1804 = {1{`RANDOM}};
  exe_stage_lsu_isAccessFaultReg = _RAND_1804[0:0];
  _RAND_1805 = {1{`RANDOM}};
  exe_stage_lsu_isPagingFault = _RAND_1805[0:0];
  _RAND_1806 = {1{`RANDOM}};
  exe_stage_lsu_isMisAlign = _RAND_1806[0:0];
  _RAND_1807 = {2{`RANDOM}};
  exe_stage_lsu_trapAddrReg = _RAND_1807[63:0];
  _RAND_1810 = {1{`RANDOM}};
  exe_stage_csr_csr_exe_iwb_fifo_maybe_full = _RAND_1810[0:0];
  _RAND_1816 = {1{`RANDOM}};
  exe_stage_csr_csr_op_fifo_maybe_full = _RAND_1816[0:0];
  _RAND_1819 = {1{`RANDOM}};
  exe_stage_mulDiv_0_mul_exe_iwb_fifo_maybe_full = _RAND_1819[0:0];
  _RAND_1820 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_isDivBusy = _RAND_1820[0:0];
  _RAND_1821 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_cnt = _RAND_1821[6:0];
  _RAND_1822 = {4{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_dividend = _RAND_1822[127:0];
  _RAND_1823 = {2{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_divisor = _RAND_1823[63:0];
  _RAND_1824 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_div = _RAND_1824[0:0];
  _RAND_1825 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divu = _RAND_1825[0:0];
  _RAND_1826 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_rem = _RAND_1826[0:0];
  _RAND_1827 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remu = _RAND_1827[0:0];
  _RAND_1828 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divw = _RAND_1828[0:0];
  _RAND_1829 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_divuw = _RAND_1829[0:0];
  _RAND_1830 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remw = _RAND_1830[0:0];
  _RAND_1831 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_fun_remuw = _RAND_1831[0:0];
  _RAND_1832 = {1{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_rd0 = _RAND_1832[5:0];
  _RAND_1833 = {2{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_dat_op1 = _RAND_1833[63:0];
  _RAND_1834 = {2{`RANDOM}};
  exe_stage_mulDiv_0_dividor_algDivider_pendingInfo_param_dat_op2 = _RAND_1834[63:0];
  _RAND_1835 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_0 = _RAND_1835[1:0];
  _RAND_1836 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_1 = _RAND_1836[1:0];
  _RAND_1837 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_2 = _RAND_1837[1:0];
  _RAND_1838 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_3 = _RAND_1838[1:0];
  _RAND_1839 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_4 = _RAND_1839[1:0];
  _RAND_1840 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_5 = _RAND_1840[1:0];
  _RAND_1841 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_6 = _RAND_1841[1:0];
  _RAND_1842 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_7 = _RAND_1842[1:0];
  _RAND_1843 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_8 = _RAND_1843[1:0];
  _RAND_1844 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_9 = _RAND_1844[1:0];
  _RAND_1845 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_10 = _RAND_1845[1:0];
  _RAND_1846 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_11 = _RAND_1846[1:0];
  _RAND_1847 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_12 = _RAND_1847[1:0];
  _RAND_1848 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_13 = _RAND_1848[1:0];
  _RAND_1849 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_14 = _RAND_1849[1:0];
  _RAND_1850 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_15 = _RAND_1850[1:0];
  _RAND_1851 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_16 = _RAND_1851[1:0];
  _RAND_1852 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_17 = _RAND_1852[1:0];
  _RAND_1853 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_18 = _RAND_1853[1:0];
  _RAND_1854 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_19 = _RAND_1854[1:0];
  _RAND_1855 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_20 = _RAND_1855[1:0];
  _RAND_1856 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_21 = _RAND_1856[1:0];
  _RAND_1857 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_22 = _RAND_1857[1:0];
  _RAND_1858 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_23 = _RAND_1858[1:0];
  _RAND_1859 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_24 = _RAND_1859[1:0];
  _RAND_1860 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_25 = _RAND_1860[1:0];
  _RAND_1861 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_26 = _RAND_1861[1:0];
  _RAND_1862 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_27 = _RAND_1862[1:0];
  _RAND_1863 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_28 = _RAND_1863[1:0];
  _RAND_1864 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_29 = _RAND_1864[1:0];
  _RAND_1865 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_30 = _RAND_1865[1:0];
  _RAND_1866 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_31 = _RAND_1866[1:0];
  _RAND_1867 = {1{`RANDOM}};
  iwb_stage_iReg_log_reg_32 = _RAND_1867[1:0];
  _RAND_1868 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_0 = _RAND_1868[63:0];
  _RAND_1869 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_1 = _RAND_1869[63:0];
  _RAND_1870 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_2 = _RAND_1870[63:0];
  _RAND_1871 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_3 = _RAND_1871[63:0];
  _RAND_1872 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_4 = _RAND_1872[63:0];
  _RAND_1873 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_5 = _RAND_1873[63:0];
  _RAND_1874 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_6 = _RAND_1874[63:0];
  _RAND_1875 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_7 = _RAND_1875[63:0];
  _RAND_1876 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_8 = _RAND_1876[63:0];
  _RAND_1877 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_9 = _RAND_1877[63:0];
  _RAND_1878 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_10 = _RAND_1878[63:0];
  _RAND_1879 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_11 = _RAND_1879[63:0];
  _RAND_1880 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_12 = _RAND_1880[63:0];
  _RAND_1881 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_13 = _RAND_1881[63:0];
  _RAND_1882 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_14 = _RAND_1882[63:0];
  _RAND_1883 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_15 = _RAND_1883[63:0];
  _RAND_1884 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_16 = _RAND_1884[63:0];
  _RAND_1885 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_17 = _RAND_1885[63:0];
  _RAND_1886 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_18 = _RAND_1886[63:0];
  _RAND_1887 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_19 = _RAND_1887[63:0];
  _RAND_1888 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_20 = _RAND_1888[63:0];
  _RAND_1889 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_21 = _RAND_1889[63:0];
  _RAND_1890 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_22 = _RAND_1890[63:0];
  _RAND_1891 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_23 = _RAND_1891[63:0];
  _RAND_1892 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_24 = _RAND_1892[63:0];
  _RAND_1893 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_25 = _RAND_1893[63:0];
  _RAND_1894 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_26 = _RAND_1894[63:0];
  _RAND_1895 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_27 = _RAND_1895[63:0];
  _RAND_1896 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_28 = _RAND_1896[63:0];
  _RAND_1897 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_29 = _RAND_1897[63:0];
  _RAND_1898 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_30 = _RAND_1898[63:0];
  _RAND_1899 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_31 = _RAND_1899[63:0];
  _RAND_1900 = {2{`RANDOM}};
  iwb_stage_iReg_files_reg_32 = _RAND_1900[63:0];
  _RAND_1901 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_0 = _RAND_1901[5:0];
  _RAND_1902 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_1 = _RAND_1902[5:0];
  _RAND_1903 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_2 = _RAND_1903[5:0];
  _RAND_1904 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_3 = _RAND_1904[5:0];
  _RAND_1905 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_4 = _RAND_1905[5:0];
  _RAND_1906 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_5 = _RAND_1906[5:0];
  _RAND_1907 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_6 = _RAND_1907[5:0];
  _RAND_1908 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_7 = _RAND_1908[5:0];
  _RAND_1909 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_8 = _RAND_1909[5:0];
  _RAND_1910 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_9 = _RAND_1910[5:0];
  _RAND_1911 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_10 = _RAND_1911[5:0];
  _RAND_1912 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_11 = _RAND_1912[5:0];
  _RAND_1913 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_12 = _RAND_1913[5:0];
  _RAND_1914 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_13 = _RAND_1914[5:0];
  _RAND_1915 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_14 = _RAND_1915[5:0];
  _RAND_1916 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_15 = _RAND_1916[5:0];
  _RAND_1917 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_16 = _RAND_1917[5:0];
  _RAND_1918 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_17 = _RAND_1918[5:0];
  _RAND_1919 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_18 = _RAND_1919[5:0];
  _RAND_1920 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_19 = _RAND_1920[5:0];
  _RAND_1921 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_20 = _RAND_1921[5:0];
  _RAND_1922 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_21 = _RAND_1922[5:0];
  _RAND_1923 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_22 = _RAND_1923[5:0];
  _RAND_1924 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_23 = _RAND_1924[5:0];
  _RAND_1925 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_24 = _RAND_1925[5:0];
  _RAND_1926 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_25 = _RAND_1926[5:0];
  _RAND_1927 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_26 = _RAND_1927[5:0];
  _RAND_1928 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_27 = _RAND_1928[5:0];
  _RAND_1929 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_28 = _RAND_1929[5:0];
  _RAND_1930 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_29 = _RAND_1930[5:0];
  _RAND_1931 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_30 = _RAND_1931[5:0];
  _RAND_1932 = {1{`RANDOM}};
  iwb_stage_iReg_rename_ptr_31 = _RAND_1932[5:0];
  _RAND_1933 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_0 = _RAND_1933[5:0];
  _RAND_1934 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_1 = _RAND_1934[5:0];
  _RAND_1935 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_2 = _RAND_1935[5:0];
  _RAND_1936 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_3 = _RAND_1936[5:0];
  _RAND_1937 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_4 = _RAND_1937[5:0];
  _RAND_1938 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_5 = _RAND_1938[5:0];
  _RAND_1939 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_6 = _RAND_1939[5:0];
  _RAND_1940 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_7 = _RAND_1940[5:0];
  _RAND_1941 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_8 = _RAND_1941[5:0];
  _RAND_1942 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_9 = _RAND_1942[5:0];
  _RAND_1943 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_10 = _RAND_1943[5:0];
  _RAND_1944 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_11 = _RAND_1944[5:0];
  _RAND_1945 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_12 = _RAND_1945[5:0];
  _RAND_1946 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_13 = _RAND_1946[5:0];
  _RAND_1947 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_14 = _RAND_1947[5:0];
  _RAND_1948 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_15 = _RAND_1948[5:0];
  _RAND_1949 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_16 = _RAND_1949[5:0];
  _RAND_1950 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_17 = _RAND_1950[5:0];
  _RAND_1951 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_18 = _RAND_1951[5:0];
  _RAND_1952 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_19 = _RAND_1952[5:0];
  _RAND_1953 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_20 = _RAND_1953[5:0];
  _RAND_1954 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_21 = _RAND_1954[5:0];
  _RAND_1955 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_22 = _RAND_1955[5:0];
  _RAND_1956 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_23 = _RAND_1956[5:0];
  _RAND_1957 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_24 = _RAND_1957[5:0];
  _RAND_1958 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_25 = _RAND_1958[5:0];
  _RAND_1959 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_26 = _RAND_1959[5:0];
  _RAND_1960 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_27 = _RAND_1960[5:0];
  _RAND_1961 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_28 = _RAND_1961[5:0];
  _RAND_1962 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_29 = _RAND_1962[5:0];
  _RAND_1963 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_30 = _RAND_1963[5:0];
  _RAND_1964 = {1{`RANDOM}};
  iwb_stage_iReg_archit_ptr_31 = _RAND_1964[5:0];
  _RAND_1965 = {1{`RANDOM}};
  iwb_stage_iReg_io_rgRsp_0_valid_REG = _RAND_1965[0:0];
  _RAND_1966 = {1{`RANDOM}};
  iwb_stage_iReg_io_rgRsp_0_bits_phy_r = _RAND_1966[5:0];
  _RAND_1967 = {2{`RANDOM}};
  iwb_stage_iReg_io_rgRsp_0_bits_op_r = _RAND_1967[63:0];
  _RAND_1968 = {1{`RANDOM}};
  cmm_stage_csrfiles_priv_lvl = _RAND_1968[1:0];
  _RAND_1969 = {1{`RANDOM}};
  cmm_stage_csrfiles_DMode = _RAND_1969[0:0];
  _RAND_1970 = {1{`RANDOM}};
  cmm_stage_csrfiles_fcsr_frm = _RAND_1970[2:0];
  _RAND_1971 = {1{`RANDOM}};
  cmm_stage_csrfiles_fcsr_fflags = _RAND_1971[4:0];
  _RAND_1972 = {2{`RANDOM}};
  cmm_stage_csrfiles_time = _RAND_1972[63:0];
  _RAND_1973 = {2{`RANDOM}};
  cmm_stage_csrfiles_stvec_base = _RAND_1973[61:0];
  _RAND_1974 = {1{`RANDOM}};
  cmm_stage_csrfiles_scounteren_hpm = _RAND_1974[31:0];
  _RAND_1975 = {2{`RANDOM}};
  cmm_stage_csrfiles_sscratch = _RAND_1975[63:0];
  _RAND_1976 = {2{`RANDOM}};
  cmm_stage_csrfiles_sepc = _RAND_1976[63:0];
  _RAND_1977 = {1{`RANDOM}};
  cmm_stage_csrfiles_scause_interrupt = _RAND_1977[0:0];
  _RAND_1978 = {2{`RANDOM}};
  cmm_stage_csrfiles_scause_exception_code = _RAND_1978[62:0];
  _RAND_1979 = {2{`RANDOM}};
  cmm_stage_csrfiles_stval = _RAND_1979[63:0];
  _RAND_1980 = {1{`RANDOM}};
  cmm_stage_csrfiles_satp_mode = _RAND_1980[3:0];
  _RAND_1981 = {1{`RANDOM}};
  cmm_stage_csrfiles_satp_asid = _RAND_1981[15:0];
  _RAND_1982 = {2{`RANDOM}};
  cmm_stage_csrfiles_satp_ppn = _RAND_1982[43:0];
  _RAND_1983 = {2{`RANDOM}};
  cmm_stage_csrfiles_marchid = _RAND_1983[63:0];
  _RAND_1984 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_sd = _RAND_1984[0:0];
  _RAND_1985 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_tsr = _RAND_1985[0:0];
  _RAND_1986 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_tw = _RAND_1986[0:0];
  _RAND_1987 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_tvm = _RAND_1987[0:0];
  _RAND_1988 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_mxr = _RAND_1988[0:0];
  _RAND_1989 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_sum = _RAND_1989[0:0];
  _RAND_1990 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_mprv = _RAND_1990[0:0];
  _RAND_1991 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_fs = _RAND_1991[1:0];
  _RAND_1992 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_mpp = _RAND_1992[1:0];
  _RAND_1993 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_spp = _RAND_1993[0:0];
  _RAND_1994 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_mpie = _RAND_1994[0:0];
  _RAND_1995 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_spie = _RAND_1995[0:0];
  _RAND_1996 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_mie = _RAND_1996[0:0];
  _RAND_1997 = {1{`RANDOM}};
  cmm_stage_csrfiles_mstatus_sie = _RAND_1997[0:0];
  _RAND_1998 = {2{`RANDOM}};
  cmm_stage_csrfiles_misa = _RAND_1998[63:0];
  _RAND_1999 = {2{`RANDOM}};
  cmm_stage_csrfiles_medeleg = _RAND_1999[63:0];
  _RAND_2000 = {2{`RANDOM}};
  cmm_stage_csrfiles_mideleg = _RAND_2000[63:0];
  _RAND_2001 = {1{`RANDOM}};
  cmm_stage_csrfiles_mie_mei = _RAND_2001[0:0];
  _RAND_2002 = {1{`RANDOM}};
  cmm_stage_csrfiles_mie_sei = _RAND_2002[0:0];
  _RAND_2003 = {1{`RANDOM}};
  cmm_stage_csrfiles_mie_mti = _RAND_2003[0:0];
  _RAND_2004 = {1{`RANDOM}};
  cmm_stage_csrfiles_mie_sti = _RAND_2004[0:0];
  _RAND_2005 = {1{`RANDOM}};
  cmm_stage_csrfiles_mie_msi = _RAND_2005[0:0];
  _RAND_2006 = {1{`RANDOM}};
  cmm_stage_csrfiles_mie_ssi = _RAND_2006[0:0];
  _RAND_2007 = {2{`RANDOM}};
  cmm_stage_csrfiles_mtvec_base = _RAND_2007[61:0];
  _RAND_2008 = {1{`RANDOM}};
  cmm_stage_csrfiles_mcounteren_hpm = _RAND_2008[31:0];
  _RAND_2009 = {2{`RANDOM}};
  cmm_stage_csrfiles_mscratch = _RAND_2009[63:0];
  _RAND_2010 = {2{`RANDOM}};
  cmm_stage_csrfiles_mepc = _RAND_2010[63:0];
  _RAND_2011 = {1{`RANDOM}};
  cmm_stage_csrfiles_mcause_interrupt = _RAND_2011[0:0];
  _RAND_2012 = {2{`RANDOM}};
  cmm_stage_csrfiles_mcause_exception_code = _RAND_2012[62:0];
  _RAND_2013 = {2{`RANDOM}};
  cmm_stage_csrfiles_mtval = _RAND_2013[63:0];
  _RAND_2014 = {1{`RANDOM}};
  cmm_stage_csrfiles_mip_mei = _RAND_2014[0:0];
  _RAND_2015 = {1{`RANDOM}};
  cmm_stage_csrfiles_mip_sei = _RAND_2015[0:0];
  _RAND_2016 = {1{`RANDOM}};
  cmm_stage_csrfiles_mip_mti = _RAND_2016[0:0];
  _RAND_2017 = {1{`RANDOM}};
  cmm_stage_csrfiles_mip_sti = _RAND_2017[0:0];
  _RAND_2018 = {1{`RANDOM}};
  cmm_stage_csrfiles_mip_msi = _RAND_2018[0:0];
  _RAND_2019 = {1{`RANDOM}};
  cmm_stage_csrfiles_mip_ssi = _RAND_2019[0:0];
  _RAND_2020 = {2{`RANDOM}};
  cmm_stage_csrfiles_mtinst = _RAND_2020[63:0];
  _RAND_2021 = {2{`RANDOM}};
  cmm_stage_csrfiles_mtval2 = _RAND_2021[63:0];
  _RAND_2022 = {2{`RANDOM}};
  cmm_stage_csrfiles_mcycle = _RAND_2022[63:0];
  _RAND_2023 = {2{`RANDOM}};
  cmm_stage_csrfiles_minstret = _RAND_2023[63:0];
  _RAND_2024 = {2{`RANDOM}};
  cmm_stage_csrfiles_tselect = _RAND_2024[63:0];
  _RAND_2025 = {2{`RANDOM}};
  cmm_stage_csrfiles_tdata1 = _RAND_2025[63:0];
  _RAND_2026 = {2{`RANDOM}};
  cmm_stage_csrfiles_tdata2 = _RAND_2026[63:0];
  _RAND_2027 = {2{`RANDOM}};
  cmm_stage_csrfiles_tdata3 = _RAND_2027[63:0];
  _RAND_2028 = {1{`RANDOM}};
  cmm_stage_csrfiles_dcsr_ebreakm = _RAND_2028[0:0];
  _RAND_2029 = {1{`RANDOM}};
  cmm_stage_csrfiles_dcsr_ebreaks = _RAND_2029[0:0];
  _RAND_2030 = {1{`RANDOM}};
  cmm_stage_csrfiles_dcsr_ebreaku = _RAND_2030[0:0];
  _RAND_2031 = {1{`RANDOM}};
  cmm_stage_csrfiles_dcsr_cause = _RAND_2031[2:0];
  _RAND_2032 = {1{`RANDOM}};
  cmm_stage_csrfiles_dcsr_step = _RAND_2032[0:0];
  _RAND_2033 = {1{`RANDOM}};
  cmm_stage_csrfiles_dcsr_prv = _RAND_2033[1:0];
  _RAND_2034 = {2{`RANDOM}};
  cmm_stage_csrfiles_dpc = _RAND_2034[63:0];
  _RAND_2035 = {2{`RANDOM}};
  cmm_stage_csrfiles_dscratch0 = _RAND_2035[63:0];
  _RAND_2036 = {2{`RANDOM}};
  cmm_stage_csrfiles_dscratch1 = _RAND_2036[63:0];
  _RAND_2037 = {2{`RANDOM}};
  cmm_stage_csrfiles_dscratch2 = _RAND_2037[63:0];
  _RAND_2038 = {1{`RANDOM}};
  cmm_stage_is_single_step = _RAND_2038[0:0];
  _RAND_2039 = {1{`RANDOM}};
  cmm_stage_emu_reset = _RAND_2039[0:0];
  _RAND_2040 = {1{`RANDOM}};
  cmm_stage_rtc_0 = _RAND_2040[0:0];
  _RAND_2041 = {1{`RANDOM}};
  cmm_stage_rtc_1 = _RAND_2041[0:0];
  _RAND_2042 = {1{`RANDOM}};
  cmm_stage_rtc_2 = _RAND_2042[0:0];
  _RAND_2043 = {1{`RANDOM}};
  cmm_stage_rtc_3 = _RAND_2043[0:0];
  _RAND_2044 = {1{`RANDOM}};
  i_mmu_itlb_random_idx_prng_state_0 = _RAND_2044[0:0];
  _RAND_2045 = {1{`RANDOM}};
  i_mmu_itlb_random_idx_prng_state_1 = _RAND_2045[0:0];
  _RAND_2046 = {1{`RANDOM}};
  i_mmu_itlb_random_idx_prng_1_state_0 = _RAND_2046[0:0];
  _RAND_2047 = {1{`RANDOM}};
  i_mmu_itlb_random_idx_prng_1_state_1 = _RAND_2047[0:0];
  _RAND_2048 = {1{`RANDOM}};
  i_mmu_itlb_random_idx_prng_2_state_0 = _RAND_2048[0:0];
  _RAND_2049 = {1{`RANDOM}};
  i_mmu_itlb_random_idx_prng_2_state_1 = _RAND_2049[0:0];
  _RAND_2050 = {1{`RANDOM}};
  i_mmu_itlb_random_idx_prng_3_state_0 = _RAND_2050[0:0];
  _RAND_2051 = {1{`RANDOM}};
  i_mmu_itlb_random_idx_prng_3_state_1 = _RAND_2051[0:0];
  _RAND_2052 = {1{`RANDOM}};
  i_mmu_itlb_tag_0_is_valid = _RAND_2052[0:0];
  _RAND_2053 = {1{`RANDOM}};
  i_mmu_itlb_tag_0_asid = _RAND_2053[15:0];
  _RAND_2054 = {1{`RANDOM}};
  i_mmu_itlb_tag_0_vpn_0 = _RAND_2054[8:0];
  _RAND_2055 = {1{`RANDOM}};
  i_mmu_itlb_tag_0_vpn_1 = _RAND_2055[8:0];
  _RAND_2056 = {1{`RANDOM}};
  i_mmu_itlb_tag_0_vpn_2 = _RAND_2056[8:0];
  _RAND_2057 = {1{`RANDOM}};
  i_mmu_itlb_tag_1_is_valid = _RAND_2057[0:0];
  _RAND_2058 = {1{`RANDOM}};
  i_mmu_itlb_tag_1_asid = _RAND_2058[15:0];
  _RAND_2059 = {1{`RANDOM}};
  i_mmu_itlb_tag_1_vpn_0 = _RAND_2059[8:0];
  _RAND_2060 = {1{`RANDOM}};
  i_mmu_itlb_tag_1_vpn_1 = _RAND_2060[8:0];
  _RAND_2061 = {1{`RANDOM}};
  i_mmu_itlb_tag_1_vpn_2 = _RAND_2061[8:0];
  _RAND_2062 = {2{`RANDOM}};
  i_mmu_itlb_pte_0_value = _RAND_2062[63:0];
  _RAND_2063 = {1{`RANDOM}};
  i_mmu_itlb_pte_0_is_giga_page = _RAND_2063[0:0];
  _RAND_2064 = {1{`RANDOM}};
  i_mmu_itlb_pte_0_is_mega_page = _RAND_2064[0:0];
  _RAND_2065 = {2{`RANDOM}};
  i_mmu_itlb_pte_1_value = _RAND_2065[63:0];
  _RAND_2066 = {1{`RANDOM}};
  i_mmu_itlb_pte_1_is_giga_page = _RAND_2066[0:0];
  _RAND_2067 = {1{`RANDOM}};
  i_mmu_itlb_pte_1_is_mega_page = _RAND_2067[0:0];
  _RAND_2068 = {1{`RANDOM}};
  i_mmu_dtlb_random_idx_prng_state_0 = _RAND_2068[0:0];
  _RAND_2069 = {1{`RANDOM}};
  i_mmu_dtlb_random_idx_prng_state_1 = _RAND_2069[0:0];
  _RAND_2070 = {1{`RANDOM}};
  i_mmu_dtlb_random_idx_prng_1_state_0 = _RAND_2070[0:0];
  _RAND_2071 = {1{`RANDOM}};
  i_mmu_dtlb_random_idx_prng_1_state_1 = _RAND_2071[0:0];
  _RAND_2072 = {1{`RANDOM}};
  i_mmu_dtlb_random_idx_prng_2_state_0 = _RAND_2072[0:0];
  _RAND_2073 = {1{`RANDOM}};
  i_mmu_dtlb_random_idx_prng_2_state_1 = _RAND_2073[0:0];
  _RAND_2074 = {1{`RANDOM}};
  i_mmu_dtlb_random_idx_prng_3_state_0 = _RAND_2074[0:0];
  _RAND_2075 = {1{`RANDOM}};
  i_mmu_dtlb_random_idx_prng_3_state_1 = _RAND_2075[0:0];
  _RAND_2076 = {1{`RANDOM}};
  i_mmu_dtlb_tag_0_is_valid = _RAND_2076[0:0];
  _RAND_2077 = {1{`RANDOM}};
  i_mmu_dtlb_tag_0_asid = _RAND_2077[15:0];
  _RAND_2078 = {1{`RANDOM}};
  i_mmu_dtlb_tag_0_vpn_0 = _RAND_2078[8:0];
  _RAND_2079 = {1{`RANDOM}};
  i_mmu_dtlb_tag_0_vpn_1 = _RAND_2079[8:0];
  _RAND_2080 = {1{`RANDOM}};
  i_mmu_dtlb_tag_0_vpn_2 = _RAND_2080[8:0];
  _RAND_2081 = {1{`RANDOM}};
  i_mmu_dtlb_tag_1_is_valid = _RAND_2081[0:0];
  _RAND_2082 = {1{`RANDOM}};
  i_mmu_dtlb_tag_1_asid = _RAND_2082[15:0];
  _RAND_2083 = {1{`RANDOM}};
  i_mmu_dtlb_tag_1_vpn_0 = _RAND_2083[8:0];
  _RAND_2084 = {1{`RANDOM}};
  i_mmu_dtlb_tag_1_vpn_1 = _RAND_2084[8:0];
  _RAND_2085 = {1{`RANDOM}};
  i_mmu_dtlb_tag_1_vpn_2 = _RAND_2085[8:0];
  _RAND_2086 = {2{`RANDOM}};
  i_mmu_dtlb_pte_0_value = _RAND_2086[63:0];
  _RAND_2087 = {1{`RANDOM}};
  i_mmu_dtlb_pte_0_is_giga_page = _RAND_2087[0:0];
  _RAND_2088 = {1{`RANDOM}};
  i_mmu_dtlb_pte_0_is_mega_page = _RAND_2088[0:0];
  _RAND_2089 = {2{`RANDOM}};
  i_mmu_dtlb_pte_1_value = _RAND_2089[63:0];
  _RAND_2090 = {1{`RANDOM}};
  i_mmu_dtlb_pte_1_is_giga_page = _RAND_2090[0:0];
  _RAND_2091 = {1{`RANDOM}};
  i_mmu_dtlb_pte_1_is_mega_page = _RAND_2091[0:0];
  _RAND_2092 = {1{`RANDOM}};
  i_mmu_iptw_currState = _RAND_2092[1:0];
  _RAND_2093 = {1{`RANDOM}};
  i_mmu_iptw_kill_trans = _RAND_2093[0:0];
  _RAND_2094 = {1{`RANDOM}};
  i_mmu_iptw_counter = _RAND_2094[0:0];
  _RAND_2095 = {1{`RANDOM}};
  i_mmu_iptw_addr_qout = _RAND_2095[31:0];
  _RAND_2096 = {2{`RANDOM}};
  i_mmu_iptw_ptw_access_data_lo_0 = _RAND_2096[63:0];
  _RAND_2097 = {2{`RANDOM}};
  i_mmu_iptw_pte_value_value = _RAND_2097[63:0];
  _RAND_2098 = {1{`RANDOM}};
  i_mmu_iptw_walkReq_is_X = _RAND_2098[0:0];
  _RAND_2099 = {2{`RANDOM}};
  i_mmu_iptw_walkReq_vaddr = _RAND_2099[63:0];
  _RAND_2100 = {1{`RANDOM}};
  i_mmu_iptw_asidReq = _RAND_2100[15:0];
  _RAND_2101 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_is_X = _RAND_2101[0:0];
  _RAND_2102 = {2{`RANDOM}};
  i_mmu_iptw_walkRspBits_renew_value = _RAND_2102[63:0];
  _RAND_2103 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_renew_is_giga_page = _RAND_2103[0:0];
  _RAND_2104 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_renew_is_mega_page = _RAND_2104[0:0];
  _RAND_2105 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_renew_asid = _RAND_2105[15:0];
  _RAND_2106 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_renew_vpn_0 = _RAND_2106[8:0];
  _RAND_2107 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_renew_vpn_1 = _RAND_2107[8:0];
  _RAND_2108 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_renew_vpn_2 = _RAND_2108[8:0];
  _RAND_2109 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_is_ptw_fail = _RAND_2109[0:0];
  _RAND_2110 = {1{`RANDOM}};
  i_mmu_iptw_walkRspBits_is_access_fault = _RAND_2110[0:0];
  _RAND_2111 = {1{`RANDOM}};
  i_mmu_iptw_walkRspValid = _RAND_2111[0:0];
  _RAND_2112 = {1{`RANDOM}};
  i_mmu_iptw_ptw_get_valid = _RAND_2112[0:0];
  _RAND_2113 = {1{`RANDOM}};
  i_mmu_iptw_ptw_access_ready = _RAND_2113[0:0];
  _RAND_2114 = {1{`RANDOM}};
  i_mmu_iptw_is_get_reqed = _RAND_2114[0:0];
  _RAND_2115 = {1{`RANDOM}};
  i_mmu_dptw_currState = _RAND_2115[1:0];
  _RAND_2116 = {1{`RANDOM}};
  i_mmu_dptw_kill_trans = _RAND_2116[0:0];
  _RAND_2117 = {1{`RANDOM}};
  i_mmu_dptw_counter = _RAND_2117[0:0];
  _RAND_2118 = {1{`RANDOM}};
  i_mmu_dptw_addr_qout = _RAND_2118[31:0];
  _RAND_2119 = {2{`RANDOM}};
  i_mmu_dptw_ptw_access_data_lo_0 = _RAND_2119[63:0];
  _RAND_2120 = {2{`RANDOM}};
  i_mmu_dptw_pte_value_value = _RAND_2120[63:0];
  _RAND_2121 = {1{`RANDOM}};
  i_mmu_dptw_walkReq_is_X = _RAND_2121[0:0];
  _RAND_2122 = {2{`RANDOM}};
  i_mmu_dptw_walkReq_vaddr = _RAND_2122[63:0];
  _RAND_2123 = {1{`RANDOM}};
  i_mmu_dptw_asidReq = _RAND_2123[15:0];
  _RAND_2124 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_is_X = _RAND_2124[0:0];
  _RAND_2125 = {2{`RANDOM}};
  i_mmu_dptw_walkRspBits_renew_value = _RAND_2125[63:0];
  _RAND_2126 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_renew_is_giga_page = _RAND_2126[0:0];
  _RAND_2127 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_renew_is_mega_page = _RAND_2127[0:0];
  _RAND_2128 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_renew_asid = _RAND_2128[15:0];
  _RAND_2129 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_renew_vpn_0 = _RAND_2129[8:0];
  _RAND_2130 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_renew_vpn_1 = _RAND_2130[8:0];
  _RAND_2131 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_renew_vpn_2 = _RAND_2131[8:0];
  _RAND_2132 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_is_ptw_fail = _RAND_2132[0:0];
  _RAND_2133 = {1{`RANDOM}};
  i_mmu_dptw_walkRspBits_is_access_fault = _RAND_2133[0:0];
  _RAND_2134 = {1{`RANDOM}};
  i_mmu_dptw_walkRspValid = _RAND_2134[0:0];
  _RAND_2135 = {1{`RANDOM}};
  i_mmu_dptw_ptw_get_valid = _RAND_2135[0:0];
  _RAND_2136 = {1{`RANDOM}};
  i_mmu_dptw_ptw_access_ready = _RAND_2136[0:0];
  _RAND_2137 = {1{`RANDOM}};
  i_mmu_dptw_is_get_reqed = _RAND_2137[0:0];
  _RAND_2138 = {1{`RANDOM}};
  i_mmu_kill_iptw = _RAND_2138[0:0];
  _RAND_2139 = {1{`RANDOM}};
  i_mmu_kill_dptw = _RAND_2139[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [2:0]  io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_b_ready,
  input         io_in_b_valid,
  input  [1:0]  io_in_b_bits_param,
  input  [31:0] io_in_b_bits_address,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [2:0]  io_in_c_bits_size,
  input  [31:0] io_in_c_bits_address,
  input         io_in_c_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [2:0]  io_in_d_bits_source,
  input  [4:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt,
  input         io_in_e_valid,
  input  [4:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 3'h3; // @[Parameters.scala 46:9]
  wire  _source_ok_T_3 = io_in_a_bits_source[2:1] == 2'h0; // @[Parameters.scala 54:32]
  wire  _source_ok_T_8 = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_3 | _source_ok_T_8; // @[Parameters.scala 1125:46]
  wire [10:0] _is_aligned_mask_T_1 = 11'hf << io_in_a_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask = ~_is_aligned_mask_T_1[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_74 = {{28'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_74; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_47 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_65 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire [32:0] _T_70 = $signed(_T_7) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_71 = $signed(_T_70) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_72 = _T_65 & _T_71; // @[Parameters.scala 670:56]
  wire  _T_74 = source_ok & _T_72; // @[Monitor.scala 82:72]
  wire  _T_89 = _source_ok_T_1 & _T_65; // @[Mux.scala 27:73]
  wire  _T_106 = _T_89 & _T_71; // @[Monitor.scala 83:78]
  wire  _T_120 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_124 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_125 = _T_124 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_129 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_133 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_210 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_223 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_245 = io_in_a_bits_size <= 3'h4; // @[Parameters.scala 92:42]
  wire  _T_253 = _T_245 & _T_71; // @[Parameters.scala 670:56]
  wire  _T_264 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_268 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_276 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_305 = source_ok & _T_253; // @[Monitor.scala 115:71]
  wire  _T_323 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_366 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_367 = io_in_a_bits_mask & _T_366; // @[Monitor.scala 127:31]
  wire  _T_368 = _T_367 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_372 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_391 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
  wire  _T_399 = _T_391 & _T_71; // @[Parameters.scala 670:56]
  wire  _T_401 = source_ok & _T_399; // @[Monitor.scala 131:74]
  wire  _T_411 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_419 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_458 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_466 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_505 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_517 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_11 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
  wire  _source_ok_T_12 = io_in_d_bits_source == 3'h3; // @[Parameters.scala 46:9]
  wire  _source_ok_T_14 = io_in_d_bits_source[2:1] == 2'h0; // @[Parameters.scala 54:32]
  wire  _source_ok_T_19 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_11 | _source_ok_T_12 | _source_ok_T_14 | _source_ok_T_19; // @[Parameters.scala 1125:46]
  wire  sink_ok = io_in_d_bits_sink < 5'h16; // @[Monitor.scala 306:31]
  wire  _T_521 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_525 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_529 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_533 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_537 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_541 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_552 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_556 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_569 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_589 = _T_537 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_598 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_615 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_633 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire [32:0] _T_657 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 137:49]
  wire [32:0] _address_ok_T_3 = $signed(_T_657) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _is_aligned_T_1 = io_in_b_bits_address & 32'hf; // @[Edges.scala 20:16]
  wire  is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala 20:24]
  wire  _T_739 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_776 = io_in_b_bits_param == 2'h0; // @[Monitor.scala 182:31]
  wire [10:0] _is_aligned_mask_T_7 = 11'hf << io_in_c_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_76 = {{28'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_76; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala 20:24]
  wire [32:0] _address_ok_T_6 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 137:49]
  wire [32:0] _address_ok_T_8 = $signed(_address_ok_T_6) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_1002 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_1009 = io_in_c_bits_size >= 3'h3; // @[Monitor.scala 245:30]
  wire  _T_1016 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_1020 = ~io_in_c_bits_corrupt; // @[Monitor.scala 248:18]
  wire  _T_1024 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_1042 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_1060 = 3'h4 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_1067 = _T_1060 & _address_ok_T_9; // @[Parameters.scala 670:56]
  wire  _T_1123 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_1200 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_1210 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_1218 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_1232 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  sink_ok_1 = io_in_e_bits_sink < 5'h16; // @[Monitor.scala 364:31]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_beats1_decode = is_aligned_mask[3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala 220:14]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [2:0] source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_1254 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1255 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1259 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1263 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1267 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1271 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _d_first_beats1_decode_T_1 = 11'hf << io_in_d_bits_size; // @[package.scala 234:77]
  wire [3:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  d_first_beats1_decode = _d_first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala 220:14]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [2:0] source_1; // @[Monitor.scala 538:22]
  reg [4:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1278 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1279 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1283 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1287 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1291 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1295 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1299 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  wire  _b_first_T = io_in_b_ready & io_in_b_valid; // @[Decoupled.scala 52:35]
  reg  b_first_counter; // @[Edges.scala 228:27]
  wire  b_first_counter1 = b_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  b_first = ~b_first_counter; // @[Edges.scala 230:25]
  reg [1:0] param_2; // @[Monitor.scala 408:22]
  reg [31:0] address_1; // @[Monitor.scala 411:22]
  wire  _T_1306 = io_in_b_valid & ~b_first; // @[Monitor.scala 412:19]
  wire  _T_1311 = io_in_b_bits_param == param_2; // @[Monitor.scala 414:32]
  wire  _T_1323 = io_in_b_bits_address == address_1; // @[Monitor.scala 417:32]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 52:35]
  wire  c_first_beats1_decode = is_aligned_mask_2[3]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  wire  c_first_beats1 = c_first_beats1_opdata & c_first_beats1_decode; // @[Edges.scala 220:14]
  reg  c_first_counter; // @[Edges.scala 228:27]
  wire  c_first_counter1 = c_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  c_first = ~c_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [2:0] size_3; // @[Monitor.scala 514:22]
  reg [31:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_1330 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_1331 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_1335 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_1339 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_1347 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg [4:0] inflight; // @[Monitor.scala 611:27]
  reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [4:0] _GEN_80 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_80}; // @[Monitor.scala 634:69]
  wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [19:0] _GEN_86 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_86; // @[Monitor.scala 634:97]
  wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
  wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_86; // @[Monitor.scala 638:91]
  wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
  wire  _T_1353 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [7:0] _GEN_27 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1356 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [4:0] _GEN_91 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_91}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [66:0] _GEN_502 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [66:0] _a_opcodes_set_T_1 = _GEN_502 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [66:0] _GEN_503 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [66:0] _a_sizes_set_T_1 = _GEN_503 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [4:0] _T_1358 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1360 = ~_T_1358[0]; // @[Monitor.scala 658:17]
  wire [7:0] _GEN_28 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
  wire [66:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
  wire [66:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1364 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1366 = ~_T_521; // @[Monitor.scala 671:74]
  wire  _T_1367 = io_in_d_valid & d_first_1 & ~_T_521; // @[Monitor.scala 671:71]
  wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [7:0] _GEN_33 = io_in_d_valid & d_first_1 & ~_T_521 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
  wire [78:0] _GEN_504 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [78:0] _d_opcodes_clr_T_5 = _GEN_504 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [7:0] _GEN_34 = _d_first_T & d_first_1 & _T_1366 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
  wire [78:0] _GEN_35 = _d_first_T & d_first_1 & _T_1366 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1353 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [4:0] _T_1377 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1379 = _T_1377[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_1384 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_1385 = io_in_d_bits_opcode == _GEN_44 | _T_1384; // @[Monitor.scala 685:77]
  wire  _T_1389 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_1396 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_1397 = io_in_d_bits_opcode == _GEN_60 | _T_1396; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_95 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1401 = _GEN_95 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1411 = _T_1364 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1366; // @[Monitor.scala 694:116]
  wire  _T_1412 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_1413 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [4:0] a_set_wo_ready = _GEN_27[4:0];
  wire [4:0] d_clr_wo_ready = _GEN_33[4:0];
  wire  _T_1420 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [4:0] a_set = _GEN_28[4:0];
  wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [4:0] d_clr = _GEN_34[4:0];
  wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [19:0] a_opcodes_set = _GEN_31[19:0];
  wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [19:0] d_opcodes_clr = _GEN_35[19:0];
  wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [19:0] a_sizes_set = _GEN_32[19:0];
  wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1429 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [4:0] inflight_1; // @[Monitor.scala 723:35]
  reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  c_first_counter_1; // @[Edges.scala 228:27]
  wire  c_first_counter1_1 = c_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = ~c_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_86; // @[Monitor.scala 747:93]
  wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
  wire  _T_1439 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_1440 = io_in_c_valid & c_first_1 & _T_1439; // @[Monitor.scala 756:37]
  wire [7:0] _GEN_72 = io_in_c_valid & c_first_1 & _T_1439 ? 8'h8 : 8'h0; // @[Monitor.scala 756:71 757:22]
  wire  _T_1446 = _c_first_T & c_first_1 & _T_1439; // @[Monitor.scala 760:38]
  wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [3:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 4'h1; // @[Monitor.scala 763:59]
  wire [3:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_1439 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 760:72 763:28]
  wire [15:0] _GEN_99 = {c_sizes_set_interm, 12'h0}; // @[Monitor.scala 765:52]
  wire [66:0] _c_sizes_set_T_1 = {{51'd0}, _GEN_99}; // @[Monitor.scala 765:52]
  wire [4:0] _T_1447 = {{3'd0}, inflight_1[4:3]}; // @[Monitor.scala 766:26]
  wire  _T_1449 = ~_T_1447[0]; // @[Monitor.scala 766:17]
  wire [7:0] _GEN_73 = _c_first_T & c_first_1 & _T_1439 ? 8'h8 : 8'h0; // @[Monitor.scala 760:72 761:28]
  wire [66:0] _GEN_77 = _c_first_T & c_first_1 & _T_1439 ? _c_sizes_set_T_1 : 67'h0; // @[Monitor.scala 760:72 765:28]
  wire  _T_1453 = io_in_d_valid & d_first_2; // @[Monitor.scala 779:26]
  wire  _T_1455 = io_in_d_valid & d_first_2 & _T_521; // @[Monitor.scala 779:71]
  wire [7:0] _GEN_78 = io_in_d_valid & d_first_2 & _T_521 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 779:89 780:22]
  wire [7:0] _GEN_79 = _d_first_T & d_first_2 & _T_521 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
  wire [78:0] _GEN_81 = _d_first_T & d_first_2 & _T_521 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 786:21]
  wire  _same_cycle_resp_T_8 = 3'h3 == io_in_d_bits_source; // @[Monitor.scala 790:113]
  wire  same_cycle_resp_1 = _T_1440 & 3'h3 == io_in_d_bits_source; // @[Monitor.scala 790:88]
  wire [4:0] _T_1463 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_1465 = _T_1463[0] | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_1469 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1473 = _GEN_95 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_1482 = _T_1453 & c_first_1 & io_in_c_valid & _same_cycle_resp_T_8 & _T_521; // @[Monitor.scala 799:116]
  wire  _T_1484 = _T_1412 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire [4:0] c_set_wo_ready = _GEN_72[4:0];
  wire  _T_1488 = |c_set_wo_ready; // @[Monitor.scala 804:28]
  wire [4:0] d_clr_wo_ready_1 = _GEN_78[4:0];
  wire  _T_1489 = c_set_wo_ready != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire [4:0] c_set = _GEN_73[4:0];
  wire [4:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala 809:35]
  wire [4:0] d_clr_1 = _GEN_79[4:0];
  wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [4:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [19:0] c_sizes_set = _GEN_77[19:0];
  wire [19:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [19:0] d_sizes_clr_1 = _GEN_81[19:0];
  wire [19:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [19:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1498 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [21:0] inflight_2; // @[Monitor.scala 823:27]
  reg  d_first_counter_3; // @[Edges.scala 228:27]
  wire  d_first_counter1_3 = d_first_counter_3 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = ~d_first_counter_3; // @[Edges.scala 230:25]
  wire  _T_1510 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_1511 = _d_first_T & d_first_3 & _T_1510; // @[Monitor.scala 829:38]
  wire [31:0] _d_set_T = 32'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [21:0] _T_1512 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_1514 = ~_T_1512[0]; // @[Monitor.scala 831:14]
  wire [31:0] _GEN_84 = _d_first_T & d_first_3 & _T_1510 ? _d_set_T : 32'h0; // @[Monitor.scala 829:72 830:13]
  wire [31:0] _e_clr_T = 32'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [21:0] d_set = _GEN_84[21:0];
  wire [21:0] _T_1521 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [21:0] _T_1522 = _T_1521 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [31:0] _GEN_85 = io_in_e_valid ? _e_clr_T : 32'h0; // @[Monitor.scala 835:73 836:13]
  wire [21:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [21:0] e_clr = _GEN_85[21:0];
  wire [21:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [21:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= a_first_beats1;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      b_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_b_first_T) begin // @[Edges.scala 234:17]
      if (b_first) begin // @[Edges.scala 235:21]
        b_first_counter <= 1'h0;
      end else begin
        b_first_counter <= b_first_counter1;
      end
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      param_2 <= io_in_b_bits_param; // @[Monitor.scala 421:15]
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      address_1 <= io_in_b_bits_address; // @[Monitor.scala 424:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        c_first_counter <= c_first_beats1;
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 5'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= a_first_beats1;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        c_first_counter_1 <= c_first_beats1;
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= d_first_beats1;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 22'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        d_first_counter_3 <= d_first_beats1;
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_47 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_47 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_47 & ~reset & ~_T_106) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_106 & (io_in_a_valid & _T_47 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_47 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_47 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_47 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_47 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_47 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_47 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_47 & ~reset & ~_T_120) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_120 & (io_in_a_valid & _T_47 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_47 & ~reset & ~_T_125) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_125 & (io_in_a_valid & _T_47 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_47 & ~reset & ~_T_129) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_129 & (io_in_a_valid & _T_47 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_106) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_106 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_120) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_120 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_210) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_210 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_125) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_125 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_129) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_129 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_253) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_253 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_264) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_264 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_129) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_129 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_305) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_305 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_264) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_264 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_305) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_305 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_264) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_264 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_368) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_368 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_372 & ~reset & ~_T_401) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_401 & (io_in_a_valid & _T_372 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_372 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_372 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_372 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_372 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_372 & ~reset & ~_T_411) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_411 & (io_in_a_valid & _T_372 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_372 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_372 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_419 & ~reset & ~_T_401) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_401 & (io_in_a_valid & _T_419 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_419 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_419 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_419 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_419 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_419 & ~reset & ~_T_458) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_458 & (io_in_a_valid & _T_419 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_419 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_419 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_466 & ~reset & ~_T_305) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_305 & (io_in_a_valid & _T_466 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_466 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_466 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_466 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_466 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_466 & ~reset & ~_T_505) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_505 & (io_in_a_valid & _T_466 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_466 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_466 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_466 & ~reset & ~_T_129) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_129 & (io_in_a_valid & _T_466 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_517) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_517 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_T_525) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_525 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_T_529) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_529 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_T_533) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_533 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_T_537) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_537 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_541 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_541 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_541 & _T_2 & ~sink_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~sink_ok & (io_in_d_valid & _T_541 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_541 & _T_2 & ~_T_525) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_525 & (io_in_d_valid & _T_541 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_541 & _T_2 & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (io_in_d_valid & _T_541 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_541 & _T_2 & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (io_in_d_valid & _T_541 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_541 & _T_2 & ~_T_533) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_533 & (io_in_d_valid & _T_541 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_541 & _T_2 & ~_T_537) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_537 & (io_in_d_valid & _T_541 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_569 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_569 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_569 & _T_2 & ~sink_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~sink_ok & (io_in_d_valid & _T_569 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_569 & _T_2 & ~_T_525) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_525 & (io_in_d_valid & _T_569 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_569 & _T_2 & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (io_in_d_valid & _T_569 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_569 & _T_2 & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (io_in_d_valid & _T_569 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_569 & _T_2 & ~_T_589) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_589 & (io_in_d_valid & _T_569 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_569 & _T_2 & ~_T_537) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_537 & (io_in_d_valid & _T_569 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_598 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_598 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_598 & _T_2 & ~_T_529) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_529 & (io_in_d_valid & _T_598 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_598 & _T_2 & ~_T_533) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_533 & (io_in_d_valid & _T_598 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_598 & _T_2 & ~_T_537) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_537 & (io_in_d_valid & _T_598 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_615 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_615 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_615 & _T_2 & ~_T_529) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_529 & (io_in_d_valid & _T_615 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_615 & _T_2 & ~_T_589) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_589 & (io_in_d_valid & _T_615 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_615 & _T_2 & ~_T_537) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_537 & (io_in_d_valid & _T_615 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_633 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_633 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_633 & _T_2 & ~_T_529) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_529 & (io_in_d_valid & _T_633 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_633 & _T_2 & ~_T_533) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_533 & (io_in_d_valid & _T_633 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_633 & _T_2 & ~_T_537) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_537 & (io_in_d_valid & _T_633 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_address_ok_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_address_ok_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~is_aligned_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_T_739) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_739 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_776 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_776 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_776 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1002 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1002 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & _T_1002 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1002 & ~reset & ~_T_1009) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1009 & (io_in_c_valid & _T_1002 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1002 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1002 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1002 & ~reset & ~_T_1016) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1016 & (io_in_c_valid & _T_1002 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1002 & ~reset & ~_T_1020) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1020 & (io_in_c_valid & _T_1002 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1024 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1024 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & _T_1024 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1024 & ~reset & ~_T_1009) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1009 & (io_in_c_valid & _T_1024 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1024 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1024 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1024 & ~reset & ~_T_1016) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1016 & (io_in_c_valid & _T_1024 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1042 & ~reset & ~_T_1067) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1067 & (io_in_c_valid & _T_1042 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1042 & ~reset & ~_T_1067) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1067 & (io_in_c_valid & _T_1042 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & _T_1042 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1042 & ~reset & ~_T_1009) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1009 & (io_in_c_valid & _T_1042 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1042 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1042 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1042 & ~reset & ~_T_1016) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1016 & (io_in_c_valid & _T_1042 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1042 & ~reset & ~_T_1020) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1020 & (io_in_c_valid & _T_1042 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1123 & ~reset & ~_T_1067) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1067 & (io_in_c_valid & _T_1123 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1123 & ~reset & ~_T_1067) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1067 & (io_in_c_valid & _T_1123 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & _T_1123 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1123 & ~reset & ~_T_1009) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1009 & (io_in_c_valid & _T_1123 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1123 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1123 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1123 & ~reset & ~_T_1016) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1016 & (io_in_c_valid & _T_1123 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1200 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1200 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & _T_1200 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1200 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1200 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1200 & ~reset & ~_T_1210) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1210 & (io_in_c_valid & _T_1200 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1200 & ~reset & ~_T_1020) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1020 & (io_in_c_valid & _T_1200 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1218 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1218 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & _T_1218 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1218 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1218 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1218 & ~reset & ~_T_1210) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1210 & (io_in_c_valid & _T_1218 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1232 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & _T_1232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1232 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1232 & ~reset & ~_T_1210) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1210 & (io_in_c_valid & _T_1232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1232 & ~reset & ~_T_1020) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck is corrupt (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1020 & (io_in_c_valid & _T_1232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_e_valid & ~reset & ~sink_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channels carries invalid sink ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~sink_ok_1 & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1254 & ~reset & ~_T_1255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1255 & (_T_1254 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1254 & ~reset & ~_T_1259) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1259 & (_T_1254 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1254 & ~reset & ~_T_1263) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1263 & (_T_1254 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1254 & ~reset & ~_T_1267) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1267 & (_T_1254 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1254 & ~reset & ~_T_1271) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1271 & (_T_1254 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1278 & _T_2 & ~_T_1279) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1279 & (_T_1278 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1278 & _T_2 & ~_T_1283) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1283 & (_T_1278 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1278 & _T_2 & ~_T_1287) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1287 & (_T_1278 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1278 & _T_2 & ~_T_1291) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1291 & (_T_1278 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1278 & _T_2 & ~_T_1295) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1295 & (_T_1278 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1278 & _T_2 & ~_T_1299) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1299 & (_T_1278 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_1306 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1306 & ~reset & ~_T_1311) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel param changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1311 & (_T_1306 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_1306 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_1306 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1306 & ~reset & ~_T_1323) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1323 & (_T_1306 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1330 & ~reset & ~_T_1331) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1331 & (_T_1330 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1330 & ~reset & ~_T_1335) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1335 & (_T_1330 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1330 & ~reset & ~_T_1339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1339 & (_T_1330 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_1330 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1330 & ~reset & ~_T_1347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1347 & (_T_1330 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1356 & ~reset & ~_T_1360) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1360 & (_T_1356 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1367 & _T_2 & ~_T_1379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1379 & (_T_1367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1367 & same_cycle_resp & _T_2 & ~_T_1385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1385 & (_T_1367 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1367 & same_cycle_resp & _T_2 & ~_T_1389) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1389 & (_T_1367 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1367 & ~same_cycle_resp & _T_2 & ~_T_1397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1397 & (_T_1367 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1367 & ~same_cycle_resp & _T_2 & ~_T_1401) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1401 & (_T_1367 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1411 & _T_2 & ~_T_1413) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1413 & (_T_1411 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1420 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1429) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1429 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1446 & ~reset & ~_T_1449) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1449 & (_T_1446 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1455 & _T_2 & ~_T_1465) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1465 & (_T_1455 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1455 & same_cycle_resp_1 & _T_2 & ~_T_1469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1469 & (_T_1455 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1455 & ~same_cycle_resp_1 & _T_2 & ~_T_1473) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1473 & (_T_1455 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1482 & _T_2 & ~_T_1484) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1484 & (_T_1482 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1488 & _T_2 & ~_T_1489) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' and 'D' concurrent, despite minlatency 2 (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1489 & (_T_1488 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1498) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1498 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1511 & _T_2 & ~_T_1514) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1514 & (_T_1511 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_e_valid & ~reset & ~_T_1522[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at Rift2Link.scala:72:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1522[0] & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[4:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  b_first_counter = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  param_2 = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  address_1 = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  c_first_counter = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  opcode_3 = _RAND_17[2:0];
  _RAND_18 = {1{`RANDOM}};
  param_3 = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  size_3 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  address_2 = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  inflight = _RAND_21[4:0];
  _RAND_22 = {1{`RANDOM}};
  inflight_opcodes = _RAND_22[19:0];
  _RAND_23 = {1{`RANDOM}};
  inflight_sizes = _RAND_23[19:0];
  _RAND_24 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  watchdog = _RAND_26[31:0];
  _RAND_27 = {1{`RANDOM}};
  inflight_1 = _RAND_27[4:0];
  _RAND_28 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_28[19:0];
  _RAND_29 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  watchdog_1 = _RAND_31[31:0];
  _RAND_32 = {1{`RANDOM}};
  inflight_2 = _RAND_32[21:0];
  _RAND_33 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_33[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_23(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [4:0]  io_enq_bits_source,
  input  [31:0] io_enq_bits_address,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [4:0]  io_deq_bits_source,
  output [31:0] io_deq_bits_address,
  output [7:0]  io_deq_bits_mask,
  output [63:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [4:0] ram_source [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [4:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [4:0] ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_address [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 275:95]
  reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 275:95]
  reg [63:0] ram_data [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = 3'h4;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = enq_ptr_value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_mask_MPORT_data = 8'hff;
  assign ram_mask_MPORT_addr = enq_ptr_value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = 64'h0;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_corrupt_MPORT_data = 1'h0;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[4:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[7:0];
  _RAND_6 = {2{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[63:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  enq_ptr_value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  deq_ptr_value = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SourceA(
  input         clock,
  input         reset,
  output        io_req_ready,
  input         io_req_valid,
  input  [25:0] io_req_bits_tag,
  input  [1:0]  io_req_bits_set,
  input  [2:0]  io_req_bits_param,
  input  [4:0]  io_req_bits_source,
  input         io_req_bits_block,
  input         io_a_ready,
  output        io_a_valid,
  output [2:0]  io_a_bits_opcode,
  output [2:0]  io_a_bits_param,
  output [2:0]  io_a_bits_size,
  output [4:0]  io_a_bits_source,
  output [31:0] io_a_bits_address,
  output [7:0]  io_a_bits_mask,
  output [63:0] io_a_bits_data,
  output        io_a_bits_corrupt
);
  wire  io_a_q_clock; // @[Decoupled.scala 377:21]
  wire  io_a_q_reset; // @[Decoupled.scala 377:21]
  wire  io_a_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  io_a_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] io_a_q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] io_a_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [4:0] io_a_q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] io_a_q_io_enq_bits_address; // @[Decoupled.scala 377:21]
  wire  io_a_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  io_a_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] io_a_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] io_a_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] io_a_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [4:0] io_a_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] io_a_q_io_deq_bits_address; // @[Decoupled.scala 377:21]
  wire [7:0] io_a_q_io_deq_bits_mask; // @[Decoupled.scala 377:21]
  wire [63:0] io_a_q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  io_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire [31:0] a_bits_address_base = {io_req_bits_tag,io_req_bits_set,4'h0}; // @[Cat.scala 33:92]
  wire [7:0] a_bits_address_lo_lo = {a_bits_address_base[7],a_bits_address_base[6],a_bits_address_base[5],
    a_bits_address_base[4],a_bits_address_base[3],a_bits_address_base[2],a_bits_address_base[1],a_bits_address_base[0]}; // @[Cat.scala 33:92]
  wire [15:0] a_bits_address_lo = {a_bits_address_base[15],a_bits_address_base[14],a_bits_address_base[13],
    a_bits_address_base[12],a_bits_address_base[11],a_bits_address_base[10],a_bits_address_base[9],a_bits_address_base[8
    ],a_bits_address_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] a_bits_address_hi_lo = {a_bits_address_base[23],a_bits_address_base[22],a_bits_address_base[21],
    a_bits_address_base[20],a_bits_address_base[19],a_bits_address_base[18],a_bits_address_base[17],a_bits_address_base[
    16]}; // @[Cat.scala 33:92]
  wire [15:0] a_bits_address_hi = {a_bits_address_base[31],a_bits_address_base[30],a_bits_address_base[29],
    a_bits_address_base[28],a_bits_address_base[27],a_bits_address_base[26],a_bits_address_base[25],a_bits_address_base[
    24],a_bits_address_hi_lo}; // @[Cat.scala 33:92]
  Queue_23 io_a_q ( // @[Decoupled.scala 377:21]
    .clock(io_a_q_clock),
    .reset(io_a_q_reset),
    .io_enq_ready(io_a_q_io_enq_ready),
    .io_enq_valid(io_a_q_io_enq_valid),
    .io_enq_bits_opcode(io_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(io_a_q_io_enq_bits_param),
    .io_enq_bits_source(io_a_q_io_enq_bits_source),
    .io_enq_bits_address(io_a_q_io_enq_bits_address),
    .io_deq_ready(io_a_q_io_deq_ready),
    .io_deq_valid(io_a_q_io_deq_valid),
    .io_deq_bits_opcode(io_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(io_a_q_io_deq_bits_param),
    .io_deq_bits_size(io_a_q_io_deq_bits_size),
    .io_deq_bits_source(io_a_q_io_deq_bits_source),
    .io_deq_bits_address(io_a_q_io_deq_bits_address),
    .io_deq_bits_mask(io_a_q_io_deq_bits_mask),
    .io_deq_bits_data(io_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(io_a_q_io_deq_bits_corrupt)
  );
  assign io_req_ready = io_a_q_io_enq_ready; // @[SourceA.scala 42:15 Decoupled.scala 381:17]
  assign io_a_valid = io_a_q_io_deq_valid; // @[SourceA.scala 43:8]
  assign io_a_bits_opcode = io_a_q_io_deq_bits_opcode; // @[SourceA.scala 43:8]
  assign io_a_bits_param = io_a_q_io_deq_bits_param; // @[SourceA.scala 43:8]
  assign io_a_bits_size = io_a_q_io_deq_bits_size; // @[SourceA.scala 43:8]
  assign io_a_bits_source = io_a_q_io_deq_bits_source; // @[SourceA.scala 43:8]
  assign io_a_bits_address = io_a_q_io_deq_bits_address; // @[SourceA.scala 43:8]
  assign io_a_bits_mask = io_a_q_io_deq_bits_mask; // @[SourceA.scala 43:8]
  assign io_a_bits_data = io_a_q_io_deq_bits_data; // @[SourceA.scala 43:8]
  assign io_a_bits_corrupt = io_a_q_io_deq_bits_corrupt; // @[SourceA.scala 43:8]
  assign io_a_q_clock = clock;
  assign io_a_q_reset = reset;
  assign io_a_q_io_enq_valid = io_req_valid; // @[SourceA.scala 42:15 46:11]
  assign io_a_q_io_enq_bits_opcode = io_req_bits_block ? 3'h6 : 3'h7; // @[SourceA.scala 49:24]
  assign io_a_q_io_enq_bits_param = io_req_bits_param; // @[SourceA.scala 42:15 50:18]
  assign io_a_q_io_enq_bits_source = io_req_bits_source; // @[SourceA.scala 42:15 52:18]
  assign io_a_q_io_enq_bits_address = {a_bits_address_hi,a_bits_address_lo}; // @[Cat.scala 33:92]
  assign io_a_q_io_deq_ready = io_a_ready; // @[SourceA.scala 43:8]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module SourceB(
  input         clock,
  input         reset,
  output        io_req_ready,
  input         io_req_valid,
  input  [2:0]  io_req_bits_param,
  input  [25:0] io_req_bits_tag,
  input  [1:0]  io_req_bits_set,
  input         io_req_bits_clients,
  input         io_b_ready,
  output        io_b_valid,
  output [1:0]  io_b_bits_param,
  output [31:0] io_b_bits_address
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg  remain; // @[SourceB.scala 44:25]
  wire  _T_6 = io_req_ready & io_req_valid; // @[Decoupled.scala 52:35]
  wire  remain_set = _T_6 & io_req_bits_clients; // @[SourceB.scala 60:{26,39}]
  wire  busy = |remain; // @[SourceB.scala 49:26]
  wire  b_valid = busy | io_req_valid; // @[SourceB.scala 66:21]
  wire  _T_7 = io_b_ready & b_valid; // @[Decoupled.scala 52:35]
  wire  todo = busy ? remain : io_req_bits_clients; // @[SourceB.scala 50:19]
  wire [1:0] _next_T_1 = {todo, 1'h0}; // @[SourceB.scala 51:31]
  wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala 51:16]
  wire [1:0] _GEN_5 = {{1'd0}, todo}; // @[SourceB.scala 51:37]
  wire [1:0] next = _next_T_2 & _GEN_5; // @[SourceB.scala 51:37]
  wire [1:0] _GEN_1 = _T_7 ? next : 2'h0; // @[SourceB.scala 67:{21,34}]
  wire  remain_clr = _GEN_1[0];
  wire  _T_4 = ~reset; // @[SourceB.scala 57:12]
  wire  _io_req_ready_T = ~busy; // @[SourceB.scala 59:21]
  reg [25:0] tag_r; // @[Reg.scala 19:16]
  wire [25:0] tag = _io_req_ready_T ? io_req_bits_tag : tag_r; // @[SourceB.scala 70:18]
  reg [1:0] set_r; // @[Reg.scala 19:16]
  wire [1:0] set = _io_req_ready_T ? io_req_bits_set : set_r; // @[SourceB.scala 71:18]
  reg [2:0] param_r; // @[Reg.scala 19:16]
  wire [2:0] param = _io_req_ready_T ? io_req_bits_param : param_r; // @[SourceB.scala 72:20]
  wire [31:0] b_bits_address_base = {tag,set,4'h0}; // @[Cat.scala 33:92]
  wire [7:0] b_bits_address_lo_lo = {b_bits_address_base[7],b_bits_address_base[6],b_bits_address_base[5],
    b_bits_address_base[4],b_bits_address_base[3],b_bits_address_base[2],b_bits_address_base[1],b_bits_address_base[0]}; // @[Cat.scala 33:92]
  wire [15:0] b_bits_address_lo = {b_bits_address_base[15],b_bits_address_base[14],b_bits_address_base[13],
    b_bits_address_base[12],b_bits_address_base[11],b_bits_address_base[10],b_bits_address_base[9],b_bits_address_base[8
    ],b_bits_address_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] b_bits_address_hi_lo = {b_bits_address_base[23],b_bits_address_base[22],b_bits_address_base[21],
    b_bits_address_base[20],b_bits_address_base[19],b_bits_address_base[18],b_bits_address_base[17],b_bits_address_base[
    16]}; // @[Cat.scala 33:92]
  wire [15:0] b_bits_address_hi = {b_bits_address_base[31],b_bits_address_base[30],b_bits_address_base[29],
    b_bits_address_base[28],b_bits_address_base[27],b_bits_address_base[26],b_bits_address_base[25],b_bits_address_base[
    24],b_bits_address_hi_lo}; // @[Cat.scala 33:92]
  assign io_req_ready = ~busy; // @[SourceB.scala 59:21]
  assign io_b_valid = busy | io_req_valid; // @[SourceB.scala 66:21]
  assign io_b_bits_param = param[1:0]; // @[SourceB.scala 63:17 75:20]
  assign io_b_bits_address = {b_bits_address_hi,b_bits_address_lo}; // @[Cat.scala 33:92]
  always @(posedge clock) begin
    if (reset) begin // @[SourceB.scala 44:25]
      remain <= 1'h0; // @[SourceB.scala 44:25]
    end else begin
      remain <= (remain | remain_set) & ~remain_clr; // @[SourceB.scala 47:12]
    end
    if (_T_6) begin // @[Reg.scala 20:18]
      tag_r <= io_req_bits_tag; // @[Reg.scala 20:22]
    end
    if (_T_6) begin // @[Reg.scala 20:18]
      set_r <= io_req_bits_set; // @[Reg.scala 20:22]
    end
    if (_T_6) begin // @[Reg.scala 20:18]
      param_r <= io_req_bits_param; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_req_valid | io_req_bits_clients)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at SourceB.scala:57 assert (!io.req.valid || io.req.bits.clients =/= UInt(0))\n"); // @[SourceB.scala 57:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_req_valid | io_req_bits_clients) & ~reset) begin
          $fatal; // @[SourceB.scala 57:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_4) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_4) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_4) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  remain = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  tag_r = _RAND_1[25:0];
  _RAND_2 = {1{`RANDOM}};
  set_r = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  param_r = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module QueueCompatibility(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [4:0]  io_enq_bits_source,
  input  [31:0] io_enq_bits_address,
  input  [63:0] io_enq_bits_data,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [4:0]  io_deq_bits_source,
  output [31:0] io_deq_bits_address,
  output [63:0] io_deq_bits_data,
  output        io_deq_bits_corrupt,
  output [2:0]  io_count
);
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_9;
  reg [63:0] _RAND_11;
  reg [31:0] _RAND_13;
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_8;
  reg [63:0] _RAND_10;
  reg [31:0] _RAND_12;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:5]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_param [0:5]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:5]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [4:0] ram_source [0:5]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [2:0] ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [4:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [4:0] ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_address [0:5]; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [2:0] ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_address_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 275:95]
  reg [63:0] ram_data [0:5]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [2:0] ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:5]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [2:0] ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] enq_ptr_value; // @[Counter.scala 61:40]
  reg [2:0] deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  wrap = enq_ptr_value == 3'h5; // @[Counter.scala 73:24]
  wire [2:0] _value_T_1 = enq_ptr_value + 3'h1; // @[Counter.scala 77:24]
  wire  wrap_1 = deq_ptr_value == 3'h5; // @[Counter.scala 73:24]
  wire [2:0] _value_T_3 = deq_ptr_value + 3'h1; // @[Counter.scala 77:24]
  wire [2:0] ptr_diff = enq_ptr_value - deq_ptr_value; // @[Decoupled.scala 328:32]
  wire [2:0] _io_count_T = maybe_full ? 3'h6 : 3'h0; // @[Decoupled.scala 335:10]
  wire [2:0] _io_count_T_3 = 3'h6 + ptr_diff; // @[Decoupled.scala 336:57]
  wire [2:0] _io_count_T_4 = deq_ptr_value > enq_ptr_value ? _io_count_T_3 : ptr_diff; // @[Decoupled.scala 336:10]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `else
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode_io_deq_bits_MPORT_addr >= 3'h6 ? _RAND_1[2:0] :
    ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `else
  assign ram_param_io_deq_bits_MPORT_data = ram_param_io_deq_bits_MPORT_addr >= 3'h6 ? _RAND_3[2:0] :
    ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `else
  assign ram_size_io_deq_bits_MPORT_data = ram_size_io_deq_bits_MPORT_addr >= 3'h6 ? _RAND_5[2:0] :
    ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign ram_size_MPORT_data = 3'h4;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `else
  assign ram_source_io_deq_bits_MPORT_data = ram_source_io_deq_bits_MPORT_addr >= 3'h6 ? _RAND_7[4:0] :
    ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = deq_ptr_value;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `else
  assign ram_address_io_deq_bits_MPORT_data = ram_address_io_deq_bits_MPORT_addr >= 3'h6 ? _RAND_9[31:0] :
    ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = enq_ptr_value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `else
  assign ram_data_io_deq_bits_MPORT_data = ram_data_io_deq_bits_MPORT_addr >= 3'h6 ? _RAND_11[63:0] :
    ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `else
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt_io_deq_bits_MPORT_addr >= 3'h6 ? _RAND_13[0:0] :
    ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign ram_corrupt_MPORT_data = 1'h0;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_count = ptr_match ? _io_count_T : _io_count_T_4; // @[Decoupled.scala 333:20]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 3'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      if (wrap) begin // @[Counter.scala 87:20]
        enq_ptr_value <= 3'h0; // @[Counter.scala 87:28]
      end else begin
        enq_ptr_value <= _value_T_1; // @[Counter.scala 77:15]
      end
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 3'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      if (wrap_1) begin // @[Counter.scala 87:20]
        deq_ptr_value <= 3'h0; // @[Counter.scala 87:28]
      end else begin
        deq_ptr_value <= _value_T_3; // @[Counter.scala 77:15]
      end
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  _RAND_1 = {1{`RANDOM}};
  _RAND_3 = {1{`RANDOM}};
  _RAND_5 = {1{`RANDOM}};
  _RAND_7 = {1{`RANDOM}};
  _RAND_9 = {1{`RANDOM}};
  _RAND_11 = {2{`RANDOM}};
  _RAND_13 = {1{`RANDOM}};
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 6; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 6; initvar = initvar+1)
    ram_param[initvar] = _RAND_2[2:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 6; initvar = initvar+1)
    ram_size[initvar] = _RAND_4[2:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 6; initvar = initvar+1)
    ram_source[initvar] = _RAND_6[4:0];
  _RAND_8 = {1{`RANDOM}};
  for (initvar = 0; initvar < 6; initvar = initvar+1)
    ram_address[initvar] = _RAND_8[31:0];
  _RAND_10 = {2{`RANDOM}};
  for (initvar = 0; initvar < 6; initvar = initvar+1)
    ram_data[initvar] = _RAND_10[63:0];
  _RAND_12 = {1{`RANDOM}};
  for (initvar = 0; initvar < 6; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_12[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_14 = {1{`RANDOM}};
  enq_ptr_value = _RAND_14[2:0];
  _RAND_15 = {1{`RANDOM}};
  deq_ptr_value = _RAND_15[2:0];
  _RAND_16 = {1{`RANDOM}};
  maybe_full = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SourceC(
  input         clock,
  input         reset,
  output        io_req_ready,
  input         io_req_valid,
  input  [2:0]  io_req_bits_opcode,
  input  [2:0]  io_req_bits_param,
  input  [4:0]  io_req_bits_source,
  input  [25:0] io_req_bits_tag,
  input  [1:0]  io_req_bits_set,
  input         io_req_bits_way,
  input         io_req_bits_dirty,
  input         io_c_ready,
  output        io_c_valid,
  output [2:0]  io_c_bits_opcode,
  output [2:0]  io_c_bits_param,
  output [2:0]  io_c_bits_size,
  output [4:0]  io_c_bits_source,
  output [31:0] io_c_bits_address,
  output [63:0] io_c_bits_data,
  output        io_c_bits_corrupt,
  input         io_bs_adr_ready,
  output        io_bs_adr_valid,
  output        io_bs_adr_bits_way,
  output [1:0]  io_bs_adr_bits_set,
  output        io_bs_adr_bits_beat,
  input  [63:0] io_bs_dat_data,
  output [1:0]  io_evict_req_set,
  output        io_evict_req_way,
  input         io_evict_safe
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
`endif // RANDOMIZE_REG_INIT
  wire  queue_clock; // @[SourceC.scala 53:21]
  wire  queue_reset; // @[SourceC.scala 53:21]
  wire  queue_io_enq_ready; // @[SourceC.scala 53:21]
  wire  queue_io_enq_valid; // @[SourceC.scala 53:21]
  wire [2:0] queue_io_enq_bits_opcode; // @[SourceC.scala 53:21]
  wire [2:0] queue_io_enq_bits_param; // @[SourceC.scala 53:21]
  wire [4:0] queue_io_enq_bits_source; // @[SourceC.scala 53:21]
  wire [31:0] queue_io_enq_bits_address; // @[SourceC.scala 53:21]
  wire [63:0] queue_io_enq_bits_data; // @[SourceC.scala 53:21]
  wire  queue_io_deq_ready; // @[SourceC.scala 53:21]
  wire  queue_io_deq_valid; // @[SourceC.scala 53:21]
  wire [2:0] queue_io_deq_bits_opcode; // @[SourceC.scala 53:21]
  wire [2:0] queue_io_deq_bits_param; // @[SourceC.scala 53:21]
  wire [2:0] queue_io_deq_bits_size; // @[SourceC.scala 53:21]
  wire [4:0] queue_io_deq_bits_source; // @[SourceC.scala 53:21]
  wire [31:0] queue_io_deq_bits_address; // @[SourceC.scala 53:21]
  wire [63:0] queue_io_deq_bits_data; // @[SourceC.scala 53:21]
  wire  queue_io_deq_bits_corrupt; // @[SourceC.scala 53:21]
  wire [2:0] queue_io_count; // @[SourceC.scala 53:21]
  reg [2:0] fill; // @[SourceC.scala 57:21]
  reg  room; // @[SourceC.scala 58:21]
  wire  _T = queue_io_enq_ready & queue_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _T_1 = queue_io_deq_ready & queue_io_deq_valid; // @[Decoupled.scala 52:35]
  wire [2:0] _fill_T_2 = _T ? 3'h1 : 3'h7; // @[SourceC.scala 60:23]
  wire [2:0] _fill_T_4 = fill + _fill_T_2; // @[SourceC.scala 60:18]
  wire  _GEN_1 = _T != _T_1 ? fill == 3'h0 | (fill == 3'h1 | fill == 3'h2) & ~_T : room; // @[SourceC.scala 59:54 61:10 58:21]
  wire  _T_6 = ~reset; // @[SourceC.scala 63:10]
  reg  busy; // @[SourceC.scala 65:21]
  reg  beat; // @[SourceC.scala 66:21]
  wire  last = &beat; // @[SourceC.scala 67:19]
  wire  _req_T = ~busy; // @[SourceC.scala 68:18]
  wire  _req_T_2 = ~busy & io_req_valid; // @[SourceC.scala 68:67]
  reg [2:0] req_r_opcode; // @[Reg.scala 19:16]
  reg [2:0] req_r_param; // @[Reg.scala 19:16]
  reg [4:0] req_r_source; // @[Reg.scala 19:16]
  reg [25:0] req_r_tag; // @[Reg.scala 19:16]
  reg [1:0] req_r_set; // @[Reg.scala 19:16]
  reg  req_r_way; // @[Reg.scala 19:16]
  wire  _want_data_T_1 = io_req_valid & room & io_req_bits_dirty; // @[SourceC.scala 69:49]
  wire  want_data = busy | io_req_valid & room & io_req_bits_dirty; // @[SourceC.scala 69:24]
  wire  _GEN_9 = _want_data_T_1 | busy; // @[SourceC.scala 65:21 86:{52,59}]
  wire  _T_16 = io_bs_adr_ready & io_bs_adr_valid; // @[Decoupled.scala 52:35]
  wire  _s2_latch_T_1 = io_req_ready & io_req_valid; // @[Decoupled.scala 52:35]
  wire  s2_latch = want_data ? _T_16 : _s2_latch_T_1; // @[SourceC.scala 92:21]
  reg  s2_valid; // @[SourceC.scala 93:25]
  reg [2:0] s2_req_opcode; // @[Reg.scala 19:16]
  reg [2:0] s2_req_param; // @[Reg.scala 19:16]
  reg [4:0] s2_req_source; // @[Reg.scala 19:16]
  reg [25:0] s2_req_tag; // @[Reg.scala 19:16]
  reg [1:0] s2_req_set; // @[Reg.scala 19:16]
  reg  s3_valid; // @[SourceC.scala 99:25]
  reg [2:0] s3_req_opcode; // @[Reg.scala 19:16]
  reg [2:0] s3_req_param; // @[Reg.scala 19:16]
  reg [4:0] s3_req_source; // @[Reg.scala 19:16]
  reg [25:0] s3_req_tag; // @[Reg.scala 19:16]
  reg [1:0] s3_req_set; // @[Reg.scala 19:16]
  wire [31:0] c_bits_address_base = {s3_req_tag,s3_req_set,4'h0}; // @[Cat.scala 33:92]
  wire [7:0] c_bits_address_lo_lo = {c_bits_address_base[7],c_bits_address_base[6],c_bits_address_base[5],
    c_bits_address_base[4],c_bits_address_base[3],c_bits_address_base[2],c_bits_address_base[1],c_bits_address_base[0]}; // @[Cat.scala 33:92]
  wire [15:0] c_bits_address_lo = {c_bits_address_base[15],c_bits_address_base[14],c_bits_address_base[13],
    c_bits_address_base[12],c_bits_address_base[11],c_bits_address_base[10],c_bits_address_base[9],c_bits_address_base[8
    ],c_bits_address_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] c_bits_address_hi_lo = {c_bits_address_base[23],c_bits_address_base[22],c_bits_address_base[21],
    c_bits_address_base[20],c_bits_address_base[19],c_bits_address_base[18],c_bits_address_base[17],c_bits_address_base[
    16]}; // @[Cat.scala 33:92]
  wire [15:0] c_bits_address_hi = {c_bits_address_base[31],c_bits_address_base[30],c_bits_address_base[29],
    c_bits_address_base[28],c_bits_address_base[27],c_bits_address_base[26],c_bits_address_base[25],c_bits_address_base[
    24],c_bits_address_hi_lo}; // @[Cat.scala 33:92]
  wire  c_ready = queue_io_enq_ready; // @[SourceC.scala 104:15 118:16]
  QueueCompatibility queue ( // @[SourceC.scala 53:21]
    .clock(queue_clock),
    .reset(queue_reset),
    .io_enq_ready(queue_io_enq_ready),
    .io_enq_valid(queue_io_enq_valid),
    .io_enq_bits_opcode(queue_io_enq_bits_opcode),
    .io_enq_bits_param(queue_io_enq_bits_param),
    .io_enq_bits_source(queue_io_enq_bits_source),
    .io_enq_bits_address(queue_io_enq_bits_address),
    .io_enq_bits_data(queue_io_enq_bits_data),
    .io_deq_ready(queue_io_deq_ready),
    .io_deq_valid(queue_io_deq_valid),
    .io_deq_bits_opcode(queue_io_deq_bits_opcode),
    .io_deq_bits_param(queue_io_deq_bits_param),
    .io_deq_bits_size(queue_io_deq_bits_size),
    .io_deq_bits_source(queue_io_deq_bits_source),
    .io_deq_bits_address(queue_io_deq_bits_address),
    .io_deq_bits_data(queue_io_deq_bits_data),
    .io_deq_bits_corrupt(queue_io_deq_bits_corrupt),
    .io_count(queue_io_count)
  );
  assign io_req_ready = _req_T & room; // @[SourceC.scala 71:25]
  assign io_c_valid = queue_io_deq_valid; // @[SourceC.scala 119:8]
  assign io_c_bits_opcode = queue_io_deq_bits_opcode; // @[SourceC.scala 119:8]
  assign io_c_bits_param = queue_io_deq_bits_param; // @[SourceC.scala 119:8]
  assign io_c_bits_size = queue_io_deq_bits_size; // @[SourceC.scala 119:8]
  assign io_c_bits_source = queue_io_deq_bits_source; // @[SourceC.scala 119:8]
  assign io_c_bits_address = queue_io_deq_bits_address; // @[SourceC.scala 119:8]
  assign io_c_bits_data = queue_io_deq_bits_data; // @[SourceC.scala 119:8]
  assign io_c_bits_corrupt = queue_io_deq_bits_corrupt; // @[SourceC.scala 119:8]
  assign io_bs_adr_valid = (|beat | io_evict_safe) & want_data; // @[SourceC.scala 76:50]
  assign io_bs_adr_bits_way = ~busy ? io_req_bits_way : req_r_way; // @[SourceC.scala 68:17]
  assign io_bs_adr_bits_set = ~busy ? io_req_bits_set : req_r_set; // @[SourceC.scala 68:17]
  assign io_bs_adr_bits_beat = beat; // @[SourceC.scala 80:23]
  assign io_evict_req_set = ~busy ? io_req_bits_set : req_r_set; // @[SourceC.scala 68:17]
  assign io_evict_req_way = ~busy ? io_req_bits_way : req_r_way; // @[SourceC.scala 68:17]
  assign queue_clock = clock;
  assign queue_reset = reset;
  assign queue_io_enq_valid = s3_valid; // @[SourceC.scala 104:15 105:18]
  assign queue_io_enq_bits_opcode = s3_req_opcode; // @[SourceC.scala 104:15 106:18]
  assign queue_io_enq_bits_param = s3_req_param; // @[SourceC.scala 104:15 107:18]
  assign queue_io_enq_bits_source = s3_req_source; // @[SourceC.scala 104:15 109:18]
  assign queue_io_enq_bits_address = {c_bits_address_hi,c_bits_address_lo}; // @[Cat.scala 33:92]
  assign queue_io_enq_bits_data = io_bs_dat_data; // @[SourceC.scala 104:15 111:18]
  assign queue_io_deq_ready = io_c_ready; // @[SourceC.scala 119:8]
  always @(posedge clock) begin
    if (reset) begin // @[SourceC.scala 57:21]
      fill <= 3'h0; // @[SourceC.scala 57:21]
    end else if (_T != _T_1) begin // @[SourceC.scala 59:54]
      fill <= _fill_T_4; // @[SourceC.scala 60:10]
    end
    room <= reset | _GEN_1; // @[SourceC.scala 58:{21,21}]
    if (reset) begin // @[SourceC.scala 65:21]
      busy <= 1'h0; // @[SourceC.scala 65:21]
    end else if (_T_16) begin // @[SourceC.scala 87:27]
      if (last) begin // @[SourceC.scala 88:17]
        busy <= 1'h0; // @[SourceC.scala 88:24]
      end else begin
        busy <= _GEN_9;
      end
    end else begin
      busy <= _GEN_9;
    end
    if (reset) begin // @[SourceC.scala 66:21]
      beat <= 1'h0; // @[SourceC.scala 66:21]
    end else if (_T_16) begin // @[SourceC.scala 87:27]
      beat <= beat + 1'h1; // @[SourceC.scala 89:10]
    end
    if (_req_T_2) begin // @[Reg.scala 20:18]
      req_r_opcode <= io_req_bits_opcode; // @[Reg.scala 20:22]
    end
    if (_req_T_2) begin // @[Reg.scala 20:18]
      req_r_param <= io_req_bits_param; // @[Reg.scala 20:22]
    end
    if (_req_T_2) begin // @[Reg.scala 20:18]
      req_r_source <= io_req_bits_source; // @[Reg.scala 20:22]
    end
    if (_req_T_2) begin // @[Reg.scala 20:18]
      req_r_tag <= io_req_bits_tag; // @[Reg.scala 20:22]
    end
    if (_req_T_2) begin // @[Reg.scala 20:18]
      req_r_set <= io_req_bits_set; // @[Reg.scala 20:22]
    end
    if (_req_T_2) begin // @[Reg.scala 20:18]
      req_r_way <= io_req_bits_way; // @[Reg.scala 20:22]
    end
    if (want_data) begin // @[SourceC.scala 92:21]
      s2_valid <= _T_16;
    end else begin
      s2_valid <= _s2_latch_T_1;
    end
    if (s2_latch) begin // @[Reg.scala 20:18]
      if (~busy) begin // @[SourceC.scala 68:17]
        s2_req_opcode <= io_req_bits_opcode;
      end else begin
        s2_req_opcode <= req_r_opcode;
      end
    end
    if (s2_latch) begin // @[Reg.scala 20:18]
      if (~busy) begin // @[SourceC.scala 68:17]
        s2_req_param <= io_req_bits_param;
      end else begin
        s2_req_param <= req_r_param;
      end
    end
    if (s2_latch) begin // @[Reg.scala 20:18]
      if (~busy) begin // @[SourceC.scala 68:17]
        s2_req_source <= io_req_bits_source;
      end else begin
        s2_req_source <= req_r_source;
      end
    end
    if (s2_latch) begin // @[Reg.scala 20:18]
      if (~busy) begin // @[SourceC.scala 68:17]
        s2_req_tag <= io_req_bits_tag;
      end else begin
        s2_req_tag <= req_r_tag;
      end
    end
    if (s2_latch) begin // @[Reg.scala 20:18]
      if (~busy) begin // @[SourceC.scala 68:17]
        s2_req_set <= io_req_bits_set;
      end else begin
        s2_req_set <= req_r_set;
      end
    end
    s3_valid <= s2_valid; // @[SourceC.scala 99:25]
    if (s2_valid) begin // @[Reg.scala 20:18]
      s3_req_opcode <= s2_req_opcode; // @[Reg.scala 20:22]
    end
    if (s2_valid) begin // @[Reg.scala 20:18]
      s3_req_param <= s2_req_param; // @[Reg.scala 20:22]
    end
    if (s2_valid) begin // @[Reg.scala 20:18]
      s3_req_source <= s2_req_source; // @[Reg.scala 20:22]
    end
    if (s2_valid) begin // @[Reg.scala 20:18]
      s3_req_tag <= s2_req_tag; // @[Reg.scala 20:22]
    end
    if (s2_valid) begin // @[Reg.scala 20:18]
      s3_req_set <= s2_req_set; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(room == queue_io_count <= 3'h1)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at SourceC.scala:63 assert (room === queue.io.count <= UInt(1))\n"
            ); // @[SourceC.scala 63:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(room == queue_io_count <= 3'h1) & ~reset) begin
          $fatal; // @[SourceC.scala 63:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_6) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_6) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_6) begin
          $fatal; // @[Parameters.scala 219:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & ~(~s3_valid | c_ready)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at SourceC.scala:115 assert(!c.valid || c.ready)\n"); // @[SourceC.scala 115:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~s3_valid | c_ready) & _T_6) begin
          $fatal; // @[SourceC.scala 115:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  fill = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  room = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  busy = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  beat = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  req_r_opcode = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  req_r_param = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  req_r_source = _RAND_6[4:0];
  _RAND_7 = {1{`RANDOM}};
  req_r_tag = _RAND_7[25:0];
  _RAND_8 = {1{`RANDOM}};
  req_r_set = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  req_r_way = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  s2_valid = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  s2_req_opcode = _RAND_11[2:0];
  _RAND_12 = {1{`RANDOM}};
  s2_req_param = _RAND_12[2:0];
  _RAND_13 = {1{`RANDOM}};
  s2_req_source = _RAND_13[4:0];
  _RAND_14 = {1{`RANDOM}};
  s2_req_tag = _RAND_14[25:0];
  _RAND_15 = {1{`RANDOM}};
  s2_req_set = _RAND_15[1:0];
  _RAND_16 = {1{`RANDOM}};
  s3_valid = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  s3_req_opcode = _RAND_17[2:0];
  _RAND_18 = {1{`RANDOM}};
  s3_req_param = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  s3_req_source = _RAND_19[4:0];
  _RAND_20 = {1{`RANDOM}};
  s3_req_tag = _RAND_20[25:0];
  _RAND_21 = {1{`RANDOM}};
  s3_req_set = _RAND_21[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module QueueCompatibility_1(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [63:0] io_enq_bits_data,
  input         io_deq_ready,
  output        io_deq_valid,
  output [63:0] io_deq_bits_data
);
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [63:0] _RAND_1;
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] ram_data [0:2]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [1:0] ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] enq_ptr_value; // @[Counter.scala 61:40]
  reg [1:0] deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  wrap = enq_ptr_value == 2'h2; // @[Counter.scala 73:24]
  wire [1:0] _value_T_1 = enq_ptr_value + 2'h1; // @[Counter.scala 77:24]
  wire  _GEN_14 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_14 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  wrap_1 = deq_ptr_value == 2'h2; // @[Counter.scala 73:24]
  wire [1:0] _value_T_3 = deq_ptr_value + 2'h1; // @[Counter.scala 77:24]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `else
  assign ram_data_io_deq_bits_MPORT_data = ram_data_io_deq_bits_MPORT_addr >= 2'h3 ? _RAND_1[63:0] :
    ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = empty ? _GEN_14 : _do_enq_T;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_data = empty ? io_enq_bits_data : ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 2'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      if (wrap) begin // @[Counter.scala 87:20]
        enq_ptr_value <= 2'h0; // @[Counter.scala 87:28]
      end else begin
        enq_ptr_value <= _value_T_1; // @[Counter.scala 77:15]
      end
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 2'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      if (wrap_1) begin // @[Counter.scala 87:20]
        deq_ptr_value <= 2'h0; // @[Counter.scala 87:28]
      end else begin
        deq_ptr_value <= _value_T_3; // @[Counter.scala 77:15]
      end
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  _RAND_1 = {2{`RANDOM}};
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {2{`RANDOM}};
  for (initvar = 0; initvar < 3; initvar = initvar+1)
    ram_data[initvar] = _RAND_0[63:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  enq_ptr_value = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  deq_ptr_value = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  maybe_full = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Atomics(
  input         io_write,
  input  [2:0]  io_a_opcode,
  input  [2:0]  io_a_param,
  input  [7:0]  io_a_mask,
  input  [63:0] io_a_data,
  input  [63:0] io_data_in,
  output [63:0] io_data_out
);
  wire  adder = io_a_param[2]; // @[Atomics.scala 19:28]
  wire  unsigned_ = io_a_param[1]; // @[Atomics.scala 20:28]
  wire  take_max = io_a_param[0]; // @[Atomics.scala 21:28]
  wire [7:0] _signBit_T = ~io_a_mask; // @[Atomics.scala 23:42]
  wire [7:0] _signBit_T_2 = {1'h1,_signBit_T[7:1]}; // @[Cat.scala 33:92]
  wire [7:0] signBit = io_a_mask & _signBit_T_2; // @[Atomics.scala 23:27]
  wire [63:0] _inv_d_T = ~io_data_in; // @[Atomics.scala 24:38]
  wire [63:0] inv_d = adder ? io_data_in : _inv_d_T; // @[Atomics.scala 24:18]
  wire [7:0] _sum_T_9 = io_a_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_11 = io_a_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_13 = io_a_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_15 = io_a_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_17 = io_a_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_19 = io_a_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_21 = io_a_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_23 = io_a_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _sum_T_24 = {_sum_T_23,_sum_T_21,_sum_T_19,_sum_T_17,_sum_T_15,_sum_T_13,_sum_T_11,_sum_T_9}; // @[Cat.scala 33:92]
  wire [63:0] _sum_T_25 = _sum_T_24 & io_a_data; // @[Atomics.scala 25:44]
  wire [63:0] sum = _sum_T_25 + inv_d; // @[Atomics.scala 25:57]
  wire [7:0] _sign_a_T_64 = {io_a_data[63],io_a_data[55],io_a_data[47],io_a_data[39],io_a_data[31],io_a_data[23],
    io_a_data[15],io_a_data[7]}; // @[Cat.scala 33:92]
  wire [7:0] _sign_a_T_65 = _sign_a_T_64 & signBit; // @[Atomics.scala 26:83]
  wire  sign_a = |_sign_a_T_65; // @[Atomics.scala 26:97]
  wire [7:0] _sign_d_T_64 = {io_data_in[63],io_data_in[55],io_data_in[47],io_data_in[39],io_data_in[31],io_data_in[23],
    io_data_in[15],io_data_in[7]}; // @[Cat.scala 33:92]
  wire [7:0] _sign_d_T_65 = _sign_d_T_64 & signBit; // @[Atomics.scala 26:83]
  wire  sign_d = |_sign_d_T_65; // @[Atomics.scala 26:97]
  wire [7:0] _sign_s_T_64 = {sum[63],sum[55],sum[47],sum[39],sum[31],sum[23],sum[15],sum[7]}; // @[Cat.scala 33:92]
  wire [7:0] _sign_s_T_65 = _sign_s_T_64 & signBit; // @[Atomics.scala 26:83]
  wire  sign_s = |_sign_s_T_65; // @[Atomics.scala 26:97]
  wire  a_bigger_uneq = unsigned_ == sign_a; // @[Atomics.scala 30:32]
  wire  a_bigger = sign_a == sign_d ? ~sign_s : a_bigger_uneq; // @[Atomics.scala 31:21]
  wire  pick_a = take_max == a_bigger; // @[Atomics.scala 32:25]
  wire [1:0] _logical_T_128 = {io_a_data[0],io_data_in[0]}; // @[Cat.scala 33:92]
  wire [3:0] _GEN_1 = 2'h1 == io_a_param[1:0] ? 4'he : 4'h6; // @[Atomics.scala 42:{8,8}]
  wire [3:0] _GEN_2 = 2'h2 == io_a_param[1:0] ? 4'h8 : _GEN_1; // @[Atomics.scala 42:{8,8}]
  wire [3:0] _GEN_3 = 2'h3 == io_a_param[1:0] ? 4'hc : _GEN_2; // @[Atomics.scala 42:{8,8}]
  wire [3:0] _logical_T_129 = _GEN_3 >> _logical_T_128; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_131 = {io_a_data[1],io_data_in[1]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_132 = _GEN_3 >> _logical_T_131; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_134 = {io_a_data[2],io_data_in[2]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_135 = _GEN_3 >> _logical_T_134; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_137 = {io_a_data[3],io_data_in[3]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_138 = _GEN_3 >> _logical_T_137; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_140 = {io_a_data[4],io_data_in[4]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_141 = _GEN_3 >> _logical_T_140; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_143 = {io_a_data[5],io_data_in[5]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_144 = _GEN_3 >> _logical_T_143; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_146 = {io_a_data[6],io_data_in[6]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_147 = _GEN_3 >> _logical_T_146; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_149 = {io_a_data[7],io_data_in[7]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_150 = _GEN_3 >> _logical_T_149; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_152 = {io_a_data[8],io_data_in[8]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_153 = _GEN_3 >> _logical_T_152; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_155 = {io_a_data[9],io_data_in[9]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_156 = _GEN_3 >> _logical_T_155; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_158 = {io_a_data[10],io_data_in[10]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_159 = _GEN_3 >> _logical_T_158; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_161 = {io_a_data[11],io_data_in[11]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_162 = _GEN_3 >> _logical_T_161; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_164 = {io_a_data[12],io_data_in[12]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_165 = _GEN_3 >> _logical_T_164; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_167 = {io_a_data[13],io_data_in[13]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_168 = _GEN_3 >> _logical_T_167; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_170 = {io_a_data[14],io_data_in[14]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_171 = _GEN_3 >> _logical_T_170; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_173 = {io_a_data[15],io_data_in[15]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_174 = _GEN_3 >> _logical_T_173; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_176 = {io_a_data[16],io_data_in[16]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_177 = _GEN_3 >> _logical_T_176; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_179 = {io_a_data[17],io_data_in[17]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_180 = _GEN_3 >> _logical_T_179; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_182 = {io_a_data[18],io_data_in[18]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_183 = _GEN_3 >> _logical_T_182; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_185 = {io_a_data[19],io_data_in[19]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_186 = _GEN_3 >> _logical_T_185; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_188 = {io_a_data[20],io_data_in[20]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_189 = _GEN_3 >> _logical_T_188; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_191 = {io_a_data[21],io_data_in[21]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_192 = _GEN_3 >> _logical_T_191; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_194 = {io_a_data[22],io_data_in[22]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_195 = _GEN_3 >> _logical_T_194; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_197 = {io_a_data[23],io_data_in[23]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_198 = _GEN_3 >> _logical_T_197; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_200 = {io_a_data[24],io_data_in[24]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_201 = _GEN_3 >> _logical_T_200; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_203 = {io_a_data[25],io_data_in[25]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_204 = _GEN_3 >> _logical_T_203; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_206 = {io_a_data[26],io_data_in[26]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_207 = _GEN_3 >> _logical_T_206; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_209 = {io_a_data[27],io_data_in[27]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_210 = _GEN_3 >> _logical_T_209; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_212 = {io_a_data[28],io_data_in[28]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_213 = _GEN_3 >> _logical_T_212; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_215 = {io_a_data[29],io_data_in[29]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_216 = _GEN_3 >> _logical_T_215; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_218 = {io_a_data[30],io_data_in[30]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_219 = _GEN_3 >> _logical_T_218; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_221 = {io_a_data[31],io_data_in[31]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_222 = _GEN_3 >> _logical_T_221; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_224 = {io_a_data[32],io_data_in[32]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_225 = _GEN_3 >> _logical_T_224; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_227 = {io_a_data[33],io_data_in[33]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_228 = _GEN_3 >> _logical_T_227; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_230 = {io_a_data[34],io_data_in[34]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_231 = _GEN_3 >> _logical_T_230; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_233 = {io_a_data[35],io_data_in[35]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_234 = _GEN_3 >> _logical_T_233; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_236 = {io_a_data[36],io_data_in[36]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_237 = _GEN_3 >> _logical_T_236; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_239 = {io_a_data[37],io_data_in[37]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_240 = _GEN_3 >> _logical_T_239; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_242 = {io_a_data[38],io_data_in[38]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_243 = _GEN_3 >> _logical_T_242; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_245 = {io_a_data[39],io_data_in[39]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_246 = _GEN_3 >> _logical_T_245; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_248 = {io_a_data[40],io_data_in[40]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_249 = _GEN_3 >> _logical_T_248; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_251 = {io_a_data[41],io_data_in[41]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_252 = _GEN_3 >> _logical_T_251; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_254 = {io_a_data[42],io_data_in[42]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_255 = _GEN_3 >> _logical_T_254; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_257 = {io_a_data[43],io_data_in[43]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_258 = _GEN_3 >> _logical_T_257; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_260 = {io_a_data[44],io_data_in[44]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_261 = _GEN_3 >> _logical_T_260; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_263 = {io_a_data[45],io_data_in[45]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_264 = _GEN_3 >> _logical_T_263; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_266 = {io_a_data[46],io_data_in[46]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_267 = _GEN_3 >> _logical_T_266; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_269 = {io_a_data[47],io_data_in[47]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_270 = _GEN_3 >> _logical_T_269; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_272 = {io_a_data[48],io_data_in[48]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_273 = _GEN_3 >> _logical_T_272; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_275 = {io_a_data[49],io_data_in[49]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_276 = _GEN_3 >> _logical_T_275; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_278 = {io_a_data[50],io_data_in[50]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_279 = _GEN_3 >> _logical_T_278; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_281 = {io_a_data[51],io_data_in[51]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_282 = _GEN_3 >> _logical_T_281; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_284 = {io_a_data[52],io_data_in[52]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_285 = _GEN_3 >> _logical_T_284; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_287 = {io_a_data[53],io_data_in[53]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_288 = _GEN_3 >> _logical_T_287; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_290 = {io_a_data[54],io_data_in[54]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_291 = _GEN_3 >> _logical_T_290; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_293 = {io_a_data[55],io_data_in[55]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_294 = _GEN_3 >> _logical_T_293; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_296 = {io_a_data[56],io_data_in[56]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_297 = _GEN_3 >> _logical_T_296; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_299 = {io_a_data[57],io_data_in[57]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_300 = _GEN_3 >> _logical_T_299; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_302 = {io_a_data[58],io_data_in[58]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_303 = _GEN_3 >> _logical_T_302; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_305 = {io_a_data[59],io_data_in[59]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_306 = _GEN_3 >> _logical_T_305; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_308 = {io_a_data[60],io_data_in[60]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_309 = _GEN_3 >> _logical_T_308; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_311 = {io_a_data[61],io_data_in[61]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_312 = _GEN_3 >> _logical_T_311; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_314 = {io_a_data[62],io_data_in[62]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_315 = _GEN_3 >> _logical_T_314; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_317 = {io_a_data[63],io_data_in[63]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_318 = _GEN_3 >> _logical_T_317; // @[Atomics.scala 42:8]
  wire [7:0] logical_lo_lo_lo = {_logical_T_150[0],_logical_T_147[0],_logical_T_144[0],_logical_T_141[0],_logical_T_138[
    0],_logical_T_135[0],_logical_T_132[0],_logical_T_129[0]}; // @[Cat.scala 33:92]
  wire [15:0] logical_lo_lo = {_logical_T_174[0],_logical_T_171[0],_logical_T_168[0],_logical_T_165[0],_logical_T_162[0]
    ,_logical_T_159[0],_logical_T_156[0],_logical_T_153[0],logical_lo_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] logical_lo_hi_lo = {_logical_T_198[0],_logical_T_195[0],_logical_T_192[0],_logical_T_189[0],_logical_T_186[
    0],_logical_T_183[0],_logical_T_180[0],_logical_T_177[0]}; // @[Cat.scala 33:92]
  wire [31:0] logical_lo = {_logical_T_222[0],_logical_T_219[0],_logical_T_216[0],_logical_T_213[0],_logical_T_210[0],
    _logical_T_207[0],_logical_T_204[0],_logical_T_201[0],logical_lo_hi_lo,logical_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] logical_hi_lo_lo = {_logical_T_246[0],_logical_T_243[0],_logical_T_240[0],_logical_T_237[0],_logical_T_234[
    0],_logical_T_231[0],_logical_T_228[0],_logical_T_225[0]}; // @[Cat.scala 33:92]
  wire [15:0] logical_hi_lo = {_logical_T_270[0],_logical_T_267[0],_logical_T_264[0],_logical_T_261[0],_logical_T_258[0]
    ,_logical_T_255[0],_logical_T_252[0],_logical_T_249[0],logical_hi_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] logical_hi_hi_lo = {_logical_T_294[0],_logical_T_291[0],_logical_T_288[0],_logical_T_285[0],_logical_T_282[
    0],_logical_T_279[0],_logical_T_276[0],_logical_T_273[0]}; // @[Cat.scala 33:92]
  wire [31:0] logical_hi = {_logical_T_318[0],_logical_T_315[0],_logical_T_312[0],_logical_T_309[0],_logical_T_306[0],
    _logical_T_303[0],_logical_T_300[0],_logical_T_297[0],logical_hi_hi_lo,logical_hi_lo}; // @[Cat.scala 33:92]
  wire [63:0] logical = {logical_hi,logical_lo}; // @[Cat.scala 33:92]
  wire [1:0] _select_T_1 = adder ? 2'h2 : {{1'd0}, pick_a}; // @[Atomics.scala 49:8]
  wire [1:0] _GEN_6 = 3'h2 == io_a_opcode ? _select_T_1 : 2'h1; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_7 = 3'h3 == io_a_opcode ? 2'h3 : _GEN_6; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_8 = 3'h4 == io_a_opcode ? 2'h0 : _GEN_7; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_9 = 3'h5 == io_a_opcode ? 2'h0 : _GEN_8; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_10 = 3'h6 == io_a_opcode ? 2'h0 : _GEN_9; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_11 = 3'h7 == io_a_opcode ? 2'h0 : _GEN_10; // @[Atomics.scala 46:{19,19}]
  wire [1:0] select = io_write ? 2'h1 : _GEN_11; // @[Atomics.scala 46:19]
  wire [1:0] selects_0 = io_a_mask[0] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_1 = io_a_mask[1] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_2 = io_a_mask[2] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_3 = io_a_mask[3] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_4 = io_a_mask[4] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_5 = io_a_mask[5] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_6 = io_a_mask[6] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_7 = io_a_mask[7] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [7:0] _GEN_13 = 2'h1 == selects_1 ? io_a_data[15:8] : io_data_in[15:8]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_14 = 2'h2 == selects_1 ? sum[15:8] : _GEN_13; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_15 = 2'h3 == selects_1 ? logical[15:8] : _GEN_14; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_17 = 2'h1 == selects_0 ? io_a_data[7:0] : io_data_in[7:0]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_18 = 2'h2 == selects_0 ? sum[7:0] : _GEN_17; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_19 = 2'h3 == selects_0 ? logical[7:0] : _GEN_18; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_21 = 2'h1 == selects_3 ? io_a_data[31:24] : io_data_in[31:24]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_22 = 2'h2 == selects_3 ? sum[31:24] : _GEN_21; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_23 = 2'h3 == selects_3 ? logical[31:24] : _GEN_22; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_25 = 2'h1 == selects_2 ? io_a_data[23:16] : io_data_in[23:16]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_26 = 2'h2 == selects_2 ? sum[23:16] : _GEN_25; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_27 = 2'h3 == selects_2 ? logical[23:16] : _GEN_26; // @[Cat.scala 33:{92,92}]
  wire [31:0] io_data_out_lo = {_GEN_23,_GEN_27,_GEN_15,_GEN_19}; // @[Cat.scala 33:92]
  wire [7:0] _GEN_29 = 2'h1 == selects_5 ? io_a_data[47:40] : io_data_in[47:40]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_30 = 2'h2 == selects_5 ? sum[47:40] : _GEN_29; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_31 = 2'h3 == selects_5 ? logical[47:40] : _GEN_30; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_33 = 2'h1 == selects_4 ? io_a_data[39:32] : io_data_in[39:32]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_34 = 2'h2 == selects_4 ? sum[39:32] : _GEN_33; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_35 = 2'h3 == selects_4 ? logical[39:32] : _GEN_34; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_37 = 2'h1 == selects_7 ? io_a_data[63:56] : io_data_in[63:56]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_38 = 2'h2 == selects_7 ? sum[63:56] : _GEN_37; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_39 = 2'h3 == selects_7 ? logical[63:56] : _GEN_38; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_41 = 2'h1 == selects_6 ? io_a_data[55:48] : io_data_in[55:48]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_42 = 2'h2 == selects_6 ? sum[55:48] : _GEN_41; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_43 = 2'h3 == selects_6 ? logical[55:48] : _GEN_42; // @[Cat.scala 33:{92,92}]
  wire [31:0] io_data_out_hi = {_GEN_39,_GEN_43,_GEN_31,_GEN_35}; // @[Cat.scala 33:92]
  assign io_data_out = {io_data_out_hi,io_data_out_lo}; // @[Cat.scala 33:92]
endmodule
module SourceD(
  input         clock,
  input         reset,
  output        io_req_ready,
  input         io_req_valid,
  input         io_req_bits_prio_0,
  input         io_req_bits_prio_2,
  input  [2:0]  io_req_bits_opcode,
  input  [2:0]  io_req_bits_param,
  input  [2:0]  io_req_bits_size,
  input  [2:0]  io_req_bits_source,
  input  [3:0]  io_req_bits_offset,
  input  [5:0]  io_req_bits_put,
  input  [1:0]  io_req_bits_set,
  input  [4:0]  io_req_bits_sink,
  input         io_req_bits_way,
  input         io_req_bits_bad,
  input         io_d_ready,
  output        io_d_valid,
  output [2:0]  io_d_bits_opcode,
  output [1:0]  io_d_bits_param,
  output [2:0]  io_d_bits_size,
  output [2:0]  io_d_bits_source,
  output [4:0]  io_d_bits_sink,
  output        io_d_bits_denied,
  output [63:0] io_d_bits_data,
  output        io_d_bits_corrupt,
  input         io_pb_pop_ready,
  output        io_pb_pop_valid,
  output [5:0]  io_pb_pop_bits_index,
  output        io_pb_pop_bits_last,
  input  [63:0] io_pb_beat_data,
  input  [7:0]  io_pb_beat_mask,
  input         io_pb_beat_corrupt,
  input         io_rel_pop_ready,
  output        io_rel_pop_valid,
  output [5:0]  io_rel_pop_bits_index,
  output        io_rel_pop_bits_last,
  input  [63:0] io_rel_beat_data,
  input         io_rel_beat_corrupt,
  input         io_bs_radr_ready,
  output        io_bs_radr_valid,
  output        io_bs_radr_bits_way,
  output [1:0]  io_bs_radr_bits_set,
  output        io_bs_radr_bits_beat,
  output        io_bs_radr_bits_mask,
  input  [63:0] io_bs_rdat_data,
  input         io_bs_wadr_ready,
  output        io_bs_wadr_valid,
  output        io_bs_wadr_bits_way,
  output [1:0]  io_bs_wadr_bits_set,
  output        io_bs_wadr_bits_beat,
  output        io_bs_wadr_bits_mask,
  output [63:0] io_bs_wdat_data,
  input  [1:0]  io_evict_req_set,
  input         io_evict_req_way,
  output        io_evict_safe,
  input  [1:0]  io_grant_req_set,
  input         io_grant_req_way,
  output        io_grant_safe
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [63:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [63:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [63:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [63:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [63:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [63:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [63:0] _RAND_84;
  reg [63:0] _RAND_85;
`endif // RANDOMIZE_REG_INIT
  wire  queue_clock; // @[SourceD.scala 119:21]
  wire  queue_reset; // @[SourceD.scala 119:21]
  wire  queue_io_enq_ready; // @[SourceD.scala 119:21]
  wire  queue_io_enq_valid; // @[SourceD.scala 119:21]
  wire [63:0] queue_io_enq_bits_data; // @[SourceD.scala 119:21]
  wire  queue_io_deq_ready; // @[SourceD.scala 119:21]
  wire  queue_io_deq_valid; // @[SourceD.scala 119:21]
  wire [63:0] queue_io_deq_bits_data; // @[SourceD.scala 119:21]
  wire  atomics_io_write; // @[SourceD.scala 257:23]
  wire [2:0] atomics_io_a_opcode; // @[SourceD.scala 257:23]
  wire [2:0] atomics_io_a_param; // @[SourceD.scala 257:23]
  wire [7:0] atomics_io_a_mask; // @[SourceD.scala 257:23]
  wire [63:0] atomics_io_a_data; // @[SourceD.scala 257:23]
  wire [63:0] atomics_io_data_in; // @[SourceD.scala 257:23]
  wire [63:0] atomics_io_data_out; // @[SourceD.scala 257:23]
  reg  busy; // @[SourceD.scala 83:21]
  reg  s1_block_r; // @[SourceD.scala 84:27]
  reg  s1_counter; // @[SourceD.scala 85:27]
  wire  _s1_req_reg_T = ~busy; // @[SourceD.scala 86:43]
  wire  _s1_req_reg_T_1 = ~busy & io_req_valid; // @[SourceD.scala 86:49]
  reg  s1_req_reg_prio_0; // @[Reg.scala 19:16]
  reg  s1_req_reg_prio_2; // @[Reg.scala 19:16]
  reg [2:0] s1_req_reg_opcode; // @[Reg.scala 19:16]
  reg [2:0] s1_req_reg_param; // @[Reg.scala 19:16]
  reg [2:0] s1_req_reg_size; // @[Reg.scala 19:16]
  reg [2:0] s1_req_reg_source; // @[Reg.scala 19:16]
  reg [3:0] s1_req_reg_offset; // @[Reg.scala 19:16]
  reg [5:0] s1_req_reg_put; // @[Reg.scala 19:16]
  reg [1:0] s1_req_reg_set; // @[Reg.scala 19:16]
  reg [4:0] s1_req_reg_sink; // @[Reg.scala 19:16]
  reg  s1_req_reg_way; // @[Reg.scala 19:16]
  reg  s1_req_reg_bad; // @[Reg.scala 19:16]
  wire  s1_req_prio_0 = _s1_req_reg_T ? io_req_bits_prio_0 : s1_req_reg_prio_0; // @[SourceD.scala 87:19]
  wire [2:0] s1_req_opcode = _s1_req_reg_T ? io_req_bits_opcode : s1_req_reg_opcode; // @[SourceD.scala 87:19]
  wire [2:0] s1_req_param = _s1_req_reg_T ? io_req_bits_param : s1_req_reg_param; // @[SourceD.scala 87:19]
  wire [2:0] s1_req_size = _s1_req_reg_T ? io_req_bits_size : s1_req_reg_size; // @[SourceD.scala 87:19]
  wire [3:0] s1_req_offset = _s1_req_reg_T ? io_req_bits_offset : s1_req_reg_offset; // @[SourceD.scala 87:19]
  wire [1:0] s1_req_set = _s1_req_reg_T ? io_req_bits_set : s1_req_reg_set; // @[SourceD.scala 87:19]
  wire  s1_req_way = _s1_req_reg_T ? io_req_bits_way : s1_req_reg_way; // @[SourceD.scala 87:19]
  wire  _s1_latch_bypass_T = busy | io_req_valid; // @[SourceD.scala 89:40]
  reg  s2_full; // @[SourceD.scala 146:24]
  wire  _s2_ready_T = ~s2_full; // @[SourceD.scala 183:15]
  reg  s3_full; // @[SourceD.scala 189:24]
  wire  _s3_ready_T = ~s3_full; // @[SourceD.scala 241:15]
  reg  s3_retires; // @[Reg.scala 19:16]
  reg  s4_full; // @[SourceD.scala 247:24]
  wire  _s4_ready_T_1 = ~s4_full; // @[SourceD.scala 291:30]
  reg  s4_need_bs; // @[Reg.scala 19:16]
  wire  _s4_ready_T_4 = ~s4_need_bs; // @[SourceD.scala 291:62]
  wire  s4_ready = ~s3_retires | ~s4_full | io_bs_wadr_ready | ~s4_need_bs; // @[SourceD.scala 291:59]
  reg  s3_valid_d; // @[SourceD.scala 190:27]
  wire  _s3_ready_T_2 = ~s3_valid_d | io_d_ready; // @[SourceD.scala 241:53]
  wire  s3_ready = ~s3_full | s4_ready & (~s3_valid_d | io_d_ready); // @[SourceD.scala 241:24]
  reg  s2_valid_pb; // @[SourceD.scala 147:28]
  reg  s2_req_prio_0; // @[Reg.scala 19:16]
  wire  pb_ready = s2_req_prio_0 ? io_pb_pop_ready : io_rel_pop_ready; // @[SourceD.scala 174:21]
  wire  _s2_ready_T_2 = ~s2_valid_pb | pb_ready; // @[SourceD.scala 183:54]
  wire  s2_ready = ~s2_full | s3_ready & (~s2_valid_pb | pb_ready); // @[SourceD.scala 183:24]
  reg  s1_latch_bypass; // @[SourceD.scala 89:32]
  reg  s1_bypass_r; // @[Reg.scala 19:16]
  reg [1:0] s2_req_set; // @[Reg.scala 19:16]
  reg  s2_req_way; // @[Reg.scala 19:16]
  reg  s2_beat; // @[Reg.scala 19:16]
  wire  s1_beat = s1_req_offset[3] | s1_counter; // @[SourceD.scala 101:56]
  reg  s2_retires; // @[Reg.scala 19:16]
  wire  s1_2_match = s2_req_set == s1_req_set & s2_req_way == s1_req_way & s2_beat == s1_beat & s2_full & s2_retires; // @[SourceD.scala 342:110]
  reg [1:0] s3_req_set; // @[Reg.scala 19:16]
  reg  s3_req_way; // @[Reg.scala 19:16]
  reg  s3_beat; // @[Reg.scala 19:16]
  wire  s1_3_match = s3_req_set == s1_req_set & s3_req_way == s1_req_way & s3_beat == s1_beat & s3_full & s3_retires; // @[SourceD.scala 343:110]
  reg [1:0] s4_req_set; // @[Reg.scala 19:16]
  reg  s4_req_way; // @[Reg.scala 19:16]
  reg  s4_beat; // @[Reg.scala 19:16]
  wire  s1_4_match = s4_req_set == s1_req_set & s4_req_way == s1_req_way & s4_beat == s1_beat & s4_full; // @[SourceD.scala 344:99]
  wire  s1_x_bypass = s1_2_match | s1_3_match | s1_4_match; // @[SourceD.scala 358:44]
  wire  _GEN_15 = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[Reg.scala 19:16 20:{18,22}]
  wire  s1_mask = ~_GEN_15; // @[SourceD.scala 91:78]
  wire  _s1_grant_T = s1_req_opcode == 3'h6; // @[SourceD.scala 92:33]
  wire  s1_grant = s1_req_opcode == 3'h6 & s1_req_param == 3'h2 | s1_req_opcode == 3'h7; // @[SourceD.scala 92:76]
  wire  _s1_need_r_T_8 = s1_req_opcode != 3'h0 | s1_req_size < 3'h3; // @[SourceD.scala 94:50]
  wire  s1_need_r = |s1_mask & s1_req_prio_0 & s1_req_opcode != 3'h5 & ~s1_grant & _s1_need_r_T_8; // @[SourceD.scala 93:88]
  wire  s1_valid_r = _s1_latch_bypass_T & s1_need_r & ~s1_block_r; // @[SourceD.scala 95:56]
  wire  s1_need_pb = s1_req_prio_0 ? ~s1_req_opcode[2] : s1_req_opcode[0]; // @[SourceD.scala 96:23]
  wire  s1_single = s1_req_prio_0 ? s1_req_opcode == 3'h5 | s1_grant : _s1_grant_T; // @[SourceD.scala 97:22]
  wire  s1_retires = ~s1_single; // @[SourceD.scala 98:20]
  wire [10:0] _s1_beats1_T_1 = 11'hf << s1_req_size; // @[package.scala 234:77]
  wire [3:0] _s1_beats1_T_3 = ~_s1_beats1_T_1[3:0]; // @[package.scala 234:46]
  wire  s1_beats1 = s1_single ? 1'h0 : _s1_beats1_T_3[3]; // @[SourceD.scala 100:22]
  wire  s1_last = s1_counter == s1_beats1; // @[SourceD.scala 102:28]
  wire  s1_first = ~s1_counter; // @[SourceD.scala 103:29]
  wire  _queue_io_enq_valid_T = io_bs_radr_ready & io_bs_radr_valid; // @[Decoupled.scala 52:35]
  reg  queue_io_enq_valid_REG; // @[SourceD.scala 120:40]
  reg  queue_io_enq_valid_REG_1; // @[SourceD.scala 120:32]
  wire  _T_9 = ~reset; // @[SourceD.scala 122:10]
  wire  _GEN_16 = _queue_io_enq_valid_T | s1_block_r; // @[SourceD.scala 126:{28,41} 84:27]
  wire  _GEN_17 = io_req_valid | busy; // @[SourceD.scala 127:{23,30} 83:21]
  wire  s1_valid = _s1_latch_bypass_T & (~s1_valid_r | io_bs_radr_ready); // @[SourceD.scala 140:38]
  wire  _T_13 = s1_valid & s2_ready; // @[SourceD.scala 128:18]
  reg  s2_bypass; // @[Reg.scala 19:16]
  reg  s2_req_prio_2; // @[Reg.scala 19:16]
  reg [2:0] s2_req_opcode; // @[Reg.scala 19:16]
  reg [2:0] s2_req_param; // @[Reg.scala 19:16]
  reg [2:0] s2_req_size; // @[Reg.scala 19:16]
  reg [2:0] s2_req_source; // @[Reg.scala 19:16]
  reg [5:0] s2_req_put; // @[Reg.scala 19:16]
  reg [4:0] s2_req_sink; // @[Reg.scala 19:16]
  reg  s2_req_bad; // @[Reg.scala 19:16]
  reg  s2_last; // @[Reg.scala 19:16]
  reg  s2_need_r; // @[Reg.scala 19:16]
  reg  s2_need_pb; // @[Reg.scala 19:16]
  wire  _s2_need_d_T_1 = ~s1_need_pb | s1_first; // @[SourceD.scala 155:41]
  reg  s2_need_d; // @[Reg.scala 19:16]
  reg [63:0] s2_pdata_r_data; // @[Reg.scala 19:16]
  reg [7:0] s2_pdata_r_mask; // @[Reg.scala 19:16]
  reg  s2_pdata_r_corrupt; // @[Reg.scala 19:16]
  wire  s2_valid = s2_full & _s2_ready_T_2; // @[SourceD.scala 182:23]
  wire  _T_20 = s2_valid & s3_ready; // @[SourceD.scala 176:18]
  wire  _GEN_49 = s2_valid & s3_ready ? 1'h0 : s2_full; // @[SourceD.scala 146:24 176:{31,41}]
  wire  _GEN_51 = _T_13 | _GEN_49; // @[SourceD.scala 178:{19,29}]
  wire  _GEN_52 = _T_20 ? s2_beat : s3_beat; // @[Reg.scala 19:16 20:{18,22}]
  reg  s3_bypass; // @[Reg.scala 19:16]
  reg  s3_req_prio_0; // @[Reg.scala 19:16]
  reg  s3_req_prio_2; // @[Reg.scala 19:16]
  reg [2:0] s3_req_opcode; // @[Reg.scala 19:16]
  reg [2:0] s3_req_param; // @[Reg.scala 19:16]
  reg [2:0] s3_req_size; // @[Reg.scala 19:16]
  reg [2:0] s3_req_source; // @[Reg.scala 19:16]
  reg [4:0] s3_req_sink; // @[Reg.scala 19:16]
  reg  s3_req_bad; // @[Reg.scala 19:16]
  wire [1:0] _GEN_65 = _T_20 ? s2_req_set : s3_req_set; // @[Reg.scala 19:16 20:{18,22}]
  wire  _GEN_67 = _T_20 ? s2_req_way : s3_req_way; // @[Reg.scala 19:16 20:{18,22}]
  reg [63:0] s3_pdata_data; // @[Reg.scala 19:16]
  reg [7:0] s3_pdata_mask; // @[Reg.scala 19:16]
  reg  s3_pdata_corrupt; // @[Reg.scala 19:16]
  reg  s3_need_bs; // @[Reg.scala 19:16]
  reg  s3_need_r; // @[Reg.scala 19:16]
  wire  s3_acq = s3_req_opcode == 3'h6 | s3_req_opcode == 3'h7; // @[SourceD.scala 201:47]
  reg  s3_bypass_data_REG; // @[SourceD.scala 335:19]
  wire [63:0] _s3_bypass_data_T_9 = atomics_io_data_out; // @[SourceD.scala 206:78]
  reg [63:0] s3_bypass_data_REG_1; // @[SourceD.scala 335:66]
  wire [63:0] s3_bypass_data = s3_bypass_data_REG ? _s3_bypass_data_T_9 : s3_bypass_data_REG_1; // @[SourceD.scala 209:75]
  wire [63:0] _s3_rdata_T_2 = queue_io_deq_bits_data; // @[SourceD.scala 206:78]
  wire [2:0] grant = s3_req_param == 3'h2 ? 3'h4 : 3'h5; // @[SourceD.scala 213:18]
  wire [2:0] _GEN_78 = 3'h2 == s3_req_opcode ? 3'h1 : 3'h0; // @[SourceD.scala 221:{24,24}]
  wire [2:0] _GEN_79 = 3'h3 == s3_req_opcode ? 3'h1 : _GEN_78; // @[SourceD.scala 221:{24,24}]
  wire [2:0] _GEN_80 = 3'h4 == s3_req_opcode ? 3'h1 : _GEN_79; // @[SourceD.scala 221:{24,24}]
  wire [2:0] _GEN_81 = 3'h5 == s3_req_opcode ? 3'h2 : _GEN_80; // @[SourceD.scala 221:{24,24}]
  wire [2:0] _GEN_82 = 3'h6 == s3_req_opcode ? grant : _GEN_81; // @[SourceD.scala 221:{24,24}]
  wire [2:0] _GEN_83 = 3'h7 == s3_req_opcode ? 3'h4 : _GEN_82; // @[SourceD.scala 221:{24,24}]
  wire [2:0] d_bits_opcode = s3_req_prio_0 ? _GEN_83 : 3'h6; // @[SourceD.scala 221:24]
  wire [1:0] _d_bits_param_T_2 = s3_req_param != 3'h0 ? 2'h0 : 2'h1; // @[SourceD.scala 222:54]
  wire  s3_valid = s3_full & _s3_ready_T_2; // @[SourceD.scala 240:23]
  wire  _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala 230:34]
  wire  _GEN_85 = _queue_io_deq_ready_T ? 1'h0 : s3_full; // @[SourceD.scala 189:24 234:{31,41}]
  wire  _GEN_87 = _T_20 | _GEN_85; // @[SourceD.scala 236:{19,29}]
  wire  s4_latch = s3_valid & s3_retires & s4_ready; // @[SourceD.scala 246:41]
  wire  _GEN_88 = s4_latch ? s3_beat : s4_beat; // @[Reg.scala 19:16 20:{18,22}]
  reg  s4_need_pb; // @[Reg.scala 19:16]
  reg  s4_req_prio_2; // @[Reg.scala 19:16]
  reg [2:0] s4_req_param; // @[Reg.scala 19:16]
  wire [1:0] _GEN_103 = s4_latch ? s3_req_set : s4_req_set; // @[Reg.scala 19:16 20:{18,22}]
  wire  _GEN_105 = s4_latch ? s3_req_way : s4_req_way; // @[Reg.scala 19:16 20:{18,22}]
  reg [2:0] s4_adjusted_opcode; // @[Reg.scala 19:16]
  reg [63:0] s4_pdata_data; // @[Reg.scala 19:16]
  reg [7:0] s4_pdata_mask; // @[Reg.scala 19:16]
  reg  s4_pdata_corrupt; // @[Reg.scala 19:16]
  reg [63:0] s4_rdata; // @[Reg.scala 19:16]
  wire  _T_78 = io_bs_wadr_ready | _s4_ready_T_4; // @[SourceD.scala 288:26]
  wire  _GEN_112 = io_bs_wadr_ready | _s4_ready_T_4 ? 1'h0 : s4_full; // @[SourceD.scala 247:24 288:{42,52}]
  wire  _GEN_113 = s4_latch | _GEN_112; // @[SourceD.scala 289:{19,29}]
  wire  retire = s4_full & _T_78; // @[SourceD.scala 298:24]
  reg [1:0] s5_req_set; // @[Reg.scala 19:16]
  reg  s5_req_way; // @[Reg.scala 19:16]
  wire [1:0] _GEN_125 = retire ? s4_req_set : s5_req_set; // @[Reg.scala 19:16 20:{18,22}]
  wire  _GEN_127 = retire ? s4_req_way : s5_req_way; // @[Reg.scala 19:16 20:{18,22}]
  reg  s5_beat; // @[Reg.scala 19:16]
  wire  _GEN_129 = retire ? s4_beat : s5_beat; // @[Reg.scala 19:16 20:{18,22}]
  reg [63:0] s5_dat; // @[Reg.scala 19:16]
  reg [1:0] s6_req_set; // @[Reg.scala 19:16]
  reg  s6_req_way; // @[Reg.scala 19:16]
  wire [1:0] _GEN_142 = retire ? s5_req_set : s6_req_set; // @[Reg.scala 19:16 20:{18,22}]
  wire  _GEN_144 = retire ? s5_req_way : s6_req_way; // @[Reg.scala 19:16 20:{18,22}]
  reg  s6_beat; // @[Reg.scala 19:16]
  wire  _GEN_146 = retire ? s5_beat : s6_beat; // @[Reg.scala 19:16 20:{18,22}]
  reg [63:0] s6_dat; // @[Reg.scala 19:16]
  reg [63:0] s7_dat; // @[Reg.scala 19:16]
  wire  pre_s4_full = s4_latch | ~_T_78 & s4_full; // @[SourceD.scala 324:30]
  wire  pre_s3_5_match = _GEN_125 == _GEN_65 & _GEN_127 == _GEN_67 & _GEN_129 == _GEN_52; // @[SourceD.scala 327:96]
  wire  pre_s3_6_match = _GEN_142 == _GEN_65 & _GEN_144 == _GEN_67 & _GEN_146 == _GEN_52; // @[SourceD.scala 328:96]
  wire  _io_evict_safe_T_9 = _s2_ready_T | io_evict_req_way != s2_req_way | io_evict_req_set != s2_req_set; // @[SourceD.scala 375:54]
  wire  _io_evict_safe_T_10 = (_s1_req_reg_T | io_evict_req_way != s1_req_reg_way | io_evict_req_set != s1_req_reg_set)
     & _io_evict_safe_T_9; // @[SourceD.scala 374:94]
  wire  _io_evict_safe_T_15 = _s3_ready_T | io_evict_req_way != s3_req_way | io_evict_req_set != s3_req_set; // @[SourceD.scala 376:54]
  wire  _io_evict_safe_T_16 = _io_evict_safe_T_10 & _io_evict_safe_T_15; // @[SourceD.scala 375:90]
  wire  _io_evict_safe_T_21 = _s4_ready_T_1 | io_evict_req_way != s4_req_way | io_evict_req_set != s4_req_set; // @[SourceD.scala 377:54]
  wire  _io_grant_safe_T_9 = _s2_ready_T | io_grant_req_way != s2_req_way | io_grant_req_set != s2_req_set; // @[SourceD.scala 382:54]
  wire  _io_grant_safe_T_10 = (_s1_req_reg_T | io_grant_req_way != s1_req_reg_way | io_grant_req_set != s1_req_reg_set)
     & _io_grant_safe_T_9; // @[SourceD.scala 381:94]
  wire  _io_grant_safe_T_15 = _s3_ready_T | io_grant_req_way != s3_req_way | io_grant_req_set != s3_req_set; // @[SourceD.scala 383:54]
  wire  _io_grant_safe_T_16 = _io_grant_safe_T_10 & _io_grant_safe_T_15; // @[SourceD.scala 382:90]
  wire  _io_grant_safe_T_21 = _s4_ready_T_1 | io_grant_req_way != s4_req_way | io_grant_req_set != s4_req_set; // @[SourceD.scala 384:54]
  QueueCompatibility_1 queue ( // @[SourceD.scala 119:21]
    .clock(queue_clock),
    .reset(queue_reset),
    .io_enq_ready(queue_io_enq_ready),
    .io_enq_valid(queue_io_enq_valid),
    .io_enq_bits_data(queue_io_enq_bits_data),
    .io_deq_ready(queue_io_deq_ready),
    .io_deq_valid(queue_io_deq_valid),
    .io_deq_bits_data(queue_io_deq_bits_data)
  );
  Atomics atomics ( // @[SourceD.scala 257:23]
    .io_write(atomics_io_write),
    .io_a_opcode(atomics_io_a_opcode),
    .io_a_param(atomics_io_a_param),
    .io_a_mask(atomics_io_a_mask),
    .io_a_data(atomics_io_a_data),
    .io_data_in(atomics_io_data_in),
    .io_data_out(atomics_io_data_out)
  );
  assign io_req_ready = ~busy; // @[SourceD.scala 139:19]
  assign io_d_valid = s3_valid_d; // @[SourceD.scala 217:15 220:11]
  assign io_d_bits_opcode = s3_req_prio_0 ? _GEN_83 : 3'h6; // @[SourceD.scala 221:24]
  assign io_d_bits_param = s3_req_prio_0 & s3_acq ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala 222:24]
  assign io_d_bits_size = s3_req_size; // @[SourceD.scala 217:15 223:18]
  assign io_d_bits_source = s3_req_source; // @[SourceD.scala 217:15 224:18]
  assign io_d_bits_sink = s3_req_sink; // @[SourceD.scala 217:15 225:18]
  assign io_d_bits_denied = s3_req_bad; // @[SourceD.scala 217:15 226:18]
  assign io_d_bits_data = s3_bypass ? s3_bypass_data : _s3_rdata_T_2; // @[SourceD.scala 209:75]
  assign io_d_bits_corrupt = s3_req_bad & d_bits_opcode[0]; // @[SourceD.scala 228:32]
  assign io_pb_pop_valid = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala 163:34]
  assign io_pb_pop_bits_index = s2_req_put; // @[SourceD.scala 164:24]
  assign io_pb_pop_bits_last = s2_last; // @[SourceD.scala 165:24]
  assign io_rel_pop_valid = s2_valid_pb & ~s2_req_prio_0; // @[SourceD.scala 166:35]
  assign io_rel_pop_bits_index = s2_req_put; // @[SourceD.scala 167:25]
  assign io_rel_pop_bits_last = s2_last; // @[SourceD.scala 168:25]
  assign io_bs_radr_valid = _s1_latch_bypass_T & s1_need_r & ~s1_block_r; // @[SourceD.scala 95:56]
  assign io_bs_radr_bits_way = _s1_req_reg_T ? io_req_bits_way : s1_req_reg_way; // @[SourceD.scala 87:19]
  assign io_bs_radr_bits_set = _s1_req_reg_T ? io_req_bits_set : s1_req_reg_set; // @[SourceD.scala 87:19]
  assign io_bs_radr_bits_beat = s1_req_offset[3] | s1_counter; // @[SourceD.scala 101:56]
  assign io_bs_radr_bits_mask = ~_GEN_15; // @[SourceD.scala 91:78]
  assign io_bs_wadr_valid = s4_full & s4_need_bs; // @[SourceD.scala 268:31]
  assign io_bs_wadr_bits_way = s4_req_way; // @[SourceD.scala 270:24]
  assign io_bs_wadr_bits_set = s4_req_set; // @[SourceD.scala 271:24]
  assign io_bs_wadr_bits_beat = s4_beat; // @[SourceD.scala 272:24]
  assign io_bs_wadr_bits_mask = s4_pdata_mask[0] | s4_pdata_mask[1] | s4_pdata_mask[2] | s4_pdata_mask[3] |
    s4_pdata_mask[4] | s4_pdata_mask[5] | s4_pdata_mask[6] | s4_pdata_mask[7]; // @[SourceD.scala 273:87]
  assign io_bs_wdat_data = atomics_io_data_out; // @[SourceD.scala 274:19]
  assign io_evict_safe = _io_evict_safe_T_16 & _io_evict_safe_T_21; // @[SourceD.scala 376:90]
  assign io_grant_safe = _io_grant_safe_T_16 & _io_grant_safe_T_21; // @[SourceD.scala 383:90]
  assign queue_clock = clock;
  assign queue_reset = reset;
  assign queue_io_enq_valid = queue_io_enq_valid_REG_1; // @[SourceD.scala 120:22]
  assign queue_io_enq_bits_data = io_bs_rdat_data; // @[SourceD.scala 121:21]
  assign queue_io_deq_ready = s3_valid & s4_ready & s3_need_r; // @[SourceD.scala 230:46]
  assign atomics_io_write = s4_req_prio_2; // @[SourceD.scala 258:24]
  assign atomics_io_a_opcode = s4_adjusted_opcode; // @[SourceD.scala 259:24]
  assign atomics_io_a_param = s4_req_param; // @[SourceD.scala 260:24]
  assign atomics_io_a_mask = s4_pdata_mask; // @[SourceD.scala 264:24]
  assign atomics_io_a_data = s4_pdata_data; // @[SourceD.scala 265:24]
  assign atomics_io_data_in = s4_rdata; // @[SourceD.scala 266:24]
  always @(posedge clock) begin
    if (reset) begin // @[SourceD.scala 83:21]
      busy <= 1'h0; // @[SourceD.scala 83:21]
    end else if (s1_valid & s2_ready) begin // @[SourceD.scala 128:31]
      if (s1_last) begin // @[SourceD.scala 131:20]
        busy <= 1'h0; // @[SourceD.scala 133:12]
      end else begin
        busy <= _GEN_17;
      end
    end else begin
      busy <= _GEN_17;
    end
    if (reset) begin // @[SourceD.scala 84:27]
      s1_block_r <= 1'h0; // @[SourceD.scala 84:27]
    end else if (s1_valid & s2_ready) begin // @[SourceD.scala 128:31]
      s1_block_r <= 1'h0; // @[SourceD.scala 130:16]
    end else begin
      s1_block_r <= _GEN_16;
    end
    if (reset) begin // @[SourceD.scala 85:27]
      s1_counter <= 1'h0; // @[SourceD.scala 85:27]
    end else if (s1_valid & s2_ready) begin // @[SourceD.scala 128:31]
      if (s1_last) begin // @[SourceD.scala 131:20]
        s1_counter <= 1'h0; // @[SourceD.scala 132:18]
      end else begin
        s1_counter <= s1_counter + 1'h1; // @[SourceD.scala 129:16]
      end
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_prio_0 <= io_req_bits_prio_0; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_prio_2 <= io_req_bits_prio_2; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_opcode <= io_req_bits_opcode; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_param <= io_req_bits_param; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_size <= io_req_bits_size; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_source <= io_req_bits_source; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_offset <= io_req_bits_offset; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_put <= io_req_bits_put; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_set <= io_req_bits_set; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_sink <= io_req_bits_sink; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_way <= io_req_bits_way; // @[Reg.scala 20:22]
    end
    if (_s1_req_reg_T_1) begin // @[Reg.scala 20:18]
      s1_req_reg_bad <= io_req_bits_bad; // @[Reg.scala 20:22]
    end
    if (reset) begin // @[SourceD.scala 146:24]
      s2_full <= 1'h0; // @[SourceD.scala 146:24]
    end else begin
      s2_full <= _GEN_51;
    end
    if (reset) begin // @[SourceD.scala 189:24]
      s3_full <= 1'h0; // @[SourceD.scala 189:24]
    end else begin
      s3_full <= _GEN_87;
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_retires <= s2_retires; // @[Reg.scala 20:22]
    end
    if (reset) begin // @[SourceD.scala 247:24]
      s4_full <= 1'h0; // @[SourceD.scala 247:24]
    end else begin
      s4_full <= _GEN_113;
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_need_bs <= s3_need_bs; // @[Reg.scala 20:22]
    end
    if (reset) begin // @[SourceD.scala 190:27]
      s3_valid_d <= 1'h0; // @[SourceD.scala 190:27]
    end else if (_T_20) begin // @[SourceD.scala 235:19]
      s3_valid_d <= s2_need_d; // @[SourceD.scala 235:32]
    end else if (io_d_ready) begin // @[SourceD.scala 233:18]
      s3_valid_d <= 1'h0; // @[SourceD.scala 233:31]
    end
    if (reset) begin // @[SourceD.scala 147:28]
      s2_valid_pb <= 1'h0; // @[SourceD.scala 147:28]
    end else if (_T_13) begin // @[SourceD.scala 177:19]
      if (s1_req_prio_0) begin // @[SourceD.scala 96:23]
        s2_valid_pb <= ~s1_req_opcode[2];
      end else begin
        s2_valid_pb <= s1_req_opcode[0];
      end
    end else if (pb_ready) begin // @[SourceD.scala 175:19]
      s2_valid_pb <= 1'h0; // @[SourceD.scala 175:33]
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_prio_0 <= io_req_bits_prio_0;
      end else begin
        s2_req_prio_0 <= s1_req_reg_prio_0;
      end
    end
    s1_latch_bypass <= ~(busy | io_req_valid) | s2_ready; // @[SourceD.scala 89:57]
    if (s1_latch_bypass) begin // @[Reg.scala 20:18]
      s1_bypass_r <= s1_x_bypass; // @[Reg.scala 20:22]
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_set <= io_req_bits_set;
      end else begin
        s2_req_set <= s1_req_reg_set;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_way <= io_req_bits_way;
      end else begin
        s2_req_way <= s1_req_reg_way;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      s2_beat <= s1_beat; // @[Reg.scala 20:22]
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      s2_retires <= s1_retires; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_set <= s2_req_set; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_way <= s2_req_way; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_beat <= s2_beat; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_req_set <= s3_req_set; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_req_way <= s3_req_way; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_beat <= s3_beat; // @[Reg.scala 20:22]
    end
    queue_io_enq_valid_REG <= io_bs_radr_ready & io_bs_radr_valid; // @[Decoupled.scala 52:35]
    queue_io_enq_valid_REG_1 <= queue_io_enq_valid_REG; // @[SourceD.scala 120:32]
    if (_T_13) begin // @[Reg.scala 20:18]
      if (s1_latch_bypass) begin // @[Reg.scala 20:18]
        s2_bypass <= s1_x_bypass; // @[Reg.scala 20:22]
      end else begin
        s2_bypass <= s1_bypass_r; // @[Reg.scala 19:16]
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_prio_2 <= io_req_bits_prio_2;
      end else begin
        s2_req_prio_2 <= s1_req_reg_prio_2;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_opcode <= io_req_bits_opcode;
      end else begin
        s2_req_opcode <= s1_req_reg_opcode;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_param <= io_req_bits_param;
      end else begin
        s2_req_param <= s1_req_reg_param;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_size <= io_req_bits_size;
      end else begin
        s2_req_size <= s1_req_reg_size;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_source <= io_req_bits_source;
      end else begin
        s2_req_source <= s1_req_reg_source;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_put <= io_req_bits_put;
      end else begin
        s2_req_put <= s1_req_reg_put;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_sink <= io_req_bits_sink;
      end else begin
        s2_req_sink <= s1_req_reg_sink;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (_s1_req_reg_T) begin // @[SourceD.scala 87:19]
        s2_req_bad <= io_req_bits_bad;
      end else begin
        s2_req_bad <= s1_req_reg_bad;
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      s2_last <= s1_last; // @[Reg.scala 20:22]
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      s2_need_r <= s1_need_r; // @[Reg.scala 20:22]
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      if (s1_req_prio_0) begin // @[SourceD.scala 96:23]
        s2_need_pb <= ~s1_req_opcode[2];
      end else begin
        s2_need_pb <= s1_req_opcode[0];
      end
    end
    if (_T_13) begin // @[Reg.scala 20:18]
      s2_need_d <= _s2_need_d_T_1; // @[Reg.scala 20:22]
    end
    if (s2_valid_pb) begin // @[Reg.scala 20:18]
      if (s2_req_prio_0) begin // @[SourceD.scala 159:30]
        s2_pdata_r_data <= io_pb_beat_data;
      end else begin
        s2_pdata_r_data <= io_rel_beat_data;
      end
    end
    if (s2_valid_pb) begin // @[Reg.scala 20:18]
      if (s2_req_prio_0) begin // @[SourceD.scala 160:30]
        s2_pdata_r_mask <= io_pb_beat_mask;
      end else begin
        s2_pdata_r_mask <= 8'hff;
      end
    end
    if (s2_valid_pb) begin // @[Reg.scala 20:18]
      if (s2_req_prio_0) begin // @[SourceD.scala 161:30]
        s2_pdata_r_corrupt <= io_pb_beat_corrupt;
      end else begin
        s2_pdata_r_corrupt <= io_rel_beat_corrupt;
      end
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_bypass <= s2_bypass; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_prio_0 <= s2_req_prio_0; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_prio_2 <= s2_req_prio_2; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_opcode <= s2_req_opcode; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_param <= s2_req_param; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_size <= s2_req_size; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_source <= s2_req_source; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_sink <= s2_req_sink; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_req_bad <= s2_req_bad; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      if (s2_valid_pb) begin // @[Reg.scala 20:18]
        if (s2_req_prio_0) begin // @[SourceD.scala 159:30]
          s3_pdata_data <= io_pb_beat_data;
        end else begin
          s3_pdata_data <= io_rel_beat_data;
        end
      end else begin
        s3_pdata_data <= s2_pdata_r_data; // @[Reg.scala 19:16]
      end
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      if (s2_valid_pb) begin // @[Reg.scala 20:18]
        if (s2_req_prio_0) begin // @[SourceD.scala 160:30]
          s3_pdata_mask <= io_pb_beat_mask;
        end else begin
          s3_pdata_mask <= 8'hff;
        end
      end else begin
        s3_pdata_mask <= s2_pdata_r_mask; // @[Reg.scala 19:16]
      end
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      if (s2_valid_pb) begin // @[Reg.scala 20:18]
        if (s2_req_prio_0) begin // @[SourceD.scala 161:30]
          s3_pdata_corrupt <= io_pb_beat_corrupt;
        end else begin
          s3_pdata_corrupt <= io_rel_beat_corrupt;
        end
      end else begin
        s3_pdata_corrupt <= s2_pdata_r_corrupt; // @[Reg.scala 19:16]
      end
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_need_bs <= s2_need_pb; // @[Reg.scala 20:22]
    end
    if (_T_20) begin // @[Reg.scala 20:18]
      s3_need_r <= s2_need_r; // @[Reg.scala 20:22]
    end
    s3_bypass_data_REG <= _GEN_103 == _GEN_65 & _GEN_105 == _GEN_67 & _GEN_88 == _GEN_52 & pre_s4_full; // @[SourceD.scala 326:127]
    if (pre_s3_5_match) begin // @[SourceD.scala 209:75]
      if (retire) begin // @[Reg.scala 20:18]
        s3_bypass_data_REG_1 <= atomics_io_data_out; // @[Reg.scala 20:22]
      end else begin
        s3_bypass_data_REG_1 <= s5_dat; // @[Reg.scala 19:16]
      end
    end else if (pre_s3_6_match) begin // @[SourceD.scala 209:75]
      if (retire) begin // @[Reg.scala 20:18]
        s3_bypass_data_REG_1 <= s5_dat; // @[Reg.scala 20:22]
      end else begin
        s3_bypass_data_REG_1 <= s6_dat; // @[Reg.scala 19:16]
      end
    end else if (retire) begin // @[Reg.scala 20:18]
      s3_bypass_data_REG_1 <= s6_dat; // @[Reg.scala 20:22]
    end else begin
      s3_bypass_data_REG_1 <= s7_dat; // @[Reg.scala 19:16]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_need_pb <= s3_need_bs; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_req_prio_2 <= s3_req_prio_2; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_req_param <= s3_req_param; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      if (s3_req_bad) begin // @[SourceD.scala 194:31]
        s4_adjusted_opcode <= 3'h4;
      end else begin
        s4_adjusted_opcode <= s3_req_opcode;
      end
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_pdata_data <= s3_pdata_data; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_pdata_mask <= s3_pdata_mask; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      s4_pdata_corrupt <= s3_pdata_corrupt; // @[Reg.scala 20:22]
    end
    if (s4_latch) begin // @[Reg.scala 20:18]
      if (s3_bypass) begin // @[SourceD.scala 209:75]
        if (s3_bypass_data_REG) begin // @[SourceD.scala 209:75]
          s4_rdata <= _s3_bypass_data_T_9;
        end else begin
          s4_rdata <= s3_bypass_data_REG_1;
        end
      end else begin
        s4_rdata <= _s3_rdata_T_2;
      end
    end
    if (retire) begin // @[Reg.scala 20:18]
      s5_req_set <= s4_req_set; // @[Reg.scala 20:22]
    end
    if (retire) begin // @[Reg.scala 20:18]
      s5_req_way <= s4_req_way; // @[Reg.scala 20:22]
    end
    if (retire) begin // @[Reg.scala 20:18]
      s5_beat <= s4_beat; // @[Reg.scala 20:22]
    end
    if (retire) begin // @[Reg.scala 20:18]
      s5_dat <= atomics_io_data_out; // @[Reg.scala 20:22]
    end
    if (retire) begin // @[Reg.scala 20:18]
      s6_req_set <= s5_req_set; // @[Reg.scala 20:22]
    end
    if (retire) begin // @[Reg.scala 20:18]
      s6_req_way <= s5_req_way; // @[Reg.scala 20:22]
    end
    if (retire) begin // @[Reg.scala 20:18]
      s6_beat <= s5_beat; // @[Reg.scala 20:22]
    end
    if (retire) begin // @[Reg.scala 20:18]
      s6_dat <= s5_dat; // @[Reg.scala 20:22]
    end
    if (retire) begin // @[Reg.scala 20:18]
      s7_dat <= s6_dat; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~queue_io_enq_valid | queue_io_enq_ready)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at SourceD.scala:122 assert (!queue.io.enq.valid || queue.io.enq.ready)\n"); // @[SourceD.scala 122:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~queue_io_enq_valid | queue_io_enq_ready) & ~reset) begin
          $fatal; // @[SourceD.scala 122:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(_s3_ready_T | ~s3_need_r | queue_io_deq_valid)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at SourceD.scala:231 assert (!s3_full || !s3_need_r || queue.io.deq.valid)\n"); // @[SourceD.scala 231:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_s3_ready_T | ~s3_need_r | queue_io_deq_valid) & _T_9) begin
          $fatal; // @[SourceD.scala 231:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(s4_full & s4_need_pb & s4_pdata_corrupt))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Data poisoning unsupported\n    at SourceD.scala:275 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n"
            ); // @[SourceD.scala 275:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(s4_full & s4_need_pb & s4_pdata_corrupt)) & _T_9) begin
          $fatal; // @[SourceD.scala 275:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  busy = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  s1_block_r = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  s1_counter = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  s1_req_reg_prio_0 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  s1_req_reg_prio_2 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  s1_req_reg_opcode = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  s1_req_reg_param = _RAND_6[2:0];
  _RAND_7 = {1{`RANDOM}};
  s1_req_reg_size = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  s1_req_reg_source = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  s1_req_reg_offset = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  s1_req_reg_put = _RAND_10[5:0];
  _RAND_11 = {1{`RANDOM}};
  s1_req_reg_set = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  s1_req_reg_sink = _RAND_12[4:0];
  _RAND_13 = {1{`RANDOM}};
  s1_req_reg_way = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  s1_req_reg_bad = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  s2_full = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  s3_full = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  s3_retires = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  s4_full = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  s4_need_bs = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  s3_valid_d = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  s2_valid_pb = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  s2_req_prio_0 = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  s1_latch_bypass = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  s1_bypass_r = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  s2_req_set = _RAND_25[1:0];
  _RAND_26 = {1{`RANDOM}};
  s2_req_way = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  s2_beat = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  s2_retires = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  s3_req_set = _RAND_29[1:0];
  _RAND_30 = {1{`RANDOM}};
  s3_req_way = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  s3_beat = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  s4_req_set = _RAND_32[1:0];
  _RAND_33 = {1{`RANDOM}};
  s4_req_way = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  s4_beat = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  queue_io_enq_valid_REG = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  queue_io_enq_valid_REG_1 = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  s2_bypass = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  s2_req_prio_2 = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  s2_req_opcode = _RAND_39[2:0];
  _RAND_40 = {1{`RANDOM}};
  s2_req_param = _RAND_40[2:0];
  _RAND_41 = {1{`RANDOM}};
  s2_req_size = _RAND_41[2:0];
  _RAND_42 = {1{`RANDOM}};
  s2_req_source = _RAND_42[2:0];
  _RAND_43 = {1{`RANDOM}};
  s2_req_put = _RAND_43[5:0];
  _RAND_44 = {1{`RANDOM}};
  s2_req_sink = _RAND_44[4:0];
  _RAND_45 = {1{`RANDOM}};
  s2_req_bad = _RAND_45[0:0];
  _RAND_46 = {1{`RANDOM}};
  s2_last = _RAND_46[0:0];
  _RAND_47 = {1{`RANDOM}};
  s2_need_r = _RAND_47[0:0];
  _RAND_48 = {1{`RANDOM}};
  s2_need_pb = _RAND_48[0:0];
  _RAND_49 = {1{`RANDOM}};
  s2_need_d = _RAND_49[0:0];
  _RAND_50 = {2{`RANDOM}};
  s2_pdata_r_data = _RAND_50[63:0];
  _RAND_51 = {1{`RANDOM}};
  s2_pdata_r_mask = _RAND_51[7:0];
  _RAND_52 = {1{`RANDOM}};
  s2_pdata_r_corrupt = _RAND_52[0:0];
  _RAND_53 = {1{`RANDOM}};
  s3_bypass = _RAND_53[0:0];
  _RAND_54 = {1{`RANDOM}};
  s3_req_prio_0 = _RAND_54[0:0];
  _RAND_55 = {1{`RANDOM}};
  s3_req_prio_2 = _RAND_55[0:0];
  _RAND_56 = {1{`RANDOM}};
  s3_req_opcode = _RAND_56[2:0];
  _RAND_57 = {1{`RANDOM}};
  s3_req_param = _RAND_57[2:0];
  _RAND_58 = {1{`RANDOM}};
  s3_req_size = _RAND_58[2:0];
  _RAND_59 = {1{`RANDOM}};
  s3_req_source = _RAND_59[2:0];
  _RAND_60 = {1{`RANDOM}};
  s3_req_sink = _RAND_60[4:0];
  _RAND_61 = {1{`RANDOM}};
  s3_req_bad = _RAND_61[0:0];
  _RAND_62 = {2{`RANDOM}};
  s3_pdata_data = _RAND_62[63:0];
  _RAND_63 = {1{`RANDOM}};
  s3_pdata_mask = _RAND_63[7:0];
  _RAND_64 = {1{`RANDOM}};
  s3_pdata_corrupt = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  s3_need_bs = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  s3_need_r = _RAND_66[0:0];
  _RAND_67 = {1{`RANDOM}};
  s3_bypass_data_REG = _RAND_67[0:0];
  _RAND_68 = {2{`RANDOM}};
  s3_bypass_data_REG_1 = _RAND_68[63:0];
  _RAND_69 = {1{`RANDOM}};
  s4_need_pb = _RAND_69[0:0];
  _RAND_70 = {1{`RANDOM}};
  s4_req_prio_2 = _RAND_70[0:0];
  _RAND_71 = {1{`RANDOM}};
  s4_req_param = _RAND_71[2:0];
  _RAND_72 = {1{`RANDOM}};
  s4_adjusted_opcode = _RAND_72[2:0];
  _RAND_73 = {2{`RANDOM}};
  s4_pdata_data = _RAND_73[63:0];
  _RAND_74 = {1{`RANDOM}};
  s4_pdata_mask = _RAND_74[7:0];
  _RAND_75 = {1{`RANDOM}};
  s4_pdata_corrupt = _RAND_75[0:0];
  _RAND_76 = {2{`RANDOM}};
  s4_rdata = _RAND_76[63:0];
  _RAND_77 = {1{`RANDOM}};
  s5_req_set = _RAND_77[1:0];
  _RAND_78 = {1{`RANDOM}};
  s5_req_way = _RAND_78[0:0];
  _RAND_79 = {1{`RANDOM}};
  s5_beat = _RAND_79[0:0];
  _RAND_80 = {2{`RANDOM}};
  s5_dat = _RAND_80[63:0];
  _RAND_81 = {1{`RANDOM}};
  s6_req_set = _RAND_81[1:0];
  _RAND_82 = {1{`RANDOM}};
  s6_req_way = _RAND_82[0:0];
  _RAND_83 = {1{`RANDOM}};
  s6_beat = _RAND_83[0:0];
  _RAND_84 = {2{`RANDOM}};
  s6_dat = _RAND_84[63:0];
  _RAND_85 = {2{`RANDOM}};
  s7_dat = _RAND_85[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_24(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input  [2:0] io_enq_bits_sink,
  output       io_deq_valid,
  output [2:0] io_deq_bits_sink
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_sink [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_sink_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
  assign ram_sink_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_sink_MPORT_data = io_enq_bits_sink;
  assign ram_sink_MPORT_addr = enq_ptr_value;
  assign ram_sink_MPORT_mask = 1'h1;
  assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
      ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (io_deq_valid) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != io_deq_valid) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_sink[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  enq_ptr_value = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  deq_ptr_value = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SourceE(
  input        clock,
  input        reset,
  output       io_req_ready,
  input        io_req_valid,
  input  [2:0] io_req_bits_sink,
  output       io_e_valid,
  output [2:0] io_e_bits_sink
);
  wire  io_e_q_clock; // @[Decoupled.scala 377:21]
  wire  io_e_q_reset; // @[Decoupled.scala 377:21]
  wire  io_e_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  io_e_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] io_e_q_io_enq_bits_sink; // @[Decoupled.scala 377:21]
  wire  io_e_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] io_e_q_io_deq_bits_sink; // @[Decoupled.scala 377:21]
  Queue_24 io_e_q ( // @[Decoupled.scala 377:21]
    .clock(io_e_q_clock),
    .reset(io_e_q_reset),
    .io_enq_ready(io_e_q_io_enq_ready),
    .io_enq_valid(io_e_q_io_enq_valid),
    .io_enq_bits_sink(io_e_q_io_enq_bits_sink),
    .io_deq_valid(io_e_q_io_deq_valid),
    .io_deq_bits_sink(io_e_q_io_deq_bits_sink)
  );
  assign io_req_ready = io_e_q_io_enq_ready; // @[SourceE.scala 38:15 Decoupled.scala 381:17]
  assign io_e_valid = io_e_q_io_deq_valid; // @[SourceE.scala 39:8]
  assign io_e_bits_sink = io_e_q_io_deq_bits_sink; // @[SourceE.scala 39:8]
  assign io_e_q_clock = clock;
  assign io_e_q_reset = reset;
  assign io_e_q_io_enq_valid = io_req_valid; // @[SourceE.scala 38:15 42:11]
  assign io_e_q_io_enq_bits_sink = io_req_bits_sink; // @[SourceE.scala 38:15 44:15]
endmodule
module ListBuffer(
  input         clock,
  input         reset,
  output        io_push_ready,
  input         io_push_valid,
  input  [5:0]  io_push_bits_index,
  input  [63:0] io_push_bits_data_data,
  input  [7:0]  io_push_bits_data_mask,
  input         io_push_bits_data_corrupt,
  output [39:0] io_valid,
  input         io_pop_valid,
  input  [5:0]  io_pop_bits,
  output [63:0] io_data_data,
  output [7:0]  io_data_mask,
  output        io_data_corrupt
);
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_6;
  reg [63:0] _RAND_8;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_12;
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_7;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_11;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_13;
  reg [63:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  reg [5:0] head [0:39]; // @[ListBuffer.scala 46:18]
  wire  head_pop_head_en; // @[ListBuffer.scala 46:18]
  wire [5:0] head_pop_head_addr; // @[ListBuffer.scala 46:18]
  wire [5:0] head_pop_head_data; // @[ListBuffer.scala 46:18]
  wire [5:0] head_MPORT_2_data; // @[ListBuffer.scala 46:18]
  wire [5:0] head_MPORT_2_addr; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_2_mask; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_2_en; // @[ListBuffer.scala 46:18]
  wire [5:0] head_MPORT_6_data; // @[ListBuffer.scala 46:18]
  wire [5:0] head_MPORT_6_addr; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_6_mask; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_6_en; // @[ListBuffer.scala 46:18]
  reg [5:0] tail [0:39]; // @[ListBuffer.scala 47:18]
  wire  tail_push_tail_en; // @[ListBuffer.scala 47:18]
  wire [5:0] tail_push_tail_addr; // @[ListBuffer.scala 47:18]
  wire [5:0] tail_push_tail_data; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_4_en; // @[ListBuffer.scala 47:18]
  wire [5:0] tail_MPORT_4_addr; // @[ListBuffer.scala 47:18]
  wire [5:0] tail_MPORT_4_data; // @[ListBuffer.scala 47:18]
  wire [5:0] tail_MPORT_3_data; // @[ListBuffer.scala 47:18]
  wire [5:0] tail_MPORT_3_addr; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_3_mask; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_3_en; // @[ListBuffer.scala 47:18]
  reg [5:0] next [0:39]; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_5_en; // @[ListBuffer.scala 49:18]
  wire [5:0] next_MPORT_5_addr; // @[ListBuffer.scala 49:18]
  wire [5:0] next_MPORT_5_data; // @[ListBuffer.scala 49:18]
  wire [5:0] next_MPORT_1_data; // @[ListBuffer.scala 49:18]
  wire [5:0] next_MPORT_1_addr; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_1_mask; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_1_en; // @[ListBuffer.scala 49:18]
  reg [63:0] data_data [0:39]; // @[ListBuffer.scala 50:18]
  wire  data_data_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [5:0] data_data_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [63:0] data_data_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [63:0] data_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [5:0] data_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_data_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_data_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [7:0] data_mask [0:39]; // @[ListBuffer.scala 50:18]
  wire  data_mask_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [5:0] data_mask_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [7:0] data_mask_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [7:0] data_mask_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [5:0] data_mask_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_mask_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_mask_MPORT_en; // @[ListBuffer.scala 50:18]
  reg  data_corrupt [0:39]; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [5:0] data_corrupt_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [5:0] data_corrupt_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [39:0] valid; // @[ListBuffer.scala 45:22]
  reg [39:0] used; // @[ListBuffer.scala 48:22]
  wire [39:0] _freeOH_T = ~used; // @[ListBuffer.scala 52:25]
  wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_1[39:0]; // @[package.scala 244:43]
  wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_4[39:0]; // @[package.scala 244:43]
  wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_7[39:0]; // @[package.scala 244:43]
  wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_10[39:0]; // @[package.scala 244:43]
  wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_13[39:0]; // @[package.scala 244:43]
  wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_16[39:0]; // @[package.scala 244:43]
  wire [40:0] _freeOH_T_20 = {_freeOH_T_18, 1'h0}; // @[ListBuffer.scala 52:32]
  wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[ListBuffer.scala 52:16]
  wire [40:0] _GEN_41 = {{1'd0}, _freeOH_T}; // @[ListBuffer.scala 52:38]
  wire [40:0] freeOH = _freeOH_T_21 & _GEN_41; // @[ListBuffer.scala 52:38]
  wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala 30:18]
  wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T = |freeIdx_hi; // @[OneHot.scala 32:14]
  wire [31:0] _GEN_42 = {{23'd0}, freeIdx_hi}; // @[OneHot.scala 32:28]
  wire [31:0] _freeIdx_T_1 = _GEN_42 | freeIdx_lo; // @[OneHot.scala 32:28]
  wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala 30:18]
  wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala 32:14]
  wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala 32:28]
  wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala 30:18]
  wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala 32:14]
  wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala 32:28]
  wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala 32:14]
  wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala 32:28]
  wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala 32:14]
  wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala 32:28]
  wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2,_freeIdx_T_4,_freeIdx_T_6,_freeIdx_T_8,_freeIdx_T_9[1]}; // @[Cat.scala 33:92]
  wire [5:0] freeIdx = {_freeIdx_T,_freeIdx_T_2,_freeIdx_T_4,_freeIdx_T_6,_freeIdx_T_8,_freeIdx_T_9[1]}; // @[Cat.scala 33:92]
  wire [39:0] _push_valid_T = valid >> io_push_bits_index; // @[ListBuffer.scala 61:25]
  wire  push_valid = _push_valid_T[0]; // @[ListBuffer.scala 61:25]
  wire  _T = io_push_ready & io_push_valid; // @[Decoupled.scala 52:35]
  wire [63:0] _valid_set_T = 64'h1 << io_push_bits_index; // @[OneHot.scala 64:12]
  wire  _GEN_7 = push_valid ? 1'h0 : 1'h1; // @[ListBuffer.scala 46:18 68:23]
  wire [39:0] valid_set = _T ? _valid_set_T[39:0] : 40'h0; // @[ListBuffer.scala 64:25 65:15]
  wire [40:0] _GEN_11 = _T ? freeOH : 41'h0; // @[ListBuffer.scala 64:25 66:14]
  wire  _GEN_21 = _T & push_valid; // @[ListBuffer.scala 49:18 64:25]
  wire [39:0] _T_2 = io_valid >> io_pop_bits; // @[ListBuffer.scala 84:39]
  wire [5:0] used_clr_shiftAmount = head_pop_head_data; // @[OneHot.scala 63:49]
  wire [63:0] _used_clr_T = 64'h1 << used_clr_shiftAmount; // @[OneHot.scala 64:12]
  wire [63:0] _valid_clr_T = 64'h1 << io_pop_bits; // @[OneHot.scala 64:12]
  wire [39:0] _GEN_30 = head_pop_head_data == tail_MPORT_4_data ? _valid_clr_T[39:0] : 40'h0; // @[ListBuffer.scala 88:48 89:17]
  wire  _T_12 = _GEN_21 & tail_push_tail_data == head_pop_head_data; // @[ListBuffer.scala 91:62]
  wire [39:0] used_clr = io_pop_valid ? _used_clr_T[39:0] : 40'h0; // @[ListBuffer.scala 86:24 87:14]
  wire [39:0] valid_clr = io_pop_valid ? _GEN_30 : 40'h0; // @[ListBuffer.scala 86:24]
  wire [39:0] _used_T = ~used_clr; // @[ListBuffer.scala 96:23]
  wire [39:0] _used_T_1 = used & _used_T; // @[ListBuffer.scala 96:21]
  wire [39:0] used_set = _GEN_11[39:0];
  wire [39:0] _used_T_2 = _used_T_1 | used_set; // @[ListBuffer.scala 96:35]
  wire [39:0] _valid_T = ~valid_clr; // @[ListBuffer.scala 97:23]
  wire [39:0] _valid_T_1 = valid & _valid_T; // @[ListBuffer.scala 97:21]
  wire [39:0] _valid_T_2 = _valid_T_1 | valid_set; // @[ListBuffer.scala 97:35]
  assign head_pop_head_en = 1'h1;
  assign head_pop_head_addr = io_pop_bits;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign head_pop_head_data = head[head_pop_head_addr]; // @[ListBuffer.scala 46:18]
  `else
  assign head_pop_head_data = head_pop_head_addr >= 6'h28 ? _RAND_1[5:0] : head[head_pop_head_addr]; // @[ListBuffer.scala 46:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign head_MPORT_2_data = {_freeIdx_T,_freeIdx_T_14};
  assign head_MPORT_2_addr = io_push_bits_index;
  assign head_MPORT_2_mask = 1'h1;
  assign head_MPORT_2_en = _T & _GEN_7;
  assign head_MPORT_6_data = _T_12 ? freeIdx : next_MPORT_5_data;
  assign head_MPORT_6_addr = io_pop_bits;
  assign head_MPORT_6_mask = 1'h1;
  assign head_MPORT_6_en = io_pop_valid;
  assign tail_push_tail_en = 1'h1;
  assign tail_push_tail_addr = io_push_bits_index;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tail_push_tail_data = tail[tail_push_tail_addr]; // @[ListBuffer.scala 47:18]
  `else
  assign tail_push_tail_data = tail_push_tail_addr >= 6'h28 ? _RAND_3[5:0] : tail[tail_push_tail_addr]; // @[ListBuffer.scala 47:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tail_MPORT_4_en = io_pop_valid;
  assign tail_MPORT_4_addr = io_pop_bits;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tail_MPORT_4_data = tail[tail_MPORT_4_addr]; // @[ListBuffer.scala 47:18]
  `else
  assign tail_MPORT_4_data = tail_MPORT_4_addr >= 6'h28 ? _RAND_4[5:0] : tail[tail_MPORT_4_addr]; // @[ListBuffer.scala 47:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tail_MPORT_3_data = {_freeIdx_T,_freeIdx_T_14};
  assign tail_MPORT_3_addr = io_push_bits_index;
  assign tail_MPORT_3_mask = 1'h1;
  assign tail_MPORT_3_en = io_push_ready & io_push_valid;
  assign next_MPORT_5_en = io_pop_valid;
  assign next_MPORT_5_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign next_MPORT_5_data = next[next_MPORT_5_addr]; // @[ListBuffer.scala 49:18]
  `else
  assign next_MPORT_5_data = next_MPORT_5_addr >= 6'h28 ? _RAND_6[5:0] : next[next_MPORT_5_addr]; // @[ListBuffer.scala 49:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign next_MPORT_1_data = {_freeIdx_T,_freeIdx_T_14};
  assign next_MPORT_1_addr = tail_push_tail_data;
  assign next_MPORT_1_mask = 1'h1;
  assign next_MPORT_1_en = _T & push_valid;
  assign data_data_io_data_MPORT_en = 1'h1;
  assign data_data_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_data_io_data_MPORT_data = data_data[data_data_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_data_io_data_MPORT_data = data_data_io_data_MPORT_addr >= 6'h28 ? _RAND_8[63:0] :
    data_data[data_data_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_data_MPORT_data = io_push_bits_data_data;
  assign data_data_MPORT_addr = {_freeIdx_T,_freeIdx_T_14};
  assign data_data_MPORT_mask = 1'h1;
  assign data_data_MPORT_en = io_push_ready & io_push_valid;
  assign data_mask_io_data_MPORT_en = 1'h1;
  assign data_mask_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_mask_io_data_MPORT_data = data_mask[data_mask_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_mask_io_data_MPORT_data = data_mask_io_data_MPORT_addr >= 6'h28 ? _RAND_10[7:0] :
    data_mask[data_mask_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_mask_MPORT_data = io_push_bits_data_mask;
  assign data_mask_MPORT_addr = {_freeIdx_T,_freeIdx_T_14};
  assign data_mask_MPORT_mask = 1'h1;
  assign data_mask_MPORT_en = io_push_ready & io_push_valid;
  assign data_corrupt_io_data_MPORT_en = 1'h1;
  assign data_corrupt_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_corrupt_io_data_MPORT_data = data_corrupt[data_corrupt_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_corrupt_io_data_MPORT_data = data_corrupt_io_data_MPORT_addr >= 6'h28 ? _RAND_12[0:0] :
    data_corrupt[data_corrupt_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_corrupt_MPORT_data = io_push_bits_data_corrupt;
  assign data_corrupt_MPORT_addr = {_freeIdx_T,_freeIdx_T_14};
  assign data_corrupt_MPORT_mask = 1'h1;
  assign data_corrupt_MPORT_en = io_push_ready & io_push_valid;
  assign io_push_ready = ~(&used); // @[ListBuffer.scala 63:20]
  assign io_valid = valid; // @[ListBuffer.scala 81:12]
  assign io_data_data = data_data_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_mask = data_mask_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_corrupt = data_corrupt_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  always @(posedge clock) begin
    if (head_MPORT_2_en & head_MPORT_2_mask) begin
      head[head_MPORT_2_addr] <= head_MPORT_2_data; // @[ListBuffer.scala 46:18]
    end
    if (head_MPORT_6_en & head_MPORT_6_mask) begin
      head[head_MPORT_6_addr] <= head_MPORT_6_data; // @[ListBuffer.scala 46:18]
    end
    if (tail_MPORT_3_en & tail_MPORT_3_mask) begin
      tail[tail_MPORT_3_addr] <= tail_MPORT_3_data; // @[ListBuffer.scala 47:18]
    end
    if (next_MPORT_1_en & next_MPORT_1_mask) begin
      next[next_MPORT_1_addr] <= next_MPORT_1_data; // @[ListBuffer.scala 49:18]
    end
    if (data_data_MPORT_en & data_data_MPORT_mask) begin
      data_data[data_data_MPORT_addr] <= data_data_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_mask_MPORT_en & data_mask_MPORT_mask) begin
      data_mask[data_mask_MPORT_addr] <= data_mask_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_corrupt_MPORT_en & data_corrupt_MPORT_mask) begin
      data_corrupt[data_corrupt_MPORT_addr] <= data_corrupt_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (reset) begin // @[ListBuffer.scala 45:22]
      valid <= 40'h0; // @[ListBuffer.scala 45:22]
    end else begin
      valid <= _valid_T_2;
    end
    if (reset) begin // @[ListBuffer.scala 48:22]
      used <= 40'h0; // @[ListBuffer.scala 48:22]
    end else begin
      used <= _used_T_2;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_pop_valid | _T_2[0])) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ListBuffer.scala:84 assert (!io.pop.fire() || (io.valid)(io.pop.bits))\n"); // @[ListBuffer.scala 84:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_pop_valid | _T_2[0]) & ~reset) begin
          $fatal; // @[ListBuffer.scala 84:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  _RAND_1 = {1{`RANDOM}};
  _RAND_3 = {1{`RANDOM}};
  _RAND_4 = {1{`RANDOM}};
  _RAND_6 = {1{`RANDOM}};
  _RAND_8 = {2{`RANDOM}};
  _RAND_10 = {1{`RANDOM}};
  _RAND_12 = {1{`RANDOM}};
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 40; initvar = initvar+1)
    head[initvar] = _RAND_0[5:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 40; initvar = initvar+1)
    tail[initvar] = _RAND_2[5:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 40; initvar = initvar+1)
    next[initvar] = _RAND_5[5:0];
  _RAND_7 = {2{`RANDOM}};
  for (initvar = 0; initvar < 40; initvar = initvar+1)
    data_data[initvar] = _RAND_7[63:0];
  _RAND_9 = {1{`RANDOM}};
  for (initvar = 0; initvar < 40; initvar = initvar+1)
    data_mask[initvar] = _RAND_9[7:0];
  _RAND_11 = {1{`RANDOM}};
  for (initvar = 0; initvar < 40; initvar = initvar+1)
    data_corrupt[initvar] = _RAND_11[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_13 = {2{`RANDOM}};
  valid = _RAND_13[39:0];
  _RAND_14 = {2{`RANDOM}};
  used = _RAND_14[39:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SinkA(
  input         clock,
  input         reset,
  input         io_req_ready,
  output        io_req_valid,
  output [2:0]  io_req_bits_opcode,
  output [2:0]  io_req_bits_param,
  output [2:0]  io_req_bits_size,
  output [2:0]  io_req_bits_source,
  output [25:0] io_req_bits_tag,
  output [3:0]  io_req_bits_offset,
  output [5:0]  io_req_bits_put,
  output [1:0]  io_req_bits_set,
  output        io_a_ready,
  input         io_a_valid,
  input  [2:0]  io_a_bits_opcode,
  input  [2:0]  io_a_bits_param,
  input  [2:0]  io_a_bits_size,
  input  [2:0]  io_a_bits_source,
  input  [31:0] io_a_bits_address,
  input  [7:0]  io_a_bits_mask,
  input  [63:0] io_a_bits_data,
  input         io_a_bits_corrupt,
  output        io_pb_pop_ready,
  input         io_pb_pop_valid,
  input  [5:0]  io_pb_pop_bits_index,
  input         io_pb_pop_bits_last,
  output [63:0] io_pb_beat_data,
  output [7:0]  io_pb_beat_mask,
  output        io_pb_beat_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  putbuffer_clock; // @[SinkA.scala 50:25]
  wire  putbuffer_reset; // @[SinkA.scala 50:25]
  wire  putbuffer_io_push_ready; // @[SinkA.scala 50:25]
  wire  putbuffer_io_push_valid; // @[SinkA.scala 50:25]
  wire [5:0] putbuffer_io_push_bits_index; // @[SinkA.scala 50:25]
  wire [63:0] putbuffer_io_push_bits_data_data; // @[SinkA.scala 50:25]
  wire [7:0] putbuffer_io_push_bits_data_mask; // @[SinkA.scala 50:25]
  wire  putbuffer_io_push_bits_data_corrupt; // @[SinkA.scala 50:25]
  wire [39:0] putbuffer_io_valid; // @[SinkA.scala 50:25]
  wire  putbuffer_io_pop_valid; // @[SinkA.scala 50:25]
  wire [5:0] putbuffer_io_pop_bits; // @[SinkA.scala 50:25]
  wire [63:0] putbuffer_io_data_data; // @[SinkA.scala 50:25]
  wire [7:0] putbuffer_io_data_mask; // @[SinkA.scala 50:25]
  wire  putbuffer_io_data_corrupt; // @[SinkA.scala 50:25]
  reg [39:0] lists; // @[SinkA.scala 51:22]
  reg  first_counter; // @[Edges.scala 228:27]
  wire  first = ~first_counter; // @[Edges.scala 230:25]
  wire  _T_3 = io_a_valid & first; // @[SinkA.scala 80:17]
  wire  hasData = ~io_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  req_block = first & ~io_req_ready; // @[SinkA.scala 69:25]
  wire  _T_5 = ~req_block; // @[SinkA.scala 80:40]
  wire  buf_block = hasData & ~putbuffer_io_push_ready; // @[SinkA.scala 70:27]
  wire  _T_7 = ~buf_block; // @[SinkA.scala 80:54]
  wire [39:0] _freeOH_T = ~lists; // @[SinkA.scala 58:25]
  wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_1[39:0]; // @[package.scala 244:43]
  wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_4[39:0]; // @[package.scala 244:43]
  wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_7[39:0]; // @[package.scala 244:43]
  wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_10[39:0]; // @[package.scala 244:43]
  wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_13[39:0]; // @[package.scala 244:43]
  wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala 244:48]
  wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_16[39:0]; // @[package.scala 244:43]
  wire [40:0] _freeOH_T_20 = {_freeOH_T_18, 1'h0}; // @[SinkA.scala 58:33]
  wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[SinkA.scala 58:16]
  wire [40:0] _GEN_4 = {{1'd0}, _freeOH_T}; // @[SinkA.scala 58:39]
  wire [40:0] freeOH = _freeOH_T_21 & _GEN_4; // @[SinkA.scala 58:39]
  wire [40:0] _GEN_1 = io_a_valid & first & hasData & ~req_block & ~buf_block ? freeOH : 41'h0; // @[SinkA.scala 80:{66,78}]
  wire [39:0] lists_set = _GEN_1[39:0];
  wire [39:0] _lists_T = lists | lists_set; // @[SinkA.scala 55:19]
  wire  _T_9 = io_pb_pop_ready & io_pb_pop_valid; // @[Decoupled.scala 52:35]
  wire [63:0] _lists_clr_T = 64'h1 << io_pb_pop_bits_index; // @[OneHot.scala 64:12]
  wire [39:0] lists_clr = _T_9 & io_pb_pop_bits_last ? _lists_clr_T[39:0] : 40'h0; // @[SinkA.scala 107:50 108:15]
  wire [39:0] _lists_T_1 = ~lists_clr; // @[SinkA.scala 55:34]
  wire [39:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkA.scala 55:32]
  wire  free = ~(&lists); // @[SinkA.scala 57:14]
  wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala 30:18]
  wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T = |freeIdx_hi; // @[OneHot.scala 32:14]
  wire [31:0] _GEN_5 = {{23'd0}, freeIdx_hi}; // @[OneHot.scala 32:28]
  wire [31:0] _freeIdx_T_1 = _GEN_5 | freeIdx_lo; // @[OneHot.scala 32:28]
  wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala 30:18]
  wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala 32:14]
  wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala 32:28]
  wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala 30:18]
  wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala 32:14]
  wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala 32:28]
  wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala 32:14]
  wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala 32:28]
  wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala 32:14]
  wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala 32:28]
  wire [5:0] freeIdx = {_freeIdx_T,_freeIdx_T_2,_freeIdx_T_4,_freeIdx_T_6,_freeIdx_T_8,_freeIdx_T_9[1]}; // @[Cat.scala 33:92]
  wire  _first_T = io_a_ready & io_a_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _first_beats1_decode_T_1 = 11'hf << io_a_bits_size; // @[package.scala 234:77]
  wire [3:0] _first_beats1_decode_T_3 = ~_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  first_beats1_decode = _first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  first_beats1 = hasData & first_beats1_decode; // @[Edges.scala 220:14]
  wire  first_counter1 = first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  set_block = hasData & first & ~free; // @[SinkA.scala 71:36]
  wire  _io_a_ready_T_3 = ~set_block; // @[SinkA.scala 77:42]
  wire [7:0] offset_lo_lo = {io_a_bits_address[7],io_a_bits_address[6],io_a_bits_address[5],io_a_bits_address[4],
    io_a_bits_address[3],io_a_bits_address[2],io_a_bits_address[1],io_a_bits_address[0]}; // @[Cat.scala 33:92]
  wire [15:0] offset_lo = {io_a_bits_address[15],io_a_bits_address[14],io_a_bits_address[13],io_a_bits_address[12],
    io_a_bits_address[11],io_a_bits_address[10],io_a_bits_address[9],io_a_bits_address[8],offset_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] offset_hi_lo = {io_a_bits_address[23],io_a_bits_address[22],io_a_bits_address[21],io_a_bits_address[20],
    io_a_bits_address[19],io_a_bits_address[18],io_a_bits_address[17],io_a_bits_address[16]}; // @[Cat.scala 33:92]
  wire [31:0] offset = {io_a_bits_address[31],io_a_bits_address[30],io_a_bits_address[29],io_a_bits_address[28],
    io_a_bits_address[27],io_a_bits_address[26],io_a_bits_address[25],io_a_bits_address[24],offset_hi_lo,offset_lo}; // @[Cat.scala 33:92]
  wire [27:0] set = offset[31:4]; // @[Parameters.scala 212:22]
  reg [5:0] put_r; // @[Reg.scala 19:16]
  wire [39:0] _io_pb_pop_ready_T = putbuffer_io_valid >> io_pb_pop_bits_index; // @[SinkA.scala 104:40]
  ListBuffer putbuffer ( // @[SinkA.scala 50:25]
    .clock(putbuffer_clock),
    .reset(putbuffer_reset),
    .io_push_ready(putbuffer_io_push_ready),
    .io_push_valid(putbuffer_io_push_valid),
    .io_push_bits_index(putbuffer_io_push_bits_index),
    .io_push_bits_data_data(putbuffer_io_push_bits_data_data),
    .io_push_bits_data_mask(putbuffer_io_push_bits_data_mask),
    .io_push_bits_data_corrupt(putbuffer_io_push_bits_data_corrupt),
    .io_valid(putbuffer_io_valid),
    .io_pop_valid(putbuffer_io_pop_valid),
    .io_pop_bits(putbuffer_io_pop_bits),
    .io_data_data(putbuffer_io_data_data),
    .io_data_mask(putbuffer_io_data_mask),
    .io_data_corrupt(putbuffer_io_data_corrupt)
  );
  assign io_req_valid = _T_3 & _T_7 & _io_a_ready_T_3; // @[SinkA.scala 78:50]
  assign io_req_bits_opcode = io_a_bits_opcode; // @[SinkA.scala 87:22]
  assign io_req_bits_param = io_a_bits_param; // @[SinkA.scala 88:22]
  assign io_req_bits_size = io_a_bits_size; // @[SinkA.scala 89:22]
  assign io_req_bits_source = io_a_bits_source; // @[SinkA.scala 90:22]
  assign io_req_bits_tag = set[27:2]; // @[Parameters.scala 213:19]
  assign io_req_bits_offset = offset[3:0]; // @[Parameters.scala 214:50]
  assign io_req_bits_put = first ? freeIdx : put_r; // @[SinkA.scala 83:16]
  assign io_req_bits_set = set[1:0]; // @[Parameters.scala 214:28]
  assign io_a_ready = _T_5 & _T_7 & ~set_block; // @[SinkA.scala 77:39]
  assign io_pb_pop_ready = _io_pb_pop_ready_T[0]; // @[SinkA.scala 104:40]
  assign io_pb_beat_data = putbuffer_io_data_data; // @[SinkA.scala 105:14]
  assign io_pb_beat_mask = putbuffer_io_data_mask; // @[SinkA.scala 105:14]
  assign io_pb_beat_corrupt = putbuffer_io_data_corrupt; // @[SinkA.scala 105:14]
  assign putbuffer_clock = clock;
  assign putbuffer_reset = reset;
  assign putbuffer_io_push_valid = io_a_valid & hasData & _T_5 & _io_a_ready_T_3; // @[SinkA.scala 79:63]
  assign putbuffer_io_push_bits_index = first ? freeIdx : put_r; // @[SinkA.scala 83:16]
  assign putbuffer_io_push_bits_data_data = io_a_bits_data; // @[SinkA.scala 97:39]
  assign putbuffer_io_push_bits_data_mask = io_a_bits_mask; // @[SinkA.scala 98:39]
  assign putbuffer_io_push_bits_data_corrupt = io_a_bits_corrupt; // @[SinkA.scala 99:39]
  assign putbuffer_io_pop_valid = io_pb_pop_ready & io_pb_pop_valid; // @[Decoupled.scala 52:35]
  assign putbuffer_io_pop_bits = io_pb_pop_bits_index; // @[SinkA.scala 102:25]
  always @(posedge clock) begin
    if (reset) begin // @[SinkA.scala 51:22]
      lists <= 40'h0; // @[SinkA.scala 51:22]
    end else begin
      lists <= _lists_T_2; // @[SinkA.scala 55:9]
    end
    if (reset) begin // @[Edges.scala 228:27]
      first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_first_T) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        first_counter <= first_beats1;
      end else begin
        first_counter <= first_counter1;
      end
    end
    if (first) begin // @[Reg.scala 20:18]
      put_r <= freeIdx; // @[Reg.scala 20:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lists = _RAND_0[39:0];
  _RAND_1 = {1{`RANDOM}};
  first_counter = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  put_r = _RAND_2[5:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_26(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [31:0] io_enq_bits_address,
  input  [63:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [2:0]  io_deq_bits_source,
  output [31:0] io_deq_bits_address,
  output [63:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_source [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_address [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 275:95]
  reg [63:0] ram_data [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_source_MPORT_data = 3'h3;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = enq_ptr_value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[31:0];
  _RAND_5 = {2{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_5[63:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  enq_ptr_value = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  deq_ptr_value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  maybe_full = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_27(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input        io_enq_bits_noop,
  input        io_enq_bits_way,
  input  [1:0] io_enq_bits_set,
  input        io_enq_bits_beat,
  input        io_deq_ready,
  output       io_deq_valid,
  output       io_deq_bits_noop,
  output       io_deq_bits_way,
  output [1:0] io_deq_bits_set,
  output       io_deq_bits_beat,
  output       io_deq_bits_mask
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  reg  ram_noop [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_noop_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_noop_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_noop_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_noop_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_noop_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_noop_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_noop_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_way [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_way_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_way_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_way_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_way_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_way_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_way_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_way_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_set [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_set_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_set_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_set_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_set_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_set_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_set_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_set_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_beat [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_beat_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_beat_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_beat_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_beat_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_beat_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_beat_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_beat_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_mask [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_noop_io_deq_bits_MPORT_en = 1'h1;
  assign ram_noop_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_noop_io_deq_bits_MPORT_data = ram_noop[ram_noop_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_noop_MPORT_data = io_enq_bits_noop;
  assign ram_noop_MPORT_addr = 1'h0;
  assign ram_noop_MPORT_mask = 1'h1;
  assign ram_noop_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_way_io_deq_bits_MPORT_en = 1'h1;
  assign ram_way_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_way_io_deq_bits_MPORT_data = ram_way[ram_way_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_way_MPORT_data = io_enq_bits_way;
  assign ram_way_MPORT_addr = 1'h0;
  assign ram_way_MPORT_mask = 1'h1;
  assign ram_way_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_set_io_deq_bits_MPORT_en = 1'h1;
  assign ram_set_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_set_io_deq_bits_MPORT_data = ram_set[ram_set_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_set_MPORT_data = io_enq_bits_set;
  assign ram_set_MPORT_addr = 1'h0;
  assign ram_set_MPORT_mask = 1'h1;
  assign ram_set_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_beat_io_deq_bits_MPORT_en = 1'h1;
  assign ram_beat_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_beat_io_deq_bits_MPORT_data = ram_beat[ram_beat_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_beat_MPORT_data = io_enq_bits_beat;
  assign ram_beat_MPORT_addr = 1'h0;
  assign ram_beat_MPORT_mask = 1'h1;
  assign ram_beat_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_mask_MPORT_data = 1'h1;
  assign ram_mask_MPORT_addr = 1'h0;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = io_deq_ready | empty; // @[Decoupled.scala 305:16 325:{24,39}]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_noop = ram_noop_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_way = ram_way_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_set = ram_set_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_beat = ram_beat_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_noop_MPORT_en & ram_noop_MPORT_mask) begin
      ram_noop[ram_noop_MPORT_addr] <= ram_noop_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_way_MPORT_en & ram_way_MPORT_mask) begin
      ram_way[ram_way_MPORT_addr] <= ram_way_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_set_MPORT_en & ram_set_MPORT_mask) begin
      ram_set[ram_set_MPORT_addr] <= ram_set_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_beat_MPORT_en & ram_beat_MPORT_mask) begin
      ram_beat[ram_beat_MPORT_addr] <= ram_beat_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_noop[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_way[initvar] = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_set[initvar] = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_beat[initvar] = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_mask[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_5 = {1{`RANDOM}};
  maybe_full = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ListBuffer_1(
  input         clock,
  input         reset,
  output        io_push_ready,
  input         io_push_valid,
  input         io_push_bits_index,
  input  [63:0] io_push_bits_data_data,
  input         io_push_bits_data_corrupt,
  output [1:0]  io_valid,
  input         io_pop_valid,
  input         io_pop_bits,
  output [63:0] io_data_data,
  output        io_data_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] head [0:1]; // @[ListBuffer.scala 46:18]
  wire  head_pop_head_en; // @[ListBuffer.scala 46:18]
  wire  head_pop_head_addr; // @[ListBuffer.scala 46:18]
  wire [1:0] head_pop_head_data; // @[ListBuffer.scala 46:18]
  wire [1:0] head_MPORT_2_data; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_2_addr; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_2_mask; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_2_en; // @[ListBuffer.scala 46:18]
  wire [1:0] head_MPORT_6_data; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_6_addr; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_6_mask; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_6_en; // @[ListBuffer.scala 46:18]
  reg [1:0] tail [0:1]; // @[ListBuffer.scala 47:18]
  wire  tail_push_tail_en; // @[ListBuffer.scala 47:18]
  wire  tail_push_tail_addr; // @[ListBuffer.scala 47:18]
  wire [1:0] tail_push_tail_data; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_4_en; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_4_addr; // @[ListBuffer.scala 47:18]
  wire [1:0] tail_MPORT_4_data; // @[ListBuffer.scala 47:18]
  wire [1:0] tail_MPORT_3_data; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_3_addr; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_3_mask; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_3_en; // @[ListBuffer.scala 47:18]
  reg [1:0] next [0:3]; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_5_en; // @[ListBuffer.scala 49:18]
  wire [1:0] next_MPORT_5_addr; // @[ListBuffer.scala 49:18]
  wire [1:0] next_MPORT_5_data; // @[ListBuffer.scala 49:18]
  wire [1:0] next_MPORT_1_data; // @[ListBuffer.scala 49:18]
  wire [1:0] next_MPORT_1_addr; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_1_mask; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_1_en; // @[ListBuffer.scala 49:18]
  reg [63:0] data_data [0:3]; // @[ListBuffer.scala 50:18]
  wire  data_data_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [1:0] data_data_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [63:0] data_data_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [63:0] data_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [1:0] data_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_data_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_data_MPORT_en; // @[ListBuffer.scala 50:18]
  reg  data_corrupt [0:3]; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [1:0] data_corrupt_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [1:0] data_corrupt_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_corrupt_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [1:0] valid; // @[ListBuffer.scala 45:22]
  reg [3:0] used; // @[ListBuffer.scala 48:22]
  wire [3:0] _freeOH_T = ~used; // @[ListBuffer.scala 52:25]
  wire [4:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala 244:48]
  wire [3:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_1[3:0]; // @[package.scala 244:43]
  wire [5:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala 244:48]
  wire [3:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_4[3:0]; // @[package.scala 244:43]
  wire [4:0] _freeOH_T_8 = {_freeOH_T_6, 1'h0}; // @[ListBuffer.scala 52:32]
  wire [4:0] _freeOH_T_9 = ~_freeOH_T_8; // @[ListBuffer.scala 52:16]
  wire [4:0] _GEN_41 = {{1'd0}, _freeOH_T}; // @[ListBuffer.scala 52:38]
  wire [4:0] freeOH = _freeOH_T_9 & _GEN_41; // @[ListBuffer.scala 52:38]
  wire  freeIdx_hi = freeOH[4]; // @[OneHot.scala 30:18]
  wire [3:0] freeIdx_lo = freeOH[3:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T = |freeIdx_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_42 = {{3'd0}, freeIdx_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _freeIdx_T_1 = _GEN_42 | freeIdx_lo; // @[OneHot.scala 32:28]
  wire [1:0] freeIdx_hi_1 = _freeIdx_T_1[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] freeIdx_lo_1 = _freeIdx_T_1[1:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] freeIdx = {_freeIdx_T,_freeIdx_T_2,_freeIdx_T_3[1]}; // @[Cat.scala 33:92]
  wire [1:0] _push_valid_T = valid >> io_push_bits_index; // @[ListBuffer.scala 61:25]
  wire  push_valid = _push_valid_T[0]; // @[ListBuffer.scala 61:25]
  wire  _T = io_push_ready & io_push_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _valid_set_T = 2'h1 << io_push_bits_index; // @[OneHot.scala 64:12]
  wire  _GEN_7 = push_valid ? 1'h0 : 1'h1; // @[ListBuffer.scala 46:18 68:23]
  wire [1:0] valid_set = _T ? _valid_set_T : 2'h0; // @[ListBuffer.scala 64:25 65:15]
  wire [4:0] _GEN_11 = _T ? freeOH : 5'h0; // @[ListBuffer.scala 64:25 66:14]
  wire  _GEN_20 = _T & push_valid; // @[ListBuffer.scala 49:18 64:25]
  wire [1:0] _T_3 = io_valid >> io_pop_bits; // @[ListBuffer.scala 84:39]
  wire [1:0] used_clr_shiftAmount = head_pop_head_data; // @[OneHot.scala 63:49]
  wire [3:0] _used_clr_T = 4'h1 << used_clr_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] _valid_clr_T = 2'h1 << io_pop_bits; // @[OneHot.scala 64:12]
  wire [1:0] _GEN_30 = head_pop_head_data == tail_MPORT_4_data ? _valid_clr_T : 2'h0; // @[ListBuffer.scala 88:48 89:17]
  wire [2:0] _T_14 = _GEN_20 & tail_push_tail_data == head_pop_head_data ? freeIdx : {{1'd0}, next_MPORT_5_data}; // @[ListBuffer.scala 91:32]
  wire [3:0] used_clr = io_pop_valid ? _used_clr_T : 4'h0; // @[ListBuffer.scala 86:24 87:14]
  wire [1:0] valid_clr = io_pop_valid ? _GEN_30 : 2'h0; // @[ListBuffer.scala 86:24]
  wire [3:0] _used_T = ~used_clr; // @[ListBuffer.scala 96:23]
  wire [3:0] _used_T_1 = used & _used_T; // @[ListBuffer.scala 96:21]
  wire [3:0] used_set = _GEN_11[3:0];
  wire [3:0] _used_T_2 = _used_T_1 | used_set; // @[ListBuffer.scala 96:35]
  wire [1:0] _valid_T = ~valid_clr; // @[ListBuffer.scala 97:23]
  wire [1:0] _valid_T_1 = valid & _valid_T; // @[ListBuffer.scala 97:21]
  wire [1:0] _valid_T_2 = _valid_T_1 | valid_set; // @[ListBuffer.scala 97:35]
  assign head_pop_head_en = 1'h1;
  assign head_pop_head_addr = io_pop_bits;
  assign head_pop_head_data = head[head_pop_head_addr]; // @[ListBuffer.scala 46:18]
  assign head_MPORT_2_data = freeIdx[1:0];
  assign head_MPORT_2_addr = io_push_bits_index;
  assign head_MPORT_2_mask = 1'h1;
  assign head_MPORT_2_en = _T & _GEN_7;
  assign head_MPORT_6_data = _T_14[1:0];
  assign head_MPORT_6_addr = io_pop_bits;
  assign head_MPORT_6_mask = 1'h1;
  assign head_MPORT_6_en = io_pop_valid;
  assign tail_push_tail_en = 1'h1;
  assign tail_push_tail_addr = io_push_bits_index;
  assign tail_push_tail_data = tail[tail_push_tail_addr]; // @[ListBuffer.scala 47:18]
  assign tail_MPORT_4_en = io_pop_valid;
  assign tail_MPORT_4_addr = io_pop_bits;
  assign tail_MPORT_4_data = tail[tail_MPORT_4_addr]; // @[ListBuffer.scala 47:18]
  assign tail_MPORT_3_data = freeIdx[1:0];
  assign tail_MPORT_3_addr = io_push_bits_index;
  assign tail_MPORT_3_mask = 1'h1;
  assign tail_MPORT_3_en = io_push_ready & io_push_valid;
  assign next_MPORT_5_en = io_pop_valid;
  assign next_MPORT_5_addr = head_pop_head_data;
  assign next_MPORT_5_data = next[next_MPORT_5_addr]; // @[ListBuffer.scala 49:18]
  assign next_MPORT_1_data = freeIdx[1:0];
  assign next_MPORT_1_addr = tail_push_tail_data;
  assign next_MPORT_1_mask = 1'h1;
  assign next_MPORT_1_en = _T & push_valid;
  assign data_data_io_data_MPORT_en = 1'h1;
  assign data_data_io_data_MPORT_addr = head_pop_head_data;
  assign data_data_io_data_MPORT_data = data_data[data_data_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  assign data_data_MPORT_data = io_push_bits_data_data;
  assign data_data_MPORT_addr = freeIdx[1:0];
  assign data_data_MPORT_mask = 1'h1;
  assign data_data_MPORT_en = io_push_ready & io_push_valid;
  assign data_corrupt_io_data_MPORT_en = 1'h1;
  assign data_corrupt_io_data_MPORT_addr = head_pop_head_data;
  assign data_corrupt_io_data_MPORT_data = data_corrupt[data_corrupt_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  assign data_corrupt_MPORT_data = io_push_bits_data_corrupt;
  assign data_corrupt_MPORT_addr = freeIdx[1:0];
  assign data_corrupt_MPORT_mask = 1'h1;
  assign data_corrupt_MPORT_en = io_push_ready & io_push_valid;
  assign io_push_ready = ~(&used); // @[ListBuffer.scala 63:20]
  assign io_valid = valid; // @[ListBuffer.scala 81:12]
  assign io_data_data = data_data_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_corrupt = data_corrupt_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  always @(posedge clock) begin
    if (head_MPORT_2_en & head_MPORT_2_mask) begin
      head[head_MPORT_2_addr] <= head_MPORT_2_data; // @[ListBuffer.scala 46:18]
    end
    if (head_MPORT_6_en & head_MPORT_6_mask) begin
      head[head_MPORT_6_addr] <= head_MPORT_6_data; // @[ListBuffer.scala 46:18]
    end
    if (tail_MPORT_3_en & tail_MPORT_3_mask) begin
      tail[tail_MPORT_3_addr] <= tail_MPORT_3_data; // @[ListBuffer.scala 47:18]
    end
    if (next_MPORT_1_en & next_MPORT_1_mask) begin
      next[next_MPORT_1_addr] <= next_MPORT_1_data; // @[ListBuffer.scala 49:18]
    end
    if (data_data_MPORT_en & data_data_MPORT_mask) begin
      data_data[data_data_MPORT_addr] <= data_data_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_corrupt_MPORT_en & data_corrupt_MPORT_mask) begin
      data_corrupt[data_corrupt_MPORT_addr] <= data_corrupt_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (reset) begin // @[ListBuffer.scala 45:22]
      valid <= 2'h0; // @[ListBuffer.scala 45:22]
    end else begin
      valid <= _valid_T_2;
    end
    if (reset) begin // @[ListBuffer.scala 48:22]
      used <= 4'h0; // @[ListBuffer.scala 48:22]
    end else begin
      used <= _used_T_2;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_pop_valid | _T_3[0])) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ListBuffer.scala:84 assert (!io.pop.fire() || (io.valid)(io.pop.bits))\n"); // @[ListBuffer.scala 84:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_pop_valid | _T_3[0]) & ~reset) begin
          $fatal; // @[ListBuffer.scala 84:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    head[initvar] = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    tail[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    next[initvar] = _RAND_2[1:0];
  _RAND_3 = {2{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    data_data[initvar] = _RAND_3[63:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    data_corrupt[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_5 = {1{`RANDOM}};
  valid = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  used = _RAND_6[3:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SinkC(
  input         clock,
  input         reset,
  input         io_req_ready,
  output        io_req_valid,
  output [2:0]  io_req_bits_opcode,
  output [2:0]  io_req_bits_param,
  output [2:0]  io_req_bits_size,
  output [2:0]  io_req_bits_source,
  output [25:0] io_req_bits_tag,
  output [3:0]  io_req_bits_offset,
  output [5:0]  io_req_bits_put,
  output [1:0]  io_req_bits_set,
  output        io_resp_valid,
  output        io_resp_bits_last,
  output [1:0]  io_resp_bits_set,
  output [25:0] io_resp_bits_tag,
  output [2:0]  io_resp_bits_source,
  output [2:0]  io_resp_bits_param,
  output        io_resp_bits_data,
  output        io_c_ready,
  input         io_c_valid,
  input  [2:0]  io_c_bits_opcode,
  input  [2:0]  io_c_bits_param,
  input  [2:0]  io_c_bits_size,
  input  [31:0] io_c_bits_address,
  input  [63:0] io_c_bits_data,
  input         io_c_bits_corrupt,
  output [1:0]  io_set,
  input         io_way,
  input         io_bs_adr_ready,
  output        io_bs_adr_valid,
  output        io_bs_adr_bits_noop,
  output        io_bs_adr_bits_way,
  output [1:0]  io_bs_adr_bits_set,
  output        io_bs_adr_bits_beat,
  output        io_bs_adr_bits_mask,
  output [63:0] io_bs_dat_data,
  output        io_rel_pop_ready,
  input         io_rel_pop_valid,
  input  [5:0]  io_rel_pop_bits_index,
  input         io_rel_pop_bits_last,
  output [63:0] io_rel_beat_data,
  output        io_rel_beat_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  wire  c_clock; // @[Decoupled.scala 377:21]
  wire  c_reset; // @[Decoupled.scala 377:21]
  wire  c_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  c_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] c_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] c_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] c_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [31:0] c_io_enq_bits_address; // @[Decoupled.scala 377:21]
  wire [63:0] c_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  c_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  c_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  c_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] c_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] c_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] c_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [2:0] c_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] c_io_deq_bits_address; // @[Decoupled.scala 377:21]
  wire [63:0] c_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  c_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_clock; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_reset; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_enq_bits_noop; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_enq_bits_way; // @[Decoupled.scala 377:21]
  wire [1:0] io_bs_adr_q_io_enq_bits_set; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_enq_bits_beat; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_deq_bits_noop; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_deq_bits_way; // @[Decoupled.scala 377:21]
  wire [1:0] io_bs_adr_q_io_deq_bits_set; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_deq_bits_beat; // @[Decoupled.scala 377:21]
  wire  io_bs_adr_q_io_deq_bits_mask; // @[Decoupled.scala 377:21]
  wire  putbuffer_clock; // @[SinkC.scala 109:27]
  wire  putbuffer_reset; // @[SinkC.scala 109:27]
  wire  putbuffer_io_push_ready; // @[SinkC.scala 109:27]
  wire  putbuffer_io_push_valid; // @[SinkC.scala 109:27]
  wire  putbuffer_io_push_bits_index; // @[SinkC.scala 109:27]
  wire [63:0] putbuffer_io_push_bits_data_data; // @[SinkC.scala 109:27]
  wire  putbuffer_io_push_bits_data_corrupt; // @[SinkC.scala 109:27]
  wire [1:0] putbuffer_io_valid; // @[SinkC.scala 109:27]
  wire  putbuffer_io_pop_valid; // @[SinkC.scala 109:27]
  wire  putbuffer_io_pop_bits; // @[SinkC.scala 109:27]
  wire [63:0] putbuffer_io_data_data; // @[SinkC.scala 109:27]
  wire  putbuffer_io_data_corrupt; // @[SinkC.scala 109:27]
  wire [7:0] offset_lo_lo = {c_io_deq_bits_address[7],c_io_deq_bits_address[6],c_io_deq_bits_address[5],
    c_io_deq_bits_address[4],c_io_deq_bits_address[3],c_io_deq_bits_address[2],c_io_deq_bits_address[1],
    c_io_deq_bits_address[0]}; // @[Cat.scala 33:92]
  wire [15:0] offset_lo = {c_io_deq_bits_address[15],c_io_deq_bits_address[14],c_io_deq_bits_address[13],
    c_io_deq_bits_address[12],c_io_deq_bits_address[11],c_io_deq_bits_address[10],c_io_deq_bits_address[9],
    c_io_deq_bits_address[8],offset_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] offset_hi_lo = {c_io_deq_bits_address[23],c_io_deq_bits_address[22],c_io_deq_bits_address[21],
    c_io_deq_bits_address[20],c_io_deq_bits_address[19],c_io_deq_bits_address[18],c_io_deq_bits_address[17],
    c_io_deq_bits_address[16]}; // @[Cat.scala 33:92]
  wire [31:0] offset = {c_io_deq_bits_address[31],c_io_deq_bits_address[30],c_io_deq_bits_address[29],
    c_io_deq_bits_address[28],c_io_deq_bits_address[27],c_io_deq_bits_address[26],c_io_deq_bits_address[25],
    c_io_deq_bits_address[24],offset_hi_lo,offset_lo}; // @[Cat.scala 33:92]
  wire [27:0] set = offset[31:4]; // @[Parameters.scala 212:22]
  wire [1:0] set_1 = set[1:0]; // @[Parameters.scala 214:28]
  wire  _T = c_io_deq_ready & c_io_deq_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _beats1_decode_T_1 = 11'hf << c_io_deq_bits_size; // @[package.scala 234:77]
  wire [3:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  beats1_decode = _beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  beats1_opdata = c_io_deq_bits_opcode[0]; // @[Edges.scala 101:36]
  wire  beats1 = beats1_opdata & beats1_decode; // @[Edges.scala 220:14]
  reg  counter; // @[Edges.scala 228:27]
  wire  counter1 = counter - 1'h1; // @[Edges.scala 229:28]
  wire  first = ~counter; // @[Edges.scala 230:25]
  wire  last = counter | ~beats1; // @[Edges.scala 231:37]
  wire  beat = beats1 & ~counter1; // @[Edges.scala 233:25]
  wire  raw_resp = c_io_deq_bits_opcode == 3'h4 | c_io_deq_bits_opcode == 3'h5; // @[SinkC.scala 72:58]
  reg  resp_r; // @[Reg.scala 19:16]
  wire  _GEN_1 = c_io_deq_valid ? raw_resp : resp_r; // @[Reg.scala 19:16 20:{18,22}]
  reg [1:0] io_set_r; // @[Reg.scala 19:16]
  wire  bs_adr_ready = io_bs_adr_q_io_enq_ready; // @[Decoupled.scala 381:17 SinkC.scala 90:22]
  wire  bs_adr_valid = _GEN_1 & (~first | c_io_deq_valid & beats1_opdata); // @[SinkC.scala 93:30]
  wire  _io_bs_dat_data_T = bs_adr_ready & bs_adr_valid; // @[Decoupled.scala 52:35]
  reg [63:0] io_bs_dat_data_r; // @[Reg.scala 19:16]
  wire  _bs_adr_bits_beat_T_1 = beat + bs_adr_ready; // @[SinkC.scala 97:59]
  reg  bs_adr_bits_beat_r; // @[Reg.scala 19:16]
  wire  _io_resp_valid_T_4 = ~beats1_opdata | bs_adr_ready; // @[SinkC.scala 101:70]
  reg [1:0] lists; // @[SinkC.scala 110:24]
  wire  _T_18 = ~_GEN_1 & c_io_deq_valid; // @[SinkC.scala 132:17]
  wire  _T_19 = ~_GEN_1 & c_io_deq_valid & first; // @[SinkC.scala 132:28]
  wire  req_block = first & ~io_req_ready; // @[SinkC.scala 120:27]
  wire  _T_21 = ~req_block; // @[SinkC.scala 132:51]
  wire  buf_block = beats1_opdata & ~putbuffer_io_push_ready; // @[SinkC.scala 121:29]
  wire  _T_23 = ~buf_block; // @[SinkC.scala 132:65]
  wire [1:0] _freeOH_T = ~lists; // @[SinkC.scala 117:27]
  wire [2:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_1[1:0]; // @[package.scala 244:43]
  wire [2:0] _freeOH_T_5 = {_freeOH_T_3, 1'h0}; // @[SinkC.scala 117:35]
  wire [2:0] _freeOH_T_6 = ~_freeOH_T_5; // @[SinkC.scala 117:18]
  wire [2:0] _GEN_8 = {{1'd0}, _freeOH_T}; // @[SinkC.scala 117:41]
  wire [2:0] freeOH = _freeOH_T_6 & _GEN_8; // @[SinkC.scala 117:41]
  wire [2:0] _GEN_5 = ~_GEN_1 & c_io_deq_valid & first & beats1_opdata & ~req_block & ~buf_block ? freeOH : 3'h0; // @[SinkC.scala 132:{77,89}]
  wire [1:0] lists_set = _GEN_5[1:0];
  wire [1:0] _lists_T = lists | lists_set; // @[SinkC.scala 114:21]
  wire  _T_25 = io_rel_pop_ready & io_rel_pop_valid; // @[Decoupled.scala 52:35]
  wire  lists_clr_shiftAmount = io_rel_pop_bits_index[0]; // @[OneHot.scala 63:49]
  wire [1:0] _lists_clr_T = 2'h1 << lists_clr_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] lists_clr = _T_25 & io_rel_pop_bits_last ? _lists_clr_T : 2'h0; // @[SinkC.scala 157:54 158:17]
  wire [1:0] _lists_T_1 = ~lists_clr; // @[SinkC.scala 114:36]
  wire [1:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkC.scala 114:34]
  wire  free = ~(&lists); // @[SinkC.scala 116:16]
  wire  freeIdx_hi = freeOH[2]; // @[OneHot.scala 30:18]
  wire [1:0] freeIdx_lo = freeOH[1:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T = |freeIdx_hi; // @[OneHot.scala 32:14]
  wire [1:0] _GEN_9 = {{1'd0}, freeIdx_hi}; // @[OneHot.scala 32:28]
  wire [1:0] _freeIdx_T_1 = _GEN_9 | freeIdx_lo; // @[OneHot.scala 32:28]
  wire [1:0] freeIdx = {_freeIdx_T,_freeIdx_T_1[1]}; // @[Cat.scala 33:92]
  wire  set_block = beats1_opdata & first & ~free; // @[SinkC.scala 122:38]
  wire  _c_io_deq_ready_T_5 = ~set_block; // @[SinkC.scala 128:84]
  reg [1:0] put_r; // @[Reg.scala 19:16]
  wire [1:0] _GEN_6 = first ? freeIdx : put_r; // @[Reg.scala 19:16 20:{18,22}]
  wire [1:0] _io_rel_pop_ready_T = putbuffer_io_valid >> io_rel_pop_bits_index; // @[SinkC.scala 154:43]
  Queue_26 c ( // @[Decoupled.scala 377:21]
    .clock(c_clock),
    .reset(c_reset),
    .io_enq_ready(c_io_enq_ready),
    .io_enq_valid(c_io_enq_valid),
    .io_enq_bits_opcode(c_io_enq_bits_opcode),
    .io_enq_bits_param(c_io_enq_bits_param),
    .io_enq_bits_size(c_io_enq_bits_size),
    .io_enq_bits_address(c_io_enq_bits_address),
    .io_enq_bits_data(c_io_enq_bits_data),
    .io_enq_bits_corrupt(c_io_enq_bits_corrupt),
    .io_deq_ready(c_io_deq_ready),
    .io_deq_valid(c_io_deq_valid),
    .io_deq_bits_opcode(c_io_deq_bits_opcode),
    .io_deq_bits_param(c_io_deq_bits_param),
    .io_deq_bits_size(c_io_deq_bits_size),
    .io_deq_bits_source(c_io_deq_bits_source),
    .io_deq_bits_address(c_io_deq_bits_address),
    .io_deq_bits_data(c_io_deq_bits_data),
    .io_deq_bits_corrupt(c_io_deq_bits_corrupt)
  );
  Queue_27 io_bs_adr_q ( // @[Decoupled.scala 377:21]
    .clock(io_bs_adr_q_clock),
    .reset(io_bs_adr_q_reset),
    .io_enq_ready(io_bs_adr_q_io_enq_ready),
    .io_enq_valid(io_bs_adr_q_io_enq_valid),
    .io_enq_bits_noop(io_bs_adr_q_io_enq_bits_noop),
    .io_enq_bits_way(io_bs_adr_q_io_enq_bits_way),
    .io_enq_bits_set(io_bs_adr_q_io_enq_bits_set),
    .io_enq_bits_beat(io_bs_adr_q_io_enq_bits_beat),
    .io_deq_ready(io_bs_adr_q_io_deq_ready),
    .io_deq_valid(io_bs_adr_q_io_deq_valid),
    .io_deq_bits_noop(io_bs_adr_q_io_deq_bits_noop),
    .io_deq_bits_way(io_bs_adr_q_io_deq_bits_way),
    .io_deq_bits_set(io_bs_adr_q_io_deq_bits_set),
    .io_deq_bits_beat(io_bs_adr_q_io_deq_bits_beat),
    .io_deq_bits_mask(io_bs_adr_q_io_deq_bits_mask)
  );
  ListBuffer_1 putbuffer ( // @[SinkC.scala 109:27]
    .clock(putbuffer_clock),
    .reset(putbuffer_reset),
    .io_push_ready(putbuffer_io_push_ready),
    .io_push_valid(putbuffer_io_push_valid),
    .io_push_bits_index(putbuffer_io_push_bits_index),
    .io_push_bits_data_data(putbuffer_io_push_bits_data_data),
    .io_push_bits_data_corrupt(putbuffer_io_push_bits_data_corrupt),
    .io_valid(putbuffer_io_valid),
    .io_pop_valid(putbuffer_io_pop_valid),
    .io_pop_bits(putbuffer_io_pop_bits),
    .io_data_data(putbuffer_io_data_data),
    .io_data_corrupt(putbuffer_io_data_corrupt)
  );
  assign io_req_valid = _T_19 & _T_23 & _c_io_deq_ready_T_5; // @[SinkC.scala 130:61]
  assign io_req_bits_opcode = c_io_deq_bits_opcode; // @[SinkC.scala 138:24]
  assign io_req_bits_param = c_io_deq_bits_param; // @[SinkC.scala 139:24]
  assign io_req_bits_size = c_io_deq_bits_size; // @[SinkC.scala 140:24]
  assign io_req_bits_source = c_io_deq_bits_source; // @[SinkC.scala 141:24]
  assign io_req_bits_tag = set[27:2]; // @[Parameters.scala 213:19]
  assign io_req_bits_offset = offset[3:0]; // @[Parameters.scala 214:50]
  assign io_req_bits_put = {{4'd0}, _GEN_6}; // @[SinkC.scala 145:24]
  assign io_req_bits_set = set[1:0]; // @[Parameters.scala 214:28]
  assign io_resp_valid = _GEN_1 & c_io_deq_valid & (first | last) & (~beats1_opdata | bs_adr_ready); // @[SinkC.scala 101:57]
  assign io_resp_bits_last = counter | ~beats1; // @[Edges.scala 231:37]
  assign io_resp_bits_set = set[1:0]; // @[Parameters.scala 214:28]
  assign io_resp_bits_tag = set[27:2]; // @[Parameters.scala 213:19]
  assign io_resp_bits_source = c_io_deq_bits_source; // @[SinkC.scala 105:25]
  assign io_resp_bits_param = c_io_deq_bits_param; // @[SinkC.scala 106:25]
  assign io_resp_bits_data = c_io_deq_bits_opcode[0]; // @[Edges.scala 101:36]
  assign io_c_ready = c_io_enq_ready; // @[Decoupled.scala 381:17]
  assign io_set = c_io_deq_valid ? set_1 : io_set_r; // @[SinkC.scala 86:18]
  assign io_bs_adr_valid = io_bs_adr_q_io_deq_valid; // @[SinkC.scala 91:15]
  assign io_bs_adr_bits_noop = io_bs_adr_q_io_deq_bits_noop; // @[SinkC.scala 91:15]
  assign io_bs_adr_bits_way = io_bs_adr_q_io_deq_bits_way; // @[SinkC.scala 91:15]
  assign io_bs_adr_bits_set = io_bs_adr_q_io_deq_bits_set; // @[SinkC.scala 91:15]
  assign io_bs_adr_bits_beat = io_bs_adr_q_io_deq_bits_beat; // @[SinkC.scala 91:15]
  assign io_bs_adr_bits_mask = io_bs_adr_q_io_deq_bits_mask; // @[SinkC.scala 91:15]
  assign io_bs_dat_data = io_bs_dat_data_r; // @[SinkC.scala 92:22]
  assign io_rel_pop_ready = _io_rel_pop_ready_T[0]; // @[SinkC.scala 154:43]
  assign io_rel_beat_data = putbuffer_io_data_data; // @[SinkC.scala 155:17]
  assign io_rel_beat_corrupt = putbuffer_io_data_corrupt; // @[SinkC.scala 155:17]
  assign c_clock = clock;
  assign c_reset = reset;
  assign c_io_enq_valid = io_c_valid; // @[Decoupled.scala 379:22]
  assign c_io_enq_bits_opcode = io_c_bits_opcode; // @[Decoupled.scala 380:21]
  assign c_io_enq_bits_param = io_c_bits_param; // @[Decoupled.scala 380:21]
  assign c_io_enq_bits_size = io_c_bits_size; // @[Decoupled.scala 380:21]
  assign c_io_enq_bits_address = io_c_bits_address; // @[Decoupled.scala 380:21]
  assign c_io_enq_bits_data = io_c_bits_data; // @[Decoupled.scala 380:21]
  assign c_io_enq_bits_corrupt = io_c_bits_corrupt; // @[Decoupled.scala 380:21]
  assign c_io_deq_ready = raw_resp ? _io_resp_valid_T_4 : _T_21 & _T_23 & ~set_block; // @[SinkC.scala 128:19]
  assign io_bs_adr_q_clock = clock;
  assign io_bs_adr_q_reset = reset;
  assign io_bs_adr_q_io_enq_valid = _GEN_1 & (~first | c_io_deq_valid & beats1_opdata); // @[SinkC.scala 93:30]
  assign io_bs_adr_q_io_enq_bits_noop = ~c_io_deq_valid; // @[SinkC.scala 94:25]
  assign io_bs_adr_q_io_enq_bits_way = io_way; // @[SinkC.scala 90:22 95:22]
  assign io_bs_adr_q_io_enq_bits_set = io_set; // @[SinkC.scala 90:22 96:22]
  assign io_bs_adr_q_io_enq_bits_beat = c_io_deq_valid ? beat : bs_adr_bits_beat_r; // @[SinkC.scala 97:28]
  assign io_bs_adr_q_io_deq_ready = io_bs_adr_ready; // @[SinkC.scala 91:15]
  assign putbuffer_clock = clock;
  assign putbuffer_reset = reset;
  assign putbuffer_io_push_valid = _T_18 & beats1_opdata & _T_21 & _c_io_deq_ready_T_5; // @[SinkC.scala 131:74]
  assign putbuffer_io_push_bits_index = _GEN_6[0]; // @[SinkC.scala 147:34]
  assign putbuffer_io_push_bits_data_data = c_io_deq_bits_data; // @[SinkC.scala 148:41]
  assign putbuffer_io_push_bits_data_corrupt = c_io_deq_bits_corrupt; // @[SinkC.scala 149:41]
  assign putbuffer_io_pop_valid = io_rel_pop_ready & io_rel_pop_valid; // @[Decoupled.scala 52:35]
  assign putbuffer_io_pop_bits = io_rel_pop_bits_index[0]; // @[SinkC.scala 152:27]
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        counter <= beats1;
      end else begin
        counter <= counter1;
      end
    end
    if (c_io_deq_valid) begin // @[Reg.scala 20:18]
      resp_r <= raw_resp; // @[Reg.scala 20:22]
    end
    if (c_io_deq_valid) begin // @[Reg.scala 20:18]
      io_set_r <= set_1; // @[Reg.scala 20:22]
    end
    if (_io_bs_dat_data_T) begin // @[Reg.scala 20:18]
      io_bs_dat_data_r <= c_io_deq_bits_data; // @[Reg.scala 20:22]
    end
    if (c_io_deq_valid) begin // @[Reg.scala 20:18]
      bs_adr_bits_beat_r <= _bs_adr_bits_beat_T_1; // @[Reg.scala 20:22]
    end
    if (reset) begin // @[SinkC.scala 110:24]
      lists <= 2'h0; // @[SinkC.scala 110:24]
    end else begin
      lists <= _lists_T_2; // @[SinkC.scala 114:11]
    end
    if (first) begin // @[Reg.scala 20:18]
      put_r <= freeIdx; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(c_io_deq_valid & c_io_deq_bits_corrupt))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Data poisoning unavailable\n    at SinkC.scala:84 assert (!(c.valid && c.bits.corrupt), \"Data poisoning unavailable\")\n"
            ); // @[SinkC.scala 84:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(c_io_deq_valid & c_io_deq_bits_corrupt)) & ~reset) begin
          $fatal; // @[SinkC.scala 84:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  resp_r = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  io_set_r = _RAND_2[1:0];
  _RAND_3 = {2{`RANDOM}};
  io_bs_dat_data_r = _RAND_3[63:0];
  _RAND_4 = {1{`RANDOM}};
  bs_adr_bits_beat_r = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  lists = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  put_r = _RAND_6[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_28(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [1:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [4:0]  io_enq_bits_source,
  input  [2:0]  io_enq_bits_sink,
  input         io_enq_bits_denied,
  input  [63:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [4:0]  io_deq_bits_source,
  output [2:0]  io_deq_bits_sink,
  output        io_deq_bits_denied,
  output [63:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_param [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [4:0] ram_source [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [4:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [4:0] ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_sink [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_sink_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_denied [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_en; // @[Decoupled.scala 275:95]
  reg [63:0] ram_data [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
  assign ram_sink_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_sink_MPORT_data = io_enq_bits_sink;
  assign ram_sink_MPORT_addr = enq_ptr_value;
  assign ram_sink_MPORT_mask = 1'h1;
  assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
  assign ram_denied_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_denied_MPORT_data = io_enq_bits_denied;
  assign ram_denied_MPORT_addr = enq_ptr_value;
  assign ram_denied_MPORT_mask = 1'h1;
  assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
      ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
      ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[4:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_sink[initvar] = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_denied[initvar] = _RAND_5[0:0];
  _RAND_6 = {2{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[63:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  enq_ptr_value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  deq_ptr_value = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SinkD(
  input         clock,
  input         reset,
  output        io_resp_valid,
  output        io_resp_bits_last,
  output [2:0]  io_resp_bits_opcode,
  output [2:0]  io_resp_bits_param,
  output [4:0]  io_resp_bits_source,
  output [2:0]  io_resp_bits_sink,
  output        io_resp_bits_denied,
  output        io_d_ready,
  input         io_d_valid,
  input  [2:0]  io_d_bits_opcode,
  input  [1:0]  io_d_bits_param,
  input  [2:0]  io_d_bits_size,
  input  [4:0]  io_d_bits_source,
  input  [2:0]  io_d_bits_sink,
  input         io_d_bits_denied,
  input  [63:0] io_d_bits_data,
  input         io_d_bits_corrupt,
  output [4:0]  io_source,
  input         io_way,
  input  [1:0]  io_set,
  input         io_bs_adr_ready,
  output        io_bs_adr_valid,
  output        io_bs_adr_bits_noop,
  output        io_bs_adr_bits_way,
  output [1:0]  io_bs_adr_bits_set,
  output        io_bs_adr_bits_beat,
  output [63:0] io_bs_dat_data,
  output [1:0]  io_grant_req_set,
  output        io_grant_req_way,
  input         io_grant_safe
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  d_clock; // @[Decoupled.scala 377:21]
  wire  d_reset; // @[Decoupled.scala 377:21]
  wire  d_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  d_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] d_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] d_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] d_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [4:0] d_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [2:0] d_io_enq_bits_sink; // @[Decoupled.scala 377:21]
  wire  d_io_enq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] d_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  d_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  d_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  d_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] d_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] d_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] d_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [4:0] d_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [2:0] d_io_deq_bits_sink; // @[Decoupled.scala 377:21]
  wire  d_io_deq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] d_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  d_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  _T = d_io_deq_ready & d_io_deq_valid; // @[Decoupled.scala 52:35]
  wire [11:0] _beats1_decode_T_1 = 12'h1f << d_io_deq_bits_size; // @[package.scala 234:77]
  wire [4:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[4:0]; // @[package.scala 234:46]
  wire [1:0] beats1_decode = _beats1_decode_T_3[4:3]; // @[Edges.scala 219:59]
  wire  beats1_opdata = d_io_deq_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [1:0] beats1 = beats1_opdata ? beats1_decode : 2'h0; // @[Edges.scala 220:14]
  reg [1:0] counter; // @[Edges.scala 228:27]
  wire [1:0] counter1 = counter - 2'h1; // @[Edges.scala 229:28]
  wire  first = counter == 2'h0; // @[Edges.scala 230:25]
  wire  last = counter == 2'h1 | beats1 == 2'h0; // @[Edges.scala 231:37]
  wire [1:0] _count_T = ~counter1; // @[Edges.scala 233:27]
  wire [1:0] beat = beats1 & _count_T; // @[Edges.scala 233:25]
  reg [4:0] io_source_r; // @[Reg.scala 19:16]
  wire  _d_io_deq_ready_T = ~first; // @[SinkD.scala 62:34]
  wire [1:0] _GEN_3 = {{1'd0}, io_bs_adr_ready}; // @[SinkD.scala 77:60]
  wire [1:0] _io_bs_adr_bits_beat_T_1 = beat + _GEN_3; // @[SinkD.scala 77:60]
  reg [1:0] io_bs_adr_bits_beat_r; // @[Reg.scala 19:16]
  wire [1:0] _io_bs_adr_bits_beat_T_2 = d_io_deq_valid ? beat : io_bs_adr_bits_beat_r; // @[SinkD.scala 77:29]
  Queue_28 d ( // @[Decoupled.scala 377:21]
    .clock(d_clock),
    .reset(d_reset),
    .io_enq_ready(d_io_enq_ready),
    .io_enq_valid(d_io_enq_valid),
    .io_enq_bits_opcode(d_io_enq_bits_opcode),
    .io_enq_bits_param(d_io_enq_bits_param),
    .io_enq_bits_size(d_io_enq_bits_size),
    .io_enq_bits_source(d_io_enq_bits_source),
    .io_enq_bits_sink(d_io_enq_bits_sink),
    .io_enq_bits_denied(d_io_enq_bits_denied),
    .io_enq_bits_data(d_io_enq_bits_data),
    .io_enq_bits_corrupt(d_io_enq_bits_corrupt),
    .io_deq_ready(d_io_deq_ready),
    .io_deq_valid(d_io_deq_valid),
    .io_deq_bits_opcode(d_io_deq_bits_opcode),
    .io_deq_bits_param(d_io_deq_bits_param),
    .io_deq_bits_size(d_io_deq_bits_size),
    .io_deq_bits_source(d_io_deq_bits_source),
    .io_deq_bits_sink(d_io_deq_bits_sink),
    .io_deq_bits_denied(d_io_deq_bits_denied),
    .io_deq_bits_data(d_io_deq_bits_data),
    .io_deq_bits_corrupt(d_io_deq_bits_corrupt)
  );
  assign io_resp_valid = (first | last) & _T; // @[SinkD.scala 61:36]
  assign io_resp_bits_last = counter == 2'h1 | beats1 == 2'h0; // @[Edges.scala 231:37]
  assign io_resp_bits_opcode = d_io_deq_bits_opcode; // @[SinkD.scala 68:23]
  assign io_resp_bits_param = {{1'd0}, d_io_deq_bits_param}; // @[SinkD.scala 69:23]
  assign io_resp_bits_source = d_io_deq_bits_source; // @[SinkD.scala 70:23]
  assign io_resp_bits_sink = d_io_deq_bits_sink; // @[SinkD.scala 71:23]
  assign io_resp_bits_denied = d_io_deq_bits_denied; // @[SinkD.scala 72:23]
  assign io_d_ready = d_io_enq_ready; // @[Decoupled.scala 381:17]
  assign io_source = d_io_deq_valid ? d_io_deq_bits_source : io_source_r; // @[SinkD.scala 56:19]
  assign io_bs_adr_valid = _d_io_deq_ready_T | d_io_deq_valid & io_grant_safe; // @[SinkD.scala 63:29]
  assign io_bs_adr_bits_noop = ~d_io_deq_valid | ~beats1_opdata; // @[SinkD.scala 74:35]
  assign io_bs_adr_bits_way = io_way; // @[SinkD.scala 75:23]
  assign io_bs_adr_bits_set = io_set; // @[SinkD.scala 76:23]
  assign io_bs_adr_bits_beat = _io_bs_adr_bits_beat_T_2[0]; // @[SinkD.scala 77:23]
  assign io_bs_dat_data = d_io_deq_bits_data; // @[SinkD.scala 79:23]
  assign io_grant_req_set = io_set; // @[SinkD.scala 58:20]
  assign io_grant_req_way = io_way; // @[SinkD.scala 57:20]
  assign d_clock = clock;
  assign d_reset = reset;
  assign d_io_enq_valid = io_d_valid; // @[Decoupled.scala 379:22]
  assign d_io_enq_bits_opcode = io_d_bits_opcode; // @[Decoupled.scala 380:21]
  assign d_io_enq_bits_param = io_d_bits_param; // @[Decoupled.scala 380:21]
  assign d_io_enq_bits_size = io_d_bits_size; // @[Decoupled.scala 380:21]
  assign d_io_enq_bits_source = io_d_bits_source; // @[Decoupled.scala 380:21]
  assign d_io_enq_bits_sink = io_d_bits_sink; // @[Decoupled.scala 380:21]
  assign d_io_enq_bits_denied = io_d_bits_denied; // @[Decoupled.scala 380:21]
  assign d_io_enq_bits_data = io_d_bits_data; // @[Decoupled.scala 380:21]
  assign d_io_enq_bits_corrupt = io_d_bits_corrupt; // @[Decoupled.scala 380:21]
  assign d_io_deq_ready = io_bs_adr_ready & (~first | io_grant_safe); // @[SinkD.scala 62:30]
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 2'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 2'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    if (d_io_deq_valid) begin // @[Reg.scala 20:18]
      io_source_r <= d_io_deq_bits_source; // @[Reg.scala 20:22]
    end
    if (d_io_deq_valid) begin // @[Reg.scala 20:18]
      io_bs_adr_bits_beat_r <= _io_bs_adr_bits_beat_T_1; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(d_io_deq_valid & d_io_deq_bits_corrupt & ~d_io_deq_bits_denied))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Data poisoning unsupported\n    at SinkD.scala:81 assert (!(d.valid && d.bits.corrupt && !d.bits.denied), \"Data poisoning unsupported\")\n"
            ); // @[SinkD.scala 81:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(d_io_deq_valid & d_io_deq_bits_corrupt & ~d_io_deq_bits_denied)) & ~reset) begin
          $fatal; // @[SinkD.scala 81:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  counter = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  io_source_r = _RAND_1[4:0];
  _RAND_2 = {1{`RANDOM}};
  io_bs_adr_bits_beat_r = _RAND_2[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SinkE(
  output       io_resp_valid,
  output [4:0] io_resp_bits_sink,
  input        io_e_valid,
  input  [4:0] io_e_bits_sink
);
  assign io_resp_valid = io_e_valid; // @[SinkE.scala 44:19]
  assign io_resp_bits_sink = io_e_bits_sink; // @[SinkE.scala 45:23]
endmodule
module Queue_30(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [1:0]  io_enq_bits_set,
  input         io_enq_bits_way,
  input         io_enq_bits_data_dirty,
  input  [1:0]  io_enq_bits_data_state,
  input         io_enq_bits_data_clients,
  input  [25:0] io_enq_bits_data_tag,
  input         io_deq_ready,
  output        io_deq_valid,
  output [1:0]  io_deq_bits_set,
  output        io_deq_bits_way,
  output        io_deq_bits_data_dirty,
  output [1:0]  io_deq_bits_data_state,
  output        io_deq_bits_data_clients,
  output [25:0] io_deq_bits_data_tag
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] ram_set [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_set_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_set_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_set_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_set_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_set_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_set_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_set_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_way [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_way_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_way_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_way_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_way_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_way_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_way_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_way_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_data_dirty [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_data_dirty_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_dirty_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_dirty_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_dirty_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_dirty_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_dirty_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_dirty_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_data_state [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_data_state_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_state_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_data_state_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_data_state_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_state_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_state_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_state_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_data_clients [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_data_clients_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_clients_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_clients_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_clients_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_clients_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_clients_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_clients_MPORT_en; // @[Decoupled.scala 275:95]
  reg [25:0] ram_data_tag [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_data_tag_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_tag_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [25:0] ram_data_tag_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [25:0] ram_data_tag_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_tag_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_tag_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_tag_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_set_io_deq_bits_MPORT_en = 1'h1;
  assign ram_set_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_set_io_deq_bits_MPORT_data = ram_set[ram_set_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_set_MPORT_data = io_enq_bits_set;
  assign ram_set_MPORT_addr = 1'h0;
  assign ram_set_MPORT_mask = 1'h1;
  assign ram_set_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_way_io_deq_bits_MPORT_en = 1'h1;
  assign ram_way_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_way_io_deq_bits_MPORT_data = ram_way[ram_way_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_way_MPORT_data = io_enq_bits_way;
  assign ram_way_MPORT_addr = 1'h0;
  assign ram_way_MPORT_mask = 1'h1;
  assign ram_way_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_dirty_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_dirty_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_data_dirty_io_deq_bits_MPORT_data = ram_data_dirty[ram_data_dirty_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_dirty_MPORT_data = io_enq_bits_data_dirty;
  assign ram_data_dirty_MPORT_addr = 1'h0;
  assign ram_data_dirty_MPORT_mask = 1'h1;
  assign ram_data_dirty_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_state_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_state_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_data_state_io_deq_bits_MPORT_data = ram_data_state[ram_data_state_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_state_MPORT_data = io_enq_bits_data_state;
  assign ram_data_state_MPORT_addr = 1'h0;
  assign ram_data_state_MPORT_mask = 1'h1;
  assign ram_data_state_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_clients_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_clients_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_data_clients_io_deq_bits_MPORT_data = ram_data_clients[ram_data_clients_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_clients_MPORT_data = io_enq_bits_data_clients;
  assign ram_data_clients_MPORT_addr = 1'h0;
  assign ram_data_clients_MPORT_mask = 1'h1;
  assign ram_data_clients_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_tag_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_tag_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_data_tag_io_deq_bits_MPORT_data = ram_data_tag[ram_data_tag_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_tag_MPORT_data = io_enq_bits_data_tag;
  assign ram_data_tag_MPORT_addr = 1'h0;
  assign ram_data_tag_MPORT_mask = 1'h1;
  assign ram_data_tag_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_set = ram_set_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_way = ram_way_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data_dirty = ram_data_dirty_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data_state = ram_data_state_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data_clients = ram_data_clients_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data_tag = ram_data_tag_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_set_MPORT_en & ram_set_MPORT_mask) begin
      ram_set[ram_set_MPORT_addr] <= ram_set_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_way_MPORT_en & ram_way_MPORT_mask) begin
      ram_way[ram_way_MPORT_addr] <= ram_way_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_dirty_MPORT_en & ram_data_dirty_MPORT_mask) begin
      ram_data_dirty[ram_data_dirty_MPORT_addr] <= ram_data_dirty_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_state_MPORT_en & ram_data_state_MPORT_mask) begin
      ram_data_state[ram_data_state_MPORT_addr] <= ram_data_state_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_clients_MPORT_en & ram_data_clients_MPORT_mask) begin
      ram_data_clients[ram_data_clients_MPORT_addr] <= ram_data_clients_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_tag_MPORT_en & ram_data_tag_MPORT_mask) begin
      ram_data_tag[ram_data_tag_MPORT_addr] <= ram_data_tag_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_set[initvar] = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_way[initvar] = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_data_dirty[initvar] = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_data_state[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_data_clients[initvar] = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_data_tag[initvar] = _RAND_5[25:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_6 = {1{`RANDOM}};
  maybe_full = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MaxPeriodFibonacciLFSR_8(
  input   clock,
  input   reset,
  input   io_increment,
  output  io_out_0,
  output  io_out_1,
  output  io_out_2,
  output  io_out_3,
  output  io_out_4,
  output  io_out_5,
  output  io_out_6,
  output  io_out_7,
  output  io_out_8,
  output  io_out_9,
  output  io_out_10,
  output  io_out_11,
  output  io_out_12,
  output  io_out_13,
  output  io_out_14,
  output  io_out_15
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
`endif // RANDOMIZE_REG_INIT
  reg  state_0; // @[PRNG.scala 55:49]
  reg  state_1; // @[PRNG.scala 55:49]
  reg  state_2; // @[PRNG.scala 55:49]
  reg  state_3; // @[PRNG.scala 55:49]
  reg  state_4; // @[PRNG.scala 55:49]
  reg  state_5; // @[PRNG.scala 55:49]
  reg  state_6; // @[PRNG.scala 55:49]
  reg  state_7; // @[PRNG.scala 55:49]
  reg  state_8; // @[PRNG.scala 55:49]
  reg  state_9; // @[PRNG.scala 55:49]
  reg  state_10; // @[PRNG.scala 55:49]
  reg  state_11; // @[PRNG.scala 55:49]
  reg  state_12; // @[PRNG.scala 55:49]
  reg  state_13; // @[PRNG.scala 55:49]
  reg  state_14; // @[PRNG.scala 55:49]
  reg  state_15; // @[PRNG.scala 55:49]
  wire  _T_2 = state_15 ^ state_13 ^ state_12 ^ state_10; // @[LFSR.scala 15:41]
  wire  _GEN_15 = io_increment ? state_14 : state_15; // @[PRNG.scala 69:22 70:11 55:49]
  assign io_out_0 = state_0; // @[PRNG.scala 78:10]
  assign io_out_1 = state_1; // @[PRNG.scala 78:10]
  assign io_out_2 = state_2; // @[PRNG.scala 78:10]
  assign io_out_3 = state_3; // @[PRNG.scala 78:10]
  assign io_out_4 = state_4; // @[PRNG.scala 78:10]
  assign io_out_5 = state_5; // @[PRNG.scala 78:10]
  assign io_out_6 = state_6; // @[PRNG.scala 78:10]
  assign io_out_7 = state_7; // @[PRNG.scala 78:10]
  assign io_out_8 = state_8; // @[PRNG.scala 78:10]
  assign io_out_9 = state_9; // @[PRNG.scala 78:10]
  assign io_out_10 = state_10; // @[PRNG.scala 78:10]
  assign io_out_11 = state_11; // @[PRNG.scala 78:10]
  assign io_out_12 = state_12; // @[PRNG.scala 78:10]
  assign io_out_13 = state_13; // @[PRNG.scala 78:10]
  assign io_out_14 = state_14; // @[PRNG.scala 78:10]
  assign io_out_15 = state_15; // @[PRNG.scala 78:10]
  always @(posedge clock) begin
    if (reset) begin // @[PRNG.scala 55:49]
      state_0 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_0 <= _T_2; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_1 <= state_0; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_2 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_2 <= state_1; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_3 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_3 <= state_2; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_4 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_4 <= state_3; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_5 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_5 <= state_4; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_6 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_6 <= state_5; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_7 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_7 <= state_6; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_8 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_8 <= state_7; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_9 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_9 <= state_8; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_10 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_10 <= state_9; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_11 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_11 <= state_10; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_12 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_12 <= state_11; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_13 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_13 <= state_12; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_14 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_14 <= state_13; // @[PRNG.scala 70:11]
    end
    state_15 <= reset | _GEN_15; // @[PRNG.scala 55:{49,49}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  state_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  state_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  state_4 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  state_5 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  state_6 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  state_7 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  state_8 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  state_9 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  state_10 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  state_11 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  state_12 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  state_13 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  state_14 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  state_15 = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Directory(
  input         clock,
  input         reset,
  output        io_write_ready,
  input         io_write_valid,
  input  [1:0]  io_write_bits_set,
  input         io_write_bits_way,
  input         io_write_bits_data_dirty,
  input  [1:0]  io_write_bits_data_state,
  input         io_write_bits_data_clients,
  input  [25:0] io_write_bits_data_tag,
  input         io_read_valid,
  input  [1:0]  io_read_bits_set,
  input  [25:0] io_read_bits_tag,
  output        io_result_bits_dirty,
  output [1:0]  io_result_bits_state,
  output        io_result_bits_clients,
  output [25:0] io_result_bits_tag,
  output        io_result_bits_hit,
  output        io_result_bits_way,
  output        io_ready
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [29:0] cc_dir_0 [0:3]; // @[DescribedSRAM.scala 19:26]
  wire  cc_dir_0_regout_en; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_dir_0_regout_addr; // @[DescribedSRAM.scala 19:26]
  wire [29:0] cc_dir_0_regout_data; // @[DescribedSRAM.scala 19:26]
  wire [29:0] cc_dir_0_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_dir_0_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire  cc_dir_0_MPORT_mask; // @[DescribedSRAM.scala 19:26]
  wire  cc_dir_0_MPORT_en; // @[DescribedSRAM.scala 19:26]
  reg  cc_dir_0_regout_en_pipe_0;
  reg [1:0] cc_dir_0_regout_addr_pipe_0;
  reg [29:0] cc_dir_1 [0:3]; // @[DescribedSRAM.scala 19:26]
  wire  cc_dir_1_regout_en; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_dir_1_regout_addr; // @[DescribedSRAM.scala 19:26]
  wire [29:0] cc_dir_1_regout_data; // @[DescribedSRAM.scala 19:26]
  wire [29:0] cc_dir_1_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_dir_1_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire  cc_dir_1_MPORT_mask; // @[DescribedSRAM.scala 19:26]
  wire  cc_dir_1_MPORT_en; // @[DescribedSRAM.scala 19:26]
  reg  cc_dir_1_regout_en_pipe_0;
  reg [1:0] cc_dir_1_regout_addr_pipe_0;
  wire  write_clock; // @[Decoupled.scala 377:21]
  wire  write_reset; // @[Decoupled.scala 377:21]
  wire  write_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  write_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [1:0] write_io_enq_bits_set; // @[Decoupled.scala 377:21]
  wire  write_io_enq_bits_way; // @[Decoupled.scala 377:21]
  wire  write_io_enq_bits_data_dirty; // @[Decoupled.scala 377:21]
  wire [1:0] write_io_enq_bits_data_state; // @[Decoupled.scala 377:21]
  wire  write_io_enq_bits_data_clients; // @[Decoupled.scala 377:21]
  wire [25:0] write_io_enq_bits_data_tag; // @[Decoupled.scala 377:21]
  wire  write_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  write_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [1:0] write_io_deq_bits_set; // @[Decoupled.scala 377:21]
  wire  write_io_deq_bits_way; // @[Decoupled.scala 377:21]
  wire  write_io_deq_bits_data_dirty; // @[Decoupled.scala 377:21]
  wire [1:0] write_io_deq_bits_data_state; // @[Decoupled.scala 377:21]
  wire  write_io_deq_bits_data_clients; // @[Decoupled.scala 377:21]
  wire [25:0] write_io_deq_bits_data_tag; // @[Decoupled.scala 377:21]
  wire  victimLFSR_prng_clock; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_reset; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_increment; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_0; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_1; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_2; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_3; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_4; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_5; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_6; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_7; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_8; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_9; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_10; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_11; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_12; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_13; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_14; // @[PRNG.scala 91:22]
  wire  victimLFSR_prng_io_out_15; // @[PRNG.scala 91:22]
  reg [2:0] wipeCount; // @[Directory.scala 77:26]
  reg  wipeOff; // @[Directory.scala 78:24]
  wire  wipeDone = wipeCount[2]; // @[Directory.scala 79:27]
  wire [1:0] wipeSet = wipeCount[1:0]; // @[Directory.scala 80:26]
  wire  _T = ~wipeDone; // @[Directory.scala 83:9]
  wire  _T_2 = ~wipeDone & ~wipeOff; // @[Directory.scala 83:19]
  wire [2:0] _wipeCount_T_1 = wipeCount + 3'h1; // @[Directory.scala 83:57]
  wire  _T_3 = ~io_read_valid; // @[Directory.scala 84:23]
  wire  _T_6 = ~reset; // @[Directory.scala 84:10]
  wire  wen = _T_2 | write_io_deq_valid; // @[Directory.scala 88:37]
  wire [29:0] _T_16 = {write_io_deq_bits_data_dirty,write_io_deq_bits_data_state,write_io_deq_bits_data_clients,
    write_io_deq_bits_data_tag}; // @[Directory.scala 97:67]
  wire  shiftAmount = write_io_deq_bits_way; // @[OneHot.scala 63:49]
  wire [1:0] _T_20 = 2'h1 << shiftAmount; // @[OneHot.scala 64:12]
  reg  ren1; // @[Directory.scala 101:21]
  reg [25:0] tag; // @[Reg.scala 19:16]
  reg [1:0] set; // @[Reg.scala 19:16]
  wire [7:0] victimLFSR_lo = {victimLFSR_prng_io_out_7,victimLFSR_prng_io_out_6,victimLFSR_prng_io_out_5,
    victimLFSR_prng_io_out_4,victimLFSR_prng_io_out_3,victimLFSR_prng_io_out_2,victimLFSR_prng_io_out_1,
    victimLFSR_prng_io_out_0}; // @[PRNG.scala 95:17]
  wire [15:0] _victimLFSR_T = {victimLFSR_prng_io_out_15,victimLFSR_prng_io_out_14,victimLFSR_prng_io_out_13,
    victimLFSR_prng_io_out_12,victimLFSR_prng_io_out_11,victimLFSR_prng_io_out_10,victimLFSR_prng_io_out_9,
    victimLFSR_prng_io_out_8,victimLFSR_lo}; // @[PRNG.scala 95:17]
  wire [7:0] victimLFSR_lo_1 = {_victimLFSR_T[8],_victimLFSR_T[9],_victimLFSR_T[10],_victimLFSR_T[11],_victimLFSR_T[12],
    _victimLFSR_T[13],_victimLFSR_T[14],_victimLFSR_T[15]}; // @[compatibility.scala 627:9]
  wire [15:0] _victimLFSR_T_17 = {_victimLFSR_T[0],_victimLFSR_T[1],_victimLFSR_T[2],_victimLFSR_T[3],_victimLFSR_T[4],
    _victimLFSR_T[5],_victimLFSR_T[6],_victimLFSR_T[7],victimLFSR_lo_1}; // @[compatibility.scala 627:9]
  wire [9:0] victimLFSR = _victimLFSR_T_17[9:0]; // @[Directory.scala 113:46]
  wire  _victimLTE_T_1 = 10'h200 <= victimLFSR; // @[Directory.scala 115:43]
  wire [1:0] victimLTE = {_victimLTE_T_1,1'h1}; // @[Cat.scala 33:92]
  wire [2:0] victimSimp = {1'h0,victimLTE[1],1'h1}; // @[Cat.scala 33:92]
  wire [1:0] _victimWayOH_T_2 = ~victimSimp[2:1]; // @[Directory.scala 117:57]
  wire [1:0] victimWayOH = victimSimp[1:0] & _victimWayOH_T_2; // @[Directory.scala 117:55]
  wire  victimWay = victimWayOH[1]; // @[CircuitMath.scala 28:8]
  wire  _T_28 = ~ren1; // @[Directory.scala 119:11]
  wire [2:0] _T_37 = ~victimSimp; // @[Directory.scala 120:41]
  wire [2:0] _GEN_18 = {{1'd0}, victimSimp[2:1]}; // @[Directory.scala 120:39]
  wire [2:0] _T_38 = _GEN_18 & _T_37; // @[Directory.scala 120:39]
  wire [1:0] _T_47 = victimWayOH[0] + victimWay; // @[Bitwise.scala 51:90]
  wire  setQuash = write_io_deq_valid & write_io_deq_bits_set == set; // @[Directory.scala 123:31]
  wire  tagMatch = write_io_deq_bits_data_tag == tag; // @[Directory.scala 124:34]
  wire  wayMatch = write_io_deq_bits_way == victimWay; // @[Directory.scala 125:29]
  wire [29:0] _ways_WIRE_1 = cc_dir_0_regout_data;
  wire [25:0] ways_0_tag = _ways_WIRE_1[25:0]; // @[Directory.scala 127:69]
  wire  ways_0_clients = _ways_WIRE_1[26]; // @[Directory.scala 127:69]
  wire [1:0] ways_0_state = _ways_WIRE_1[28:27]; // @[Directory.scala 127:69]
  wire  ways_0_dirty = _ways_WIRE_1[29]; // @[Directory.scala 127:69]
  wire [29:0] _ways_WIRE_3 = cc_dir_1_regout_data;
  wire [25:0] ways_1_tag = _ways_WIRE_3[25:0]; // @[Directory.scala 127:69]
  wire  ways_1_clients = _ways_WIRE_3[26]; // @[Directory.scala 127:69]
  wire [1:0] ways_1_state = _ways_WIRE_3[28:27]; // @[Directory.scala 127:69]
  wire  ways_1_dirty = _ways_WIRE_3[29]; // @[Directory.scala 127:69]
  wire  _hits_T_6 = ways_0_tag == tag & ways_0_state != 2'h0 & (~setQuash | shiftAmount); // @[Directory.scala 129:42]
  wire  _hits_T_13 = ways_1_tag == tag & ways_1_state != 2'h0 & (~setQuash | ~write_io_deq_bits_way); // @[Directory.scala 129:42]
  wire [1:0] hits = {_hits_T_13,_hits_T_6}; // @[Cat.scala 33:92]
  wire  hit = |hits; // @[Directory.scala 131:21]
  wire [25:0] _io_result_bits_T_2 = hits[0] ? ways_0_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _io_result_bits_T_3 = hits[1] ? ways_1_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _io_result_bits_T_4 = _io_result_bits_T_2 | _io_result_bits_T_3; // @[Mux.scala 27:73]
  wire  _io_result_bits_T_7 = hits[0] & ways_0_clients | hits[1] & ways_1_clients; // @[Mux.scala 27:73]
  wire [1:0] _io_result_bits_T_8 = hits[0] ? ways_0_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_result_bits_T_9 = hits[1] ? ways_1_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_result_bits_T_10 = _io_result_bits_T_8 | _io_result_bits_T_9; // @[Mux.scala 27:73]
  wire  _io_result_bits_T_13 = hits[0] & ways_0_dirty | hits[1] & ways_1_dirty; // @[Mux.scala 27:73]
  wire [25:0] _io_result_bits_T_18 = victimWayOH[0] ? ways_0_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _io_result_bits_T_19 = victimWay ? ways_1_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _io_result_bits_T_20 = _io_result_bits_T_18 | _io_result_bits_T_19; // @[Mux.scala 27:73]
  wire  _io_result_bits_T_23 = victimWayOH[0] & ways_0_clients | victimWay & ways_1_clients; // @[Mux.scala 27:73]
  wire [1:0] _io_result_bits_T_24 = victimWayOH[0] ? ways_0_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_result_bits_T_25 = victimWay ? ways_1_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_result_bits_T_26 = _io_result_bits_T_24 | _io_result_bits_T_25; // @[Mux.scala 27:73]
  wire  _io_result_bits_T_29 = victimWayOH[0] & ways_0_dirty | victimWay & ways_1_dirty; // @[Mux.scala 27:73]
  wire  _io_result_bits_T_30_dirty = setQuash & (tagMatch | wayMatch) ? write_io_deq_bits_data_dirty :
    _io_result_bits_T_29; // @[Directory.scala 134:52]
  wire [1:0] _io_result_bits_T_30_state = setQuash & (tagMatch | wayMatch) ? write_io_deq_bits_data_state :
    _io_result_bits_T_26; // @[Directory.scala 134:52]
  wire  _io_result_bits_T_30_clients = setQuash & (tagMatch | wayMatch) ? write_io_deq_bits_data_clients :
    _io_result_bits_T_23; // @[Directory.scala 134:52]
  wire [25:0] _io_result_bits_T_30_tag = setQuash & (tagMatch | wayMatch) ? write_io_deq_bits_data_tag :
    _io_result_bits_T_20; // @[Directory.scala 134:52]
  wire  _io_result_bits_hit_T = setQuash & tagMatch; // @[Directory.scala 135:42]
  wire  _io_result_bits_way_T_2 = _io_result_bits_hit_T ? write_io_deq_bits_way : victimWay; // @[Directory.scala 136:53]
  Queue_30 write ( // @[Decoupled.scala 377:21]
    .clock(write_clock),
    .reset(write_reset),
    .io_enq_ready(write_io_enq_ready),
    .io_enq_valid(write_io_enq_valid),
    .io_enq_bits_set(write_io_enq_bits_set),
    .io_enq_bits_way(write_io_enq_bits_way),
    .io_enq_bits_data_dirty(write_io_enq_bits_data_dirty),
    .io_enq_bits_data_state(write_io_enq_bits_data_state),
    .io_enq_bits_data_clients(write_io_enq_bits_data_clients),
    .io_enq_bits_data_tag(write_io_enq_bits_data_tag),
    .io_deq_ready(write_io_deq_ready),
    .io_deq_valid(write_io_deq_valid),
    .io_deq_bits_set(write_io_deq_bits_set),
    .io_deq_bits_way(write_io_deq_bits_way),
    .io_deq_bits_data_dirty(write_io_deq_bits_data_dirty),
    .io_deq_bits_data_state(write_io_deq_bits_data_state),
    .io_deq_bits_data_clients(write_io_deq_bits_data_clients),
    .io_deq_bits_data_tag(write_io_deq_bits_data_tag)
  );
  MaxPeriodFibonacciLFSR_8 victimLFSR_prng ( // @[PRNG.scala 91:22]
    .clock(victimLFSR_prng_clock),
    .reset(victimLFSR_prng_reset),
    .io_increment(victimLFSR_prng_io_increment),
    .io_out_0(victimLFSR_prng_io_out_0),
    .io_out_1(victimLFSR_prng_io_out_1),
    .io_out_2(victimLFSR_prng_io_out_2),
    .io_out_3(victimLFSR_prng_io_out_3),
    .io_out_4(victimLFSR_prng_io_out_4),
    .io_out_5(victimLFSR_prng_io_out_5),
    .io_out_6(victimLFSR_prng_io_out_6),
    .io_out_7(victimLFSR_prng_io_out_7),
    .io_out_8(victimLFSR_prng_io_out_8),
    .io_out_9(victimLFSR_prng_io_out_9),
    .io_out_10(victimLFSR_prng_io_out_10),
    .io_out_11(victimLFSR_prng_io_out_11),
    .io_out_12(victimLFSR_prng_io_out_12),
    .io_out_13(victimLFSR_prng_io_out_13),
    .io_out_14(victimLFSR_prng_io_out_14),
    .io_out_15(victimLFSR_prng_io_out_15)
  );
  assign cc_dir_0_regout_en = cc_dir_0_regout_en_pipe_0;
  assign cc_dir_0_regout_addr = cc_dir_0_regout_addr_pipe_0;
  assign cc_dir_0_regout_data = cc_dir_0[cc_dir_0_regout_addr]; // @[DescribedSRAM.scala 19:26]
  assign cc_dir_0_MPORT_data = wipeDone ? _T_16 : 30'h0;
  assign cc_dir_0_MPORT_addr = wipeDone ? write_io_deq_bits_set : wipeSet;
  assign cc_dir_0_MPORT_mask = _T_20[0] | _T;
  assign cc_dir_0_MPORT_en = _T_3 & wen;
  assign cc_dir_1_regout_en = cc_dir_1_regout_en_pipe_0;
  assign cc_dir_1_regout_addr = cc_dir_1_regout_addr_pipe_0;
  assign cc_dir_1_regout_data = cc_dir_1[cc_dir_1_regout_addr]; // @[DescribedSRAM.scala 19:26]
  assign cc_dir_1_MPORT_data = wipeDone ? _T_16 : 30'h0;
  assign cc_dir_1_MPORT_addr = wipeDone ? write_io_deq_bits_set : wipeSet;
  assign cc_dir_1_MPORT_mask = _T_20[1] | _T;
  assign cc_dir_1_MPORT_en = _T_3 & wen;
  assign io_write_ready = write_io_enq_ready; // @[Decoupled.scala 381:17]
  assign io_result_bits_dirty = hit ? _io_result_bits_T_13 : _io_result_bits_T_30_dirty; // @[Directory.scala 134:24]
  assign io_result_bits_state = hit ? _io_result_bits_T_10 : _io_result_bits_T_30_state; // @[Directory.scala 134:24]
  assign io_result_bits_clients = hit ? _io_result_bits_T_7 : _io_result_bits_T_30_clients; // @[Directory.scala 134:24]
  assign io_result_bits_tag = hit ? _io_result_bits_T_4 : _io_result_bits_T_30_tag; // @[Directory.scala 134:24]
  assign io_result_bits_hit = hit | setQuash & tagMatch & write_io_deq_bits_data_state != 2'h0; // @[Directory.scala 135:29]
  assign io_result_bits_way = hit ? hits[1] : _io_result_bits_way_T_2; // @[Directory.scala 136:28]
  assign io_ready = wipeCount[2]; // @[Directory.scala 79:27]
  assign write_clock = clock;
  assign write_reset = reset;
  assign write_io_enq_valid = io_write_valid; // @[Decoupled.scala 379:22]
  assign write_io_enq_bits_set = io_write_bits_set; // @[Decoupled.scala 380:21]
  assign write_io_enq_bits_way = io_write_bits_way; // @[Decoupled.scala 380:21]
  assign write_io_enq_bits_data_dirty = io_write_bits_data_dirty; // @[Decoupled.scala 380:21]
  assign write_io_enq_bits_data_state = io_write_bits_data_state; // @[Decoupled.scala 380:21]
  assign write_io_enq_bits_data_clients = io_write_bits_data_clients; // @[Decoupled.scala 380:21]
  assign write_io_enq_bits_data_tag = io_write_bits_data_tag; // @[Decoupled.scala 380:21]
  assign write_io_deq_ready = ~io_read_valid; // @[Directory.scala 93:18]
  assign victimLFSR_prng_clock = clock;
  assign victimLFSR_prng_reset = reset;
  assign victimLFSR_prng_io_increment = io_read_valid; // @[PRNG.scala 94:23]
  always @(posedge clock) begin
    if (cc_dir_0_MPORT_en & cc_dir_0_MPORT_mask) begin
      cc_dir_0[cc_dir_0_MPORT_addr] <= cc_dir_0_MPORT_data; // @[DescribedSRAM.scala 19:26]
    end
    cc_dir_0_regout_en_pipe_0 <= io_read_valid;
    if (io_read_valid) begin
      cc_dir_0_regout_addr_pipe_0 <= io_read_bits_set;
    end
    if (cc_dir_1_MPORT_en & cc_dir_1_MPORT_mask) begin
      cc_dir_1[cc_dir_1_MPORT_addr] <= cc_dir_1_MPORT_data; // @[DescribedSRAM.scala 19:26]
    end
    cc_dir_1_regout_en_pipe_0 <= io_read_valid;
    if (io_read_valid) begin
      cc_dir_1_regout_addr_pipe_0 <= io_read_bits_set;
    end
    if (reset) begin // @[Directory.scala 77:26]
      wipeCount <= 3'h0; // @[Directory.scala 77:26]
    end else if (~wipeDone & ~wipeOff) begin // @[Directory.scala 83:32]
      wipeCount <= _wipeCount_T_1; // @[Directory.scala 83:44]
    end
    wipeOff <= reset; // @[Directory.scala 78:{24,24,24}]
    if (reset) begin // @[Directory.scala 101:21]
      ren1 <= 1'h0; // @[Directory.scala 101:21]
    end else begin
      ren1 <= io_read_valid; // @[Directory.scala 104:8]
    end
    if (io_read_valid) begin // @[Reg.scala 20:18]
      tag <= io_read_bits_tag; // @[Reg.scala 20:22]
    end
    if (io_read_valid) begin // @[Reg.scala 20:18]
      set <= io_read_bits_set; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(wipeDone | ~io_read_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Directory.scala:84 assert (wipeDone || !io.read.valid)\n"); // @[Directory.scala 84:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(wipeDone | ~io_read_valid) & ~reset) begin
          $fatal; // @[Directory.scala 84:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & ~(_T_3 | wipeDone)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Directory.scala:89 assert (!io.read.valid || wipeDone)\n"); // @[Directory.scala 89:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_3 | wipeDone) & _T_6) begin
          $fatal; // @[Directory.scala 89:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & ~(~ren1 | victimLTE[0])) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Directory.scala:119 assert (!ren2 || victimLTE(0) === UInt(1))\n"); // @[Directory.scala 119:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~ren1 | victimLTE[0]) & _T_6) begin
          $fatal; // @[Directory.scala 119:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & ~(_T_28 | _T_38 == 3'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Directory.scala:120 assert (!ren2 || ((victimSimp >> 1) & ~victimSimp) === UInt(0)) // monotone\n"
            ); // @[Directory.scala 120:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_28 | _T_38 == 3'h0) & _T_6) begin
          $fatal; // @[Directory.scala 120:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_6 & ~(_T_28 | _T_47 == 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Directory.scala:121 assert (!ren2 || PopCount(victimWayOH) === UInt(1))\n"); // @[Directory.scala 121:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_28 | _T_47 == 2'h1) & _T_6) begin
          $fatal; // @[Directory.scala 121:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    cc_dir_0[initvar] = _RAND_0[29:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    cc_dir_1[initvar] = _RAND_3[29:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  cc_dir_0_regout_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  cc_dir_0_regout_addr_pipe_0 = _RAND_2[1:0];
  _RAND_4 = {1{`RANDOM}};
  cc_dir_1_regout_en_pipe_0 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  cc_dir_1_regout_addr_pipe_0 = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  wipeCount = _RAND_6[2:0];
  _RAND_7 = {1{`RANDOM}};
  wipeOff = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  ren1 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  tag = _RAND_9[25:0];
  _RAND_10 = {1{`RANDOM}};
  set = _RAND_10[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module BankedStore(
  input         clock,
  output        io_sinkC_adr_ready,
  input         io_sinkC_adr_valid,
  input         io_sinkC_adr_bits_noop,
  input         io_sinkC_adr_bits_way,
  input  [1:0]  io_sinkC_adr_bits_set,
  input         io_sinkC_adr_bits_beat,
  input         io_sinkC_adr_bits_mask,
  input  [63:0] io_sinkC_dat_data,
  output        io_sinkD_adr_ready,
  input         io_sinkD_adr_valid,
  input         io_sinkD_adr_bits_noop,
  input         io_sinkD_adr_bits_way,
  input  [1:0]  io_sinkD_adr_bits_set,
  input         io_sinkD_adr_bits_beat,
  input  [63:0] io_sinkD_dat_data,
  output        io_sourceC_adr_ready,
  input         io_sourceC_adr_valid,
  input         io_sourceC_adr_bits_way,
  input  [1:0]  io_sourceC_adr_bits_set,
  input         io_sourceC_adr_bits_beat,
  output [63:0] io_sourceC_dat_data,
  output        io_sourceD_radr_ready,
  input         io_sourceD_radr_valid,
  input         io_sourceD_radr_bits_way,
  input  [1:0]  io_sourceD_radr_bits_set,
  input         io_sourceD_radr_bits_beat,
  input         io_sourceD_radr_bits_mask,
  output [63:0] io_sourceD_rdat_data,
  output        io_sourceD_wadr_ready,
  input         io_sourceD_wadr_valid,
  input         io_sourceD_wadr_bits_way,
  input  [1:0]  io_sourceD_wadr_bits_set,
  input         io_sourceD_wadr_bits_beat,
  input         io_sourceD_wadr_bits_mask,
  input  [63:0] io_sourceD_wdat_data
);
`ifdef RANDOMIZE_MEM_INIT
  reg [63:0] _RAND_0;
  reg [63:0] _RAND_3;
  reg [63:0] _RAND_6;
  reg [63:0] _RAND_9;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [63:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [63:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [63:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] cc_banks_0 [0:3]; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_0_regout_MPORT_1_en; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_banks_0_regout_MPORT_1_addr; // @[DescribedSRAM.scala 19:26]
  wire [63:0] cc_banks_0_regout_MPORT_1_data; // @[DescribedSRAM.scala 19:26]
  wire [63:0] cc_banks_0_regout_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_banks_0_regout_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_0_regout_MPORT_mask; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_0_regout_MPORT_en; // @[DescribedSRAM.scala 19:26]
  reg  cc_banks_0_regout_MPORT_1_en_pipe_0;
  reg [1:0] cc_banks_0_regout_MPORT_1_addr_pipe_0;
  reg [63:0] cc_banks_1 [0:3]; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_1_regout_MPORT_3_en; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_banks_1_regout_MPORT_3_addr; // @[DescribedSRAM.scala 19:26]
  wire [63:0] cc_banks_1_regout_MPORT_3_data; // @[DescribedSRAM.scala 19:26]
  wire [63:0] cc_banks_1_regout_MPORT_2_data; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_banks_1_regout_MPORT_2_addr; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_1_regout_MPORT_2_mask; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_1_regout_MPORT_2_en; // @[DescribedSRAM.scala 19:26]
  reg  cc_banks_1_regout_MPORT_3_en_pipe_0;
  reg [1:0] cc_banks_1_regout_MPORT_3_addr_pipe_0;
  reg [63:0] cc_banks_2 [0:3]; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_2_regout_MPORT_5_en; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_banks_2_regout_MPORT_5_addr; // @[DescribedSRAM.scala 19:26]
  wire [63:0] cc_banks_2_regout_MPORT_5_data; // @[DescribedSRAM.scala 19:26]
  wire [63:0] cc_banks_2_regout_MPORT_4_data; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_banks_2_regout_MPORT_4_addr; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_2_regout_MPORT_4_mask; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_2_regout_MPORT_4_en; // @[DescribedSRAM.scala 19:26]
  reg  cc_banks_2_regout_MPORT_5_en_pipe_0;
  reg [1:0] cc_banks_2_regout_MPORT_5_addr_pipe_0;
  reg [63:0] cc_banks_3 [0:3]; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_3_regout_MPORT_7_en; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_banks_3_regout_MPORT_7_addr; // @[DescribedSRAM.scala 19:26]
  wire [63:0] cc_banks_3_regout_MPORT_7_data; // @[DescribedSRAM.scala 19:26]
  wire [63:0] cc_banks_3_regout_MPORT_6_data; // @[DescribedSRAM.scala 19:26]
  wire [1:0] cc_banks_3_regout_MPORT_6_addr; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_3_regout_MPORT_6_mask; // @[DescribedSRAM.scala 19:26]
  wire  cc_banks_3_regout_MPORT_6_en; // @[DescribedSRAM.scala 19:26]
  reg  cc_banks_3_regout_MPORT_7_en_pipe_0;
  reg [1:0] cc_banks_3_regout_MPORT_7_addr_pipe_0;
  wire [3:0] sinkC_req_a = {io_sinkC_adr_bits_way,io_sinkC_adr_bits_set,io_sinkC_adr_bits_beat}; // @[Cat.scala 33:92]
  wire [1:0] sinkC_req_select_shiftAmount = sinkC_req_a[1:0]; // @[BankedStore.scala 129:28]
  wire [3:0] sinkC_req_select = 4'h1 << sinkC_req_select_shiftAmount; // @[OneHot.scala 64:12]
  wire [3:0] _sinkC_req_io_sinkC_adr_ready_T_1 = 4'hf >> sinkC_req_select_shiftAmount; // @[BankedStore.scala 131:21]
  wire [1:0] reqs_0_index = sinkC_req_a[3:2]; // @[BankedStore.scala 134:23]
  wire [3:0] _sinkC_req_out_bankSel_T_4 = {sinkC_req_select[3],sinkC_req_select[2],sinkC_req_select[1],sinkC_req_select[
    0]}; // @[Cat.scala 33:92]
  wire [3:0] _sinkC_req_out_bankSel_T_6 = io_sinkC_adr_bits_mask ? 4'hf : 4'h0; // @[Bitwise.scala 77:12]
  wire [3:0] _sinkC_req_out_bankSel_T_7 = _sinkC_req_out_bankSel_T_4 & _sinkC_req_out_bankSel_T_6; // @[BankedStore.scala 135:65]
  wire [3:0] reqs_0_bankSel = io_sinkC_adr_valid ? _sinkC_req_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala 135:24]
  wire [3:0] reqs_0_bankEn = io_sinkC_adr_bits_noop ? 4'h0 : reqs_0_bankSel; // @[BankedStore.scala 136:24]
  wire [3:0] sinkD_req_a = {io_sinkD_adr_bits_way,io_sinkD_adr_bits_set,io_sinkD_adr_bits_beat}; // @[Cat.scala 33:92]
  wire [1:0] sinkD_req_select_shiftAmount = sinkD_req_a[1:0]; // @[BankedStore.scala 129:28]
  wire [3:0] sinkD_req_select = 4'h1 << sinkD_req_select_shiftAmount; // @[OneHot.scala 64:12]
  wire [3:0] sourceC_req_a = {io_sourceC_adr_bits_way,io_sourceC_adr_bits_set,io_sourceC_adr_bits_beat}; // @[Cat.scala 33:92]
  wire [1:0] sourceC_req_select_shiftAmount = sourceC_req_a[1:0]; // @[BankedStore.scala 129:28]
  wire [3:0] sourceC_req_select = 4'h1 << sourceC_req_select_shiftAmount; // @[OneHot.scala 64:12]
  wire [3:0] _sourceC_req_out_bankSel_T_4 = {sourceC_req_select[3],sourceC_req_select[2],sourceC_req_select[1],
    sourceC_req_select[0]}; // @[Cat.scala 33:92]
  wire [3:0] reqs_1_bankSel = io_sourceC_adr_valid ? _sourceC_req_out_bankSel_T_4 : 4'h0; // @[BankedStore.scala 135:24]
  wire [3:0] reqs_2_bankSum = reqs_1_bankSel | reqs_0_bankSel; // @[BankedStore.scala 160:17]
  wire  _sinkD_req_ready_T_3 = ~(|reqs_2_bankSum[0]); // @[BankedStore.scala 130:58]
  wire  _sinkD_req_ready_T_7 = ~(|reqs_2_bankSum[1]); // @[BankedStore.scala 130:58]
  wire  _sinkD_req_ready_T_11 = ~(|reqs_2_bankSum[2]); // @[BankedStore.scala 130:58]
  wire  _sinkD_req_ready_T_15 = ~(|reqs_2_bankSum[3]); // @[BankedStore.scala 130:58]
  wire [3:0] sinkD_req_ready = {_sinkD_req_ready_T_15,_sinkD_req_ready_T_11,_sinkD_req_ready_T_7,_sinkD_req_ready_T_3}; // @[Cat.scala 33:92]
  wire [3:0] _sinkD_req_io_sinkD_adr_ready_T_1 = sinkD_req_ready >> sinkD_req_select_shiftAmount; // @[BankedStore.scala 131:21]
  wire [1:0] reqs_2_index = sinkD_req_a[3:2]; // @[BankedStore.scala 134:23]
  wire [3:0] _sinkD_req_out_bankSel_T_4 = {sinkD_req_select[3],sinkD_req_select[2],sinkD_req_select[1],sinkD_req_select[
    0]}; // @[Cat.scala 33:92]
  wire [3:0] reqs_2_bankSel = io_sinkD_adr_valid ? _sinkD_req_out_bankSel_T_4 : 4'h0; // @[BankedStore.scala 135:24]
  wire [3:0] _sinkD_req_out_bankEn_T_4 = {sinkD_req_ready[3],sinkD_req_ready[2],sinkD_req_ready[1],sinkD_req_ready[0]}; // @[Cat.scala 33:92]
  wire [3:0] _sinkD_req_out_bankEn_T_5 = reqs_2_bankSel & _sinkD_req_out_bankEn_T_4; // @[BankedStore.scala 136:59]
  wire [3:0] reqs_2_bankEn = io_sinkD_adr_bits_noop ? 4'h0 : _sinkD_req_out_bankEn_T_5; // @[BankedStore.scala 136:24]
  wire  _sourceC_req_ready_T_3 = ~(|reqs_0_bankSel[0]); // @[BankedStore.scala 130:58]
  wire  _sourceC_req_ready_T_7 = ~(|reqs_0_bankSel[1]); // @[BankedStore.scala 130:58]
  wire  _sourceC_req_ready_T_11 = ~(|reqs_0_bankSel[2]); // @[BankedStore.scala 130:58]
  wire  _sourceC_req_ready_T_15 = ~(|reqs_0_bankSel[3]); // @[BankedStore.scala 130:58]
  wire [3:0] sourceC_req_ready = {_sourceC_req_ready_T_15,_sourceC_req_ready_T_11,_sourceC_req_ready_T_7,
    _sourceC_req_ready_T_3}; // @[Cat.scala 33:92]
  wire [3:0] _sourceC_req_io_sourceC_adr_ready_T_1 = sourceC_req_ready >> sourceC_req_select_shiftAmount; // @[BankedStore.scala 131:21]
  wire [1:0] reqs_1_index = sourceC_req_a[3:2]; // @[BankedStore.scala 134:23]
  wire [3:0] _sourceC_req_out_bankEn_T_4 = {sourceC_req_ready[3],sourceC_req_ready[2],sourceC_req_ready[1],
    sourceC_req_ready[0]}; // @[Cat.scala 33:92]
  wire [3:0] reqs_1_bankEn = reqs_1_bankSel & _sourceC_req_out_bankEn_T_4; // @[BankedStore.scala 136:59]
  wire [3:0] sourceD_rreq_a = {io_sourceD_radr_bits_way,io_sourceD_radr_bits_set,io_sourceD_radr_bits_beat}; // @[Cat.scala 33:92]
  wire [1:0] sourceD_rreq_select_shiftAmount = sourceD_rreq_a[1:0]; // @[BankedStore.scala 129:28]
  wire [3:0] sourceD_rreq_select = 4'h1 << sourceD_rreq_select_shiftAmount; // @[OneHot.scala 64:12]
  wire [3:0] sourceD_wreq_a = {io_sourceD_wadr_bits_way,io_sourceD_wadr_bits_set,io_sourceD_wadr_bits_beat}; // @[Cat.scala 33:92]
  wire [1:0] sourceD_wreq_select_shiftAmount = sourceD_wreq_a[1:0]; // @[BankedStore.scala 129:28]
  wire [3:0] sourceD_wreq_select = 4'h1 << sourceD_wreq_select_shiftAmount; // @[OneHot.scala 64:12]
  wire [3:0] _sourceD_wreq_out_bankSel_T_4 = {sourceD_wreq_select[3],sourceD_wreq_select[2],sourceD_wreq_select[1],
    sourceD_wreq_select[0]}; // @[Cat.scala 33:92]
  wire [3:0] _sourceD_wreq_out_bankSel_T_6 = io_sourceD_wadr_bits_mask ? 4'hf : 4'h0; // @[Bitwise.scala 77:12]
  wire [3:0] _sourceD_wreq_out_bankSel_T_7 = _sourceD_wreq_out_bankSel_T_4 & _sourceD_wreq_out_bankSel_T_6; // @[BankedStore.scala 135:65]
  wire [3:0] reqs_3_bankSel = io_sourceD_wadr_valid ? _sourceD_wreq_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala 135:24]
  wire [3:0] reqs_3_bankSum = reqs_2_bankSel | reqs_2_bankSum; // @[BankedStore.scala 160:17]
  wire [3:0] reqs_4_bankSum = reqs_3_bankSel | reqs_3_bankSum; // @[BankedStore.scala 160:17]
  wire  _sourceD_rreq_ready_T_3 = ~(|(reqs_4_bankSum[0] & io_sourceD_radr_bits_mask)); // @[BankedStore.scala 130:58]
  wire  _sourceD_rreq_ready_T_7 = ~(|(reqs_4_bankSum[1] & io_sourceD_radr_bits_mask)); // @[BankedStore.scala 130:58]
  wire  _sourceD_rreq_ready_T_11 = ~(|(reqs_4_bankSum[2] & io_sourceD_radr_bits_mask)); // @[BankedStore.scala 130:58]
  wire  _sourceD_rreq_ready_T_15 = ~(|(reqs_4_bankSum[3] & io_sourceD_radr_bits_mask)); // @[BankedStore.scala 130:58]
  wire [3:0] sourceD_rreq_ready = {_sourceD_rreq_ready_T_15,_sourceD_rreq_ready_T_11,_sourceD_rreq_ready_T_7,
    _sourceD_rreq_ready_T_3}; // @[Cat.scala 33:92]
  wire [3:0] _sourceD_rreq_io_sourceD_radr_ready_T_1 = sourceD_rreq_ready >> sourceD_rreq_select_shiftAmount; // @[BankedStore.scala 131:21]
  wire [1:0] reqs_4_index = sourceD_rreq_a[3:2]; // @[BankedStore.scala 134:23]
  wire [3:0] _sourceD_rreq_out_bankSel_T_4 = {sourceD_rreq_select[3],sourceD_rreq_select[2],sourceD_rreq_select[1],
    sourceD_rreq_select[0]}; // @[Cat.scala 33:92]
  wire [3:0] _sourceD_rreq_out_bankSel_T_6 = io_sourceD_radr_bits_mask ? 4'hf : 4'h0; // @[Bitwise.scala 77:12]
  wire [3:0] _sourceD_rreq_out_bankSel_T_7 = _sourceD_rreq_out_bankSel_T_4 & _sourceD_rreq_out_bankSel_T_6; // @[BankedStore.scala 135:65]
  wire [3:0] reqs_4_bankSel = io_sourceD_radr_valid ? _sourceD_rreq_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala 135:24]
  wire [3:0] _sourceD_rreq_out_bankEn_T_4 = {sourceD_rreq_ready[3],sourceD_rreq_ready[2],sourceD_rreq_ready[1],
    sourceD_rreq_ready[0]}; // @[Cat.scala 33:92]
  wire [3:0] reqs_4_bankEn = reqs_4_bankSel & _sourceD_rreq_out_bankEn_T_4; // @[BankedStore.scala 136:59]
  wire  _sourceD_wreq_ready_T_3 = ~(|(reqs_3_bankSum[0] & io_sourceD_wadr_bits_mask)); // @[BankedStore.scala 130:58]
  wire  _sourceD_wreq_ready_T_7 = ~(|(reqs_3_bankSum[1] & io_sourceD_wadr_bits_mask)); // @[BankedStore.scala 130:58]
  wire  _sourceD_wreq_ready_T_11 = ~(|(reqs_3_bankSum[2] & io_sourceD_wadr_bits_mask)); // @[BankedStore.scala 130:58]
  wire  _sourceD_wreq_ready_T_15 = ~(|(reqs_3_bankSum[3] & io_sourceD_wadr_bits_mask)); // @[BankedStore.scala 130:58]
  wire [3:0] sourceD_wreq_ready = {_sourceD_wreq_ready_T_15,_sourceD_wreq_ready_T_11,_sourceD_wreq_ready_T_7,
    _sourceD_wreq_ready_T_3}; // @[Cat.scala 33:92]
  wire [3:0] _sourceD_wreq_io_sourceD_wadr_ready_T_1 = sourceD_wreq_ready >> sourceD_wreq_select_shiftAmount; // @[BankedStore.scala 131:21]
  wire [1:0] reqs_3_index = sourceD_wreq_a[3:2]; // @[BankedStore.scala 134:23]
  wire [3:0] _sourceD_wreq_out_bankEn_T_4 = {sourceD_wreq_ready[3],sourceD_wreq_ready[2],sourceD_wreq_ready[1],
    sourceD_wreq_ready[0]}; // @[Cat.scala 33:92]
  wire [3:0] reqs_3_bankEn = reqs_3_bankSel & _sourceD_wreq_out_bankEn_T_4; // @[BankedStore.scala 136:59]
  wire  regout_en = reqs_0_bankEn[0] | reqs_1_bankEn[0] | reqs_2_bankEn[0] | reqs_3_bankEn[0] | reqs_4_bankEn[0]; // @[BankedStore.scala 164:45]
  wire  regout_sel_1 = reqs_1_bankSel[0]; // @[BankedStore.scala 165:33]
  wire  regout_sel_2 = reqs_2_bankSel[0]; // @[BankedStore.scala 165:33]
  wire  regout_sel_3 = reqs_3_bankSel[0]; // @[BankedStore.scala 165:33]
  wire  _regout_wen_T_2 = regout_sel_1 ? 1'h0 : regout_sel_2 | regout_sel_3; // @[Mux.scala 47:70]
  wire  regout_wen = reqs_0_bankSel[0] | _regout_wen_T_2; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T = regout_sel_3 ? reqs_3_index : reqs_4_index; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_1 = regout_sel_2 ? reqs_2_index : _regout_idx_T; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_2 = regout_sel_1 ? reqs_1_index : _regout_idx_T_1; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T = regout_sel_3 ? io_sourceD_wdat_data : 64'h0; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_1 = regout_sel_2 ? io_sinkD_dat_data : _regout_data_T; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_2 = regout_sel_1 ? 64'h0 : _regout_data_T_1; // @[Mux.scala 47:70]
  wire  _regout_T_1 = ~regout_wen; // @[BankedStore.scala 171:27]
  reg  regout_REG; // @[BankedStore.scala 171:47]
  reg [63:0] regout_r; // @[Reg.scala 19:16]
  wire  regout_en_1 = reqs_0_bankEn[1] | reqs_1_bankEn[1] | reqs_2_bankEn[1] | reqs_3_bankEn[1] | reqs_4_bankEn[1]; // @[BankedStore.scala 164:45]
  wire  regout_sel_1_1 = reqs_1_bankSel[1]; // @[BankedStore.scala 165:33]
  wire  regout_sel_2_1 = reqs_2_bankSel[1]; // @[BankedStore.scala 165:33]
  wire  regout_sel_3_1 = reqs_3_bankSel[1]; // @[BankedStore.scala 165:33]
  wire  _regout_wen_T_5 = regout_sel_1_1 ? 1'h0 : regout_sel_2_1 | regout_sel_3_1; // @[Mux.scala 47:70]
  wire  regout_wen_1 = reqs_0_bankSel[1] | _regout_wen_T_5; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_3 = regout_sel_3_1 ? reqs_3_index : reqs_4_index; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_4 = regout_sel_2_1 ? reqs_2_index : _regout_idx_T_3; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_5 = regout_sel_1_1 ? reqs_1_index : _regout_idx_T_4; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_3 = regout_sel_3_1 ? io_sourceD_wdat_data : 64'h0; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_4 = regout_sel_2_1 ? io_sinkD_dat_data : _regout_data_T_3; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_5 = regout_sel_1_1 ? 64'h0 : _regout_data_T_4; // @[Mux.scala 47:70]
  wire  _regout_T_8 = ~regout_wen_1; // @[BankedStore.scala 171:27]
  reg  regout_REG_1; // @[BankedStore.scala 171:47]
  reg [63:0] regout_r_1; // @[Reg.scala 19:16]
  wire  regout_en_2 = reqs_0_bankEn[2] | reqs_1_bankEn[2] | reqs_2_bankEn[2] | reqs_3_bankEn[2] | reqs_4_bankEn[2]; // @[BankedStore.scala 164:45]
  wire  regout_sel_1_2 = reqs_1_bankSel[2]; // @[BankedStore.scala 165:33]
  wire  regout_sel_2_2 = reqs_2_bankSel[2]; // @[BankedStore.scala 165:33]
  wire  regout_sel_3_2 = reqs_3_bankSel[2]; // @[BankedStore.scala 165:33]
  wire  _regout_wen_T_8 = regout_sel_1_2 ? 1'h0 : regout_sel_2_2 | regout_sel_3_2; // @[Mux.scala 47:70]
  wire  regout_wen_2 = reqs_0_bankSel[2] | _regout_wen_T_8; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_6 = regout_sel_3_2 ? reqs_3_index : reqs_4_index; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_7 = regout_sel_2_2 ? reqs_2_index : _regout_idx_T_6; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_8 = regout_sel_1_2 ? reqs_1_index : _regout_idx_T_7; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_6 = regout_sel_3_2 ? io_sourceD_wdat_data : 64'h0; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_7 = regout_sel_2_2 ? io_sinkD_dat_data : _regout_data_T_6; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_8 = regout_sel_1_2 ? 64'h0 : _regout_data_T_7; // @[Mux.scala 47:70]
  wire  _regout_T_15 = ~regout_wen_2; // @[BankedStore.scala 171:27]
  reg  regout_REG_2; // @[BankedStore.scala 171:47]
  reg [63:0] regout_r_2; // @[Reg.scala 19:16]
  wire  regout_en_3 = reqs_0_bankEn[3] | reqs_1_bankEn[3] | reqs_2_bankEn[3] | reqs_3_bankEn[3] | reqs_4_bankEn[3]; // @[BankedStore.scala 164:45]
  wire  regout_sel_1_3 = reqs_1_bankSel[3]; // @[BankedStore.scala 165:33]
  wire  regout_sel_2_3 = reqs_2_bankSel[3]; // @[BankedStore.scala 165:33]
  wire  regout_sel_3_3 = reqs_3_bankSel[3]; // @[BankedStore.scala 165:33]
  wire  _regout_wen_T_11 = regout_sel_1_3 ? 1'h0 : regout_sel_2_3 | regout_sel_3_3; // @[Mux.scala 47:70]
  wire  regout_wen_3 = reqs_0_bankSel[3] | _regout_wen_T_11; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_9 = regout_sel_3_3 ? reqs_3_index : reqs_4_index; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_10 = regout_sel_2_3 ? reqs_2_index : _regout_idx_T_9; // @[Mux.scala 47:70]
  wire [1:0] _regout_idx_T_11 = regout_sel_1_3 ? reqs_1_index : _regout_idx_T_10; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_9 = regout_sel_3_3 ? io_sourceD_wdat_data : 64'h0; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_10 = regout_sel_2_3 ? io_sinkD_dat_data : _regout_data_T_9; // @[Mux.scala 47:70]
  wire [63:0] _regout_data_T_11 = regout_sel_1_3 ? 64'h0 : _regout_data_T_10; // @[Mux.scala 47:70]
  wire  _regout_T_22 = ~regout_wen_3; // @[BankedStore.scala 171:27]
  reg  regout_REG_3; // @[BankedStore.scala 171:47]
  reg [63:0] regout_r_3; // @[Reg.scala 19:16]
  reg [3:0] regsel_sourceC_REG; // @[BankedStore.scala 174:39]
  reg [3:0] regsel_sourceC; // @[BankedStore.scala 174:31]
  reg [3:0] regsel_sourceD_REG; // @[BankedStore.scala 175:39]
  reg [3:0] regsel_sourceD; // @[BankedStore.scala 175:31]
  wire [63:0] _decodeC_T_1 = regsel_sourceC[0] ? regout_r : 64'h0; // @[BankedStore.scala 178:23]
  wire [63:0] _decodeC_T_3 = regsel_sourceC[1] ? regout_r_1 : 64'h0; // @[BankedStore.scala 178:23]
  wire [63:0] _decodeC_T_5 = regsel_sourceC[2] ? regout_r_2 : 64'h0; // @[BankedStore.scala 178:23]
  wire [63:0] _decodeC_T_7 = regsel_sourceC[3] ? regout_r_3 : 64'h0; // @[BankedStore.scala 178:23]
  wire [63:0] _decodeC_T_8 = _decodeC_T_1 | _decodeC_T_3; // @[BankedStore.scala 179:85]
  wire [63:0] _decodeC_T_9 = _decodeC_T_8 | _decodeC_T_5; // @[BankedStore.scala 179:85]
  wire [63:0] _decodeD_T_1 = regsel_sourceD[0] ? regout_r : 64'h0; // @[BankedStore.scala 185:23]
  wire [63:0] _decodeD_T_3 = regsel_sourceD[1] ? regout_r_1 : 64'h0; // @[BankedStore.scala 185:23]
  wire [63:0] _decodeD_T_5 = regsel_sourceD[2] ? regout_r_2 : 64'h0; // @[BankedStore.scala 185:23]
  wire [63:0] _decodeD_T_7 = regsel_sourceD[3] ? regout_r_3 : 64'h0; // @[BankedStore.scala 185:23]
  wire [63:0] _decodeD_T_8 = _decodeD_T_1 | _decodeD_T_3; // @[BankedStore.scala 186:85]
  wire [63:0] _decodeD_T_9 = _decodeD_T_8 | _decodeD_T_5; // @[BankedStore.scala 186:85]
  assign cc_banks_0_regout_MPORT_1_en = cc_banks_0_regout_MPORT_1_en_pipe_0;
  assign cc_banks_0_regout_MPORT_1_addr = cc_banks_0_regout_MPORT_1_addr_pipe_0;
  assign cc_banks_0_regout_MPORT_1_data = cc_banks_0[cc_banks_0_regout_MPORT_1_addr]; // @[DescribedSRAM.scala 19:26]
  assign cc_banks_0_regout_MPORT_data = reqs_0_bankSel[0] ? io_sinkC_dat_data : _regout_data_T_2;
  assign cc_banks_0_regout_MPORT_addr = reqs_0_bankSel[0] ? reqs_0_index : _regout_idx_T_2;
  assign cc_banks_0_regout_MPORT_mask = 1'h1;
  assign cc_banks_0_regout_MPORT_en = regout_wen & regout_en;
  assign cc_banks_1_regout_MPORT_3_en = cc_banks_1_regout_MPORT_3_en_pipe_0;
  assign cc_banks_1_regout_MPORT_3_addr = cc_banks_1_regout_MPORT_3_addr_pipe_0;
  assign cc_banks_1_regout_MPORT_3_data = cc_banks_1[cc_banks_1_regout_MPORT_3_addr]; // @[DescribedSRAM.scala 19:26]
  assign cc_banks_1_regout_MPORT_2_data = reqs_0_bankSel[1] ? io_sinkC_dat_data : _regout_data_T_5;
  assign cc_banks_1_regout_MPORT_2_addr = reqs_0_bankSel[1] ? reqs_0_index : _regout_idx_T_5;
  assign cc_banks_1_regout_MPORT_2_mask = 1'h1;
  assign cc_banks_1_regout_MPORT_2_en = regout_wen_1 & regout_en_1;
  assign cc_banks_2_regout_MPORT_5_en = cc_banks_2_regout_MPORT_5_en_pipe_0;
  assign cc_banks_2_regout_MPORT_5_addr = cc_banks_2_regout_MPORT_5_addr_pipe_0;
  assign cc_banks_2_regout_MPORT_5_data = cc_banks_2[cc_banks_2_regout_MPORT_5_addr]; // @[DescribedSRAM.scala 19:26]
  assign cc_banks_2_regout_MPORT_4_data = reqs_0_bankSel[2] ? io_sinkC_dat_data : _regout_data_T_8;
  assign cc_banks_2_regout_MPORT_4_addr = reqs_0_bankSel[2] ? reqs_0_index : _regout_idx_T_8;
  assign cc_banks_2_regout_MPORT_4_mask = 1'h1;
  assign cc_banks_2_regout_MPORT_4_en = regout_wen_2 & regout_en_2;
  assign cc_banks_3_regout_MPORT_7_en = cc_banks_3_regout_MPORT_7_en_pipe_0;
  assign cc_banks_3_regout_MPORT_7_addr = cc_banks_3_regout_MPORT_7_addr_pipe_0;
  assign cc_banks_3_regout_MPORT_7_data = cc_banks_3[cc_banks_3_regout_MPORT_7_addr]; // @[DescribedSRAM.scala 19:26]
  assign cc_banks_3_regout_MPORT_6_data = reqs_0_bankSel[3] ? io_sinkC_dat_data : _regout_data_T_11;
  assign cc_banks_3_regout_MPORT_6_addr = reqs_0_bankSel[3] ? reqs_0_index : _regout_idx_T_11;
  assign cc_banks_3_regout_MPORT_6_mask = 1'h1;
  assign cc_banks_3_regout_MPORT_6_en = regout_wen_3 & regout_en_3;
  assign io_sinkC_adr_ready = _sinkC_req_io_sinkC_adr_ready_T_1[0]; // @[BankedStore.scala 131:21]
  assign io_sinkD_adr_ready = _sinkD_req_io_sinkD_adr_ready_T_1[0]; // @[BankedStore.scala 131:21]
  assign io_sourceC_adr_ready = _sourceC_req_io_sourceC_adr_ready_T_1[0]; // @[BankedStore.scala 131:21]
  assign io_sourceC_dat_data = _decodeC_T_9 | _decodeC_T_7; // @[BankedStore.scala 179:85]
  assign io_sourceD_radr_ready = _sourceD_rreq_io_sourceD_radr_ready_T_1[0]; // @[BankedStore.scala 131:21]
  assign io_sourceD_rdat_data = _decodeD_T_9 | _decodeD_T_7; // @[BankedStore.scala 186:85]
  assign io_sourceD_wadr_ready = _sourceD_wreq_io_sourceD_wadr_ready_T_1[0]; // @[BankedStore.scala 131:21]
  always @(posedge clock) begin
    if (cc_banks_0_regout_MPORT_en & cc_banks_0_regout_MPORT_mask) begin
      cc_banks_0[cc_banks_0_regout_MPORT_addr] <= cc_banks_0_regout_MPORT_data; // @[DescribedSRAM.scala 19:26]
    end
    cc_banks_0_regout_MPORT_1_en_pipe_0 <= _regout_T_1 & regout_en;
    if (_regout_T_1 & regout_en) begin
      if (reqs_0_bankSel[0]) begin
        cc_banks_0_regout_MPORT_1_addr_pipe_0 <= reqs_0_index;
      end else if (regout_sel_1) begin // @[Mux.scala 47:70]
        cc_banks_0_regout_MPORT_1_addr_pipe_0 <= reqs_1_index;
      end else if (regout_sel_2) begin // @[Mux.scala 47:70]
        cc_banks_0_regout_MPORT_1_addr_pipe_0 <= reqs_2_index;
      end else begin
        cc_banks_0_regout_MPORT_1_addr_pipe_0 <= _regout_idx_T;
      end
    end
    if (cc_banks_1_regout_MPORT_2_en & cc_banks_1_regout_MPORT_2_mask) begin
      cc_banks_1[cc_banks_1_regout_MPORT_2_addr] <= cc_banks_1_regout_MPORT_2_data; // @[DescribedSRAM.scala 19:26]
    end
    cc_banks_1_regout_MPORT_3_en_pipe_0 <= _regout_T_8 & regout_en_1;
    if (_regout_T_8 & regout_en_1) begin
      if (reqs_0_bankSel[1]) begin
        cc_banks_1_regout_MPORT_3_addr_pipe_0 <= reqs_0_index;
      end else if (regout_sel_1_1) begin // @[Mux.scala 47:70]
        cc_banks_1_regout_MPORT_3_addr_pipe_0 <= reqs_1_index;
      end else if (regout_sel_2_1) begin // @[Mux.scala 47:70]
        cc_banks_1_regout_MPORT_3_addr_pipe_0 <= reqs_2_index;
      end else begin
        cc_banks_1_regout_MPORT_3_addr_pipe_0 <= _regout_idx_T_3;
      end
    end
    if (cc_banks_2_regout_MPORT_4_en & cc_banks_2_regout_MPORT_4_mask) begin
      cc_banks_2[cc_banks_2_regout_MPORT_4_addr] <= cc_banks_2_regout_MPORT_4_data; // @[DescribedSRAM.scala 19:26]
    end
    cc_banks_2_regout_MPORT_5_en_pipe_0 <= _regout_T_15 & regout_en_2;
    if (_regout_T_15 & regout_en_2) begin
      if (reqs_0_bankSel[2]) begin
        cc_banks_2_regout_MPORT_5_addr_pipe_0 <= reqs_0_index;
      end else if (regout_sel_1_2) begin // @[Mux.scala 47:70]
        cc_banks_2_regout_MPORT_5_addr_pipe_0 <= reqs_1_index;
      end else if (regout_sel_2_2) begin // @[Mux.scala 47:70]
        cc_banks_2_regout_MPORT_5_addr_pipe_0 <= reqs_2_index;
      end else begin
        cc_banks_2_regout_MPORT_5_addr_pipe_0 <= _regout_idx_T_6;
      end
    end
    if (cc_banks_3_regout_MPORT_6_en & cc_banks_3_regout_MPORT_6_mask) begin
      cc_banks_3[cc_banks_3_regout_MPORT_6_addr] <= cc_banks_3_regout_MPORT_6_data; // @[DescribedSRAM.scala 19:26]
    end
    cc_banks_3_regout_MPORT_7_en_pipe_0 <= _regout_T_22 & regout_en_3;
    if (_regout_T_22 & regout_en_3) begin
      if (reqs_0_bankSel[3]) begin
        cc_banks_3_regout_MPORT_7_addr_pipe_0 <= reqs_0_index;
      end else if (regout_sel_1_3) begin // @[Mux.scala 47:70]
        cc_banks_3_regout_MPORT_7_addr_pipe_0 <= reqs_1_index;
      end else if (regout_sel_2_3) begin // @[Mux.scala 47:70]
        cc_banks_3_regout_MPORT_7_addr_pipe_0 <= reqs_2_index;
      end else begin
        cc_banks_3_regout_MPORT_7_addr_pipe_0 <= _regout_idx_T_9;
      end
    end
    regout_REG <= ~regout_wen & regout_en; // @[BankedStore.scala 171:53]
    if (regout_REG) begin // @[Reg.scala 20:18]
      regout_r <= cc_banks_0_regout_MPORT_1_data; // @[Reg.scala 20:22]
    end
    regout_REG_1 <= ~regout_wen_1 & regout_en_1; // @[BankedStore.scala 171:53]
    if (regout_REG_1) begin // @[Reg.scala 20:18]
      regout_r_1 <= cc_banks_1_regout_MPORT_3_data; // @[Reg.scala 20:22]
    end
    regout_REG_2 <= ~regout_wen_2 & regout_en_2; // @[BankedStore.scala 171:53]
    if (regout_REG_2) begin // @[Reg.scala 20:18]
      regout_r_2 <= cc_banks_2_regout_MPORT_5_data; // @[Reg.scala 20:22]
    end
    regout_REG_3 <= ~regout_wen_3 & regout_en_3; // @[BankedStore.scala 171:53]
    if (regout_REG_3) begin // @[Reg.scala 20:18]
      regout_r_3 <= cc_banks_3_regout_MPORT_7_data; // @[Reg.scala 20:22]
    end
    regsel_sourceC_REG <= reqs_1_bankSel & _sourceC_req_out_bankEn_T_4; // @[BankedStore.scala 136:59]
    regsel_sourceC <= regsel_sourceC_REG; // @[BankedStore.scala 174:31]
    regsel_sourceD_REG <= reqs_4_bankSel & _sourceD_rreq_out_bankEn_T_4; // @[BankedStore.scala 136:59]
    regsel_sourceD <= regsel_sourceD_REG; // @[BankedStore.scala 175:31]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {2{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    cc_banks_0[initvar] = _RAND_0[63:0];
  _RAND_3 = {2{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    cc_banks_1[initvar] = _RAND_3[63:0];
  _RAND_6 = {2{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    cc_banks_2[initvar] = _RAND_6[63:0];
  _RAND_9 = {2{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    cc_banks_3[initvar] = _RAND_9[63:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  cc_banks_0_regout_MPORT_1_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  cc_banks_0_regout_MPORT_1_addr_pipe_0 = _RAND_2[1:0];
  _RAND_4 = {1{`RANDOM}};
  cc_banks_1_regout_MPORT_3_en_pipe_0 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  cc_banks_1_regout_MPORT_3_addr_pipe_0 = _RAND_5[1:0];
  _RAND_7 = {1{`RANDOM}};
  cc_banks_2_regout_MPORT_5_en_pipe_0 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  cc_banks_2_regout_MPORT_5_addr_pipe_0 = _RAND_8[1:0];
  _RAND_10 = {1{`RANDOM}};
  cc_banks_3_regout_MPORT_7_en_pipe_0 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  cc_banks_3_regout_MPORT_7_addr_pipe_0 = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  regout_REG = _RAND_12[0:0];
  _RAND_13 = {2{`RANDOM}};
  regout_r = _RAND_13[63:0];
  _RAND_14 = {1{`RANDOM}};
  regout_REG_1 = _RAND_14[0:0];
  _RAND_15 = {2{`RANDOM}};
  regout_r_1 = _RAND_15[63:0];
  _RAND_16 = {1{`RANDOM}};
  regout_REG_2 = _RAND_16[0:0];
  _RAND_17 = {2{`RANDOM}};
  regout_r_2 = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  regout_REG_3 = _RAND_18[0:0];
  _RAND_19 = {2{`RANDOM}};
  regout_r_3 = _RAND_19[63:0];
  _RAND_20 = {1{`RANDOM}};
  regsel_sourceC_REG = _RAND_20[3:0];
  _RAND_21 = {1{`RANDOM}};
  regsel_sourceC = _RAND_21[3:0];
  _RAND_22 = {1{`RANDOM}};
  regsel_sourceD_REG = _RAND_22[3:0];
  _RAND_23 = {1{`RANDOM}};
  regsel_sourceD = _RAND_23[3:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ListBuffer_2(
  input         clock,
  input         reset,
  output        io_push_ready,
  input         io_push_valid,
  input  [6:0]  io_push_bits_index,
  input         io_push_bits_data_prio_0,
  input         io_push_bits_data_prio_2,
  input  [2:0]  io_push_bits_data_opcode,
  input  [2:0]  io_push_bits_data_param,
  input  [2:0]  io_push_bits_data_size,
  input  [2:0]  io_push_bits_data_source,
  input  [25:0] io_push_bits_data_tag,
  input  [3:0]  io_push_bits_data_offset,
  input  [5:0]  io_push_bits_data_put,
  output [65:0] io_valid,
  input         io_pop_valid,
  input  [6:0]  io_pop_bits,
  output        io_data_prio_0,
  output        io_data_prio_1,
  output        io_data_prio_2,
  output [2:0]  io_data_opcode,
  output [2:0]  io_data_param,
  output [2:0]  io_data_size,
  output [2:0]  io_data_source,
  output [25:0] io_data_tag,
  output [3:0]  io_data_offset,
  output [5:0]  io_data_put
);
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_26;
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_25;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [95:0] _RAND_27;
  reg [31:0] _RAND_28;
`endif // RANDOMIZE_REG_INIT
  reg [4:0] head [0:65]; // @[ListBuffer.scala 46:18]
  wire  head_pop_head_en; // @[ListBuffer.scala 46:18]
  wire [6:0] head_pop_head_addr; // @[ListBuffer.scala 46:18]
  wire [4:0] head_pop_head_data; // @[ListBuffer.scala 46:18]
  wire [4:0] head_MPORT_2_data; // @[ListBuffer.scala 46:18]
  wire [6:0] head_MPORT_2_addr; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_2_mask; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_2_en; // @[ListBuffer.scala 46:18]
  wire [4:0] head_MPORT_6_data; // @[ListBuffer.scala 46:18]
  wire [6:0] head_MPORT_6_addr; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_6_mask; // @[ListBuffer.scala 46:18]
  wire  head_MPORT_6_en; // @[ListBuffer.scala 46:18]
  reg [4:0] tail [0:65]; // @[ListBuffer.scala 47:18]
  wire  tail_push_tail_en; // @[ListBuffer.scala 47:18]
  wire [6:0] tail_push_tail_addr; // @[ListBuffer.scala 47:18]
  wire [4:0] tail_push_tail_data; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_4_en; // @[ListBuffer.scala 47:18]
  wire [6:0] tail_MPORT_4_addr; // @[ListBuffer.scala 47:18]
  wire [4:0] tail_MPORT_4_data; // @[ListBuffer.scala 47:18]
  wire [4:0] tail_MPORT_3_data; // @[ListBuffer.scala 47:18]
  wire [6:0] tail_MPORT_3_addr; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_3_mask; // @[ListBuffer.scala 47:18]
  wire  tail_MPORT_3_en; // @[ListBuffer.scala 47:18]
  reg [4:0] next [0:21]; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_5_en; // @[ListBuffer.scala 49:18]
  wire [4:0] next_MPORT_5_addr; // @[ListBuffer.scala 49:18]
  wire [4:0] next_MPORT_5_data; // @[ListBuffer.scala 49:18]
  wire [4:0] next_MPORT_1_data; // @[ListBuffer.scala 49:18]
  wire [4:0] next_MPORT_1_addr; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_1_mask; // @[ListBuffer.scala 49:18]
  wire  next_MPORT_1_en; // @[ListBuffer.scala 49:18]
  reg  data_prio_0 [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_prio_0_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_prio_0_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_prio_0_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire  data_prio_0_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_prio_0_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_prio_0_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_prio_0_MPORT_en; // @[ListBuffer.scala 50:18]
  reg  data_prio_1 [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_prio_1_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_prio_1_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_prio_1_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire  data_prio_1_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_prio_1_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_prio_1_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_prio_1_MPORT_en; // @[ListBuffer.scala 50:18]
  reg  data_prio_2 [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_prio_2_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_prio_2_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_prio_2_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire  data_prio_2_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_prio_2_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_prio_2_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_prio_2_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [2:0] data_opcode [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_opcode_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_opcode_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [2:0] data_opcode_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [2:0] data_opcode_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_opcode_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_opcode_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_opcode_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [2:0] data_param [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_param_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_param_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [2:0] data_param_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [2:0] data_param_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_param_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_param_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_param_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [2:0] data_size [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_size_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_size_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [2:0] data_size_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [2:0] data_size_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_size_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_size_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_size_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [2:0] data_source [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_source_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_source_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [2:0] data_source_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [2:0] data_source_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_source_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_source_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_source_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [25:0] data_tag [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_tag_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_tag_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [25:0] data_tag_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [25:0] data_tag_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_tag_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_tag_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_tag_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [3:0] data_offset [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_offset_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_offset_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [3:0] data_offset_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [3:0] data_offset_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_offset_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_offset_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_offset_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [5:0] data_put [0:21]; // @[ListBuffer.scala 50:18]
  wire  data_put_io_data_MPORT_en; // @[ListBuffer.scala 50:18]
  wire [4:0] data_put_io_data_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire [5:0] data_put_io_data_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [5:0] data_put_MPORT_data; // @[ListBuffer.scala 50:18]
  wire [4:0] data_put_MPORT_addr; // @[ListBuffer.scala 50:18]
  wire  data_put_MPORT_mask; // @[ListBuffer.scala 50:18]
  wire  data_put_MPORT_en; // @[ListBuffer.scala 50:18]
  reg [65:0] valid; // @[ListBuffer.scala 45:22]
  reg [21:0] used; // @[ListBuffer.scala 48:22]
  wire [21:0] _freeOH_T = ~used; // @[ListBuffer.scala 52:25]
  wire [22:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala 244:48]
  wire [21:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_1[21:0]; // @[package.scala 244:43]
  wire [23:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala 244:48]
  wire [21:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_4[21:0]; // @[package.scala 244:43]
  wire [25:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala 244:48]
  wire [21:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_7[21:0]; // @[package.scala 244:43]
  wire [29:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala 244:48]
  wire [21:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_10[21:0]; // @[package.scala 244:43]
  wire [37:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala 244:48]
  wire [21:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_13[21:0]; // @[package.scala 244:43]
  wire [22:0] _freeOH_T_17 = {_freeOH_T_15, 1'h0}; // @[ListBuffer.scala 52:32]
  wire [22:0] _freeOH_T_18 = ~_freeOH_T_17; // @[ListBuffer.scala 52:16]
  wire [22:0] _GEN_49 = {{1'd0}, _freeOH_T}; // @[ListBuffer.scala 52:38]
  wire [22:0] freeOH = _freeOH_T_18 & _GEN_49; // @[ListBuffer.scala 52:38]
  wire [6:0] freeIdx_hi = freeOH[22:16]; // @[OneHot.scala 30:18]
  wire [15:0] freeIdx_lo = freeOH[15:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T = |freeIdx_hi; // @[OneHot.scala 32:14]
  wire [15:0] _GEN_50 = {{9'd0}, freeIdx_hi}; // @[OneHot.scala 32:28]
  wire [15:0] _freeIdx_T_1 = _GEN_50 | freeIdx_lo; // @[OneHot.scala 32:28]
  wire [7:0] freeIdx_hi_1 = _freeIdx_T_1[15:8]; // @[OneHot.scala 30:18]
  wire [7:0] freeIdx_lo_1 = _freeIdx_T_1[7:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala 32:14]
  wire [7:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala 32:28]
  wire [3:0] freeIdx_hi_2 = _freeIdx_T_3[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] freeIdx_lo_2 = _freeIdx_T_3[3:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala 32:14]
  wire [3:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala 32:28]
  wire [1:0] freeIdx_hi_3 = _freeIdx_T_5[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] freeIdx_lo_3 = _freeIdx_T_5[1:0]; // @[OneHot.scala 31:18]
  wire  _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala 32:14]
  wire [1:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala 32:28]
  wire [3:0] _freeIdx_T_11 = {_freeIdx_T_2,_freeIdx_T_4,_freeIdx_T_6,_freeIdx_T_7[1]}; // @[Cat.scala 33:92]
  wire [4:0] freeIdx = {_freeIdx_T,_freeIdx_T_2,_freeIdx_T_4,_freeIdx_T_6,_freeIdx_T_7[1]}; // @[Cat.scala 33:92]
  wire [65:0] _push_valid_T = valid >> io_push_bits_index; // @[ListBuffer.scala 61:25]
  wire  push_valid = _push_valid_T[0]; // @[ListBuffer.scala 61:25]
  wire  _T = io_push_ready & io_push_valid; // @[Decoupled.scala 52:35]
  wire [127:0] _valid_set_T = 128'h1 << io_push_bits_index; // @[OneHot.scala 64:12]
  wire  _GEN_7 = push_valid ? 1'h0 : 1'h1; // @[ListBuffer.scala 46:18 68:23]
  wire [65:0] valid_set = _T ? _valid_set_T[65:0] : 66'h0; // @[ListBuffer.scala 64:25 65:15]
  wire [22:0] _GEN_11 = _T ? freeOH : 23'h0; // @[ListBuffer.scala 64:25 66:14]
  wire  _GEN_29 = _T & push_valid; // @[ListBuffer.scala 49:18 64:25]
  wire [65:0] _T_2 = io_valid >> io_pop_bits; // @[ListBuffer.scala 84:39]
  wire [4:0] used_clr_shiftAmount = head_pop_head_data; // @[OneHot.scala 63:49]
  wire [31:0] _used_clr_T = 32'h1 << used_clr_shiftAmount; // @[OneHot.scala 64:12]
  wire [127:0] _valid_clr_T = 128'h1 << io_pop_bits; // @[OneHot.scala 64:12]
  wire [65:0] _GEN_38 = head_pop_head_data == tail_MPORT_4_data ? _valid_clr_T[65:0] : 66'h0; // @[ListBuffer.scala 88:48 89:17]
  wire  _T_12 = _GEN_29 & tail_push_tail_data == head_pop_head_data; // @[ListBuffer.scala 91:62]
  wire [21:0] used_clr = io_pop_valid ? _used_clr_T[21:0] : 22'h0; // @[ListBuffer.scala 86:24 87:14]
  wire [65:0] valid_clr = io_pop_valid ? _GEN_38 : 66'h0; // @[ListBuffer.scala 86:24]
  wire [21:0] _used_T = ~used_clr; // @[ListBuffer.scala 96:23]
  wire [21:0] _used_T_1 = used & _used_T; // @[ListBuffer.scala 96:21]
  wire [21:0] used_set = _GEN_11[21:0];
  wire [21:0] _used_T_2 = _used_T_1 | used_set; // @[ListBuffer.scala 96:35]
  wire [65:0] _valid_T = ~valid_clr; // @[ListBuffer.scala 97:23]
  wire [65:0] _valid_T_1 = valid & _valid_T; // @[ListBuffer.scala 97:21]
  wire [65:0] _valid_T_2 = _valid_T_1 | valid_set; // @[ListBuffer.scala 97:35]
  assign head_pop_head_en = 1'h1;
  assign head_pop_head_addr = io_pop_bits;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign head_pop_head_data = head[head_pop_head_addr]; // @[ListBuffer.scala 46:18]
  `else
  assign head_pop_head_data = head_pop_head_addr >= 7'h42 ? _RAND_1[4:0] : head[head_pop_head_addr]; // @[ListBuffer.scala 46:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign head_MPORT_2_data = {_freeIdx_T,_freeIdx_T_11};
  assign head_MPORT_2_addr = io_push_bits_index;
  assign head_MPORT_2_mask = 1'h1;
  assign head_MPORT_2_en = _T & _GEN_7;
  assign head_MPORT_6_data = _T_12 ? freeIdx : next_MPORT_5_data;
  assign head_MPORT_6_addr = io_pop_bits;
  assign head_MPORT_6_mask = 1'h1;
  assign head_MPORT_6_en = io_pop_valid;
  assign tail_push_tail_en = 1'h1;
  assign tail_push_tail_addr = io_push_bits_index;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tail_push_tail_data = tail[tail_push_tail_addr]; // @[ListBuffer.scala 47:18]
  `else
  assign tail_push_tail_data = tail_push_tail_addr >= 7'h42 ? _RAND_3[4:0] : tail[tail_push_tail_addr]; // @[ListBuffer.scala 47:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tail_MPORT_4_en = io_pop_valid;
  assign tail_MPORT_4_addr = io_pop_bits;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tail_MPORT_4_data = tail[tail_MPORT_4_addr]; // @[ListBuffer.scala 47:18]
  `else
  assign tail_MPORT_4_data = tail_MPORT_4_addr >= 7'h42 ? _RAND_4[4:0] : tail[tail_MPORT_4_addr]; // @[ListBuffer.scala 47:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tail_MPORT_3_data = {_freeIdx_T,_freeIdx_T_11};
  assign tail_MPORT_3_addr = io_push_bits_index;
  assign tail_MPORT_3_mask = 1'h1;
  assign tail_MPORT_3_en = io_push_ready & io_push_valid;
  assign next_MPORT_5_en = io_pop_valid;
  assign next_MPORT_5_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign next_MPORT_5_data = next[next_MPORT_5_addr]; // @[ListBuffer.scala 49:18]
  `else
  assign next_MPORT_5_data = next_MPORT_5_addr >= 5'h16 ? _RAND_6[4:0] : next[next_MPORT_5_addr]; // @[ListBuffer.scala 49:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign next_MPORT_1_data = {_freeIdx_T,_freeIdx_T_11};
  assign next_MPORT_1_addr = tail_push_tail_data;
  assign next_MPORT_1_mask = 1'h1;
  assign next_MPORT_1_en = _T & push_valid;
  assign data_prio_0_io_data_MPORT_en = 1'h1;
  assign data_prio_0_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_prio_0_io_data_MPORT_data = data_prio_0[data_prio_0_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_prio_0_io_data_MPORT_data = data_prio_0_io_data_MPORT_addr >= 5'h16 ? _RAND_8[0:0] :
    data_prio_0[data_prio_0_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_prio_0_MPORT_data = io_push_bits_data_prio_0;
  assign data_prio_0_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_prio_0_MPORT_mask = 1'h1;
  assign data_prio_0_MPORT_en = io_push_ready & io_push_valid;
  assign data_prio_1_io_data_MPORT_en = 1'h1;
  assign data_prio_1_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_prio_1_io_data_MPORT_data = data_prio_1[data_prio_1_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_prio_1_io_data_MPORT_data = data_prio_1_io_data_MPORT_addr >= 5'h16 ? _RAND_10[0:0] :
    data_prio_1[data_prio_1_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_prio_1_MPORT_data = 1'h0;
  assign data_prio_1_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_prio_1_MPORT_mask = 1'h1;
  assign data_prio_1_MPORT_en = io_push_ready & io_push_valid;
  assign data_prio_2_io_data_MPORT_en = 1'h1;
  assign data_prio_2_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_prio_2_io_data_MPORT_data = data_prio_2[data_prio_2_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_prio_2_io_data_MPORT_data = data_prio_2_io_data_MPORT_addr >= 5'h16 ? _RAND_12[0:0] :
    data_prio_2[data_prio_2_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_prio_2_MPORT_data = io_push_bits_data_prio_2;
  assign data_prio_2_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_prio_2_MPORT_mask = 1'h1;
  assign data_prio_2_MPORT_en = io_push_ready & io_push_valid;
  assign data_opcode_io_data_MPORT_en = 1'h1;
  assign data_opcode_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_opcode_io_data_MPORT_data = data_opcode[data_opcode_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_opcode_io_data_MPORT_data = data_opcode_io_data_MPORT_addr >= 5'h16 ? _RAND_14[2:0] :
    data_opcode[data_opcode_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_opcode_MPORT_data = io_push_bits_data_opcode;
  assign data_opcode_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_opcode_MPORT_mask = 1'h1;
  assign data_opcode_MPORT_en = io_push_ready & io_push_valid;
  assign data_param_io_data_MPORT_en = 1'h1;
  assign data_param_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_param_io_data_MPORT_data = data_param[data_param_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_param_io_data_MPORT_data = data_param_io_data_MPORT_addr >= 5'h16 ? _RAND_16[2:0] :
    data_param[data_param_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_param_MPORT_data = io_push_bits_data_param;
  assign data_param_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_param_MPORT_mask = 1'h1;
  assign data_param_MPORT_en = io_push_ready & io_push_valid;
  assign data_size_io_data_MPORT_en = 1'h1;
  assign data_size_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_size_io_data_MPORT_data = data_size[data_size_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_size_io_data_MPORT_data = data_size_io_data_MPORT_addr >= 5'h16 ? _RAND_18[2:0] :
    data_size[data_size_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_size_MPORT_data = io_push_bits_data_size;
  assign data_size_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_size_MPORT_mask = 1'h1;
  assign data_size_MPORT_en = io_push_ready & io_push_valid;
  assign data_source_io_data_MPORT_en = 1'h1;
  assign data_source_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_source_io_data_MPORT_data = data_source[data_source_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_source_io_data_MPORT_data = data_source_io_data_MPORT_addr >= 5'h16 ? _RAND_20[2:0] :
    data_source[data_source_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_source_MPORT_data = io_push_bits_data_source;
  assign data_source_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_source_MPORT_mask = 1'h1;
  assign data_source_MPORT_en = io_push_ready & io_push_valid;
  assign data_tag_io_data_MPORT_en = 1'h1;
  assign data_tag_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_tag_io_data_MPORT_data = data_tag[data_tag_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_tag_io_data_MPORT_data = data_tag_io_data_MPORT_addr >= 5'h16 ? _RAND_22[25:0] :
    data_tag[data_tag_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_tag_MPORT_data = io_push_bits_data_tag;
  assign data_tag_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_tag_MPORT_mask = 1'h1;
  assign data_tag_MPORT_en = io_push_ready & io_push_valid;
  assign data_offset_io_data_MPORT_en = 1'h1;
  assign data_offset_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_offset_io_data_MPORT_data = data_offset[data_offset_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_offset_io_data_MPORT_data = data_offset_io_data_MPORT_addr >= 5'h16 ? _RAND_24[3:0] :
    data_offset[data_offset_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_offset_MPORT_data = io_push_bits_data_offset;
  assign data_offset_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_offset_MPORT_mask = 1'h1;
  assign data_offset_MPORT_en = io_push_ready & io_push_valid;
  assign data_put_io_data_MPORT_en = 1'h1;
  assign data_put_io_data_MPORT_addr = head_pop_head_data;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign data_put_io_data_MPORT_data = data_put[data_put_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `else
  assign data_put_io_data_MPORT_data = data_put_io_data_MPORT_addr >= 5'h16 ? _RAND_26[5:0] :
    data_put[data_put_io_data_MPORT_addr]; // @[ListBuffer.scala 50:18]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign data_put_MPORT_data = io_push_bits_data_put;
  assign data_put_MPORT_addr = {_freeIdx_T,_freeIdx_T_11};
  assign data_put_MPORT_mask = 1'h1;
  assign data_put_MPORT_en = io_push_ready & io_push_valid;
  assign io_push_ready = ~(&used); // @[ListBuffer.scala 63:20]
  assign io_valid = valid; // @[ListBuffer.scala 81:12]
  assign io_data_prio_0 = data_prio_0_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_prio_1 = data_prio_1_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_prio_2 = data_prio_2_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_opcode = data_opcode_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_param = data_param_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_size = data_size_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_source = data_source_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_tag = data_tag_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_offset = data_offset_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  assign io_data_put = data_put_io_data_MPORT_data; // @[ListBuffer.scala 80:11]
  always @(posedge clock) begin
    if (head_MPORT_2_en & head_MPORT_2_mask) begin
      head[head_MPORT_2_addr] <= head_MPORT_2_data; // @[ListBuffer.scala 46:18]
    end
    if (head_MPORT_6_en & head_MPORT_6_mask) begin
      head[head_MPORT_6_addr] <= head_MPORT_6_data; // @[ListBuffer.scala 46:18]
    end
    if (tail_MPORT_3_en & tail_MPORT_3_mask) begin
      tail[tail_MPORT_3_addr] <= tail_MPORT_3_data; // @[ListBuffer.scala 47:18]
    end
    if (next_MPORT_1_en & next_MPORT_1_mask) begin
      next[next_MPORT_1_addr] <= next_MPORT_1_data; // @[ListBuffer.scala 49:18]
    end
    if (data_prio_0_MPORT_en & data_prio_0_MPORT_mask) begin
      data_prio_0[data_prio_0_MPORT_addr] <= data_prio_0_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_prio_1_MPORT_en & data_prio_1_MPORT_mask) begin
      data_prio_1[data_prio_1_MPORT_addr] <= data_prio_1_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_prio_2_MPORT_en & data_prio_2_MPORT_mask) begin
      data_prio_2[data_prio_2_MPORT_addr] <= data_prio_2_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_opcode_MPORT_en & data_opcode_MPORT_mask) begin
      data_opcode[data_opcode_MPORT_addr] <= data_opcode_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_param_MPORT_en & data_param_MPORT_mask) begin
      data_param[data_param_MPORT_addr] <= data_param_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_size_MPORT_en & data_size_MPORT_mask) begin
      data_size[data_size_MPORT_addr] <= data_size_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_source_MPORT_en & data_source_MPORT_mask) begin
      data_source[data_source_MPORT_addr] <= data_source_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_tag_MPORT_en & data_tag_MPORT_mask) begin
      data_tag[data_tag_MPORT_addr] <= data_tag_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_offset_MPORT_en & data_offset_MPORT_mask) begin
      data_offset[data_offset_MPORT_addr] <= data_offset_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (data_put_MPORT_en & data_put_MPORT_mask) begin
      data_put[data_put_MPORT_addr] <= data_put_MPORT_data; // @[ListBuffer.scala 50:18]
    end
    if (reset) begin // @[ListBuffer.scala 45:22]
      valid <= 66'h0; // @[ListBuffer.scala 45:22]
    end else begin
      valid <= _valid_T_2;
    end
    if (reset) begin // @[ListBuffer.scala 48:22]
      used <= 22'h0; // @[ListBuffer.scala 48:22]
    end else begin
      used <= _used_T_2;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_pop_valid | _T_2[0])) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ListBuffer.scala:84 assert (!io.pop.fire() || (io.valid)(io.pop.bits))\n"); // @[ListBuffer.scala 84:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_pop_valid | _T_2[0]) & ~reset) begin
          $fatal; // @[ListBuffer.scala 84:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  _RAND_1 = {1{`RANDOM}};
  _RAND_3 = {1{`RANDOM}};
  _RAND_4 = {1{`RANDOM}};
  _RAND_6 = {1{`RANDOM}};
  _RAND_8 = {1{`RANDOM}};
  _RAND_10 = {1{`RANDOM}};
  _RAND_12 = {1{`RANDOM}};
  _RAND_14 = {1{`RANDOM}};
  _RAND_16 = {1{`RANDOM}};
  _RAND_18 = {1{`RANDOM}};
  _RAND_20 = {1{`RANDOM}};
  _RAND_22 = {1{`RANDOM}};
  _RAND_24 = {1{`RANDOM}};
  _RAND_26 = {1{`RANDOM}};
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 66; initvar = initvar+1)
    head[initvar] = _RAND_0[4:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 66; initvar = initvar+1)
    tail[initvar] = _RAND_2[4:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    next[initvar] = _RAND_5[4:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_prio_0[initvar] = _RAND_7[0:0];
  _RAND_9 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_prio_1[initvar] = _RAND_9[0:0];
  _RAND_11 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_prio_2[initvar] = _RAND_11[0:0];
  _RAND_13 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_opcode[initvar] = _RAND_13[2:0];
  _RAND_15 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_param[initvar] = _RAND_15[2:0];
  _RAND_17 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_size[initvar] = _RAND_17[2:0];
  _RAND_19 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_source[initvar] = _RAND_19[2:0];
  _RAND_21 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_tag[initvar] = _RAND_21[25:0];
  _RAND_23 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_offset[initvar] = _RAND_23[3:0];
  _RAND_25 = {1{`RANDOM}};
  for (initvar = 0; initvar < 22; initvar = initvar+1)
    data_put[initvar] = _RAND_25[5:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_27 = {3{`RANDOM}};
  valid = _RAND_27[65:0];
  _RAND_28 = {1{`RANDOM}};
  used = _RAND_28[21:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MSHR(
  input         clock,
  input         reset,
  input         io_allocate_valid,
  input         io_allocate_bits_prio_0,
  input         io_allocate_bits_prio_1,
  input         io_allocate_bits_prio_2,
  input  [2:0]  io_allocate_bits_opcode,
  input  [2:0]  io_allocate_bits_param,
  input  [2:0]  io_allocate_bits_size,
  input  [2:0]  io_allocate_bits_source,
  input  [25:0] io_allocate_bits_tag,
  input  [3:0]  io_allocate_bits_offset,
  input  [5:0]  io_allocate_bits_put,
  input  [1:0]  io_allocate_bits_set,
  input         io_allocate_bits_repeat,
  input         io_directory_valid,
  input         io_directory_bits_dirty,
  input  [1:0]  io_directory_bits_state,
  input         io_directory_bits_clients,
  input  [25:0] io_directory_bits_tag,
  input         io_directory_bits_hit,
  input         io_directory_bits_way,
  output        io_status_valid,
  output [1:0]  io_status_bits_set,
  output [25:0] io_status_bits_tag,
  output        io_status_bits_way,
  output        io_status_bits_blockB,
  output        io_status_bits_nestB,
  output        io_status_bits_blockC,
  output        io_status_bits_nestC,
  input         io_schedule_ready,
  output        io_schedule_valid,
  output        io_schedule_bits_a_valid,
  output [25:0] io_schedule_bits_a_bits_tag,
  output [1:0]  io_schedule_bits_a_bits_set,
  output [2:0]  io_schedule_bits_a_bits_param,
  output        io_schedule_bits_a_bits_block,
  output        io_schedule_bits_b_valid,
  output [2:0]  io_schedule_bits_b_bits_param,
  output [25:0] io_schedule_bits_b_bits_tag,
  output [1:0]  io_schedule_bits_b_bits_set,
  output        io_schedule_bits_b_bits_clients,
  output        io_schedule_bits_c_valid,
  output [2:0]  io_schedule_bits_c_bits_opcode,
  output [2:0]  io_schedule_bits_c_bits_param,
  output [25:0] io_schedule_bits_c_bits_tag,
  output [1:0]  io_schedule_bits_c_bits_set,
  output        io_schedule_bits_c_bits_way,
  output        io_schedule_bits_c_bits_dirty,
  output        io_schedule_bits_d_valid,
  output        io_schedule_bits_d_bits_prio_0,
  output        io_schedule_bits_d_bits_prio_2,
  output [2:0]  io_schedule_bits_d_bits_opcode,
  output [2:0]  io_schedule_bits_d_bits_param,
  output [2:0]  io_schedule_bits_d_bits_size,
  output [2:0]  io_schedule_bits_d_bits_source,
  output [3:0]  io_schedule_bits_d_bits_offset,
  output [5:0]  io_schedule_bits_d_bits_put,
  output [1:0]  io_schedule_bits_d_bits_set,
  output        io_schedule_bits_d_bits_way,
  output        io_schedule_bits_d_bits_bad,
  output        io_schedule_bits_e_valid,
  output [2:0]  io_schedule_bits_e_bits_sink,
  output        io_schedule_bits_x_valid,
  output        io_schedule_bits_dir_valid,
  output [1:0]  io_schedule_bits_dir_bits_set,
  output        io_schedule_bits_dir_bits_way,
  output        io_schedule_bits_dir_bits_data_dirty,
  output [1:0]  io_schedule_bits_dir_bits_data_state,
  output        io_schedule_bits_dir_bits_data_clients,
  output [25:0] io_schedule_bits_dir_bits_data_tag,
  output        io_schedule_bits_reload,
  input         io_sinkc_valid,
  input         io_sinkc_bits_last,
  input  [25:0] io_sinkc_bits_tag,
  input  [2:0]  io_sinkc_bits_source,
  input  [2:0]  io_sinkc_bits_param,
  input         io_sinkc_bits_data,
  input         io_sinkd_valid,
  input         io_sinkd_bits_last,
  input  [2:0]  io_sinkd_bits_opcode,
  input  [2:0]  io_sinkd_bits_param,
  input  [2:0]  io_sinkd_bits_sink,
  input         io_sinkd_bits_denied,
  input         io_sinke_valid,
  input  [1:0]  io_nestedwb_set,
  input  [25:0] io_nestedwb_tag,
  input         io_nestedwb_b_toN,
  input         io_nestedwb_b_toB,
  input         io_nestedwb_b_clr_dirty,
  input         io_nestedwb_c_set_dirty
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
`endif // RANDOMIZE_REG_INIT
  reg  request_valid; // @[MSHR.scala 94:30]
  reg  request_prio_0; // @[MSHR.scala 95:20]
  reg  request_prio_1; // @[MSHR.scala 95:20]
  reg  request_prio_2; // @[MSHR.scala 95:20]
  reg [2:0] request_opcode; // @[MSHR.scala 95:20]
  reg [2:0] request_param; // @[MSHR.scala 95:20]
  reg [2:0] request_size; // @[MSHR.scala 95:20]
  reg [2:0] request_source; // @[MSHR.scala 95:20]
  reg [25:0] request_tag; // @[MSHR.scala 95:20]
  reg [3:0] request_offset; // @[MSHR.scala 95:20]
  reg [5:0] request_put; // @[MSHR.scala 95:20]
  reg [1:0] request_set; // @[MSHR.scala 95:20]
  reg  meta_valid; // @[MSHR.scala 96:27]
  reg  meta_dirty; // @[MSHR.scala 97:17]
  reg [1:0] meta_state; // @[MSHR.scala 97:17]
  reg  meta_clients; // @[MSHR.scala 97:17]
  reg [25:0] meta_tag; // @[MSHR.scala 97:17]
  reg  meta_hit; // @[MSHR.scala 97:17]
  reg  meta_way; // @[MSHR.scala 97:17]
  wire  _T = meta_state == 2'h0; // @[MSHR.scala 101:22]
  wire  _T_1 = |meta_clients; // @[MSHR.scala 102:29]
  wire  _T_2 = ~(|meta_clients); // @[MSHR.scala 102:15]
  wire  _T_4 = ~reset; // @[MSHR.scala 102:14]
  wire  _T_6 = ~meta_dirty; // @[MSHR.scala 103:15]
  wire  _T_9 = ~(~meta_dirty); // @[MSHR.scala 103:14]
  wire  _T_10 = meta_state == 2'h1; // @[MSHR.scala 105:22]
  wire  _T_15 = meta_state == 2'h2; // @[MSHR.scala 108:22]
  reg  s_rprobe; // @[MSHR.scala 118:33]
  reg  w_rprobeackfirst; // @[MSHR.scala 119:33]
  reg  w_rprobeacklast; // @[MSHR.scala 120:33]
  reg  s_release; // @[MSHR.scala 121:33]
  reg  w_releaseack; // @[MSHR.scala 122:33]
  reg  s_pprobe; // @[MSHR.scala 123:33]
  reg  s_acquire; // @[MSHR.scala 124:33]
  reg  w_grantfirst; // @[MSHR.scala 126:33]
  reg  w_grantlast; // @[MSHR.scala 127:33]
  reg  w_grant; // @[MSHR.scala 128:33]
  reg  w_pprobeackfirst; // @[MSHR.scala 129:33]
  reg  w_pprobeacklast; // @[MSHR.scala 130:33]
  reg  w_pprobeack; // @[MSHR.scala 131:33]
  reg  s_grantack; // @[MSHR.scala 133:33]
  reg  s_execute; // @[MSHR.scala 134:33]
  reg  w_grantack; // @[MSHR.scala 135:33]
  reg  s_writeback; // @[MSHR.scala 136:33]
  reg [2:0] sink; // @[MSHR.scala 144:17]
  reg  gotT; // @[MSHR.scala 145:17]
  reg  bad_grant; // @[MSHR.scala 146:22]
  reg  probes_done; // @[MSHR.scala 147:24]
  reg  probes_toN; // @[MSHR.scala 148:23]
  wire  _T_28 = meta_state != 2'h0; // @[MSHR.scala 152:34]
  wire  _T_30 = io_nestedwb_set == request_set; // @[MSHR.scala 153:25]
  wire  _T_31 = meta_valid & meta_state != 2'h0 & _T_30; // @[MSHR.scala 152:46]
  wire  _GEN_0 = io_nestedwb_b_clr_dirty ? 1'h0 : meta_dirty; // @[MSHR.scala 154:{36,49} 97:17]
  wire  _GEN_1 = io_nestedwb_c_set_dirty | _GEN_0; // @[MSHR.scala 155:{36,49}]
  wire  _GEN_4 = _T_31 & io_nestedwb_tag == meta_tag ? _GEN_1 : meta_dirty; // @[MSHR.scala 153:74 97:17]
  wire  _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala 165:28]
  wire  _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala 165:103]
  wire  no_wait = w_rprobeacklast & w_releaseack & w_grantlast & w_pprobeacklast & w_grantack; // @[MSHR.scala 180:83]
  wire  _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala 182:31]
  wire  _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala 183:32]
  wire  _io_schedule_bits_c_valid_T_1 = ~s_release & w_rprobeackfirst; // @[MSHR.scala 183:43]
  wire  _io_schedule_bits_dir_valid_T_3 = ~s_writeback & no_wait; // @[MSHR.scala 187:83]
  wire  _io_schedule_valid_T_2 = io_schedule_bits_a_valid | io_schedule_bits_b_valid | io_schedule_bits_c_valid |
    io_schedule_bits_d_valid; // @[MSHR.scala 189:105]
  wire  _GEN_7 = w_rprobeackfirst | s_release; // @[MSHR.scala 121:33 196:{35,50}]
  wire  _GEN_8 = s_release & s_pprobe | s_acquire; // @[MSHR.scala 124:33 198:{35,50}]
  wire  _GEN_11 = w_grantfirst | s_grantack; // @[MSHR.scala 133:33 201:{35,50}]
  wire  _GEN_12 = w_pprobeack & w_grant | s_execute; // @[MSHR.scala 134:33 202:{35,50}]
  wire  _GEN_13 = no_wait | s_writeback; // @[MSHR.scala 136:33 203:{35,50}]
  wire  _GEN_14 = no_wait ? 1'h0 : request_valid; // @[MSHR.scala 205:20 206:21 94:30]
  wire  _GEN_15 = no_wait ? 1'h0 : meta_valid; // @[MSHR.scala 205:20 207:18 96:27]
  wire  _GEN_16 = io_schedule_ready | s_rprobe; // @[MSHR.scala 194:28 118:33 195:50]
  wire  _GEN_17 = io_schedule_ready ? _GEN_7 : s_release; // @[MSHR.scala 194:28 121:33]
  wire  _GEN_18 = io_schedule_ready | s_pprobe; // @[MSHR.scala 194:28 123:33 197:50]
  wire  _GEN_19 = io_schedule_ready ? _GEN_8 : s_acquire; // @[MSHR.scala 194:28 124:33]
  wire  _GEN_22 = io_schedule_ready ? _GEN_11 : s_grantack; // @[MSHR.scala 194:28 133:33]
  wire  _GEN_23 = io_schedule_ready ? _GEN_12 : s_execute; // @[MSHR.scala 194:28 134:33]
  wire  _GEN_24 = io_schedule_ready ? _GEN_13 : s_writeback; // @[MSHR.scala 194:28 136:33]
  wire  _GEN_25 = io_schedule_ready ? _GEN_14 : request_valid; // @[MSHR.scala 194:28 94:30]
  wire  _GEN_26 = io_schedule_ready ? _GEN_15 : meta_valid; // @[MSHR.scala 194:28 96:27]
  wire  req_clientBit = request_source == 3'h3; // @[Parameters.scala 46:9]
  wire  _req_needT_T_1 = ~request_opcode[2]; // @[Parameters.scala 265:5]
  wire  _req_needT_T_3 = request_param == 3'h1; // @[Parameters.scala 266:42]
  wire  _req_needT_T_4 = request_opcode == 3'h5 & request_param == 3'h1; // @[Parameters.scala 266:33]
  wire  _req_needT_T_5 = ~request_opcode[2] | _req_needT_T_4; // @[Parameters.scala 265:16]
  wire  _req_needT_T_7 = request_opcode == 3'h7; // @[Parameters.scala 267:52]
  wire  _req_needT_T_8 = request_opcode == 3'h6 | request_opcode == 3'h7; // @[Parameters.scala 267:42]
  wire  _req_needT_T_10 = (request_opcode == 3'h6 | request_opcode == 3'h7) & request_param != 3'h0; // @[Parameters.scala 267:80]
  wire  req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala 266:70]
  wire  _req_promoteT_T_2 = meta_hit ? _T_2 & meta_state == 2'h3 : gotT; // @[MSHR.scala 218:40]
  wire  req_promoteT = _req_needT_T_8 & _req_promoteT_T_2; // @[MSHR.scala 218:34]
  wire [1:0] _final_meta_writeback_state_T_3 = request_param != 3'h3 & _T_15 ? 2'h3 : meta_state; // @[MSHR.scala 222:40]
  wire  _final_meta_writeback_clients_T_4 = _req_needT_T_3 | request_param == 3'h2 | request_param == 3'h5; // @[Parameters.scala 278:66]
  wire  _final_meta_writeback_clients_T_9 = meta_clients & ~probes_toN; // @[MSHR.scala 229:52]
  wire  _final_meta_writeback_dirty_T_5 = meta_hit & meta_dirty | _req_needT_T_1; // @[MSHR.scala 233:60]
  wire [1:0] _final_meta_writeback_state_T_4 = _req_needT_T_8 ? 2'h2 : 2'h3; // @[MSHR.scala 235:40]
  wire  _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala 236:41]
  wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_4 : 2'h1; // @[MSHR.scala 236:55]
  wire [1:0] _final_meta_writeback_state_T_9 = _T_2 & _req_needT_T_8 ? 2'h2 : 2'h3; // @[MSHR.scala 241:55]
  wire  _final_meta_writeback_state_T_10 = 2'h1 == meta_state; // @[Mux.scala 81:61]
  wire  _final_meta_writeback_state_T_12 = 2'h2 == meta_state; // @[Mux.scala 81:61]
  wire [1:0] _final_meta_writeback_state_T_13 = 2'h2 == meta_state ? 2'h3 : 2'h1; // @[Mux.scala 81:58]
  wire  _final_meta_writeback_state_T_14 = 2'h3 == meta_state; // @[Mux.scala 81:61]
  wire [1:0] _final_meta_writeback_state_T_15 = 2'h3 == meta_state ? _final_meta_writeback_state_T_9 :
    _final_meta_writeback_state_T_13; // @[Mux.scala 81:58]
  wire [1:0] _final_meta_writeback_state_T_16 = ~meta_hit ? _final_meta_writeback_state_T_7 :
    _final_meta_writeback_state_T_15; // @[MSHR.scala 236:40]
  wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 :
    _final_meta_writeback_state_T_16; // @[MSHR.scala 234:38]
  wire  _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_9; // @[MSHR.scala 242:40]
  wire  _final_meta_writeback_clients_T_13 = _req_needT_T_8 & req_clientBit; // @[MSHR.scala 243:40]
  wire  _final_meta_writeback_clients_T_14 = meta_hit & _final_meta_writeback_clients_T_9 |
    _final_meta_writeback_clients_T_13; // @[MSHR.scala 242:88]
  wire  _GEN_35 = request_prio_2 ? meta_dirty | request_opcode[0] : _final_meta_writeback_dirty_T_5; // @[MSHR.scala 220:54 221:34]
  wire [1:0] _GEN_36 = request_prio_2 ? _final_meta_writeback_state_T_3 : _final_meta_writeback_state_T_17; // @[MSHR.scala 220:54 222:34]
  wire  _GEN_37 = request_prio_2 ? meta_clients & ~(_final_meta_writeback_clients_T_4 & req_clientBit) :
    _final_meta_writeback_clients_T_14; // @[MSHR.scala 220:54 223:34]
  wire [25:0] final_meta_writeback_tag = request_prio_2 ? meta_tag : request_tag; // @[MSHR.scala 220:54]
  wire [1:0] _GEN_42 = meta_hit ? 2'h1 : 2'h0; // @[MSHR.scala 249:21 254:36 260:36]
  wire  final_meta_writeback_hit = bad_grant ? meta_hit : 1'h1; // @[MSHR.scala 248:20]
  wire  final_meta_writeback_dirty = bad_grant ? 1'h0 : _GEN_35; // @[MSHR.scala 248:20]
  wire [1:0] final_meta_writeback_state = bad_grant ? _GEN_42 : _GEN_36; // @[MSHR.scala 248:20]
  wire  final_meta_writeback_clients = bad_grant ? _final_meta_writeback_clients_T_12 : _GEN_37; // @[MSHR.scala 248:20]
  wire  honour_BtoT = meta_hit & |(meta_clients & req_clientBit); // @[MSHR.scala 273:30]
  wire  _excluded_client_T_5 = _req_needT_T_8 | request_opcode == 3'h4; // @[Parameters.scala 275:77]
  wire  excluded_client = meta_hit & request_prio_0 & _excluded_client_T_5 & req_clientBit; // @[MSHR.scala 276:28]
  wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala 279:56]
  wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[MSHR.scala 279:41]
  wire  _io_schedule_bits_a_bits_block_T_4 = ~(request_opcode == 3'h0 | _req_needT_T_7); // @[MSHR.scala 281:38]
  wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[MSHR.scala 283:97]
  wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {{1'd0},
    _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala 283:61]
  wire  _io_schedule_bits_b_bits_clients_T_1 = meta_clients & ~excluded_client; // @[MSHR.scala 286:51]
  wire [1:0] _io_schedule_bits_d_bits_param_T_1 = req_promoteT ? 2'h1 : 2'h0; // @[MSHR.scala 297:53]
  wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala 298:53]
  wire [2:0] _io_schedule_bits_d_bits_param_T_4 = 3'h0 == request_param ? {{1'd0}, _io_schedule_bits_d_bits_param_T_1}
     : 3'h0; // @[Mux.scala 81:58]
  wire [2:0] _io_schedule_bits_d_bits_param_T_6 = 3'h2 == request_param ? {{1'd0}, _io_schedule_bits_d_bits_param_T_2}
     : _io_schedule_bits_d_bits_param_T_4; // @[Mux.scala 81:58]
  wire [2:0] _io_schedule_bits_d_bits_param_T_8 = 3'h1 == request_param ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[Mux.scala 81:58]
  wire  _evict_out_T = _T_1 ? 1'h0 : 1'h1; // @[MSHR.scala 315:32]
  wire [1:0] _evict_out_T_1 = meta_dirty ? 2'h2 : 2'h3; // @[MSHR.scala 316:32]
  wire [2:0] _evict_out_T_2 = meta_dirty ? 3'h4 : 3'h5; // @[MSHR.scala 317:39]
  wire [2:0] _evict_out_T_3 = meta_dirty ? 3'h6 : 3'h7; // @[MSHR.scala 317:76]
  wire [2:0] _evict_out_T_4 = _T_1 ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala 317:32]
  wire [3:0] _GEN_49 = _final_meta_writeback_state_T_14 ? {{1'd0}, _evict_out_T_4} : 4'h8; // @[MSHR.scala 314:26 317:26]
  wire [3:0] _GEN_50 = _final_meta_writeback_state_T_12 ? {{2'd0}, _evict_out_T_1} : _GEN_49; // @[MSHR.scala 314:26 316:26]
  wire [3:0] _GEN_51 = _final_meta_writeback_state_T_10 ? {{3'd0}, _evict_out_T} : _GEN_50; // @[MSHR.scala 314:26 315:26]
  wire [3:0] evict = ~_final_meta_writeback_state_T_5 ? 4'h8 : _GEN_51; // @[MSHR.scala 320:{17,23}]
  wire [3:0] before_ = _final_meta_writeback_state_T_5 ? 4'h8 : _GEN_51; // @[MSHR.scala 320:{17,23}]
  wire  after_c = |final_meta_writeback_clients; // @[MSHR.scala 312:27]
  wire  _after_out_T = after_c ? 1'h0 : 1'h1; // @[MSHR.scala 315:32]
  wire [1:0] _after_out_T_1 = final_meta_writeback_dirty ? 2'h2 : 2'h3; // @[MSHR.scala 316:32]
  wire [2:0] _after_out_T_2 = final_meta_writeback_dirty ? 3'h4 : 3'h5; // @[MSHR.scala 317:39]
  wire [2:0] _after_out_T_3 = final_meta_writeback_dirty ? 3'h6 : 3'h7; // @[MSHR.scala 317:76]
  wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala 317:32]
  wire [3:0] _GEN_59 = 2'h3 == final_meta_writeback_state ? {{1'd0}, _after_out_T_4} : 4'h8; // @[MSHR.scala 314:26 317:26]
  wire [3:0] _GEN_60 = 2'h2 == final_meta_writeback_state ? {{2'd0}, _after_out_T_1} : _GEN_59; // @[MSHR.scala 314:26 316:26]
  wire [3:0] after = 2'h1 == final_meta_writeback_state ? {{3'd0}, _after_out_T} : _GEN_60; // @[MSHR.scala 314:26 315:26]
  wire  _T_58 = _io_schedule_bits_c_valid_T_1 & io_schedule_ready; // @[MSHR.scala 360:42]
  wire  _T_64 = before_ == 4'h1; // @[MSHR.scala 361:13]
  wire  _T_74 = before_ == 4'h0; // @[MSHR.scala 362:13]
  wire  _T_80 = before_ == 4'h7; // @[MSHR.scala 363:13]
  wire  _T_86 = before_ == 4'h5; // @[MSHR.scala 364:13]
  wire  _T_92 = before_ == 4'h4; // @[MSHR.scala 365:13]
  wire  _T_98 = before_ == 4'h6; // @[MSHR.scala 366:13]
  wire  _T_104 = before_ == 4'h3; // @[MSHR.scala 367:13]
  wire  _T_110 = before_ == 4'h2; // @[MSHR.scala 368:13]
  wire  _T_117 = _io_schedule_bits_dir_valid_T_3 & io_schedule_ready; // @[MSHR.scala 371:35]
  wire  _T_118 = before_ == 4'h8; // @[MSHR.scala 372:15]
  wire  _T_119 = after == 4'h1; // @[MSHR.scala 372:15]
  wire  _T_126 = after == 4'h0; // @[MSHR.scala 373:15]
  wire  _T_136 = after == 4'h5; // @[MSHR.scala 375:15]
  wire  _T_143 = after == 4'h4; // @[MSHR.scala 376:15]
  wire  _T_156 = after == 4'h2; // @[MSHR.scala 379:15]
  wire  _T_163 = after == 4'h8; // @[MSHR.scala 381:15]
  wire  _T_177 = after == 4'h7; // @[MSHR.scala 383:15]
  wire  _T_198 = after == 4'h6; // @[MSHR.scala 386:15]
  wire  _T_205 = after == 4'h3; // @[MSHR.scala 387:15]
  wire  probe_bit = io_sinkc_bits_source == 3'h3; // @[Parameters.scala 46:9]
  wire  _last_probe_T = probes_done | probe_bit; // @[MSHR.scala 456:33]
  wire  last_probe = (probes_done | probe_bit) == _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala 456:46]
  wire  probe_toN = io_sinkc_bits_param == 3'h1 | io_sinkc_bits_param == 3'h2 | io_sinkc_bits_param == 3'h5; // @[Parameters.scala 278:66]
  wire  _w_rprobeacklast_T = last_probe & io_sinkc_bits_last; // @[MSHR.scala 468:55]
  wire  _set_pprobeack_T = request_offset == 4'h0; // @[MSHR.scala 472:77]
  wire  set_pprobeack = last_probe & (io_sinkc_bits_last | request_offset == 4'h0); // @[MSHR.scala 472:36]
  wire  _GEN_63 = _T_28 & io_sinkc_bits_tag == meta_tag & io_sinkc_bits_data | _GEN_4; // @[MSHR.scala 477:{104,91}]
  wire  _GEN_67 = io_sinkc_valid ? w_rprobeackfirst | last_probe : w_rprobeackfirst; // @[MSHR.scala 458:49 467:22 119:33]
  wire  _GEN_68 = io_sinkc_valid ? w_rprobeacklast | last_probe & io_sinkc_bits_last : w_rprobeacklast; // @[MSHR.scala 458:49 468:21 120:33]
  wire  _GEN_69 = io_sinkc_valid ? w_pprobeackfirst | last_probe : w_pprobeackfirst; // @[MSHR.scala 458:49 469:22 129:33]
  wire  _GEN_70 = io_sinkc_valid ? w_pprobeacklast | _w_rprobeacklast_T : w_pprobeacklast; // @[MSHR.scala 458:49 470:21 130:33]
  wire  _GEN_71 = io_sinkc_valid ? w_pprobeack | set_pprobeack : w_pprobeack; // @[MSHR.scala 458:49 473:17 131:33]
  wire  _GEN_73 = io_sinkd_bits_opcode == 3'h6 | w_releaseack; // @[MSHR.scala 492:53 493:20 122:33]
  wire  _GEN_75 = io_sinkd_bits_opcode == 3'h4 | io_sinkd_bits_opcode == 3'h5 | w_grantfirst; // @[MSHR.scala 480:81 482:20 126:33]
  wire  _GEN_76 = io_sinkd_bits_opcode == 3'h4 | io_sinkd_bits_opcode == 3'h5 ? io_sinkd_bits_last : w_grantlast; // @[MSHR.scala 480:81 483:19 127:33]
  wire  _GEN_78 = io_sinkd_bits_opcode == 3'h4 | io_sinkd_bits_opcode == 3'h5 ? _set_pprobeack_T | io_sinkd_bits_last :
    w_grant; // @[MSHR.scala 480:81 487:15 128:33]
  wire  _GEN_80 = io_sinkd_bits_opcode == 3'h4 | io_sinkd_bits_opcode == 3'h5 ? w_releaseack : _GEN_73; // @[MSHR.scala 122:33 480:81]
  wire  _GEN_82 = io_sinkd_valid ? _GEN_75 : w_grantfirst; // @[MSHR.scala 479:25 126:33]
  wire  _GEN_83 = io_sinkd_valid ? _GEN_76 : w_grantlast; // @[MSHR.scala 479:25 127:33]
  wire  _GEN_85 = io_sinkd_valid ? _GEN_78 : w_grant; // @[MSHR.scala 479:25 128:33]
  wire  _GEN_87 = io_sinkd_valid ? _GEN_80 : w_releaseack; // @[MSHR.scala 479:25 122:33]
  wire  _GEN_88 = io_sinke_valid | w_grantack; // @[MSHR.scala 496:25 497:16 135:33]
  wire  _new_meta_T = io_allocate_valid & io_allocate_bits_repeat; // @[MSHR.scala 502:40]
  wire  new_meta_dirty = io_allocate_valid & io_allocate_bits_repeat ? final_meta_writeback_dirty :
    io_directory_bits_dirty; // @[MSHR.scala 502:21]
  wire [1:0] new_meta_state = io_allocate_valid & io_allocate_bits_repeat ? final_meta_writeback_state :
    io_directory_bits_state; // @[MSHR.scala 502:21]
  wire  new_meta_clients = io_allocate_valid & io_allocate_bits_repeat ? final_meta_writeback_clients :
    io_directory_bits_clients; // @[MSHR.scala 502:21]
  wire  new_meta_hit = io_allocate_valid & io_allocate_bits_repeat ? final_meta_writeback_hit : io_directory_bits_hit; // @[MSHR.scala 502:21]
  wire  new_request_prio_2 = io_allocate_valid ? io_allocate_bits_prio_2 : request_prio_2; // @[MSHR.scala 503:24]
  wire [2:0] new_request_opcode = io_allocate_valid ? io_allocate_bits_opcode : request_opcode; // @[MSHR.scala 503:24]
  wire [2:0] new_request_param = io_allocate_valid ? io_allocate_bits_param : request_param; // @[MSHR.scala 503:24]
  wire [2:0] new_request_source = io_allocate_valid ? io_allocate_bits_source : request_source; // @[MSHR.scala 503:24]
  wire  _new_needT_T_1 = ~new_request_opcode[2]; // @[Parameters.scala 265:5]
  wire  _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala 266:42]
  wire  _new_needT_T_4 = new_request_opcode == 3'h5 & new_request_param == 3'h1; // @[Parameters.scala 266:33]
  wire  _new_needT_T_5 = ~new_request_opcode[2] | _new_needT_T_4; // @[Parameters.scala 265:16]
  wire  _new_needT_T_8 = new_request_opcode == 3'h6 | new_request_opcode == 3'h7; // @[Parameters.scala 267:42]
  wire  _new_needT_T_10 = (new_request_opcode == 3'h6 | new_request_opcode == 3'h7) & new_request_param != 3'h0; // @[Parameters.scala 267:80]
  wire  new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala 266:70]
  wire  new_clientBit = new_request_source == 3'h3; // @[Parameters.scala 46:9]
  wire  _new_skipProbe_T_4 = _new_needT_T_8 | new_request_opcode == 3'h4; // @[Parameters.scala 275:77]
  wire  new_skipProbe = _new_skipProbe_T_4 & new_clientBit; // @[MSHR.scala 506:26]
  wire  _T_595 = io_schedule_ready & io_schedule_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_94 = io_allocate_valid | _GEN_25; // @[MSHR.scala 529:28 531:19]
  wire  _T_602 = io_directory_valid | _new_meta_T; // @[MSHR.scala 536:28]
  wire  _T_605 = ~new_meta_dirty; // @[MSHR.scala 571:38]
  wire  _GEN_107 = new_request_opcode[0] & ~new_meta_dirty ? 1'h0 : 1'h1; // @[MSHR.scala 571:55 572:21 565:22]
  wire  _T_609 = new_request_param == 3'h0 | new_request_param == 3'h4; // @[Parameters.scala 281:34]
  wire  _T_610 = new_meta_state == 2'h2; // @[MSHR.scala 575:56]
  wire  _GEN_108 = _T_609 & new_meta_state == 2'h2 ? 1'h0 : _GEN_107; // @[MSHR.scala 575:67 576:21]
  wire  _T_616 = _new_needT_T_3 | new_request_param == 3'h2 | new_request_param == 3'h5; // @[Parameters.scala 278:66]
  wire  _GEN_109 = _T_616 & (new_meta_clients & new_clientBit) ? 1'h0 : _GEN_108; // @[MSHR.scala 579:89 580:21]
  wire  _T_622 = ~new_meta_hit; // @[MSHR.scala 582:14]
  wire  _GEN_110 = new_meta_clients ? 1'h0 : 1'h1; // @[MSHR.scala 592:75 593:20 547:22]
  wire  _GEN_114 = _T_622 & new_meta_state != 2'h0 ? 1'h0 : 1'h1; // @[MSHR.scala 603:58 604:19 550:22]
  wire  _GEN_115 = _T_622 & new_meta_state != 2'h0 ? _GEN_110 : 1'h1; // @[MSHR.scala 547:22 603:58]
  wire  _GEN_116 = _T_622 | new_meta_state == 2'h1 & new_needT ? 1'h0 : 1'h1; // @[MSHR.scala 614:72 615:19 553:22]
  wire  _T_636 = new_needT | _T_610; // @[MSHR.scala 624:24]
  wire  _T_637 = new_meta_hit & _T_636; // @[MSHR.scala 623:55]
  wire  _T_639 = new_meta_clients & ~new_skipProbe; // @[MSHR.scala 625:31]
  wire  _T_641 = _T_637 & _T_639; // @[MSHR.scala 624:53]
  wire  _GEN_117 = _T_641 ? 1'h0 : 1'h1; // @[MSHR.scala 625:63 626:18 552:22]
  wire  _GEN_118 = _T_641 ? 1'h0 : _GEN_116; // @[MSHR.scala 625:63 630:21]
  wire  _GEN_119 = _new_needT_T_8 ? 1'h0 : 1'h1; // @[MSHR.scala 633:88 634:20 564:22]
  wire  _GEN_120 = _new_needT_T_8 ? 1'h0 : _GEN_118; // @[MSHR.scala 633:88 635:21]
  wire  _GEN_121 = _new_needT_T_1 & new_meta_hit & _T_605 ? 1'h0 : _GEN_120; // @[MSHR.scala 638:72 639:21]
  wire  _GEN_131 = new_request_prio_2 ? _GEN_109 : _GEN_121; // @[MSHR.scala 568:60]
  wire  _GEN_133 = new_request_prio_2 | _GEN_114; // @[MSHR.scala 550:22 568:60]
  wire  _GEN_134 = new_request_prio_2 | _GEN_115; // @[MSHR.scala 547:22 568:60]
  wire  _GEN_135 = new_request_prio_2 | _GEN_116; // @[MSHR.scala 553:22 568:60]
  wire  _GEN_136 = new_request_prio_2 | _GEN_117; // @[MSHR.scala 552:22 568:60]
  wire  _GEN_137 = new_request_prio_2 | _GEN_119; // @[MSHR.scala 564:22 568:60]
  wire  _GEN_138 = io_directory_valid | _new_meta_T | _GEN_26; // @[MSHR.scala 536:79 537:16]
  wire  _GEN_150 = io_directory_valid | _new_meta_T ? _GEN_134 : _GEN_16; // @[MSHR.scala 536:79]
  wire  _GEN_151 = io_directory_valid | _new_meta_T ? _GEN_134 : _GEN_67; // @[MSHR.scala 536:79]
  wire  _GEN_152 = io_directory_valid | _new_meta_T ? _GEN_134 : _GEN_68; // @[MSHR.scala 536:79]
  wire  _GEN_153 = io_directory_valid | _new_meta_T ? _GEN_133 : _GEN_17; // @[MSHR.scala 536:79]
  wire  _GEN_154 = io_directory_valid | _new_meta_T ? _GEN_133 : _GEN_87; // @[MSHR.scala 536:79]
  wire  _GEN_155 = io_directory_valid | _new_meta_T ? _GEN_136 : _GEN_18; // @[MSHR.scala 536:79]
  wire  _GEN_156 = io_directory_valid | _new_meta_T ? _GEN_135 : _GEN_19; // @[MSHR.scala 536:79]
  wire  _GEN_158 = io_directory_valid | _new_meta_T ? _GEN_135 : _GEN_82; // @[MSHR.scala 536:79]
  wire  _GEN_159 = io_directory_valid | _new_meta_T ? _GEN_135 : _GEN_83; // @[MSHR.scala 536:79]
  wire  _GEN_160 = io_directory_valid | _new_meta_T ? _GEN_135 : _GEN_85; // @[MSHR.scala 536:79]
  wire  _GEN_161 = io_directory_valid | _new_meta_T ? _GEN_136 : _GEN_69; // @[MSHR.scala 536:79]
  wire  _GEN_162 = io_directory_valid | _new_meta_T ? _GEN_136 : _GEN_70; // @[MSHR.scala 536:79]
  wire  _GEN_163 = io_directory_valid | _new_meta_T ? _GEN_136 : _GEN_71; // @[MSHR.scala 536:79]
  wire  _GEN_165 = io_directory_valid | _new_meta_T ? _GEN_135 : _GEN_22; // @[MSHR.scala 536:79]
  wire  _GEN_166 = io_directory_valid | _new_meta_T ? 1'h0 : _GEN_23; // @[MSHR.scala 536:79]
  wire  _GEN_167 = io_directory_valid | _new_meta_T ? _GEN_137 : _GEN_88; // @[MSHR.scala 536:79]
  wire  _GEN_168 = io_directory_valid | _new_meta_T ? _GEN_131 : _GEN_24; // @[MSHR.scala 536:79]
  wire  _GEN_66 = meta_valid & _T; // @[MSHR.scala 102:14]
  wire  _GEN_147 = meta_valid & _T & ~reset; // @[MSHR.scala 102:14]
  wire  _GEN_176 = meta_valid & _T_15; // @[MSHR.scala 109:14]
  wire  _GEN_177 = meta_valid & _T_15 & _T_4; // @[MSHR.scala 109:14]
  wire  _GEN_185 = _T_58 & _T_4; // @[MSHR.scala 361:13]
  wire  _GEN_195 = _T_117 & _T_4; // @[MSHR.scala 372:15]
  wire  _GEN_249 = _new_meta_T & _T_4; // @[MSHR.scala 518:11]
  assign io_status_valid = request_valid; // @[MSHR.scala 161:19]
  assign io_status_bits_set = request_set; // @[MSHR.scala 162:25]
  assign io_status_bits_tag = request_tag; // @[MSHR.scala 163:25]
  assign io_status_bits_way = meta_way; // @[MSHR.scala 164:25]
  assign io_status_bits_blockB = ~meta_valid | (~w_releaseack | ~w_rprobeacklast | ~w_pprobeacklast) & ~w_grantfirst; // @[MSHR.scala 165:40]
  assign io_status_bits_nestB = meta_valid & w_releaseack & w_rprobeacklast & w_pprobeacklast &
    _io_status_bits_blockB_T_6; // @[MSHR.scala 166:93]
  assign io_status_bits_blockC = ~meta_valid; // @[MSHR.scala 169:28]
  assign io_status_bits_nestC = meta_valid & (~w_rprobeackfirst | ~w_pprobeackfirst | _io_status_bits_blockB_T_6); // @[MSHR.scala 170:39]
  assign io_schedule_valid = _io_schedule_valid_T_2 | io_schedule_bits_e_valid | io_schedule_bits_x_valid |
    io_schedule_bits_dir_valid; // @[MSHR.scala 190:105]
  assign io_schedule_bits_a_valid = ~s_acquire & s_release & s_pprobe; // @[MSHR.scala 181:55]
  assign io_schedule_bits_a_bits_tag = request_tag; // @[MSHR.scala 277:35]
  assign io_schedule_bits_a_bits_set = request_set; // @[MSHR.scala 278:35]
  assign io_schedule_bits_a_bits_param = {{1'd0}, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala 279:35]
  assign io_schedule_bits_a_bits_block = request_size != 3'h4 | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala 280:95]
  assign io_schedule_bits_b_valid = ~s_rprobe | ~s_pprobe; // @[MSHR.scala 182:41]
  assign io_schedule_bits_b_bits_param = _io_schedule_bits_b_valid_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala 283:41]
  assign io_schedule_bits_b_bits_tag = _io_schedule_bits_b_valid_T ? meta_tag : request_tag; // @[MSHR.scala 284:41]
  assign io_schedule_bits_b_bits_set = request_set; // @[MSHR.scala 285:35]
  assign io_schedule_bits_b_bits_clients = meta_clients & ~excluded_client; // @[MSHR.scala 286:51]
  assign io_schedule_bits_c_valid = ~s_release & w_rprobeackfirst; // @[MSHR.scala 183:43]
  assign io_schedule_bits_c_bits_opcode = meta_dirty ? 3'h7 : 3'h6; // @[MSHR.scala 287:41]
  assign io_schedule_bits_c_bits_param = _T_10 ? 3'h2 : 3'h1; // @[MSHR.scala 288:41]
  assign io_schedule_bits_c_bits_tag = meta_tag; // @[MSHR.scala 290:35]
  assign io_schedule_bits_c_bits_set = request_set; // @[MSHR.scala 291:35]
  assign io_schedule_bits_c_bits_way = meta_way; // @[MSHR.scala 292:35]
  assign io_schedule_bits_c_bits_dirty = meta_dirty; // @[MSHR.scala 293:35]
  assign io_schedule_bits_d_valid = ~s_execute & w_pprobeack & w_grant; // @[MSHR.scala 184:57]
  assign io_schedule_bits_d_bits_prio_0 = request_prio_0; // @[MSHR.scala 294:35]
  assign io_schedule_bits_d_bits_prio_2 = request_prio_2; // @[MSHR.scala 294:35]
  assign io_schedule_bits_d_bits_opcode = request_opcode; // @[MSHR.scala 294:35]
  assign io_schedule_bits_d_bits_param = ~_req_needT_T_8 ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala 295:41]
  assign io_schedule_bits_d_bits_size = request_size; // @[MSHR.scala 294:35]
  assign io_schedule_bits_d_bits_source = request_source; // @[MSHR.scala 294:35]
  assign io_schedule_bits_d_bits_offset = request_offset; // @[MSHR.scala 294:35]
  assign io_schedule_bits_d_bits_put = request_put; // @[MSHR.scala 294:35]
  assign io_schedule_bits_d_bits_set = request_set; // @[MSHR.scala 294:35]
  assign io_schedule_bits_d_bits_way = meta_way; // @[MSHR.scala 301:35]
  assign io_schedule_bits_d_bits_bad = bad_grant; // @[MSHR.scala 302:35]
  assign io_schedule_bits_e_valid = ~s_grantack & w_grantfirst; // @[MSHR.scala 185:43]
  assign io_schedule_bits_e_bits_sink = sink; // @[MSHR.scala 303:35]
  assign io_schedule_bits_x_valid = 1'h0; // @[MSHR.scala 186:40]
  assign io_schedule_bits_dir_valid = _io_schedule_bits_c_valid_T_1 | ~s_writeback & no_wait; // @[MSHR.scala 187:66]
  assign io_schedule_bits_dir_bits_set = request_set; // @[MSHR.scala 305:35]
  assign io_schedule_bits_dir_bits_way = meta_way; // @[MSHR.scala 306:35]
  assign io_schedule_bits_dir_bits_data_dirty = _io_schedule_bits_c_valid_T ? 1'h0 : final_meta_writeback_dirty; // @[MSHR.scala 307:41]
  assign io_schedule_bits_dir_bits_data_state = _io_schedule_bits_c_valid_T ? 2'h0 : final_meta_writeback_state; // @[MSHR.scala 307:41]
  assign io_schedule_bits_dir_bits_data_clients = _io_schedule_bits_c_valid_T ? 1'h0 : final_meta_writeback_clients; // @[MSHR.scala 307:41]
  assign io_schedule_bits_dir_bits_data_tag = _io_schedule_bits_c_valid_T ? 26'h0 : final_meta_writeback_tag; // @[MSHR.scala 307:41]
  assign io_schedule_bits_reload = w_rprobeacklast & w_releaseack & w_grantlast & w_pprobeacklast & w_grantack; // @[MSHR.scala 180:83]
  always @(posedge clock) begin
    if (reset) begin // @[MSHR.scala 94:30]
      request_valid <= 1'h0; // @[MSHR.scala 94:30]
    end else begin
      request_valid <= _GEN_94;
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_prio_0 <= io_allocate_bits_prio_0; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_prio_1 <= io_allocate_bits_prio_1; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_prio_2 <= io_allocate_bits_prio_2; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_opcode <= io_allocate_bits_opcode; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_param <= io_allocate_bits_param; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_size <= io_allocate_bits_size; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_source <= io_allocate_bits_source; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_tag <= io_allocate_bits_tag; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_offset <= io_allocate_bits_offset; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_put <= io_allocate_bits_put; // @[MSHR.scala 532:13]
    end
    if (io_allocate_valid) begin // @[MSHR.scala 529:28]
      request_set <= io_allocate_bits_set; // @[MSHR.scala 532:13]
    end
    if (reset) begin // @[MSHR.scala 96:27]
      meta_valid <= 1'h0; // @[MSHR.scala 96:27]
    end else begin
      meta_valid <= _GEN_138;
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      if (io_allocate_valid & io_allocate_bits_repeat) begin // @[MSHR.scala 502:21]
        if (bad_grant) begin // @[MSHR.scala 248:20]
          meta_dirty <= 1'h0;
        end else if (request_prio_2) begin // @[MSHR.scala 220:54]
          meta_dirty <= meta_dirty | request_opcode[0]; // @[MSHR.scala 221:34]
        end else begin
          meta_dirty <= _final_meta_writeback_dirty_T_5;
        end
      end else begin
        meta_dirty <= io_directory_bits_dirty;
      end
    end else if (io_sinkc_valid) begin // @[MSHR.scala 458:49]
      meta_dirty <= _GEN_63;
    end else if (_T_31 & io_nestedwb_tag == meta_tag) begin // @[MSHR.scala 153:74]
      meta_dirty <= _GEN_1;
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      if (io_allocate_valid & io_allocate_bits_repeat) begin // @[MSHR.scala 502:21]
        if (bad_grant) begin // @[MSHR.scala 248:20]
          if (meta_hit) begin // @[MSHR.scala 249:21]
            meta_state <= 2'h1; // @[MSHR.scala 254:36]
          end else begin
            meta_state <= 2'h0; // @[MSHR.scala 260:36]
          end
        end else if (request_prio_2) begin // @[MSHR.scala 220:54]
          meta_state <= _final_meta_writeback_state_T_3; // @[MSHR.scala 222:34]
        end else begin
          meta_state <= _final_meta_writeback_state_T_17;
        end
      end else begin
        meta_state <= io_directory_bits_state;
      end
    end else if (_T_31 & io_nestedwb_tag == meta_tag) begin // @[MSHR.scala 153:74]
      if (io_nestedwb_b_toB) begin // @[MSHR.scala 156:30]
        meta_state <= 2'h1; // @[MSHR.scala 156:43]
      end
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      if (io_allocate_valid & io_allocate_bits_repeat) begin // @[MSHR.scala 502:21]
        if (bad_grant) begin // @[MSHR.scala 248:20]
          meta_clients <= _final_meta_writeback_clients_T_12;
        end else if (request_prio_2) begin // @[MSHR.scala 220:54]
          meta_clients <= meta_clients & ~(_final_meta_writeback_clients_T_4 & req_clientBit); // @[MSHR.scala 223:34]
        end else begin
          meta_clients <= _final_meta_writeback_clients_T_14;
        end
      end else begin
        meta_clients <= io_directory_bits_clients;
      end
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      if (io_allocate_valid & io_allocate_bits_repeat) begin // @[MSHR.scala 502:21]
        if (!(request_prio_2)) begin // @[MSHR.scala 220:54]
          meta_tag <= request_tag;
        end
      end else begin
        meta_tag <= io_directory_bits_tag;
      end
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      if (io_allocate_valid & io_allocate_bits_repeat) begin // @[MSHR.scala 502:21]
        if (!(bad_grant)) begin // @[MSHR.scala 248:20]
          meta_hit <= 1'h1;
        end
      end else begin
        meta_hit <= io_directory_bits_hit;
      end
    end else if (_T_31 & io_nestedwb_tag == meta_tag) begin // @[MSHR.scala 153:74]
      if (io_nestedwb_b_toN) begin // @[MSHR.scala 157:30]
        meta_hit <= 1'h0; // @[MSHR.scala 157:41]
      end
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      if (!(io_allocate_valid & io_allocate_bits_repeat)) begin // @[MSHR.scala 502:21]
        meta_way <= io_directory_bits_way;
      end
    end
    s_rprobe <= reset | _GEN_150; // @[MSHR.scala 118:{33,33}]
    w_rprobeackfirst <= reset | _GEN_151; // @[MSHR.scala 119:{33,33}]
    w_rprobeacklast <= reset | _GEN_152; // @[MSHR.scala 120:{33,33}]
    s_release <= reset | _GEN_153; // @[MSHR.scala 121:{33,33}]
    w_releaseack <= reset | _GEN_154; // @[MSHR.scala 122:{33,33}]
    s_pprobe <= reset | _GEN_155; // @[MSHR.scala 123:{33,33}]
    s_acquire <= reset | _GEN_156; // @[MSHR.scala 124:{33,33}]
    w_grantfirst <= reset | _GEN_158; // @[MSHR.scala 126:{33,33}]
    w_grantlast <= reset | _GEN_159; // @[MSHR.scala 127:{33,33}]
    w_grant <= reset | _GEN_160; // @[MSHR.scala 128:{33,33}]
    w_pprobeackfirst <= reset | _GEN_161; // @[MSHR.scala 129:{33,33}]
    w_pprobeacklast <= reset | _GEN_162; // @[MSHR.scala 130:{33,33}]
    w_pprobeack <= reset | _GEN_163; // @[MSHR.scala 131:{33,33}]
    s_grantack <= reset | _GEN_165; // @[MSHR.scala 133:{33,33}]
    s_execute <= reset | _GEN_166; // @[MSHR.scala 134:{33,33}]
    w_grantack <= reset | _GEN_167; // @[MSHR.scala 135:{33,33}]
    s_writeback <= reset | _GEN_168; // @[MSHR.scala 136:{33,33}]
    if (io_sinkd_valid) begin // @[MSHR.scala 479:25]
      if (io_sinkd_bits_opcode == 3'h4 | io_sinkd_bits_opcode == 3'h5) begin // @[MSHR.scala 480:81]
        sink <= io_sinkd_bits_sink; // @[MSHR.scala 481:12]
      end
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      gotT <= 1'h0; // @[MSHR.scala 542:10]
    end else if (io_sinkd_valid) begin // @[MSHR.scala 479:25]
      if (io_sinkd_bits_opcode == 3'h4 | io_sinkd_bits_opcode == 3'h5) begin // @[MSHR.scala 480:81]
        gotT <= io_sinkd_bits_param == 3'h0; // @[MSHR.scala 490:12]
      end
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      bad_grant <= 1'h0; // @[MSHR.scala 543:15]
    end else if (io_sinkd_valid) begin // @[MSHR.scala 479:25]
      if (io_sinkd_bits_opcode == 3'h4 | io_sinkd_bits_opcode == 3'h5) begin // @[MSHR.scala 480:81]
        bad_grant <= io_sinkd_bits_denied; // @[MSHR.scala 485:17]
      end
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      probes_done <= 1'h0; // @[MSHR.scala 539:17]
    end else if (io_sinkc_valid) begin // @[MSHR.scala 458:49]
      probes_done <= _last_probe_T; // @[MSHR.scala 464:17]
    end
    if (io_directory_valid | _new_meta_T) begin // @[MSHR.scala 536:79]
      probes_toN <= 1'h0; // @[MSHR.scala 540:16]
    end else if (io_sinkc_valid) begin // @[MSHR.scala 458:49]
      probes_toN <= probes_toN | probe_toN & probe_bit; // @[MSHR.scala 465:16]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (meta_valid & _T & ~reset & ~(~(|meta_clients))) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MSHR.scala:102 assert (!meta.clients.orR)\n"); // @[MSHR.scala 102:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(|meta_clients)) & (meta_valid & _T & ~reset)) begin
          $fatal; // @[MSHR.scala 102:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_147 & ~(~meta_dirty)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MSHR.scala:103 assert (!meta.dirty)\n"); // @[MSHR.scala 103:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~meta_dirty) & (_GEN_66 & _T_4)) begin
          $fatal; // @[MSHR.scala 103:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (meta_valid & _T_10 & _T_4 & _T_9) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MSHR.scala:106 assert (!meta.dirty)\n"); // @[MSHR.scala 106:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_6 & (meta_valid & _T_10 & _T_4)) begin
          $fatal; // @[MSHR.scala 106:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (meta_valid & _T_15 & _T_4 & _T_2) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MSHR.scala:109 assert (meta.clients.orR)\n"); // @[MSHR.scala 109:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1 & (meta_valid & _T_15 & _T_4)) begin
          $fatal; // @[MSHR.scala 109:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_177 & ~(~(meta_clients & meta_clients - 1'h1))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MSHR.scala:110 assert ((meta.clients & (meta.clients - UInt(1))) === UInt(0)) // at most one\n"
            ); // @[MSHR.scala 110:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(meta_clients & meta_clients - 1'h1)) & (_GEN_176 & _T_4)) begin
          $fatal; // @[MSHR.scala 110:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_4 & ~(~io_status_bits_nestB | ~io_status_bits_blockB)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MSHR.scala:176 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n"); // @[MSHR.scala 176:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_status_bits_nestB | ~io_status_bits_blockB) & _T_4) begin
          $fatal; // @[MSHR.scala 176:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_4 & ~(~io_status_bits_nestC | ~io_status_bits_blockC)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MSHR.scala:177 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n"); // @[MSHR.scala 177:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_status_bits_nestC | ~io_status_bits_blockC) & _T_4) begin
          $fatal; // @[MSHR.scala 177:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (bad_grant & meta_hit & _T_4 & ~(_io_status_bits_blockB_T | _T_10)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MSHR.scala:251 assert (!meta_valid || meta.state === BRANCH)\n"
            ); // @[MSHR.scala 251:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_io_status_bits_blockB_T | _T_10) & (bad_grant & meta_hit & _T_4)) begin
          $fatal; // @[MSHR.scala 251:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_58 & _T_4 & ~(~(evict == 4'h1))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,false)\n    at MSHR.scala:343 assert(!(evict === from.code), s\"State transition from ${from} to evicted should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 361:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(evict == 4'h1)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 361:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_58 & _T_4 & ~(~(before_ == 4'h1))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,false)\n    at MSHR.scala:348 assert(!(before === from.code), s\"State transition from ${from} to flushed should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 361:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h1)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 361:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_185 & ~(~(evict == 4'h0))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,false)\n    at MSHR.scala:343 assert(!(evict === from.code), s\"State transition from ${from} to evicted should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 362:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(evict == 4'h0)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 362:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_185 & ~(~(before_ == 4'h0))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,false)\n    at MSHR.scala:348 assert(!(before === from.code), s\"State transition from ${from} to flushed should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 362:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h0)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 362:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_185 & ~(~(before_ == 4'h7))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP to flushed should be impossible (false,true,true,false,false)\n    at MSHR.scala:348 assert(!(before === from.code), s\"State transition from ${from} to flushed should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 363:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h7)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 363:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_185 & ~(~(before_ == 4'h5))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_C to flushed should be impossible (false,true,true,false,false)\n    at MSHR.scala:348 assert(!(before === from.code), s\"State transition from ${from} to flushed should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 364:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h5)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 364:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_185 & ~(~(before_ == 4'h4))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_CD to flushed should be impossible (false,true,true,false,false)\n    at MSHR.scala:348 assert(!(before === from.code), s\"State transition from ${from} to flushed should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 365:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h4)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 365:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_185 & ~(~(before_ == 4'h6))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_D to flushed should be impossible (false,true,true,false,false)\n    at MSHR.scala:348 assert(!(before === from.code), s\"State transition from ${from} to flushed should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 366:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h6)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 366:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_185 & ~(~(before_ == 4'h3))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_C to flushed should be impossible (false,true,true,false,false)\n    at MSHR.scala:348 assert(!(before === from.code), s\"State transition from ${from} to flushed should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 367:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h3)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 367:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_185 & ~(~(before_ == 4'h2))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_CD to flushed should be impossible (false,true,true,false,false)\n    at MSHR.scala:348 assert(!(before === from.code), s\"State transition from ${from} to flushed should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 368:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h2)) & (_T_58 & _T_4)) begin
          $fatal; // @[MSHR.scala 368:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_117 & _T_4 & ~(~(before_ == 4'h8 & after == 4'h1))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 372:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(before_ == 4'h8 & after == 4'h1)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 372:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_118 & after == 4'h0))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 373:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_118 & after == 4'h0)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 373:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_118 & after == 4'h5))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 375:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_118 & after == 4'h5)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 375:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_118 & after == 4'h4))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 376:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_118 & after == 4'h4)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 376:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_118 & after == 4'h2))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 379:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_118 & after == 4'h2)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 379:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_64 & after == 4'h8))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 381:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_64 & after == 4'h8)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 381:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_64 & _T_126))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 382:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_64 & _T_126)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 382:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_64 & after == 4'h7))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 383:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_64 & after == 4'h7)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 383:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_64 & _T_136))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 384:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_64 & _T_136)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 384:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_64 & _T_143))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 385:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_64 & _T_143)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 385:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_64 & after == 4'h6))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 386:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_64 & after == 4'h6)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 386:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_64 & after == 4'h3))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 387:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_64 & after == 4'h3)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 387:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_64 & _T_156))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 388:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_64 & _T_156)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 388:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_74 & _T_163))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 390:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_74 & _T_163)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 390:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_74 & _T_119))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 391:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_74 & _T_119)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 391:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_74 & _T_177))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 392:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_74 & _T_177)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 392:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_74 & _T_136))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 393:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_74 & _T_136)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 393:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_74 & _T_198))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 394:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_74 & _T_198)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 394:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_74 & _T_143))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 395:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_74 & _T_143)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 395:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_74 & _T_205))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 396:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_74 & _T_205)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 396:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_74 & _T_156))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 397:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_74 & _T_156)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 397:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_80 & _T_163))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 399:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_80 & _T_163)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 399:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_80 & _T_119))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 400:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_80 & _T_119)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 400:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_80 & _T_126))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 401:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_80 & _T_126)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 401:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_80 & _T_136))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 402:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_80 & _T_136)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 402:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_80 & _T_143))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 404:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_80 & _T_143)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 404:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_80 & _T_156))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 406:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_80 & _T_156)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 406:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_86 & _T_163))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 408:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_86 & _T_163)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 408:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_86 & _T_119))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 409:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_86 & _T_119)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 409:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_86 & _T_126))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 410:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_86 & _T_126)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 410:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_86 & _T_143))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 413:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_86 & _T_143)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 413:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_86 & _T_156))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 415:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_86 & _T_156)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 415:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_98 & _T_163))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 417:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_98 & _T_163)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 417:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_98 & _T_119))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 418:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_98 & _T_119)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 418:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_98 & _T_126))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 419:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_98 & _T_126)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 419:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_98 & _T_177))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 420:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_98 & _T_177)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 420:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_98 & _T_136))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 421:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_98 & _T_136)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 421:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_98 & _T_143))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 422:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_98 & _T_143)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 422:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_98 & _T_205))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 423:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_98 & _T_205)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 423:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_92 & _T_163))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 426:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_92 & _T_163)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 426:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_92 & _T_119))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 427:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_92 & _T_119)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 427:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_92 & _T_126))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 428:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_92 & _T_126)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 428:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_92 & _T_177))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 429:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_92 & _T_177)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 429:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_92 & _T_136))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 430:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_92 & _T_136)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 430:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_92 & _T_205))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 432:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_92 & _T_205)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 432:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_104 & _T_163))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 435:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_104 & _T_163)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 435:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_104 & _T_119))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 436:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_104 & _T_119)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 436:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_104 & _T_126))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 437:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_104 & _T_126)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 437:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_110 & _T_163))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 444:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_110 & _T_163)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 444:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_110 & _T_119))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 445:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_110 & _T_119)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 445:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_110 & _T_126))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 446:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_110 & _T_126)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 446:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_110 & _T_177))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 447:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_110 & _T_177)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 447:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_110 & _T_136))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 448:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_110 & _T_136)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 448:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_195 & ~(~(_T_110 & _T_205))) begin
          $fwrite(32'h80000002,
            "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:356 assert(!(before === from.code && after === to.code), s\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 451:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(_T_110 & _T_205)) & (_T_117 & _T_4)) begin
          $fatal; // @[MSHR.scala 451:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_new_meta_T & _T_4 & ~(~_T_163)) begin
          $fwrite(32'h80000002,
            "Assertion failed: State bypass from S_INVALID should be impossible (false,true,true,false,false)\n    at MSHR.scala:513 assert(!(prior === from.code), s\"State bypass from ${from} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 518:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_T_163) & (_new_meta_T & _T_4)) begin
          $fatal; // @[MSHR.scala 518:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_249 & ~(~_T_119)) begin
          $fwrite(32'h80000002,
            "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,false)\n    at MSHR.scala:513 assert(!(prior === from.code), s\"State bypass from ${from} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 519:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_T_119) & (_new_meta_T & _T_4)) begin
          $fatal; // @[MSHR.scala 519:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_249 & ~(~_T_126)) begin
          $fwrite(32'h80000002,
            "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,false)\n    at MSHR.scala:513 assert(!(prior === from.code), s\"State bypass from ${from} should be impossible ${cfg}\")\n"
            ); // @[MSHR.scala 520:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_T_126) & (_new_meta_T & _T_4)) begin
          $fatal; // @[MSHR.scala 520:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_allocate_valid & _T_4 & ~(~request_valid | no_wait & _T_595)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MSHR.scala:530 assert (!request_valid || (no_wait && io.schedule.fire()))\n"); // @[MSHR.scala 530:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~request_valid | no_wait & _T_595) & (io_allocate_valid & _T_4)) begin
          $fatal; // @[MSHR.scala 530:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_602 & new_request_prio_2 & _T_4 & ~new_meta_hit) begin
          $fwrite(32'h80000002,"Assertion failed\n    at MSHR.scala:582 assert (new_meta.hit)\n"); // @[MSHR.scala 582:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~new_meta_hit & (_T_602 & new_request_prio_2 & _T_4)) begin
          $fatal; // @[MSHR.scala 582:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  request_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  request_prio_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  request_prio_1 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  request_prio_2 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  request_opcode = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  request_param = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  request_size = _RAND_6[2:0];
  _RAND_7 = {1{`RANDOM}};
  request_source = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  request_tag = _RAND_8[25:0];
  _RAND_9 = {1{`RANDOM}};
  request_offset = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  request_put = _RAND_10[5:0];
  _RAND_11 = {1{`RANDOM}};
  request_set = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  meta_valid = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  meta_dirty = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  meta_state = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  meta_clients = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  meta_tag = _RAND_16[25:0];
  _RAND_17 = {1{`RANDOM}};
  meta_hit = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  meta_way = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  s_rprobe = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  w_rprobeackfirst = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  w_rprobeacklast = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  s_release = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  w_releaseack = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  s_pprobe = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  s_acquire = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  w_grantfirst = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  w_grantlast = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  w_grant = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  w_pprobeackfirst = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  w_pprobeacklast = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  w_pprobeack = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  s_grantack = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  s_execute = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  w_grantack = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  s_writeback = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  sink = _RAND_36[2:0];
  _RAND_37 = {1{`RANDOM}};
  gotT = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  bad_grant = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  probes_done = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  probes_toN = _RAND_40[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Scheduler(
  input         clock,
  input         reset,
  output        io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [2:0]  io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input  [63:0] io_in_a_bits_data,
  input         io_in_a_bits_corrupt,
  input         io_in_b_ready,
  output        io_in_b_valid,
  output [1:0]  io_in_b_bits_param,
  output [31:0] io_in_b_bits_address,
  output        io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [2:0]  io_in_c_bits_size,
  input  [31:0] io_in_c_bits_address,
  input  [63:0] io_in_c_bits_data,
  input         io_in_c_bits_corrupt,
  input         io_in_d_ready,
  output        io_in_d_valid,
  output [2:0]  io_in_d_bits_opcode,
  output [1:0]  io_in_d_bits_param,
  output [2:0]  io_in_d_bits_size,
  output [2:0]  io_in_d_bits_source,
  output [4:0]  io_in_d_bits_sink,
  output        io_in_d_bits_denied,
  output [63:0] io_in_d_bits_data,
  output        io_in_d_bits_corrupt,
  input         io_in_e_valid,
  input  [4:0]  io_in_e_bits_sink,
  input         io_out_a_ready,
  output        io_out_a_valid,
  output [2:0]  io_out_a_bits_opcode,
  output [2:0]  io_out_a_bits_param,
  output [2:0]  io_out_a_bits_size,
  output [4:0]  io_out_a_bits_source,
  output [31:0] io_out_a_bits_address,
  output [7:0]  io_out_a_bits_mask,
  output [63:0] io_out_a_bits_data,
  output        io_out_a_bits_corrupt,
  input         io_out_c_ready,
  output        io_out_c_valid,
  output [2:0]  io_out_c_bits_opcode,
  output [2:0]  io_out_c_bits_param,
  output [2:0]  io_out_c_bits_size,
  output [4:0]  io_out_c_bits_source,
  output [31:0] io_out_c_bits_address,
  output [63:0] io_out_c_bits_data,
  output        io_out_c_bits_corrupt,
  output        io_out_d_ready,
  input         io_out_d_valid,
  input  [2:0]  io_out_d_bits_opcode,
  input  [1:0]  io_out_d_bits_param,
  input  [2:0]  io_out_d_bits_size,
  input  [4:0]  io_out_d_bits_source,
  input  [2:0]  io_out_d_bits_sink,
  input         io_out_d_bits_denied,
  input  [63:0] io_out_d_bits_data,
  input         io_out_d_bits_corrupt,
  output        io_out_e_valid,
  output [2:0]  io_out_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  sourceA_clock; // @[Scheduler.scala 38:23]
  wire  sourceA_reset; // @[Scheduler.scala 38:23]
  wire  sourceA_io_req_ready; // @[Scheduler.scala 38:23]
  wire  sourceA_io_req_valid; // @[Scheduler.scala 38:23]
  wire [25:0] sourceA_io_req_bits_tag; // @[Scheduler.scala 38:23]
  wire [1:0] sourceA_io_req_bits_set; // @[Scheduler.scala 38:23]
  wire [2:0] sourceA_io_req_bits_param; // @[Scheduler.scala 38:23]
  wire [4:0] sourceA_io_req_bits_source; // @[Scheduler.scala 38:23]
  wire  sourceA_io_req_bits_block; // @[Scheduler.scala 38:23]
  wire  sourceA_io_a_ready; // @[Scheduler.scala 38:23]
  wire  sourceA_io_a_valid; // @[Scheduler.scala 38:23]
  wire [2:0] sourceA_io_a_bits_opcode; // @[Scheduler.scala 38:23]
  wire [2:0] sourceA_io_a_bits_param; // @[Scheduler.scala 38:23]
  wire [2:0] sourceA_io_a_bits_size; // @[Scheduler.scala 38:23]
  wire [4:0] sourceA_io_a_bits_source; // @[Scheduler.scala 38:23]
  wire [31:0] sourceA_io_a_bits_address; // @[Scheduler.scala 38:23]
  wire [7:0] sourceA_io_a_bits_mask; // @[Scheduler.scala 38:23]
  wire [63:0] sourceA_io_a_bits_data; // @[Scheduler.scala 38:23]
  wire  sourceA_io_a_bits_corrupt; // @[Scheduler.scala 38:23]
  wire  sourceB_clock; // @[Scheduler.scala 39:23]
  wire  sourceB_reset; // @[Scheduler.scala 39:23]
  wire  sourceB_io_req_ready; // @[Scheduler.scala 39:23]
  wire  sourceB_io_req_valid; // @[Scheduler.scala 39:23]
  wire [2:0] sourceB_io_req_bits_param; // @[Scheduler.scala 39:23]
  wire [25:0] sourceB_io_req_bits_tag; // @[Scheduler.scala 39:23]
  wire [1:0] sourceB_io_req_bits_set; // @[Scheduler.scala 39:23]
  wire  sourceB_io_req_bits_clients; // @[Scheduler.scala 39:23]
  wire  sourceB_io_b_ready; // @[Scheduler.scala 39:23]
  wire  sourceB_io_b_valid; // @[Scheduler.scala 39:23]
  wire [1:0] sourceB_io_b_bits_param; // @[Scheduler.scala 39:23]
  wire [31:0] sourceB_io_b_bits_address; // @[Scheduler.scala 39:23]
  wire  sourceC_clock; // @[Scheduler.scala 40:23]
  wire  sourceC_reset; // @[Scheduler.scala 40:23]
  wire  sourceC_io_req_ready; // @[Scheduler.scala 40:23]
  wire  sourceC_io_req_valid; // @[Scheduler.scala 40:23]
  wire [2:0] sourceC_io_req_bits_opcode; // @[Scheduler.scala 40:23]
  wire [2:0] sourceC_io_req_bits_param; // @[Scheduler.scala 40:23]
  wire [4:0] sourceC_io_req_bits_source; // @[Scheduler.scala 40:23]
  wire [25:0] sourceC_io_req_bits_tag; // @[Scheduler.scala 40:23]
  wire [1:0] sourceC_io_req_bits_set; // @[Scheduler.scala 40:23]
  wire  sourceC_io_req_bits_way; // @[Scheduler.scala 40:23]
  wire  sourceC_io_req_bits_dirty; // @[Scheduler.scala 40:23]
  wire  sourceC_io_c_ready; // @[Scheduler.scala 40:23]
  wire  sourceC_io_c_valid; // @[Scheduler.scala 40:23]
  wire [2:0] sourceC_io_c_bits_opcode; // @[Scheduler.scala 40:23]
  wire [2:0] sourceC_io_c_bits_param; // @[Scheduler.scala 40:23]
  wire [2:0] sourceC_io_c_bits_size; // @[Scheduler.scala 40:23]
  wire [4:0] sourceC_io_c_bits_source; // @[Scheduler.scala 40:23]
  wire [31:0] sourceC_io_c_bits_address; // @[Scheduler.scala 40:23]
  wire [63:0] sourceC_io_c_bits_data; // @[Scheduler.scala 40:23]
  wire  sourceC_io_c_bits_corrupt; // @[Scheduler.scala 40:23]
  wire  sourceC_io_bs_adr_ready; // @[Scheduler.scala 40:23]
  wire  sourceC_io_bs_adr_valid; // @[Scheduler.scala 40:23]
  wire  sourceC_io_bs_adr_bits_way; // @[Scheduler.scala 40:23]
  wire [1:0] sourceC_io_bs_adr_bits_set; // @[Scheduler.scala 40:23]
  wire  sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala 40:23]
  wire [63:0] sourceC_io_bs_dat_data; // @[Scheduler.scala 40:23]
  wire [1:0] sourceC_io_evict_req_set; // @[Scheduler.scala 40:23]
  wire  sourceC_io_evict_req_way; // @[Scheduler.scala 40:23]
  wire  sourceC_io_evict_safe; // @[Scheduler.scala 40:23]
  wire  sourceD_clock; // @[Scheduler.scala 41:23]
  wire  sourceD_reset; // @[Scheduler.scala 41:23]
  wire  sourceD_io_req_ready; // @[Scheduler.scala 41:23]
  wire  sourceD_io_req_valid; // @[Scheduler.scala 41:23]
  wire  sourceD_io_req_bits_prio_0; // @[Scheduler.scala 41:23]
  wire  sourceD_io_req_bits_prio_2; // @[Scheduler.scala 41:23]
  wire [2:0] sourceD_io_req_bits_opcode; // @[Scheduler.scala 41:23]
  wire [2:0] sourceD_io_req_bits_param; // @[Scheduler.scala 41:23]
  wire [2:0] sourceD_io_req_bits_size; // @[Scheduler.scala 41:23]
  wire [2:0] sourceD_io_req_bits_source; // @[Scheduler.scala 41:23]
  wire [3:0] sourceD_io_req_bits_offset; // @[Scheduler.scala 41:23]
  wire [5:0] sourceD_io_req_bits_put; // @[Scheduler.scala 41:23]
  wire [1:0] sourceD_io_req_bits_set; // @[Scheduler.scala 41:23]
  wire [4:0] sourceD_io_req_bits_sink; // @[Scheduler.scala 41:23]
  wire  sourceD_io_req_bits_way; // @[Scheduler.scala 41:23]
  wire  sourceD_io_req_bits_bad; // @[Scheduler.scala 41:23]
  wire  sourceD_io_d_ready; // @[Scheduler.scala 41:23]
  wire  sourceD_io_d_valid; // @[Scheduler.scala 41:23]
  wire [2:0] sourceD_io_d_bits_opcode; // @[Scheduler.scala 41:23]
  wire [1:0] sourceD_io_d_bits_param; // @[Scheduler.scala 41:23]
  wire [2:0] sourceD_io_d_bits_size; // @[Scheduler.scala 41:23]
  wire [2:0] sourceD_io_d_bits_source; // @[Scheduler.scala 41:23]
  wire [4:0] sourceD_io_d_bits_sink; // @[Scheduler.scala 41:23]
  wire  sourceD_io_d_bits_denied; // @[Scheduler.scala 41:23]
  wire [63:0] sourceD_io_d_bits_data; // @[Scheduler.scala 41:23]
  wire  sourceD_io_d_bits_corrupt; // @[Scheduler.scala 41:23]
  wire  sourceD_io_pb_pop_ready; // @[Scheduler.scala 41:23]
  wire  sourceD_io_pb_pop_valid; // @[Scheduler.scala 41:23]
  wire [5:0] sourceD_io_pb_pop_bits_index; // @[Scheduler.scala 41:23]
  wire  sourceD_io_pb_pop_bits_last; // @[Scheduler.scala 41:23]
  wire [63:0] sourceD_io_pb_beat_data; // @[Scheduler.scala 41:23]
  wire [7:0] sourceD_io_pb_beat_mask; // @[Scheduler.scala 41:23]
  wire  sourceD_io_pb_beat_corrupt; // @[Scheduler.scala 41:23]
  wire  sourceD_io_rel_pop_ready; // @[Scheduler.scala 41:23]
  wire  sourceD_io_rel_pop_valid; // @[Scheduler.scala 41:23]
  wire [5:0] sourceD_io_rel_pop_bits_index; // @[Scheduler.scala 41:23]
  wire  sourceD_io_rel_pop_bits_last; // @[Scheduler.scala 41:23]
  wire [63:0] sourceD_io_rel_beat_data; // @[Scheduler.scala 41:23]
  wire  sourceD_io_rel_beat_corrupt; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_radr_ready; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_radr_valid; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_radr_bits_way; // @[Scheduler.scala 41:23]
  wire [1:0] sourceD_io_bs_radr_bits_set; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala 41:23]
  wire [63:0] sourceD_io_bs_rdat_data; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_wadr_ready; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_wadr_valid; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala 41:23]
  wire [1:0] sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala 41:23]
  wire  sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala 41:23]
  wire [63:0] sourceD_io_bs_wdat_data; // @[Scheduler.scala 41:23]
  wire [1:0] sourceD_io_evict_req_set; // @[Scheduler.scala 41:23]
  wire  sourceD_io_evict_req_way; // @[Scheduler.scala 41:23]
  wire  sourceD_io_evict_safe; // @[Scheduler.scala 41:23]
  wire [1:0] sourceD_io_grant_req_set; // @[Scheduler.scala 41:23]
  wire  sourceD_io_grant_req_way; // @[Scheduler.scala 41:23]
  wire  sourceD_io_grant_safe; // @[Scheduler.scala 41:23]
  wire  sourceE_clock; // @[Scheduler.scala 42:23]
  wire  sourceE_reset; // @[Scheduler.scala 42:23]
  wire  sourceE_io_req_ready; // @[Scheduler.scala 42:23]
  wire  sourceE_io_req_valid; // @[Scheduler.scala 42:23]
  wire [2:0] sourceE_io_req_bits_sink; // @[Scheduler.scala 42:23]
  wire  sourceE_io_e_valid; // @[Scheduler.scala 42:23]
  wire [2:0] sourceE_io_e_bits_sink; // @[Scheduler.scala 42:23]
  wire  sinkA_clock; // @[Scheduler.scala 52:21]
  wire  sinkA_reset; // @[Scheduler.scala 52:21]
  wire  sinkA_io_req_ready; // @[Scheduler.scala 52:21]
  wire  sinkA_io_req_valid; // @[Scheduler.scala 52:21]
  wire [2:0] sinkA_io_req_bits_opcode; // @[Scheduler.scala 52:21]
  wire [2:0] sinkA_io_req_bits_param; // @[Scheduler.scala 52:21]
  wire [2:0] sinkA_io_req_bits_size; // @[Scheduler.scala 52:21]
  wire [2:0] sinkA_io_req_bits_source; // @[Scheduler.scala 52:21]
  wire [25:0] sinkA_io_req_bits_tag; // @[Scheduler.scala 52:21]
  wire [3:0] sinkA_io_req_bits_offset; // @[Scheduler.scala 52:21]
  wire [5:0] sinkA_io_req_bits_put; // @[Scheduler.scala 52:21]
  wire [1:0] sinkA_io_req_bits_set; // @[Scheduler.scala 52:21]
  wire  sinkA_io_a_ready; // @[Scheduler.scala 52:21]
  wire  sinkA_io_a_valid; // @[Scheduler.scala 52:21]
  wire [2:0] sinkA_io_a_bits_opcode; // @[Scheduler.scala 52:21]
  wire [2:0] sinkA_io_a_bits_param; // @[Scheduler.scala 52:21]
  wire [2:0] sinkA_io_a_bits_size; // @[Scheduler.scala 52:21]
  wire [2:0] sinkA_io_a_bits_source; // @[Scheduler.scala 52:21]
  wire [31:0] sinkA_io_a_bits_address; // @[Scheduler.scala 52:21]
  wire [7:0] sinkA_io_a_bits_mask; // @[Scheduler.scala 52:21]
  wire [63:0] sinkA_io_a_bits_data; // @[Scheduler.scala 52:21]
  wire  sinkA_io_a_bits_corrupt; // @[Scheduler.scala 52:21]
  wire  sinkA_io_pb_pop_ready; // @[Scheduler.scala 52:21]
  wire  sinkA_io_pb_pop_valid; // @[Scheduler.scala 52:21]
  wire [5:0] sinkA_io_pb_pop_bits_index; // @[Scheduler.scala 52:21]
  wire  sinkA_io_pb_pop_bits_last; // @[Scheduler.scala 52:21]
  wire [63:0] sinkA_io_pb_beat_data; // @[Scheduler.scala 52:21]
  wire [7:0] sinkA_io_pb_beat_mask; // @[Scheduler.scala 52:21]
  wire  sinkA_io_pb_beat_corrupt; // @[Scheduler.scala 52:21]
  wire  sinkC_clock; // @[Scheduler.scala 53:21]
  wire  sinkC_reset; // @[Scheduler.scala 53:21]
  wire  sinkC_io_req_ready; // @[Scheduler.scala 53:21]
  wire  sinkC_io_req_valid; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_req_bits_opcode; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_req_bits_param; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_req_bits_size; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_req_bits_source; // @[Scheduler.scala 53:21]
  wire [25:0] sinkC_io_req_bits_tag; // @[Scheduler.scala 53:21]
  wire [3:0] sinkC_io_req_bits_offset; // @[Scheduler.scala 53:21]
  wire [5:0] sinkC_io_req_bits_put; // @[Scheduler.scala 53:21]
  wire [1:0] sinkC_io_req_bits_set; // @[Scheduler.scala 53:21]
  wire  sinkC_io_resp_valid; // @[Scheduler.scala 53:21]
  wire  sinkC_io_resp_bits_last; // @[Scheduler.scala 53:21]
  wire [1:0] sinkC_io_resp_bits_set; // @[Scheduler.scala 53:21]
  wire [25:0] sinkC_io_resp_bits_tag; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_resp_bits_source; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_resp_bits_param; // @[Scheduler.scala 53:21]
  wire  sinkC_io_resp_bits_data; // @[Scheduler.scala 53:21]
  wire  sinkC_io_c_ready; // @[Scheduler.scala 53:21]
  wire  sinkC_io_c_valid; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_c_bits_opcode; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_c_bits_param; // @[Scheduler.scala 53:21]
  wire [2:0] sinkC_io_c_bits_size; // @[Scheduler.scala 53:21]
  wire [31:0] sinkC_io_c_bits_address; // @[Scheduler.scala 53:21]
  wire [63:0] sinkC_io_c_bits_data; // @[Scheduler.scala 53:21]
  wire  sinkC_io_c_bits_corrupt; // @[Scheduler.scala 53:21]
  wire [1:0] sinkC_io_set; // @[Scheduler.scala 53:21]
  wire  sinkC_io_way; // @[Scheduler.scala 53:21]
  wire  sinkC_io_bs_adr_ready; // @[Scheduler.scala 53:21]
  wire  sinkC_io_bs_adr_valid; // @[Scheduler.scala 53:21]
  wire  sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala 53:21]
  wire  sinkC_io_bs_adr_bits_way; // @[Scheduler.scala 53:21]
  wire [1:0] sinkC_io_bs_adr_bits_set; // @[Scheduler.scala 53:21]
  wire  sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala 53:21]
  wire  sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala 53:21]
  wire [63:0] sinkC_io_bs_dat_data; // @[Scheduler.scala 53:21]
  wire  sinkC_io_rel_pop_ready; // @[Scheduler.scala 53:21]
  wire  sinkC_io_rel_pop_valid; // @[Scheduler.scala 53:21]
  wire [5:0] sinkC_io_rel_pop_bits_index; // @[Scheduler.scala 53:21]
  wire  sinkC_io_rel_pop_bits_last; // @[Scheduler.scala 53:21]
  wire [63:0] sinkC_io_rel_beat_data; // @[Scheduler.scala 53:21]
  wire  sinkC_io_rel_beat_corrupt; // @[Scheduler.scala 53:21]
  wire  sinkD_clock; // @[Scheduler.scala 54:21]
  wire  sinkD_reset; // @[Scheduler.scala 54:21]
  wire  sinkD_io_resp_valid; // @[Scheduler.scala 54:21]
  wire  sinkD_io_resp_bits_last; // @[Scheduler.scala 54:21]
  wire [2:0] sinkD_io_resp_bits_opcode; // @[Scheduler.scala 54:21]
  wire [2:0] sinkD_io_resp_bits_param; // @[Scheduler.scala 54:21]
  wire [4:0] sinkD_io_resp_bits_source; // @[Scheduler.scala 54:21]
  wire [2:0] sinkD_io_resp_bits_sink; // @[Scheduler.scala 54:21]
  wire  sinkD_io_resp_bits_denied; // @[Scheduler.scala 54:21]
  wire  sinkD_io_d_ready; // @[Scheduler.scala 54:21]
  wire  sinkD_io_d_valid; // @[Scheduler.scala 54:21]
  wire [2:0] sinkD_io_d_bits_opcode; // @[Scheduler.scala 54:21]
  wire [1:0] sinkD_io_d_bits_param; // @[Scheduler.scala 54:21]
  wire [2:0] sinkD_io_d_bits_size; // @[Scheduler.scala 54:21]
  wire [4:0] sinkD_io_d_bits_source; // @[Scheduler.scala 54:21]
  wire [2:0] sinkD_io_d_bits_sink; // @[Scheduler.scala 54:21]
  wire  sinkD_io_d_bits_denied; // @[Scheduler.scala 54:21]
  wire [63:0] sinkD_io_d_bits_data; // @[Scheduler.scala 54:21]
  wire  sinkD_io_d_bits_corrupt; // @[Scheduler.scala 54:21]
  wire [4:0] sinkD_io_source; // @[Scheduler.scala 54:21]
  wire  sinkD_io_way; // @[Scheduler.scala 54:21]
  wire [1:0] sinkD_io_set; // @[Scheduler.scala 54:21]
  wire  sinkD_io_bs_adr_ready; // @[Scheduler.scala 54:21]
  wire  sinkD_io_bs_adr_valid; // @[Scheduler.scala 54:21]
  wire  sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala 54:21]
  wire  sinkD_io_bs_adr_bits_way; // @[Scheduler.scala 54:21]
  wire [1:0] sinkD_io_bs_adr_bits_set; // @[Scheduler.scala 54:21]
  wire  sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala 54:21]
  wire [63:0] sinkD_io_bs_dat_data; // @[Scheduler.scala 54:21]
  wire [1:0] sinkD_io_grant_req_set; // @[Scheduler.scala 54:21]
  wire  sinkD_io_grant_req_way; // @[Scheduler.scala 54:21]
  wire  sinkD_io_grant_safe; // @[Scheduler.scala 54:21]
  wire  sinkE_io_resp_valid; // @[Scheduler.scala 55:21]
  wire [4:0] sinkE_io_resp_bits_sink; // @[Scheduler.scala 55:21]
  wire  sinkE_io_e_valid; // @[Scheduler.scala 55:21]
  wire [4:0] sinkE_io_e_bits_sink; // @[Scheduler.scala 55:21]
  wire  directory_clock; // @[Scheduler.scala 66:25]
  wire  directory_reset; // @[Scheduler.scala 66:25]
  wire  directory_io_write_ready; // @[Scheduler.scala 66:25]
  wire  directory_io_write_valid; // @[Scheduler.scala 66:25]
  wire [1:0] directory_io_write_bits_set; // @[Scheduler.scala 66:25]
  wire  directory_io_write_bits_way; // @[Scheduler.scala 66:25]
  wire  directory_io_write_bits_data_dirty; // @[Scheduler.scala 66:25]
  wire [1:0] directory_io_write_bits_data_state; // @[Scheduler.scala 66:25]
  wire  directory_io_write_bits_data_clients; // @[Scheduler.scala 66:25]
  wire [25:0] directory_io_write_bits_data_tag; // @[Scheduler.scala 66:25]
  wire  directory_io_read_valid; // @[Scheduler.scala 66:25]
  wire [1:0] directory_io_read_bits_set; // @[Scheduler.scala 66:25]
  wire [25:0] directory_io_read_bits_tag; // @[Scheduler.scala 66:25]
  wire  directory_io_result_bits_dirty; // @[Scheduler.scala 66:25]
  wire [1:0] directory_io_result_bits_state; // @[Scheduler.scala 66:25]
  wire  directory_io_result_bits_clients; // @[Scheduler.scala 66:25]
  wire [25:0] directory_io_result_bits_tag; // @[Scheduler.scala 66:25]
  wire  directory_io_result_bits_hit; // @[Scheduler.scala 66:25]
  wire  directory_io_result_bits_way; // @[Scheduler.scala 66:25]
  wire  directory_io_ready; // @[Scheduler.scala 66:25]
  wire  bankedStore_clock; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkC_adr_valid; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkC_adr_bits_noop; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkC_adr_bits_way; // @[Scheduler.scala 67:27]
  wire [1:0] bankedStore_io_sinkC_adr_bits_set; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkC_adr_bits_beat; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkC_adr_bits_mask; // @[Scheduler.scala 67:27]
  wire [63:0] bankedStore_io_sinkC_dat_data; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkD_adr_valid; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkD_adr_bits_noop; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkD_adr_bits_way; // @[Scheduler.scala 67:27]
  wire [1:0] bankedStore_io_sinkD_adr_bits_set; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sinkD_adr_bits_beat; // @[Scheduler.scala 67:27]
  wire [63:0] bankedStore_io_sinkD_dat_data; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceC_adr_valid; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceC_adr_bits_way; // @[Scheduler.scala 67:27]
  wire [1:0] bankedStore_io_sourceC_adr_bits_set; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceC_adr_bits_beat; // @[Scheduler.scala 67:27]
  wire [63:0] bankedStore_io_sourceC_dat_data; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_radr_valid; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_radr_bits_way; // @[Scheduler.scala 67:27]
  wire [1:0] bankedStore_io_sourceD_radr_bits_set; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_radr_bits_beat; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_radr_bits_mask; // @[Scheduler.scala 67:27]
  wire [63:0] bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_wadr_valid; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_wadr_bits_way; // @[Scheduler.scala 67:27]
  wire [1:0] bankedStore_io_sourceD_wadr_bits_set; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_wadr_bits_beat; // @[Scheduler.scala 67:27]
  wire  bankedStore_io_sourceD_wadr_bits_mask; // @[Scheduler.scala 67:27]
  wire [63:0] bankedStore_io_sourceD_wdat_data; // @[Scheduler.scala 67:27]
  wire  requests_clock; // @[Scheduler.scala 68:24]
  wire  requests_reset; // @[Scheduler.scala 68:24]
  wire  requests_io_push_ready; // @[Scheduler.scala 68:24]
  wire  requests_io_push_valid; // @[Scheduler.scala 68:24]
  wire [6:0] requests_io_push_bits_index; // @[Scheduler.scala 68:24]
  wire  requests_io_push_bits_data_prio_0; // @[Scheduler.scala 68:24]
  wire  requests_io_push_bits_data_prio_2; // @[Scheduler.scala 68:24]
  wire [2:0] requests_io_push_bits_data_opcode; // @[Scheduler.scala 68:24]
  wire [2:0] requests_io_push_bits_data_param; // @[Scheduler.scala 68:24]
  wire [2:0] requests_io_push_bits_data_size; // @[Scheduler.scala 68:24]
  wire [2:0] requests_io_push_bits_data_source; // @[Scheduler.scala 68:24]
  wire [25:0] requests_io_push_bits_data_tag; // @[Scheduler.scala 68:24]
  wire [3:0] requests_io_push_bits_data_offset; // @[Scheduler.scala 68:24]
  wire [5:0] requests_io_push_bits_data_put; // @[Scheduler.scala 68:24]
  wire [65:0] requests_io_valid; // @[Scheduler.scala 68:24]
  wire  requests_io_pop_valid; // @[Scheduler.scala 68:24]
  wire [6:0] requests_io_pop_bits; // @[Scheduler.scala 68:24]
  wire  requests_io_data_prio_0; // @[Scheduler.scala 68:24]
  wire  requests_io_data_prio_1; // @[Scheduler.scala 68:24]
  wire  requests_io_data_prio_2; // @[Scheduler.scala 68:24]
  wire [2:0] requests_io_data_opcode; // @[Scheduler.scala 68:24]
  wire [2:0] requests_io_data_param; // @[Scheduler.scala 68:24]
  wire [2:0] requests_io_data_size; // @[Scheduler.scala 68:24]
  wire [2:0] requests_io_data_source; // @[Scheduler.scala 68:24]
  wire [25:0] requests_io_data_tag; // @[Scheduler.scala 68:24]
  wire [3:0] requests_io_data_offset; // @[Scheduler.scala 68:24]
  wire [5:0] requests_io_data_put; // @[Scheduler.scala 68:24]
  wire  abc_mshrs_0_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_0_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_0_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_0_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_0_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_0_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_0_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_1_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_1_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_1_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_1_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_1_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_1_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_2_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_2_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_2_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_2_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_2_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_2_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_3_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_3_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_3_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_3_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_3_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_3_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_4_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_4_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_4_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_4_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_4_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_4_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_5_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_5_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_5_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_5_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_5_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_5_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_6_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_6_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_6_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_6_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_6_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_6_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_7_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_7_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_7_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_7_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_7_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_7_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_7_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_7_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_8_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_8_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_8_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_8_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_8_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_8_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_8_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_8_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_9_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_9_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_9_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_9_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_9_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_9_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_9_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_9_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_10_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_10_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_10_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_10_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_10_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_10_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_10_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_10_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_11_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_11_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_11_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_11_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_11_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_11_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_11_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_11_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_12_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_12_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_12_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_12_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_12_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_12_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_12_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_12_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_13_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_13_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_13_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_13_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_13_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_13_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_13_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_13_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_14_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_14_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_14_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_14_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_14_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_14_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_14_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_14_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_15_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_15_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_15_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_15_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_15_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_15_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_15_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_15_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_16_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_16_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_16_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_16_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_16_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_16_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_16_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_16_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_17_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_17_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_17_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_17_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_17_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_17_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_17_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_17_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_18_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_18_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_18_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_18_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_18_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_18_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_18_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_18_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_clock; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_reset; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_19_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_19_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] abc_mshrs_19_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] abc_mshrs_19_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] abc_mshrs_19_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] abc_mshrs_19_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] abc_mshrs_19_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  abc_mshrs_19_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  bc_mshr_clock; // @[Scheduler.scala 69:46]
  wire  bc_mshr_reset; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] bc_mshr_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] bc_mshr_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] bc_mshr_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] bc_mshr_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] bc_mshr_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] bc_mshr_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] bc_mshr_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  bc_mshr_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  c_mshr_clock; // @[Scheduler.scala 69:46]
  wire  c_mshr_reset; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_allocate_valid; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_allocate_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_allocate_bits_prio_1; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_allocate_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_allocate_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_allocate_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_allocate_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_allocate_bits_source; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_allocate_bits_tag; // @[Scheduler.scala 69:46]
  wire [3:0] c_mshr_io_allocate_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] c_mshr_io_allocate_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_allocate_bits_set; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_allocate_bits_repeat; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_directory_valid; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_directory_bits_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_directory_bits_state; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_directory_bits_clients; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_directory_bits_tag; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_directory_bits_hit; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_directory_bits_way; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_status_valid; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_status_bits_set; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_status_bits_tag; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_status_bits_way; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_status_bits_blockB; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_status_bits_nestB; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_status_bits_blockC; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_status_bits_nestC; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_ready; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_valid; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_a_valid; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_schedule_bits_a_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_schedule_bits_a_bits_set; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_a_bits_param; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_a_bits_block; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_b_valid; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_b_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_schedule_bits_b_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_schedule_bits_b_bits_set; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_b_bits_clients; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_c_valid; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_c_bits_param; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_schedule_bits_c_bits_tag; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_schedule_bits_c_bits_set; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_c_bits_way; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_d_valid; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_d_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_d_bits_size; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_d_bits_source; // @[Scheduler.scala 69:46]
  wire [3:0] c_mshr_io_schedule_bits_d_bits_offset; // @[Scheduler.scala 69:46]
  wire [5:0] c_mshr_io_schedule_bits_d_bits_put; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_schedule_bits_d_bits_set; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_d_bits_way; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_d_bits_bad; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_e_valid; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_schedule_bits_e_bits_sink; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_x_valid; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_schedule_bits_dir_bits_set; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_dir_bits_way; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_schedule_bits_reload; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_sinkc_valid; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_sinkc_bits_last; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_sinkc_bits_tag; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_sinkc_bits_source; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_sinkc_bits_param; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_sinkc_bits_data; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_sinkd_valid; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_sinkd_bits_last; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_sinkd_bits_opcode; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_sinkd_bits_param; // @[Scheduler.scala 69:46]
  wire [2:0] c_mshr_io_sinkd_bits_sink; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_sinkd_bits_denied; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_sinke_valid; // @[Scheduler.scala 69:46]
  wire [1:0] c_mshr_io_nestedwb_set; // @[Scheduler.scala 69:46]
  wire [25:0] c_mshr_io_nestedwb_tag; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_nestedwb_b_toN; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_nestedwb_b_toB; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_nestedwb_b_clr_dirty; // @[Scheduler.scala 69:46]
  wire  c_mshr_io_nestedwb_c_set_dirty; // @[Scheduler.scala 69:46]
  wire  _mshr_stall_abc_T_3 = c_mshr_io_status_valid & abc_mshrs_0_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_0 = bc_mshr_io_status_valid & abc_mshrs_0_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_3; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_7 = c_mshr_io_status_valid & abc_mshrs_1_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_1 = bc_mshr_io_status_valid & abc_mshrs_1_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_7; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_11 = c_mshr_io_status_valid & abc_mshrs_2_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_2 = bc_mshr_io_status_valid & abc_mshrs_2_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_11; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_15 = c_mshr_io_status_valid & abc_mshrs_3_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_3 = bc_mshr_io_status_valid & abc_mshrs_3_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_15; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_19 = c_mshr_io_status_valid & abc_mshrs_4_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_4 = bc_mshr_io_status_valid & abc_mshrs_4_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_19; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_23 = c_mshr_io_status_valid & abc_mshrs_5_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_5 = bc_mshr_io_status_valid & abc_mshrs_5_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_23; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_27 = c_mshr_io_status_valid & abc_mshrs_6_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_6 = bc_mshr_io_status_valid & abc_mshrs_6_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_27; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_31 = c_mshr_io_status_valid & abc_mshrs_7_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_7 = bc_mshr_io_status_valid & abc_mshrs_7_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_31; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_35 = c_mshr_io_status_valid & abc_mshrs_8_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_8 = bc_mshr_io_status_valid & abc_mshrs_8_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_35; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_39 = c_mshr_io_status_valid & abc_mshrs_9_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_9 = bc_mshr_io_status_valid & abc_mshrs_9_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_39; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_43 = c_mshr_io_status_valid & abc_mshrs_10_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_10 = bc_mshr_io_status_valid & abc_mshrs_10_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_43; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_47 = c_mshr_io_status_valid & abc_mshrs_11_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_11 = bc_mshr_io_status_valid & abc_mshrs_11_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_47; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_51 = c_mshr_io_status_valid & abc_mshrs_12_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_12 = bc_mshr_io_status_valid & abc_mshrs_12_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_51; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_55 = c_mshr_io_status_valid & abc_mshrs_13_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_13 = bc_mshr_io_status_valid & abc_mshrs_13_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_55; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_59 = c_mshr_io_status_valid & abc_mshrs_14_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_14 = bc_mshr_io_status_valid & abc_mshrs_14_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_59; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_63 = c_mshr_io_status_valid & abc_mshrs_15_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_15 = bc_mshr_io_status_valid & abc_mshrs_15_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_63; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_67 = c_mshr_io_status_valid & abc_mshrs_16_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_16 = bc_mshr_io_status_valid & abc_mshrs_16_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_67; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_71 = c_mshr_io_status_valid & abc_mshrs_17_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_17 = bc_mshr_io_status_valid & abc_mshrs_17_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_71; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_75 = c_mshr_io_status_valid & abc_mshrs_18_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_18 = bc_mshr_io_status_valid & abc_mshrs_18_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_75; // @[Scheduler.scala 88:86]
  wire  _mshr_stall_abc_T_79 = c_mshr_io_status_valid & abc_mshrs_19_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 89:30]
  wire  mshr_stall_19 = bc_mshr_io_status_valid & abc_mshrs_19_io_status_bits_set == bc_mshr_io_status_bits_set |
    _mshr_stall_abc_T_79; // @[Scheduler.scala 88:86]
  wire  mshr_stall_20 = c_mshr_io_status_valid & bc_mshr_io_status_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 92:28]
  wire  _mshr_request_T_3 = sourceA_io_req_ready | ~abc_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_4 = abc_mshrs_0_io_schedule_valid & ~mshr_stall_0 & _mshr_request_T_3; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_6 = sourceB_io_req_ready | ~abc_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_9 = sourceC_io_req_ready | ~abc_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_12 = sourceD_io_req_ready | ~abc_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_15 = sourceE_io_req_ready | ~abc_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_21 = directory_io_write_ready | ~abc_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_22 = _mshr_request_T_16 & _mshr_request_T_21; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_26 = sourceA_io_req_ready | ~abc_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_27 = abc_mshrs_1_io_schedule_valid & ~mshr_stall_1 & _mshr_request_T_26; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_29 = sourceB_io_req_ready | ~abc_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_32 = sourceC_io_req_ready | ~abc_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_35 = sourceD_io_req_ready | ~abc_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_38 = sourceE_io_req_ready | ~abc_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_44 = directory_io_write_ready | ~abc_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_45 = _mshr_request_T_39 & _mshr_request_T_44; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_49 = sourceA_io_req_ready | ~abc_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_50 = abc_mshrs_2_io_schedule_valid & ~mshr_stall_2 & _mshr_request_T_49; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_52 = sourceB_io_req_ready | ~abc_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_55 = sourceC_io_req_ready | ~abc_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_58 = sourceD_io_req_ready | ~abc_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_61 = sourceE_io_req_ready | ~abc_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_67 = directory_io_write_ready | ~abc_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_68 = _mshr_request_T_62 & _mshr_request_T_67; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_72 = sourceA_io_req_ready | ~abc_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_73 = abc_mshrs_3_io_schedule_valid & ~mshr_stall_3 & _mshr_request_T_72; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_75 = sourceB_io_req_ready | ~abc_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_78 = sourceC_io_req_ready | ~abc_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_81 = sourceD_io_req_ready | ~abc_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_84 = sourceE_io_req_ready | ~abc_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_90 = directory_io_write_ready | ~abc_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_91 = _mshr_request_T_85 & _mshr_request_T_90; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_95 = sourceA_io_req_ready | ~abc_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_96 = abc_mshrs_4_io_schedule_valid & ~mshr_stall_4 & _mshr_request_T_95; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_98 = sourceB_io_req_ready | ~abc_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_101 = sourceC_io_req_ready | ~abc_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_104 = sourceD_io_req_ready | ~abc_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_107 = sourceE_io_req_ready | ~abc_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_113 = directory_io_write_ready | ~abc_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_114 = _mshr_request_T_108 & _mshr_request_T_113; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_118 = sourceA_io_req_ready | ~abc_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_119 = abc_mshrs_5_io_schedule_valid & ~mshr_stall_5 & _mshr_request_T_118; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_121 = sourceB_io_req_ready | ~abc_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_124 = sourceC_io_req_ready | ~abc_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_127 = sourceD_io_req_ready | ~abc_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_130 = sourceE_io_req_ready | ~abc_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_136 = directory_io_write_ready | ~abc_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_137 = _mshr_request_T_131 & _mshr_request_T_136; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_141 = sourceA_io_req_ready | ~abc_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_142 = abc_mshrs_6_io_schedule_valid & ~mshr_stall_6 & _mshr_request_T_141; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_144 = sourceB_io_req_ready | ~abc_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_147 = sourceC_io_req_ready | ~abc_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_150 = sourceD_io_req_ready | ~abc_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_153 = sourceE_io_req_ready | ~abc_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_159 = directory_io_write_ready | ~abc_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_160 = _mshr_request_T_154 & _mshr_request_T_159; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_164 = sourceA_io_req_ready | ~abc_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_165 = abc_mshrs_7_io_schedule_valid & ~mshr_stall_7 & _mshr_request_T_164; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_167 = sourceB_io_req_ready | ~abc_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_168 = _mshr_request_T_165 & _mshr_request_T_167; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_170 = sourceC_io_req_ready | ~abc_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_171 = _mshr_request_T_168 & _mshr_request_T_170; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_173 = sourceD_io_req_ready | ~abc_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_174 = _mshr_request_T_171 & _mshr_request_T_173; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_176 = sourceE_io_req_ready | ~abc_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_177 = _mshr_request_T_174 & _mshr_request_T_176; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_182 = directory_io_write_ready | ~abc_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_183 = _mshr_request_T_177 & _mshr_request_T_182; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_187 = sourceA_io_req_ready | ~abc_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_188 = abc_mshrs_8_io_schedule_valid & ~mshr_stall_8 & _mshr_request_T_187; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_190 = sourceB_io_req_ready | ~abc_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_191 = _mshr_request_T_188 & _mshr_request_T_190; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_193 = sourceC_io_req_ready | ~abc_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_194 = _mshr_request_T_191 & _mshr_request_T_193; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_196 = sourceD_io_req_ready | ~abc_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_197 = _mshr_request_T_194 & _mshr_request_T_196; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_199 = sourceE_io_req_ready | ~abc_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_200 = _mshr_request_T_197 & _mshr_request_T_199; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_205 = directory_io_write_ready | ~abc_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_206 = _mshr_request_T_200 & _mshr_request_T_205; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_210 = sourceA_io_req_ready | ~abc_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_211 = abc_mshrs_9_io_schedule_valid & ~mshr_stall_9 & _mshr_request_T_210; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_213 = sourceB_io_req_ready | ~abc_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_214 = _mshr_request_T_211 & _mshr_request_T_213; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_216 = sourceC_io_req_ready | ~abc_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_217 = _mshr_request_T_214 & _mshr_request_T_216; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_219 = sourceD_io_req_ready | ~abc_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_220 = _mshr_request_T_217 & _mshr_request_T_219; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_222 = sourceE_io_req_ready | ~abc_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_223 = _mshr_request_T_220 & _mshr_request_T_222; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_228 = directory_io_write_ready | ~abc_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_229 = _mshr_request_T_223 & _mshr_request_T_228; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_233 = sourceA_io_req_ready | ~abc_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_234 = abc_mshrs_10_io_schedule_valid & ~mshr_stall_10 & _mshr_request_T_233; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_236 = sourceB_io_req_ready | ~abc_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_237 = _mshr_request_T_234 & _mshr_request_T_236; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_239 = sourceC_io_req_ready | ~abc_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_240 = _mshr_request_T_237 & _mshr_request_T_239; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_242 = sourceD_io_req_ready | ~abc_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_243 = _mshr_request_T_240 & _mshr_request_T_242; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_245 = sourceE_io_req_ready | ~abc_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_246 = _mshr_request_T_243 & _mshr_request_T_245; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_251 = directory_io_write_ready | ~abc_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_252 = _mshr_request_T_246 & _mshr_request_T_251; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_256 = sourceA_io_req_ready | ~abc_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_257 = abc_mshrs_11_io_schedule_valid & ~mshr_stall_11 & _mshr_request_T_256; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_259 = sourceB_io_req_ready | ~abc_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_260 = _mshr_request_T_257 & _mshr_request_T_259; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_262 = sourceC_io_req_ready | ~abc_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_263 = _mshr_request_T_260 & _mshr_request_T_262; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_265 = sourceD_io_req_ready | ~abc_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_266 = _mshr_request_T_263 & _mshr_request_T_265; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_268 = sourceE_io_req_ready | ~abc_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_269 = _mshr_request_T_266 & _mshr_request_T_268; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_274 = directory_io_write_ready | ~abc_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_275 = _mshr_request_T_269 & _mshr_request_T_274; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_279 = sourceA_io_req_ready | ~abc_mshrs_12_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_280 = abc_mshrs_12_io_schedule_valid & ~mshr_stall_12 & _mshr_request_T_279; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_282 = sourceB_io_req_ready | ~abc_mshrs_12_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_283 = _mshr_request_T_280 & _mshr_request_T_282; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_285 = sourceC_io_req_ready | ~abc_mshrs_12_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_286 = _mshr_request_T_283 & _mshr_request_T_285; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_288 = sourceD_io_req_ready | ~abc_mshrs_12_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_289 = _mshr_request_T_286 & _mshr_request_T_288; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_291 = sourceE_io_req_ready | ~abc_mshrs_12_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_292 = _mshr_request_T_289 & _mshr_request_T_291; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_297 = directory_io_write_ready | ~abc_mshrs_12_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_298 = _mshr_request_T_292 & _mshr_request_T_297; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_302 = sourceA_io_req_ready | ~abc_mshrs_13_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_303 = abc_mshrs_13_io_schedule_valid & ~mshr_stall_13 & _mshr_request_T_302; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_305 = sourceB_io_req_ready | ~abc_mshrs_13_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_306 = _mshr_request_T_303 & _mshr_request_T_305; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_308 = sourceC_io_req_ready | ~abc_mshrs_13_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_309 = _mshr_request_T_306 & _mshr_request_T_308; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_311 = sourceD_io_req_ready | ~abc_mshrs_13_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_312 = _mshr_request_T_309 & _mshr_request_T_311; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_314 = sourceE_io_req_ready | ~abc_mshrs_13_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_315 = _mshr_request_T_312 & _mshr_request_T_314; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_320 = directory_io_write_ready | ~abc_mshrs_13_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_321 = _mshr_request_T_315 & _mshr_request_T_320; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_325 = sourceA_io_req_ready | ~abc_mshrs_14_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_326 = abc_mshrs_14_io_schedule_valid & ~mshr_stall_14 & _mshr_request_T_325; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_328 = sourceB_io_req_ready | ~abc_mshrs_14_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_329 = _mshr_request_T_326 & _mshr_request_T_328; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_331 = sourceC_io_req_ready | ~abc_mshrs_14_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_332 = _mshr_request_T_329 & _mshr_request_T_331; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_334 = sourceD_io_req_ready | ~abc_mshrs_14_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_335 = _mshr_request_T_332 & _mshr_request_T_334; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_337 = sourceE_io_req_ready | ~abc_mshrs_14_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_338 = _mshr_request_T_335 & _mshr_request_T_337; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_343 = directory_io_write_ready | ~abc_mshrs_14_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_344 = _mshr_request_T_338 & _mshr_request_T_343; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_348 = sourceA_io_req_ready | ~abc_mshrs_15_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_349 = abc_mshrs_15_io_schedule_valid & ~mshr_stall_15 & _mshr_request_T_348; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_351 = sourceB_io_req_ready | ~abc_mshrs_15_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_352 = _mshr_request_T_349 & _mshr_request_T_351; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_354 = sourceC_io_req_ready | ~abc_mshrs_15_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_355 = _mshr_request_T_352 & _mshr_request_T_354; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_357 = sourceD_io_req_ready | ~abc_mshrs_15_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_358 = _mshr_request_T_355 & _mshr_request_T_357; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_360 = sourceE_io_req_ready | ~abc_mshrs_15_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_361 = _mshr_request_T_358 & _mshr_request_T_360; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_366 = directory_io_write_ready | ~abc_mshrs_15_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_367 = _mshr_request_T_361 & _mshr_request_T_366; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_371 = sourceA_io_req_ready | ~abc_mshrs_16_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_372 = abc_mshrs_16_io_schedule_valid & ~mshr_stall_16 & _mshr_request_T_371; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_374 = sourceB_io_req_ready | ~abc_mshrs_16_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_375 = _mshr_request_T_372 & _mshr_request_T_374; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_377 = sourceC_io_req_ready | ~abc_mshrs_16_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_378 = _mshr_request_T_375 & _mshr_request_T_377; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_380 = sourceD_io_req_ready | ~abc_mshrs_16_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_381 = _mshr_request_T_378 & _mshr_request_T_380; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_383 = sourceE_io_req_ready | ~abc_mshrs_16_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_384 = _mshr_request_T_381 & _mshr_request_T_383; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_389 = directory_io_write_ready | ~abc_mshrs_16_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_390 = _mshr_request_T_384 & _mshr_request_T_389; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_394 = sourceA_io_req_ready | ~abc_mshrs_17_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_395 = abc_mshrs_17_io_schedule_valid & ~mshr_stall_17 & _mshr_request_T_394; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_397 = sourceB_io_req_ready | ~abc_mshrs_17_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_398 = _mshr_request_T_395 & _mshr_request_T_397; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_400 = sourceC_io_req_ready | ~abc_mshrs_17_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_401 = _mshr_request_T_398 & _mshr_request_T_400; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_403 = sourceD_io_req_ready | ~abc_mshrs_17_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_404 = _mshr_request_T_401 & _mshr_request_T_403; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_406 = sourceE_io_req_ready | ~abc_mshrs_17_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_407 = _mshr_request_T_404 & _mshr_request_T_406; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_412 = directory_io_write_ready | ~abc_mshrs_17_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_413 = _mshr_request_T_407 & _mshr_request_T_412; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_417 = sourceA_io_req_ready | ~abc_mshrs_18_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_418 = abc_mshrs_18_io_schedule_valid & ~mshr_stall_18 & _mshr_request_T_417; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_420 = sourceB_io_req_ready | ~abc_mshrs_18_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_421 = _mshr_request_T_418 & _mshr_request_T_420; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_423 = sourceC_io_req_ready | ~abc_mshrs_18_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_424 = _mshr_request_T_421 & _mshr_request_T_423; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_426 = sourceD_io_req_ready | ~abc_mshrs_18_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_427 = _mshr_request_T_424 & _mshr_request_T_426; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_429 = sourceE_io_req_ready | ~abc_mshrs_18_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_430 = _mshr_request_T_427 & _mshr_request_T_429; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_435 = directory_io_write_ready | ~abc_mshrs_18_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_436 = _mshr_request_T_430 & _mshr_request_T_435; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_440 = sourceA_io_req_ready | ~abc_mshrs_19_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_441 = abc_mshrs_19_io_schedule_valid & ~mshr_stall_19 & _mshr_request_T_440; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_443 = sourceB_io_req_ready | ~abc_mshrs_19_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_444 = _mshr_request_T_441 & _mshr_request_T_443; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_446 = sourceC_io_req_ready | ~abc_mshrs_19_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_447 = _mshr_request_T_444 & _mshr_request_T_446; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_449 = sourceD_io_req_ready | ~abc_mshrs_19_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_450 = _mshr_request_T_447 & _mshr_request_T_449; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_452 = sourceE_io_req_ready | ~abc_mshrs_19_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_453 = _mshr_request_T_450 & _mshr_request_T_452; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_458 = directory_io_write_ready | ~abc_mshrs_19_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_459 = _mshr_request_T_453 & _mshr_request_T_458; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_463 = sourceA_io_req_ready | ~bc_mshr_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_464 = bc_mshr_io_schedule_valid & ~mshr_stall_20 & _mshr_request_T_463; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_466 = sourceB_io_req_ready | ~bc_mshr_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_467 = _mshr_request_T_464 & _mshr_request_T_466; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_469 = sourceC_io_req_ready | ~bc_mshr_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_470 = _mshr_request_T_467 & _mshr_request_T_469; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_472 = sourceD_io_req_ready | ~bc_mshr_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_473 = _mshr_request_T_470 & _mshr_request_T_472; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_475 = sourceE_io_req_ready | ~bc_mshr_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_476 = _mshr_request_T_473 & _mshr_request_T_475; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_481 = directory_io_write_ready | ~bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_482 = _mshr_request_T_476 & _mshr_request_T_481; // @[Scheduler.scala 111:61]
  wire  _mshr_request_T_486 = sourceA_io_req_ready | ~c_mshr_io_schedule_bits_a_valid; // @[Scheduler.scala 106:29]
  wire  _mshr_request_T_487 = c_mshr_io_schedule_valid & _mshr_request_T_486; // @[Scheduler.scala 105:31]
  wire  _mshr_request_T_489 = sourceB_io_req_ready | ~c_mshr_io_schedule_bits_b_valid; // @[Scheduler.scala 107:29]
  wire  _mshr_request_T_490 = _mshr_request_T_487 & _mshr_request_T_489; // @[Scheduler.scala 106:61]
  wire  _mshr_request_T_492 = sourceC_io_req_ready | ~c_mshr_io_schedule_bits_c_valid; // @[Scheduler.scala 108:29]
  wire  _mshr_request_T_493 = _mshr_request_T_490 & _mshr_request_T_492; // @[Scheduler.scala 107:61]
  wire  _mshr_request_T_495 = sourceD_io_req_ready | ~c_mshr_io_schedule_bits_d_valid; // @[Scheduler.scala 109:29]
  wire  _mshr_request_T_496 = _mshr_request_T_493 & _mshr_request_T_495; // @[Scheduler.scala 108:61]
  wire  _mshr_request_T_498 = sourceE_io_req_ready | ~c_mshr_io_schedule_bits_e_valid; // @[Scheduler.scala 110:29]
  wire  _mshr_request_T_499 = _mshr_request_T_496 & _mshr_request_T_498; // @[Scheduler.scala 109:61]
  wire  _mshr_request_T_504 = directory_io_write_ready | ~c_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 112:33]
  wire  _mshr_request_T_505 = _mshr_request_T_499 & _mshr_request_T_504; // @[Scheduler.scala 111:61]
  wire [4:0] mshr_request_lo_lo = {_mshr_request_T_114,_mshr_request_T_91,_mshr_request_T_68,_mshr_request_T_45,
    _mshr_request_T_22}; // @[Cat.scala 33:92]
  wire [10:0] mshr_request_lo = {_mshr_request_T_252,_mshr_request_T_229,_mshr_request_T_206,_mshr_request_T_183,
    _mshr_request_T_160,_mshr_request_T_137,mshr_request_lo_lo}; // @[Cat.scala 33:92]
  wire [4:0] mshr_request_hi_lo = {_mshr_request_T_367,_mshr_request_T_344,_mshr_request_T_321,_mshr_request_T_298,
    _mshr_request_T_275}; // @[Cat.scala 33:92]
  wire [21:0] mshr_request = {_mshr_request_T_505,_mshr_request_T_482,_mshr_request_T_459,_mshr_request_T_436,
    _mshr_request_T_413,_mshr_request_T_390,mshr_request_hi_lo,mshr_request_lo}; // @[Cat.scala 33:92]
  reg [21:0] robin_filter; // @[Scheduler.scala 116:29]
  wire [21:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala 117:54]
  wire [43:0] robin_request = {_mshr_request_T_505,_mshr_request_T_482,_mshr_request_T_459,_mshr_request_T_436,
    _mshr_request_T_413,_mshr_request_T_390,mshr_request_hi_lo,mshr_request_lo,_robin_request_T}; // @[Cat.scala 33:92]
  wire [44:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala 244:48]
  wire [43:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T[43:0]; // @[package.scala 244:43]
  wire [45:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala 244:48]
  wire [43:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_3[43:0]; // @[package.scala 244:43]
  wire [47:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala 244:48]
  wire [43:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_6[43:0]; // @[package.scala 244:43]
  wire [51:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala 244:48]
  wire [43:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_9[43:0]; // @[package.scala 244:43]
  wire [59:0] _mshr_selectOH2_T_12 = {_mshr_selectOH2_T_11, 16'h0}; // @[package.scala 244:48]
  wire [43:0] _mshr_selectOH2_T_14 = _mshr_selectOH2_T_11 | _mshr_selectOH2_T_12[43:0]; // @[package.scala 244:43]
  wire [75:0] _mshr_selectOH2_T_15 = {_mshr_selectOH2_T_14, 32'h0}; // @[package.scala 244:48]
  wire [43:0] _mshr_selectOH2_T_17 = _mshr_selectOH2_T_14 | _mshr_selectOH2_T_15[43:0]; // @[package.scala 244:43]
  wire [44:0] _mshr_selectOH2_T_19 = {_mshr_selectOH2_T_17, 1'h0}; // @[Scheduler.scala 118:48]
  wire [44:0] _mshr_selectOH2_T_20 = ~_mshr_selectOH2_T_19; // @[Scheduler.scala 118:24]
  wire [44:0] _GEN_282 = {{1'd0}, robin_request}; // @[Scheduler.scala 118:54]
  wire [44:0] mshr_selectOH2 = _mshr_selectOH2_T_20 & _GEN_282; // @[Scheduler.scala 118:54]
  wire [21:0] mshr_selectOH = mshr_selectOH2[43:22] | mshr_selectOH2[21:0]; // @[Scheduler.scala 119:70]
  wire [5:0] mshr_select_hi = mshr_selectOH[21:16]; // @[OneHot.scala 30:18]
  wire [15:0] mshr_select_lo = mshr_selectOH[15:0]; // @[OneHot.scala 31:18]
  wire  _mshr_select_T = |mshr_select_hi; // @[OneHot.scala 32:14]
  wire [15:0] _GEN_296 = {{10'd0}, mshr_select_hi}; // @[OneHot.scala 32:28]
  wire [15:0] _mshr_select_T_1 = _GEN_296 | mshr_select_lo; // @[OneHot.scala 32:28]
  wire [7:0] mshr_select_hi_1 = _mshr_select_T_1[15:8]; // @[OneHot.scala 30:18]
  wire [7:0] mshr_select_lo_1 = _mshr_select_T_1[7:0]; // @[OneHot.scala 31:18]
  wire  _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala 32:14]
  wire [7:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala 32:28]
  wire [3:0] mshr_select_hi_2 = _mshr_select_T_3[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] mshr_select_lo_2 = _mshr_select_T_3[3:0]; // @[OneHot.scala 31:18]
  wire  _mshr_select_T_4 = |mshr_select_hi_2; // @[OneHot.scala 32:14]
  wire [3:0] _mshr_select_T_5 = mshr_select_hi_2 | mshr_select_lo_2; // @[OneHot.scala 32:28]
  wire [1:0] mshr_select_hi_3 = _mshr_select_T_5[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] mshr_select_lo_3 = _mshr_select_T_5[1:0]; // @[OneHot.scala 31:18]
  wire  _mshr_select_T_6 = |mshr_select_hi_3; // @[OneHot.scala 32:14]
  wire [1:0] _mshr_select_T_7 = mshr_select_hi_3 | mshr_select_lo_3; // @[OneHot.scala 32:28]
  wire [3:0] _mshr_select_T_11 = {_mshr_select_T_2,_mshr_select_T_4,_mshr_select_T_6,_mshr_select_T_7[1]}; // @[Cat.scala 33:92]
  wire [4:0] mshr_select = {_mshr_select_T,_mshr_select_T_2,_mshr_select_T_4,_mshr_select_T_6,_mshr_select_T_7[1]}; // @[Cat.scala 33:92]
  wire  _schedule_T_37 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_reload; // @[Mux.scala 27:73]
  wire  _schedule_T_58 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_reload | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_reload | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_reload | mshr_selectOH[3] &
    abc_mshrs_3_io_schedule_bits_reload | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_reload | mshr_selectOH[5] &
    abc_mshrs_5_io_schedule_bits_reload | mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_reload | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_reload | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_reload | mshr_selectOH[9] &
    abc_mshrs_9_io_schedule_bits_reload | mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_reload | mshr_selectOH[11]
     & abc_mshrs_11_io_schedule_bits_reload | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_reload | mshr_selectOH[
    13] & abc_mshrs_13_io_schedule_bits_reload | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_reload |
    _schedule_T_37; // @[Mux.scala 27:73]
  wire  schedule_reload = _schedule_T_58 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_reload | mshr_selectOH[17]
     & abc_mshrs_17_io_schedule_bits_reload | mshr_selectOH[18] & abc_mshrs_18_io_schedule_bits_reload | mshr_selectOH[
    19] & abc_mshrs_19_io_schedule_bits_reload | mshr_selectOH[20] & bc_mshr_io_schedule_bits_reload | mshr_selectOH[21]
     & c_mshr_io_schedule_bits_reload; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_65 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_66 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_67 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_68 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_69 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_70 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_71 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_72 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_73 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_74 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_75 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_76 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_77 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_78 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_79 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_80 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_81 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_82 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_83 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_84 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_85 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_86 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_dir_bits_data_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_87 = _schedule_T_65 | _schedule_T_66; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_88 = _schedule_T_87 | _schedule_T_67; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_89 = _schedule_T_88 | _schedule_T_68; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_90 = _schedule_T_89 | _schedule_T_69; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_91 = _schedule_T_90 | _schedule_T_70; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_92 = _schedule_T_91 | _schedule_T_71; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_93 = _schedule_T_92 | _schedule_T_72; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_73; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_74; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_75; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_76; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_98 = _schedule_T_97 | _schedule_T_77; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_99 = _schedule_T_98 | _schedule_T_78; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_100 = _schedule_T_99 | _schedule_T_79; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_101 = _schedule_T_100 | _schedule_T_80; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_102 = _schedule_T_101 | _schedule_T_81; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_103 = _schedule_T_102 | _schedule_T_82; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_104 = _schedule_T_103 | _schedule_T_83; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_105 = _schedule_T_104 | _schedule_T_84; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_106 = _schedule_T_105 | _schedule_T_85; // @[Mux.scala 27:73]
  wire  _schedule_T_123 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala 27:73]
  wire  _schedule_T_144 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[2] &
    abc_mshrs_2_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[3] &
    abc_mshrs_3_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[4] &
    abc_mshrs_4_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[5] &
    abc_mshrs_5_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[6] &
    abc_mshrs_6_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[8] &
    abc_mshrs_8_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[9] &
    abc_mshrs_9_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[10] &
    abc_mshrs_10_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[11] &
    abc_mshrs_11_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[12] &
    abc_mshrs_12_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[13] &
    abc_mshrs_13_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[14] &
    abc_mshrs_14_io_schedule_bits_dir_bits_data_clients | _schedule_T_123; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_151 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_152 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_153 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_154 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_155 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_156 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_157 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_158 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_159 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_160 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_161 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_162 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_163 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_164 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_165 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_166 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_167 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_168 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_169 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_170 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_171 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_172 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_173 = _schedule_T_151 | _schedule_T_152; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_174 = _schedule_T_173 | _schedule_T_153; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_175 = _schedule_T_174 | _schedule_T_154; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_176 = _schedule_T_175 | _schedule_T_155; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_177 = _schedule_T_176 | _schedule_T_156; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_178 = _schedule_T_177 | _schedule_T_157; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_179 = _schedule_T_178 | _schedule_T_158; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_180 = _schedule_T_179 | _schedule_T_159; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_181 = _schedule_T_180 | _schedule_T_160; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_182 = _schedule_T_181 | _schedule_T_161; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_183 = _schedule_T_182 | _schedule_T_162; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_184 = _schedule_T_183 | _schedule_T_163; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_185 = _schedule_T_184 | _schedule_T_164; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_186 = _schedule_T_185 | _schedule_T_165; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_187 = _schedule_T_186 | _schedule_T_166; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_188 = _schedule_T_187 | _schedule_T_167; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_189 = _schedule_T_188 | _schedule_T_168; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_190 = _schedule_T_189 | _schedule_T_169; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_191 = _schedule_T_190 | _schedule_T_170; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_192 = _schedule_T_191 | _schedule_T_171; // @[Mux.scala 27:73]
  wire  _schedule_T_209 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala 27:73]
  wire  _schedule_T_230 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[2] &
    abc_mshrs_2_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[3] &
    abc_mshrs_3_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[4] &
    abc_mshrs_4_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[5] &
    abc_mshrs_5_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[6] &
    abc_mshrs_6_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[8] &
    abc_mshrs_8_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[9] &
    abc_mshrs_9_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[10] &
    abc_mshrs_10_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[11] &
    abc_mshrs_11_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[12] &
    abc_mshrs_12_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[13] &
    abc_mshrs_13_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[14] &
    abc_mshrs_14_io_schedule_bits_dir_bits_data_dirty | _schedule_T_209; // @[Mux.scala 27:73]
  wire  _schedule_T_252 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_dir_bits_way; // @[Mux.scala 27:73]
  wire  _schedule_T_273 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_dir_bits_way | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_dir_bits_way | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_dir_bits_way |
    mshr_selectOH[3] & abc_mshrs_3_io_schedule_bits_dir_bits_way | mshr_selectOH[4] &
    abc_mshrs_4_io_schedule_bits_dir_bits_way | mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_dir_bits_way |
    mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_dir_bits_way | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_dir_bits_way | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_dir_bits_way |
    mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_dir_bits_way | mshr_selectOH[10] &
    abc_mshrs_10_io_schedule_bits_dir_bits_way | mshr_selectOH[11] & abc_mshrs_11_io_schedule_bits_dir_bits_way |
    mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_dir_bits_way | mshr_selectOH[13] &
    abc_mshrs_13_io_schedule_bits_dir_bits_way | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_dir_bits_way |
    _schedule_T_252; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_280 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_281 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_282 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_283 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_284 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_285 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_286 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_287 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_288 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_289 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_290 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_291 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_292 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_293 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_294 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_295 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_296 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_297 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_298 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_299 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_300 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_301 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_dir_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_302 = _schedule_T_280 | _schedule_T_281; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_303 = _schedule_T_302 | _schedule_T_282; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_304 = _schedule_T_303 | _schedule_T_283; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_305 = _schedule_T_304 | _schedule_T_284; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_306 = _schedule_T_305 | _schedule_T_285; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_307 = _schedule_T_306 | _schedule_T_286; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_308 = _schedule_T_307 | _schedule_T_287; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_309 = _schedule_T_308 | _schedule_T_288; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_310 = _schedule_T_309 | _schedule_T_289; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_311 = _schedule_T_310 | _schedule_T_290; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_312 = _schedule_T_311 | _schedule_T_291; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_313 = _schedule_T_312 | _schedule_T_292; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_314 = _schedule_T_313 | _schedule_T_293; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_315 = _schedule_T_314 | _schedule_T_294; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_316 = _schedule_T_315 | _schedule_T_295; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_317 = _schedule_T_316 | _schedule_T_296; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_318 = _schedule_T_317 | _schedule_T_297; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_319 = _schedule_T_318 | _schedule_T_298; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_320 = _schedule_T_319 | _schedule_T_299; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_321 = _schedule_T_320 | _schedule_T_300; // @[Mux.scala 27:73]
  wire  _schedule_T_338 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_dir_valid; // @[Mux.scala 27:73]
  wire  _schedule_T_343 = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Mux.scala 27:73]
  wire  _schedule_T_344 = mshr_selectOH[21] & c_mshr_io_schedule_bits_dir_valid; // @[Mux.scala 27:73]
  wire  _schedule_T_359 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_dir_valid | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_dir_valid | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_dir_valid | mshr_selectOH[3
    ] & abc_mshrs_3_io_schedule_bits_dir_valid | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_dir_valid |
    mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_dir_valid | mshr_selectOH[6] &
    abc_mshrs_6_io_schedule_bits_dir_valid | mshr_selectOH[7] & abc_mshrs_7_io_schedule_bits_dir_valid | mshr_selectOH[8
    ] & abc_mshrs_8_io_schedule_bits_dir_valid | mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_dir_valid |
    mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_dir_valid | mshr_selectOH[11] &
    abc_mshrs_11_io_schedule_bits_dir_valid | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_dir_valid |
    mshr_selectOH[13] & abc_mshrs_13_io_schedule_bits_dir_valid | mshr_selectOH[14] &
    abc_mshrs_14_io_schedule_bits_dir_valid | _schedule_T_338; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_452 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_453 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_454 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_455 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_456 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_457 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_458 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_459 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_460 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_461 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_462 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_463 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_464 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_465 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_466 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_467 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_468 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_469 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_470 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_471 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_472 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_473 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_474 = _schedule_T_452 | _schedule_T_453; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_475 = _schedule_T_474 | _schedule_T_454; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_476 = _schedule_T_475 | _schedule_T_455; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_477 = _schedule_T_476 | _schedule_T_456; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_478 = _schedule_T_477 | _schedule_T_457; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_479 = _schedule_T_478 | _schedule_T_458; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_480 = _schedule_T_479 | _schedule_T_459; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_481 = _schedule_T_480 | _schedule_T_460; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_482 = _schedule_T_481 | _schedule_T_461; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_483 = _schedule_T_482 | _schedule_T_462; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_484 = _schedule_T_483 | _schedule_T_463; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_485 = _schedule_T_484 | _schedule_T_464; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_486 = _schedule_T_485 | _schedule_T_465; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_487 = _schedule_T_486 | _schedule_T_466; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_488 = _schedule_T_487 | _schedule_T_467; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_489 = _schedule_T_488 | _schedule_T_468; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_490 = _schedule_T_489 | _schedule_T_469; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_491 = _schedule_T_490 | _schedule_T_470; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_492 = _schedule_T_491 | _schedule_T_471; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_493 = _schedule_T_492 | _schedule_T_472; // @[Mux.scala 27:73]
  wire  _schedule_T_510 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_e_valid; // @[Mux.scala 27:73]
  wire  _schedule_T_531 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_e_valid | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_e_valid | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_e_valid | mshr_selectOH[3] &
    abc_mshrs_3_io_schedule_bits_e_valid | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_e_valid | mshr_selectOH[5] &
    abc_mshrs_5_io_schedule_bits_e_valid | mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_e_valid | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_e_valid | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_e_valid | mshr_selectOH[9] &
    abc_mshrs_9_io_schedule_bits_e_valid | mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_e_valid | mshr_selectOH[11]
     & abc_mshrs_11_io_schedule_bits_e_valid | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_e_valid | mshr_selectOH
    [13] & abc_mshrs_13_io_schedule_bits_e_valid | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_e_valid |
    _schedule_T_510; // @[Mux.scala 27:73]
  wire  _schedule_T_553 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_d_bits_bad; // @[Mux.scala 27:73]
  wire  _schedule_T_574 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_d_bits_bad | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_d_bits_bad | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_d_bits_bad | mshr_selectOH
    [3] & abc_mshrs_3_io_schedule_bits_d_bits_bad | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_d_bits_bad |
    mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_d_bits_bad | mshr_selectOH[6] &
    abc_mshrs_6_io_schedule_bits_d_bits_bad | mshr_selectOH[7] & abc_mshrs_7_io_schedule_bits_d_bits_bad | mshr_selectOH
    [8] & abc_mshrs_8_io_schedule_bits_d_bits_bad | mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_d_bits_bad |
    mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_d_bits_bad | mshr_selectOH[11] &
    abc_mshrs_11_io_schedule_bits_d_bits_bad | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_d_bits_bad |
    mshr_selectOH[13] & abc_mshrs_13_io_schedule_bits_d_bits_bad | mshr_selectOH[14] &
    abc_mshrs_14_io_schedule_bits_d_bits_bad | _schedule_T_553; // @[Mux.scala 27:73]
  wire  _schedule_T_596 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_d_bits_way; // @[Mux.scala 27:73]
  wire  _schedule_T_617 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_d_bits_way | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_d_bits_way | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_d_bits_way | mshr_selectOH
    [3] & abc_mshrs_3_io_schedule_bits_d_bits_way | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_d_bits_way |
    mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_d_bits_way | mshr_selectOH[6] &
    abc_mshrs_6_io_schedule_bits_d_bits_way | mshr_selectOH[7] & abc_mshrs_7_io_schedule_bits_d_bits_way | mshr_selectOH
    [8] & abc_mshrs_8_io_schedule_bits_d_bits_way | mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_d_bits_way |
    mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_d_bits_way | mshr_selectOH[11] &
    abc_mshrs_11_io_schedule_bits_d_bits_way | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_d_bits_way |
    mshr_selectOH[13] & abc_mshrs_13_io_schedule_bits_d_bits_way | mshr_selectOH[14] &
    abc_mshrs_14_io_schedule_bits_d_bits_way | _schedule_T_596; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_667 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_668 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_669 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_670 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_671 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_672 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_673 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_674 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_675 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_676 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_677 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_678 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_679 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_680 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_681 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_682 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_683 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_684 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_685 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_686 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_687 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_688 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_d_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_689 = _schedule_T_667 | _schedule_T_668; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_690 = _schedule_T_689 | _schedule_T_669; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_691 = _schedule_T_690 | _schedule_T_670; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_692 = _schedule_T_691 | _schedule_T_671; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_693 = _schedule_T_692 | _schedule_T_672; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_694 = _schedule_T_693 | _schedule_T_673; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_695 = _schedule_T_694 | _schedule_T_674; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_696 = _schedule_T_695 | _schedule_T_675; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_697 = _schedule_T_696 | _schedule_T_676; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_698 = _schedule_T_697 | _schedule_T_677; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_699 = _schedule_T_698 | _schedule_T_678; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_700 = _schedule_T_699 | _schedule_T_679; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_701 = _schedule_T_700 | _schedule_T_680; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_702 = _schedule_T_701 | _schedule_T_681; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_703 = _schedule_T_702 | _schedule_T_682; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_704 = _schedule_T_703 | _schedule_T_683; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_705 = _schedule_T_704 | _schedule_T_684; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_706 = _schedule_T_705 | _schedule_T_685; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_707 = _schedule_T_706 | _schedule_T_686; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_708 = _schedule_T_707 | _schedule_T_687; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_710 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_711 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_712 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_713 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_714 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_715 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_716 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_717 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_718 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_719 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_720 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_721 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_722 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_723 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_724 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_725 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_726 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_727 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_728 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_729 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_730 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_731 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_732 = _schedule_T_710 | _schedule_T_711; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_733 = _schedule_T_732 | _schedule_T_712; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_734 = _schedule_T_733 | _schedule_T_713; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_735 = _schedule_T_734 | _schedule_T_714; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_736 = _schedule_T_735 | _schedule_T_715; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_737 = _schedule_T_736 | _schedule_T_716; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_738 = _schedule_T_737 | _schedule_T_717; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_739 = _schedule_T_738 | _schedule_T_718; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_740 = _schedule_T_739 | _schedule_T_719; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_741 = _schedule_T_740 | _schedule_T_720; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_742 = _schedule_T_741 | _schedule_T_721; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_743 = _schedule_T_742 | _schedule_T_722; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_744 = _schedule_T_743 | _schedule_T_723; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_745 = _schedule_T_744 | _schedule_T_724; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_746 = _schedule_T_745 | _schedule_T_725; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_747 = _schedule_T_746 | _schedule_T_726; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_748 = _schedule_T_747 | _schedule_T_727; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_749 = _schedule_T_748 | _schedule_T_728; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_750 = _schedule_T_749 | _schedule_T_729; // @[Mux.scala 27:73]
  wire [5:0] _schedule_T_751 = _schedule_T_750 | _schedule_T_730; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_753 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_754 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_755 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_756 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_757 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_758 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_759 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_760 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_761 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_762 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_763 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_764 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_765 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_766 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_767 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_768 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_769 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_770 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_771 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_772 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_773 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_774 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_d_bits_offset : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_775 = _schedule_T_753 | _schedule_T_754; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_776 = _schedule_T_775 | _schedule_T_755; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_777 = _schedule_T_776 | _schedule_T_756; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_778 = _schedule_T_777 | _schedule_T_757; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_779 = _schedule_T_778 | _schedule_T_758; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_780 = _schedule_T_779 | _schedule_T_759; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_781 = _schedule_T_780 | _schedule_T_760; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_782 = _schedule_T_781 | _schedule_T_761; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_783 = _schedule_T_782 | _schedule_T_762; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_784 = _schedule_T_783 | _schedule_T_763; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_785 = _schedule_T_784 | _schedule_T_764; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_786 = _schedule_T_785 | _schedule_T_765; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_787 = _schedule_T_786 | _schedule_T_766; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_788 = _schedule_T_787 | _schedule_T_767; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_789 = _schedule_T_788 | _schedule_T_768; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_790 = _schedule_T_789 | _schedule_T_769; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_791 = _schedule_T_790 | _schedule_T_770; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_792 = _schedule_T_791 | _schedule_T_771; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_793 = _schedule_T_792 | _schedule_T_772; // @[Mux.scala 27:73]
  wire [3:0] _schedule_T_794 = _schedule_T_793 | _schedule_T_773; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_839 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_840 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_841 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_842 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_843 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_844 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_845 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_846 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_847 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_848 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_849 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_850 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_851 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_852 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_853 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_854 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_855 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_856 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_857 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_858 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_859 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_860 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_d_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_861 = _schedule_T_839 | _schedule_T_840; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_862 = _schedule_T_861 | _schedule_T_841; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_863 = _schedule_T_862 | _schedule_T_842; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_864 = _schedule_T_863 | _schedule_T_843; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_865 = _schedule_T_864 | _schedule_T_844; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_866 = _schedule_T_865 | _schedule_T_845; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_867 = _schedule_T_866 | _schedule_T_846; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_868 = _schedule_T_867 | _schedule_T_847; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_869 = _schedule_T_868 | _schedule_T_848; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_870 = _schedule_T_869 | _schedule_T_849; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_871 = _schedule_T_870 | _schedule_T_850; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_872 = _schedule_T_871 | _schedule_T_851; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_873 = _schedule_T_872 | _schedule_T_852; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_874 = _schedule_T_873 | _schedule_T_853; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_875 = _schedule_T_874 | _schedule_T_854; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_876 = _schedule_T_875 | _schedule_T_855; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_877 = _schedule_T_876 | _schedule_T_856; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_878 = _schedule_T_877 | _schedule_T_857; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_879 = _schedule_T_878 | _schedule_T_858; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_880 = _schedule_T_879 | _schedule_T_859; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_882 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_883 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_884 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_885 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_886 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_887 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_888 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_889 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_890 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_891 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_892 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_893 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_894 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_895 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_896 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_897 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_898 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_899 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_900 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_901 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_902 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_903 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_904 = _schedule_T_882 | _schedule_T_883; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_905 = _schedule_T_904 | _schedule_T_884; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_906 = _schedule_T_905 | _schedule_T_885; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_907 = _schedule_T_906 | _schedule_T_886; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_908 = _schedule_T_907 | _schedule_T_887; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_909 = _schedule_T_908 | _schedule_T_888; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_910 = _schedule_T_909 | _schedule_T_889; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_911 = _schedule_T_910 | _schedule_T_890; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_912 = _schedule_T_911 | _schedule_T_891; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_913 = _schedule_T_912 | _schedule_T_892; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_914 = _schedule_T_913 | _schedule_T_893; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_915 = _schedule_T_914 | _schedule_T_894; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_916 = _schedule_T_915 | _schedule_T_895; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_917 = _schedule_T_916 | _schedule_T_896; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_918 = _schedule_T_917 | _schedule_T_897; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_919 = _schedule_T_918 | _schedule_T_898; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_920 = _schedule_T_919 | _schedule_T_899; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_921 = _schedule_T_920 | _schedule_T_900; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_922 = _schedule_T_921 | _schedule_T_901; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_923 = _schedule_T_922 | _schedule_T_902; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_925 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_926 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_927 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_928 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_929 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_930 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_931 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_932 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_933 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_934 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_935 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_936 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_937 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_938 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_939 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_940 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_941 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_942 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_943 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_944 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_945 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_946 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_947 = _schedule_T_925 | _schedule_T_926; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_948 = _schedule_T_947 | _schedule_T_927; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_949 = _schedule_T_948 | _schedule_T_928; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_950 = _schedule_T_949 | _schedule_T_929; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_951 = _schedule_T_950 | _schedule_T_930; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_952 = _schedule_T_951 | _schedule_T_931; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_953 = _schedule_T_952 | _schedule_T_932; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_954 = _schedule_T_953 | _schedule_T_933; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_955 = _schedule_T_954 | _schedule_T_934; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_956 = _schedule_T_955 | _schedule_T_935; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_957 = _schedule_T_956 | _schedule_T_936; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_958 = _schedule_T_957 | _schedule_T_937; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_959 = _schedule_T_958 | _schedule_T_938; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_960 = _schedule_T_959 | _schedule_T_939; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_961 = _schedule_T_960 | _schedule_T_940; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_962 = _schedule_T_961 | _schedule_T_941; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_963 = _schedule_T_962 | _schedule_T_942; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_964 = _schedule_T_963 | _schedule_T_943; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_965 = _schedule_T_964 | _schedule_T_944; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_966 = _schedule_T_965 | _schedule_T_945; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_968 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_969 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_970 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_971 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_972 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_973 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_974 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_975 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_976 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_977 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_978 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_979 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_980 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_981 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_982 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_983 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_984 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_985 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_986 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_987 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_988 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_989 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_990 = _schedule_T_968 | _schedule_T_969; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_991 = _schedule_T_990 | _schedule_T_970; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_992 = _schedule_T_991 | _schedule_T_971; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_993 = _schedule_T_992 | _schedule_T_972; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_994 = _schedule_T_993 | _schedule_T_973; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_995 = _schedule_T_994 | _schedule_T_974; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_996 = _schedule_T_995 | _schedule_T_975; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_997 = _schedule_T_996 | _schedule_T_976; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_998 = _schedule_T_997 | _schedule_T_977; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_999 = _schedule_T_998 | _schedule_T_978; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1000 = _schedule_T_999 | _schedule_T_979; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1001 = _schedule_T_1000 | _schedule_T_980; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1002 = _schedule_T_1001 | _schedule_T_981; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1003 = _schedule_T_1002 | _schedule_T_982; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1004 = _schedule_T_1003 | _schedule_T_983; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1005 = _schedule_T_1004 | _schedule_T_984; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1006 = _schedule_T_1005 | _schedule_T_985; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1007 = _schedule_T_1006 | _schedule_T_986; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1008 = _schedule_T_1007 | _schedule_T_987; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1009 = _schedule_T_1008 | _schedule_T_988; // @[Mux.scala 27:73]
  wire  _schedule_T_1069 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_d_bits_prio_0; // @[Mux.scala 27:73]
  wire  _schedule_T_1090 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_d_bits_prio_0 |
    mshr_selectOH[3] & abc_mshrs_3_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[4] &
    abc_mshrs_4_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_d_bits_prio_0 |
    mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_d_bits_prio_0 |
    mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[10] &
    abc_mshrs_10_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[11] & abc_mshrs_11_io_schedule_bits_d_bits_prio_0 |
    mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[13] &
    abc_mshrs_13_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_d_bits_prio_0 |
    _schedule_T_1069; // @[Mux.scala 27:73]
  wire  _schedule_T_1155 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_d_bits_prio_2; // @[Mux.scala 27:73]
  wire  _schedule_T_1176 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_d_bits_prio_2 |
    mshr_selectOH[3] & abc_mshrs_3_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[4] &
    abc_mshrs_4_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_d_bits_prio_2 |
    mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_d_bits_prio_2 |
    mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[10] &
    abc_mshrs_10_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[11] & abc_mshrs_11_io_schedule_bits_d_bits_prio_2 |
    mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[13] &
    abc_mshrs_13_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_d_bits_prio_2 |
    _schedule_T_1155; // @[Mux.scala 27:73]
  wire  _schedule_T_1198 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_d_valid; // @[Mux.scala 27:73]
  wire  _schedule_T_1219 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_d_valid | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_d_valid | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_d_valid | mshr_selectOH[3] &
    abc_mshrs_3_io_schedule_bits_d_valid | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_d_valid | mshr_selectOH[5] &
    abc_mshrs_5_io_schedule_bits_d_valid | mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_d_valid | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_d_valid | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_d_valid | mshr_selectOH[9] &
    abc_mshrs_9_io_schedule_bits_d_valid | mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_d_valid | mshr_selectOH[11]
     & abc_mshrs_11_io_schedule_bits_d_valid | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_d_valid | mshr_selectOH
    [13] & abc_mshrs_13_io_schedule_bits_d_valid | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_d_valid |
    _schedule_T_1198; // @[Mux.scala 27:73]
  wire  _schedule_T_1241 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_c_bits_dirty; // @[Mux.scala 27:73]
  wire  _schedule_T_1262 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_c_bits_dirty | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_c_bits_dirty | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_c_bits_dirty |
    mshr_selectOH[3] & abc_mshrs_3_io_schedule_bits_c_bits_dirty | mshr_selectOH[4] &
    abc_mshrs_4_io_schedule_bits_c_bits_dirty | mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_c_bits_dirty |
    mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_c_bits_dirty | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_c_bits_dirty | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_c_bits_dirty |
    mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_c_bits_dirty | mshr_selectOH[10] &
    abc_mshrs_10_io_schedule_bits_c_bits_dirty | mshr_selectOH[11] & abc_mshrs_11_io_schedule_bits_c_bits_dirty |
    mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_c_bits_dirty | mshr_selectOH[13] &
    abc_mshrs_13_io_schedule_bits_c_bits_dirty | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_c_bits_dirty |
    _schedule_T_1241; // @[Mux.scala 27:73]
  wire  _schedule_T_1284 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_c_bits_way; // @[Mux.scala 27:73]
  wire  _schedule_T_1305 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_c_bits_way | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_c_bits_way | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_c_bits_way | mshr_selectOH
    [3] & abc_mshrs_3_io_schedule_bits_c_bits_way | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_c_bits_way |
    mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_c_bits_way | mshr_selectOH[6] &
    abc_mshrs_6_io_schedule_bits_c_bits_way | mshr_selectOH[7] & abc_mshrs_7_io_schedule_bits_c_bits_way | mshr_selectOH
    [8] & abc_mshrs_8_io_schedule_bits_c_bits_way | mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_c_bits_way |
    mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_c_bits_way | mshr_selectOH[11] &
    abc_mshrs_11_io_schedule_bits_c_bits_way | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_c_bits_way |
    mshr_selectOH[13] & abc_mshrs_13_io_schedule_bits_c_bits_way | mshr_selectOH[14] &
    abc_mshrs_14_io_schedule_bits_c_bits_way | _schedule_T_1284; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1312 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1313 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1314 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1315 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1316 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1317 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1318 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1319 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1320 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1321 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1322 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1323 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1324 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1325 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1326 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1327 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1328 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1329 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1330 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1331 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1332 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1333 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_c_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1334 = _schedule_T_1312 | _schedule_T_1313; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1335 = _schedule_T_1334 | _schedule_T_1314; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1336 = _schedule_T_1335 | _schedule_T_1315; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1337 = _schedule_T_1336 | _schedule_T_1316; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1338 = _schedule_T_1337 | _schedule_T_1317; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1339 = _schedule_T_1338 | _schedule_T_1318; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1340 = _schedule_T_1339 | _schedule_T_1319; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1341 = _schedule_T_1340 | _schedule_T_1320; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1342 = _schedule_T_1341 | _schedule_T_1321; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1343 = _schedule_T_1342 | _schedule_T_1322; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1344 = _schedule_T_1343 | _schedule_T_1323; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1345 = _schedule_T_1344 | _schedule_T_1324; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1346 = _schedule_T_1345 | _schedule_T_1325; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1347 = _schedule_T_1346 | _schedule_T_1326; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1348 = _schedule_T_1347 | _schedule_T_1327; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1349 = _schedule_T_1348 | _schedule_T_1328; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1350 = _schedule_T_1349 | _schedule_T_1329; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1351 = _schedule_T_1350 | _schedule_T_1330; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1352 = _schedule_T_1351 | _schedule_T_1331; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1353 = _schedule_T_1352 | _schedule_T_1332; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1355 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1356 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1357 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1358 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1359 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1360 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1361 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1362 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1363 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1364 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1365 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1366 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1367 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1368 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1369 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1370 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1371 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1372 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1373 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1374 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1375 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1376 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_c_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1377 = _schedule_T_1355 | _schedule_T_1356; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1378 = _schedule_T_1377 | _schedule_T_1357; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1379 = _schedule_T_1378 | _schedule_T_1358; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1380 = _schedule_T_1379 | _schedule_T_1359; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1381 = _schedule_T_1380 | _schedule_T_1360; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1382 = _schedule_T_1381 | _schedule_T_1361; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1383 = _schedule_T_1382 | _schedule_T_1362; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1384 = _schedule_T_1383 | _schedule_T_1363; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1385 = _schedule_T_1384 | _schedule_T_1364; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1386 = _schedule_T_1385 | _schedule_T_1365; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1387 = _schedule_T_1386 | _schedule_T_1366; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1388 = _schedule_T_1387 | _schedule_T_1367; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1389 = _schedule_T_1388 | _schedule_T_1368; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1390 = _schedule_T_1389 | _schedule_T_1369; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1391 = _schedule_T_1390 | _schedule_T_1370; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1392 = _schedule_T_1391 | _schedule_T_1371; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1393 = _schedule_T_1392 | _schedule_T_1372; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1394 = _schedule_T_1393 | _schedule_T_1373; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1395 = _schedule_T_1394 | _schedule_T_1374; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1396 = _schedule_T_1395 | _schedule_T_1375; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1441 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1442 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1443 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1444 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1445 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1446 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1447 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1448 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1449 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1450 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1451 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1452 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1453 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1454 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1455 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1456 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1457 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1458 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1459 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1460 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1461 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1462 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1463 = _schedule_T_1441 | _schedule_T_1442; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1464 = _schedule_T_1463 | _schedule_T_1443; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1465 = _schedule_T_1464 | _schedule_T_1444; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1466 = _schedule_T_1465 | _schedule_T_1445; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1467 = _schedule_T_1466 | _schedule_T_1446; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1468 = _schedule_T_1467 | _schedule_T_1447; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1469 = _schedule_T_1468 | _schedule_T_1448; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1470 = _schedule_T_1469 | _schedule_T_1449; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1471 = _schedule_T_1470 | _schedule_T_1450; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1472 = _schedule_T_1471 | _schedule_T_1451; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1473 = _schedule_T_1472 | _schedule_T_1452; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1474 = _schedule_T_1473 | _schedule_T_1453; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1475 = _schedule_T_1474 | _schedule_T_1454; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1476 = _schedule_T_1475 | _schedule_T_1455; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1477 = _schedule_T_1476 | _schedule_T_1456; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1478 = _schedule_T_1477 | _schedule_T_1457; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1479 = _schedule_T_1478 | _schedule_T_1458; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1480 = _schedule_T_1479 | _schedule_T_1459; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1481 = _schedule_T_1480 | _schedule_T_1460; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1482 = _schedule_T_1481 | _schedule_T_1461; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1484 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1485 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1486 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1487 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1488 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1489 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1490 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1491 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1492 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1493 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1494 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1495 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1496 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1497 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1498 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1499 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1500 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1501 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1502 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1503 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1504 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1505 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1506 = _schedule_T_1484 | _schedule_T_1485; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1507 = _schedule_T_1506 | _schedule_T_1486; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1508 = _schedule_T_1507 | _schedule_T_1487; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1509 = _schedule_T_1508 | _schedule_T_1488; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1510 = _schedule_T_1509 | _schedule_T_1489; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1511 = _schedule_T_1510 | _schedule_T_1490; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1512 = _schedule_T_1511 | _schedule_T_1491; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1513 = _schedule_T_1512 | _schedule_T_1492; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1514 = _schedule_T_1513 | _schedule_T_1493; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1515 = _schedule_T_1514 | _schedule_T_1494; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1516 = _schedule_T_1515 | _schedule_T_1495; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1517 = _schedule_T_1516 | _schedule_T_1496; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1518 = _schedule_T_1517 | _schedule_T_1497; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1519 = _schedule_T_1518 | _schedule_T_1498; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1520 = _schedule_T_1519 | _schedule_T_1499; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1521 = _schedule_T_1520 | _schedule_T_1500; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1522 = _schedule_T_1521 | _schedule_T_1501; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1523 = _schedule_T_1522 | _schedule_T_1502; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1524 = _schedule_T_1523 | _schedule_T_1503; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1525 = _schedule_T_1524 | _schedule_T_1504; // @[Mux.scala 27:73]
  wire [2:0] schedule_c_bits_opcode = _schedule_T_1525 | _schedule_T_1505; // @[Mux.scala 27:73]
  wire  _schedule_T_1542 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_c_valid; // @[Mux.scala 27:73]
  wire  _schedule_T_1563 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_c_valid | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_c_valid | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_c_valid | mshr_selectOH[3] &
    abc_mshrs_3_io_schedule_bits_c_valid | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_c_valid | mshr_selectOH[5] &
    abc_mshrs_5_io_schedule_bits_c_valid | mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_c_valid | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_c_valid | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_c_valid | mshr_selectOH[9] &
    abc_mshrs_9_io_schedule_bits_c_valid | mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_c_valid | mshr_selectOH[11]
     & abc_mshrs_11_io_schedule_bits_c_valid | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_c_valid | mshr_selectOH
    [13] & abc_mshrs_13_io_schedule_bits_c_valid | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_c_valid |
    _schedule_T_1542; // @[Mux.scala 27:73]
  wire  _schedule_T_1585 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_b_bits_clients; // @[Mux.scala 27:73]
  wire  _schedule_T_1606 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_b_bits_clients | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_b_bits_clients | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_b_bits_clients |
    mshr_selectOH[3] & abc_mshrs_3_io_schedule_bits_b_bits_clients | mshr_selectOH[4] &
    abc_mshrs_4_io_schedule_bits_b_bits_clients | mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_b_bits_clients |
    mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_b_bits_clients | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_b_bits_clients | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_b_bits_clients |
    mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_b_bits_clients | mshr_selectOH[10] &
    abc_mshrs_10_io_schedule_bits_b_bits_clients | mshr_selectOH[11] & abc_mshrs_11_io_schedule_bits_b_bits_clients |
    mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_b_bits_clients | mshr_selectOH[13] &
    abc_mshrs_13_io_schedule_bits_b_bits_clients | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_b_bits_clients |
    _schedule_T_1585; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1613 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1614 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1615 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1616 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1617 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1618 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1619 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1620 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1621 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1622 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1623 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1624 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1625 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1626 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1627 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1628 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1629 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1630 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1631 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1632 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1633 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1634 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_b_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1635 = _schedule_T_1613 | _schedule_T_1614; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1636 = _schedule_T_1635 | _schedule_T_1615; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1637 = _schedule_T_1636 | _schedule_T_1616; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1638 = _schedule_T_1637 | _schedule_T_1617; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1639 = _schedule_T_1638 | _schedule_T_1618; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1640 = _schedule_T_1639 | _schedule_T_1619; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1641 = _schedule_T_1640 | _schedule_T_1620; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1642 = _schedule_T_1641 | _schedule_T_1621; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1643 = _schedule_T_1642 | _schedule_T_1622; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1644 = _schedule_T_1643 | _schedule_T_1623; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1645 = _schedule_T_1644 | _schedule_T_1624; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1646 = _schedule_T_1645 | _schedule_T_1625; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1647 = _schedule_T_1646 | _schedule_T_1626; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1648 = _schedule_T_1647 | _schedule_T_1627; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1649 = _schedule_T_1648 | _schedule_T_1628; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1650 = _schedule_T_1649 | _schedule_T_1629; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1651 = _schedule_T_1650 | _schedule_T_1630; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1652 = _schedule_T_1651 | _schedule_T_1631; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1653 = _schedule_T_1652 | _schedule_T_1632; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1654 = _schedule_T_1653 | _schedule_T_1633; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1656 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1657 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1658 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1659 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1660 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1661 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1662 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1663 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1664 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1665 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1666 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1667 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1668 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1669 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1670 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1671 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1672 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1673 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1674 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1675 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1676 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1677 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_b_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1678 = _schedule_T_1656 | _schedule_T_1657; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1679 = _schedule_T_1678 | _schedule_T_1658; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1680 = _schedule_T_1679 | _schedule_T_1659; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1681 = _schedule_T_1680 | _schedule_T_1660; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1682 = _schedule_T_1681 | _schedule_T_1661; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1683 = _schedule_T_1682 | _schedule_T_1662; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1684 = _schedule_T_1683 | _schedule_T_1663; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1685 = _schedule_T_1684 | _schedule_T_1664; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1686 = _schedule_T_1685 | _schedule_T_1665; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1687 = _schedule_T_1686 | _schedule_T_1666; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1688 = _schedule_T_1687 | _schedule_T_1667; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1689 = _schedule_T_1688 | _schedule_T_1668; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1690 = _schedule_T_1689 | _schedule_T_1669; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1691 = _schedule_T_1690 | _schedule_T_1670; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1692 = _schedule_T_1691 | _schedule_T_1671; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1693 = _schedule_T_1692 | _schedule_T_1672; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1694 = _schedule_T_1693 | _schedule_T_1673; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1695 = _schedule_T_1694 | _schedule_T_1674; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1696 = _schedule_T_1695 | _schedule_T_1675; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1697 = _schedule_T_1696 | _schedule_T_1676; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1699 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1700 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1701 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1702 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1703 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1704 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1705 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1706 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1707 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1708 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1709 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1710 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1711 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1712 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1713 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1714 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1715 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1716 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1717 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1718 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1719 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1720 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1721 = _schedule_T_1699 | _schedule_T_1700; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1722 = _schedule_T_1721 | _schedule_T_1701; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1723 = _schedule_T_1722 | _schedule_T_1702; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1724 = _schedule_T_1723 | _schedule_T_1703; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1725 = _schedule_T_1724 | _schedule_T_1704; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1726 = _schedule_T_1725 | _schedule_T_1705; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1727 = _schedule_T_1726 | _schedule_T_1706; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1728 = _schedule_T_1727 | _schedule_T_1707; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1729 = _schedule_T_1728 | _schedule_T_1708; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1730 = _schedule_T_1729 | _schedule_T_1709; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1731 = _schedule_T_1730 | _schedule_T_1710; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1732 = _schedule_T_1731 | _schedule_T_1711; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1733 = _schedule_T_1732 | _schedule_T_1712; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1734 = _schedule_T_1733 | _schedule_T_1713; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1735 = _schedule_T_1734 | _schedule_T_1714; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1736 = _schedule_T_1735 | _schedule_T_1715; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1737 = _schedule_T_1736 | _schedule_T_1716; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1738 = _schedule_T_1737 | _schedule_T_1717; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1739 = _schedule_T_1738 | _schedule_T_1718; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1740 = _schedule_T_1739 | _schedule_T_1719; // @[Mux.scala 27:73]
  wire  _schedule_T_1757 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_b_valid; // @[Mux.scala 27:73]
  wire  _schedule_T_1778 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_b_valid | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_b_valid | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_b_valid | mshr_selectOH[3] &
    abc_mshrs_3_io_schedule_bits_b_valid | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_b_valid | mshr_selectOH[5] &
    abc_mshrs_5_io_schedule_bits_b_valid | mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_b_valid | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_b_valid | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_b_valid | mshr_selectOH[9] &
    abc_mshrs_9_io_schedule_bits_b_valid | mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_b_valid | mshr_selectOH[11]
     & abc_mshrs_11_io_schedule_bits_b_valid | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_b_valid | mshr_selectOH
    [13] & abc_mshrs_13_io_schedule_bits_b_valid | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_b_valid |
    _schedule_T_1757; // @[Mux.scala 27:73]
  wire  _schedule_T_1800 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_a_bits_block; // @[Mux.scala 27:73]
  wire  _schedule_T_1821 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_a_bits_block | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_a_bits_block | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_a_bits_block |
    mshr_selectOH[3] & abc_mshrs_3_io_schedule_bits_a_bits_block | mshr_selectOH[4] &
    abc_mshrs_4_io_schedule_bits_a_bits_block | mshr_selectOH[5] & abc_mshrs_5_io_schedule_bits_a_bits_block |
    mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_a_bits_block | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_a_bits_block | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_a_bits_block |
    mshr_selectOH[9] & abc_mshrs_9_io_schedule_bits_a_bits_block | mshr_selectOH[10] &
    abc_mshrs_10_io_schedule_bits_a_bits_block | mshr_selectOH[11] & abc_mshrs_11_io_schedule_bits_a_bits_block |
    mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_a_bits_block | mshr_selectOH[13] &
    abc_mshrs_13_io_schedule_bits_a_bits_block | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_a_bits_block |
    _schedule_T_1800; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1871 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1872 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1873 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1874 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1875 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1876 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1877 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1878 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1879 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1880 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1881 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1882 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1883 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1884 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1885 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1886 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1887 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1888 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1889 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1890 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1891 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1892 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1893 = _schedule_T_1871 | _schedule_T_1872; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1894 = _schedule_T_1893 | _schedule_T_1873; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1895 = _schedule_T_1894 | _schedule_T_1874; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1896 = _schedule_T_1895 | _schedule_T_1875; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1897 = _schedule_T_1896 | _schedule_T_1876; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1898 = _schedule_T_1897 | _schedule_T_1877; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1899 = _schedule_T_1898 | _schedule_T_1878; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1900 = _schedule_T_1899 | _schedule_T_1879; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1901 = _schedule_T_1900 | _schedule_T_1880; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1902 = _schedule_T_1901 | _schedule_T_1881; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1903 = _schedule_T_1902 | _schedule_T_1882; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1904 = _schedule_T_1903 | _schedule_T_1883; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1905 = _schedule_T_1904 | _schedule_T_1884; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1906 = _schedule_T_1905 | _schedule_T_1885; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1907 = _schedule_T_1906 | _schedule_T_1886; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1908 = _schedule_T_1907 | _schedule_T_1887; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1909 = _schedule_T_1908 | _schedule_T_1888; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1910 = _schedule_T_1909 | _schedule_T_1889; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1911 = _schedule_T_1910 | _schedule_T_1890; // @[Mux.scala 27:73]
  wire [2:0] _schedule_T_1912 = _schedule_T_1911 | _schedule_T_1891; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1914 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1915 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1916 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1917 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1918 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1919 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1920 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1921 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1922 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1923 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1924 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1925 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1926 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1927 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1928 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1929 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1930 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1931 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1932 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1933 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1934 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1935 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_a_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1936 = _schedule_T_1914 | _schedule_T_1915; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1937 = _schedule_T_1936 | _schedule_T_1916; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1938 = _schedule_T_1937 | _schedule_T_1917; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1939 = _schedule_T_1938 | _schedule_T_1918; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1940 = _schedule_T_1939 | _schedule_T_1919; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1941 = _schedule_T_1940 | _schedule_T_1920; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1942 = _schedule_T_1941 | _schedule_T_1921; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1943 = _schedule_T_1942 | _schedule_T_1922; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1944 = _schedule_T_1943 | _schedule_T_1923; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1945 = _schedule_T_1944 | _schedule_T_1924; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1946 = _schedule_T_1945 | _schedule_T_1925; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1947 = _schedule_T_1946 | _schedule_T_1926; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1948 = _schedule_T_1947 | _schedule_T_1927; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1949 = _schedule_T_1948 | _schedule_T_1928; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1950 = _schedule_T_1949 | _schedule_T_1929; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1951 = _schedule_T_1950 | _schedule_T_1930; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1952 = _schedule_T_1951 | _schedule_T_1931; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1953 = _schedule_T_1952 | _schedule_T_1932; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1954 = _schedule_T_1953 | _schedule_T_1933; // @[Mux.scala 27:73]
  wire [1:0] _schedule_T_1955 = _schedule_T_1954 | _schedule_T_1934; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1957 = mshr_selectOH[0] ? abc_mshrs_0_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1958 = mshr_selectOH[1] ? abc_mshrs_1_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1959 = mshr_selectOH[2] ? abc_mshrs_2_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1960 = mshr_selectOH[3] ? abc_mshrs_3_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1961 = mshr_selectOH[4] ? abc_mshrs_4_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1962 = mshr_selectOH[5] ? abc_mshrs_5_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1963 = mshr_selectOH[6] ? abc_mshrs_6_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1964 = mshr_selectOH[7] ? abc_mshrs_7_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1965 = mshr_selectOH[8] ? abc_mshrs_8_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1966 = mshr_selectOH[9] ? abc_mshrs_9_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1967 = mshr_selectOH[10] ? abc_mshrs_10_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1968 = mshr_selectOH[11] ? abc_mshrs_11_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1969 = mshr_selectOH[12] ? abc_mshrs_12_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1970 = mshr_selectOH[13] ? abc_mshrs_13_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1971 = mshr_selectOH[14] ? abc_mshrs_14_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1972 = mshr_selectOH[15] ? abc_mshrs_15_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1973 = mshr_selectOH[16] ? abc_mshrs_16_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1974 = mshr_selectOH[17] ? abc_mshrs_17_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1975 = mshr_selectOH[18] ? abc_mshrs_18_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1976 = mshr_selectOH[19] ? abc_mshrs_19_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1977 = mshr_selectOH[20] ? bc_mshr_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1978 = mshr_selectOH[21] ? c_mshr_io_schedule_bits_a_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1979 = _schedule_T_1957 | _schedule_T_1958; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1980 = _schedule_T_1979 | _schedule_T_1959; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1981 = _schedule_T_1980 | _schedule_T_1960; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1982 = _schedule_T_1981 | _schedule_T_1961; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1983 = _schedule_T_1982 | _schedule_T_1962; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1984 = _schedule_T_1983 | _schedule_T_1963; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1985 = _schedule_T_1984 | _schedule_T_1964; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1986 = _schedule_T_1985 | _schedule_T_1965; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1987 = _schedule_T_1986 | _schedule_T_1966; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1988 = _schedule_T_1987 | _schedule_T_1967; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1989 = _schedule_T_1988 | _schedule_T_1968; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1990 = _schedule_T_1989 | _schedule_T_1969; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1991 = _schedule_T_1990 | _schedule_T_1970; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1992 = _schedule_T_1991 | _schedule_T_1971; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1993 = _schedule_T_1992 | _schedule_T_1972; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1994 = _schedule_T_1993 | _schedule_T_1973; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1995 = _schedule_T_1994 | _schedule_T_1974; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1996 = _schedule_T_1995 | _schedule_T_1975; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1997 = _schedule_T_1996 | _schedule_T_1976; // @[Mux.scala 27:73]
  wire [25:0] _schedule_T_1998 = _schedule_T_1997 | _schedule_T_1977; // @[Mux.scala 27:73]
  wire  _schedule_T_2015 = mshr_selectOH[15] & abc_mshrs_15_io_schedule_bits_a_valid; // @[Mux.scala 27:73]
  wire  _schedule_T_2036 = mshr_selectOH[0] & abc_mshrs_0_io_schedule_bits_a_valid | mshr_selectOH[1] &
    abc_mshrs_1_io_schedule_bits_a_valid | mshr_selectOH[2] & abc_mshrs_2_io_schedule_bits_a_valid | mshr_selectOH[3] &
    abc_mshrs_3_io_schedule_bits_a_valid | mshr_selectOH[4] & abc_mshrs_4_io_schedule_bits_a_valid | mshr_selectOH[5] &
    abc_mshrs_5_io_schedule_bits_a_valid | mshr_selectOH[6] & abc_mshrs_6_io_schedule_bits_a_valid | mshr_selectOH[7] &
    abc_mshrs_7_io_schedule_bits_a_valid | mshr_selectOH[8] & abc_mshrs_8_io_schedule_bits_a_valid | mshr_selectOH[9] &
    abc_mshrs_9_io_schedule_bits_a_valid | mshr_selectOH[10] & abc_mshrs_10_io_schedule_bits_a_valid | mshr_selectOH[11]
     & abc_mshrs_11_io_schedule_bits_a_valid | mshr_selectOH[12] & abc_mshrs_12_io_schedule_bits_a_valid | mshr_selectOH
    [13] & abc_mshrs_13_io_schedule_bits_a_valid | mshr_selectOH[14] & abc_mshrs_14_io_schedule_bits_a_valid |
    _schedule_T_2015; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_22 = mshr_selectOH[0] ? abc_mshrs_0_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_23 = mshr_selectOH[1] ? abc_mshrs_1_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_24 = mshr_selectOH[2] ? abc_mshrs_2_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_25 = mshr_selectOH[3] ? abc_mshrs_3_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_26 = mshr_selectOH[4] ? abc_mshrs_4_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_27 = mshr_selectOH[5] ? abc_mshrs_5_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_28 = mshr_selectOH[6] ? abc_mshrs_6_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_29 = mshr_selectOH[7] ? abc_mshrs_7_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_30 = mshr_selectOH[8] ? abc_mshrs_8_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_31 = mshr_selectOH[9] ? abc_mshrs_9_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_32 = mshr_selectOH[10] ? abc_mshrs_10_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_33 = mshr_selectOH[11] ? abc_mshrs_11_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_34 = mshr_selectOH[12] ? abc_mshrs_12_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_35 = mshr_selectOH[13] ? abc_mshrs_13_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_36 = mshr_selectOH[14] ? abc_mshrs_14_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_37 = mshr_selectOH[15] ? abc_mshrs_15_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_38 = mshr_selectOH[16] ? abc_mshrs_16_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_39 = mshr_selectOH[17] ? abc_mshrs_17_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_40 = mshr_selectOH[18] ? abc_mshrs_18_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_41 = mshr_selectOH[19] ? abc_mshrs_19_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_42 = mshr_selectOH[20] ? bc_mshr_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_43 = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : 26'h0; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_44 = _scheduleTag_T_22 | _scheduleTag_T_23; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_45 = _scheduleTag_T_44 | _scheduleTag_T_24; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_46 = _scheduleTag_T_45 | _scheduleTag_T_25; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_47 = _scheduleTag_T_46 | _scheduleTag_T_26; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_48 = _scheduleTag_T_47 | _scheduleTag_T_27; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_49 = _scheduleTag_T_48 | _scheduleTag_T_28; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_50 = _scheduleTag_T_49 | _scheduleTag_T_29; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_51 = _scheduleTag_T_50 | _scheduleTag_T_30; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_52 = _scheduleTag_T_51 | _scheduleTag_T_31; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_53 = _scheduleTag_T_52 | _scheduleTag_T_32; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_54 = _scheduleTag_T_53 | _scheduleTag_T_33; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_55 = _scheduleTag_T_54 | _scheduleTag_T_34; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_56 = _scheduleTag_T_55 | _scheduleTag_T_35; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_57 = _scheduleTag_T_56 | _scheduleTag_T_36; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_58 = _scheduleTag_T_57 | _scheduleTag_T_37; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_59 = _scheduleTag_T_58 | _scheduleTag_T_38; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_60 = _scheduleTag_T_59 | _scheduleTag_T_39; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_61 = _scheduleTag_T_60 | _scheduleTag_T_40; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_62 = _scheduleTag_T_61 | _scheduleTag_T_41; // @[Mux.scala 27:73]
  wire [25:0] _scheduleTag_T_63 = _scheduleTag_T_62 | _scheduleTag_T_42; // @[Mux.scala 27:73]
  wire [25:0] scheduleTag = _scheduleTag_T_63 | _scheduleTag_T_43; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_22 = mshr_selectOH[0] ? abc_mshrs_0_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_23 = mshr_selectOH[1] ? abc_mshrs_1_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_24 = mshr_selectOH[2] ? abc_mshrs_2_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_25 = mshr_selectOH[3] ? abc_mshrs_3_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_26 = mshr_selectOH[4] ? abc_mshrs_4_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_27 = mshr_selectOH[5] ? abc_mshrs_5_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_28 = mshr_selectOH[6] ? abc_mshrs_6_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_29 = mshr_selectOH[7] ? abc_mshrs_7_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_30 = mshr_selectOH[8] ? abc_mshrs_8_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_31 = mshr_selectOH[9] ? abc_mshrs_9_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_32 = mshr_selectOH[10] ? abc_mshrs_10_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_33 = mshr_selectOH[11] ? abc_mshrs_11_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_34 = mshr_selectOH[12] ? abc_mshrs_12_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_35 = mshr_selectOH[13] ? abc_mshrs_13_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_36 = mshr_selectOH[14] ? abc_mshrs_14_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_37 = mshr_selectOH[15] ? abc_mshrs_15_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_38 = mshr_selectOH[16] ? abc_mshrs_16_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_39 = mshr_selectOH[17] ? abc_mshrs_17_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_40 = mshr_selectOH[18] ? abc_mshrs_18_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_41 = mshr_selectOH[19] ? abc_mshrs_19_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_42 = mshr_selectOH[20] ? bc_mshr_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_43 = mshr_selectOH[21] ? c_mshr_io_status_bits_set : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_44 = _scheduleSet_T_22 | _scheduleSet_T_23; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_45 = _scheduleSet_T_44 | _scheduleSet_T_24; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_46 = _scheduleSet_T_45 | _scheduleSet_T_25; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_47 = _scheduleSet_T_46 | _scheduleSet_T_26; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_48 = _scheduleSet_T_47 | _scheduleSet_T_27; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_49 = _scheduleSet_T_48 | _scheduleSet_T_28; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_50 = _scheduleSet_T_49 | _scheduleSet_T_29; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_51 = _scheduleSet_T_50 | _scheduleSet_T_30; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_52 = _scheduleSet_T_51 | _scheduleSet_T_31; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_53 = _scheduleSet_T_52 | _scheduleSet_T_32; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_54 = _scheduleSet_T_53 | _scheduleSet_T_33; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_55 = _scheduleSet_T_54 | _scheduleSet_T_34; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_56 = _scheduleSet_T_55 | _scheduleSet_T_35; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_57 = _scheduleSet_T_56 | _scheduleSet_T_36; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_58 = _scheduleSet_T_57 | _scheduleSet_T_37; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_59 = _scheduleSet_T_58 | _scheduleSet_T_38; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_60 = _scheduleSet_T_59 | _scheduleSet_T_39; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_61 = _scheduleSet_T_60 | _scheduleSet_T_40; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_62 = _scheduleSet_T_61 | _scheduleSet_T_41; // @[Mux.scala 27:73]
  wire [1:0] _scheduleSet_T_63 = _scheduleSet_T_62 | _scheduleSet_T_42; // @[Mux.scala 27:73]
  wire [1:0] scheduleSet = _scheduleSet_T_63 | _scheduleSet_T_43; // @[Mux.scala 27:73]
  wire [21:0] _GEN_297 = {{1'd0}, mshr_selectOH[21:1]}; // @[package.scala 253:43]
  wire [21:0] _robin_filter_T_1 = mshr_selectOH | _GEN_297; // @[package.scala 253:43]
  wire [21:0] _GEN_310 = {{2'd0}, _robin_filter_T_1[21:2]}; // @[package.scala 253:43]
  wire [21:0] _robin_filter_T_3 = _robin_filter_T_1 | _GEN_310; // @[package.scala 253:43]
  wire [21:0] _GEN_324 = {{4'd0}, _robin_filter_T_3[21:4]}; // @[package.scala 253:43]
  wire [21:0] _robin_filter_T_5 = _robin_filter_T_3 | _GEN_324; // @[package.scala 253:43]
  wire [21:0] _GEN_325 = {{8'd0}, _robin_filter_T_5[21:8]}; // @[package.scala 253:43]
  wire [21:0] _robin_filter_T_7 = _robin_filter_T_5 | _GEN_325; // @[package.scala 253:43]
  wire [21:0] _GEN_381 = {{16'd0}, _robin_filter_T_7[21:16]}; // @[package.scala 253:43]
  wire [21:0] _robin_filter_T_9 = _robin_filter_T_7 | _GEN_381; // @[package.scala 253:43]
  wire [21:0] _robin_filter_T_11 = ~_robin_filter_T_9; // @[Scheduler.scala 126:47]
  wire  request_valid = directory_io_ready & (sinkA_io_req_valid | sinkC_io_req_valid); // @[Scheduler.scala 153:39]
  wire [2:0] _request_bits_T_opcode = sinkA_io_req_bits_opcode; // @[Scheduler.scala 155:22]
  wire [2:0] _request_bits_T_param = sinkA_io_req_bits_param; // @[Scheduler.scala 155:22]
  wire [2:0] _request_bits_T_size = sinkA_io_req_bits_size; // @[Scheduler.scala 155:22]
  wire [2:0] _request_bits_T_source = sinkA_io_req_bits_source; // @[Scheduler.scala 155:22]
  wire [25:0] _request_bits_T_tag = sinkA_io_req_bits_tag; // @[Scheduler.scala 155:22]
  wire [3:0] _request_bits_T_offset = sinkA_io_req_bits_offset; // @[Scheduler.scala 155:22]
  wire [5:0] _request_bits_T_put = sinkA_io_req_bits_put; // @[Scheduler.scala 155:22]
  wire [1:0] _request_bits_T_set = sinkA_io_req_bits_set; // @[Scheduler.scala 155:22]
  wire  request_bits_prio_0 = sinkC_io_req_valid ? 1'h0 : 1'h1; // @[Scheduler.scala 154:22]
  wire  request_bits_prio_2 = sinkC_io_req_valid; // @[Scheduler.scala 154:22]
  wire [2:0] request_bits_opcode = sinkC_io_req_valid ? sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala 154:22]
  wire [2:0] request_bits_param = sinkC_io_req_valid ? sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala 154:22]
  wire [2:0] request_bits_size = sinkC_io_req_valid ? sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala 154:22]
  wire [2:0] request_bits_source = sinkC_io_req_valid ? sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala 154:22]
  wire [25:0] request_bits_tag = sinkC_io_req_valid ? sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala 154:22]
  wire [3:0] request_bits_offset = sinkC_io_req_valid ? sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala 154:22]
  wire [5:0] request_bits_put = sinkC_io_req_valid ? sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala 154:22]
  wire [1:0] request_bits_set = sinkC_io_req_valid ? sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala 154:22]
  wire  _setMatches_T_43 = c_mshr_io_status_valid & c_mshr_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_41 = bc_mshr_io_status_valid & bc_mshr_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_39 = abc_mshrs_19_io_status_valid & abc_mshrs_19_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_37 = abc_mshrs_18_io_status_valid & abc_mshrs_18_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_35 = abc_mshrs_17_io_status_valid & abc_mshrs_17_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_33 = abc_mshrs_16_io_status_valid & abc_mshrs_16_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_31 = abc_mshrs_15_io_status_valid & abc_mshrs_15_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_29 = abc_mshrs_14_io_status_valid & abc_mshrs_14_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_27 = abc_mshrs_13_io_status_valid & abc_mshrs_13_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_25 = abc_mshrs_12_io_status_valid & abc_mshrs_12_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_23 = abc_mshrs_11_io_status_valid & abc_mshrs_11_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire [4:0] setMatches_hi_lo = {_setMatches_T_31,_setMatches_T_29,_setMatches_T_27,_setMatches_T_25,_setMatches_T_23}; // @[Cat.scala 33:92]
  wire  _setMatches_T_21 = abc_mshrs_10_io_status_valid & abc_mshrs_10_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_19 = abc_mshrs_9_io_status_valid & abc_mshrs_9_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_17 = abc_mshrs_8_io_status_valid & abc_mshrs_8_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_15 = abc_mshrs_7_io_status_valid & abc_mshrs_7_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_13 = abc_mshrs_6_io_status_valid & abc_mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_11 = abc_mshrs_5_io_status_valid & abc_mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_9 = abc_mshrs_4_io_status_valid & abc_mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_7 = abc_mshrs_3_io_status_valid & abc_mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_5 = abc_mshrs_2_io_status_valid & abc_mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_3 = abc_mshrs_1_io_status_valid & abc_mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire  _setMatches_T_1 = abc_mshrs_0_io_status_valid & abc_mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala 161:59]
  wire [4:0] setMatches_lo_lo = {_setMatches_T_9,_setMatches_T_7,_setMatches_T_5,_setMatches_T_3,_setMatches_T_1}; // @[Cat.scala 33:92]
  wire [10:0] setMatches_lo = {_setMatches_T_21,_setMatches_T_19,_setMatches_T_17,_setMatches_T_15,_setMatches_T_13,
    _setMatches_T_11,setMatches_lo_lo}; // @[Cat.scala 33:92]
  wire [21:0] setMatches = {_setMatches_T_43,_setMatches_T_41,_setMatches_T_39,_setMatches_T_37,_setMatches_T_35,
    _setMatches_T_33,setMatches_hi_lo,setMatches_lo}; // @[Cat.scala 33:92]
  wire  alloc = ~(|setMatches); // @[Scheduler.scala 162:15]
  wire [65:0] _selected_requests_T = {mshr_selectOH,mshr_selectOH,mshr_selectOH}; // @[Cat.scala 33:92]
  wire [65:0] selected_requests = _selected_requests_T & requests_io_valid; // @[Scheduler.scala 195:76]
  wire  a_pop = |selected_requests[21:0]; // @[Scheduler.scala 196:82]
  wire  b_pop = |selected_requests[43:22]; // @[Scheduler.scala 197:82]
  wire  c_pop = |selected_requests[65:44]; // @[Scheduler.scala 198:82]
  wire  may_pop = a_pop | b_pop | c_pop; // @[Scheduler.scala 201:32]
  wire  _mshr_uses_directory_assuming_no_bypass_T = schedule_reload & may_pop; // @[Scheduler.scala 236:64]
  wire  lb_tag_mismatch = scheduleTag != requests_io_data_tag; // @[Scheduler.scala 235:37]
  wire  mshr_uses_directory_assuming_no_bypass = schedule_reload & may_pop & lb_tag_mismatch; // @[Scheduler.scala 236:75]
  wire  _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala 247:16]
  wire [4:0] mshr_validOH_hi_lo = {abc_mshrs_15_io_status_valid,abc_mshrs_14_io_status_valid,
    abc_mshrs_13_io_status_valid,abc_mshrs_12_io_status_valid,abc_mshrs_11_io_status_valid}; // @[Cat.scala 33:92]
  wire [4:0] mshr_validOH_lo_lo = {abc_mshrs_4_io_status_valid,abc_mshrs_3_io_status_valid,abc_mshrs_2_io_status_valid,
    abc_mshrs_1_io_status_valid,abc_mshrs_0_io_status_valid}; // @[Cat.scala 33:92]
  wire [10:0] mshr_validOH_lo = {abc_mshrs_10_io_status_valid,abc_mshrs_9_io_status_valid,abc_mshrs_8_io_status_valid,
    abc_mshrs_7_io_status_valid,abc_mshrs_6_io_status_valid,abc_mshrs_5_io_status_valid,mshr_validOH_lo_lo}; // @[Cat.scala 33:92]
  wire [21:0] mshr_validOH = {c_mshr_io_status_valid,bc_mshr_io_status_valid,abc_mshrs_19_io_status_valid,
    abc_mshrs_18_io_status_valid,abc_mshrs_17_io_status_valid,abc_mshrs_16_io_status_valid,mshr_validOH_hi_lo,
    mshr_validOH_lo}; // @[Cat.scala 33:92]
  wire [21:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala 242:20]
  wire  _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala 171:46]
  wire [21:0] prioFilter = {request_bits_prio_2,_prioFilter_T,20'hfffff}; // @[Cat.scala 33:92]
  wire [21:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala 242:34]
  wire  mshr_free = |_mshr_free_T_1; // @[Scheduler.scala 242:51]
  wire  _request_alloc_cases_T_2 = alloc & ~mshr_uses_directory_assuming_no_bypass & mshr_free; // @[Scheduler.scala 247:56]
  wire  _request_alloc_cases_T_7 = ~c_mshr_io_status_valid; // @[Scheduler.scala 248:87]
  wire  _nestC_T_37 = setMatches[15] & abc_mshrs_15_io_status_bits_nestC; // @[Mux.scala 27:73]
  wire  _nestC_T_58 = setMatches[0] & abc_mshrs_0_io_status_bits_nestC | setMatches[1] &
    abc_mshrs_1_io_status_bits_nestC | setMatches[2] & abc_mshrs_2_io_status_bits_nestC | setMatches[3] &
    abc_mshrs_3_io_status_bits_nestC | setMatches[4] & abc_mshrs_4_io_status_bits_nestC | setMatches[5] &
    abc_mshrs_5_io_status_bits_nestC | setMatches[6] & abc_mshrs_6_io_status_bits_nestC | setMatches[7] &
    abc_mshrs_7_io_status_bits_nestC | setMatches[8] & abc_mshrs_8_io_status_bits_nestC | setMatches[9] &
    abc_mshrs_9_io_status_bits_nestC | setMatches[10] & abc_mshrs_10_io_status_bits_nestC | setMatches[11] &
    abc_mshrs_11_io_status_bits_nestC | setMatches[12] & abc_mshrs_12_io_status_bits_nestC | setMatches[13] &
    abc_mshrs_13_io_status_bits_nestC | setMatches[14] & abc_mshrs_14_io_status_bits_nestC | _nestC_T_37; // @[Mux.scala 27:73]
  wire  _nestC_T_64 = _nestC_T_58 | setMatches[16] & abc_mshrs_16_io_status_bits_nestC | setMatches[17] &
    abc_mshrs_17_io_status_bits_nestC | setMatches[18] & abc_mshrs_18_io_status_bits_nestC | setMatches[19] &
    abc_mshrs_19_io_status_bits_nestC | setMatches[20] & bc_mshr_io_status_bits_nestC | setMatches[21] &
    c_mshr_io_status_bits_nestC; // @[Mux.scala 27:73]
  wire  nestC = _nestC_T_64 & request_bits_prio_2; // @[Scheduler.scala 169:70]
  wire  _request_alloc_cases_T_13 = nestC & _request_alloc_cases_T & _request_alloc_cases_T_7; // @[Scheduler.scala 249:56]
  wire  request_alloc_cases = _request_alloc_cases_T_2 | _request_alloc_cases_T_13; // @[Scheduler.scala 248:112]
  wire [21:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala 172:33]
  wire  _blockC_T_37 = setMatches[15] & abc_mshrs_15_io_status_bits_blockC; // @[Mux.scala 27:73]
  wire  _blockC_T_58 = setMatches[0] & abc_mshrs_0_io_status_bits_blockC | setMatches[1] &
    abc_mshrs_1_io_status_bits_blockC | setMatches[2] & abc_mshrs_2_io_status_bits_blockC | setMatches[3] &
    abc_mshrs_3_io_status_bits_blockC | setMatches[4] & abc_mshrs_4_io_status_bits_blockC | setMatches[5] &
    abc_mshrs_5_io_status_bits_blockC | setMatches[6] & abc_mshrs_6_io_status_bits_blockC | setMatches[7] &
    abc_mshrs_7_io_status_bits_blockC | setMatches[8] & abc_mshrs_8_io_status_bits_blockC | setMatches[9] &
    abc_mshrs_9_io_status_bits_blockC | setMatches[10] & abc_mshrs_10_io_status_bits_blockC | setMatches[11] &
    abc_mshrs_11_io_status_bits_blockC | setMatches[12] & abc_mshrs_12_io_status_bits_blockC | setMatches[13] &
    abc_mshrs_13_io_status_bits_blockC | setMatches[14] & abc_mshrs_14_io_status_bits_blockC | _blockC_T_37; // @[Mux.scala 27:73]
  wire  _blockC_T_64 = _blockC_T_58 | setMatches[16] & abc_mshrs_16_io_status_bits_blockC | setMatches[17] &
    abc_mshrs_17_io_status_bits_blockC | setMatches[18] & abc_mshrs_18_io_status_bits_blockC | setMatches[19] &
    abc_mshrs_19_io_status_bits_blockC | setMatches[20] & bc_mshr_io_status_bits_blockC | setMatches[21] &
    c_mshr_io_status_bits_blockC; // @[Mux.scala 27:73]
  wire  blockC = _blockC_T_64 & request_bits_prio_2; // @[Scheduler.scala 165:70]
  wire  queue = |lowerMatches & ~nestC & ~blockC; // @[Scheduler.scala 174:65]
  wire [21:0] _lowerMatches1_T_2 = lowerMatches[20] ? 22'h100000 : lowerMatches; // @[Scheduler.scala 190:8]
  wire [21:0] lowerMatches1 = lowerMatches[21] ? 22'h200000 : _lowerMatches1_T_2; // @[Scheduler.scala 189:8]
  wire [21:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala 199:38]
  wire  _bypassMatches_T_7 = b_pop ? ~b_pop : ~a_pop; // @[Scheduler.scala 200:69]
  wire  _bypassMatches_T_8 = c_pop | request_bits_prio_2 ? ~c_pop : _bypassMatches_T_7; // @[Scheduler.scala 200:26]
  wire  bypassMatches = |_bypassMatches_T & _bypassMatches_T_8; // @[Scheduler.scala 199:61]
  wire  bypassQueue = schedule_reload & bypassMatches; // @[Scheduler.scala 245:37]
  wire  request_ready = request_alloc_cases | queue & (bypassQueue | requests_io_push_ready); // @[Scheduler.scala 250:40]
  wire  _sinkC_io_req_ready_T = directory_io_ready & request_ready; // @[Scheduler.scala 156:44]
  wire  _sinkX_io_req_ready_T_1 = ~sinkC_io_req_valid; // @[Scheduler.scala 157:64]
  wire  _bypass_T = request_valid & queue; // @[Scheduler.scala 202:30]
  wire  bypass = request_valid & queue & bypassMatches; // @[Scheduler.scala 202:39]
  wire  will_reload = schedule_reload & (may_pop | bypass); // @[Scheduler.scala 203:37]
  wire  will_pop = _mshr_uses_directory_assuming_no_bypass_T & ~bypass; // @[Scheduler.scala 204:45]
  wire  a_pop_1 = requests_io_valid[0]; // @[Scheduler.scala 214:34]
  wire  b_pop_1 = requests_io_valid[22]; // @[Scheduler.scala 215:34]
  wire  c_pop_1 = requests_io_valid[44]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_15 = b_pop_1 ? ~b_pop_1 : ~a_pop_1; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_16 = c_pop_1 | request_bits_prio_2 ? ~c_pop_1 : _bypassMatches_T_15; // @[Scheduler.scala 218:28]
  wire  bypassMatches_1 = lowerMatches1[0] & _bypassMatches_T_16; // @[Scheduler.scala 217:42]
  wire  may_pop_1 = a_pop_1 | b_pop_1 | c_pop_1; // @[Scheduler.scala 219:34]
  wire  bypass_1 = _bypass_T & bypassMatches_1; // @[Scheduler.scala 220:41]
  wire  will_reload_1 = abc_mshrs_0_io_schedule_bits_reload & (may_pop_1 | bypass_1); // @[Scheduler.scala 221:49]
  wire  _mshrs_0_io_allocate_bits_T_prio_0 = bypass_1 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_0_io_allocate_bits_T_prio_1 = bypass_1 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_0_io_allocate_bits_T_prio_2 = bypass_1 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_0_io_allocate_bits_T_opcode = bypass_1 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_0_io_allocate_bits_T_param = bypass_1 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_0_io_allocate_bits_T_size = bypass_1 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_0_io_allocate_bits_T_source = bypass_1 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_0_io_allocate_bits_T_tag = bypass_1 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_0_io_allocate_bits_T_offset = bypass_1 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_0_io_allocate_bits_T_put = bypass_1 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_2 = requests_io_valid[1]; // @[Scheduler.scala 214:34]
  wire  b_pop_2 = requests_io_valid[23]; // @[Scheduler.scala 215:34]
  wire  c_pop_2 = requests_io_valid[45]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_23 = b_pop_2 ? ~b_pop_2 : ~a_pop_2; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_24 = c_pop_2 | request_bits_prio_2 ? ~c_pop_2 : _bypassMatches_T_23; // @[Scheduler.scala 218:28]
  wire  bypassMatches_2 = lowerMatches1[1] & _bypassMatches_T_24; // @[Scheduler.scala 217:42]
  wire  may_pop_2 = a_pop_2 | b_pop_2 | c_pop_2; // @[Scheduler.scala 219:34]
  wire  bypass_2 = _bypass_T & bypassMatches_2; // @[Scheduler.scala 220:41]
  wire  will_reload_2 = abc_mshrs_1_io_schedule_bits_reload & (may_pop_2 | bypass_2); // @[Scheduler.scala 221:49]
  wire  _mshrs_1_io_allocate_bits_T_prio_0 = bypass_2 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_1_io_allocate_bits_T_prio_1 = bypass_2 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_1_io_allocate_bits_T_prio_2 = bypass_2 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_1_io_allocate_bits_T_opcode = bypass_2 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_1_io_allocate_bits_T_param = bypass_2 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_1_io_allocate_bits_T_size = bypass_2 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_1_io_allocate_bits_T_source = bypass_2 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_1_io_allocate_bits_T_tag = bypass_2 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_1_io_allocate_bits_T_offset = bypass_2 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_1_io_allocate_bits_T_put = bypass_2 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_3 = requests_io_valid[2]; // @[Scheduler.scala 214:34]
  wire  b_pop_3 = requests_io_valid[24]; // @[Scheduler.scala 215:34]
  wire  c_pop_3 = requests_io_valid[46]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_31 = b_pop_3 ? ~b_pop_3 : ~a_pop_3; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_32 = c_pop_3 | request_bits_prio_2 ? ~c_pop_3 : _bypassMatches_T_31; // @[Scheduler.scala 218:28]
  wire  bypassMatches_3 = lowerMatches1[2] & _bypassMatches_T_32; // @[Scheduler.scala 217:42]
  wire  may_pop_3 = a_pop_3 | b_pop_3 | c_pop_3; // @[Scheduler.scala 219:34]
  wire  bypass_3 = _bypass_T & bypassMatches_3; // @[Scheduler.scala 220:41]
  wire  will_reload_3 = abc_mshrs_2_io_schedule_bits_reload & (may_pop_3 | bypass_3); // @[Scheduler.scala 221:49]
  wire  _mshrs_2_io_allocate_bits_T_prio_0 = bypass_3 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_2_io_allocate_bits_T_prio_1 = bypass_3 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_2_io_allocate_bits_T_prio_2 = bypass_3 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_2_io_allocate_bits_T_opcode = bypass_3 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_2_io_allocate_bits_T_param = bypass_3 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_2_io_allocate_bits_T_size = bypass_3 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_2_io_allocate_bits_T_source = bypass_3 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_2_io_allocate_bits_T_tag = bypass_3 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_2_io_allocate_bits_T_offset = bypass_3 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_2_io_allocate_bits_T_put = bypass_3 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_4 = requests_io_valid[3]; // @[Scheduler.scala 214:34]
  wire  b_pop_4 = requests_io_valid[25]; // @[Scheduler.scala 215:34]
  wire  c_pop_4 = requests_io_valid[47]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_39 = b_pop_4 ? ~b_pop_4 : ~a_pop_4; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_40 = c_pop_4 | request_bits_prio_2 ? ~c_pop_4 : _bypassMatches_T_39; // @[Scheduler.scala 218:28]
  wire  bypassMatches_4 = lowerMatches1[3] & _bypassMatches_T_40; // @[Scheduler.scala 217:42]
  wire  may_pop_4 = a_pop_4 | b_pop_4 | c_pop_4; // @[Scheduler.scala 219:34]
  wire  bypass_4 = _bypass_T & bypassMatches_4; // @[Scheduler.scala 220:41]
  wire  will_reload_4 = abc_mshrs_3_io_schedule_bits_reload & (may_pop_4 | bypass_4); // @[Scheduler.scala 221:49]
  wire  _mshrs_3_io_allocate_bits_T_prio_0 = bypass_4 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_3_io_allocate_bits_T_prio_1 = bypass_4 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_3_io_allocate_bits_T_prio_2 = bypass_4 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_3_io_allocate_bits_T_opcode = bypass_4 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_3_io_allocate_bits_T_param = bypass_4 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_3_io_allocate_bits_T_size = bypass_4 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_3_io_allocate_bits_T_source = bypass_4 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_3_io_allocate_bits_T_tag = bypass_4 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_3_io_allocate_bits_T_offset = bypass_4 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_3_io_allocate_bits_T_put = bypass_4 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_5 = requests_io_valid[4]; // @[Scheduler.scala 214:34]
  wire  b_pop_5 = requests_io_valid[26]; // @[Scheduler.scala 215:34]
  wire  c_pop_5 = requests_io_valid[48]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_47 = b_pop_5 ? ~b_pop_5 : ~a_pop_5; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_48 = c_pop_5 | request_bits_prio_2 ? ~c_pop_5 : _bypassMatches_T_47; // @[Scheduler.scala 218:28]
  wire  bypassMatches_5 = lowerMatches1[4] & _bypassMatches_T_48; // @[Scheduler.scala 217:42]
  wire  may_pop_5 = a_pop_5 | b_pop_5 | c_pop_5; // @[Scheduler.scala 219:34]
  wire  bypass_5 = _bypass_T & bypassMatches_5; // @[Scheduler.scala 220:41]
  wire  will_reload_5 = abc_mshrs_4_io_schedule_bits_reload & (may_pop_5 | bypass_5); // @[Scheduler.scala 221:49]
  wire  _mshrs_4_io_allocate_bits_T_prio_0 = bypass_5 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_4_io_allocate_bits_T_prio_1 = bypass_5 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_4_io_allocate_bits_T_prio_2 = bypass_5 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_4_io_allocate_bits_T_opcode = bypass_5 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_4_io_allocate_bits_T_param = bypass_5 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_4_io_allocate_bits_T_size = bypass_5 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_4_io_allocate_bits_T_source = bypass_5 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_4_io_allocate_bits_T_tag = bypass_5 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_4_io_allocate_bits_T_offset = bypass_5 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_4_io_allocate_bits_T_put = bypass_5 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_6 = requests_io_valid[5]; // @[Scheduler.scala 214:34]
  wire  b_pop_6 = requests_io_valid[27]; // @[Scheduler.scala 215:34]
  wire  c_pop_6 = requests_io_valid[49]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_55 = b_pop_6 ? ~b_pop_6 : ~a_pop_6; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_56 = c_pop_6 | request_bits_prio_2 ? ~c_pop_6 : _bypassMatches_T_55; // @[Scheduler.scala 218:28]
  wire  bypassMatches_6 = lowerMatches1[5] & _bypassMatches_T_56; // @[Scheduler.scala 217:42]
  wire  may_pop_6 = a_pop_6 | b_pop_6 | c_pop_6; // @[Scheduler.scala 219:34]
  wire  bypass_6 = _bypass_T & bypassMatches_6; // @[Scheduler.scala 220:41]
  wire  will_reload_6 = abc_mshrs_5_io_schedule_bits_reload & (may_pop_6 | bypass_6); // @[Scheduler.scala 221:49]
  wire  _mshrs_5_io_allocate_bits_T_prio_0 = bypass_6 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_5_io_allocate_bits_T_prio_1 = bypass_6 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_5_io_allocate_bits_T_prio_2 = bypass_6 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_5_io_allocate_bits_T_opcode = bypass_6 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_5_io_allocate_bits_T_param = bypass_6 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_5_io_allocate_bits_T_size = bypass_6 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_5_io_allocate_bits_T_source = bypass_6 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_5_io_allocate_bits_T_tag = bypass_6 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_5_io_allocate_bits_T_offset = bypass_6 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_5_io_allocate_bits_T_put = bypass_6 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_7 = requests_io_valid[6]; // @[Scheduler.scala 214:34]
  wire  b_pop_7 = requests_io_valid[28]; // @[Scheduler.scala 215:34]
  wire  c_pop_7 = requests_io_valid[50]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_63 = b_pop_7 ? ~b_pop_7 : ~a_pop_7; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_64 = c_pop_7 | request_bits_prio_2 ? ~c_pop_7 : _bypassMatches_T_63; // @[Scheduler.scala 218:28]
  wire  bypassMatches_7 = lowerMatches1[6] & _bypassMatches_T_64; // @[Scheduler.scala 217:42]
  wire  may_pop_7 = a_pop_7 | b_pop_7 | c_pop_7; // @[Scheduler.scala 219:34]
  wire  bypass_7 = _bypass_T & bypassMatches_7; // @[Scheduler.scala 220:41]
  wire  will_reload_7 = abc_mshrs_6_io_schedule_bits_reload & (may_pop_7 | bypass_7); // @[Scheduler.scala 221:49]
  wire  _mshrs_6_io_allocate_bits_T_prio_0 = bypass_7 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_6_io_allocate_bits_T_prio_1 = bypass_7 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_6_io_allocate_bits_T_prio_2 = bypass_7 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_6_io_allocate_bits_T_opcode = bypass_7 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_6_io_allocate_bits_T_param = bypass_7 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_6_io_allocate_bits_T_size = bypass_7 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_6_io_allocate_bits_T_source = bypass_7 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_6_io_allocate_bits_T_tag = bypass_7 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_6_io_allocate_bits_T_offset = bypass_7 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_6_io_allocate_bits_T_put = bypass_7 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_8 = requests_io_valid[7]; // @[Scheduler.scala 214:34]
  wire  b_pop_8 = requests_io_valid[29]; // @[Scheduler.scala 215:34]
  wire  c_pop_8 = requests_io_valid[51]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_71 = b_pop_8 ? ~b_pop_8 : ~a_pop_8; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_72 = c_pop_8 | request_bits_prio_2 ? ~c_pop_8 : _bypassMatches_T_71; // @[Scheduler.scala 218:28]
  wire  bypassMatches_8 = lowerMatches1[7] & _bypassMatches_T_72; // @[Scheduler.scala 217:42]
  wire  may_pop_8 = a_pop_8 | b_pop_8 | c_pop_8; // @[Scheduler.scala 219:34]
  wire  bypass_8 = _bypass_T & bypassMatches_8; // @[Scheduler.scala 220:41]
  wire  will_reload_8 = abc_mshrs_7_io_schedule_bits_reload & (may_pop_8 | bypass_8); // @[Scheduler.scala 221:49]
  wire  _mshrs_7_io_allocate_bits_T_prio_0 = bypass_8 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_7_io_allocate_bits_T_prio_1 = bypass_8 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_7_io_allocate_bits_T_prio_2 = bypass_8 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_7_io_allocate_bits_T_opcode = bypass_8 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_7_io_allocate_bits_T_param = bypass_8 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_7_io_allocate_bits_T_size = bypass_8 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_7_io_allocate_bits_T_source = bypass_8 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_7_io_allocate_bits_T_tag = bypass_8 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_7_io_allocate_bits_T_offset = bypass_8 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_7_io_allocate_bits_T_put = bypass_8 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_9 = requests_io_valid[8]; // @[Scheduler.scala 214:34]
  wire  b_pop_9 = requests_io_valid[30]; // @[Scheduler.scala 215:34]
  wire  c_pop_9 = requests_io_valid[52]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_79 = b_pop_9 ? ~b_pop_9 : ~a_pop_9; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_80 = c_pop_9 | request_bits_prio_2 ? ~c_pop_9 : _bypassMatches_T_79; // @[Scheduler.scala 218:28]
  wire  bypassMatches_9 = lowerMatches1[8] & _bypassMatches_T_80; // @[Scheduler.scala 217:42]
  wire  may_pop_9 = a_pop_9 | b_pop_9 | c_pop_9; // @[Scheduler.scala 219:34]
  wire  bypass_9 = _bypass_T & bypassMatches_9; // @[Scheduler.scala 220:41]
  wire  will_reload_9 = abc_mshrs_8_io_schedule_bits_reload & (may_pop_9 | bypass_9); // @[Scheduler.scala 221:49]
  wire  _mshrs_8_io_allocate_bits_T_prio_0 = bypass_9 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_8_io_allocate_bits_T_prio_1 = bypass_9 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_8_io_allocate_bits_T_prio_2 = bypass_9 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_8_io_allocate_bits_T_opcode = bypass_9 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_8_io_allocate_bits_T_param = bypass_9 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_8_io_allocate_bits_T_size = bypass_9 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_8_io_allocate_bits_T_source = bypass_9 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_8_io_allocate_bits_T_tag = bypass_9 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_8_io_allocate_bits_T_offset = bypass_9 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_8_io_allocate_bits_T_put = bypass_9 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_10 = requests_io_valid[9]; // @[Scheduler.scala 214:34]
  wire  b_pop_10 = requests_io_valid[31]; // @[Scheduler.scala 215:34]
  wire  c_pop_10 = requests_io_valid[53]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_87 = b_pop_10 ? ~b_pop_10 : ~a_pop_10; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_88 = c_pop_10 | request_bits_prio_2 ? ~c_pop_10 : _bypassMatches_T_87; // @[Scheduler.scala 218:28]
  wire  bypassMatches_10 = lowerMatches1[9] & _bypassMatches_T_88; // @[Scheduler.scala 217:42]
  wire  may_pop_10 = a_pop_10 | b_pop_10 | c_pop_10; // @[Scheduler.scala 219:34]
  wire  bypass_10 = _bypass_T & bypassMatches_10; // @[Scheduler.scala 220:41]
  wire  will_reload_10 = abc_mshrs_9_io_schedule_bits_reload & (may_pop_10 | bypass_10); // @[Scheduler.scala 221:49]
  wire  _mshrs_9_io_allocate_bits_T_prio_0 = bypass_10 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_9_io_allocate_bits_T_prio_1 = bypass_10 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_9_io_allocate_bits_T_prio_2 = bypass_10 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_9_io_allocate_bits_T_opcode = bypass_10 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_9_io_allocate_bits_T_param = bypass_10 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_9_io_allocate_bits_T_size = bypass_10 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_9_io_allocate_bits_T_source = bypass_10 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_9_io_allocate_bits_T_tag = bypass_10 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_9_io_allocate_bits_T_offset = bypass_10 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_9_io_allocate_bits_T_put = bypass_10 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_11 = requests_io_valid[10]; // @[Scheduler.scala 214:34]
  wire  b_pop_11 = requests_io_valid[32]; // @[Scheduler.scala 215:34]
  wire  c_pop_11 = requests_io_valid[54]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_95 = b_pop_11 ? ~b_pop_11 : ~a_pop_11; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_96 = c_pop_11 | request_bits_prio_2 ? ~c_pop_11 : _bypassMatches_T_95; // @[Scheduler.scala 218:28]
  wire  bypassMatches_11 = lowerMatches1[10] & _bypassMatches_T_96; // @[Scheduler.scala 217:42]
  wire  may_pop_11 = a_pop_11 | b_pop_11 | c_pop_11; // @[Scheduler.scala 219:34]
  wire  bypass_11 = _bypass_T & bypassMatches_11; // @[Scheduler.scala 220:41]
  wire  will_reload_11 = abc_mshrs_10_io_schedule_bits_reload & (may_pop_11 | bypass_11); // @[Scheduler.scala 221:49]
  wire  _mshrs_10_io_allocate_bits_T_prio_0 = bypass_11 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_10_io_allocate_bits_T_prio_1 = bypass_11 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_10_io_allocate_bits_T_prio_2 = bypass_11 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_10_io_allocate_bits_T_opcode = bypass_11 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_10_io_allocate_bits_T_param = bypass_11 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_10_io_allocate_bits_T_size = bypass_11 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_10_io_allocate_bits_T_source = bypass_11 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_10_io_allocate_bits_T_tag = bypass_11 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_10_io_allocate_bits_T_offset = bypass_11 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_10_io_allocate_bits_T_put = bypass_11 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_12 = requests_io_valid[11]; // @[Scheduler.scala 214:34]
  wire  b_pop_12 = requests_io_valid[33]; // @[Scheduler.scala 215:34]
  wire  c_pop_12 = requests_io_valid[55]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_103 = b_pop_12 ? ~b_pop_12 : ~a_pop_12; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_104 = c_pop_12 | request_bits_prio_2 ? ~c_pop_12 : _bypassMatches_T_103; // @[Scheduler.scala 218:28]
  wire  bypassMatches_12 = lowerMatches1[11] & _bypassMatches_T_104; // @[Scheduler.scala 217:42]
  wire  may_pop_12 = a_pop_12 | b_pop_12 | c_pop_12; // @[Scheduler.scala 219:34]
  wire  bypass_12 = _bypass_T & bypassMatches_12; // @[Scheduler.scala 220:41]
  wire  will_reload_12 = abc_mshrs_11_io_schedule_bits_reload & (may_pop_12 | bypass_12); // @[Scheduler.scala 221:49]
  wire  _mshrs_11_io_allocate_bits_T_prio_0 = bypass_12 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_11_io_allocate_bits_T_prio_1 = bypass_12 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_11_io_allocate_bits_T_prio_2 = bypass_12 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_11_io_allocate_bits_T_opcode = bypass_12 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_11_io_allocate_bits_T_param = bypass_12 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_11_io_allocate_bits_T_size = bypass_12 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_11_io_allocate_bits_T_source = bypass_12 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_11_io_allocate_bits_T_tag = bypass_12 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_11_io_allocate_bits_T_offset = bypass_12 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_11_io_allocate_bits_T_put = bypass_12 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_13 = requests_io_valid[12]; // @[Scheduler.scala 214:34]
  wire  b_pop_13 = requests_io_valid[34]; // @[Scheduler.scala 215:34]
  wire  c_pop_13 = requests_io_valid[56]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_111 = b_pop_13 ? ~b_pop_13 : ~a_pop_13; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_112 = c_pop_13 | request_bits_prio_2 ? ~c_pop_13 : _bypassMatches_T_111; // @[Scheduler.scala 218:28]
  wire  bypassMatches_13 = lowerMatches1[12] & _bypassMatches_T_112; // @[Scheduler.scala 217:42]
  wire  may_pop_13 = a_pop_13 | b_pop_13 | c_pop_13; // @[Scheduler.scala 219:34]
  wire  bypass_13 = _bypass_T & bypassMatches_13; // @[Scheduler.scala 220:41]
  wire  will_reload_13 = abc_mshrs_12_io_schedule_bits_reload & (may_pop_13 | bypass_13); // @[Scheduler.scala 221:49]
  wire  _mshrs_12_io_allocate_bits_T_prio_0 = bypass_13 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_12_io_allocate_bits_T_prio_1 = bypass_13 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_12_io_allocate_bits_T_prio_2 = bypass_13 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_12_io_allocate_bits_T_opcode = bypass_13 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_12_io_allocate_bits_T_param = bypass_13 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_12_io_allocate_bits_T_size = bypass_13 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_12_io_allocate_bits_T_source = bypass_13 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_12_io_allocate_bits_T_tag = bypass_13 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_12_io_allocate_bits_T_offset = bypass_13 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_12_io_allocate_bits_T_put = bypass_13 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_14 = requests_io_valid[13]; // @[Scheduler.scala 214:34]
  wire  b_pop_14 = requests_io_valid[35]; // @[Scheduler.scala 215:34]
  wire  c_pop_14 = requests_io_valid[57]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_119 = b_pop_14 ? ~b_pop_14 : ~a_pop_14; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_120 = c_pop_14 | request_bits_prio_2 ? ~c_pop_14 : _bypassMatches_T_119; // @[Scheduler.scala 218:28]
  wire  bypassMatches_14 = lowerMatches1[13] & _bypassMatches_T_120; // @[Scheduler.scala 217:42]
  wire  may_pop_14 = a_pop_14 | b_pop_14 | c_pop_14; // @[Scheduler.scala 219:34]
  wire  bypass_14 = _bypass_T & bypassMatches_14; // @[Scheduler.scala 220:41]
  wire  will_reload_14 = abc_mshrs_13_io_schedule_bits_reload & (may_pop_14 | bypass_14); // @[Scheduler.scala 221:49]
  wire  _mshrs_13_io_allocate_bits_T_prio_0 = bypass_14 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_13_io_allocate_bits_T_prio_1 = bypass_14 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_13_io_allocate_bits_T_prio_2 = bypass_14 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_13_io_allocate_bits_T_opcode = bypass_14 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_13_io_allocate_bits_T_param = bypass_14 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_13_io_allocate_bits_T_size = bypass_14 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_13_io_allocate_bits_T_source = bypass_14 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_13_io_allocate_bits_T_tag = bypass_14 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_13_io_allocate_bits_T_offset = bypass_14 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_13_io_allocate_bits_T_put = bypass_14 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_15 = requests_io_valid[14]; // @[Scheduler.scala 214:34]
  wire  b_pop_15 = requests_io_valid[36]; // @[Scheduler.scala 215:34]
  wire  c_pop_15 = requests_io_valid[58]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_127 = b_pop_15 ? ~b_pop_15 : ~a_pop_15; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_128 = c_pop_15 | request_bits_prio_2 ? ~c_pop_15 : _bypassMatches_T_127; // @[Scheduler.scala 218:28]
  wire  bypassMatches_15 = lowerMatches1[14] & _bypassMatches_T_128; // @[Scheduler.scala 217:42]
  wire  may_pop_15 = a_pop_15 | b_pop_15 | c_pop_15; // @[Scheduler.scala 219:34]
  wire  bypass_15 = _bypass_T & bypassMatches_15; // @[Scheduler.scala 220:41]
  wire  will_reload_15 = abc_mshrs_14_io_schedule_bits_reload & (may_pop_15 | bypass_15); // @[Scheduler.scala 221:49]
  wire  _mshrs_14_io_allocate_bits_T_prio_0 = bypass_15 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_14_io_allocate_bits_T_prio_1 = bypass_15 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_14_io_allocate_bits_T_prio_2 = bypass_15 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_14_io_allocate_bits_T_opcode = bypass_15 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_14_io_allocate_bits_T_param = bypass_15 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_14_io_allocate_bits_T_size = bypass_15 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_14_io_allocate_bits_T_source = bypass_15 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_14_io_allocate_bits_T_tag = bypass_15 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_14_io_allocate_bits_T_offset = bypass_15 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_14_io_allocate_bits_T_put = bypass_15 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_16 = requests_io_valid[15]; // @[Scheduler.scala 214:34]
  wire  b_pop_16 = requests_io_valid[37]; // @[Scheduler.scala 215:34]
  wire  c_pop_16 = requests_io_valid[59]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_135 = b_pop_16 ? ~b_pop_16 : ~a_pop_16; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_136 = c_pop_16 | request_bits_prio_2 ? ~c_pop_16 : _bypassMatches_T_135; // @[Scheduler.scala 218:28]
  wire  bypassMatches_16 = lowerMatches1[15] & _bypassMatches_T_136; // @[Scheduler.scala 217:42]
  wire  may_pop_16 = a_pop_16 | b_pop_16 | c_pop_16; // @[Scheduler.scala 219:34]
  wire  bypass_16 = _bypass_T & bypassMatches_16; // @[Scheduler.scala 220:41]
  wire  will_reload_16 = abc_mshrs_15_io_schedule_bits_reload & (may_pop_16 | bypass_16); // @[Scheduler.scala 221:49]
  wire  _mshrs_15_io_allocate_bits_T_prio_0 = bypass_16 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_15_io_allocate_bits_T_prio_1 = bypass_16 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_15_io_allocate_bits_T_prio_2 = bypass_16 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_15_io_allocate_bits_T_opcode = bypass_16 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_15_io_allocate_bits_T_param = bypass_16 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_15_io_allocate_bits_T_size = bypass_16 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_15_io_allocate_bits_T_source = bypass_16 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_15_io_allocate_bits_T_tag = bypass_16 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_15_io_allocate_bits_T_offset = bypass_16 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_15_io_allocate_bits_T_put = bypass_16 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_17 = requests_io_valid[16]; // @[Scheduler.scala 214:34]
  wire  b_pop_17 = requests_io_valid[38]; // @[Scheduler.scala 215:34]
  wire  c_pop_17 = requests_io_valid[60]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_143 = b_pop_17 ? ~b_pop_17 : ~a_pop_17; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_144 = c_pop_17 | request_bits_prio_2 ? ~c_pop_17 : _bypassMatches_T_143; // @[Scheduler.scala 218:28]
  wire  bypassMatches_17 = lowerMatches1[16] & _bypassMatches_T_144; // @[Scheduler.scala 217:42]
  wire  may_pop_17 = a_pop_17 | b_pop_17 | c_pop_17; // @[Scheduler.scala 219:34]
  wire  bypass_17 = _bypass_T & bypassMatches_17; // @[Scheduler.scala 220:41]
  wire  will_reload_17 = abc_mshrs_16_io_schedule_bits_reload & (may_pop_17 | bypass_17); // @[Scheduler.scala 221:49]
  wire  _mshrs_16_io_allocate_bits_T_prio_0 = bypass_17 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_16_io_allocate_bits_T_prio_1 = bypass_17 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_16_io_allocate_bits_T_prio_2 = bypass_17 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_16_io_allocate_bits_T_opcode = bypass_17 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_16_io_allocate_bits_T_param = bypass_17 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_16_io_allocate_bits_T_size = bypass_17 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_16_io_allocate_bits_T_source = bypass_17 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_16_io_allocate_bits_T_tag = bypass_17 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_16_io_allocate_bits_T_offset = bypass_17 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_16_io_allocate_bits_T_put = bypass_17 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_18 = requests_io_valid[17]; // @[Scheduler.scala 214:34]
  wire  b_pop_18 = requests_io_valid[39]; // @[Scheduler.scala 215:34]
  wire  c_pop_18 = requests_io_valid[61]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_151 = b_pop_18 ? ~b_pop_18 : ~a_pop_18; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_152 = c_pop_18 | request_bits_prio_2 ? ~c_pop_18 : _bypassMatches_T_151; // @[Scheduler.scala 218:28]
  wire  bypassMatches_18 = lowerMatches1[17] & _bypassMatches_T_152; // @[Scheduler.scala 217:42]
  wire  may_pop_18 = a_pop_18 | b_pop_18 | c_pop_18; // @[Scheduler.scala 219:34]
  wire  bypass_18 = _bypass_T & bypassMatches_18; // @[Scheduler.scala 220:41]
  wire  will_reload_18 = abc_mshrs_17_io_schedule_bits_reload & (may_pop_18 | bypass_18); // @[Scheduler.scala 221:49]
  wire  _mshrs_17_io_allocate_bits_T_prio_0 = bypass_18 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_17_io_allocate_bits_T_prio_1 = bypass_18 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_17_io_allocate_bits_T_prio_2 = bypass_18 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_17_io_allocate_bits_T_opcode = bypass_18 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_17_io_allocate_bits_T_param = bypass_18 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_17_io_allocate_bits_T_size = bypass_18 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_17_io_allocate_bits_T_source = bypass_18 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_17_io_allocate_bits_T_tag = bypass_18 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_17_io_allocate_bits_T_offset = bypass_18 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_17_io_allocate_bits_T_put = bypass_18 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_19 = requests_io_valid[18]; // @[Scheduler.scala 214:34]
  wire  b_pop_19 = requests_io_valid[40]; // @[Scheduler.scala 215:34]
  wire  c_pop_19 = requests_io_valid[62]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_159 = b_pop_19 ? ~b_pop_19 : ~a_pop_19; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_160 = c_pop_19 | request_bits_prio_2 ? ~c_pop_19 : _bypassMatches_T_159; // @[Scheduler.scala 218:28]
  wire  bypassMatches_19 = lowerMatches1[18] & _bypassMatches_T_160; // @[Scheduler.scala 217:42]
  wire  may_pop_19 = a_pop_19 | b_pop_19 | c_pop_19; // @[Scheduler.scala 219:34]
  wire  bypass_19 = _bypass_T & bypassMatches_19; // @[Scheduler.scala 220:41]
  wire  will_reload_19 = abc_mshrs_18_io_schedule_bits_reload & (may_pop_19 | bypass_19); // @[Scheduler.scala 221:49]
  wire  _mshrs_18_io_allocate_bits_T_prio_0 = bypass_19 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_18_io_allocate_bits_T_prio_1 = bypass_19 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_18_io_allocate_bits_T_prio_2 = bypass_19 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_18_io_allocate_bits_T_opcode = bypass_19 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_18_io_allocate_bits_T_param = bypass_19 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_18_io_allocate_bits_T_size = bypass_19 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_18_io_allocate_bits_T_source = bypass_19 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_18_io_allocate_bits_T_tag = bypass_19 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_18_io_allocate_bits_T_offset = bypass_19 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_18_io_allocate_bits_T_put = bypass_19 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_20 = requests_io_valid[19]; // @[Scheduler.scala 214:34]
  wire  b_pop_20 = requests_io_valid[41]; // @[Scheduler.scala 215:34]
  wire  c_pop_20 = requests_io_valid[63]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_167 = b_pop_20 ? ~b_pop_20 : ~a_pop_20; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_168 = c_pop_20 | request_bits_prio_2 ? ~c_pop_20 : _bypassMatches_T_167; // @[Scheduler.scala 218:28]
  wire  bypassMatches_20 = lowerMatches1[19] & _bypassMatches_T_168; // @[Scheduler.scala 217:42]
  wire  may_pop_20 = a_pop_20 | b_pop_20 | c_pop_20; // @[Scheduler.scala 219:34]
  wire  bypass_20 = _bypass_T & bypassMatches_20; // @[Scheduler.scala 220:41]
  wire  will_reload_20 = abc_mshrs_19_io_schedule_bits_reload & (may_pop_20 | bypass_20); // @[Scheduler.scala 221:49]
  wire  _mshrs_19_io_allocate_bits_T_prio_0 = bypass_20 ? request_bits_prio_0 : requests_io_data_prio_0; // @[Scheduler.scala 222:30]
  wire  _mshrs_19_io_allocate_bits_T_prio_1 = bypass_20 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_19_io_allocate_bits_T_prio_2 = bypass_20 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_19_io_allocate_bits_T_opcode = bypass_20 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_19_io_allocate_bits_T_param = bypass_20 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_19_io_allocate_bits_T_size = bypass_20 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_19_io_allocate_bits_T_source = bypass_20 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_19_io_allocate_bits_T_tag = bypass_20 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_19_io_allocate_bits_T_offset = bypass_20 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_19_io_allocate_bits_T_put = bypass_20 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_21 = requests_io_valid[20]; // @[Scheduler.scala 214:34]
  wire  b_pop_21 = requests_io_valid[42]; // @[Scheduler.scala 215:34]
  wire  c_pop_21 = requests_io_valid[64]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_175 = b_pop_21 ? ~b_pop_21 : ~a_pop_21; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_176 = c_pop_21 | request_bits_prio_2 ? ~c_pop_21 : _bypassMatches_T_175; // @[Scheduler.scala 218:28]
  wire  bypassMatches_21 = lowerMatches1[20] & _bypassMatches_T_176; // @[Scheduler.scala 217:42]
  wire  may_pop_21 = a_pop_21 | b_pop_21 | c_pop_21; // @[Scheduler.scala 219:34]
  wire  bypass_21 = _bypass_T & bypassMatches_21; // @[Scheduler.scala 220:41]
  wire  will_reload_21 = bc_mshr_io_schedule_bits_reload & (may_pop_21 | bypass_21); // @[Scheduler.scala 221:49]
  wire  _mshrs_20_io_allocate_bits_T_prio_1 = bypass_21 ? 1'h0 : requests_io_data_prio_1; // @[Scheduler.scala 222:30]
  wire  _mshrs_20_io_allocate_bits_T_prio_2 = bypass_21 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_20_io_allocate_bits_T_opcode = bypass_21 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_20_io_allocate_bits_T_param = bypass_21 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_20_io_allocate_bits_T_size = bypass_21 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_20_io_allocate_bits_T_source = bypass_21 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_20_io_allocate_bits_T_tag = bypass_21 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_20_io_allocate_bits_T_offset = bypass_21 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_20_io_allocate_bits_T_put = bypass_21 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire  a_pop_22 = requests_io_valid[21]; // @[Scheduler.scala 214:34]
  wire  b_pop_22 = requests_io_valid[43]; // @[Scheduler.scala 215:34]
  wire  c_pop_22 = requests_io_valid[65]; // @[Scheduler.scala 216:34]
  wire  _bypassMatches_T_183 = b_pop_22 ? ~b_pop_22 : ~a_pop_22; // @[Scheduler.scala 218:71]
  wire  _bypassMatches_T_184 = c_pop_22 | request_bits_prio_2 ? ~c_pop_22 : _bypassMatches_T_183; // @[Scheduler.scala 218:28]
  wire  bypassMatches_22 = lowerMatches1[21] & _bypassMatches_T_184; // @[Scheduler.scala 217:42]
  wire  may_pop_22 = a_pop_22 | b_pop_22 | c_pop_22; // @[Scheduler.scala 219:34]
  wire  bypass_22 = _bypass_T & bypassMatches_22; // @[Scheduler.scala 220:41]
  wire  will_reload_22 = c_mshr_io_schedule_bits_reload & (may_pop_22 | bypass_22); // @[Scheduler.scala 221:49]
  wire  _mshrs_21_io_allocate_bits_T_prio_2 = bypass_22 ? request_bits_prio_2 : requests_io_data_prio_2; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_21_io_allocate_bits_T_opcode = bypass_22 ? request_bits_opcode : requests_io_data_opcode; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_21_io_allocate_bits_T_param = bypass_22 ? request_bits_param : requests_io_data_param; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_21_io_allocate_bits_T_size = bypass_22 ? request_bits_size : requests_io_data_size; // @[Scheduler.scala 222:30]
  wire [2:0] _mshrs_21_io_allocate_bits_T_source = bypass_22 ? request_bits_source : requests_io_data_source; // @[Scheduler.scala 222:30]
  wire [25:0] _mshrs_21_io_allocate_bits_T_tag = bypass_22 ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 222:30]
  wire [3:0] _mshrs_21_io_allocate_bits_T_offset = bypass_22 ? request_bits_offset : requests_io_data_offset; // @[Scheduler.scala 222:30]
  wire [5:0] _mshrs_21_io_allocate_bits_T_put = bypass_22 ? request_bits_put : requests_io_data_put; // @[Scheduler.scala 222:30]
  wire [65:0] _prio_requests_T = ~requests_io_valid; // @[Scheduler.scala 229:25]
  wire [65:0] _GEN_382 = {{22'd0}, requests_io_valid[65:22]}; // @[Scheduler.scala 229:44]
  wire [65:0] _prio_requests_T_2 = _prio_requests_T | _GEN_382; // @[Scheduler.scala 229:44]
  wire [65:0] _GEN_383 = {{44'd0}, requests_io_valid[65:44]}; // @[Scheduler.scala 229:82]
  wire [65:0] _prio_requests_T_4 = _prio_requests_T_2 | _GEN_383; // @[Scheduler.scala 229:82]
  wire [65:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala 229:23]
  wire [65:0] _pop_index_T_1 = _selected_requests_T & prio_requests; // @[Scheduler.scala 230:77]
  wire [1:0] pop_index_hi_1 = _pop_index_T_1[65:64]; // @[OneHot.scala 30:18]
  wire [63:0] pop_index_lo = _pop_index_T_1[63:0]; // @[OneHot.scala 31:18]
  wire  _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala 32:14]
  wire [63:0] _GEN_384 = {{62'd0}, pop_index_hi_1}; // @[OneHot.scala 32:28]
  wire [63:0] _pop_index_T_3 = _GEN_384 | pop_index_lo; // @[OneHot.scala 32:28]
  wire [31:0] pop_index_hi_2 = _pop_index_T_3[63:32]; // @[OneHot.scala 30:18]
  wire [31:0] pop_index_lo_1 = _pop_index_T_3[31:0]; // @[OneHot.scala 31:18]
  wire  _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala 32:14]
  wire [31:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala 32:28]
  wire [15:0] pop_index_hi_3 = _pop_index_T_5[31:16]; // @[OneHot.scala 30:18]
  wire [15:0] pop_index_lo_2 = _pop_index_T_5[15:0]; // @[OneHot.scala 31:18]
  wire  _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala 32:14]
  wire [15:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala 32:28]
  wire [7:0] pop_index_hi_4 = _pop_index_T_7[15:8]; // @[OneHot.scala 30:18]
  wire [7:0] pop_index_lo_3 = _pop_index_T_7[7:0]; // @[OneHot.scala 31:18]
  wire  _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala 32:14]
  wire [7:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala 32:28]
  wire [3:0] pop_index_hi_5 = _pop_index_T_9[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] pop_index_lo_4 = _pop_index_T_9[3:0]; // @[OneHot.scala 31:18]
  wire  _pop_index_T_10 = |pop_index_hi_5; // @[OneHot.scala 32:14]
  wire [3:0] _pop_index_T_11 = pop_index_hi_5 | pop_index_lo_4; // @[OneHot.scala 32:28]
  wire [1:0] pop_index_hi_6 = _pop_index_T_11[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] pop_index_lo_5 = _pop_index_T_11[1:0]; // @[OneHot.scala 31:18]
  wire  _pop_index_T_12 = |pop_index_hi_6; // @[OneHot.scala 32:14]
  wire [1:0] _pop_index_T_13 = pop_index_hi_6 | pop_index_lo_5; // @[OneHot.scala 32:28]
  wire [5:0] _pop_index_T_19 = {_pop_index_T_4,_pop_index_T_6,_pop_index_T_8,_pop_index_T_10,_pop_index_T_12,
    _pop_index_T_13[1]}; // @[Cat.scala 33:92]
  wire  mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala 237:45]
  wire [25:0] _mshr_uses_directory_T = bypass ? request_bits_tag : requests_io_data_tag; // @[Scheduler.scala 238:63]
  wire  mshr_uses_directory = will_reload & scheduleTag != _mshr_uses_directory_T; // @[Scheduler.scala 238:41]
  wire  alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala 251:44]
  wire [5:0] requests_io_push_bits_index_hi = lowerMatches1[21:16]; // @[OneHot.scala 30:18]
  wire [15:0] requests_io_push_bits_index_lo = lowerMatches1[15:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala 32:14]
  wire [15:0] _GEN_385 = {{10'd0}, requests_io_push_bits_index_hi}; // @[OneHot.scala 32:28]
  wire [15:0] _requests_io_push_bits_index_T_2 = _GEN_385 | requests_io_push_bits_index_lo; // @[OneHot.scala 32:28]
  wire [7:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[15:8]; // @[OneHot.scala 30:18]
  wire [7:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[7:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala 32:14]
  wire [7:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala 32:28]
  wire [3:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_4[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_4[3:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_5 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala 32:14]
  wire [3:0] _requests_io_push_bits_index_T_6 = requests_io_push_bits_index_hi_2 | requests_io_push_bits_index_lo_2; // @[OneHot.scala 32:28]
  wire [1:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_6[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_6[1:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_7 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala 32:14]
  wire [1:0] _requests_io_push_bits_index_T_8 = requests_io_push_bits_index_hi_3 | requests_io_push_bits_index_lo_3; // @[OneHot.scala 32:28]
  wire [4:0] _requests_io_push_bits_index_T_13 = {_requests_io_push_bits_index_T_1,_requests_io_push_bits_index_T_3,
    _requests_io_push_bits_index_T_5,_requests_io_push_bits_index_T_7,_requests_io_push_bits_index_T_8[1]}; // @[Cat.scala 33:92]
  wire [65:0] _requests_io_push_bits_index_T_31 = {lowerMatches1, 44'h0}; // @[Scheduler.scala 265:30]
  wire [1:0] requests_io_push_bits_index_hi_9 = _requests_io_push_bits_index_T_31[65:64]; // @[OneHot.scala 30:18]
  wire [63:0] requests_io_push_bits_index_lo_9 = _requests_io_push_bits_index_T_31[63:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_32 = |requests_io_push_bits_index_hi_9; // @[OneHot.scala 32:14]
  wire [63:0] _GEN_387 = {{62'd0}, requests_io_push_bits_index_hi_9}; // @[OneHot.scala 32:28]
  wire [63:0] _requests_io_push_bits_index_T_33 = _GEN_387 | requests_io_push_bits_index_lo_9; // @[OneHot.scala 32:28]
  wire [31:0] requests_io_push_bits_index_hi_10 = _requests_io_push_bits_index_T_33[63:32]; // @[OneHot.scala 30:18]
  wire [31:0] requests_io_push_bits_index_lo_10 = _requests_io_push_bits_index_T_33[31:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_34 = |requests_io_push_bits_index_hi_10; // @[OneHot.scala 32:14]
  wire [31:0] _requests_io_push_bits_index_T_35 = requests_io_push_bits_index_hi_10 | requests_io_push_bits_index_lo_10; // @[OneHot.scala 32:28]
  wire [15:0] requests_io_push_bits_index_hi_11 = _requests_io_push_bits_index_T_35[31:16]; // @[OneHot.scala 30:18]
  wire [15:0] requests_io_push_bits_index_lo_11 = _requests_io_push_bits_index_T_35[15:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_36 = |requests_io_push_bits_index_hi_11; // @[OneHot.scala 32:14]
  wire [15:0] _requests_io_push_bits_index_T_37 = requests_io_push_bits_index_hi_11 | requests_io_push_bits_index_lo_11; // @[OneHot.scala 32:28]
  wire [7:0] requests_io_push_bits_index_hi_12 = _requests_io_push_bits_index_T_37[15:8]; // @[OneHot.scala 30:18]
  wire [7:0] requests_io_push_bits_index_lo_12 = _requests_io_push_bits_index_T_37[7:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_38 = |requests_io_push_bits_index_hi_12; // @[OneHot.scala 32:14]
  wire [7:0] _requests_io_push_bits_index_T_39 = requests_io_push_bits_index_hi_12 | requests_io_push_bits_index_lo_12; // @[OneHot.scala 32:28]
  wire [3:0] requests_io_push_bits_index_hi_13 = _requests_io_push_bits_index_T_39[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] requests_io_push_bits_index_lo_13 = _requests_io_push_bits_index_T_39[3:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_40 = |requests_io_push_bits_index_hi_13; // @[OneHot.scala 32:14]
  wire [3:0] _requests_io_push_bits_index_T_41 = requests_io_push_bits_index_hi_13 | requests_io_push_bits_index_lo_13; // @[OneHot.scala 32:28]
  wire [1:0] requests_io_push_bits_index_hi_14 = _requests_io_push_bits_index_T_41[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] requests_io_push_bits_index_lo_14 = _requests_io_push_bits_index_T_41[1:0]; // @[OneHot.scala 31:18]
  wire  _requests_io_push_bits_index_T_42 = |requests_io_push_bits_index_hi_14; // @[OneHot.scala 32:14]
  wire [1:0] _requests_io_push_bits_index_T_43 = requests_io_push_bits_index_hi_14 | requests_io_push_bits_index_lo_14; // @[OneHot.scala 32:28]
  wire [6:0] _requests_io_push_bits_index_T_50 = {_requests_io_push_bits_index_T_32,_requests_io_push_bits_index_T_34,
    _requests_io_push_bits_index_T_36,_requests_io_push_bits_index_T_38,_requests_io_push_bits_index_T_40,
    _requests_io_push_bits_index_T_42,_requests_io_push_bits_index_T_43[1]}; // @[Cat.scala 33:92]
  wire [4:0] _requests_io_push_bits_index_T_51 = request_bits_prio_0 ? _requests_io_push_bits_index_T_13 : 5'h0; // @[Mux.scala 27:73]
  wire [6:0] _requests_io_push_bits_index_T_53 = request_bits_prio_2 ? _requests_io_push_bits_index_T_50 : 7'h0; // @[Mux.scala 27:73]
  wire [5:0] _requests_io_push_bits_index_T_54 = {{1'd0}, _requests_io_push_bits_index_T_51}; // @[Mux.scala 27:73]
  wire [6:0] _GEN_388 = {{1'd0}, _requests_io_push_bits_index_T_54}; // @[Mux.scala 27:73]
  wire [22:0] _mshr_insertOH_T_1 = {_mshr_free_T, 1'h0}; // @[package.scala 244:48]
  wire [21:0] _mshr_insertOH_T_3 = _mshr_free_T | _mshr_insertOH_T_1[21:0]; // @[package.scala 244:43]
  wire [23:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala 244:48]
  wire [21:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_4[21:0]; // @[package.scala 244:43]
  wire [25:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala 244:48]
  wire [21:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_7[21:0]; // @[package.scala 244:43]
  wire [29:0] _mshr_insertOH_T_10 = {_mshr_insertOH_T_9, 8'h0}; // @[package.scala 244:48]
  wire [21:0] _mshr_insertOH_T_12 = _mshr_insertOH_T_9 | _mshr_insertOH_T_10[21:0]; // @[package.scala 244:43]
  wire [37:0] _mshr_insertOH_T_13 = {_mshr_insertOH_T_12, 16'h0}; // @[package.scala 244:48]
  wire [21:0] _mshr_insertOH_T_15 = _mshr_insertOH_T_12 | _mshr_insertOH_T_13[21:0]; // @[package.scala 244:43]
  wire [22:0] _mshr_insertOH_T_17 = {_mshr_insertOH_T_15, 1'h0}; // @[Scheduler.scala 267:47]
  wire [22:0] _mshr_insertOH_T_18 = ~_mshr_insertOH_T_17; // @[Scheduler.scala 267:23]
  wire [22:0] _GEN_389 = {{1'd0}, _mshr_free_T}; // @[Scheduler.scala 267:53]
  wire [22:0] _mshr_insertOH_T_20 = _mshr_insertOH_T_18 & _GEN_389; // @[Scheduler.scala 267:53]
  wire [22:0] _GEN_390 = {{1'd0}, prioFilter}; // @[Scheduler.scala 267:69]
  wire [22:0] mshr_insertOH = _mshr_insertOH_T_20 & _GEN_390; // @[Scheduler.scala 267:69]
  wire  _GEN_295 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T | mshr_selectOH[21] &
    will_reload_22; // @[Scheduler.scala 225:25 269:83 270:27]
  wire  _GEN_298 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_prio_2 :
    _mshrs_21_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  wire [2:0] _GEN_300 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_opcode :
    _mshrs_21_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  wire [2:0] _GEN_301 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_param :
    _mshrs_21_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  wire [2:0] _GEN_302 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_size :
    _mshrs_21_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  wire [2:0] _GEN_303 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_source :
    _mshrs_21_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  wire [25:0] _GEN_304 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_tag :
    _mshrs_21_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  wire [3:0] _GEN_305 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_offset :
    _mshrs_21_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  wire [5:0] _GEN_306 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_put :
    _mshrs_21_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  wire [1:0] _GEN_307 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? request_bits_set :
    c_mshr_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  wire  _GEN_308 = request_valid & alloc & mshr_insertOH[21] & _request_alloc_cases_T ? 1'h0 :
    c_mshr_io_allocate_bits_tag == c_mshr_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  wire  _T_149 = ~reset; // @[Scheduler.scala 280:12]
  wire  _T_150 = ~_prioFilter_T; // @[Scheduler.scala 280:12]
  wire  _T_155 = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T; // @[Scheduler.scala 284:59]
  reg [22:0] directoryFanout; // @[Scheduler.scala 296:46]
  wire  _sinkC_io_way_T_3 = abc_mshrs_0_io_status_valid & abc_mshrs_0_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_5 = abc_mshrs_1_io_status_valid & abc_mshrs_1_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_7 = abc_mshrs_2_io_status_valid & abc_mshrs_2_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_9 = abc_mshrs_3_io_status_valid & abc_mshrs_3_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_11 = abc_mshrs_4_io_status_valid & abc_mshrs_4_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_13 = abc_mshrs_5_io_status_valid & abc_mshrs_5_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_15 = abc_mshrs_6_io_status_valid & abc_mshrs_6_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_17 = abc_mshrs_7_io_status_valid & abc_mshrs_7_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_19 = abc_mshrs_8_io_status_valid & abc_mshrs_8_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_21 = abc_mshrs_9_io_status_valid & abc_mshrs_9_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_23 = abc_mshrs_10_io_status_valid & abc_mshrs_10_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_25 = abc_mshrs_11_io_status_valid & abc_mshrs_11_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_27 = abc_mshrs_12_io_status_valid & abc_mshrs_12_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_29 = abc_mshrs_13_io_status_valid & abc_mshrs_13_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_31 = abc_mshrs_14_io_status_valid & abc_mshrs_14_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_33 = abc_mshrs_15_io_status_valid & abc_mshrs_15_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_35 = abc_mshrs_16_io_status_valid & abc_mshrs_16_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_37 = abc_mshrs_17_io_status_valid & abc_mshrs_17_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_39 = abc_mshrs_18_io_status_valid & abc_mshrs_18_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_41 = abc_mshrs_19_io_status_valid & abc_mshrs_19_io_status_bits_set == sinkC_io_set; // @[Scheduler.scala 306:50]
  wire  _sinkC_io_way_T_57 = _sinkC_io_way_T_33 & abc_mshrs_15_io_status_bits_way; // @[Mux.scala 27:73]
  wire  _sinkC_io_way_T_76 = _sinkC_io_way_T_3 & abc_mshrs_0_io_status_bits_way | _sinkC_io_way_T_5 &
    abc_mshrs_1_io_status_bits_way | _sinkC_io_way_T_7 & abc_mshrs_2_io_status_bits_way | _sinkC_io_way_T_9 &
    abc_mshrs_3_io_status_bits_way | _sinkC_io_way_T_11 & abc_mshrs_4_io_status_bits_way | _sinkC_io_way_T_13 &
    abc_mshrs_5_io_status_bits_way | _sinkC_io_way_T_15 & abc_mshrs_6_io_status_bits_way | _sinkC_io_way_T_17 &
    abc_mshrs_7_io_status_bits_way | _sinkC_io_way_T_19 & abc_mshrs_8_io_status_bits_way | _sinkC_io_way_T_21 &
    abc_mshrs_9_io_status_bits_way | _sinkC_io_way_T_23 & abc_mshrs_10_io_status_bits_way | _sinkC_io_way_T_25 &
    abc_mshrs_11_io_status_bits_way | _sinkC_io_way_T_27 & abc_mshrs_12_io_status_bits_way | _sinkC_io_way_T_29 &
    abc_mshrs_13_io_status_bits_way | _sinkC_io_way_T_31 & abc_mshrs_14_io_status_bits_way | _sinkC_io_way_T_57; // @[Mux.scala 27:73]
  wire  _sinkC_io_way_T_80 = _sinkC_io_way_T_76 | _sinkC_io_way_T_35 & abc_mshrs_16_io_status_bits_way |
    _sinkC_io_way_T_37 & abc_mshrs_17_io_status_bits_way | _sinkC_io_way_T_39 & abc_mshrs_18_io_status_bits_way |
    _sinkC_io_way_T_41 & abc_mshrs_19_io_status_bits_way; // @[Mux.scala 27:73]
  wire  _GEN_338 = 5'h1 == sinkD_io_source ? abc_mshrs_1_io_status_bits_way : abc_mshrs_0_io_status_bits_way; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_339 = 5'h2 == sinkD_io_source ? abc_mshrs_2_io_status_bits_way : _GEN_338; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_340 = 5'h3 == sinkD_io_source ? abc_mshrs_3_io_status_bits_way : _GEN_339; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_341 = 5'h4 == sinkD_io_source ? abc_mshrs_4_io_status_bits_way : _GEN_340; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_342 = 5'h5 == sinkD_io_source ? abc_mshrs_5_io_status_bits_way : _GEN_341; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_343 = 5'h6 == sinkD_io_source ? abc_mshrs_6_io_status_bits_way : _GEN_342; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_344 = 5'h7 == sinkD_io_source ? abc_mshrs_7_io_status_bits_way : _GEN_343; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_345 = 5'h8 == sinkD_io_source ? abc_mshrs_8_io_status_bits_way : _GEN_344; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_346 = 5'h9 == sinkD_io_source ? abc_mshrs_9_io_status_bits_way : _GEN_345; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_347 = 5'ha == sinkD_io_source ? abc_mshrs_10_io_status_bits_way : _GEN_346; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_348 = 5'hb == sinkD_io_source ? abc_mshrs_11_io_status_bits_way : _GEN_347; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_349 = 5'hc == sinkD_io_source ? abc_mshrs_12_io_status_bits_way : _GEN_348; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_350 = 5'hd == sinkD_io_source ? abc_mshrs_13_io_status_bits_way : _GEN_349; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_351 = 5'he == sinkD_io_source ? abc_mshrs_14_io_status_bits_way : _GEN_350; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_352 = 5'hf == sinkD_io_source ? abc_mshrs_15_io_status_bits_way : _GEN_351; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_353 = 5'h10 == sinkD_io_source ? abc_mshrs_16_io_status_bits_way : _GEN_352; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_354 = 5'h11 == sinkD_io_source ? abc_mshrs_17_io_status_bits_way : _GEN_353; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_355 = 5'h12 == sinkD_io_source ? abc_mshrs_18_io_status_bits_way : _GEN_354; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_356 = 5'h13 == sinkD_io_source ? abc_mshrs_19_io_status_bits_way : _GEN_355; // @[Scheduler.scala 308:{16,16}]
  wire  _GEN_357 = 5'h14 == sinkD_io_source ? bc_mshr_io_status_bits_way : _GEN_356; // @[Scheduler.scala 308:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_0 = abc_mshrs_0_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _sinkD_io_set_WIRE_1 = abc_mshrs_1_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_360 = 5'h1 == sinkD_io_source ? _sinkD_io_set_WIRE_1 : _sinkD_io_set_WIRE_0; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_2 = abc_mshrs_2_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_361 = 5'h2 == sinkD_io_source ? _sinkD_io_set_WIRE_2 : _GEN_360; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_3 = abc_mshrs_3_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_362 = 5'h3 == sinkD_io_source ? _sinkD_io_set_WIRE_3 : _GEN_361; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_4 = abc_mshrs_4_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_363 = 5'h4 == sinkD_io_source ? _sinkD_io_set_WIRE_4 : _GEN_362; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_5 = abc_mshrs_5_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_364 = 5'h5 == sinkD_io_source ? _sinkD_io_set_WIRE_5 : _GEN_363; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_6 = abc_mshrs_6_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_365 = 5'h6 == sinkD_io_source ? _sinkD_io_set_WIRE_6 : _GEN_364; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_7 = abc_mshrs_7_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_366 = 5'h7 == sinkD_io_source ? _sinkD_io_set_WIRE_7 : _GEN_365; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_8 = abc_mshrs_8_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_367 = 5'h8 == sinkD_io_source ? _sinkD_io_set_WIRE_8 : _GEN_366; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_9 = abc_mshrs_9_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_368 = 5'h9 == sinkD_io_source ? _sinkD_io_set_WIRE_9 : _GEN_367; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_10 = abc_mshrs_10_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_369 = 5'ha == sinkD_io_source ? _sinkD_io_set_WIRE_10 : _GEN_368; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_11 = abc_mshrs_11_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_370 = 5'hb == sinkD_io_source ? _sinkD_io_set_WIRE_11 : _GEN_369; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_12 = abc_mshrs_12_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_371 = 5'hc == sinkD_io_source ? _sinkD_io_set_WIRE_12 : _GEN_370; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_13 = abc_mshrs_13_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_372 = 5'hd == sinkD_io_source ? _sinkD_io_set_WIRE_13 : _GEN_371; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_14 = abc_mshrs_14_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_373 = 5'he == sinkD_io_source ? _sinkD_io_set_WIRE_14 : _GEN_372; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_15 = abc_mshrs_15_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_374 = 5'hf == sinkD_io_source ? _sinkD_io_set_WIRE_15 : _GEN_373; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_16 = abc_mshrs_16_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_375 = 5'h10 == sinkD_io_source ? _sinkD_io_set_WIRE_16 : _GEN_374; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_17 = abc_mshrs_17_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_376 = 5'h11 == sinkD_io_source ? _sinkD_io_set_WIRE_17 : _GEN_375; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_18 = abc_mshrs_18_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_377 = 5'h12 == sinkD_io_source ? _sinkD_io_set_WIRE_18 : _GEN_376; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_19 = abc_mshrs_19_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_378 = 5'h13 == sinkD_io_source ? _sinkD_io_set_WIRE_19 : _GEN_377; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_20 = bc_mshr_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  wire [1:0] _GEN_379 = 5'h14 == sinkD_io_source ? _sinkD_io_set_WIRE_20 : _GEN_378; // @[Scheduler.scala 309:{16,16}]
  wire [1:0] _sinkD_io_set_WIRE_21 = c_mshr_io_status_bits_set; // @[Scheduler.scala 309:{22,22}]
  SourceA sourceA ( // @[Scheduler.scala 38:23]
    .clock(sourceA_clock),
    .reset(sourceA_reset),
    .io_req_ready(sourceA_io_req_ready),
    .io_req_valid(sourceA_io_req_valid),
    .io_req_bits_tag(sourceA_io_req_bits_tag),
    .io_req_bits_set(sourceA_io_req_bits_set),
    .io_req_bits_param(sourceA_io_req_bits_param),
    .io_req_bits_source(sourceA_io_req_bits_source),
    .io_req_bits_block(sourceA_io_req_bits_block),
    .io_a_ready(sourceA_io_a_ready),
    .io_a_valid(sourceA_io_a_valid),
    .io_a_bits_opcode(sourceA_io_a_bits_opcode),
    .io_a_bits_param(sourceA_io_a_bits_param),
    .io_a_bits_size(sourceA_io_a_bits_size),
    .io_a_bits_source(sourceA_io_a_bits_source),
    .io_a_bits_address(sourceA_io_a_bits_address),
    .io_a_bits_mask(sourceA_io_a_bits_mask),
    .io_a_bits_data(sourceA_io_a_bits_data),
    .io_a_bits_corrupt(sourceA_io_a_bits_corrupt)
  );
  SourceB sourceB ( // @[Scheduler.scala 39:23]
    .clock(sourceB_clock),
    .reset(sourceB_reset),
    .io_req_ready(sourceB_io_req_ready),
    .io_req_valid(sourceB_io_req_valid),
    .io_req_bits_param(sourceB_io_req_bits_param),
    .io_req_bits_tag(sourceB_io_req_bits_tag),
    .io_req_bits_set(sourceB_io_req_bits_set),
    .io_req_bits_clients(sourceB_io_req_bits_clients),
    .io_b_ready(sourceB_io_b_ready),
    .io_b_valid(sourceB_io_b_valid),
    .io_b_bits_param(sourceB_io_b_bits_param),
    .io_b_bits_address(sourceB_io_b_bits_address)
  );
  SourceC sourceC ( // @[Scheduler.scala 40:23]
    .clock(sourceC_clock),
    .reset(sourceC_reset),
    .io_req_ready(sourceC_io_req_ready),
    .io_req_valid(sourceC_io_req_valid),
    .io_req_bits_opcode(sourceC_io_req_bits_opcode),
    .io_req_bits_param(sourceC_io_req_bits_param),
    .io_req_bits_source(sourceC_io_req_bits_source),
    .io_req_bits_tag(sourceC_io_req_bits_tag),
    .io_req_bits_set(sourceC_io_req_bits_set),
    .io_req_bits_way(sourceC_io_req_bits_way),
    .io_req_bits_dirty(sourceC_io_req_bits_dirty),
    .io_c_ready(sourceC_io_c_ready),
    .io_c_valid(sourceC_io_c_valid),
    .io_c_bits_opcode(sourceC_io_c_bits_opcode),
    .io_c_bits_param(sourceC_io_c_bits_param),
    .io_c_bits_size(sourceC_io_c_bits_size),
    .io_c_bits_source(sourceC_io_c_bits_source),
    .io_c_bits_address(sourceC_io_c_bits_address),
    .io_c_bits_data(sourceC_io_c_bits_data),
    .io_c_bits_corrupt(sourceC_io_c_bits_corrupt),
    .io_bs_adr_ready(sourceC_io_bs_adr_ready),
    .io_bs_adr_valid(sourceC_io_bs_adr_valid),
    .io_bs_adr_bits_way(sourceC_io_bs_adr_bits_way),
    .io_bs_adr_bits_set(sourceC_io_bs_adr_bits_set),
    .io_bs_adr_bits_beat(sourceC_io_bs_adr_bits_beat),
    .io_bs_dat_data(sourceC_io_bs_dat_data),
    .io_evict_req_set(sourceC_io_evict_req_set),
    .io_evict_req_way(sourceC_io_evict_req_way),
    .io_evict_safe(sourceC_io_evict_safe)
  );
  SourceD sourceD ( // @[Scheduler.scala 41:23]
    .clock(sourceD_clock),
    .reset(sourceD_reset),
    .io_req_ready(sourceD_io_req_ready),
    .io_req_valid(sourceD_io_req_valid),
    .io_req_bits_prio_0(sourceD_io_req_bits_prio_0),
    .io_req_bits_prio_2(sourceD_io_req_bits_prio_2),
    .io_req_bits_opcode(sourceD_io_req_bits_opcode),
    .io_req_bits_param(sourceD_io_req_bits_param),
    .io_req_bits_size(sourceD_io_req_bits_size),
    .io_req_bits_source(sourceD_io_req_bits_source),
    .io_req_bits_offset(sourceD_io_req_bits_offset),
    .io_req_bits_put(sourceD_io_req_bits_put),
    .io_req_bits_set(sourceD_io_req_bits_set),
    .io_req_bits_sink(sourceD_io_req_bits_sink),
    .io_req_bits_way(sourceD_io_req_bits_way),
    .io_req_bits_bad(sourceD_io_req_bits_bad),
    .io_d_ready(sourceD_io_d_ready),
    .io_d_valid(sourceD_io_d_valid),
    .io_d_bits_opcode(sourceD_io_d_bits_opcode),
    .io_d_bits_param(sourceD_io_d_bits_param),
    .io_d_bits_size(sourceD_io_d_bits_size),
    .io_d_bits_source(sourceD_io_d_bits_source),
    .io_d_bits_sink(sourceD_io_d_bits_sink),
    .io_d_bits_denied(sourceD_io_d_bits_denied),
    .io_d_bits_data(sourceD_io_d_bits_data),
    .io_d_bits_corrupt(sourceD_io_d_bits_corrupt),
    .io_pb_pop_ready(sourceD_io_pb_pop_ready),
    .io_pb_pop_valid(sourceD_io_pb_pop_valid),
    .io_pb_pop_bits_index(sourceD_io_pb_pop_bits_index),
    .io_pb_pop_bits_last(sourceD_io_pb_pop_bits_last),
    .io_pb_beat_data(sourceD_io_pb_beat_data),
    .io_pb_beat_mask(sourceD_io_pb_beat_mask),
    .io_pb_beat_corrupt(sourceD_io_pb_beat_corrupt),
    .io_rel_pop_ready(sourceD_io_rel_pop_ready),
    .io_rel_pop_valid(sourceD_io_rel_pop_valid),
    .io_rel_pop_bits_index(sourceD_io_rel_pop_bits_index),
    .io_rel_pop_bits_last(sourceD_io_rel_pop_bits_last),
    .io_rel_beat_data(sourceD_io_rel_beat_data),
    .io_rel_beat_corrupt(sourceD_io_rel_beat_corrupt),
    .io_bs_radr_ready(sourceD_io_bs_radr_ready),
    .io_bs_radr_valid(sourceD_io_bs_radr_valid),
    .io_bs_radr_bits_way(sourceD_io_bs_radr_bits_way),
    .io_bs_radr_bits_set(sourceD_io_bs_radr_bits_set),
    .io_bs_radr_bits_beat(sourceD_io_bs_radr_bits_beat),
    .io_bs_radr_bits_mask(sourceD_io_bs_radr_bits_mask),
    .io_bs_rdat_data(sourceD_io_bs_rdat_data),
    .io_bs_wadr_ready(sourceD_io_bs_wadr_ready),
    .io_bs_wadr_valid(sourceD_io_bs_wadr_valid),
    .io_bs_wadr_bits_way(sourceD_io_bs_wadr_bits_way),
    .io_bs_wadr_bits_set(sourceD_io_bs_wadr_bits_set),
    .io_bs_wadr_bits_beat(sourceD_io_bs_wadr_bits_beat),
    .io_bs_wadr_bits_mask(sourceD_io_bs_wadr_bits_mask),
    .io_bs_wdat_data(sourceD_io_bs_wdat_data),
    .io_evict_req_set(sourceD_io_evict_req_set),
    .io_evict_req_way(sourceD_io_evict_req_way),
    .io_evict_safe(sourceD_io_evict_safe),
    .io_grant_req_set(sourceD_io_grant_req_set),
    .io_grant_req_way(sourceD_io_grant_req_way),
    .io_grant_safe(sourceD_io_grant_safe)
  );
  SourceE sourceE ( // @[Scheduler.scala 42:23]
    .clock(sourceE_clock),
    .reset(sourceE_reset),
    .io_req_ready(sourceE_io_req_ready),
    .io_req_valid(sourceE_io_req_valid),
    .io_req_bits_sink(sourceE_io_req_bits_sink),
    .io_e_valid(sourceE_io_e_valid),
    .io_e_bits_sink(sourceE_io_e_bits_sink)
  );
  SinkA sinkA ( // @[Scheduler.scala 52:21]
    .clock(sinkA_clock),
    .reset(sinkA_reset),
    .io_req_ready(sinkA_io_req_ready),
    .io_req_valid(sinkA_io_req_valid),
    .io_req_bits_opcode(sinkA_io_req_bits_opcode),
    .io_req_bits_param(sinkA_io_req_bits_param),
    .io_req_bits_size(sinkA_io_req_bits_size),
    .io_req_bits_source(sinkA_io_req_bits_source),
    .io_req_bits_tag(sinkA_io_req_bits_tag),
    .io_req_bits_offset(sinkA_io_req_bits_offset),
    .io_req_bits_put(sinkA_io_req_bits_put),
    .io_req_bits_set(sinkA_io_req_bits_set),
    .io_a_ready(sinkA_io_a_ready),
    .io_a_valid(sinkA_io_a_valid),
    .io_a_bits_opcode(sinkA_io_a_bits_opcode),
    .io_a_bits_param(sinkA_io_a_bits_param),
    .io_a_bits_size(sinkA_io_a_bits_size),
    .io_a_bits_source(sinkA_io_a_bits_source),
    .io_a_bits_address(sinkA_io_a_bits_address),
    .io_a_bits_mask(sinkA_io_a_bits_mask),
    .io_a_bits_data(sinkA_io_a_bits_data),
    .io_a_bits_corrupt(sinkA_io_a_bits_corrupt),
    .io_pb_pop_ready(sinkA_io_pb_pop_ready),
    .io_pb_pop_valid(sinkA_io_pb_pop_valid),
    .io_pb_pop_bits_index(sinkA_io_pb_pop_bits_index),
    .io_pb_pop_bits_last(sinkA_io_pb_pop_bits_last),
    .io_pb_beat_data(sinkA_io_pb_beat_data),
    .io_pb_beat_mask(sinkA_io_pb_beat_mask),
    .io_pb_beat_corrupt(sinkA_io_pb_beat_corrupt)
  );
  SinkC sinkC ( // @[Scheduler.scala 53:21]
    .clock(sinkC_clock),
    .reset(sinkC_reset),
    .io_req_ready(sinkC_io_req_ready),
    .io_req_valid(sinkC_io_req_valid),
    .io_req_bits_opcode(sinkC_io_req_bits_opcode),
    .io_req_bits_param(sinkC_io_req_bits_param),
    .io_req_bits_size(sinkC_io_req_bits_size),
    .io_req_bits_source(sinkC_io_req_bits_source),
    .io_req_bits_tag(sinkC_io_req_bits_tag),
    .io_req_bits_offset(sinkC_io_req_bits_offset),
    .io_req_bits_put(sinkC_io_req_bits_put),
    .io_req_bits_set(sinkC_io_req_bits_set),
    .io_resp_valid(sinkC_io_resp_valid),
    .io_resp_bits_last(sinkC_io_resp_bits_last),
    .io_resp_bits_set(sinkC_io_resp_bits_set),
    .io_resp_bits_tag(sinkC_io_resp_bits_tag),
    .io_resp_bits_source(sinkC_io_resp_bits_source),
    .io_resp_bits_param(sinkC_io_resp_bits_param),
    .io_resp_bits_data(sinkC_io_resp_bits_data),
    .io_c_ready(sinkC_io_c_ready),
    .io_c_valid(sinkC_io_c_valid),
    .io_c_bits_opcode(sinkC_io_c_bits_opcode),
    .io_c_bits_param(sinkC_io_c_bits_param),
    .io_c_bits_size(sinkC_io_c_bits_size),
    .io_c_bits_address(sinkC_io_c_bits_address),
    .io_c_bits_data(sinkC_io_c_bits_data),
    .io_c_bits_corrupt(sinkC_io_c_bits_corrupt),
    .io_set(sinkC_io_set),
    .io_way(sinkC_io_way),
    .io_bs_adr_ready(sinkC_io_bs_adr_ready),
    .io_bs_adr_valid(sinkC_io_bs_adr_valid),
    .io_bs_adr_bits_noop(sinkC_io_bs_adr_bits_noop),
    .io_bs_adr_bits_way(sinkC_io_bs_adr_bits_way),
    .io_bs_adr_bits_set(sinkC_io_bs_adr_bits_set),
    .io_bs_adr_bits_beat(sinkC_io_bs_adr_bits_beat),
    .io_bs_adr_bits_mask(sinkC_io_bs_adr_bits_mask),
    .io_bs_dat_data(sinkC_io_bs_dat_data),
    .io_rel_pop_ready(sinkC_io_rel_pop_ready),
    .io_rel_pop_valid(sinkC_io_rel_pop_valid),
    .io_rel_pop_bits_index(sinkC_io_rel_pop_bits_index),
    .io_rel_pop_bits_last(sinkC_io_rel_pop_bits_last),
    .io_rel_beat_data(sinkC_io_rel_beat_data),
    .io_rel_beat_corrupt(sinkC_io_rel_beat_corrupt)
  );
  SinkD sinkD ( // @[Scheduler.scala 54:21]
    .clock(sinkD_clock),
    .reset(sinkD_reset),
    .io_resp_valid(sinkD_io_resp_valid),
    .io_resp_bits_last(sinkD_io_resp_bits_last),
    .io_resp_bits_opcode(sinkD_io_resp_bits_opcode),
    .io_resp_bits_param(sinkD_io_resp_bits_param),
    .io_resp_bits_source(sinkD_io_resp_bits_source),
    .io_resp_bits_sink(sinkD_io_resp_bits_sink),
    .io_resp_bits_denied(sinkD_io_resp_bits_denied),
    .io_d_ready(sinkD_io_d_ready),
    .io_d_valid(sinkD_io_d_valid),
    .io_d_bits_opcode(sinkD_io_d_bits_opcode),
    .io_d_bits_param(sinkD_io_d_bits_param),
    .io_d_bits_size(sinkD_io_d_bits_size),
    .io_d_bits_source(sinkD_io_d_bits_source),
    .io_d_bits_sink(sinkD_io_d_bits_sink),
    .io_d_bits_denied(sinkD_io_d_bits_denied),
    .io_d_bits_data(sinkD_io_d_bits_data),
    .io_d_bits_corrupt(sinkD_io_d_bits_corrupt),
    .io_source(sinkD_io_source),
    .io_way(sinkD_io_way),
    .io_set(sinkD_io_set),
    .io_bs_adr_ready(sinkD_io_bs_adr_ready),
    .io_bs_adr_valid(sinkD_io_bs_adr_valid),
    .io_bs_adr_bits_noop(sinkD_io_bs_adr_bits_noop),
    .io_bs_adr_bits_way(sinkD_io_bs_adr_bits_way),
    .io_bs_adr_bits_set(sinkD_io_bs_adr_bits_set),
    .io_bs_adr_bits_beat(sinkD_io_bs_adr_bits_beat),
    .io_bs_dat_data(sinkD_io_bs_dat_data),
    .io_grant_req_set(sinkD_io_grant_req_set),
    .io_grant_req_way(sinkD_io_grant_req_way),
    .io_grant_safe(sinkD_io_grant_safe)
  );
  SinkE sinkE ( // @[Scheduler.scala 55:21]
    .io_resp_valid(sinkE_io_resp_valid),
    .io_resp_bits_sink(sinkE_io_resp_bits_sink),
    .io_e_valid(sinkE_io_e_valid),
    .io_e_bits_sink(sinkE_io_e_bits_sink)
  );
  Directory directory ( // @[Scheduler.scala 66:25]
    .clock(directory_clock),
    .reset(directory_reset),
    .io_write_ready(directory_io_write_ready),
    .io_write_valid(directory_io_write_valid),
    .io_write_bits_set(directory_io_write_bits_set),
    .io_write_bits_way(directory_io_write_bits_way),
    .io_write_bits_data_dirty(directory_io_write_bits_data_dirty),
    .io_write_bits_data_state(directory_io_write_bits_data_state),
    .io_write_bits_data_clients(directory_io_write_bits_data_clients),
    .io_write_bits_data_tag(directory_io_write_bits_data_tag),
    .io_read_valid(directory_io_read_valid),
    .io_read_bits_set(directory_io_read_bits_set),
    .io_read_bits_tag(directory_io_read_bits_tag),
    .io_result_bits_dirty(directory_io_result_bits_dirty),
    .io_result_bits_state(directory_io_result_bits_state),
    .io_result_bits_clients(directory_io_result_bits_clients),
    .io_result_bits_tag(directory_io_result_bits_tag),
    .io_result_bits_hit(directory_io_result_bits_hit),
    .io_result_bits_way(directory_io_result_bits_way),
    .io_ready(directory_io_ready)
  );
  BankedStore bankedStore ( // @[Scheduler.scala 67:27]
    .clock(bankedStore_clock),
    .io_sinkC_adr_ready(bankedStore_io_sinkC_adr_ready),
    .io_sinkC_adr_valid(bankedStore_io_sinkC_adr_valid),
    .io_sinkC_adr_bits_noop(bankedStore_io_sinkC_adr_bits_noop),
    .io_sinkC_adr_bits_way(bankedStore_io_sinkC_adr_bits_way),
    .io_sinkC_adr_bits_set(bankedStore_io_sinkC_adr_bits_set),
    .io_sinkC_adr_bits_beat(bankedStore_io_sinkC_adr_bits_beat),
    .io_sinkC_adr_bits_mask(bankedStore_io_sinkC_adr_bits_mask),
    .io_sinkC_dat_data(bankedStore_io_sinkC_dat_data),
    .io_sinkD_adr_ready(bankedStore_io_sinkD_adr_ready),
    .io_sinkD_adr_valid(bankedStore_io_sinkD_adr_valid),
    .io_sinkD_adr_bits_noop(bankedStore_io_sinkD_adr_bits_noop),
    .io_sinkD_adr_bits_way(bankedStore_io_sinkD_adr_bits_way),
    .io_sinkD_adr_bits_set(bankedStore_io_sinkD_adr_bits_set),
    .io_sinkD_adr_bits_beat(bankedStore_io_sinkD_adr_bits_beat),
    .io_sinkD_dat_data(bankedStore_io_sinkD_dat_data),
    .io_sourceC_adr_ready(bankedStore_io_sourceC_adr_ready),
    .io_sourceC_adr_valid(bankedStore_io_sourceC_adr_valid),
    .io_sourceC_adr_bits_way(bankedStore_io_sourceC_adr_bits_way),
    .io_sourceC_adr_bits_set(bankedStore_io_sourceC_adr_bits_set),
    .io_sourceC_adr_bits_beat(bankedStore_io_sourceC_adr_bits_beat),
    .io_sourceC_dat_data(bankedStore_io_sourceC_dat_data),
    .io_sourceD_radr_ready(bankedStore_io_sourceD_radr_ready),
    .io_sourceD_radr_valid(bankedStore_io_sourceD_radr_valid),
    .io_sourceD_radr_bits_way(bankedStore_io_sourceD_radr_bits_way),
    .io_sourceD_radr_bits_set(bankedStore_io_sourceD_radr_bits_set),
    .io_sourceD_radr_bits_beat(bankedStore_io_sourceD_radr_bits_beat),
    .io_sourceD_radr_bits_mask(bankedStore_io_sourceD_radr_bits_mask),
    .io_sourceD_rdat_data(bankedStore_io_sourceD_rdat_data),
    .io_sourceD_wadr_ready(bankedStore_io_sourceD_wadr_ready),
    .io_sourceD_wadr_valid(bankedStore_io_sourceD_wadr_valid),
    .io_sourceD_wadr_bits_way(bankedStore_io_sourceD_wadr_bits_way),
    .io_sourceD_wadr_bits_set(bankedStore_io_sourceD_wadr_bits_set),
    .io_sourceD_wadr_bits_beat(bankedStore_io_sourceD_wadr_bits_beat),
    .io_sourceD_wadr_bits_mask(bankedStore_io_sourceD_wadr_bits_mask),
    .io_sourceD_wdat_data(bankedStore_io_sourceD_wdat_data)
  );
  ListBuffer_2 requests ( // @[Scheduler.scala 68:24]
    .clock(requests_clock),
    .reset(requests_reset),
    .io_push_ready(requests_io_push_ready),
    .io_push_valid(requests_io_push_valid),
    .io_push_bits_index(requests_io_push_bits_index),
    .io_push_bits_data_prio_0(requests_io_push_bits_data_prio_0),
    .io_push_bits_data_prio_2(requests_io_push_bits_data_prio_2),
    .io_push_bits_data_opcode(requests_io_push_bits_data_opcode),
    .io_push_bits_data_param(requests_io_push_bits_data_param),
    .io_push_bits_data_size(requests_io_push_bits_data_size),
    .io_push_bits_data_source(requests_io_push_bits_data_source),
    .io_push_bits_data_tag(requests_io_push_bits_data_tag),
    .io_push_bits_data_offset(requests_io_push_bits_data_offset),
    .io_push_bits_data_put(requests_io_push_bits_data_put),
    .io_valid(requests_io_valid),
    .io_pop_valid(requests_io_pop_valid),
    .io_pop_bits(requests_io_pop_bits),
    .io_data_prio_0(requests_io_data_prio_0),
    .io_data_prio_1(requests_io_data_prio_1),
    .io_data_prio_2(requests_io_data_prio_2),
    .io_data_opcode(requests_io_data_opcode),
    .io_data_param(requests_io_data_param),
    .io_data_size(requests_io_data_size),
    .io_data_source(requests_io_data_source),
    .io_data_tag(requests_io_data_tag),
    .io_data_offset(requests_io_data_offset),
    .io_data_put(requests_io_data_put)
  );
  MSHR abc_mshrs_0 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_0_clock),
    .reset(abc_mshrs_0_reset),
    .io_allocate_valid(abc_mshrs_0_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_0_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_0_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_0_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_0_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_0_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_0_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_0_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_0_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_0_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_0_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_0_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_0_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_0_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_0_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_0_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_0_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_0_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_0_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_0_io_directory_bits_way),
    .io_status_valid(abc_mshrs_0_io_status_valid),
    .io_status_bits_set(abc_mshrs_0_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_0_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_0_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_0_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_0_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_0_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_0_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_0_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_0_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_0_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_0_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_0_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_0_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_0_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_0_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_0_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_0_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_0_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_0_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_0_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_0_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_0_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_0_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_0_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_0_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_0_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_0_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_0_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_0_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_0_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_0_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_0_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_0_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_0_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_0_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_0_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_0_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_0_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_0_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_0_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_0_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_0_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_0_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_0_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_0_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_0_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_0_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_0_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_0_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_0_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_0_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_0_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_0_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_0_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_0_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_0_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_0_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_0_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_0_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_0_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_0_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_0_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_0_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_0_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_0_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_0_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_0_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_0_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_1 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_1_clock),
    .reset(abc_mshrs_1_reset),
    .io_allocate_valid(abc_mshrs_1_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_1_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_1_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_1_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_1_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_1_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_1_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_1_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_1_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_1_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_1_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_1_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_1_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_1_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_1_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_1_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_1_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_1_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_1_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_1_io_directory_bits_way),
    .io_status_valid(abc_mshrs_1_io_status_valid),
    .io_status_bits_set(abc_mshrs_1_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_1_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_1_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_1_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_1_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_1_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_1_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_1_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_1_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_1_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_1_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_1_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_1_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_1_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_1_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_1_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_1_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_1_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_1_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_1_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_1_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_1_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_1_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_1_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_1_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_1_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_1_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_1_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_1_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_1_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_1_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_1_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_1_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_1_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_1_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_1_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_1_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_1_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_1_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_1_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_1_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_1_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_1_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_1_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_1_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_1_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_1_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_1_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_1_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_1_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_1_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_1_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_1_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_1_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_1_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_1_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_1_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_1_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_1_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_1_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_1_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_1_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_1_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_1_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_1_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_1_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_1_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_1_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_2 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_2_clock),
    .reset(abc_mshrs_2_reset),
    .io_allocate_valid(abc_mshrs_2_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_2_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_2_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_2_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_2_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_2_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_2_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_2_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_2_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_2_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_2_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_2_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_2_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_2_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_2_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_2_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_2_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_2_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_2_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_2_io_directory_bits_way),
    .io_status_valid(abc_mshrs_2_io_status_valid),
    .io_status_bits_set(abc_mshrs_2_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_2_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_2_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_2_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_2_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_2_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_2_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_2_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_2_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_2_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_2_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_2_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_2_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_2_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_2_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_2_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_2_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_2_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_2_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_2_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_2_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_2_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_2_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_2_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_2_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_2_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_2_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_2_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_2_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_2_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_2_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_2_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_2_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_2_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_2_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_2_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_2_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_2_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_2_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_2_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_2_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_2_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_2_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_2_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_2_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_2_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_2_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_2_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_2_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_2_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_2_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_2_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_2_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_2_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_2_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_2_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_2_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_2_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_2_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_2_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_2_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_2_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_2_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_2_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_2_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_2_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_2_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_2_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_3 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_3_clock),
    .reset(abc_mshrs_3_reset),
    .io_allocate_valid(abc_mshrs_3_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_3_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_3_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_3_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_3_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_3_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_3_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_3_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_3_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_3_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_3_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_3_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_3_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_3_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_3_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_3_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_3_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_3_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_3_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_3_io_directory_bits_way),
    .io_status_valid(abc_mshrs_3_io_status_valid),
    .io_status_bits_set(abc_mshrs_3_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_3_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_3_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_3_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_3_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_3_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_3_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_3_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_3_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_3_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_3_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_3_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_3_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_3_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_3_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_3_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_3_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_3_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_3_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_3_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_3_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_3_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_3_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_3_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_3_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_3_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_3_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_3_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_3_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_3_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_3_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_3_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_3_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_3_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_3_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_3_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_3_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_3_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_3_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_3_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_3_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_3_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_3_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_3_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_3_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_3_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_3_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_3_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_3_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_3_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_3_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_3_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_3_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_3_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_3_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_3_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_3_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_3_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_3_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_3_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_3_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_3_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_3_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_3_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_3_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_3_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_3_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_3_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_4 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_4_clock),
    .reset(abc_mshrs_4_reset),
    .io_allocate_valid(abc_mshrs_4_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_4_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_4_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_4_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_4_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_4_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_4_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_4_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_4_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_4_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_4_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_4_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_4_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_4_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_4_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_4_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_4_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_4_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_4_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_4_io_directory_bits_way),
    .io_status_valid(abc_mshrs_4_io_status_valid),
    .io_status_bits_set(abc_mshrs_4_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_4_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_4_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_4_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_4_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_4_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_4_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_4_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_4_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_4_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_4_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_4_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_4_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_4_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_4_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_4_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_4_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_4_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_4_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_4_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_4_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_4_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_4_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_4_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_4_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_4_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_4_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_4_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_4_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_4_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_4_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_4_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_4_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_4_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_4_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_4_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_4_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_4_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_4_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_4_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_4_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_4_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_4_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_4_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_4_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_4_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_4_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_4_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_4_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_4_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_4_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_4_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_4_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_4_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_4_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_4_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_4_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_4_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_4_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_4_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_4_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_4_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_4_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_4_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_4_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_4_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_4_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_4_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_5 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_5_clock),
    .reset(abc_mshrs_5_reset),
    .io_allocate_valid(abc_mshrs_5_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_5_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_5_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_5_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_5_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_5_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_5_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_5_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_5_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_5_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_5_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_5_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_5_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_5_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_5_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_5_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_5_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_5_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_5_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_5_io_directory_bits_way),
    .io_status_valid(abc_mshrs_5_io_status_valid),
    .io_status_bits_set(abc_mshrs_5_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_5_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_5_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_5_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_5_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_5_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_5_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_5_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_5_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_5_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_5_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_5_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_5_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_5_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_5_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_5_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_5_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_5_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_5_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_5_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_5_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_5_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_5_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_5_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_5_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_5_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_5_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_5_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_5_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_5_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_5_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_5_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_5_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_5_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_5_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_5_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_5_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_5_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_5_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_5_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_5_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_5_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_5_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_5_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_5_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_5_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_5_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_5_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_5_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_5_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_5_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_5_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_5_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_5_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_5_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_5_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_5_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_5_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_5_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_5_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_5_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_5_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_5_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_5_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_5_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_5_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_5_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_5_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_6 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_6_clock),
    .reset(abc_mshrs_6_reset),
    .io_allocate_valid(abc_mshrs_6_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_6_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_6_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_6_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_6_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_6_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_6_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_6_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_6_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_6_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_6_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_6_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_6_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_6_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_6_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_6_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_6_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_6_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_6_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_6_io_directory_bits_way),
    .io_status_valid(abc_mshrs_6_io_status_valid),
    .io_status_bits_set(abc_mshrs_6_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_6_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_6_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_6_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_6_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_6_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_6_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_6_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_6_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_6_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_6_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_6_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_6_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_6_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_6_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_6_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_6_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_6_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_6_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_6_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_6_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_6_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_6_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_6_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_6_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_6_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_6_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_6_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_6_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_6_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_6_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_6_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_6_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_6_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_6_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_6_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_6_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_6_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_6_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_6_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_6_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_6_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_6_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_6_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_6_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_6_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_6_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_6_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_6_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_6_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_6_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_6_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_6_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_6_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_6_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_6_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_6_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_6_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_6_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_6_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_6_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_6_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_6_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_6_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_6_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_6_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_6_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_6_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_7 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_7_clock),
    .reset(abc_mshrs_7_reset),
    .io_allocate_valid(abc_mshrs_7_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_7_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_7_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_7_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_7_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_7_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_7_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_7_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_7_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_7_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_7_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_7_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_7_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_7_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_7_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_7_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_7_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_7_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_7_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_7_io_directory_bits_way),
    .io_status_valid(abc_mshrs_7_io_status_valid),
    .io_status_bits_set(abc_mshrs_7_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_7_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_7_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_7_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_7_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_7_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_7_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_7_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_7_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_7_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_7_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_7_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_7_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_7_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_7_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_7_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_7_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_7_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_7_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_7_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_7_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_7_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_7_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_7_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_7_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_7_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_7_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_7_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_7_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_7_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_7_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_7_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_7_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_7_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_7_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_7_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_7_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_7_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_7_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_7_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_7_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_7_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_7_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_7_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_7_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_7_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_7_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_7_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_7_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_7_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_7_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_7_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_7_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_7_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_7_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_7_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_7_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_7_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_7_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_7_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_7_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_7_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_7_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_7_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_7_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_7_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_7_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_7_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_8 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_8_clock),
    .reset(abc_mshrs_8_reset),
    .io_allocate_valid(abc_mshrs_8_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_8_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_8_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_8_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_8_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_8_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_8_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_8_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_8_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_8_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_8_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_8_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_8_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_8_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_8_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_8_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_8_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_8_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_8_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_8_io_directory_bits_way),
    .io_status_valid(abc_mshrs_8_io_status_valid),
    .io_status_bits_set(abc_mshrs_8_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_8_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_8_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_8_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_8_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_8_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_8_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_8_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_8_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_8_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_8_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_8_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_8_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_8_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_8_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_8_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_8_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_8_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_8_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_8_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_8_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_8_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_8_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_8_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_8_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_8_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_8_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_8_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_8_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_8_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_8_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_8_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_8_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_8_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_8_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_8_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_8_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_8_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_8_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_8_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_8_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_8_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_8_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_8_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_8_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_8_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_8_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_8_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_8_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_8_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_8_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_8_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_8_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_8_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_8_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_8_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_8_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_8_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_8_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_8_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_8_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_8_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_8_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_8_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_8_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_8_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_8_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_8_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_9 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_9_clock),
    .reset(abc_mshrs_9_reset),
    .io_allocate_valid(abc_mshrs_9_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_9_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_9_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_9_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_9_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_9_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_9_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_9_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_9_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_9_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_9_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_9_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_9_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_9_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_9_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_9_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_9_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_9_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_9_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_9_io_directory_bits_way),
    .io_status_valid(abc_mshrs_9_io_status_valid),
    .io_status_bits_set(abc_mshrs_9_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_9_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_9_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_9_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_9_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_9_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_9_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_9_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_9_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_9_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_9_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_9_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_9_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_9_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_9_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_9_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_9_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_9_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_9_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_9_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_9_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_9_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_9_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_9_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_9_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_9_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_9_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_9_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_9_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_9_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_9_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_9_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_9_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_9_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_9_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_9_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_9_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_9_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_9_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_9_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_9_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_9_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_9_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_9_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_9_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_9_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_9_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_9_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_9_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_9_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_9_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_9_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_9_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_9_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_9_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_9_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_9_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_9_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_9_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_9_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_9_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_9_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_9_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_9_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_9_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_9_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_9_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_9_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_10 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_10_clock),
    .reset(abc_mshrs_10_reset),
    .io_allocate_valid(abc_mshrs_10_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_10_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_10_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_10_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_10_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_10_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_10_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_10_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_10_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_10_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_10_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_10_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_10_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_10_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_10_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_10_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_10_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_10_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_10_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_10_io_directory_bits_way),
    .io_status_valid(abc_mshrs_10_io_status_valid),
    .io_status_bits_set(abc_mshrs_10_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_10_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_10_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_10_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_10_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_10_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_10_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_10_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_10_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_10_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_10_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_10_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_10_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_10_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_10_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_10_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_10_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_10_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_10_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_10_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_10_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_10_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_10_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_10_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_10_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_10_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_10_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_10_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_10_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_10_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_10_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_10_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_10_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_10_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_10_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_10_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_10_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_10_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_10_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_10_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_10_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_10_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_10_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_10_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_10_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_10_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_10_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_10_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_10_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_10_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_10_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_10_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_10_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_10_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_10_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_10_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_10_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_10_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_10_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_10_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_10_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_10_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_10_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_10_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_10_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_10_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_10_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_10_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_11 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_11_clock),
    .reset(abc_mshrs_11_reset),
    .io_allocate_valid(abc_mshrs_11_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_11_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_11_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_11_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_11_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_11_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_11_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_11_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_11_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_11_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_11_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_11_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_11_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_11_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_11_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_11_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_11_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_11_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_11_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_11_io_directory_bits_way),
    .io_status_valid(abc_mshrs_11_io_status_valid),
    .io_status_bits_set(abc_mshrs_11_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_11_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_11_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_11_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_11_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_11_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_11_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_11_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_11_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_11_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_11_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_11_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_11_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_11_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_11_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_11_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_11_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_11_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_11_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_11_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_11_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_11_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_11_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_11_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_11_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_11_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_11_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_11_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_11_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_11_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_11_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_11_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_11_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_11_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_11_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_11_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_11_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_11_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_11_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_11_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_11_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_11_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_11_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_11_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_11_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_11_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_11_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_11_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_11_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_11_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_11_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_11_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_11_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_11_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_11_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_11_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_11_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_11_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_11_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_11_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_11_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_11_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_11_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_11_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_11_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_11_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_11_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_11_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_12 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_12_clock),
    .reset(abc_mshrs_12_reset),
    .io_allocate_valid(abc_mshrs_12_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_12_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_12_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_12_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_12_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_12_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_12_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_12_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_12_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_12_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_12_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_12_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_12_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_12_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_12_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_12_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_12_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_12_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_12_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_12_io_directory_bits_way),
    .io_status_valid(abc_mshrs_12_io_status_valid),
    .io_status_bits_set(abc_mshrs_12_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_12_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_12_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_12_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_12_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_12_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_12_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_12_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_12_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_12_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_12_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_12_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_12_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_12_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_12_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_12_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_12_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_12_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_12_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_12_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_12_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_12_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_12_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_12_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_12_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_12_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_12_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_12_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_12_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_12_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_12_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_12_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_12_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_12_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_12_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_12_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_12_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_12_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_12_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_12_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_12_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_12_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_12_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_12_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_12_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_12_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_12_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_12_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_12_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_12_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_12_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_12_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_12_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_12_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_12_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_12_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_12_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_12_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_12_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_12_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_12_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_12_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_12_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_12_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_12_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_12_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_12_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_12_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_13 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_13_clock),
    .reset(abc_mshrs_13_reset),
    .io_allocate_valid(abc_mshrs_13_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_13_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_13_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_13_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_13_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_13_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_13_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_13_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_13_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_13_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_13_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_13_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_13_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_13_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_13_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_13_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_13_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_13_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_13_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_13_io_directory_bits_way),
    .io_status_valid(abc_mshrs_13_io_status_valid),
    .io_status_bits_set(abc_mshrs_13_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_13_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_13_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_13_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_13_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_13_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_13_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_13_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_13_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_13_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_13_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_13_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_13_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_13_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_13_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_13_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_13_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_13_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_13_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_13_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_13_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_13_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_13_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_13_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_13_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_13_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_13_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_13_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_13_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_13_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_13_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_13_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_13_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_13_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_13_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_13_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_13_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_13_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_13_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_13_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_13_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_13_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_13_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_13_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_13_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_13_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_13_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_13_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_13_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_13_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_13_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_13_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_13_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_13_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_13_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_13_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_13_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_13_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_13_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_13_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_13_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_13_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_13_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_13_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_13_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_13_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_13_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_13_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_14 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_14_clock),
    .reset(abc_mshrs_14_reset),
    .io_allocate_valid(abc_mshrs_14_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_14_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_14_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_14_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_14_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_14_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_14_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_14_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_14_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_14_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_14_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_14_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_14_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_14_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_14_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_14_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_14_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_14_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_14_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_14_io_directory_bits_way),
    .io_status_valid(abc_mshrs_14_io_status_valid),
    .io_status_bits_set(abc_mshrs_14_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_14_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_14_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_14_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_14_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_14_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_14_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_14_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_14_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_14_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_14_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_14_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_14_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_14_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_14_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_14_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_14_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_14_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_14_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_14_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_14_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_14_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_14_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_14_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_14_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_14_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_14_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_14_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_14_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_14_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_14_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_14_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_14_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_14_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_14_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_14_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_14_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_14_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_14_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_14_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_14_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_14_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_14_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_14_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_14_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_14_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_14_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_14_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_14_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_14_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_14_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_14_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_14_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_14_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_14_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_14_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_14_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_14_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_14_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_14_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_14_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_14_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_14_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_14_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_14_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_14_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_14_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_14_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_15 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_15_clock),
    .reset(abc_mshrs_15_reset),
    .io_allocate_valid(abc_mshrs_15_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_15_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_15_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_15_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_15_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_15_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_15_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_15_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_15_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_15_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_15_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_15_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_15_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_15_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_15_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_15_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_15_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_15_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_15_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_15_io_directory_bits_way),
    .io_status_valid(abc_mshrs_15_io_status_valid),
    .io_status_bits_set(abc_mshrs_15_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_15_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_15_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_15_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_15_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_15_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_15_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_15_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_15_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_15_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_15_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_15_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_15_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_15_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_15_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_15_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_15_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_15_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_15_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_15_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_15_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_15_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_15_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_15_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_15_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_15_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_15_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_15_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_15_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_15_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_15_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_15_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_15_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_15_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_15_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_15_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_15_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_15_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_15_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_15_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_15_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_15_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_15_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_15_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_15_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_15_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_15_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_15_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_15_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_15_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_15_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_15_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_15_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_15_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_15_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_15_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_15_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_15_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_15_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_15_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_15_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_15_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_15_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_15_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_15_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_15_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_15_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_15_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_16 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_16_clock),
    .reset(abc_mshrs_16_reset),
    .io_allocate_valid(abc_mshrs_16_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_16_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_16_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_16_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_16_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_16_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_16_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_16_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_16_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_16_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_16_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_16_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_16_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_16_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_16_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_16_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_16_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_16_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_16_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_16_io_directory_bits_way),
    .io_status_valid(abc_mshrs_16_io_status_valid),
    .io_status_bits_set(abc_mshrs_16_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_16_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_16_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_16_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_16_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_16_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_16_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_16_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_16_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_16_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_16_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_16_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_16_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_16_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_16_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_16_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_16_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_16_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_16_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_16_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_16_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_16_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_16_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_16_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_16_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_16_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_16_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_16_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_16_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_16_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_16_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_16_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_16_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_16_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_16_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_16_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_16_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_16_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_16_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_16_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_16_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_16_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_16_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_16_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_16_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_16_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_16_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_16_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_16_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_16_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_16_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_16_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_16_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_16_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_16_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_16_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_16_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_16_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_16_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_16_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_16_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_16_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_16_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_16_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_16_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_16_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_16_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_16_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_17 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_17_clock),
    .reset(abc_mshrs_17_reset),
    .io_allocate_valid(abc_mshrs_17_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_17_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_17_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_17_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_17_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_17_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_17_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_17_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_17_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_17_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_17_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_17_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_17_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_17_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_17_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_17_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_17_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_17_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_17_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_17_io_directory_bits_way),
    .io_status_valid(abc_mshrs_17_io_status_valid),
    .io_status_bits_set(abc_mshrs_17_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_17_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_17_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_17_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_17_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_17_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_17_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_17_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_17_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_17_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_17_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_17_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_17_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_17_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_17_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_17_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_17_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_17_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_17_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_17_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_17_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_17_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_17_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_17_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_17_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_17_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_17_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_17_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_17_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_17_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_17_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_17_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_17_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_17_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_17_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_17_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_17_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_17_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_17_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_17_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_17_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_17_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_17_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_17_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_17_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_17_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_17_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_17_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_17_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_17_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_17_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_17_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_17_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_17_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_17_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_17_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_17_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_17_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_17_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_17_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_17_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_17_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_17_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_17_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_17_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_17_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_17_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_17_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_18 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_18_clock),
    .reset(abc_mshrs_18_reset),
    .io_allocate_valid(abc_mshrs_18_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_18_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_18_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_18_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_18_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_18_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_18_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_18_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_18_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_18_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_18_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_18_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_18_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_18_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_18_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_18_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_18_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_18_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_18_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_18_io_directory_bits_way),
    .io_status_valid(abc_mshrs_18_io_status_valid),
    .io_status_bits_set(abc_mshrs_18_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_18_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_18_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_18_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_18_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_18_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_18_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_18_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_18_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_18_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_18_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_18_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_18_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_18_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_18_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_18_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_18_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_18_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_18_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_18_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_18_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_18_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_18_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_18_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_18_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_18_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_18_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_18_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_18_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_18_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_18_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_18_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_18_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_18_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_18_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_18_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_18_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_18_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_18_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_18_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_18_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_18_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_18_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_18_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_18_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_18_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_18_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_18_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_18_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_18_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_18_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_18_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_18_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_18_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_18_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_18_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_18_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_18_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_18_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_18_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_18_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_18_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_18_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_18_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_18_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_18_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_18_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_18_io_nestedwb_c_set_dirty)
  );
  MSHR abc_mshrs_19 ( // @[Scheduler.scala 69:46]
    .clock(abc_mshrs_19_clock),
    .reset(abc_mshrs_19_reset),
    .io_allocate_valid(abc_mshrs_19_io_allocate_valid),
    .io_allocate_bits_prio_0(abc_mshrs_19_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(abc_mshrs_19_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(abc_mshrs_19_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(abc_mshrs_19_io_allocate_bits_opcode),
    .io_allocate_bits_param(abc_mshrs_19_io_allocate_bits_param),
    .io_allocate_bits_size(abc_mshrs_19_io_allocate_bits_size),
    .io_allocate_bits_source(abc_mshrs_19_io_allocate_bits_source),
    .io_allocate_bits_tag(abc_mshrs_19_io_allocate_bits_tag),
    .io_allocate_bits_offset(abc_mshrs_19_io_allocate_bits_offset),
    .io_allocate_bits_put(abc_mshrs_19_io_allocate_bits_put),
    .io_allocate_bits_set(abc_mshrs_19_io_allocate_bits_set),
    .io_allocate_bits_repeat(abc_mshrs_19_io_allocate_bits_repeat),
    .io_directory_valid(abc_mshrs_19_io_directory_valid),
    .io_directory_bits_dirty(abc_mshrs_19_io_directory_bits_dirty),
    .io_directory_bits_state(abc_mshrs_19_io_directory_bits_state),
    .io_directory_bits_clients(abc_mshrs_19_io_directory_bits_clients),
    .io_directory_bits_tag(abc_mshrs_19_io_directory_bits_tag),
    .io_directory_bits_hit(abc_mshrs_19_io_directory_bits_hit),
    .io_directory_bits_way(abc_mshrs_19_io_directory_bits_way),
    .io_status_valid(abc_mshrs_19_io_status_valid),
    .io_status_bits_set(abc_mshrs_19_io_status_bits_set),
    .io_status_bits_tag(abc_mshrs_19_io_status_bits_tag),
    .io_status_bits_way(abc_mshrs_19_io_status_bits_way),
    .io_status_bits_blockB(abc_mshrs_19_io_status_bits_blockB),
    .io_status_bits_nestB(abc_mshrs_19_io_status_bits_nestB),
    .io_status_bits_blockC(abc_mshrs_19_io_status_bits_blockC),
    .io_status_bits_nestC(abc_mshrs_19_io_status_bits_nestC),
    .io_schedule_ready(abc_mshrs_19_io_schedule_ready),
    .io_schedule_valid(abc_mshrs_19_io_schedule_valid),
    .io_schedule_bits_a_valid(abc_mshrs_19_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(abc_mshrs_19_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(abc_mshrs_19_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(abc_mshrs_19_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(abc_mshrs_19_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(abc_mshrs_19_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(abc_mshrs_19_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(abc_mshrs_19_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(abc_mshrs_19_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(abc_mshrs_19_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(abc_mshrs_19_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(abc_mshrs_19_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(abc_mshrs_19_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(abc_mshrs_19_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(abc_mshrs_19_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(abc_mshrs_19_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(abc_mshrs_19_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(abc_mshrs_19_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(abc_mshrs_19_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(abc_mshrs_19_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(abc_mshrs_19_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(abc_mshrs_19_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(abc_mshrs_19_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(abc_mshrs_19_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(abc_mshrs_19_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(abc_mshrs_19_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(abc_mshrs_19_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(abc_mshrs_19_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(abc_mshrs_19_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(abc_mshrs_19_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(abc_mshrs_19_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(abc_mshrs_19_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(abc_mshrs_19_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(abc_mshrs_19_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(abc_mshrs_19_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(abc_mshrs_19_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(abc_mshrs_19_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(abc_mshrs_19_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(abc_mshrs_19_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(abc_mshrs_19_io_schedule_bits_reload),
    .io_sinkc_valid(abc_mshrs_19_io_sinkc_valid),
    .io_sinkc_bits_last(abc_mshrs_19_io_sinkc_bits_last),
    .io_sinkc_bits_tag(abc_mshrs_19_io_sinkc_bits_tag),
    .io_sinkc_bits_source(abc_mshrs_19_io_sinkc_bits_source),
    .io_sinkc_bits_param(abc_mshrs_19_io_sinkc_bits_param),
    .io_sinkc_bits_data(abc_mshrs_19_io_sinkc_bits_data),
    .io_sinkd_valid(abc_mshrs_19_io_sinkd_valid),
    .io_sinkd_bits_last(abc_mshrs_19_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(abc_mshrs_19_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(abc_mshrs_19_io_sinkd_bits_param),
    .io_sinkd_bits_sink(abc_mshrs_19_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(abc_mshrs_19_io_sinkd_bits_denied),
    .io_sinke_valid(abc_mshrs_19_io_sinke_valid),
    .io_nestedwb_set(abc_mshrs_19_io_nestedwb_set),
    .io_nestedwb_tag(abc_mshrs_19_io_nestedwb_tag),
    .io_nestedwb_b_toN(abc_mshrs_19_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(abc_mshrs_19_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(abc_mshrs_19_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(abc_mshrs_19_io_nestedwb_c_set_dirty)
  );
  MSHR bc_mshr ( // @[Scheduler.scala 69:46]
    .clock(bc_mshr_clock),
    .reset(bc_mshr_reset),
    .io_allocate_valid(bc_mshr_io_allocate_valid),
    .io_allocate_bits_prio_0(bc_mshr_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(bc_mshr_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(bc_mshr_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(bc_mshr_io_allocate_bits_opcode),
    .io_allocate_bits_param(bc_mshr_io_allocate_bits_param),
    .io_allocate_bits_size(bc_mshr_io_allocate_bits_size),
    .io_allocate_bits_source(bc_mshr_io_allocate_bits_source),
    .io_allocate_bits_tag(bc_mshr_io_allocate_bits_tag),
    .io_allocate_bits_offset(bc_mshr_io_allocate_bits_offset),
    .io_allocate_bits_put(bc_mshr_io_allocate_bits_put),
    .io_allocate_bits_set(bc_mshr_io_allocate_bits_set),
    .io_allocate_bits_repeat(bc_mshr_io_allocate_bits_repeat),
    .io_directory_valid(bc_mshr_io_directory_valid),
    .io_directory_bits_dirty(bc_mshr_io_directory_bits_dirty),
    .io_directory_bits_state(bc_mshr_io_directory_bits_state),
    .io_directory_bits_clients(bc_mshr_io_directory_bits_clients),
    .io_directory_bits_tag(bc_mshr_io_directory_bits_tag),
    .io_directory_bits_hit(bc_mshr_io_directory_bits_hit),
    .io_directory_bits_way(bc_mshr_io_directory_bits_way),
    .io_status_valid(bc_mshr_io_status_valid),
    .io_status_bits_set(bc_mshr_io_status_bits_set),
    .io_status_bits_tag(bc_mshr_io_status_bits_tag),
    .io_status_bits_way(bc_mshr_io_status_bits_way),
    .io_status_bits_blockB(bc_mshr_io_status_bits_blockB),
    .io_status_bits_nestB(bc_mshr_io_status_bits_nestB),
    .io_status_bits_blockC(bc_mshr_io_status_bits_blockC),
    .io_status_bits_nestC(bc_mshr_io_status_bits_nestC),
    .io_schedule_ready(bc_mshr_io_schedule_ready),
    .io_schedule_valid(bc_mshr_io_schedule_valid),
    .io_schedule_bits_a_valid(bc_mshr_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(bc_mshr_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(bc_mshr_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(bc_mshr_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(bc_mshr_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(bc_mshr_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(bc_mshr_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(bc_mshr_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(bc_mshr_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(bc_mshr_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(bc_mshr_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(bc_mshr_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(bc_mshr_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(bc_mshr_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(bc_mshr_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(bc_mshr_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(bc_mshr_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(bc_mshr_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(bc_mshr_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(bc_mshr_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(bc_mshr_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(bc_mshr_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(bc_mshr_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(bc_mshr_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(bc_mshr_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(bc_mshr_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(bc_mshr_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(bc_mshr_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(bc_mshr_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(bc_mshr_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(bc_mshr_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(bc_mshr_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(bc_mshr_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(bc_mshr_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(bc_mshr_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(bc_mshr_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(bc_mshr_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(bc_mshr_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(bc_mshr_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(bc_mshr_io_schedule_bits_reload),
    .io_sinkc_valid(bc_mshr_io_sinkc_valid),
    .io_sinkc_bits_last(bc_mshr_io_sinkc_bits_last),
    .io_sinkc_bits_tag(bc_mshr_io_sinkc_bits_tag),
    .io_sinkc_bits_source(bc_mshr_io_sinkc_bits_source),
    .io_sinkc_bits_param(bc_mshr_io_sinkc_bits_param),
    .io_sinkc_bits_data(bc_mshr_io_sinkc_bits_data),
    .io_sinkd_valid(bc_mshr_io_sinkd_valid),
    .io_sinkd_bits_last(bc_mshr_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(bc_mshr_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(bc_mshr_io_sinkd_bits_param),
    .io_sinkd_bits_sink(bc_mshr_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(bc_mshr_io_sinkd_bits_denied),
    .io_sinke_valid(bc_mshr_io_sinke_valid),
    .io_nestedwb_set(bc_mshr_io_nestedwb_set),
    .io_nestedwb_tag(bc_mshr_io_nestedwb_tag),
    .io_nestedwb_b_toN(bc_mshr_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(bc_mshr_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(bc_mshr_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(bc_mshr_io_nestedwb_c_set_dirty)
  );
  MSHR c_mshr ( // @[Scheduler.scala 69:46]
    .clock(c_mshr_clock),
    .reset(c_mshr_reset),
    .io_allocate_valid(c_mshr_io_allocate_valid),
    .io_allocate_bits_prio_0(c_mshr_io_allocate_bits_prio_0),
    .io_allocate_bits_prio_1(c_mshr_io_allocate_bits_prio_1),
    .io_allocate_bits_prio_2(c_mshr_io_allocate_bits_prio_2),
    .io_allocate_bits_opcode(c_mshr_io_allocate_bits_opcode),
    .io_allocate_bits_param(c_mshr_io_allocate_bits_param),
    .io_allocate_bits_size(c_mshr_io_allocate_bits_size),
    .io_allocate_bits_source(c_mshr_io_allocate_bits_source),
    .io_allocate_bits_tag(c_mshr_io_allocate_bits_tag),
    .io_allocate_bits_offset(c_mshr_io_allocate_bits_offset),
    .io_allocate_bits_put(c_mshr_io_allocate_bits_put),
    .io_allocate_bits_set(c_mshr_io_allocate_bits_set),
    .io_allocate_bits_repeat(c_mshr_io_allocate_bits_repeat),
    .io_directory_valid(c_mshr_io_directory_valid),
    .io_directory_bits_dirty(c_mshr_io_directory_bits_dirty),
    .io_directory_bits_state(c_mshr_io_directory_bits_state),
    .io_directory_bits_clients(c_mshr_io_directory_bits_clients),
    .io_directory_bits_tag(c_mshr_io_directory_bits_tag),
    .io_directory_bits_hit(c_mshr_io_directory_bits_hit),
    .io_directory_bits_way(c_mshr_io_directory_bits_way),
    .io_status_valid(c_mshr_io_status_valid),
    .io_status_bits_set(c_mshr_io_status_bits_set),
    .io_status_bits_tag(c_mshr_io_status_bits_tag),
    .io_status_bits_way(c_mshr_io_status_bits_way),
    .io_status_bits_blockB(c_mshr_io_status_bits_blockB),
    .io_status_bits_nestB(c_mshr_io_status_bits_nestB),
    .io_status_bits_blockC(c_mshr_io_status_bits_blockC),
    .io_status_bits_nestC(c_mshr_io_status_bits_nestC),
    .io_schedule_ready(c_mshr_io_schedule_ready),
    .io_schedule_valid(c_mshr_io_schedule_valid),
    .io_schedule_bits_a_valid(c_mshr_io_schedule_bits_a_valid),
    .io_schedule_bits_a_bits_tag(c_mshr_io_schedule_bits_a_bits_tag),
    .io_schedule_bits_a_bits_set(c_mshr_io_schedule_bits_a_bits_set),
    .io_schedule_bits_a_bits_param(c_mshr_io_schedule_bits_a_bits_param),
    .io_schedule_bits_a_bits_block(c_mshr_io_schedule_bits_a_bits_block),
    .io_schedule_bits_b_valid(c_mshr_io_schedule_bits_b_valid),
    .io_schedule_bits_b_bits_param(c_mshr_io_schedule_bits_b_bits_param),
    .io_schedule_bits_b_bits_tag(c_mshr_io_schedule_bits_b_bits_tag),
    .io_schedule_bits_b_bits_set(c_mshr_io_schedule_bits_b_bits_set),
    .io_schedule_bits_b_bits_clients(c_mshr_io_schedule_bits_b_bits_clients),
    .io_schedule_bits_c_valid(c_mshr_io_schedule_bits_c_valid),
    .io_schedule_bits_c_bits_opcode(c_mshr_io_schedule_bits_c_bits_opcode),
    .io_schedule_bits_c_bits_param(c_mshr_io_schedule_bits_c_bits_param),
    .io_schedule_bits_c_bits_tag(c_mshr_io_schedule_bits_c_bits_tag),
    .io_schedule_bits_c_bits_set(c_mshr_io_schedule_bits_c_bits_set),
    .io_schedule_bits_c_bits_way(c_mshr_io_schedule_bits_c_bits_way),
    .io_schedule_bits_c_bits_dirty(c_mshr_io_schedule_bits_c_bits_dirty),
    .io_schedule_bits_d_valid(c_mshr_io_schedule_bits_d_valid),
    .io_schedule_bits_d_bits_prio_0(c_mshr_io_schedule_bits_d_bits_prio_0),
    .io_schedule_bits_d_bits_prio_2(c_mshr_io_schedule_bits_d_bits_prio_2),
    .io_schedule_bits_d_bits_opcode(c_mshr_io_schedule_bits_d_bits_opcode),
    .io_schedule_bits_d_bits_param(c_mshr_io_schedule_bits_d_bits_param),
    .io_schedule_bits_d_bits_size(c_mshr_io_schedule_bits_d_bits_size),
    .io_schedule_bits_d_bits_source(c_mshr_io_schedule_bits_d_bits_source),
    .io_schedule_bits_d_bits_offset(c_mshr_io_schedule_bits_d_bits_offset),
    .io_schedule_bits_d_bits_put(c_mshr_io_schedule_bits_d_bits_put),
    .io_schedule_bits_d_bits_set(c_mshr_io_schedule_bits_d_bits_set),
    .io_schedule_bits_d_bits_way(c_mshr_io_schedule_bits_d_bits_way),
    .io_schedule_bits_d_bits_bad(c_mshr_io_schedule_bits_d_bits_bad),
    .io_schedule_bits_e_valid(c_mshr_io_schedule_bits_e_valid),
    .io_schedule_bits_e_bits_sink(c_mshr_io_schedule_bits_e_bits_sink),
    .io_schedule_bits_x_valid(c_mshr_io_schedule_bits_x_valid),
    .io_schedule_bits_dir_valid(c_mshr_io_schedule_bits_dir_valid),
    .io_schedule_bits_dir_bits_set(c_mshr_io_schedule_bits_dir_bits_set),
    .io_schedule_bits_dir_bits_way(c_mshr_io_schedule_bits_dir_bits_way),
    .io_schedule_bits_dir_bits_data_dirty(c_mshr_io_schedule_bits_dir_bits_data_dirty),
    .io_schedule_bits_dir_bits_data_state(c_mshr_io_schedule_bits_dir_bits_data_state),
    .io_schedule_bits_dir_bits_data_clients(c_mshr_io_schedule_bits_dir_bits_data_clients),
    .io_schedule_bits_dir_bits_data_tag(c_mshr_io_schedule_bits_dir_bits_data_tag),
    .io_schedule_bits_reload(c_mshr_io_schedule_bits_reload),
    .io_sinkc_valid(c_mshr_io_sinkc_valid),
    .io_sinkc_bits_last(c_mshr_io_sinkc_bits_last),
    .io_sinkc_bits_tag(c_mshr_io_sinkc_bits_tag),
    .io_sinkc_bits_source(c_mshr_io_sinkc_bits_source),
    .io_sinkc_bits_param(c_mshr_io_sinkc_bits_param),
    .io_sinkc_bits_data(c_mshr_io_sinkc_bits_data),
    .io_sinkd_valid(c_mshr_io_sinkd_valid),
    .io_sinkd_bits_last(c_mshr_io_sinkd_bits_last),
    .io_sinkd_bits_opcode(c_mshr_io_sinkd_bits_opcode),
    .io_sinkd_bits_param(c_mshr_io_sinkd_bits_param),
    .io_sinkd_bits_sink(c_mshr_io_sinkd_bits_sink),
    .io_sinkd_bits_denied(c_mshr_io_sinkd_bits_denied),
    .io_sinke_valid(c_mshr_io_sinke_valid),
    .io_nestedwb_set(c_mshr_io_nestedwb_set),
    .io_nestedwb_tag(c_mshr_io_nestedwb_tag),
    .io_nestedwb_b_toN(c_mshr_io_nestedwb_b_toN),
    .io_nestedwb_b_toB(c_mshr_io_nestedwb_b_toB),
    .io_nestedwb_b_clr_dirty(c_mshr_io_nestedwb_b_clr_dirty),
    .io_nestedwb_c_set_dirty(c_mshr_io_nestedwb_c_set_dirty)
  );
  assign io_in_a_ready = sinkA_io_a_ready; // @[Scheduler.scala 58:14]
  assign io_in_b_valid = sourceB_io_b_valid; // @[Scheduler.scala 48:11]
  assign io_in_b_bits_param = sourceB_io_b_bits_param; // @[Scheduler.scala 48:11]
  assign io_in_b_bits_address = sourceB_io_b_bits_address; // @[Scheduler.scala 48:11]
  assign io_in_c_ready = sinkC_io_c_ready; // @[Scheduler.scala 59:14]
  assign io_in_d_valid = sourceD_io_d_valid; // @[Scheduler.scala 49:11]
  assign io_in_d_bits_opcode = sourceD_io_d_bits_opcode; // @[Scheduler.scala 49:11]
  assign io_in_d_bits_param = sourceD_io_d_bits_param; // @[Scheduler.scala 49:11]
  assign io_in_d_bits_size = sourceD_io_d_bits_size; // @[Scheduler.scala 49:11]
  assign io_in_d_bits_source = sourceD_io_d_bits_source; // @[Scheduler.scala 49:11]
  assign io_in_d_bits_sink = sourceD_io_d_bits_sink; // @[Scheduler.scala 49:11]
  assign io_in_d_bits_denied = sourceD_io_d_bits_denied; // @[Scheduler.scala 49:11]
  assign io_in_d_bits_data = sourceD_io_d_bits_data; // @[Scheduler.scala 49:11]
  assign io_in_d_bits_corrupt = sourceD_io_d_bits_corrupt; // @[Scheduler.scala 49:11]
  assign io_out_a_valid = sourceA_io_a_valid; // @[Scheduler.scala 45:12]
  assign io_out_a_bits_opcode = sourceA_io_a_bits_opcode; // @[Scheduler.scala 45:12]
  assign io_out_a_bits_param = sourceA_io_a_bits_param; // @[Scheduler.scala 45:12]
  assign io_out_a_bits_size = sourceA_io_a_bits_size; // @[Scheduler.scala 45:12]
  assign io_out_a_bits_source = sourceA_io_a_bits_source; // @[Scheduler.scala 45:12]
  assign io_out_a_bits_address = sourceA_io_a_bits_address; // @[Scheduler.scala 45:12]
  assign io_out_a_bits_mask = sourceA_io_a_bits_mask; // @[Scheduler.scala 45:12]
  assign io_out_a_bits_data = sourceA_io_a_bits_data; // @[Scheduler.scala 45:12]
  assign io_out_a_bits_corrupt = sourceA_io_a_bits_corrupt; // @[Scheduler.scala 45:12]
  assign io_out_c_valid = sourceC_io_c_valid; // @[Scheduler.scala 46:12]
  assign io_out_c_bits_opcode = sourceC_io_c_bits_opcode; // @[Scheduler.scala 46:12]
  assign io_out_c_bits_param = sourceC_io_c_bits_param; // @[Scheduler.scala 46:12]
  assign io_out_c_bits_size = sourceC_io_c_bits_size; // @[Scheduler.scala 46:12]
  assign io_out_c_bits_source = sourceC_io_c_bits_source; // @[Scheduler.scala 46:12]
  assign io_out_c_bits_address = sourceC_io_c_bits_address; // @[Scheduler.scala 46:12]
  assign io_out_c_bits_data = sourceC_io_c_bits_data; // @[Scheduler.scala 46:12]
  assign io_out_c_bits_corrupt = sourceC_io_c_bits_corrupt; // @[Scheduler.scala 46:12]
  assign io_out_d_ready = sinkD_io_d_ready; // @[Scheduler.scala 61:14]
  assign io_out_e_valid = sourceE_io_e_valid; // @[Scheduler.scala 47:12]
  assign io_out_e_bits_sink = sourceE_io_e_bits_sink; // @[Scheduler.scala 47:12]
  assign sourceA_clock = clock;
  assign sourceA_reset = reset;
  assign sourceA_io_req_valid = _schedule_T_2036 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_a_valid |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_a_valid | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_a_valid | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_a_valid | mshr_selectOH[20
    ] & bc_mshr_io_schedule_bits_a_valid | mshr_selectOH[21] & c_mshr_io_schedule_bits_a_valid; // @[Mux.scala 27:73]
  assign sourceA_io_req_bits_tag = _schedule_T_1998 | _schedule_T_1978; // @[Mux.scala 27:73]
  assign sourceA_io_req_bits_set = _schedule_T_1955 | _schedule_T_1935; // @[Mux.scala 27:73]
  assign sourceA_io_req_bits_param = _schedule_T_1912 | _schedule_T_1892; // @[Mux.scala 27:73]
  assign sourceA_io_req_bits_source = {_mshr_select_T,_mshr_select_T_11}; // @[Cat.scala 33:92]
  assign sourceA_io_req_bits_block = _schedule_T_1821 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_a_bits_block
     | mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_a_bits_block | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_a_bits_block | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_a_bits_block |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_a_bits_block | mshr_selectOH[21] & c_mshr_io_schedule_bits_a_bits_block
    ; // @[Mux.scala 27:73]
  assign sourceA_io_a_ready = io_out_a_ready; // @[Scheduler.scala 45:12]
  assign sourceB_clock = clock;
  assign sourceB_reset = reset;
  assign sourceB_io_req_valid = _schedule_T_1778 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_b_valid |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_b_valid | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_b_valid | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_b_valid | mshr_selectOH[20
    ] & bc_mshr_io_schedule_bits_b_valid | mshr_selectOH[21] & c_mshr_io_schedule_bits_b_valid; // @[Mux.scala 27:73]
  assign sourceB_io_req_bits_param = _schedule_T_1740 | _schedule_T_1720; // @[Mux.scala 27:73]
  assign sourceB_io_req_bits_tag = _schedule_T_1697 | _schedule_T_1677; // @[Mux.scala 27:73]
  assign sourceB_io_req_bits_set = _schedule_T_1654 | _schedule_T_1634; // @[Mux.scala 27:73]
  assign sourceB_io_req_bits_clients = _schedule_T_1606 | mshr_selectOH[16] &
    abc_mshrs_16_io_schedule_bits_b_bits_clients | mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_b_bits_clients |
    mshr_selectOH[18] & abc_mshrs_18_io_schedule_bits_b_bits_clients | mshr_selectOH[19] &
    abc_mshrs_19_io_schedule_bits_b_bits_clients | mshr_selectOH[20] & bc_mshr_io_schedule_bits_b_bits_clients |
    mshr_selectOH[21] & c_mshr_io_schedule_bits_b_bits_clients; // @[Mux.scala 27:73]
  assign sourceB_io_b_ready = io_in_b_ready; // @[Scheduler.scala 48:11]
  assign sourceC_clock = clock;
  assign sourceC_reset = reset;
  assign sourceC_io_req_valid = _schedule_T_1563 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_c_valid |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_c_valid | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_c_valid | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_c_valid | mshr_selectOH[20
    ] & bc_mshr_io_schedule_bits_c_valid | mshr_selectOH[21] & c_mshr_io_schedule_bits_c_valid; // @[Mux.scala 27:73]
  assign sourceC_io_req_bits_opcode = _schedule_T_1525 | _schedule_T_1505; // @[Mux.scala 27:73]
  assign sourceC_io_req_bits_param = _schedule_T_1482 | _schedule_T_1462; // @[Mux.scala 27:73]
  assign sourceC_io_req_bits_source = schedule_c_bits_opcode[1] ? mshr_select : 5'h0; // @[Scheduler.scala 130:32]
  assign sourceC_io_req_bits_tag = _schedule_T_1396 | _schedule_T_1376; // @[Mux.scala 27:73]
  assign sourceC_io_req_bits_set = _schedule_T_1353 | _schedule_T_1333; // @[Mux.scala 27:73]
  assign sourceC_io_req_bits_way = _schedule_T_1305 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_c_bits_way |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_c_bits_way | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_c_bits_way | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_c_bits_way |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_c_bits_way | mshr_selectOH[21] & c_mshr_io_schedule_bits_c_bits_way; // @[Mux.scala 27:73]
  assign sourceC_io_req_bits_dirty = _schedule_T_1262 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_c_bits_dirty
     | mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_c_bits_dirty | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_c_bits_dirty | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_c_bits_dirty |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_c_bits_dirty | mshr_selectOH[21] & c_mshr_io_schedule_bits_c_bits_dirty
    ; // @[Mux.scala 27:73]
  assign sourceC_io_c_ready = io_out_c_ready; // @[Scheduler.scala 46:12]
  assign sourceC_io_bs_adr_ready = bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala 322:30]
  assign sourceC_io_bs_dat_data = bankedStore_io_sourceC_dat_data; // @[Scheduler.scala 326:21]
  assign sourceC_io_evict_safe = sourceD_io_evict_safe; // @[Scheduler.scala 332:25]
  assign sourceD_clock = clock;
  assign sourceD_reset = reset;
  assign sourceD_io_req_valid = _schedule_T_1219 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_d_valid |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_d_valid | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_d_valid | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_d_valid | mshr_selectOH[20
    ] & bc_mshr_io_schedule_bits_d_valid | mshr_selectOH[21] & c_mshr_io_schedule_bits_d_valid; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_prio_0 = _schedule_T_1090 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_d_bits_prio_0
     | mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_d_bits_prio_0 |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_d_bits_prio_0 | mshr_selectOH[21] &
    c_mshr_io_schedule_bits_d_bits_prio_0; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_prio_2 = _schedule_T_1176 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_d_bits_prio_2
     | mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_d_bits_prio_2 |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_d_bits_prio_2 | mshr_selectOH[21] &
    c_mshr_io_schedule_bits_d_bits_prio_2; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_opcode = _schedule_T_1009 | _schedule_T_989; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_param = _schedule_T_966 | _schedule_T_946; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_size = _schedule_T_923 | _schedule_T_903; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_source = _schedule_T_880 | _schedule_T_860; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_offset = _schedule_T_794 | _schedule_T_774; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_put = _schedule_T_751 | _schedule_T_731; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_set = _schedule_T_708 | _schedule_T_688; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_sink = {_mshr_select_T,_mshr_select_T_11}; // @[Cat.scala 33:92]
  assign sourceD_io_req_bits_way = _schedule_T_617 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_d_bits_way |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_d_bits_way | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_d_bits_way | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_d_bits_way |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_d_bits_way | mshr_selectOH[21] & c_mshr_io_schedule_bits_d_bits_way; // @[Mux.scala 27:73]
  assign sourceD_io_req_bits_bad = _schedule_T_574 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_d_bits_bad |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_d_bits_bad | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_d_bits_bad | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_d_bits_bad |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_d_bits_bad | mshr_selectOH[21] & c_mshr_io_schedule_bits_d_bits_bad; // @[Mux.scala 27:73]
  assign sourceD_io_d_ready = io_in_d_ready; // @[Scheduler.scala 49:11]
  assign sourceD_io_pb_pop_ready = sinkA_io_pb_pop_ready; // @[Scheduler.scala 312:19]
  assign sourceD_io_pb_beat_data = sinkA_io_pb_beat_data; // @[Scheduler.scala 313:22]
  assign sourceD_io_pb_beat_mask = sinkA_io_pb_beat_mask; // @[Scheduler.scala 313:22]
  assign sourceD_io_pb_beat_corrupt = sinkA_io_pb_beat_corrupt; // @[Scheduler.scala 313:22]
  assign sourceD_io_rel_pop_ready = sinkC_io_rel_pop_ready; // @[Scheduler.scala 314:20]
  assign sourceD_io_rel_beat_data = sinkC_io_rel_beat_data; // @[Scheduler.scala 315:23]
  assign sourceD_io_rel_beat_corrupt = sinkC_io_rel_beat_corrupt; // @[Scheduler.scala 315:23]
  assign sourceD_io_bs_radr_ready = bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala 323:31]
  assign sourceD_io_bs_rdat_data = bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala 327:22]
  assign sourceD_io_bs_wadr_ready = bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala 324:31]
  assign sourceD_io_evict_req_set = sourceC_io_evict_req_set; // @[Scheduler.scala 330:24]
  assign sourceD_io_evict_req_way = sourceC_io_evict_req_way; // @[Scheduler.scala 330:24]
  assign sourceD_io_grant_req_set = sinkD_io_grant_req_set; // @[Scheduler.scala 331:24]
  assign sourceD_io_grant_req_way = sinkD_io_grant_req_way; // @[Scheduler.scala 331:24]
  assign sourceE_clock = clock;
  assign sourceE_reset = reset;
  assign sourceE_io_req_valid = _schedule_T_531 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_e_valid |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_e_valid | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_e_valid | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_e_valid | mshr_selectOH[20
    ] & bc_mshr_io_schedule_bits_e_valid | mshr_selectOH[21] & c_mshr_io_schedule_bits_e_valid; // @[Mux.scala 27:73]
  assign sourceE_io_req_bits_sink = _schedule_T_493 | _schedule_T_473; // @[Mux.scala 27:73]
  assign sinkA_clock = clock;
  assign sinkA_reset = reset;
  assign sinkA_io_req_ready = _sinkC_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala 158:61]
  assign sinkA_io_a_valid = io_in_a_valid; // @[Scheduler.scala 58:14]
  assign sinkA_io_a_bits_opcode = io_in_a_bits_opcode; // @[Scheduler.scala 58:14]
  assign sinkA_io_a_bits_param = io_in_a_bits_param; // @[Scheduler.scala 58:14]
  assign sinkA_io_a_bits_size = io_in_a_bits_size; // @[Scheduler.scala 58:14]
  assign sinkA_io_a_bits_source = io_in_a_bits_source; // @[Scheduler.scala 58:14]
  assign sinkA_io_a_bits_address = io_in_a_bits_address; // @[Scheduler.scala 58:14]
  assign sinkA_io_a_bits_mask = io_in_a_bits_mask; // @[Scheduler.scala 58:14]
  assign sinkA_io_a_bits_data = io_in_a_bits_data; // @[Scheduler.scala 58:14]
  assign sinkA_io_a_bits_corrupt = io_in_a_bits_corrupt; // @[Scheduler.scala 58:14]
  assign sinkA_io_pb_pop_valid = sourceD_io_pb_pop_valid; // @[Scheduler.scala 312:19]
  assign sinkA_io_pb_pop_bits_index = sourceD_io_pb_pop_bits_index; // @[Scheduler.scala 312:19]
  assign sinkA_io_pb_pop_bits_last = sourceD_io_pb_pop_bits_last; // @[Scheduler.scala 312:19]
  assign sinkC_clock = clock;
  assign sinkC_reset = reset;
  assign sinkC_io_req_ready = directory_io_ready & request_ready; // @[Scheduler.scala 156:44]
  assign sinkC_io_c_valid = io_in_c_valid; // @[Scheduler.scala 59:14]
  assign sinkC_io_c_bits_opcode = io_in_c_bits_opcode; // @[Scheduler.scala 59:14]
  assign sinkC_io_c_bits_param = io_in_c_bits_param; // @[Scheduler.scala 59:14]
  assign sinkC_io_c_bits_size = io_in_c_bits_size; // @[Scheduler.scala 59:14]
  assign sinkC_io_c_bits_address = io_in_c_bits_address; // @[Scheduler.scala 59:14]
  assign sinkC_io_c_bits_data = io_in_c_bits_data; // @[Scheduler.scala 59:14]
  assign sinkC_io_c_bits_corrupt = io_in_c_bits_corrupt; // @[Scheduler.scala 59:14]
  assign sinkC_io_way = bc_mshr_io_status_valid & bc_mshr_io_status_bits_set == sinkC_io_set ?
    bc_mshr_io_status_bits_way : _sinkC_io_way_T_80; // @[Scheduler.scala 304:8]
  assign sinkC_io_bs_adr_ready = bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala 318:28]
  assign sinkC_io_rel_pop_valid = sourceD_io_rel_pop_valid; // @[Scheduler.scala 314:20]
  assign sinkC_io_rel_pop_bits_index = sourceD_io_rel_pop_bits_index; // @[Scheduler.scala 314:20]
  assign sinkC_io_rel_pop_bits_last = sourceD_io_rel_pop_bits_last; // @[Scheduler.scala 314:20]
  assign sinkD_clock = clock;
  assign sinkD_reset = reset;
  assign sinkD_io_d_valid = io_out_d_valid; // @[Scheduler.scala 61:14]
  assign sinkD_io_d_bits_opcode = io_out_d_bits_opcode; // @[Scheduler.scala 61:14]
  assign sinkD_io_d_bits_param = io_out_d_bits_param; // @[Scheduler.scala 61:14]
  assign sinkD_io_d_bits_size = io_out_d_bits_size; // @[Scheduler.scala 61:14]
  assign sinkD_io_d_bits_source = io_out_d_bits_source; // @[Scheduler.scala 61:14]
  assign sinkD_io_d_bits_sink = io_out_d_bits_sink; // @[Scheduler.scala 61:14]
  assign sinkD_io_d_bits_denied = io_out_d_bits_denied; // @[Scheduler.scala 61:14]
  assign sinkD_io_d_bits_data = io_out_d_bits_data; // @[Scheduler.scala 61:14]
  assign sinkD_io_d_bits_corrupt = io_out_d_bits_corrupt; // @[Scheduler.scala 61:14]
  assign sinkD_io_way = 5'h15 == sinkD_io_source ? c_mshr_io_status_bits_way : _GEN_357; // @[Scheduler.scala 308:{16,16}]
  assign sinkD_io_set = 5'h15 == sinkD_io_source ? _sinkD_io_set_WIRE_21 : _GEN_379; // @[Scheduler.scala 309:{16,16}]
  assign sinkD_io_bs_adr_ready = bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala 320:28]
  assign sinkD_io_grant_safe = sourceD_io_grant_safe; // @[Scheduler.scala 333:25]
  assign sinkE_io_e_valid = io_in_e_valid; // @[Scheduler.scala 60:14]
  assign sinkE_io_e_bits_sink = io_in_e_bits_sink; // @[Scheduler.scala 60:14]
  assign directory_clock = clock;
  assign directory_reset = reset;
  assign directory_io_write_valid = _schedule_T_359 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_dir_valid |
    mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_dir_valid | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_dir_valid | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_dir_valid |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid | mshr_selectOH[21] & c_mshr_io_schedule_bits_dir_valid; // @[Mux.scala 27:73]
  assign directory_io_write_bits_set = _schedule_T_321 | _schedule_T_301; // @[Mux.scala 27:73]
  assign directory_io_write_bits_way = _schedule_T_273 | mshr_selectOH[16] & abc_mshrs_16_io_schedule_bits_dir_bits_way
     | mshr_selectOH[17] & abc_mshrs_17_io_schedule_bits_dir_bits_way | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_dir_bits_way | mshr_selectOH[19] & abc_mshrs_19_io_schedule_bits_dir_bits_way |
    mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_bits_way | mshr_selectOH[21] & c_mshr_io_schedule_bits_dir_bits_way
    ; // @[Mux.scala 27:73]
  assign directory_io_write_bits_data_dirty = _schedule_T_230 | mshr_selectOH[16] &
    abc_mshrs_16_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[17] &
    abc_mshrs_17_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[19] &
    abc_mshrs_19_io_schedule_bits_dir_bits_data_dirty | mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_bits_data_dirty
     | mshr_selectOH[21] & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala 27:73]
  assign directory_io_write_bits_data_state = _schedule_T_192 | _schedule_T_172; // @[Mux.scala 27:73]
  assign directory_io_write_bits_data_clients = _schedule_T_144 | mshr_selectOH[16] &
    abc_mshrs_16_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[17] &
    abc_mshrs_17_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[18] &
    abc_mshrs_18_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[19] &
    abc_mshrs_19_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[20] &
    bc_mshr_io_schedule_bits_dir_bits_data_clients | mshr_selectOH[21] & c_mshr_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala 27:73]
  assign directory_io_write_bits_data_tag = _schedule_T_106 | _schedule_T_86; // @[Mux.scala 27:73]
  assign directory_io_read_valid = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala 254:50]
  assign directory_io_read_bits_set = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Scheduler.scala 255:36]
  assign directory_io_read_bits_tag = mshr_uses_directory_for_lb ? requests_io_data_tag : request_bits_tag; // @[Scheduler.scala 256:36]
  assign bankedStore_clock = clock;
  assign bankedStore_io_sinkC_adr_valid = sinkC_io_bs_adr_valid; // @[Scheduler.scala 318:28]
  assign bankedStore_io_sinkC_adr_bits_noop = sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala 318:28]
  assign bankedStore_io_sinkC_adr_bits_way = sinkC_io_bs_adr_bits_way; // @[Scheduler.scala 318:28]
  assign bankedStore_io_sinkC_adr_bits_set = sinkC_io_bs_adr_bits_set; // @[Scheduler.scala 318:28]
  assign bankedStore_io_sinkC_adr_bits_beat = sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala 318:28]
  assign bankedStore_io_sinkC_adr_bits_mask = sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala 318:28]
  assign bankedStore_io_sinkC_dat_data = sinkC_io_bs_dat_data; // @[Scheduler.scala 319:28]
  assign bankedStore_io_sinkD_adr_valid = sinkD_io_bs_adr_valid; // @[Scheduler.scala 320:28]
  assign bankedStore_io_sinkD_adr_bits_noop = sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala 320:28]
  assign bankedStore_io_sinkD_adr_bits_way = sinkD_io_bs_adr_bits_way; // @[Scheduler.scala 320:28]
  assign bankedStore_io_sinkD_adr_bits_set = sinkD_io_bs_adr_bits_set; // @[Scheduler.scala 320:28]
  assign bankedStore_io_sinkD_adr_bits_beat = sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala 320:28]
  assign bankedStore_io_sinkD_dat_data = sinkD_io_bs_dat_data; // @[Scheduler.scala 321:28]
  assign bankedStore_io_sourceC_adr_valid = sourceC_io_bs_adr_valid; // @[Scheduler.scala 322:30]
  assign bankedStore_io_sourceC_adr_bits_way = sourceC_io_bs_adr_bits_way; // @[Scheduler.scala 322:30]
  assign bankedStore_io_sourceC_adr_bits_set = sourceC_io_bs_adr_bits_set; // @[Scheduler.scala 322:30]
  assign bankedStore_io_sourceC_adr_bits_beat = sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala 322:30]
  assign bankedStore_io_sourceD_radr_valid = sourceD_io_bs_radr_valid; // @[Scheduler.scala 323:31]
  assign bankedStore_io_sourceD_radr_bits_way = sourceD_io_bs_radr_bits_way; // @[Scheduler.scala 323:31]
  assign bankedStore_io_sourceD_radr_bits_set = sourceD_io_bs_radr_bits_set; // @[Scheduler.scala 323:31]
  assign bankedStore_io_sourceD_radr_bits_beat = sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala 323:31]
  assign bankedStore_io_sourceD_radr_bits_mask = sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala 323:31]
  assign bankedStore_io_sourceD_wadr_valid = sourceD_io_bs_wadr_valid; // @[Scheduler.scala 324:31]
  assign bankedStore_io_sourceD_wadr_bits_way = sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala 324:31]
  assign bankedStore_io_sourceD_wadr_bits_set = sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala 324:31]
  assign bankedStore_io_sourceD_wadr_bits_beat = sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala 324:31]
  assign bankedStore_io_sourceD_wadr_bits_mask = sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala 324:31]
  assign bankedStore_io_sourceD_wdat_data = sourceD_io_bs_wdat_data; // @[Scheduler.scala 325:31]
  assign requests_clock = clock;
  assign requests_reset = reset;
  assign requests_io_push_valid = _bypass_T & ~bypassQueue; // @[Scheduler.scala 259:52]
  assign requests_io_push_bits_index = _GEN_388 | _requests_io_push_bits_index_T_53; // @[Mux.scala 27:73]
  assign requests_io_push_bits_data_prio_0 = sinkC_io_req_valid ? 1'h0 : 1'h1; // @[Scheduler.scala 154:22]
  assign requests_io_push_bits_data_prio_2 = sinkC_io_req_valid; // @[Scheduler.scala 154:22]
  assign requests_io_push_bits_data_opcode = sinkC_io_req_valid ? sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala 154:22]
  assign requests_io_push_bits_data_param = sinkC_io_req_valid ? sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala 154:22]
  assign requests_io_push_bits_data_size = sinkC_io_req_valid ? sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala 154:22]
  assign requests_io_push_bits_data_source = sinkC_io_req_valid ? sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala 154:22]
  assign requests_io_push_bits_data_tag = sinkC_io_req_valid ? sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala 154:22]
  assign requests_io_push_bits_data_offset = sinkC_io_req_valid ? sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala 154:22]
  assign requests_io_push_bits_data_put = sinkC_io_req_valid ? sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala 154:22]
  assign requests_io_pop_valid = _mshr_uses_directory_assuming_no_bypass_T & ~bypass; // @[Scheduler.scala 204:45]
  assign requests_io_pop_bits = {_pop_index_T_2,_pop_index_T_19}; // @[Cat.scala 33:92]
  assign abc_mshrs_0_clock = clock;
  assign abc_mshrs_0_reset = reset;
  assign abc_mshrs_0_io_allocate_valid = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T |
    mshr_selectOH[0] & will_reload_1; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_0_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_0_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ? 1'h0
     : _mshrs_0_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_0_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_0_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_0_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_0_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_0_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_0_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_0_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_0_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_0_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_0_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_0_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[0] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_0_io_allocate_bits_tag == abc_mshrs_0_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_0_io_directory_valid = directoryFanout[0]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_0_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_0_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_0_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_0_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_0_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_0_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_0_io_schedule_ready = mshr_selectOH[0]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_0_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_0_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_0_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_0_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_0_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_0_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_0_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_0_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h0; // @[Scheduler.scala 78:45]
  assign abc_mshrs_0_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_0_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_0_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_0_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_0_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_0_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h0; // @[Scheduler.scala 79:45]
  assign abc_mshrs_0_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_0_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_0_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_0_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_0_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_0_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_1_clock = clock;
  assign abc_mshrs_1_reset = reset;
  assign abc_mshrs_1_io_allocate_valid = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T |
    mshr_selectOH[1] & will_reload_2; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_1_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_1_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ? 1'h0
     : _mshrs_1_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_1_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_1_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_1_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_1_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_1_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_1_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_1_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_1_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_1_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_1_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_1_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[1] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_1_io_allocate_bits_tag == abc_mshrs_1_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_1_io_directory_valid = directoryFanout[1]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_1_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_1_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_1_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_1_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_1_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_1_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_1_io_schedule_ready = mshr_selectOH[1]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_1_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_1_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_1_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_1_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_1_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_1_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_1_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_1_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h1; // @[Scheduler.scala 78:45]
  assign abc_mshrs_1_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_1_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_1_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_1_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_1_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_1_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h1; // @[Scheduler.scala 79:45]
  assign abc_mshrs_1_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_1_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_1_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_1_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_1_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_1_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_2_clock = clock;
  assign abc_mshrs_2_reset = reset;
  assign abc_mshrs_2_io_allocate_valid = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T |
    mshr_selectOH[2] & will_reload_3; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_2_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_2_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ? 1'h0
     : _mshrs_2_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_2_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_2_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_2_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_2_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_2_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_2_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_2_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_2_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_2_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_2_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_2_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[2] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_2_io_allocate_bits_tag == abc_mshrs_2_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_2_io_directory_valid = directoryFanout[2]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_2_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_2_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_2_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_2_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_2_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_2_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_2_io_schedule_ready = mshr_selectOH[2]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_2_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_2_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_2_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_2_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_2_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_2_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_2_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_2_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h2; // @[Scheduler.scala 78:45]
  assign abc_mshrs_2_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_2_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_2_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_2_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_2_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_2_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h2; // @[Scheduler.scala 79:45]
  assign abc_mshrs_2_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_2_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_2_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_2_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_2_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_2_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_3_clock = clock;
  assign abc_mshrs_3_reset = reset;
  assign abc_mshrs_3_io_allocate_valid = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T |
    mshr_selectOH[3] & will_reload_4; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_3_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_3_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ? 1'h0
     : _mshrs_3_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_3_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_3_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_3_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_3_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_3_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_3_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_3_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_3_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_3_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_3_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_3_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[3] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_3_io_allocate_bits_tag == abc_mshrs_3_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_3_io_directory_valid = directoryFanout[3]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_3_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_3_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_3_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_3_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_3_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_3_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_3_io_schedule_ready = mshr_selectOH[3]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_3_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_3_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_3_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_3_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_3_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_3_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_3_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_3_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h3; // @[Scheduler.scala 78:45]
  assign abc_mshrs_3_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_3_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_3_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_3_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_3_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_3_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h3; // @[Scheduler.scala 79:45]
  assign abc_mshrs_3_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_3_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_3_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_3_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_3_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_3_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_4_clock = clock;
  assign abc_mshrs_4_reset = reset;
  assign abc_mshrs_4_io_allocate_valid = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T |
    mshr_selectOH[4] & will_reload_5; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_4_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_4_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ? 1'h0
     : _mshrs_4_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_4_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_4_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_4_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_4_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_4_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_4_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_4_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_4_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_4_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_4_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_4_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[4] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_4_io_allocate_bits_tag == abc_mshrs_4_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_4_io_directory_valid = directoryFanout[4]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_4_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_4_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_4_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_4_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_4_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_4_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_4_io_schedule_ready = mshr_selectOH[4]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_4_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_4_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_4_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_4_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_4_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_4_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_4_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_4_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h4; // @[Scheduler.scala 78:45]
  assign abc_mshrs_4_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_4_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_4_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_4_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_4_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_4_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h4; // @[Scheduler.scala 79:45]
  assign abc_mshrs_4_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_4_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_4_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_4_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_4_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_4_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_5_clock = clock;
  assign abc_mshrs_5_reset = reset;
  assign abc_mshrs_5_io_allocate_valid = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T |
    mshr_selectOH[5] & will_reload_6; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_5_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_5_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ? 1'h0
     : _mshrs_5_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_5_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_5_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_5_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_5_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_5_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_5_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_5_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_5_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_5_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_5_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_5_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[5] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_5_io_allocate_bits_tag == abc_mshrs_5_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_5_io_directory_valid = directoryFanout[5]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_5_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_5_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_5_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_5_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_5_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_5_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_5_io_schedule_ready = mshr_selectOH[5]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_5_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_5_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_5_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_5_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_5_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_5_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_5_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_5_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h5; // @[Scheduler.scala 78:45]
  assign abc_mshrs_5_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_5_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_5_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_5_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_5_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_5_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h5; // @[Scheduler.scala 79:45]
  assign abc_mshrs_5_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_5_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_5_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_5_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_5_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_5_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_6_clock = clock;
  assign abc_mshrs_6_reset = reset;
  assign abc_mshrs_6_io_allocate_valid = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T |
    mshr_selectOH[6] & will_reload_7; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_6_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_6_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ? 1'h0
     : _mshrs_6_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_6_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_6_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_6_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_6_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_6_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_6_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_6_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_6_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_6_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_6_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_6_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[6] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_6_io_allocate_bits_tag == abc_mshrs_6_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_6_io_directory_valid = directoryFanout[6]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_6_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_6_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_6_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_6_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_6_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_6_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_6_io_schedule_ready = mshr_selectOH[6]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_6_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_6_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_6_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_6_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_6_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_6_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_6_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_6_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h6; // @[Scheduler.scala 78:45]
  assign abc_mshrs_6_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_6_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_6_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_6_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_6_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_6_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h6; // @[Scheduler.scala 79:45]
  assign abc_mshrs_6_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_6_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_6_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_6_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_6_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_6_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_7_clock = clock;
  assign abc_mshrs_7_reset = reset;
  assign abc_mshrs_7_io_allocate_valid = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T |
    mshr_selectOH[7] & will_reload_8; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_7_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_7_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ? 1'h0
     : _mshrs_7_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_7_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_7_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_7_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_7_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_7_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_7_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_7_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_7_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_7_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_7_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_7_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[7] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_7_io_allocate_bits_tag == abc_mshrs_7_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_7_io_directory_valid = directoryFanout[7]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_7_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_7_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_7_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_7_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_7_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_7_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_7_io_schedule_ready = mshr_selectOH[7]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_7_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_7_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_7_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_7_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_7_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_7_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_7_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_7_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h7; // @[Scheduler.scala 78:45]
  assign abc_mshrs_7_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_7_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_7_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_7_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_7_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_7_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h7; // @[Scheduler.scala 79:45]
  assign abc_mshrs_7_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_7_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_7_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_7_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_7_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_7_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_8_clock = clock;
  assign abc_mshrs_8_reset = reset;
  assign abc_mshrs_8_io_allocate_valid = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T |
    mshr_selectOH[8] & will_reload_9; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_8_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_8_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ? 1'h0
     : _mshrs_8_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_8_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_8_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_8_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_8_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_8_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_8_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_8_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_8_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_8_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_8_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_8_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[8] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_8_io_allocate_bits_tag == abc_mshrs_8_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_8_io_directory_valid = directoryFanout[8]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_8_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_8_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_8_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_8_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_8_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_8_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_8_io_schedule_ready = mshr_selectOH[8]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_8_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_8_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_8_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_8_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_8_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_8_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_8_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_8_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h8; // @[Scheduler.scala 78:45]
  assign abc_mshrs_8_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_8_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_8_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_8_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_8_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_8_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h8; // @[Scheduler.scala 79:45]
  assign abc_mshrs_8_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_8_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_8_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_8_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_8_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_8_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_9_clock = clock;
  assign abc_mshrs_9_reset = reset;
  assign abc_mshrs_9_io_allocate_valid = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T |
    mshr_selectOH[9] & will_reload_10; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_9_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_9_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ? 1'h0
     : _mshrs_9_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_9_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_9_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_9_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_9_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_9_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_9_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_9_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_9_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_9_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_9_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_9_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[9] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_9_io_allocate_bits_tag == abc_mshrs_9_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_9_io_directory_valid = directoryFanout[9]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_9_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_9_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_9_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_9_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_9_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_9_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_9_io_schedule_ready = mshr_selectOH[9]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_9_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_9_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_9_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_9_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_9_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_9_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_9_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_9_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h9; // @[Scheduler.scala 78:45]
  assign abc_mshrs_9_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_9_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_9_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_9_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_9_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_9_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h9; // @[Scheduler.scala 79:45]
  assign abc_mshrs_9_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_9_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_9_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_9_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_9_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_9_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_10_clock = clock;
  assign abc_mshrs_10_reset = reset;
  assign abc_mshrs_10_io_allocate_valid = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T |
    mshr_selectOH[10] & will_reload_11; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_10_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_10_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ? 1'h0
     : _mshrs_10_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_10_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_10_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_10_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_10_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_10_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_10_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_10_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_10_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_10_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_10_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_10_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[10] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_10_io_allocate_bits_tag == abc_mshrs_10_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_10_io_directory_valid = directoryFanout[10]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_10_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_10_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_10_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_10_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_10_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_10_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_10_io_schedule_ready = mshr_selectOH[10]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_10_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_10_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_10_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_10_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_10_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_10_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_10_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_10_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'ha; // @[Scheduler.scala 78:45]
  assign abc_mshrs_10_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_10_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_10_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_10_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_10_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_10_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'ha; // @[Scheduler.scala 79:45]
  assign abc_mshrs_10_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_10_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_10_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_10_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_10_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_10_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_11_clock = clock;
  assign abc_mshrs_11_reset = reset;
  assign abc_mshrs_11_io_allocate_valid = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T |
    mshr_selectOH[11] & will_reload_12; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_11_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_11_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ? 1'h0
     : _mshrs_11_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_11_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_11_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_11_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_11_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_11_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_11_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_11_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_11_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_11_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_11_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_11_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[11] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_11_io_allocate_bits_tag == abc_mshrs_11_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_11_io_directory_valid = directoryFanout[11]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_11_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_11_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_11_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_11_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_11_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_11_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_11_io_schedule_ready = mshr_selectOH[11]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_11_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_11_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_11_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_11_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_11_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_11_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_11_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_11_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'hb; // @[Scheduler.scala 78:45]
  assign abc_mshrs_11_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_11_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_11_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_11_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_11_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_11_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'hb; // @[Scheduler.scala 79:45]
  assign abc_mshrs_11_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_11_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_11_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_11_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_11_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_11_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_12_clock = clock;
  assign abc_mshrs_12_reset = reset;
  assign abc_mshrs_12_io_allocate_valid = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T |
    mshr_selectOH[12] & will_reload_13; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_12_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_12_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ? 1'h0
     : _mshrs_12_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_12_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_12_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_12_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_12_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_12_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_12_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_12_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_12_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_12_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_12_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_12_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[12] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_12_io_allocate_bits_tag == abc_mshrs_12_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_12_io_directory_valid = directoryFanout[12]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_12_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_12_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_12_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_12_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_12_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_12_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_12_io_schedule_ready = mshr_selectOH[12]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_12_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_12_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_12_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_12_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_12_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_12_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_12_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_12_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'hc; // @[Scheduler.scala 78:45]
  assign abc_mshrs_12_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_12_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_12_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_12_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_12_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_12_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'hc; // @[Scheduler.scala 79:45]
  assign abc_mshrs_12_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_12_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_12_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_12_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_12_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_12_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_13_clock = clock;
  assign abc_mshrs_13_reset = reset;
  assign abc_mshrs_13_io_allocate_valid = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T |
    mshr_selectOH[13] & will_reload_14; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_13_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_13_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ? 1'h0
     : _mshrs_13_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_13_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_13_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_13_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_13_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_13_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_13_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_13_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_13_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_13_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_13_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_13_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[13] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_13_io_allocate_bits_tag == abc_mshrs_13_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_13_io_directory_valid = directoryFanout[13]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_13_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_13_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_13_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_13_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_13_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_13_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_13_io_schedule_ready = mshr_selectOH[13]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_13_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_13_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_13_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_13_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_13_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_13_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_13_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_13_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'hd; // @[Scheduler.scala 78:45]
  assign abc_mshrs_13_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_13_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_13_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_13_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_13_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_13_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'hd; // @[Scheduler.scala 79:45]
  assign abc_mshrs_13_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_13_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_13_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_13_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_13_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_13_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_14_clock = clock;
  assign abc_mshrs_14_reset = reset;
  assign abc_mshrs_14_io_allocate_valid = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T |
    mshr_selectOH[14] & will_reload_15; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_14_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_14_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ? 1'h0
     : _mshrs_14_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_14_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_14_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_14_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_14_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_14_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_14_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_14_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_14_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_14_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_14_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_14_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[14] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_14_io_allocate_bits_tag == abc_mshrs_14_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_14_io_directory_valid = directoryFanout[14]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_14_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_14_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_14_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_14_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_14_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_14_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_14_io_schedule_ready = mshr_selectOH[14]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_14_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_14_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_14_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_14_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_14_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_14_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_14_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_14_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'he; // @[Scheduler.scala 78:45]
  assign abc_mshrs_14_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_14_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_14_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_14_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_14_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_14_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'he; // @[Scheduler.scala 79:45]
  assign abc_mshrs_14_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_14_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_14_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_14_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_14_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_14_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_15_clock = clock;
  assign abc_mshrs_15_reset = reset;
  assign abc_mshrs_15_io_allocate_valid = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T |
    mshr_selectOH[15] & will_reload_16; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_15_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_15_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ? 1'h0
     : _mshrs_15_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_15_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_15_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_15_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_15_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_15_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_15_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_15_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_15_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_15_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_15_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_15_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[15] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_15_io_allocate_bits_tag == abc_mshrs_15_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_15_io_directory_valid = directoryFanout[15]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_15_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_15_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_15_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_15_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_15_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_15_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_15_io_schedule_ready = mshr_selectOH[15]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_15_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_15_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_15_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_15_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_15_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_15_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_15_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_15_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'hf; // @[Scheduler.scala 78:45]
  assign abc_mshrs_15_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_15_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_15_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_15_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_15_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_15_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'hf; // @[Scheduler.scala 79:45]
  assign abc_mshrs_15_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_15_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_15_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_15_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_15_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_15_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_16_clock = clock;
  assign abc_mshrs_16_reset = reset;
  assign abc_mshrs_16_io_allocate_valid = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T |
    mshr_selectOH[16] & will_reload_17; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_16_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_16_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ? 1'h0
     : _mshrs_16_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_16_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_16_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_16_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_16_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_16_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_16_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_16_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_16_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_16_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_16_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_16_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[16] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_16_io_allocate_bits_tag == abc_mshrs_16_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_16_io_directory_valid = directoryFanout[16]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_16_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_16_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_16_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_16_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_16_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_16_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_16_io_schedule_ready = mshr_selectOH[16]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_16_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_16_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_16_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_16_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_16_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_16_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_16_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_16_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h10; // @[Scheduler.scala 78:45]
  assign abc_mshrs_16_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_16_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_16_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_16_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_16_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_16_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h10; // @[Scheduler.scala 79:45]
  assign abc_mshrs_16_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_16_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_16_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_16_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_16_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_16_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_17_clock = clock;
  assign abc_mshrs_17_reset = reset;
  assign abc_mshrs_17_io_allocate_valid = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T |
    mshr_selectOH[17] & will_reload_18; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_17_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_17_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ? 1'h0
     : _mshrs_17_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_17_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_17_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_17_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_17_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_17_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_17_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_17_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_17_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_17_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_17_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_17_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[17] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_17_io_allocate_bits_tag == abc_mshrs_17_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_17_io_directory_valid = directoryFanout[17]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_17_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_17_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_17_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_17_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_17_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_17_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_17_io_schedule_ready = mshr_selectOH[17]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_17_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_17_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_17_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_17_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_17_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_17_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_17_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_17_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h11; // @[Scheduler.scala 78:45]
  assign abc_mshrs_17_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_17_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_17_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_17_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_17_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_17_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h11; // @[Scheduler.scala 79:45]
  assign abc_mshrs_17_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_17_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_17_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_17_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_17_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_17_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_18_clock = clock;
  assign abc_mshrs_18_reset = reset;
  assign abc_mshrs_18_io_allocate_valid = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T |
    mshr_selectOH[18] & will_reload_19; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_18_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_18_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ? 1'h0
     : _mshrs_18_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_18_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_18_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_18_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_18_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_18_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_18_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_18_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_18_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_18_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_18_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_18_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[18] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_18_io_allocate_bits_tag == abc_mshrs_18_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_18_io_directory_valid = directoryFanout[18]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_18_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_18_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_18_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_18_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_18_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_18_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_18_io_schedule_ready = mshr_selectOH[18]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_18_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_18_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_18_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_18_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_18_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_18_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_18_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_18_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h12; // @[Scheduler.scala 78:45]
  assign abc_mshrs_18_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_18_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_18_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_18_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_18_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_18_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h12; // @[Scheduler.scala 79:45]
  assign abc_mshrs_18_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_18_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_18_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_18_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_18_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_18_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign abc_mshrs_19_clock = clock;
  assign abc_mshrs_19_reset = reset;
  assign abc_mshrs_19_io_allocate_valid = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T |
    mshr_selectOH[19] & will_reload_20; // @[Scheduler.scala 225:25 269:83 270:27]
  assign abc_mshrs_19_io_allocate_bits_prio_0 = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_prio_0 : _mshrs_19_io_allocate_bits_T_prio_0; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ? 1'h0
     : _mshrs_19_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_19_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_19_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_19_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_19_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_19_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_19_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_19_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_19_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign abc_mshrs_19_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ?
    request_bits_set : abc_mshrs_19_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign abc_mshrs_19_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[19] & _request_alloc_cases_T ? 1'h0
     : abc_mshrs_19_io_allocate_bits_tag == abc_mshrs_19_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign abc_mshrs_19_io_directory_valid = directoryFanout[19]; // @[Scheduler.scala 298:44]
  assign abc_mshrs_19_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign abc_mshrs_19_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign abc_mshrs_19_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign abc_mshrs_19_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign abc_mshrs_19_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign abc_mshrs_19_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign abc_mshrs_19_io_schedule_ready = mshr_selectOH[19]; // @[Scheduler.scala 212:28]
  assign abc_mshrs_19_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == abc_mshrs_19_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign abc_mshrs_19_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign abc_mshrs_19_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign abc_mshrs_19_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign abc_mshrs_19_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign abc_mshrs_19_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign abc_mshrs_19_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h13; // @[Scheduler.scala 78:45]
  assign abc_mshrs_19_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign abc_mshrs_19_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign abc_mshrs_19_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign abc_mshrs_19_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign abc_mshrs_19_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign abc_mshrs_19_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h13; // @[Scheduler.scala 79:45]
  assign abc_mshrs_19_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign abc_mshrs_19_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign abc_mshrs_19_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign abc_mshrs_19_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign abc_mshrs_19_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign abc_mshrs_19_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign bc_mshr_clock = clock;
  assign bc_mshr_reset = reset;
  assign bc_mshr_io_allocate_valid = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T | mshr_selectOH[
    20] & will_reload_21; // @[Scheduler.scala 225:25 269:83 270:27]
  assign bc_mshr_io_allocate_bits_prio_0 = 1'h0; // @[Scheduler.scala 282:36]
  assign bc_mshr_io_allocate_bits_prio_1 = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ? 1'h0 :
    _mshrs_20_io_allocate_bits_T_prio_1; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_prio_2 = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_prio_2 : _mshrs_20_io_allocate_bits_T_prio_2; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_opcode = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_opcode : _mshrs_20_io_allocate_bits_T_opcode; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_param = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_param : _mshrs_20_io_allocate_bits_T_param; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_size = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_size : _mshrs_20_io_allocate_bits_T_size; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_source = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_source : _mshrs_20_io_allocate_bits_T_source; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_tag = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_tag : _mshrs_20_io_allocate_bits_T_tag; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_offset = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_offset : _mshrs_20_io_allocate_bits_T_offset; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_put = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_put : _mshrs_20_io_allocate_bits_T_put; // @[Scheduler.scala 222:24 269:83 271:26]
  assign bc_mshr_io_allocate_bits_set = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ?
    request_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 269:83 271:26 223:28]
  assign bc_mshr_io_allocate_bits_repeat = request_valid & alloc & mshr_insertOH[20] & _request_alloc_cases_T ? 1'h0 :
    bc_mshr_io_allocate_bits_tag == bc_mshr_io_status_bits_tag; // @[Scheduler.scala 224:31 269:83 272:33]
  assign bc_mshr_io_directory_valid = directoryFanout[20]; // @[Scheduler.scala 298:44]
  assign bc_mshr_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign bc_mshr_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign bc_mshr_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign bc_mshr_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign bc_mshr_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign bc_mshr_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign bc_mshr_io_schedule_ready = mshr_selectOH[20]; // @[Scheduler.scala 212:28]
  assign bc_mshr_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == bc_mshr_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign bc_mshr_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign bc_mshr_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign bc_mshr_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign bc_mshr_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign bc_mshr_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign bc_mshr_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h14; // @[Scheduler.scala 78:45]
  assign bc_mshr_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign bc_mshr_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign bc_mshr_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign bc_mshr_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign bc_mshr_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign bc_mshr_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h14; // @[Scheduler.scala 79:45]
  assign bc_mshr_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign bc_mshr_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign bc_mshr_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign bc_mshr_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign bc_mshr_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign bc_mshr_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  assign c_mshr_clock = clock;
  assign c_mshr_reset = reset;
  assign c_mshr_io_allocate_valid = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T | _GEN_295
    ; // @[Scheduler.scala 284:103 285:30]
  assign c_mshr_io_allocate_bits_prio_0 = 1'h0; // @[Scheduler.scala 291:35]
  assign c_mshr_io_allocate_bits_prio_1 = 1'h0; // @[Scheduler.scala 292:35]
  assign c_mshr_io_allocate_bits_prio_2 = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_prio_2 : _GEN_298; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_opcode = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_opcode : _GEN_300; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_param = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_param : _GEN_301; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_size = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_size : _GEN_302; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_source = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_source : _GEN_303; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_tag = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_tag : _GEN_304; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_offset = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_offset : _GEN_305; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_put = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_put : _GEN_306; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_set = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ?
    request_bits_set : _GEN_307; // @[Scheduler.scala 284:103 286:29]
  assign c_mshr_io_allocate_bits_repeat = request_valid & nestC & _request_alloc_cases_T_7 & _request_alloc_cases_T ? 1'h0
     : _GEN_308; // @[Scheduler.scala 284:103 287:36]
  assign c_mshr_io_directory_valid = directoryFanout[21]; // @[Scheduler.scala 298:44]
  assign c_mshr_io_directory_bits_dirty = directory_io_result_bits_dirty; // @[Scheduler.scala 299:25]
  assign c_mshr_io_directory_bits_state = directory_io_result_bits_state; // @[Scheduler.scala 299:25]
  assign c_mshr_io_directory_bits_clients = directory_io_result_bits_clients; // @[Scheduler.scala 299:25]
  assign c_mshr_io_directory_bits_tag = directory_io_result_bits_tag; // @[Scheduler.scala 299:25]
  assign c_mshr_io_directory_bits_hit = directory_io_result_bits_hit; // @[Scheduler.scala 299:25]
  assign c_mshr_io_directory_bits_way = directory_io_result_bits_way; // @[Scheduler.scala 299:25]
  assign c_mshr_io_schedule_ready = mshr_selectOH[21]; // @[Scheduler.scala 212:28]
  assign c_mshr_io_sinkc_valid = sinkC_io_resp_valid & sinkC_io_resp_bits_set == c_mshr_io_status_bits_set; // @[Scheduler.scala 77:45]
  assign c_mshr_io_sinkc_bits_last = sinkC_io_resp_bits_last; // @[Scheduler.scala 80:21]
  assign c_mshr_io_sinkc_bits_tag = sinkC_io_resp_bits_tag; // @[Scheduler.scala 80:21]
  assign c_mshr_io_sinkc_bits_source = sinkC_io_resp_bits_source; // @[Scheduler.scala 80:21]
  assign c_mshr_io_sinkc_bits_param = sinkC_io_resp_bits_param; // @[Scheduler.scala 80:21]
  assign c_mshr_io_sinkc_bits_data = sinkC_io_resp_bits_data; // @[Scheduler.scala 80:21]
  assign c_mshr_io_sinkd_valid = sinkD_io_resp_valid & sinkD_io_resp_bits_source == 5'h15; // @[Scheduler.scala 78:45]
  assign c_mshr_io_sinkd_bits_last = sinkD_io_resp_bits_last; // @[Scheduler.scala 81:21]
  assign c_mshr_io_sinkd_bits_opcode = sinkD_io_resp_bits_opcode; // @[Scheduler.scala 81:21]
  assign c_mshr_io_sinkd_bits_param = sinkD_io_resp_bits_param; // @[Scheduler.scala 81:21]
  assign c_mshr_io_sinkd_bits_sink = sinkD_io_resp_bits_sink; // @[Scheduler.scala 81:21]
  assign c_mshr_io_sinkd_bits_denied = sinkD_io_resp_bits_denied; // @[Scheduler.scala 81:21]
  assign c_mshr_io_sinke_valid = sinkE_io_resp_valid & sinkE_io_resp_bits_sink == 5'h15; // @[Scheduler.scala 79:45]
  assign c_mshr_io_nestedwb_set = mshr_selectOH[21] ? c_mshr_io_status_bits_set : bc_mshr_io_status_bits_set; // @[Scheduler.scala 144:24]
  assign c_mshr_io_nestedwb_tag = mshr_selectOH[21] ? c_mshr_io_status_bits_tag : bc_mshr_io_status_bits_tag; // @[Scheduler.scala 145:24]
  assign c_mshr_io_nestedwb_b_toN = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala 146:75]
  assign c_mshr_io_nestedwb_b_toB = _schedule_T_343 & bc_mshr_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala 147:75]
  assign c_mshr_io_nestedwb_b_clr_dirty = mshr_selectOH[20] & bc_mshr_io_schedule_bits_dir_valid; // @[Scheduler.scala 148:37]
  assign c_mshr_io_nestedwb_c_set_dirty = _schedule_T_344 & c_mshr_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala 149:75]
  always @(posedge clock) begin
    if (reset) begin // @[Scheduler.scala 116:29]
      robin_filter <= 22'h0; // @[Scheduler.scala 116:29]
    end else if (|mshr_request) begin // @[Scheduler.scala 126:29]
      robin_filter <= _robin_filter_T_11; // @[Scheduler.scala 126:44]
    end
    if (mshr_uses_directory) begin // @[Scheduler.scala 296:50]
      directoryFanout <= {{1'd0}, mshr_selectOH};
    end else if (alloc_uses_directory) begin // @[Scheduler.scala 296:90]
      if (alloc) begin // @[Scheduler.scala 295:22]
        directoryFanout <= mshr_insertOH;
      end else begin
        directoryFanout <= 23'h200000;
      end
    end else begin
      directoryFanout <= 23'h0;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_prioFilter_T & 1'h0) begin
          $fatal; // @[Scheduler.scala 280:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_155 & _T_149 & _T_150) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Scheduler.scala:288 assert (!request.bits.prio(0))\n"); // @[Scheduler.scala 288:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_prioFilter_T & (_T_155 & _T_149)) begin
          $fatal; // @[Scheduler.scala 288:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_155 & _T_149)) begin
          $fatal; // @[Scheduler.scala 289:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  robin_filter = _RAND_0[21:0];
  _RAND_1 = {1{`RANDOM}};
  directoryFanout = _RAND_1[22:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module InclusiveCache(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [2:0]  auto_in_a_bits_source,
  input  [31:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [1:0]  auto_in_b_bits_param,
  output [31:0] auto_in_b_bits_address,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [2:0]  auto_in_c_bits_size,
  input  [31:0] auto_in_c_bits_address,
  input  [63:0] auto_in_c_bits_data,
  input         auto_in_c_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [2:0]  auto_in_d_bits_source,
  output [4:0]  auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [63:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_in_e_valid,
  input  [4:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [4:0]  auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [2:0]  auto_out_c_bits_size,
  output [4:0]  auto_out_c_bits_source,
  output [31:0] auto_out_c_bits_address,
  output [63:0] auto_out_c_bits_data,
  output        auto_out_c_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [4:0]  auto_out_d_bits_source,
  input  [2:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [63:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt,
  output        auto_out_e_valid,
  output [2:0]  auto_out_e_bits_sink
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_b_bits_param; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_b_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  wire  mods_0_clock; // @[InclusiveCache.scala 199:29]
  wire  mods_0_reset; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_a_ready; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_a_valid; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_a_bits_opcode; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_a_bits_param; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_a_bits_size; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_a_bits_source; // @[InclusiveCache.scala 199:29]
  wire [31:0] mods_0_io_in_a_bits_address; // @[InclusiveCache.scala 199:29]
  wire [7:0] mods_0_io_in_a_bits_mask; // @[InclusiveCache.scala 199:29]
  wire [63:0] mods_0_io_in_a_bits_data; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_a_bits_corrupt; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_b_ready; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_b_valid; // @[InclusiveCache.scala 199:29]
  wire [1:0] mods_0_io_in_b_bits_param; // @[InclusiveCache.scala 199:29]
  wire [31:0] mods_0_io_in_b_bits_address; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_c_ready; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_c_valid; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_c_bits_opcode; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_c_bits_param; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_c_bits_size; // @[InclusiveCache.scala 199:29]
  wire [31:0] mods_0_io_in_c_bits_address; // @[InclusiveCache.scala 199:29]
  wire [63:0] mods_0_io_in_c_bits_data; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_c_bits_corrupt; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_d_ready; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_d_valid; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_d_bits_opcode; // @[InclusiveCache.scala 199:29]
  wire [1:0] mods_0_io_in_d_bits_param; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_d_bits_size; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_in_d_bits_source; // @[InclusiveCache.scala 199:29]
  wire [4:0] mods_0_io_in_d_bits_sink; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_d_bits_denied; // @[InclusiveCache.scala 199:29]
  wire [63:0] mods_0_io_in_d_bits_data; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_d_bits_corrupt; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_in_e_valid; // @[InclusiveCache.scala 199:29]
  wire [4:0] mods_0_io_in_e_bits_sink; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_a_ready; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_a_valid; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_a_bits_opcode; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_a_bits_param; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_a_bits_size; // @[InclusiveCache.scala 199:29]
  wire [4:0] mods_0_io_out_a_bits_source; // @[InclusiveCache.scala 199:29]
  wire [31:0] mods_0_io_out_a_bits_address; // @[InclusiveCache.scala 199:29]
  wire [7:0] mods_0_io_out_a_bits_mask; // @[InclusiveCache.scala 199:29]
  wire [63:0] mods_0_io_out_a_bits_data; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_a_bits_corrupt; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_c_ready; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_c_valid; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_c_bits_opcode; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_c_bits_param; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_c_bits_size; // @[InclusiveCache.scala 199:29]
  wire [4:0] mods_0_io_out_c_bits_source; // @[InclusiveCache.scala 199:29]
  wire [31:0] mods_0_io_out_c_bits_address; // @[InclusiveCache.scala 199:29]
  wire [63:0] mods_0_io_out_c_bits_data; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_c_bits_corrupt; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_d_ready; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_d_valid; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_d_bits_opcode; // @[InclusiveCache.scala 199:29]
  wire [1:0] mods_0_io_out_d_bits_param; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_d_bits_size; // @[InclusiveCache.scala 199:29]
  wire [4:0] mods_0_io_out_d_bits_source; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_d_bits_sink; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_d_bits_denied; // @[InclusiveCache.scala 199:29]
  wire [63:0] mods_0_io_out_d_bits_data; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_d_bits_corrupt; // @[InclusiveCache.scala 199:29]
  wire  mods_0_io_out_e_valid; // @[InclusiveCache.scala 199:29]
  wire [2:0] mods_0_io_out_e_bits_sink; // @[InclusiveCache.scala 199:29]
  TLMonitor monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_b_ready(monitor_io_in_b_ready),
    .io_in_b_valid(monitor_io_in_b_valid),
    .io_in_b_bits_param(monitor_io_in_b_bits_param),
    .io_in_b_bits_address(monitor_io_in_b_bits_address),
    .io_in_c_ready(monitor_io_in_c_ready),
    .io_in_c_valid(monitor_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_io_in_c_bits_size),
    .io_in_c_bits_address(monitor_io_in_c_bits_address),
    .io_in_c_bits_corrupt(monitor_io_in_c_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt),
    .io_in_e_valid(monitor_io_in_e_valid),
    .io_in_e_bits_sink(monitor_io_in_e_bits_sink)
  );
  Scheduler mods_0 ( // @[InclusiveCache.scala 199:29]
    .clock(mods_0_clock),
    .reset(mods_0_reset),
    .io_in_a_ready(mods_0_io_in_a_ready),
    .io_in_a_valid(mods_0_io_in_a_valid),
    .io_in_a_bits_opcode(mods_0_io_in_a_bits_opcode),
    .io_in_a_bits_param(mods_0_io_in_a_bits_param),
    .io_in_a_bits_size(mods_0_io_in_a_bits_size),
    .io_in_a_bits_source(mods_0_io_in_a_bits_source),
    .io_in_a_bits_address(mods_0_io_in_a_bits_address),
    .io_in_a_bits_mask(mods_0_io_in_a_bits_mask),
    .io_in_a_bits_data(mods_0_io_in_a_bits_data),
    .io_in_a_bits_corrupt(mods_0_io_in_a_bits_corrupt),
    .io_in_b_ready(mods_0_io_in_b_ready),
    .io_in_b_valid(mods_0_io_in_b_valid),
    .io_in_b_bits_param(mods_0_io_in_b_bits_param),
    .io_in_b_bits_address(mods_0_io_in_b_bits_address),
    .io_in_c_ready(mods_0_io_in_c_ready),
    .io_in_c_valid(mods_0_io_in_c_valid),
    .io_in_c_bits_opcode(mods_0_io_in_c_bits_opcode),
    .io_in_c_bits_param(mods_0_io_in_c_bits_param),
    .io_in_c_bits_size(mods_0_io_in_c_bits_size),
    .io_in_c_bits_address(mods_0_io_in_c_bits_address),
    .io_in_c_bits_data(mods_0_io_in_c_bits_data),
    .io_in_c_bits_corrupt(mods_0_io_in_c_bits_corrupt),
    .io_in_d_ready(mods_0_io_in_d_ready),
    .io_in_d_valid(mods_0_io_in_d_valid),
    .io_in_d_bits_opcode(mods_0_io_in_d_bits_opcode),
    .io_in_d_bits_param(mods_0_io_in_d_bits_param),
    .io_in_d_bits_size(mods_0_io_in_d_bits_size),
    .io_in_d_bits_source(mods_0_io_in_d_bits_source),
    .io_in_d_bits_sink(mods_0_io_in_d_bits_sink),
    .io_in_d_bits_denied(mods_0_io_in_d_bits_denied),
    .io_in_d_bits_data(mods_0_io_in_d_bits_data),
    .io_in_d_bits_corrupt(mods_0_io_in_d_bits_corrupt),
    .io_in_e_valid(mods_0_io_in_e_valid),
    .io_in_e_bits_sink(mods_0_io_in_e_bits_sink),
    .io_out_a_ready(mods_0_io_out_a_ready),
    .io_out_a_valid(mods_0_io_out_a_valid),
    .io_out_a_bits_opcode(mods_0_io_out_a_bits_opcode),
    .io_out_a_bits_param(mods_0_io_out_a_bits_param),
    .io_out_a_bits_size(mods_0_io_out_a_bits_size),
    .io_out_a_bits_source(mods_0_io_out_a_bits_source),
    .io_out_a_bits_address(mods_0_io_out_a_bits_address),
    .io_out_a_bits_mask(mods_0_io_out_a_bits_mask),
    .io_out_a_bits_data(mods_0_io_out_a_bits_data),
    .io_out_a_bits_corrupt(mods_0_io_out_a_bits_corrupt),
    .io_out_c_ready(mods_0_io_out_c_ready),
    .io_out_c_valid(mods_0_io_out_c_valid),
    .io_out_c_bits_opcode(mods_0_io_out_c_bits_opcode),
    .io_out_c_bits_param(mods_0_io_out_c_bits_param),
    .io_out_c_bits_size(mods_0_io_out_c_bits_size),
    .io_out_c_bits_source(mods_0_io_out_c_bits_source),
    .io_out_c_bits_address(mods_0_io_out_c_bits_address),
    .io_out_c_bits_data(mods_0_io_out_c_bits_data),
    .io_out_c_bits_corrupt(mods_0_io_out_c_bits_corrupt),
    .io_out_d_ready(mods_0_io_out_d_ready),
    .io_out_d_valid(mods_0_io_out_d_valid),
    .io_out_d_bits_opcode(mods_0_io_out_d_bits_opcode),
    .io_out_d_bits_param(mods_0_io_out_d_bits_param),
    .io_out_d_bits_size(mods_0_io_out_d_bits_size),
    .io_out_d_bits_source(mods_0_io_out_d_bits_source),
    .io_out_d_bits_sink(mods_0_io_out_d_bits_sink),
    .io_out_d_bits_denied(mods_0_io_out_d_bits_denied),
    .io_out_d_bits_data(mods_0_io_out_d_bits_data),
    .io_out_d_bits_corrupt(mods_0_io_out_d_bits_corrupt),
    .io_out_e_valid(mods_0_io_out_e_valid),
    .io_out_e_bits_sink(mods_0_io_out_e_bits_sink)
  );
  assign auto_in_a_ready = mods_0_io_in_a_ready; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_b_valid = mods_0_io_in_b_valid; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_b_bits_param = mods_0_io_in_b_bits_param; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_b_bits_address = mods_0_io_in_b_bits_address; // @[Parameters.scala 244:14]
  assign auto_in_c_ready = mods_0_io_in_c_ready; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_valid = mods_0_io_in_d_valid; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_bits_opcode = mods_0_io_in_d_bits_opcode; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_bits_param = mods_0_io_in_d_bits_param; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_bits_size = mods_0_io_in_d_bits_size; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_bits_source = mods_0_io_in_d_bits_source; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_bits_sink = mods_0_io_in_d_bits_sink; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_bits_denied = mods_0_io_in_d_bits_denied; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_bits_data = mods_0_io_in_d_bits_data; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_in_d_bits_corrupt = mods_0_io_in_d_bits_corrupt; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign auto_out_a_valid = mods_0_io_out_a_valid; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_a_bits_opcode = mods_0_io_out_a_bits_opcode; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_a_bits_param = mods_0_io_out_a_bits_param; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_a_bits_size = mods_0_io_out_a_bits_size; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_a_bits_source = mods_0_io_out_a_bits_source; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_a_bits_address = mods_0_io_out_a_bits_address; // @[Parameters.scala 244:14]
  assign auto_out_a_bits_mask = mods_0_io_out_a_bits_mask; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_a_bits_data = mods_0_io_out_a_bits_data; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_a_bits_corrupt = mods_0_io_out_a_bits_corrupt; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_c_valid = mods_0_io_out_c_valid; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_c_bits_opcode = mods_0_io_out_c_bits_opcode; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_c_bits_param = mods_0_io_out_c_bits_param; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_c_bits_size = mods_0_io_out_c_bits_size; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_c_bits_source = mods_0_io_out_c_bits_source; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_c_bits_address = mods_0_io_out_c_bits_address; // @[Parameters.scala 244:14]
  assign auto_out_c_bits_data = mods_0_io_out_c_bits_data; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_c_bits_corrupt = mods_0_io_out_c_bits_corrupt; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_d_ready = mods_0_io_out_d_ready; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_e_valid = mods_0_io_out_e_valid; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign auto_out_e_bits_sink = mods_0_io_out_e_bits_sink; // @[Nodes.scala 1207:84 InclusiveCache.scala 202:11]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = mods_0_io_in_a_ready; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_valid = mods_0_io_in_b_valid; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_b_bits_param = mods_0_io_in_b_bits_param; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_b_bits_address = mods_0_io_in_b_bits_address; // @[Parameters.scala 244:14]
  assign monitor_io_in_c_ready = mods_0_io_in_c_ready; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = mods_0_io_in_d_valid; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_d_bits_opcode = mods_0_io_in_d_bits_opcode; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_d_bits_param = mods_0_io_in_d_bits_param; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_d_bits_size = mods_0_io_in_d_bits_size; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_d_bits_source = mods_0_io_in_d_bits_source; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_d_bits_sink = mods_0_io_in_d_bits_sink; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_d_bits_denied = mods_0_io_in_d_bits_denied; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_d_bits_corrupt = mods_0_io_in_d_bits_corrupt; // @[Nodes.scala 1210:84 InclusiveCache.scala 201:23]
  assign monitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_clock = clock;
  assign mods_0_reset = reset;
  assign mods_0_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_c_bits_data = auto_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign mods_0_io_out_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mods_0_io_out_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[InclusiveCache.scala 209:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module TLMonitor_1(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [9:0]  io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [9:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [543:0] _RAND_10;
  reg [2079:0] _RAND_11;
  reg [2079:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [543:0] _RAND_16;
  reg [2079:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [8:0] source_ok_uncommonBits = io_in_a_bits_source[8:0]; // @[Parameters.scala 52:64]
  wire  _source_ok_T_1 = ~io_in_a_bits_source[9]; // @[Parameters.scala 54:32]
  wire  _source_ok_T_4 = source_ok_uncommonBits <= 9'h13f; // @[Parameters.scala 57:20]
  wire  _source_ok_T_5 = _source_ok_T_1 & _source_ok_T_4; // @[Parameters.scala 56:50]
  wire  _source_ok_T_6 = io_in_a_bits_source == 10'h201; // @[Parameters.scala 46:9]
  wire  _source_ok_T_7 = io_in_a_bits_source == 10'h200; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T_5 | _source_ok_T_6 | _source_ok_T_7; // @[Parameters.scala 1125:46]
  wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_15 = {{29'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_15; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
  wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire [32:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_38 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_54 = _source_ok_T_6 | _source_ok_T_7; // @[Parameters.scala 1161:43]
  wire  _T_57 = _source_ok_T_5 | _T_54; // @[Parameters.scala 1162:30]
  wire [32:0] _T_62 = $signed(_T_12) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_63 = $signed(_T_62) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_95 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_99 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_100 = _T_99 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_104 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_108 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_169 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_182 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_205 = 2'h3 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_212 = _T_205 & _T_63; // @[Parameters.scala 670:56]
  wire  _T_223 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_227 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_235 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_264 = _T_57 & _T_212; // @[Monitor.scala 115:71]
  wire  _T_282 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_325 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_326 = io_in_a_bits_mask & _T_325; // @[Monitor.scala 127:31]
  wire  _T_327 = _T_326 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_331 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_369 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_377 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_415 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_423 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_461 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_473 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire [8:0] source_ok_uncommonBits_1 = io_in_d_bits_source[8:0]; // @[Parameters.scala 52:64]
  wire  _source_ok_T_10 = ~io_in_d_bits_source[9]; // @[Parameters.scala 54:32]
  wire  _source_ok_T_13 = source_ok_uncommonBits_1 <= 9'h13f; // @[Parameters.scala 57:20]
  wire  _source_ok_T_14 = _source_ok_T_10 & _source_ok_T_13; // @[Parameters.scala 56:50]
  wire  _source_ok_T_15 = io_in_d_bits_source == 10'h201; // @[Parameters.scala 46:9]
  wire  _source_ok_T_16 = io_in_d_bits_source == 10'h200; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_14 | _source_ok_T_15 | _source_ok_T_16; // @[Parameters.scala 1125:46]
  wire  _T_477 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_481 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
  wire  _T_497 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_525 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_554 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_571 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_589 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [9:0] source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_619 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_620 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_624 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_628 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_632 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_636 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [9:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_643 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_644 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_652 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_656 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [513:0] inflight; // @[Monitor.scala 611:27]
  reg [2055:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [2055:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [11:0] _GEN_21 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [12:0] _a_opcode_lookup_T = {{1'd0}, _GEN_21}; // @[Monitor.scala 634:69]
  wire [2055:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [2055:0] _GEN_60 = {{2040'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [2055:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_60; // @[Monitor.scala 634:97]
  wire [2055:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[2055:1]}; // @[Monitor.scala 634:152]
  wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [2055:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_60; // @[Monitor.scala 638:91]
  wire [2055:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala 638:144]
  wire  _T_673 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [1023:0] _a_set_T = 1024'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [11:0] _GEN_71 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [12:0] _a_opcodes_set_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [8194:0] _GEN_305 = {{8191'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [8194:0] _a_opcodes_set_T_1 = _GEN_305 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [8193:0] _GEN_306 = {{8191'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [8193:0] _a_sizes_set_T_1 = _GEN_306 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [513:0] _T_675 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_677 = ~_T_675[0]; // @[Monitor.scala 658:17]
  wire [1023:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_T : 1024'h0; // @[Monitor.scala 652:72 653:28]
  wire [8194:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 8195'h0; // @[Monitor.scala 652:72 656:28]
  wire [8193:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 8194'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_688 = ~_T_477; // @[Monitor.scala 675:75]
  wire [1023:0] _d_clr_T = 1024'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [8206:0] _GEN_307 = {{8191'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [8206:0] _d_opcodes_clr_T_5 = _GEN_307 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1023:0] _GEN_22 = _d_first_T & d_first_1 & ~_T_477 ? _d_clr_T : 1024'h0; // @[Monitor.scala 675:91 676:21]
  wire [8206:0] _GEN_23 = _d_first_T & d_first_1 & ~_T_477 ? _d_opcodes_clr_T_5 : 8207'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_690 = io_in_d_valid & d_first_1; // @[Monitor.scala 680:26]
  wire  _T_693 = io_in_d_valid & d_first_1 & _T_688; // @[Monitor.scala 680:71]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = io_in_a_valid & a_first_1 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [513:0] _T_694 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_696 = _T_694[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_701 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_702 = io_in_d_bits_opcode == _GEN_32 | _T_701; // @[Monitor.scala 685:77]
  wire  _T_706 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_713 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_714 = io_in_d_bits_opcode == _GEN_48 | _T_713; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_75 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_718 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_728 = _T_690 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_688; // @[Monitor.scala 694:116]
  wire  _T_729 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_730 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [513:0] a_set = _GEN_16[513:0];
  wire [513:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [513:0] d_clr = _GEN_22[513:0];
  wire [513:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [513:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [2055:0] a_opcodes_set = _GEN_19[2055:0];
  wire [2055:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [2055:0] d_opcodes_clr = _GEN_23[2055:0];
  wire [2055:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [2055:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [2055:0] a_sizes_set = _GEN_20[2055:0];
  wire [2055:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_739 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [513:0] inflight_1; // @[Monitor.scala 723:35]
  reg [2055:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [2055:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_60; // @[Monitor.scala 747:93]
  wire [2055:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala 747:146]
  wire  _T_759 = ~inflight_1[0]; // @[Monitor.scala 766:17]
  wire [1023:0] _GEN_67 = _d_first_T & d_first_2 & _T_477 ? _d_clr_T : 1024'h0; // @[Monitor.scala 783:90 784:21]
  wire [8206:0] _GEN_69 = _d_first_T & d_first_2 & _T_477 ? _d_opcodes_clr_T_5 : 8207'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_772 = io_in_d_valid & d_first_2 & _T_477; // @[Monitor.scala 789:71]
  wire [513:0] _T_773 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_779 = io_in_d_bits_size == 2'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_783 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [513:0] d_clr_1 = _GEN_67[513:0];
  wire [513:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [513:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [2055:0] d_sizes_clr_1 = _GEN_69[2055:0];
  wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [2055:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_803 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 514'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 2056'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 2056'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 514'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 2056'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_38 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_38 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_38 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_38 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_38 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_38 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_38 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_38 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_38 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_38 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_38 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_38 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_38 & ~reset & ~_T_100) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_100 & (io_in_a_valid & _T_38 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_38 & ~reset & ~_T_104) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_104 & (io_in_a_valid & _T_38 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset & ~_T_100) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_100 & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_108 & ~reset & ~_T_104) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_104 & (io_in_a_valid & _T_108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_182 & ~reset & ~_T_57) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_57 & (io_in_a_valid & _T_182 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_182 & ~reset & ~_T_212) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_212 & (io_in_a_valid & _T_182 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_182 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_182 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_182 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_182 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_182 & ~reset & ~_T_223) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_223 & (io_in_a_valid & _T_182 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_182 & ~reset & ~_T_227) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_227 & (io_in_a_valid & _T_182 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_182 & ~reset & ~_T_104) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_104 & (io_in_a_valid & _T_182 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_235 & ~reset & ~_T_264) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_264 & (io_in_a_valid & _T_235 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_235 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_235 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_235 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_235 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_235 & ~reset & ~_T_223) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_223 & (io_in_a_valid & _T_235 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_235 & ~reset & ~_T_227) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_227 & (io_in_a_valid & _T_235 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_282 & ~reset & ~_T_264) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_264 & (io_in_a_valid & _T_282 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_282 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_282 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_282 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_282 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_282 & ~reset & ~_T_223) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_223 & (io_in_a_valid & _T_282 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_282 & ~reset & ~_T_327) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_327 & (io_in_a_valid & _T_282 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_331 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_331 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_331 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_331 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_331 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_331 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_331 & ~reset & ~_T_369) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_369 & (io_in_a_valid & _T_331 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_331 & ~reset & ~_T_227) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_227 & (io_in_a_valid & _T_331 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_377 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_377 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_377 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_377 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_377 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_377 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_377 & ~reset & ~_T_415) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_415 & (io_in_a_valid & _T_377 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_377 & ~reset & ~_T_227) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_227 & (io_in_a_valid & _T_377 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_423 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_423 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_423 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_423 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_423 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_423 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_423 & ~reset & ~_T_461) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_461 & (io_in_a_valid & _T_423 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_423 & ~reset & ~_T_227) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_227 & (io_in_a_valid & _T_423 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_423 & ~reset & ~_T_104) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_104 & (io_in_a_valid & _T_423 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_473) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_473 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_477 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_477 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_477 & _T_2 & ~_T_481) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_481 & (io_in_d_valid & _T_477 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_477 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_477 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_477 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_497 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_497 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_497 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_497 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_497 & _T_2 & ~_T_481) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_481 & (io_in_d_valid & _T_497 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_497 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_497 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_497 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_497 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_525 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_525 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_525 & _T_2 & ~_T_481) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_481 & (io_in_d_valid & _T_525 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_525 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_525 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_525 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_525 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_554 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_554 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_554 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_554 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_554 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_571 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_571 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_571 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_571 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_571 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_589 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_589 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_589 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_589 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_589 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~reset & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~reset & ~_T_628) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_628 & (_T_619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~reset & ~_T_632) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_632 & (_T_619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~reset & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & (_T_619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_643 & _T_2 & ~_T_644) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_644 & (_T_643 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_643 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_643 & _T_2 & ~_T_652) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_652 & (_T_643 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_643 & _T_2 & ~_T_656) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_656 & (_T_643 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_643 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_643 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_673 & ~reset & ~_T_677) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_673 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_696) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_696 & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & same_cycle_resp & _T_2 & ~_T_702) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_702 & (_T_693 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & same_cycle_resp & _T_2 & ~_T_706) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_706 & (_T_693 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & ~same_cycle_resp & _T_2 & ~_T_714) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_714 & (_T_693 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & ~same_cycle_resp & _T_2 & ~_T_718) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_718 & (_T_693 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_728 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_739) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_739 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_759 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_772 & _T_2 & ~_T_773[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_773[0] & (_T_772 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_779 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_772 & _T_2 & ~_T_783) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_783 & (_T_772 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_729 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_803) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:67:36)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_803 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[9:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[9:0];
  _RAND_10 = {17{`RANDOM}};
  inflight = _RAND_10[513:0];
  _RAND_11 = {65{`RANDOM}};
  inflight_opcodes = _RAND_11[2055:0];
  _RAND_12 = {65{`RANDOM}};
  inflight_sizes = _RAND_12[2055:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {17{`RANDOM}};
  inflight_1 = _RAND_16[513:0];
  _RAND_17 = {65{`RANDOM}};
  inflight_sizes_1 = _RAND_17[2055:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLSlave(
  input         clock,
  input         reset,
  input         io_req_ready,
  output        io_req_valid,
  output [31:0] io_req_bits_paddr,
  output [63:0] io_req_bits_wdata,
  output [7:0]  io_req_bits_wmask,
  output        io_rsp_ready,
  input         io_rsp_valid,
  input  [63:0] io_rsp_bits_rdata,
  output        io_a_ready,
  input         io_a_valid,
  input  [2:0]  io_a_bits_opcode,
  input  [1:0]  io_a_bits_size,
  input  [9:0]  io_a_bits_source,
  input  [31:0] io_a_bits_address,
  input  [7:0]  io_a_bits_mask,
  input  [63:0] io_a_bits_data,
  input         io_d_ready,
  output        io_d_valid,
  output [2:0]  io_d_bits_opcode,
  output [1:0]  io_d_bits_size,
  output [9:0]  io_d_bits_source,
  output [63:0] io_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] reqInfo_paddr; // @[Chiplink.scala 71:22]
  reg [63:0] reqInfo_wdata; // @[Chiplink.scala 71:22]
  reg [7:0] reqInfo_wmask; // @[Chiplink.scala 71:22]
  reg [63:0] rspInfo_rdata; // @[Chiplink.scala 72:22]
  reg [1:0] tlaInfo_size; // @[Chiplink.scala 73:22]
  reg [9:0] tlaInfo_source; // @[Chiplink.scala 73:22]
  reg  reqValid; // @[Chiplink.scala 75:27]
  reg  rspReady; // @[Chiplink.scala 76:27]
  reg  tlAReady; // @[Chiplink.scala 77:28]
  reg  tlDValid; // @[Chiplink.scala 78:27]
  reg  isRead; // @[Chiplink.scala 80:22]
  wire  _T = io_a_ready & io_a_valid; // @[Decoupled.scala 52:35]
  wire  _T_3 = io_a_bits_opcode == 3'h0 | io_a_bits_opcode == 3'h1; // @[Chiplink.scala 92:40]
  wire  _T_4 = io_a_bits_opcode == 3'h4; // @[Chiplink.scala 96:37]
  wire  _GEN_2 = io_a_bits_opcode == 3'h4 | isRead; // @[Chiplink.scala 96:47 99:16 80:22]
  wire  _T_9 = io_req_ready & io_req_valid; // @[Decoupled.scala 52:35]
  wire  _T_10 = io_rsp_ready & io_rsp_valid; // @[Decoupled.scala 52:35]
  wire  _T_11 = io_d_ready & io_d_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_18 = _T_11 | tlAReady; // @[Chiplink.scala 114:30 115:16 77:28]
  wire  _GEN_19 = _T_11 ? 1'h0 : tlDValid; // @[Chiplink.scala 114:30 116:16 78:27]
  wire  _GEN_20 = _T_10 ? 1'h0 : rspReady; // @[Chiplink.scala 111:32 112:16 76:27]
  wire  _GEN_21 = _T_10 | _GEN_19; // @[Chiplink.scala 111:32 113:16]
  wire  _GEN_22 = _T_10 ? tlAReady : _GEN_18; // @[Chiplink.scala 111:32 77:28]
  wire  _GEN_23 = _T_9 ? 1'h0 : reqValid; // @[Chiplink.scala 108:32 109:16 75:27]
  wire  _GEN_24 = _T_9 | _GEN_20; // @[Chiplink.scala 108:32 110:16]
  wire  _GEN_26 = _T_9 ? tlAReady : _GEN_22; // @[Chiplink.scala 108:32 77:28]
  wire  _GEN_27 = _T | _GEN_23; // @[Chiplink.scala 105:22 106:16]
  wire  _GEN_28 = _T ? 1'h0 : _GEN_26; // @[Chiplink.scala 105:22 107:18]
  assign io_req_valid = reqValid; // @[Chiplink.scala 82:18]
  assign io_req_bits_paddr = reqInfo_paddr; // @[Chiplink.scala 83:18]
  assign io_req_bits_wdata = reqInfo_wdata; // @[Chiplink.scala 83:18]
  assign io_req_bits_wmask = reqInfo_wmask; // @[Chiplink.scala 83:18]
  assign io_rsp_ready = rspReady; // @[Chiplink.scala 84:18]
  assign io_a_ready = tlAReady; // @[Chiplink.scala 85:16]
  assign io_d_valid = tlDValid; // @[Chiplink.scala 86:16]
  assign io_d_bits_opcode = isRead ? 3'h1 : 3'h0; // @[Chiplink.scala 124:18 125:17 127:17]
  assign io_d_bits_size = tlaInfo_size; // @[Chiplink.scala 124:18 125:17 127:17]
  assign io_d_bits_source = tlaInfo_source; // @[Chiplink.scala 124:18 125:17 127:17]
  assign io_d_bits_data = isRead ? rspInfo_rdata : 64'h0; // @[Chiplink.scala 124:18 125:17 127:17]
  always @(posedge clock) begin
    if (_T) begin // @[Chiplink.scala 89:23]
      reqInfo_paddr <= io_a_bits_address; // @[Chiplink.scala 91:21]
    end
    if (_T) begin // @[Chiplink.scala 89:23]
      if (io_a_bits_opcode == 3'h0 | io_a_bits_opcode == 3'h1) begin // @[Chiplink.scala 92:72]
        reqInfo_wdata <= io_a_bits_data; // @[Chiplink.scala 93:23]
      end else if (io_a_bits_opcode == 3'h4) begin // @[Chiplink.scala 96:47]
        reqInfo_wdata <= 64'h0; // @[Chiplink.scala 97:23]
      end
    end
    if (_T) begin // @[Chiplink.scala 89:23]
      if (io_a_bits_opcode == 3'h0 | io_a_bits_opcode == 3'h1) begin // @[Chiplink.scala 92:72]
        reqInfo_wmask <= io_a_bits_mask; // @[Chiplink.scala 94:23]
      end else if (io_a_bits_opcode == 3'h4) begin // @[Chiplink.scala 96:47]
        reqInfo_wmask <= 8'h0; // @[Chiplink.scala 98:23]
      end
    end
    if (_T_10) begin // @[Chiplink.scala 120:25]
      rspInfo_rdata <= io_rsp_bits_rdata; // @[Chiplink.scala 121:15]
    end
    if (_T) begin // @[Chiplink.scala 89:23]
      tlaInfo_size <= io_a_bits_size; // @[Chiplink.scala 90:15]
    end
    if (_T) begin // @[Chiplink.scala 89:23]
      tlaInfo_source <= io_a_bits_source; // @[Chiplink.scala 90:15]
    end
    if (reset) begin // @[Chiplink.scala 75:27]
      reqValid <= 1'h0; // @[Chiplink.scala 75:27]
    end else begin
      reqValid <= _GEN_27;
    end
    if (reset) begin // @[Chiplink.scala 76:27]
      rspReady <= 1'h0; // @[Chiplink.scala 76:27]
    end else if (!(_T)) begin // @[Chiplink.scala 105:22]
      rspReady <= _GEN_24;
    end
    tlAReady <= reset | _GEN_28; // @[Chiplink.scala 77:{28,28}]
    if (reset) begin // @[Chiplink.scala 78:27]
      tlDValid <= 1'h0; // @[Chiplink.scala 78:27]
    end else if (!(_T)) begin // @[Chiplink.scala 105:22]
      if (!(_T_9)) begin // @[Chiplink.scala 108:32]
        tlDValid <= _GEN_21;
      end
    end
    if (_T) begin // @[Chiplink.scala 89:23]
      if (io_a_bits_opcode == 3'h0 | io_a_bits_opcode == 3'h1) begin // @[Chiplink.scala 92:72]
        isRead <= 1'h0; // @[Chiplink.scala 95:16]
      end else begin
        isRead <= _GEN_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T & ~_T_3 & ~_T_4 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: Assert Failed! Unsupport Operation!\n    at Chiplink.scala:101 assert( false.B, \"Assert Failed! Unsupport Operation!\" )\n"
            ); // @[Chiplink.scala 101:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (_T & ~_T_3 & ~_T_4 & ~reset)) begin
          $fatal; // @[Chiplink.scala 101:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reqInfo_paddr = _RAND_0[31:0];
  _RAND_1 = {2{`RANDOM}};
  reqInfo_wdata = _RAND_1[63:0];
  _RAND_2 = {1{`RANDOM}};
  reqInfo_wmask = _RAND_2[7:0];
  _RAND_3 = {2{`RANDOM}};
  rspInfo_rdata = _RAND_3[63:0];
  _RAND_4 = {1{`RANDOM}};
  tlaInfo_size = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  tlaInfo_source = _RAND_5[9:0];
  _RAND_6 = {1{`RANDOM}};
  reqValid = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  rspReady = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  tlAReady = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  tlDValid = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  isRead = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module HexSpiMaster(
  input         clock,
  input         reset,
  output        io_hspi_clk,
  input         io_hspi_rx_enable,
  input  [15:0] io_hspi_rx_data,
  output        io_hspi_tx_enable,
  output [15:0] io_hspi_tx_data,
  output        io_hspi_oen,
  output        io_req_ready,
  input         io_req_valid,
  input  [31:0] io_req_bits_paddr,
  input  [63:0] io_req_bits_wdata,
  input  [7:0]  io_req_bits_wmask,
  input         io_rsp_ready,
  output        io_rsp_valid,
  output [63:0] io_rsp_bits_rdata
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [127:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  reg [3:0] txCounter; // @[Chiplink.scala 147:30]
  reg [2:0] rxCounter; // @[Chiplink.scala 148:30]
  reg  isTxRxn; // @[Chiplink.scala 149:28]
  reg [111:0] reqInfo; // @[Chiplink.scala 151:24]
  reg [63:0] rspInfo; // @[Chiplink.scala 152:24]
  reg  reqReady; // @[Chiplink.scala 154:29]
  reg  rspValid; // @[Chiplink.scala 155:29]
  wire  _io_hspi_oen_T = ~isTxRxn; // @[Chiplink.scala 157:22]
  wire  _T = io_req_ready & io_req_valid; // @[Decoupled.scala 52:35]
  wire  _T_2 = ~reset; // @[Chiplink.scala 166:15]
  wire [111:0] updateInfo = {io_req_bits_paddr,io_req_bits_wdata,io_req_bits_wmask,8'h0}; // @[Cat.scala 33:92]
  wire  _T_4 = txCounter < 4'h7; // @[Chiplink.scala 174:30]
  wire [3:0] _txCounter_T_1 = txCounter + 4'h1; // @[Chiplink.scala 176:32]
  wire [95:0] updateInfo_1 = reqInfo[111:16]; // @[Chiplink.scala 177:34]
  wire  _T_8 = txCounter == 4'h7; // @[Chiplink.scala 183:30]
  wire  _GEN_0 = txCounter == 4'h7 ? 1'h0 : isTxRxn; // @[Chiplink.scala 183:41 185:19 149:28]
  wire [15:0] _GEN_5 = txCounter < 4'h7 ? updateInfo_1[15:0] : 16'h0; // @[Chiplink.scala 174:38 180:27]
  wire  _GEN_7 = txCounter < 4'h7 ? isTxRxn : _GEN_0; // @[Chiplink.scala 149:28 174:38]
  wire  _GEN_8 = _T ? 1'h0 : reqReady; // @[Chiplink.scala 165:27 168:18 154:29]
  wire  _GEN_13 = _T ? isTxRxn : _GEN_7; // @[Chiplink.scala 165:27 149:28]
  wire  _T_15 = ~_io_hspi_oen_T; // @[Chiplink.scala 198:15]
  wire [2:0] _rxCounter_T_1 = rxCounter + 3'h1; // @[Chiplink.scala 200:32]
  wire [79:0] _rspInfo_T = {io_hspi_rx_data,rspInfo}; // @[Cat.scala 33:92]
  wire  _T_20 = rxCounter == 3'h4; // @[Chiplink.scala 202:30]
  wire  _T_25 = io_rsp_ready & io_rsp_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_14 = _T_25 ? 1'h0 : rspValid; // @[Chiplink.scala 207:34 208:18 155:29]
  wire  _GEN_15 = _T_25 | _GEN_8; // @[Chiplink.scala 207:34 209:18]
  wire  _GEN_16 = rxCounter == 3'h4 | _GEN_13; // @[Chiplink.scala 202:40 204:17]
  wire  _GEN_17 = rxCounter == 3'h4 | _GEN_14; // @[Chiplink.scala 202:40 205:18]
  wire  _GEN_19 = rxCounter == 3'h4 ? _GEN_8 : _GEN_15; // @[Chiplink.scala 202:40]
  wire  _GEN_22 = io_hspi_rx_enable ? _GEN_13 : _GEN_16; // @[Chiplink.scala 197:33]
  wire  _GEN_24 = io_hspi_rx_enable ? _GEN_8 : _GEN_19; // @[Chiplink.scala 197:33]
  wire  _GEN_26 = ~_T; // @[Chiplink.scala 175:15]
  wire  _GEN_40 = io_hspi_rx_enable & _T_2; // @[Chiplink.scala 198:15]
  assign io_hspi_clk = clock; // @[Chiplink.scala 145:34]
  assign io_hspi_tx_enable = _T | _T_4; // @[Chiplink.scala 165:27 173:27]
  assign io_hspi_tx_data = _T ? updateInfo[15:0] : _GEN_5; // @[Chiplink.scala 165:27 172:25]
  assign io_hspi_oen = ~isTxRxn; // @[Chiplink.scala 157:22]
  assign io_req_ready = reqReady; // @[Chiplink.scala 159:20]
  assign io_rsp_valid = rspValid; // @[Chiplink.scala 160:20]
  assign io_rsp_bits_rdata = rspInfo; // @[Chiplink.scala 161:26]
  always @(posedge clock) begin
    if (reset) begin // @[Chiplink.scala 147:30]
      txCounter <= 4'hf; // @[Chiplink.scala 147:30]
    end else if (_T) begin // @[Chiplink.scala 165:27]
      txCounter <= 4'h1; // @[Chiplink.scala 170:19]
    end else if (txCounter < 4'h7) begin // @[Chiplink.scala 174:38]
      txCounter <= _txCounter_T_1; // @[Chiplink.scala 176:19]
    end else if (txCounter == 4'h7) begin // @[Chiplink.scala 183:41]
      txCounter <= 4'hf; // @[Chiplink.scala 187:21]
    end
    if (reset) begin // @[Chiplink.scala 148:30]
      rxCounter <= 3'h0; // @[Chiplink.scala 148:30]
    end else if (io_hspi_rx_enable) begin // @[Chiplink.scala 197:33]
      rxCounter <= _rxCounter_T_1; // @[Chiplink.scala 200:19]
    end else if (rxCounter == 3'h4) begin // @[Chiplink.scala 202:40]
      rxCounter <= 3'h0; // @[Chiplink.scala 206:19]
    end
    isTxRxn <= reset | _GEN_22; // @[Chiplink.scala 149:{28,28}]
    if (_T) begin // @[Chiplink.scala 165:27]
      reqInfo <= updateInfo; // @[Chiplink.scala 169:17]
    end else if (txCounter < 4'h7) begin // @[Chiplink.scala 174:38]
      reqInfo <= {{16'd0}, updateInfo_1}; // @[Chiplink.scala 178:17]
    end
    if (io_hspi_rx_enable) begin // @[Chiplink.scala 197:33]
      rspInfo <= _rspInfo_T[79:16]; // @[Chiplink.scala 201:17]
    end
    reqReady <= reset | _GEN_24; // @[Chiplink.scala 154:{29,29}]
    if (reset) begin // @[Chiplink.scala 155:29]
      rspValid <= 1'h0; // @[Chiplink.scala 155:29]
    end else if (!(io_hspi_rx_enable)) begin // @[Chiplink.scala 197:33]
      rspValid <= _GEN_17;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T & ~reset & _io_hspi_oen_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Chiplink.scala:166 assert( isTxRxn )\n"); // @[Chiplink.scala 166:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~isTxRxn & (_T & ~reset)) begin
          $fatal; // @[Chiplink.scala 166:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T & _T_4 & _T_2 & _io_hspi_oen_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Chiplink.scala:175 assert( isTxRxn )\n"); // @[Chiplink.scala 175:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~isTxRxn & (~_T & _T_4 & _T_2)) begin
          $fatal; // @[Chiplink.scala 175:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_26 & ~_T_4 & _T_8 & _T_2 & _io_hspi_oen_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Chiplink.scala:184 assert( isTxRxn )\n"); // @[Chiplink.scala 184:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~isTxRxn & (_GEN_26 & ~_T_4 & _T_8 & _T_2)) begin
          $fatal; // @[Chiplink.scala 184:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_hspi_rx_enable & _T_2 & ~_io_hspi_oen_T) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Chiplink.scala:198 assert( ~isTxRxn )\n"); // @[Chiplink.scala 198:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_io_hspi_oen_T & (io_hspi_rx_enable & _T_2)) begin
          $fatal; // @[Chiplink.scala 198:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_40 & ~(rxCounter < 3'h4)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Chiplink.scala:199 assert( rxCounter < 4.U )\n"); // @[Chiplink.scala 199:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(rxCounter < 3'h4) & (io_hspi_rx_enable & _T_2)) begin
          $fatal; // @[Chiplink.scala 199:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~io_hspi_rx_enable & _T_20 & _T_2 & _T_15) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Chiplink.scala:203 assert( ~isTxRxn )\n"); // @[Chiplink.scala 203:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_io_hspi_oen_T & (~io_hspi_rx_enable & _T_20 & _T_2)) begin
          $fatal; // @[Chiplink.scala 203:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  txCounter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  rxCounter = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  isTxRxn = _RAND_2[0:0];
  _RAND_3 = {4{`RANDOM}};
  reqInfo = _RAND_3[111:0];
  _RAND_4 = {2{`RANDOM}};
  rspInfo = _RAND_4[63:0];
  _RAND_5 = {1{`RANDOM}};
  reqReady = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  rspValid = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ChipLinkMaster(
  input         clock,
  input         reset,
  output        auto_chip_link_master_in_a_ready,
  input         auto_chip_link_master_in_a_valid,
  input  [2:0]  auto_chip_link_master_in_a_bits_opcode,
  input  [2:0]  auto_chip_link_master_in_a_bits_param,
  input  [1:0]  auto_chip_link_master_in_a_bits_size,
  input  [9:0]  auto_chip_link_master_in_a_bits_source,
  input  [31:0] auto_chip_link_master_in_a_bits_address,
  input  [7:0]  auto_chip_link_master_in_a_bits_mask,
  input  [63:0] auto_chip_link_master_in_a_bits_data,
  input         auto_chip_link_master_in_a_bits_corrupt,
  input         auto_chip_link_master_in_d_ready,
  output        auto_chip_link_master_in_d_valid,
  output [2:0]  auto_chip_link_master_in_d_bits_opcode,
  output [1:0]  auto_chip_link_master_in_d_bits_size,
  output [9:0]  auto_chip_link_master_in_d_bits_source,
  output [63:0] auto_chip_link_master_in_d_bits_data,
  output        io_hspi_clk,
  input         io_hspi_rx_enable,
  input  [15:0] io_hspi_rx_data,
  output        io_hspi_tx_enable,
  output [15:0] io_hspi_tx_data,
  output        io_hspi_oen
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [9:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [9:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  tlSlave_clock; // @[Chiplink.scala 231:25]
  wire  tlSlave_reset; // @[Chiplink.scala 231:25]
  wire  tlSlave_io_req_ready; // @[Chiplink.scala 231:25]
  wire  tlSlave_io_req_valid; // @[Chiplink.scala 231:25]
  wire [31:0] tlSlave_io_req_bits_paddr; // @[Chiplink.scala 231:25]
  wire [63:0] tlSlave_io_req_bits_wdata; // @[Chiplink.scala 231:25]
  wire [7:0] tlSlave_io_req_bits_wmask; // @[Chiplink.scala 231:25]
  wire  tlSlave_io_rsp_ready; // @[Chiplink.scala 231:25]
  wire  tlSlave_io_rsp_valid; // @[Chiplink.scala 231:25]
  wire [63:0] tlSlave_io_rsp_bits_rdata; // @[Chiplink.scala 231:25]
  wire  tlSlave_io_a_ready; // @[Chiplink.scala 231:25]
  wire  tlSlave_io_a_valid; // @[Chiplink.scala 231:25]
  wire [2:0] tlSlave_io_a_bits_opcode; // @[Chiplink.scala 231:25]
  wire [1:0] tlSlave_io_a_bits_size; // @[Chiplink.scala 231:25]
  wire [9:0] tlSlave_io_a_bits_source; // @[Chiplink.scala 231:25]
  wire [31:0] tlSlave_io_a_bits_address; // @[Chiplink.scala 231:25]
  wire [7:0] tlSlave_io_a_bits_mask; // @[Chiplink.scala 231:25]
  wire [63:0] tlSlave_io_a_bits_data; // @[Chiplink.scala 231:25]
  wire  tlSlave_io_d_ready; // @[Chiplink.scala 231:25]
  wire  tlSlave_io_d_valid; // @[Chiplink.scala 231:25]
  wire [2:0] tlSlave_io_d_bits_opcode; // @[Chiplink.scala 231:25]
  wire [1:0] tlSlave_io_d_bits_size; // @[Chiplink.scala 231:25]
  wire [9:0] tlSlave_io_d_bits_source; // @[Chiplink.scala 231:25]
  wire [63:0] tlSlave_io_d_bits_data; // @[Chiplink.scala 231:25]
  wire  hspiMst_clock; // @[Chiplink.scala 232:25]
  wire  hspiMst_reset; // @[Chiplink.scala 232:25]
  wire  hspiMst_io_hspi_clk; // @[Chiplink.scala 232:25]
  wire  hspiMst_io_hspi_rx_enable; // @[Chiplink.scala 232:25]
  wire [15:0] hspiMst_io_hspi_rx_data; // @[Chiplink.scala 232:25]
  wire  hspiMst_io_hspi_tx_enable; // @[Chiplink.scala 232:25]
  wire [15:0] hspiMst_io_hspi_tx_data; // @[Chiplink.scala 232:25]
  wire  hspiMst_io_hspi_oen; // @[Chiplink.scala 232:25]
  wire  hspiMst_io_req_ready; // @[Chiplink.scala 232:25]
  wire  hspiMst_io_req_valid; // @[Chiplink.scala 232:25]
  wire [31:0] hspiMst_io_req_bits_paddr; // @[Chiplink.scala 232:25]
  wire [63:0] hspiMst_io_req_bits_wdata; // @[Chiplink.scala 232:25]
  wire [7:0] hspiMst_io_req_bits_wmask; // @[Chiplink.scala 232:25]
  wire  hspiMst_io_rsp_ready; // @[Chiplink.scala 232:25]
  wire  hspiMst_io_rsp_valid; // @[Chiplink.scala 232:25]
  wire [63:0] hspiMst_io_rsp_bits_rdata; // @[Chiplink.scala 232:25]
  TLMonitor_1 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  TLSlave tlSlave ( // @[Chiplink.scala 231:25]
    .clock(tlSlave_clock),
    .reset(tlSlave_reset),
    .io_req_ready(tlSlave_io_req_ready),
    .io_req_valid(tlSlave_io_req_valid),
    .io_req_bits_paddr(tlSlave_io_req_bits_paddr),
    .io_req_bits_wdata(tlSlave_io_req_bits_wdata),
    .io_req_bits_wmask(tlSlave_io_req_bits_wmask),
    .io_rsp_ready(tlSlave_io_rsp_ready),
    .io_rsp_valid(tlSlave_io_rsp_valid),
    .io_rsp_bits_rdata(tlSlave_io_rsp_bits_rdata),
    .io_a_ready(tlSlave_io_a_ready),
    .io_a_valid(tlSlave_io_a_valid),
    .io_a_bits_opcode(tlSlave_io_a_bits_opcode),
    .io_a_bits_size(tlSlave_io_a_bits_size),
    .io_a_bits_source(tlSlave_io_a_bits_source),
    .io_a_bits_address(tlSlave_io_a_bits_address),
    .io_a_bits_mask(tlSlave_io_a_bits_mask),
    .io_a_bits_data(tlSlave_io_a_bits_data),
    .io_d_ready(tlSlave_io_d_ready),
    .io_d_valid(tlSlave_io_d_valid),
    .io_d_bits_opcode(tlSlave_io_d_bits_opcode),
    .io_d_bits_size(tlSlave_io_d_bits_size),
    .io_d_bits_source(tlSlave_io_d_bits_source),
    .io_d_bits_data(tlSlave_io_d_bits_data)
  );
  HexSpiMaster hspiMst ( // @[Chiplink.scala 232:25]
    .clock(hspiMst_clock),
    .reset(hspiMst_reset),
    .io_hspi_clk(hspiMst_io_hspi_clk),
    .io_hspi_rx_enable(hspiMst_io_hspi_rx_enable),
    .io_hspi_rx_data(hspiMst_io_hspi_rx_data),
    .io_hspi_tx_enable(hspiMst_io_hspi_tx_enable),
    .io_hspi_tx_data(hspiMst_io_hspi_tx_data),
    .io_hspi_oen(hspiMst_io_hspi_oen),
    .io_req_ready(hspiMst_io_req_ready),
    .io_req_valid(hspiMst_io_req_valid),
    .io_req_bits_paddr(hspiMst_io_req_bits_paddr),
    .io_req_bits_wdata(hspiMst_io_req_bits_wdata),
    .io_req_bits_wmask(hspiMst_io_req_bits_wmask),
    .io_rsp_ready(hspiMst_io_rsp_ready),
    .io_rsp_valid(hspiMst_io_rsp_valid),
    .io_rsp_bits_rdata(hspiMst_io_rsp_bits_rdata)
  );
  assign auto_chip_link_master_in_a_ready = tlSlave_io_a_ready; // @[Nodes.scala 1210:84 Chiplink.scala 236:22]
  assign auto_chip_link_master_in_d_valid = tlSlave_io_d_valid; // @[Nodes.scala 1210:84 Chiplink.scala 238:22]
  assign auto_chip_link_master_in_d_bits_opcode = tlSlave_io_d_bits_opcode; // @[Nodes.scala 1210:84 Chiplink.scala 239:21]
  assign auto_chip_link_master_in_d_bits_size = tlSlave_io_d_bits_size; // @[Nodes.scala 1210:84 Chiplink.scala 239:21]
  assign auto_chip_link_master_in_d_bits_source = tlSlave_io_d_bits_source; // @[Nodes.scala 1210:84 Chiplink.scala 239:21]
  assign auto_chip_link_master_in_d_bits_data = tlSlave_io_d_bits_data; // @[Nodes.scala 1210:84 Chiplink.scala 239:21]
  assign io_hspi_clk = hspiMst_io_hspi_clk; // @[Chiplink.scala 242:17]
  assign io_hspi_tx_enable = hspiMst_io_hspi_tx_enable; // @[Chiplink.scala 245:18]
  assign io_hspi_tx_data = hspiMst_io_hspi_tx_data; // @[Chiplink.scala 245:18]
  assign io_hspi_oen = hspiMst_io_hspi_oen; // @[Chiplink.scala 246:18]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = tlSlave_io_a_ready; // @[Nodes.scala 1210:84 Chiplink.scala 236:22]
  assign monitor_io_in_a_valid = auto_chip_link_master_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_chip_link_master_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_chip_link_master_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_chip_link_master_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_chip_link_master_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_chip_link_master_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_chip_link_master_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_chip_link_master_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_chip_link_master_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = tlSlave_io_d_valid; // @[Nodes.scala 1210:84 Chiplink.scala 238:22]
  assign monitor_io_in_d_bits_opcode = tlSlave_io_d_bits_opcode; // @[Nodes.scala 1210:84 Chiplink.scala 239:21]
  assign monitor_io_in_d_bits_size = tlSlave_io_d_bits_size; // @[Nodes.scala 1210:84 Chiplink.scala 239:21]
  assign monitor_io_in_d_bits_source = tlSlave_io_d_bits_source; // @[Nodes.scala 1210:84 Chiplink.scala 239:21]
  assign tlSlave_clock = clock;
  assign tlSlave_reset = reset;
  assign tlSlave_io_req_ready = hspiMst_io_req_ready; // @[Chiplink.scala 249:20]
  assign tlSlave_io_rsp_valid = hspiMst_io_rsp_valid; // @[Chiplink.scala 248:20]
  assign tlSlave_io_rsp_bits_rdata = hspiMst_io_rsp_bits_rdata; // @[Chiplink.scala 248:20]
  assign tlSlave_io_a_valid = auto_chip_link_master_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlave_io_a_bits_opcode = auto_chip_link_master_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlave_io_a_bits_size = auto_chip_link_master_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlave_io_a_bits_source = auto_chip_link_master_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlave_io_a_bits_address = auto_chip_link_master_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlave_io_a_bits_mask = auto_chip_link_master_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlave_io_a_bits_data = auto_chip_link_master_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlave_io_d_ready = auto_chip_link_master_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign hspiMst_clock = clock;
  assign hspiMst_reset = reset;
  assign hspiMst_io_hspi_rx_enable = io_hspi_rx_enable; // @[Chiplink.scala 244:24]
  assign hspiMst_io_hspi_rx_data = io_hspi_rx_data; // @[Chiplink.scala 244:24]
  assign hspiMst_io_req_valid = tlSlave_io_req_valid; // @[Chiplink.scala 249:20]
  assign hspiMst_io_req_bits_paddr = tlSlave_io_req_bits_paddr; // @[Chiplink.scala 249:20]
  assign hspiMst_io_req_bits_wdata = tlSlave_io_req_bits_wdata; // @[Chiplink.scala 249:20]
  assign hspiMst_io_req_bits_wmask = tlSlave_io_req_bits_wmask; // @[Chiplink.scala 249:20]
  assign hspiMst_io_rsp_ready = tlSlave_io_rsp_ready; // @[Chiplink.scala 248:20]
endmodule
module TLMonitor_2(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [4:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire [10:0] _is_aligned_mask_T_1 = 11'hf << io_in_a_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask = ~_is_aligned_mask_T_1[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_62 = {{28'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_62; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
  wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_22 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire [32:0] _T_27 = $signed(_T_7) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_28 = $signed(_T_27) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_29 = _T_22 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_31 = _source_ok_T & _T_29; // @[Monitor.scala 82:72]
  wire  _T_60 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_64 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_65 = _T_64 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_69 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_73 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_122 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_135 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_146 = io_in_a_bits_size <= 3'h4; // @[Parameters.scala 92:42]
  wire  _T_154 = _T_146 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_165 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_169 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_177 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_195 = _source_ok_T & _T_154; // @[Monitor.scala 115:71]
  wire  _T_213 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_245 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_246 = io_in_a_bits_mask & _T_245; // @[Monitor.scala 127:31]
  wire  _T_247 = _T_246 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_251 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_259 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
  wire  _T_267 = _T_259 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_269 = _source_ok_T & _T_267; // @[Monitor.scala 131:74]
  wire  _T_279 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_287 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_315 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_323 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_351 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_363 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_367 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_371 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_375 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_379 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_383 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_387 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_398 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_402 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_415 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_435 = _T_383 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_444 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_461 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_479 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_beats1_decode = is_aligned_mask[3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala 220:14]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_509 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_510 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_514 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_518 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_522 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_526 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _d_first_beats1_decode_T_1 = 11'hf << io_in_d_bits_size; // @[package.scala 234:77]
  wire [3:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  d_first_beats1_decode = _d_first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala 220:14]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [4:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_533 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_534 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_538 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_542 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_550 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_554 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_64 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_64 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _GEN_71 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_560 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_563 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_73 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_73}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_335 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_335 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [18:0] _GEN_336 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [18:0] _a_sizes_set_T_1 = _GEN_336 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire  _T_567 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [18:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_571 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_573 = ~_T_367; // @[Monitor.scala 671:74]
  wire  _T_574 = io_in_d_valid & d_first_1 & ~_T_367; // @[Monitor.scala 671:71]
  wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_367 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_573 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_573 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  same_cycle_resp = _T_560 & _source_ok_T; // @[Monitor.scala 681:88]
  wire  _T_586 = inflight | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_591 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_592 = io_in_d_bits_opcode == _GEN_32 | _T_591; // @[Monitor.scala 685:77]
  wire  _T_596 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_603 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_604 = io_in_d_bits_opcode == _GEN_48 | _T_603; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_75 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_608 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_618 = _T_571 & a_first_1 & io_in_a_valid & _source_ok_T & _T_573; // @[Monitor.scala 694:116]
  wire  _T_619 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_620 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set_wo_ready = _GEN_15[0];
  wire  d_clr_wo_ready = _GEN_21[0];
  wire  _T_627 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_636 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [15:0] _GEN_76 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_662 = io_in_d_valid & d_first_2 & _T_367; // @[Monitor.scala 779:71]
  wire [1:0] _GEN_66 = io_in_d_valid & d_first_2 & _T_367 ? 2'h1 : 2'h0; // @[Monitor.scala 779:89 780:22]
  wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_367 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_676 = io_in_d_bits_size == 3'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_680 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  d_clr_wo_ready_1 = _GEN_66[0];
  wire [3:0] d_sizes_clr_1 = _GEN_69[3:0];
  wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= a_first_beats1;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= a_first_beats1;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= d_first_beats1;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_60) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_60 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_65) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_65 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_60) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_60 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_122) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_122 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_65) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_65 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_154) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_154 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_247) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_247 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_279) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_279 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_315) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_315 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_351) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_351 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_363) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_363 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_398) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_398 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_398) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_398 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_510) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_510 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_514) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_514 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_518) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_518 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_522) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_522 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_526) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_526 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_534) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_534 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_538 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_542) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_542 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_550 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_554) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_554 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_563 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_563 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & _T_2 & ~_T_586) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_586 & (_T_574 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & same_cycle_resp & _T_2 & ~_T_592) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_592 & (_T_574 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & same_cycle_resp & _T_2 & ~_T_596) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & (_T_574 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & ~same_cycle_resp & _T_2 & ~_T_604) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_604 & (_T_574 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & ~same_cycle_resp & _T_2 & ~_T_608) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_608 & (_T_574 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_618 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_618 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_662 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (_T_662 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_676 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_662 & _T_2 & ~_T_680) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:76:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_680 & (_T_662 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_619 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~d_clr_wo_ready_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  sink = _RAND_10[4:0];
  _RAND_11 = {1{`RANDOM}};
  denied = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  inflight = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight_opcodes = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_sizes = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  watchdog = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_3(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_b_ready,
  input         io_in_b_valid,
  input  [1:0]  io_in_b_bits_param,
  input  [31:0] io_in_b_bits_address,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [2:0]  io_in_c_bits_size,
  input         io_in_c_bits_source,
  input  [31:0] io_in_c_bits_address,
  input         io_in_c_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [4:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt,
  input         io_in_e_valid,
  input  [4:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire [10:0] _is_aligned_mask_T_1 = 11'hf << io_in_a_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask = ~_is_aligned_mask_T_1[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_74 = {{28'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_74; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
  wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_22 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire [32:0] _T_27 = $signed(_T_7) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_28 = $signed(_T_27) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_29 = _T_22 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_31 = _source_ok_T & _T_29; // @[Monitor.scala 82:72]
  wire  _T_61 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_65 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_66 = _T_65 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_70 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_74 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_124 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_137 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_148 = io_in_a_bits_size <= 3'h4; // @[Parameters.scala 92:42]
  wire  _T_156 = _T_148 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_167 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_171 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_179 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_197 = _source_ok_T & _T_156; // @[Monitor.scala 115:71]
  wire  _T_215 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_247 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_248 = io_in_a_bits_mask & _T_247; // @[Monitor.scala 127:31]
  wire  _T_249 = _T_248 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_253 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_261 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
  wire  _T_269 = _T_261 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_271 = _source_ok_T & _T_269; // @[Monitor.scala 131:74]
  wire  _T_281 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_289 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_317 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_325 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_353 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_365 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_369 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_373 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_377 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_381 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_385 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_389 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_400 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_404 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_417 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_437 = _T_385 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_446 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_463 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_481 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire [32:0] _T_505 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 137:49]
  wire [32:0] _address_ok_T_3 = $signed(_T_505) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _is_aligned_T_1 = io_in_b_bits_address & 32'hf; // @[Edges.scala 20:16]
  wire  is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala 20:24]
  wire  _T_539 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_576 = io_in_b_bits_param == 2'h0; // @[Monitor.scala 182:31]
  wire  _source_ok_T_2 = ~io_in_c_bits_source; // @[Parameters.scala 46:9]
  wire [10:0] _is_aligned_mask_T_7 = 11'hf << io_in_c_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_76 = {{28'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_76; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala 20:24]
  wire [32:0] _address_ok_T_6 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 137:49]
  wire [32:0] _address_ok_T_8 = $signed(_address_ok_T_6) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_760 = ~_source_ok_T_2; // @[Monitor.scala 63:7]
  wire  _T_770 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_777 = io_in_c_bits_size >= 3'h3; // @[Monitor.scala 245:30]
  wire  _T_784 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_788 = ~io_in_c_bits_corrupt; // @[Monitor.scala 248:18]
  wire  _T_792 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_810 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_817 = 3'h4 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_824 = _T_817 & _address_ok_T_9; // @[Parameters.scala 670:56]
  wire  _T_826 = _source_ok_T_2 & _T_824; // @[Monitor.scala 260:78]
  wire  _T_864 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_914 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_924 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_932 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_946 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_beats1_decode = is_aligned_mask[3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala 220:14]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_968 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_969 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_973 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_977 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_981 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_985 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _d_first_beats1_decode_T_1 = 11'hf << io_in_d_bits_size; // @[package.scala 234:77]
  wire [3:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  d_first_beats1_decode = _d_first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala 220:14]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [4:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_992 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_993 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_997 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1001 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1009 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1013 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  wire  _b_first_T = io_in_b_ready & io_in_b_valid; // @[Decoupled.scala 52:35]
  reg  b_first_counter; // @[Edges.scala 228:27]
  wire  b_first_counter1 = b_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  b_first = ~b_first_counter; // @[Edges.scala 230:25]
  reg [1:0] param_2; // @[Monitor.scala 408:22]
  reg [31:0] address_1; // @[Monitor.scala 411:22]
  wire  _T_1020 = io_in_b_valid & ~b_first; // @[Monitor.scala 412:19]
  wire  _T_1025 = io_in_b_bits_param == param_2; // @[Monitor.scala 414:32]
  wire  _T_1037 = io_in_b_bits_address == address_1; // @[Monitor.scala 417:32]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 52:35]
  wire  c_first_beats1_decode = is_aligned_mask_2[3]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  wire  c_first_beats1 = c_first_beats1_opdata & c_first_beats1_decode; // @[Edges.scala 220:14]
  reg  c_first_counter; // @[Edges.scala 228:27]
  wire  c_first_counter1 = c_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  c_first = ~c_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [2:0] size_3; // @[Monitor.scala 514:22]
  reg  source_3; // @[Monitor.scala 515:22]
  reg [31:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_1044 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_1045 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_1049 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_1053 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_1057 = io_in_c_bits_source == source_3; // @[Monitor.scala 521:32]
  wire  _T_1061 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_80 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_80 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _GEN_87 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1067 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_27 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1070 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_89 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_89}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_492 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_492 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [18:0] _GEN_493 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [18:0] _a_sizes_set_T_1 = _GEN_493 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire  _T_1074 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
  wire [1:0] _GEN_28 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [18:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1078 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1080 = ~_T_369; // @[Monitor.scala 671:74]
  wire  _T_1081 = io_in_d_valid & d_first_1 & ~_T_369; // @[Monitor.scala 671:71]
  wire [1:0] _GEN_33 = io_in_d_valid & d_first_1 & ~_T_369 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_34 = _d_first_T & d_first_1 & _T_1080 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_35 = _d_first_T & d_first_1 & _T_1080 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  same_cycle_resp = _T_1067 & _source_ok_T; // @[Monitor.scala 681:88]
  wire  _T_1093 = inflight | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_1098 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_1099 = io_in_d_bits_opcode == _GEN_44 | _T_1098; // @[Monitor.scala 685:77]
  wire  _T_1103 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_1110 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_1111 = io_in_d_bits_opcode == _GEN_60 | _T_1110; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_91 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1115 = _GEN_91 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1125 = _T_1078 & a_first_1 & io_in_a_valid & _source_ok_T & _T_1080; // @[Monitor.scala 694:116]
  wire  _T_1126 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_1127 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set_wo_ready = _GEN_27[0];
  wire  d_clr_wo_ready = _GEN_33[0];
  wire  _T_1134 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire  a_set = _GEN_28[0];
  wire  d_clr = _GEN_34[0];
  wire [3:0] a_opcodes_set = _GEN_31[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_35[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_32[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1143 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg  inflight_1; // @[Monitor.scala 723:35]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  c_first_counter_1; // @[Edges.scala 228:27]
  wire  c_first_counter1_1 = c_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = ~c_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [15:0] _GEN_92 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_92 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1153 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_1154 = io_in_c_valid & c_first_1 & _T_1153; // @[Monitor.scala 756:37]
  wire [1:0] _c_set_wo_ready_T = 2'h1 << io_in_c_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_72 = io_in_c_valid & c_first_1 & _T_1153 ? _c_set_wo_ready_T : 2'h0; // @[Monitor.scala 756:71 757:22]
  wire  _T_1160 = _c_first_T & c_first_1 & _T_1153; // @[Monitor.scala 760:38]
  wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [3:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 4'h1; // @[Monitor.scala 763:59]
  wire [2:0] _GEN_94 = {io_in_c_bits_source, 2'h0}; // @[Monitor.scala 765:77]
  wire [3:0] _c_sizes_set_T = {{1'd0}, _GEN_94}; // @[Monitor.scala 765:77]
  wire [3:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_1153 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 760:72 763:28]
  wire [18:0] _GEN_494 = {{15'd0}, c_sizes_set_interm}; // @[Monitor.scala 765:52]
  wire [18:0] _c_sizes_set_T_1 = _GEN_494 << _c_sizes_set_T; // @[Monitor.scala 765:52]
  wire  _T_1163 = ~(inflight_1 >> io_in_c_bits_source); // @[Monitor.scala 766:17]
  wire [1:0] _GEN_73 = _c_first_T & c_first_1 & _T_1153 ? _c_set_wo_ready_T : 2'h0; // @[Monitor.scala 760:72 761:28]
  wire [18:0] _GEN_77 = _c_first_T & c_first_1 & _T_1153 ? _c_sizes_set_T_1 : 19'h0; // @[Monitor.scala 760:72 765:28]
  wire  _T_1167 = io_in_d_valid & d_first_2; // @[Monitor.scala 779:26]
  wire  _T_1169 = io_in_d_valid & d_first_2 & _T_369; // @[Monitor.scala 779:71]
  wire [1:0] _GEN_78 = io_in_d_valid & d_first_2 & _T_369 ? 2'h1 : 2'h0; // @[Monitor.scala 779:89 780:22]
  wire [1:0] _GEN_79 = _d_first_T & d_first_2 & _T_369 ? 2'h1 : 2'h0; // @[Monitor.scala 783:90 784:21]
  wire [30:0] _GEN_81 = _d_first_T & d_first_2 & _T_369 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire  same_cycle_resp_1 = _T_1154 & _source_ok_T_2; // @[Monitor.scala 790:88]
  wire  _T_1179 = inflight_1 | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_1183 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1187 = _GEN_91 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_1196 = _T_1167 & c_first_1 & io_in_c_valid & _source_ok_T_2 & _T_369; // @[Monitor.scala 799:116]
  wire  _T_1198 = _T_1126 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire  c_set_wo_ready = _GEN_72[0];
  wire  _T_1202 = |c_set_wo_ready; // @[Monitor.scala 804:28]
  wire  d_clr_wo_ready_1 = _GEN_78[0];
  wire  _T_1203 = c_set_wo_ready != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire  c_set = _GEN_73[0];
  wire  d_clr_1 = _GEN_79[0];
  wire [3:0] c_sizes_set = _GEN_77[3:0];
  wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [3:0] d_sizes_clr_1 = _GEN_81[3:0];
  wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1212 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [31:0] inflight_2; // @[Monitor.scala 823:27]
  reg  d_first_counter_3; // @[Edges.scala 228:27]
  wire  d_first_counter1_3 = d_first_counter_3 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = ~d_first_counter_3; // @[Edges.scala 230:25]
  wire  _T_1224 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_1225 = _d_first_T & d_first_3 & _T_1224; // @[Monitor.scala 829:38]
  wire [31:0] _d_set_T = 32'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [31:0] _T_1226 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_1228 = ~_T_1226[0]; // @[Monitor.scala 831:14]
  wire [31:0] d_set = _d_first_T & d_first_3 & _T_1224 ? _d_set_T : 32'h0; // @[Monitor.scala 829:72 830:13]
  wire [31:0] _e_clr_T = 32'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [31:0] _T_1235 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [31:0] _T_1236 = _T_1235 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [31:0] e_clr = io_in_e_valid ? _e_clr_T : 32'h0; // @[Monitor.scala 835:73 836:13]
  wire [31:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [31:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [31:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= a_first_beats1;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      b_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_b_first_T) begin // @[Edges.scala 234:17]
      if (b_first) begin // @[Edges.scala 235:21]
        b_first_counter <= 1'h0;
      end else begin
        b_first_counter <= b_first_counter1;
      end
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      param_2 <= io_in_b_bits_param; // @[Monitor.scala 421:15]
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      address_1 <= io_in_b_bits_address; // @[Monitor.scala 424:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        c_first_counter <= c_first_beats1;
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      source_3 <= io_in_c_bits_source; // @[Monitor.scala 528:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= a_first_beats1;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 1'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= (inflight_1 | c_set) & ~d_clr_1; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        c_first_counter_1 <= c_first_beats1;
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= d_first_beats1;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 32'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        d_first_counter_3 <= d_first_beats1;
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_29) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_29 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_61) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_61 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_66) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_66 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_29) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_29 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_61) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_61 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_124) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_124 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_66) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_66 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~_T_156) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_156 & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~_T_167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_167 & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & ~_T_197) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_197 & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & ~_T_167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_167 & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & ~_T_197) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_197 & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & ~_T_167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_167 & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & ~_T_271) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_271 & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & ~_T_281) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_281 & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & ~_T_271) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_271 & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & ~_T_317) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_317 & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_197) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_197 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_353) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_353 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_365) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_365 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_T_373) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_373 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_381 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_373) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_373 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_400) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_400 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_404) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_404 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_381 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_373) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_373 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_400) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_400 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_404) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_404 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_381 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_463 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_463 & _T_2 & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_d_valid & _T_463 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_463 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_463 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_463 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_463 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_381 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_address_ok_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_address_ok_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~is_aligned_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_T_539) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_539 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~_T_784) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_784 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~_T_788) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_788 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & ~_T_784) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_784 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_826) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_826 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_824) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_824 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_784) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_784 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_788) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_788 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~_T_826) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_826 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~_T_824) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_824 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~_T_784) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_784 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & ~_T_924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_924 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & ~_T_788) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_788 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_932 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_932 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_932 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_932 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_932 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_932 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_932 & ~reset & ~_T_924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_924 & (io_in_c_valid & _T_932 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & ~_T_924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_924 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & ~_T_788) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck is corrupt (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_788 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_969) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_969 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_973) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_973 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_977) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_977 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_981) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_981 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_985) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_985 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_993) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_993 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_997) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_997 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_1001) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1001 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_1009) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1009 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_1013) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1013 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1020 & ~reset & ~_T_1025) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel param changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1025 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1020 & ~reset & ~_T_1037) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1037 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1045) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1045 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1049) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1049 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1053) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1053 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1057) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel source changed within multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1057 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1061) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1061 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1070 & ~reset & ~_T_1074) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1074 & (_T_1070 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & _T_2 & ~_T_1093) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1093 & (_T_1081 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & same_cycle_resp & _T_2 & ~_T_1099) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1099 & (_T_1081 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & same_cycle_resp & _T_2 & ~_T_1103) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1103 & (_T_1081 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & ~same_cycle_resp & _T_2 & ~_T_1111) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1111 & (_T_1081 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & ~same_cycle_resp & _T_2 & ~_T_1115) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1115 & (_T_1081 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1125 & _T_2 & ~_T_1127) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1127 & (_T_1125 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1134) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1134 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1143) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1143 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1160 & ~reset & ~_T_1163) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1163 & (_T_1160 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1169 & _T_2 & ~_T_1179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1179 & (_T_1169 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1169 & same_cycle_resp_1 & _T_2 & ~_T_1183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1183 & (_T_1169 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1169 & ~same_cycle_resp_1 & _T_2 & ~_T_1187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1187 & (_T_1169 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1196 & _T_2 & ~_T_1198) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1198 & (_T_1196 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1202 & _T_2 & ~_T_1203) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' and 'D' concurrent, despite minlatency 2 (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1203 & (_T_1202 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1212) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1212 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1225 & _T_2 & ~_T_1228) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1228 & (_T_1225 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_e_valid & ~reset & ~_T_1236[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at Rift2Link.scala:77:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1236[0] & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  sink = _RAND_10[4:0];
  _RAND_11 = {1{`RANDOM}};
  denied = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  b_first_counter = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  param_2 = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  address_1 = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  c_first_counter = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  opcode_3 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  param_3 = _RAND_17[2:0];
  _RAND_18 = {1{`RANDOM}};
  size_3 = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  source_3 = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  address_2 = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  inflight = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  inflight_opcodes = _RAND_22[3:0];
  _RAND_23 = {1{`RANDOM}};
  inflight_sizes = _RAND_23[3:0];
  _RAND_24 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  watchdog = _RAND_26[31:0];
  _RAND_27 = {1{`RANDOM}};
  inflight_1 = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_28[3:0];
  _RAND_29 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  watchdog_1 = _RAND_31[31:0];
  _RAND_32 = {1{`RANDOM}};
  inflight_2 = _RAND_32[31:0];
  _RAND_33 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_33[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_4(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input         io_in_d_bits_source,
  input  [4:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [10:0] _is_aligned_mask_T_1 = 11'hf << io_in_a_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask = ~_is_aligned_mask_T_1[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_62 = {{28'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_62; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire [32:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_32 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire [32:0] _T_37 = $signed(_T_12) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_38 = $signed(_T_37) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_39 = _T_32 & _T_38; // @[Parameters.scala 670:56]
  wire  _T_70 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_74 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_75 = _T_74 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_79 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_83 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_137 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_150 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_166 = io_in_a_bits_size <= 3'h4; // @[Parameters.scala 92:42]
  wire  _T_174 = _T_166 & _T_38; // @[Parameters.scala 670:56]
  wire  _T_185 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_189 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_197 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_238 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_275 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_276 = io_in_a_bits_mask & _T_275; // @[Monitor.scala 127:31]
  wire  _T_277 = _T_276 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_281 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_294 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
  wire  _T_302 = _T_294 & _T_38; // @[Parameters.scala 670:56]
  wire  _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_355 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_363 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_396 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_408 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_412 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_416 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_420 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_424 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_428 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_432 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_443 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_447 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_460 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_480 = _T_428 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_489 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_506 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_524 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_beats1_decode = is_aligned_mask[3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala 220:14]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_554 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_555 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_559 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_563 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_567 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_571 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _d_first_beats1_decode_T_1 = 11'hf << io_in_d_bits_size; // @[package.scala 234:77]
  wire [3:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  d_first_beats1_decode = _d_first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala 220:14]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg  source_1; // @[Monitor.scala 538:22]
  reg [4:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_578 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_579 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_583 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_587 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_591 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_595 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_599 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [1:0] inflight; // @[Monitor.scala 611:27]
  reg [7:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [2:0] _GEN_64 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_64}; // @[Monitor.scala 634:69]
  wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_68 = {{8'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_68 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_73 = {{8'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_605 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_608 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_75 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_75}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_325 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_325 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [18:0] _GEN_326 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [18:0] _a_sizes_set_T_1 = _GEN_326 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [1:0] _T_610 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_612 = ~_T_610[0]; // @[Monitor.scala 658:17]
  wire [1:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [18:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_616 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_618 = ~_T_412; // @[Monitor.scala 671:74]
  wire  _T_619 = io_in_d_valid & d_first_1 & ~_T_412; // @[Monitor.scala 671:71]
  wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_412 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _GEN_327 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_opcodes_clr_T_5 = _GEN_327 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1:0] d_clr = _d_first_T & d_first_1 & _T_618 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_618 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_605 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [1:0] _T_629 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_631 = _T_629[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_636 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_32 | _T_636; // @[Monitor.scala 685:77]
  wire  _T_641 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_48 | _T_648; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_79 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_653 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_663 = _T_616 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_618; // @[Monitor.scala 694:116]
  wire  _T_664 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_665 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_672 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [7:0] a_opcodes_set = _GEN_19[7:0];
  wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [7:0] d_opcodes_clr = _GEN_23[7:0];
  wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [7:0] a_sizes_set = _GEN_20[7:0];
  wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_681 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [1:0] inflight_1; // @[Monitor.scala 723:35]
  reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_81 = {{8'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_81 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_701 = ~inflight_1[0]; // @[Monitor.scala 766:17]
  wire  _T_707 = io_in_d_valid & d_first_2 & _T_412; // @[Monitor.scala 779:71]
  wire [1:0] d_clr_wo_ready_1 = io_in_d_valid & d_first_2 & _T_412 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 779:89 780:22]
  wire [1:0] d_clr_1 = _d_first_T & d_first_2 & _T_412 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 783:90 784:21]
  wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_412 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire [1:0] _T_715 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_721 = io_in_d_bits_size == 3'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_725 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_741 = 2'h0 != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [1:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
  wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= a_first_beats1;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 2'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 8'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= a_first_beats1;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 2'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= d_first_beats1;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_39) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_39 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_75) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_75 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_39) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_39 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_137) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_137 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_75) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_75 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_238 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_238 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_238 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_238 & ~reset & ~_T_277) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_277 & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_281 & ~reset & ~_T_302) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_302 & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_281 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_281 & ~reset & ~_T_314) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_314 & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_281 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_322 & ~reset & ~_T_302) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_302 & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_322 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_322 & ~reset & ~_T_355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_355 & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_322 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_396) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_396 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_412 & _T_2 & ~_T_416) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_416 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_412 & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_412 & _T_2 & ~_T_424) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_424 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_412 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_416) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_416 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_443) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_443 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_447) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_447 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_424) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_424 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_416) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_416 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_443) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_443 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_447) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_447 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_480) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_480 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_489 & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_489 & _T_2 & ~_T_424) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_424 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_489 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_506 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_506 & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_506 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_506 & _T_2 & ~_T_480) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_480 & (io_in_d_valid & _T_506 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_506 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_506 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_524 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_524 & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_524 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_524 & _T_2 & ~_T_424) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_424 & (io_in_d_valid & _T_524 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_524 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_524 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_555) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_555 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_559) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_559 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_563) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_563 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_587 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_595 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~reset & ~_T_612) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_612 & (_T_608 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & _T_2 & ~_T_631) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_631 & (_T_619 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & same_cycle_resp & _T_2 & ~_T_637) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_637 & (_T_619 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & same_cycle_resp & _T_2 & ~_T_641) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_641 & (_T_619 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_619 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_619 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_663 & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_663 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_672) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_672 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_681) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_681 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_707 & _T_2 & ~_T_715[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_715[0] & (_T_707 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_721 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_707 & _T_2 & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (_T_707 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_664 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_741 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:78:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[4:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[7:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[1:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[7:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_5(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [4:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire [10:0] _is_aligned_mask_T_1 = 11'hf << io_in_a_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask = ~_is_aligned_mask_T_1[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_62 = {{28'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_62; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
  wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_22 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire [32:0] _T_27 = $signed(_T_7) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_28 = $signed(_T_27) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_29 = _T_22 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_31 = _source_ok_T & _T_29; // @[Monitor.scala 82:72]
  wire  _T_60 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_64 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_65 = _T_64 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_69 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_73 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_122 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_135 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_146 = io_in_a_bits_size <= 3'h4; // @[Parameters.scala 92:42]
  wire  _T_154 = _T_146 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_165 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_169 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_177 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_195 = _source_ok_T & _T_154; // @[Monitor.scala 115:71]
  wire  _T_213 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_245 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_246 = io_in_a_bits_mask & _T_245; // @[Monitor.scala 127:31]
  wire  _T_247 = _T_246 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_251 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_259 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
  wire  _T_267 = _T_259 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_269 = _source_ok_T & _T_267; // @[Monitor.scala 131:74]
  wire  _T_279 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_287 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_315 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_323 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_351 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_363 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_367 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_371 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_375 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_379 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_383 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_387 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_398 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_402 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_415 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_435 = _T_383 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_444 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_461 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_479 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_beats1_decode = is_aligned_mask[3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala 220:14]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_509 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_510 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_514 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_518 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_522 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_526 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _d_first_beats1_decode_T_1 = 11'hf << io_in_d_bits_size; // @[package.scala 234:77]
  wire [3:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  d_first_beats1_decode = _d_first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala 220:14]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [4:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_533 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_534 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_538 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_542 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_550 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_554 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_64 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_64 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _GEN_71 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_560 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_563 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_73 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_73}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_335 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_335 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [18:0] _GEN_336 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [18:0] _a_sizes_set_T_1 = _GEN_336 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire  _T_567 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [18:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_571 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_573 = ~_T_367; // @[Monitor.scala 671:74]
  wire  _T_574 = io_in_d_valid & d_first_1 & ~_T_367; // @[Monitor.scala 671:71]
  wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_367 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_573 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_573 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  same_cycle_resp = _T_560 & _source_ok_T; // @[Monitor.scala 681:88]
  wire  _T_586 = inflight | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_591 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_592 = io_in_d_bits_opcode == _GEN_32 | _T_591; // @[Monitor.scala 685:77]
  wire  _T_596 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_603 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_604 = io_in_d_bits_opcode == _GEN_48 | _T_603; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_75 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_608 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_618 = _T_571 & a_first_1 & io_in_a_valid & _source_ok_T & _T_573; // @[Monitor.scala 694:116]
  wire  _T_619 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_620 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set_wo_ready = _GEN_15[0];
  wire  d_clr_wo_ready = _GEN_21[0];
  wire  _T_627 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_636 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [15:0] _GEN_76 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_662 = io_in_d_valid & d_first_2 & _T_367; // @[Monitor.scala 779:71]
  wire [1:0] _GEN_66 = io_in_d_valid & d_first_2 & _T_367 ? 2'h1 : 2'h0; // @[Monitor.scala 779:89 780:22]
  wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_367 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_676 = io_in_d_bits_size == 3'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_680 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  d_clr_wo_ready_1 = _GEN_66[0];
  wire [3:0] d_sizes_clr_1 = _GEN_69[3:0];
  wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= a_first_beats1;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= a_first_beats1;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= d_first_beats1;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_60) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_60 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_65) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_65 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_60) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_60 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_122) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_122 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_65) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_65 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_154) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_154 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_247) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_247 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_279) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_279 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_315) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_315 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_351) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_351 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_363) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_363 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_398) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_398 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_398) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_398 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_510) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_510 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_514) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_514 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_518) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_518 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_522) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_522 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_526) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_526 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_534) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_534 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_538 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_542) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_542 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_550 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_554) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_554 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_563 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_563 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & _T_2 & ~_T_586) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_586 & (_T_574 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & same_cycle_resp & _T_2 & ~_T_592) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_592 & (_T_574 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & same_cycle_resp & _T_2 & ~_T_596) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & (_T_574 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & ~same_cycle_resp & _T_2 & ~_T_604) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_604 & (_T_574 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & ~same_cycle_resp & _T_2 & ~_T_608) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_608 & (_T_574 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_618 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_618 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_662 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (_T_662 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_676 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_662 & _T_2 & ~_T_680) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:79:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_680 & (_T_662 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_619 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~d_clr_wo_ready_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  sink = _RAND_10[4:0];
  _RAND_11 = {1{`RANDOM}};
  denied = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  inflight = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight_opcodes = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_sizes = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  watchdog = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLXbar(
  input         clock,
  input         reset,
  input         auto_in_3_a_valid,
  input  [2:0]  auto_in_3_a_bits_opcode,
  input  [2:0]  auto_in_3_a_bits_param,
  input  [2:0]  auto_in_3_a_bits_size,
  input         auto_in_3_a_bits_source,
  input  [31:0] auto_in_3_a_bits_address,
  input  [7:0]  auto_in_3_a_bits_mask,
  input  [63:0] auto_in_3_a_bits_data,
  input         auto_in_3_a_bits_corrupt,
  input         auto_in_3_d_ready,
  output        auto_in_2_a_ready,
  input         auto_in_2_a_valid,
  input  [2:0]  auto_in_2_a_bits_opcode,
  input  [2:0]  auto_in_2_a_bits_param,
  input  [2:0]  auto_in_2_a_bits_size,
  input         auto_in_2_a_bits_source,
  input  [31:0] auto_in_2_a_bits_address,
  input  [7:0]  auto_in_2_a_bits_mask,
  input  [63:0] auto_in_2_a_bits_data,
  input         auto_in_2_a_bits_corrupt,
  input         auto_in_2_d_ready,
  output        auto_in_2_d_valid,
  output [2:0]  auto_in_2_d_bits_opcode,
  output [1:0]  auto_in_2_d_bits_param,
  output [2:0]  auto_in_2_d_bits_size,
  output        auto_in_2_d_bits_source,
  output [4:0]  auto_in_2_d_bits_sink,
  output        auto_in_2_d_bits_denied,
  output [63:0] auto_in_2_d_bits_data,
  output        auto_in_2_d_bits_corrupt,
  output        auto_in_1_a_ready,
  input         auto_in_1_a_valid,
  input  [2:0]  auto_in_1_a_bits_opcode,
  input  [2:0]  auto_in_1_a_bits_param,
  input  [2:0]  auto_in_1_a_bits_size,
  input         auto_in_1_a_bits_source,
  input  [31:0] auto_in_1_a_bits_address,
  input  [7:0]  auto_in_1_a_bits_mask,
  input  [63:0] auto_in_1_a_bits_data,
  input         auto_in_1_a_bits_corrupt,
  input         auto_in_1_b_ready,
  output        auto_in_1_b_valid,
  output [1:0]  auto_in_1_b_bits_param,
  output [31:0] auto_in_1_b_bits_address,
  output        auto_in_1_c_ready,
  input         auto_in_1_c_valid,
  input  [2:0]  auto_in_1_c_bits_opcode,
  input  [2:0]  auto_in_1_c_bits_param,
  input  [2:0]  auto_in_1_c_bits_size,
  input         auto_in_1_c_bits_source,
  input  [31:0] auto_in_1_c_bits_address,
  input  [63:0] auto_in_1_c_bits_data,
  input         auto_in_1_c_bits_corrupt,
  input         auto_in_1_d_ready,
  output        auto_in_1_d_valid,
  output [2:0]  auto_in_1_d_bits_opcode,
  output [1:0]  auto_in_1_d_bits_param,
  output [2:0]  auto_in_1_d_bits_size,
  output [4:0]  auto_in_1_d_bits_sink,
  output        auto_in_1_d_bits_denied,
  output [63:0] auto_in_1_d_bits_data,
  output        auto_in_1_d_bits_corrupt,
  input         auto_in_1_e_valid,
  input  [4:0]  auto_in_1_e_bits_sink,
  output        auto_in_0_a_ready,
  input         auto_in_0_a_valid,
  input  [2:0]  auto_in_0_a_bits_opcode,
  input  [2:0]  auto_in_0_a_bits_param,
  input  [2:0]  auto_in_0_a_bits_size,
  input         auto_in_0_a_bits_source,
  input  [31:0] auto_in_0_a_bits_address,
  input  [7:0]  auto_in_0_a_bits_mask,
  input  [63:0] auto_in_0_a_bits_data,
  input         auto_in_0_a_bits_corrupt,
  input         auto_in_0_d_ready,
  output        auto_in_0_d_valid,
  output [2:0]  auto_in_0_d_bits_opcode,
  output [1:0]  auto_in_0_d_bits_param,
  output [2:0]  auto_in_0_d_bits_size,
  output [4:0]  auto_in_0_d_bits_sink,
  output        auto_in_0_d_bits_denied,
  output [63:0] auto_in_0_d_bits_data,
  output        auto_in_0_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [2:0]  auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_param,
  input  [31:0] auto_out_b_bits_address,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [2:0]  auto_out_c_bits_size,
  output [31:0] auto_out_c_bits_address,
  output [63:0] auto_out_c_bits_data,
  output        auto_out_c_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [2:0]  auto_out_d_bits_source,
  input  [4:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [63:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt,
  output        auto_out_e_valid,
  output [4:0]  auto_out_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_1_clock; // @[Nodes.scala 24:25]
  wire  monitor_1_reset; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_b_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_b_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_b_bits_param; // @[Nodes.scala 24:25]
  wire [31:0] monitor_1_io_in_b_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_c_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_1_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_c_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [4:0] monitor_1_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [4:0] monitor_1_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_2_clock; // @[Nodes.scala 24:25]
  wire  monitor_2_reset; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_2_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_2_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_2_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_2_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_2_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_2_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_2_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_2_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [4:0] monitor_2_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_3_clock; // @[Nodes.scala 24:25]
  wire  monitor_3_reset; // @[Nodes.scala 24:25]
  wire  monitor_3_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_3_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_3_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_3_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_3_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_3_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_3_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_3_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_3_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_3_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_3_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_3_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_3_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_3_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [4:0] monitor_3_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_3_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_3_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire [2:0] _GEN_1 = {{2'd0}, auto_in_0_a_bits_source}; // @[Xbar.scala 237:55]
  wire [2:0] in_0_a_bits_source = _GEN_1 | 3'h4; // @[Xbar.scala 237:55]
  wire [1:0] _GEN_2 = {{1'd0}, auto_in_3_a_bits_source}; // @[Xbar.scala 237:55]
  wire [1:0] _in_3_a_bits_source_T = _GEN_2 | 2'h2; // @[Xbar.scala 237:55]
  wire  requestDOI_0_0 = auto_out_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
  wire  requestDOI_0_1 = auto_out_d_bits_source == 3'h3; // @[Parameters.scala 46:9]
  wire  requestDOI_0_2 = auto_out_d_bits_source[2:1] == 2'h0; // @[Parameters.scala 54:32]
  wire  requestDOI_0_3 = auto_out_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
  wire [10:0] _beatsAI_decode_T_1 = 11'hf << auto_in_0_a_bits_size; // @[package.scala 234:77]
  wire [3:0] _beatsAI_decode_T_3 = ~_beatsAI_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  beatsAI_decode = _beatsAI_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  beatsAI_opdata = ~auto_in_0_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  beatsAI_0 = beatsAI_opdata & beatsAI_decode; // @[Edges.scala 220:14]
  wire [10:0] _beatsAI_decode_T_5 = 11'hf << auto_in_1_a_bits_size; // @[package.scala 234:77]
  wire [3:0] _beatsAI_decode_T_7 = ~_beatsAI_decode_T_5[3:0]; // @[package.scala 234:46]
  wire  beatsAI_decode_1 = _beatsAI_decode_T_7[3]; // @[Edges.scala 219:59]
  wire  beatsAI_opdata_1 = ~auto_in_1_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  beatsAI_1 = beatsAI_opdata_1 & beatsAI_decode_1; // @[Edges.scala 220:14]
  wire [10:0] _beatsAI_decode_T_9 = 11'hf << auto_in_2_a_bits_size; // @[package.scala 234:77]
  wire [3:0] _beatsAI_decode_T_11 = ~_beatsAI_decode_T_9[3:0]; // @[package.scala 234:46]
  wire  beatsAI_decode_2 = _beatsAI_decode_T_11[3]; // @[Edges.scala 219:59]
  wire  beatsAI_opdata_2 = ~auto_in_2_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  beatsAI_2 = beatsAI_opdata_2 & beatsAI_decode_2; // @[Edges.scala 220:14]
  wire [10:0] _beatsAI_decode_T_13 = 11'hf << auto_in_3_a_bits_size; // @[package.scala 234:77]
  wire [3:0] _beatsAI_decode_T_15 = ~_beatsAI_decode_T_13[3:0]; // @[package.scala 234:46]
  wire  beatsAI_decode_3 = _beatsAI_decode_T_15[3]; // @[Edges.scala 219:59]
  wire  beatsAI_opdata_3 = ~auto_in_3_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  beatsAI_3 = beatsAI_opdata_3 & beatsAI_decode_3; // @[Edges.scala 220:14]
  reg  beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = ~beatsLeft; // @[Arbiter.scala 88:28]
  wire  latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
  wire [3:0] readys_valid = {auto_in_3_a_valid,auto_in_2_a_valid,auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 33:92]
  wire  _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
  reg [3:0] readys_mask; // @[Arbiter.scala 23:23]
  wire [3:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
  wire [3:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
  wire [7:0] readys_filter = {_readys_filter_T_1,auto_in_3_a_valid,auto_in_2_a_valid,auto_in_1_a_valid,auto_in_0_a_valid
    }; // @[Cat.scala 33:92]
  wire [7:0] _GEN_3 = {{1'd0}, readys_filter[7:1]}; // @[package.scala 253:43]
  wire [7:0] _readys_unready_T_1 = readys_filter | _GEN_3; // @[package.scala 253:43]
  wire [7:0] _GEN_4 = {{2'd0}, _readys_unready_T_1[7:2]}; // @[package.scala 253:43]
  wire [7:0] _readys_unready_T_3 = _readys_unready_T_1 | _GEN_4; // @[package.scala 253:43]
  wire [7:0] _readys_unready_T_6 = {readys_mask, 4'h0}; // @[Arbiter.scala 25:66]
  wire [7:0] _GEN_5 = {{1'd0}, _readys_unready_T_3[7:1]}; // @[Arbiter.scala 25:58]
  wire [7:0] readys_unready = _GEN_5 | _readys_unready_T_6; // @[Arbiter.scala 25:58]
  wire [3:0] _readys_readys_T_2 = readys_unready[7:4] & readys_unready[3:0]; // @[Arbiter.scala 26:39]
  wire [3:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire [3:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
  wire [4:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [3:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[3:0]; // @[package.scala 244:43]
  wire [5:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala 244:48]
  wire [3:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_4[3:0]; // @[package.scala 244:43]
  wire  readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
  wire  readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
  wire  readys_2 = readys_readys[2]; // @[Arbiter.scala 95:86]
  wire  readys_3 = readys_readys[3]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & auto_in_0_a_valid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1 = readys_1 & auto_in_1_a_valid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_2 = readys_2 & auto_in_2_a_valid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_3 = readys_3 & auto_in_3_a_valid; // @[Arbiter.scala 97:79]
  wire  prefixOR_2 = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  prefixOR_3 = prefixOR_2 | earlyWinner_2; // @[Arbiter.scala 104:53]
  wire  _T_21 = auto_in_0_a_valid | auto_in_1_a_valid | auto_in_2_a_valid | auto_in_3_a_valid; // @[Arbiter.scala 107:36]
  wire  _T_22 = ~(auto_in_0_a_valid | auto_in_1_a_valid | auto_in_2_a_valid | auto_in_3_a_valid); // @[Arbiter.scala 107:15]
  wire  maskedBeats_0 = earlyWinner_0 & beatsAI_0; // @[Arbiter.scala 111:73]
  wire  maskedBeats_1 = earlyWinner_1 & beatsAI_1; // @[Arbiter.scala 111:73]
  wire  maskedBeats_2 = earlyWinner_2 & beatsAI_2; // @[Arbiter.scala 111:73]
  wire  maskedBeats_3 = earlyWinner_3 & beatsAI_3; // @[Arbiter.scala 111:73]
  wire  initBeats = maskedBeats_0 | maskedBeats_1 | maskedBeats_2 | maskedBeats_3; // @[Arbiter.scala 112:44]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  reg  state_2; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_2 = idle ? earlyWinner_2 : state_2; // @[Arbiter.scala 117:30]
  reg  state_3; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_3 = idle ? earlyWinner_3 : state_3; // @[Arbiter.scala 117:30]
  wire  _out_0_a_earlyValid_T_9 = state_0 & auto_in_0_a_valid | state_1 & auto_in_1_a_valid | state_2 &
    auto_in_2_a_valid | state_3 & auto_in_3_a_valid; // @[Mux.scala 27:73]
  wire  out_4_0_a_earlyValid = idle ? _T_21 : _out_0_a_earlyValid_T_9; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_out_a_ready & out_4_0_a_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire  allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala 121:24]
  wire  allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala 121:24]
  wire [63:0] _T_48 = muxStateEarly_0 ? auto_in_0_a_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_49 = muxStateEarly_1 ? auto_in_1_a_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_50 = muxStateEarly_2 ? auto_in_2_a_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_51 = muxStateEarly_3 ? auto_in_3_a_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_52 = _T_48 | _T_49; // @[Mux.scala 27:73]
  wire [63:0] _T_53 = _T_52 | _T_50; // @[Mux.scala 27:73]
  wire [7:0] _T_55 = muxStateEarly_0 ? auto_in_0_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_56 = muxStateEarly_1 ? auto_in_1_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_57 = muxStateEarly_2 ? auto_in_2_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_58 = muxStateEarly_3 ? auto_in_3_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_59 = _T_55 | _T_56; // @[Mux.scala 27:73]
  wire [7:0] _T_60 = _T_59 | _T_57; // @[Mux.scala 27:73]
  wire [31:0] _T_62 = muxStateEarly_0 ? auto_in_0_a_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_63 = muxStateEarly_1 ? auto_in_1_a_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_64 = muxStateEarly_2 ? auto_in_2_a_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_65 = muxStateEarly_3 ? auto_in_3_a_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_66 = _T_62 | _T_63; // @[Mux.scala 27:73]
  wire [31:0] _T_67 = _T_66 | _T_64; // @[Mux.scala 27:73]
  wire [2:0] _T_69 = muxStateEarly_0 ? in_0_a_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_70 = muxStateEarly_1 ? 3'h3 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] in_2_a_bits_source = {{2'd0}, auto_in_2_a_bits_source}; // @[Xbar.scala 231:18 237:29]
  wire [2:0] _T_71 = muxStateEarly_2 ? in_2_a_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] in_3_a_bits_source = {{1'd0}, _in_3_a_bits_source_T}; // @[Xbar.scala 231:18 237:29]
  wire [2:0] _T_72 = muxStateEarly_3 ? in_3_a_bits_source : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_73 = _T_69 | _T_70; // @[Mux.scala 27:73]
  wire [2:0] _T_74 = _T_73 | _T_71; // @[Mux.scala 27:73]
  wire [2:0] _T_76 = muxStateEarly_0 ? auto_in_0_a_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_77 = muxStateEarly_1 ? auto_in_1_a_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_78 = muxStateEarly_2 ? auto_in_2_a_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_79 = muxStateEarly_3 ? auto_in_3_a_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_80 = _T_76 | _T_77; // @[Mux.scala 27:73]
  wire [2:0] _T_81 = _T_80 | _T_78; // @[Mux.scala 27:73]
  wire [2:0] _T_83 = muxStateEarly_0 ? auto_in_0_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_84 = muxStateEarly_1 ? auto_in_1_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_85 = muxStateEarly_2 ? auto_in_2_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_86 = muxStateEarly_3 ? auto_in_3_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_87 = _T_83 | _T_84; // @[Mux.scala 27:73]
  wire [2:0] _T_88 = _T_87 | _T_85; // @[Mux.scala 27:73]
  wire [2:0] _T_90 = muxStateEarly_0 ? auto_in_0_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_91 = muxStateEarly_1 ? auto_in_1_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_92 = muxStateEarly_2 ? auto_in_2_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_93 = muxStateEarly_3 ? auto_in_3_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_94 = _T_90 | _T_91; // @[Mux.scala 27:73]
  wire [2:0] _T_95 = _T_94 | _T_92; // @[Mux.scala 27:73]
  TLMonitor_2 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  TLMonitor_3 monitor_1 ( // @[Nodes.scala 24:25]
    .clock(monitor_1_clock),
    .reset(monitor_1_reset),
    .io_in_a_ready(monitor_1_io_in_a_ready),
    .io_in_a_valid(monitor_1_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
    .io_in_b_ready(monitor_1_io_in_b_ready),
    .io_in_b_valid(monitor_1_io_in_b_valid),
    .io_in_b_bits_param(monitor_1_io_in_b_bits_param),
    .io_in_b_bits_address(monitor_1_io_in_b_bits_address),
    .io_in_c_ready(monitor_1_io_in_c_ready),
    .io_in_c_valid(monitor_1_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_1_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_1_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_1_io_in_c_bits_size),
    .io_in_c_bits_source(monitor_1_io_in_c_bits_source),
    .io_in_c_bits_address(monitor_1_io_in_c_bits_address),
    .io_in_c_bits_corrupt(monitor_1_io_in_c_bits_corrupt),
    .io_in_d_ready(monitor_1_io_in_d_ready),
    .io_in_d_valid(monitor_1_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_1_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
    .io_in_d_bits_sink(monitor_1_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_1_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_1_io_in_d_bits_corrupt),
    .io_in_e_valid(monitor_1_io_in_e_valid),
    .io_in_e_bits_sink(monitor_1_io_in_e_bits_sink)
  );
  TLMonitor_4 monitor_2 ( // @[Nodes.scala 24:25]
    .clock(monitor_2_clock),
    .reset(monitor_2_reset),
    .io_in_a_ready(monitor_2_io_in_a_ready),
    .io_in_a_valid(monitor_2_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_2_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_2_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_2_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_2_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_2_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_2_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_2_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_2_io_in_d_ready),
    .io_in_d_valid(monitor_2_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_2_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_2_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_2_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_2_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_2_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_2_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_2_io_in_d_bits_corrupt)
  );
  TLMonitor_5 monitor_3 ( // @[Nodes.scala 24:25]
    .clock(monitor_3_clock),
    .reset(monitor_3_reset),
    .io_in_a_ready(monitor_3_io_in_a_ready),
    .io_in_a_valid(monitor_3_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_3_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_3_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_3_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_3_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_3_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_3_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_3_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_3_io_in_d_ready),
    .io_in_d_valid(monitor_3_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_3_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_3_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_3_io_in_d_bits_size),
    .io_in_d_bits_sink(monitor_3_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_3_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_3_io_in_d_bits_corrupt)
  );
  assign auto_in_2_a_ready = auto_out_a_ready & allowed_2; // @[Arbiter.scala 123:31]
  assign auto_in_2_d_valid = auto_out_d_valid & requestDOI_0_2; // @[Xbar.scala 179:40]
  assign auto_in_2_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_2_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_2_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_2_d_bits_source = auto_out_d_bits_source[0]; // @[Xbar.scala 228:69]
  assign auto_in_2_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign auto_in_2_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_2_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_2_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign auto_in_1_b_valid = auto_out_b_valid; // @[Xbar.scala 179:40]
  assign auto_in_1_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
  assign auto_in_1_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign auto_in_1_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign auto_in_0_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
  assign auto_in_0_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign auto_in_0_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = idle ? _T_21 : _out_0_a_earlyValid_T_9; // @[Arbiter.scala 125:29]
  assign auto_out_a_bits_opcode = _T_95 | _T_93; // @[Mux.scala 27:73]
  assign auto_out_a_bits_param = _T_88 | _T_86; // @[Mux.scala 27:73]
  assign auto_out_a_bits_size = _T_81 | _T_79; // @[Mux.scala 27:73]
  assign auto_out_a_bits_source = _T_74 | _T_72; // @[Mux.scala 27:73]
  assign auto_out_a_bits_address = _T_67 | _T_65; // @[Mux.scala 27:73]
  assign auto_out_a_bits_mask = _T_60 | _T_58; // @[Mux.scala 27:73]
  assign auto_out_a_bits_data = _T_53 | _T_51; // @[Mux.scala 27:73]
  assign auto_out_a_bits_corrupt = muxStateEarly_0 & auto_in_0_a_bits_corrupt | muxStateEarly_1 &
    auto_in_1_a_bits_corrupt | muxStateEarly_2 & auto_in_2_a_bits_corrupt | muxStateEarly_3 & auto_in_3_a_bits_corrupt; // @[Mux.scala 27:73]
  assign auto_out_b_ready = auto_in_1_b_ready; // @[Mux.scala 27:73]
  assign auto_out_c_valid = auto_in_1_c_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_c_bits_opcode = auto_in_1_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_param = auto_in_1_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_size = auto_in_1_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_address = auto_in_1_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_data = auto_in_1_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_corrupt = auto_in_1_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = requestDOI_0_0 & auto_in_0_d_ready | requestDOI_0_1 & auto_in_1_d_ready | requestDOI_0_2 &
    auto_in_2_d_ready | requestDOI_0_3 & auto_in_3_d_ready; // @[Mux.scala 27:73]
  assign auto_out_e_valid = auto_in_1_e_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_e_bits_sink = auto_in_1_e_bits_sink; // @[Xbar.scala 228:69]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign monitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_clock = clock;
  assign monitor_1_reset = reset;
  assign monitor_1_io_in_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign monitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_opcode = auto_in_1_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_param = auto_in_1_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_size = auto_in_1_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_source = auto_in_1_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_mask = auto_in_1_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_b_ready = auto_in_1_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_b_valid = auto_out_b_valid; // @[Xbar.scala 179:40]
  assign monitor_1_io_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_c_valid = auto_in_1_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_c_bits_opcode = auto_in_1_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_c_bits_param = auto_in_1_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_c_bits_size = auto_in_1_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_c_bits_source = auto_in_1_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_c_bits_address = auto_in_1_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_c_bits_corrupt = auto_in_1_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_ready = auto_in_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
  assign monitor_1_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign monitor_1_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_e_valid = auto_in_1_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_e_bits_sink = auto_in_1_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_clock = clock;
  assign monitor_2_reset = reset;
  assign monitor_2_io_in_a_ready = auto_out_a_ready & allowed_2; // @[Arbiter.scala 123:31]
  assign monitor_2_io_in_a_valid = auto_in_2_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_opcode = auto_in_2_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_param = auto_in_2_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_size = auto_in_2_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_source = auto_in_2_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_address = auto_in_2_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_mask = auto_in_2_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_corrupt = auto_in_2_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_d_ready = auto_in_2_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_d_valid = auto_out_d_valid & requestDOI_0_2; // @[Xbar.scala 179:40]
  assign monitor_2_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_2_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_2_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_2_io_in_d_bits_source = auto_out_d_bits_source[0]; // @[Xbar.scala 228:69]
  assign monitor_2_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign monitor_2_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_2_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_3_clock = clock;
  assign monitor_3_reset = reset;
  assign monitor_3_io_in_a_ready = auto_out_a_ready & allowed_3; // @[Arbiter.scala 123:31]
  assign monitor_3_io_in_a_valid = auto_in_3_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_a_bits_opcode = auto_in_3_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_a_bits_param = auto_in_3_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_a_bits_size = auto_in_3_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_a_bits_source = auto_in_3_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_a_bits_address = auto_in_3_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_a_bits_mask = auto_in_3_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_a_bits_corrupt = auto_in_3_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_d_ready = auto_in_3_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_3_io_in_d_valid = auto_out_d_valid & requestDOI_0_3; // @[Xbar.scala 179:40]
  assign monitor_3_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_3_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_3_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_3_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign monitor_3_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_3_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 1'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      beatsLeft <= initBeats;
    end else begin
      beatsLeft <= beatsLeft - _beatsLeft_T_2;
    end
    if (reset) begin // @[Arbiter.scala 23:23]
      readys_mask <= 4'hf; // @[Arbiter.scala 23:23]
    end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
      readys_mask <= _readys_mask_T_6; // @[Arbiter.scala 28:12]
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_2 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_2 <= earlyWinner_2;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_3 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_3 <= earlyWinner_3;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Arbiter.scala 22:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~
          earlyWinner_3))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~earlyWinner_3)) &
          _readys_T_3) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~(auto_in_0_a_valid | auto_in_1_a_valid | auto_in_2_a_valid | auto_in_3_a_valid) | (
          prefixOR_3 | earlyWinner_3))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(auto_in_0_a_valid | auto_in_1_a_valid | auto_in_2_a_valid | auto_in_3_a_valid) | (prefixOR_3 |
          earlyWinner_3)) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(_T_22 | _T_21)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_22 | _T_21) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  readys_mask = _RAND_1[3:0];
  _RAND_2 = {1{`RANDOM}};
  state_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_1 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  state_2 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  state_3 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_6(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [8:0]  io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [8:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [319:0] _RAND_10;
  reg [1279:0] _RAND_11;
  reg [1279:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [319:0] _RAND_16;
  reg [1279:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 9'h13f; // @[Parameters.scala 57:20]
  wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_15 = {{29'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_15; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
  wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire [32:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [32:0] _T_36 = $signed(_T_12) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_163 = 2'h3 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_170 = _T_163 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_181 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_185 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_193 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_214 = _source_ok_T_4 & _T_170; // @[Monitor.scala 115:71]
  wire  _T_232 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_267 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_268 = io_in_a_bits_mask & _T_267; // @[Monitor.scala 127:31]
  wire  _T_269 = _T_268 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_273 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_303 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_311 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_341 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_349 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_379 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_391 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 9'h13f; // @[Parameters.scala 57:20]
  wire  _T_395 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_399 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
  wire  _T_415 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_443 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_489 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_507 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [8:0] source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_537 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_538 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_542 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_546 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_550 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_554 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [8:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_561 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_562 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_570 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_574 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [319:0] inflight; // @[Monitor.scala 611:27]
  reg [1279:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [1279:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [10:0] _GEN_21 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T = {{1'd0}, _GEN_21}; // @[Monitor.scala 634:69]
  wire [1279:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [1279:0] _GEN_60 = {{1264'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [1279:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_60; // @[Monitor.scala 634:97]
  wire [1279:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[1279:1]}; // @[Monitor.scala 634:152]
  wire [1279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [1279:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_60; // @[Monitor.scala 638:91]
  wire [1279:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[1279:1]}; // @[Monitor.scala 638:144]
  wire  _T_591 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [511:0] _a_set_T = 512'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [10:0] _GEN_71 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [11:0] _a_opcodes_set_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [4098:0] _GEN_305 = {{4095'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [4098:0] _a_opcodes_set_T_1 = _GEN_305 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [4097:0] _GEN_306 = {{4095'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [4097:0] _a_sizes_set_T_1 = _GEN_306 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [319:0] _T_593 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_595 = ~_T_593[0]; // @[Monitor.scala 658:17]
  wire [511:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_T : 512'h0; // @[Monitor.scala 652:72 653:28]
  wire [4098:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 4099'h0; // @[Monitor.scala 652:72 656:28]
  wire [4097:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 4098'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_606 = ~_T_395; // @[Monitor.scala 675:75]
  wire [511:0] _d_clr_T = 512'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [4110:0] _GEN_307 = {{4095'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [4110:0] _d_opcodes_clr_T_5 = _GEN_307 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [511:0] _GEN_22 = _d_first_T & d_first_1 & ~_T_395 ? _d_clr_T : 512'h0; // @[Monitor.scala 675:91 676:21]
  wire [4110:0] _GEN_23 = _d_first_T & d_first_1 & ~_T_395 ? _d_opcodes_clr_T_5 : 4111'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_608 = io_in_d_valid & d_first_1; // @[Monitor.scala 680:26]
  wire  _T_611 = io_in_d_valid & d_first_1 & _T_606; // @[Monitor.scala 680:71]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = io_in_a_valid & a_first_1 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [319:0] _T_612 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_614 = _T_612[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_619 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_620 = io_in_d_bits_opcode == _GEN_32 | _T_619; // @[Monitor.scala 685:77]
  wire  _T_624 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_631 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_632 = io_in_d_bits_opcode == _GEN_48 | _T_631; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_75 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_636 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_646 = _T_608 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_606; // @[Monitor.scala 694:116]
  wire  _T_647 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_648 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [319:0] a_set = _GEN_16[319:0];
  wire [319:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [319:0] d_clr = _GEN_22[319:0];
  wire [319:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [319:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [1279:0] a_opcodes_set = _GEN_19[1279:0];
  wire [1279:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [1279:0] d_opcodes_clr = _GEN_23[1279:0];
  wire [1279:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [1279:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [1279:0] a_sizes_set = _GEN_20[1279:0];
  wire [1279:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [1279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_657 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [319:0] inflight_1; // @[Monitor.scala 723:35]
  reg [1279:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [1279:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [1279:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_60; // @[Monitor.scala 747:93]
  wire [1279:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[1279:1]}; // @[Monitor.scala 747:146]
  wire  _T_677 = ~inflight_1[0]; // @[Monitor.scala 766:17]
  wire [511:0] _GEN_67 = _d_first_T & d_first_2 & _T_395 ? _d_clr_T : 512'h0; // @[Monitor.scala 783:90 784:21]
  wire [4110:0] _GEN_69 = _d_first_T & d_first_2 & _T_395 ? _d_opcodes_clr_T_5 : 4111'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_690 = io_in_d_valid & d_first_2 & _T_395; // @[Monitor.scala 789:71]
  wire [319:0] _T_691 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_697 = io_in_d_bits_size == 2'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_701 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [319:0] d_clr_1 = _GEN_67[319:0];
  wire [319:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [319:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [1279:0] d_sizes_clr_1 = _GEN_69[1279:0];
  wire [1279:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [1279:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_721 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 320'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 1280'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 1280'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 320'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 1280'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_170) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_170 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_214) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_214 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~_T_214) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_214 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~_T_303) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_303 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~_T_341) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_341 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_391) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_391 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_395 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_395 & _T_2 & ~_T_399) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_399 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_399) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_399 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_443 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_443 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_443 & _T_2 & ~_T_399) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_399 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_489 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_507 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_507 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_507 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_507 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_507 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_538 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_542) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_542 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_546 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_550 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_554) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_554 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_561 & _T_2 & ~_T_562) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_562 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_561 & _T_2 & ~_T_570) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_570 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_561 & _T_2 & ~_T_574) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_574 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_591 & ~reset & ~_T_595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_595 & (_T_591 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & _T_2 & ~_T_614) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_614 & (_T_611 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & same_cycle_resp & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_611 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & same_cycle_resp & _T_2 & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_611 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & ~same_cycle_resp & _T_2 & ~_T_632) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_632 & (_T_611 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & ~same_cycle_resp & _T_2 & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & (_T_611 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_646 & _T_2 & ~_T_648) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_648 & (_T_646 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_657) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_657 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_690 & _T_2 & ~_T_691[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_691[0] & (_T_690 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_690 & _T_2 & ~_T_701) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701 & (_T_690 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_647 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_721) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:70:17)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_721 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[8:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[8:0];
  _RAND_10 = {10{`RANDOM}};
  inflight = _RAND_10[319:0];
  _RAND_11 = {40{`RANDOM}};
  inflight_opcodes = _RAND_11[1279:0];
  _RAND_12 = {40{`RANDOM}};
  inflight_sizes = _RAND_12[1279:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {10{`RANDOM}};
  inflight_1 = _RAND_16[319:0];
  _RAND_17 = {40{`RANDOM}};
  inflight_sizes_1 = _RAND_17[1279:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_7(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_15 = {{29'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_15; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
  wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
  wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [32:0] _T_26 = $signed(_T_7) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_63 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_64 = _T_63 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_68 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_72 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_120 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_133 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_143 = 2'h3 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_150 = _T_143 & _T_27; // @[Parameters.scala 670:56]
  wire  _T_161 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_165 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_173 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_189 = _source_ok_T & _T_150; // @[Monitor.scala 115:71]
  wire  _T_207 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_237 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_238 = io_in_a_bits_mask & _T_237; // @[Monitor.scala 127:31]
  wire  _T_239 = _T_238 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_243 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_268 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_276 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_301 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_309 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_346 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_350 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_354 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
  wire  _T_370 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_398 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_427 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_444 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_462 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_492 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_493 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_497 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_501 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_505 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_509 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  wire  _T_516 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_517 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_525 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_21 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_21 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _GEN_62 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_62 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_546 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [1:0] _a_set_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_66 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_66}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_285 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_285 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [17:0] _GEN_286 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [17:0] _a_sizes_set_T_1 = _GEN_286 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire  _T_550 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [17:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_561 = ~_T_350; // @[Monitor.scala 675:75]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = _d_first_T & d_first_1 & ~_T_350 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = _d_first_T & d_first_1 & ~_T_350 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_563 = io_in_d_valid & d_first_1; // @[Monitor.scala 680:26]
  wire  _T_566 = io_in_d_valid & d_first_1 & _T_561; // @[Monitor.scala 680:71]
  wire  same_cycle_resp = io_in_a_valid & a_first_1 & _source_ok_T; // @[Monitor.scala 681:88]
  wire  _T_569 = inflight | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_574 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_575 = io_in_d_bits_opcode == _GEN_32 | _T_574; // @[Monitor.scala 685:77]
  wire  _T_579 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_586 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_587 = io_in_d_bits_opcode == _GEN_48 | _T_586; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_71 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_591 = _GEN_71 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_601 = _T_563 & a_first_1 & io_in_a_valid & _source_ok_T & _T_561; // @[Monitor.scala 694:116]
  wire  _T_602 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_603 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_612 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [15:0] _GEN_72 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_350 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_645 = io_in_d_valid & d_first_2 & _T_350; // @[Monitor.scala 789:71]
  wire  _T_652 = io_in_d_bits_size == 2'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_656 = _GEN_71 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] d_sizes_clr_1 = _GEN_69[3:0];
  wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_59) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_59 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_64) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_64 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_68) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_68 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_T_59) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_59 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_T_120) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_120 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_T_64) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_64 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_T_68) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_68 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_150) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_150 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_161) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_161 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_68) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_68 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~_T_161) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_161 & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~_T_161) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_161 & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~_T_239) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_239 & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~_T_68) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_68 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_346) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_346 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_350 & _T_2 & ~_T_354) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_354 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_370 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_370 & _T_2 & ~_T_354) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_354 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_398 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_398 & _T_2 & ~_T_354) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_354 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_462 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_462 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_462 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_462 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_493) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_493 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_497) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_497 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_501) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_501 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_505) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_505 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_509) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_509 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_516 & _T_2 & ~_T_517) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_517 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_516 & _T_2 & ~_T_525) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_525 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_546 & ~reset & ~_T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_550 & (_T_546 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & _T_2 & ~_T_569) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_569 & (_T_566 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & same_cycle_resp & _T_2 & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & same_cycle_resp & _T_2 & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~same_cycle_resp & _T_2 & ~_T_587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_587 & (_T_566 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~same_cycle_resp & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_566 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_601 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_612) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_612 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_645 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (_T_645 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_652 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_645 & _T_2 & ~_T_656) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:85:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_656 & (_T_645 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_602 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  inflight = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight_opcodes = _RAND_10[3:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_sizes = _RAND_11[3:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_15[3:0];
  _RAND_16 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_8(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_15 = {{29'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_15; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
  wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
  wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [32:0] _T_26 = $signed(_T_7) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_63 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_64 = _T_63 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_68 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_72 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_120 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_133 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_143 = 2'h3 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_150 = _T_143 & _T_27; // @[Parameters.scala 670:56]
  wire  _T_161 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_165 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_173 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_189 = _source_ok_T & _T_150; // @[Monitor.scala 115:71]
  wire  _T_207 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_237 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_238 = io_in_a_bits_mask & _T_237; // @[Monitor.scala 127:31]
  wire  _T_239 = _T_238 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_243 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_268 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_276 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_301 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_309 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_346 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_350 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_354 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
  wire  _T_370 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_398 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_427 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_444 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_462 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_492 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_493 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_497 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_501 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_505 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_509 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  wire  _T_516 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_517 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_525 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_21 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_21 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _GEN_62 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_62 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_546 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [1:0] _a_set_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_66 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_66}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_285 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_285 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [17:0] _GEN_286 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [17:0] _a_sizes_set_T_1 = _GEN_286 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire  _T_550 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [17:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_561 = ~_T_350; // @[Monitor.scala 675:75]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = _d_first_T & d_first_1 & ~_T_350 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = _d_first_T & d_first_1 & ~_T_350 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_563 = io_in_d_valid & d_first_1; // @[Monitor.scala 680:26]
  wire  _T_566 = io_in_d_valid & d_first_1 & _T_561; // @[Monitor.scala 680:71]
  wire  same_cycle_resp = io_in_a_valid & a_first_1 & _source_ok_T; // @[Monitor.scala 681:88]
  wire  _T_569 = inflight | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_574 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_575 = io_in_d_bits_opcode == _GEN_32 | _T_574; // @[Monitor.scala 685:77]
  wire  _T_579 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_586 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_587 = io_in_d_bits_opcode == _GEN_48 | _T_586; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_71 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_591 = _GEN_71 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_601 = _T_563 & a_first_1 & io_in_a_valid & _source_ok_T & _T_561; // @[Monitor.scala 694:116]
  wire  _T_602 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_603 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_612 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [15:0] _GEN_72 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_350 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_645 = io_in_d_valid & d_first_2 & _T_350; // @[Monitor.scala 789:71]
  wire  _T_652 = io_in_d_bits_size == 2'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_656 = _GEN_71 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] d_sizes_clr_1 = _GEN_69[3:0];
  wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_59) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_59 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_64) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_64 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_68) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_68 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_T_59) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_59 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_T_120) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_120 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_T_64) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_64 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~_T_68) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_68 & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_150) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_150 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_161) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_161 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_68) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_68 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~_T_161) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_161 & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~_T_161) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_161 & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~_T_239) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_239 & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_243 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_243 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~_T_68) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_68 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_346) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_346 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_350 & _T_2 & ~_T_354) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_354 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_370 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_370 & _T_2 & ~_T_354) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_354 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_370 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_398 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_398 & _T_2 & ~_T_354) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_354 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_462 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_462 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_462 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_462 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_493) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_493 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_497) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_497 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_501) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_501 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_505) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_505 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_492 & ~reset & ~_T_509) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_509 & (_T_492 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_516 & _T_2 & ~_T_517) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_517 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_516 & _T_2 & ~_T_525) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_525 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_516 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_546 & ~reset & ~_T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_550 & (_T_546 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & _T_2 & ~_T_569) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_569 & (_T_566 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & same_cycle_resp & _T_2 & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & same_cycle_resp & _T_2 & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~same_cycle_resp & _T_2 & ~_T_587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_587 & (_T_566 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~same_cycle_resp & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_566 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_601 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_612) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_612 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_645 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (_T_645 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_652 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_645 & _T_2 & ~_T_656) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:86:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_656 & (_T_645 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_602 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  inflight = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight_opcodes = _RAND_10[3:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_sizes = _RAND_11[3:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_15[3:0];
  _RAND_16 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLXbar_1(
  input         clock,
  input         reset,
  output        auto_in_2_a_ready,
  input         auto_in_2_a_valid,
  input  [2:0]  auto_in_2_a_bits_opcode,
  input  [2:0]  auto_in_2_a_bits_param,
  input  [1:0]  auto_in_2_a_bits_size,
  input         auto_in_2_a_bits_source,
  input  [31:0] auto_in_2_a_bits_address,
  input  [7:0]  auto_in_2_a_bits_mask,
  input  [63:0] auto_in_2_a_bits_data,
  input         auto_in_2_a_bits_corrupt,
  input         auto_in_2_d_ready,
  output        auto_in_2_d_valid,
  output [2:0]  auto_in_2_d_bits_opcode,
  output [63:0] auto_in_2_d_bits_data,
  output        auto_in_1_a_ready,
  input         auto_in_1_a_valid,
  input  [2:0]  auto_in_1_a_bits_opcode,
  input  [2:0]  auto_in_1_a_bits_param,
  input  [1:0]  auto_in_1_a_bits_size,
  input         auto_in_1_a_bits_source,
  input  [31:0] auto_in_1_a_bits_address,
  input  [7:0]  auto_in_1_a_bits_mask,
  input  [63:0] auto_in_1_a_bits_data,
  input         auto_in_1_a_bits_corrupt,
  input         auto_in_1_d_ready,
  output        auto_in_1_d_valid,
  output [2:0]  auto_in_1_d_bits_opcode,
  output [63:0] auto_in_1_d_bits_data,
  output        auto_in_0_a_ready,
  input         auto_in_0_a_valid,
  input  [2:0]  auto_in_0_a_bits_opcode,
  input  [2:0]  auto_in_0_a_bits_param,
  input  [1:0]  auto_in_0_a_bits_size,
  input  [8:0]  auto_in_0_a_bits_source,
  input  [31:0] auto_in_0_a_bits_address,
  input  [7:0]  auto_in_0_a_bits_mask,
  input  [63:0] auto_in_0_a_bits_data,
  input         auto_in_0_a_bits_corrupt,
  input         auto_in_0_d_ready,
  output        auto_in_0_d_valid,
  output [2:0]  auto_in_0_d_bits_opcode,
  output [1:0]  auto_in_0_d_bits_size,
  output [8:0]  auto_in_0_d_bits_source,
  output [63:0] auto_in_0_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [9:0]  auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [9:0]  auto_out_d_bits_source,
  input  [63:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_1_clock; // @[Nodes.scala 24:25]
  wire  monitor_1_reset; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_2_clock; // @[Nodes.scala 24:25]
  wire  monitor_2_reset; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_2_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_2_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_2_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_2_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_2_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_2_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_2_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_2_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [9:0] _GEN_1 = {{9'd0}, auto_in_1_a_bits_source}; // @[Xbar.scala 237:55]
  wire [9:0] in_1_a_bits_source = _GEN_1 | 10'h201; // @[Xbar.scala 237:55]
  wire [9:0] _GEN_2 = {{9'd0}, auto_in_2_a_bits_source}; // @[Xbar.scala 237:55]
  wire [9:0] in_2_a_bits_source = _GEN_2 | 10'h200; // @[Xbar.scala 237:55]
  wire  requestDOI_0_0 = ~auto_out_d_bits_source[9]; // @[Parameters.scala 54:32]
  wire  requestDOI_0_1 = auto_out_d_bits_source == 10'h201; // @[Parameters.scala 46:9]
  wire  requestDOI_0_2 = auto_out_d_bits_source == 10'h200; // @[Parameters.scala 46:9]
  reg  beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = ~beatsLeft; // @[Arbiter.scala 88:28]
  wire  latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
  wire [2:0] readys_valid = {auto_in_2_a_valid,auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 33:92]
  wire  _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
  reg [2:0] readys_mask; // @[Arbiter.scala 23:23]
  wire [2:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
  wire [2:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
  wire [5:0] readys_filter = {_readys_filter_T_1,auto_in_2_a_valid,auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 33:92]
  wire [5:0] _GEN_3 = {{1'd0}, readys_filter[5:1]}; // @[package.scala 253:43]
  wire [5:0] _readys_unready_T_1 = readys_filter | _GEN_3; // @[package.scala 253:43]
  wire [5:0] _GEN_4 = {{2'd0}, _readys_unready_T_1[5:2]}; // @[package.scala 253:43]
  wire [5:0] _readys_unready_T_3 = _readys_unready_T_1 | _GEN_4; // @[package.scala 253:43]
  wire [5:0] _readys_unready_T_6 = {readys_mask, 3'h0}; // @[Arbiter.scala 25:66]
  wire [5:0] _GEN_5 = {{1'd0}, _readys_unready_T_3[5:1]}; // @[Arbiter.scala 25:58]
  wire [5:0] readys_unready = _GEN_5 | _readys_unready_T_6; // @[Arbiter.scala 25:58]
  wire [2:0] _readys_readys_T_2 = readys_unready[5:3] & readys_unready[2:0]; // @[Arbiter.scala 26:39]
  wire [2:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire [2:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
  wire [3:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [2:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[2:0]; // @[package.scala 244:43]
  wire [4:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala 244:48]
  wire [2:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_4[2:0]; // @[package.scala 244:43]
  wire  readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
  wire  readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
  wire  readys_2 = readys_readys[2]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & auto_in_0_a_valid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1 = readys_1 & auto_in_1_a_valid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_2 = readys_2 & auto_in_2_a_valid; // @[Arbiter.scala 97:79]
  wire  prefixOR_2 = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  _T_15 = auto_in_0_a_valid | auto_in_1_a_valid | auto_in_2_a_valid; // @[Arbiter.scala 107:36]
  wire  _T_16 = ~(auto_in_0_a_valid | auto_in_1_a_valid | auto_in_2_a_valid); // @[Arbiter.scala 107:15]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  reg  state_2; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_2 = idle ? earlyWinner_2 : state_2; // @[Arbiter.scala 117:30]
  wire  _out_0_a_earlyValid_T_6 = state_0 & auto_in_0_a_valid | state_1 & auto_in_1_a_valid | state_2 &
    auto_in_2_a_valid; // @[Mux.scala 27:73]
  wire  out_3_0_a_earlyValid = idle ? _T_15 : _out_0_a_earlyValid_T_6; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_out_a_ready & out_3_0_a_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire  allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala 121:24]
  wire [63:0] _T_37 = muxStateEarly_0 ? auto_in_0_a_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_38 = muxStateEarly_1 ? auto_in_1_a_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_39 = muxStateEarly_2 ? auto_in_2_a_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_40 = _T_37 | _T_38; // @[Mux.scala 27:73]
  wire [7:0] _T_42 = muxStateEarly_0 ? auto_in_0_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_43 = muxStateEarly_1 ? auto_in_1_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_44 = muxStateEarly_2 ? auto_in_2_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_45 = _T_42 | _T_43; // @[Mux.scala 27:73]
  wire [31:0] _T_47 = muxStateEarly_0 ? auto_in_0_a_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_48 = muxStateEarly_1 ? auto_in_1_a_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_49 = muxStateEarly_2 ? auto_in_2_a_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_50 = _T_47 | _T_48; // @[Mux.scala 27:73]
  wire [9:0] in_0_a_bits_source = {{1'd0}, auto_in_0_a_bits_source}; // @[Xbar.scala 231:18 237:29]
  wire [9:0] _T_52 = muxStateEarly_0 ? in_0_a_bits_source : 10'h0; // @[Mux.scala 27:73]
  wire [9:0] _T_53 = muxStateEarly_1 ? in_1_a_bits_source : 10'h0; // @[Mux.scala 27:73]
  wire [9:0] _T_54 = muxStateEarly_2 ? in_2_a_bits_source : 10'h0; // @[Mux.scala 27:73]
  wire [9:0] _T_55 = _T_52 | _T_53; // @[Mux.scala 27:73]
  wire [1:0] _T_57 = muxStateEarly_0 ? auto_in_0_a_bits_size : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_58 = muxStateEarly_1 ? auto_in_1_a_bits_size : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_59 = muxStateEarly_2 ? auto_in_2_a_bits_size : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_60 = _T_57 | _T_58; // @[Mux.scala 27:73]
  wire [2:0] _T_62 = muxStateEarly_0 ? auto_in_0_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_63 = muxStateEarly_1 ? auto_in_1_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_64 = muxStateEarly_2 ? auto_in_2_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_65 = _T_62 | _T_63; // @[Mux.scala 27:73]
  wire [2:0] _T_67 = muxStateEarly_0 ? auto_in_0_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_68 = muxStateEarly_1 ? auto_in_1_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_69 = muxStateEarly_2 ? auto_in_2_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_70 = _T_67 | _T_68; // @[Mux.scala 27:73]
  TLMonitor_6 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  TLMonitor_7 monitor_1 ( // @[Nodes.scala 24:25]
    .clock(monitor_1_clock),
    .reset(monitor_1_reset),
    .io_in_a_ready(monitor_1_io_in_a_ready),
    .io_in_a_valid(monitor_1_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_1_io_in_d_ready),
    .io_in_d_valid(monitor_1_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_1_io_in_d_bits_size)
  );
  TLMonitor_8 monitor_2 ( // @[Nodes.scala 24:25]
    .clock(monitor_2_clock),
    .reset(monitor_2_reset),
    .io_in_a_ready(monitor_2_io_in_a_ready),
    .io_in_a_valid(monitor_2_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_2_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_2_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_2_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_2_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_2_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_2_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_2_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_2_io_in_d_ready),
    .io_in_d_valid(monitor_2_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_2_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_2_io_in_d_bits_size)
  );
  assign auto_in_2_a_ready = auto_out_a_ready & allowed_2; // @[Arbiter.scala 123:31]
  assign auto_in_2_d_valid = auto_out_d_valid & requestDOI_0_2; // @[Xbar.scala 179:40]
  assign auto_in_2_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_2_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign auto_in_1_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
  assign auto_in_1_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign auto_in_0_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
  assign auto_in_0_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_source = auto_out_d_bits_source[8:0]; // @[Xbar.scala 228:69]
  assign auto_in_0_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = idle ? _T_15 : _out_0_a_earlyValid_T_6; // @[Arbiter.scala 125:29]
  assign auto_out_a_bits_opcode = _T_70 | _T_69; // @[Mux.scala 27:73]
  assign auto_out_a_bits_param = _T_65 | _T_64; // @[Mux.scala 27:73]
  assign auto_out_a_bits_size = _T_60 | _T_59; // @[Mux.scala 27:73]
  assign auto_out_a_bits_source = _T_55 | _T_54; // @[Mux.scala 27:73]
  assign auto_out_a_bits_address = _T_50 | _T_49; // @[Mux.scala 27:73]
  assign auto_out_a_bits_mask = _T_45 | _T_44; // @[Mux.scala 27:73]
  assign auto_out_a_bits_data = _T_40 | _T_39; // @[Mux.scala 27:73]
  assign auto_out_a_bits_corrupt = muxStateEarly_0 & auto_in_0_a_bits_corrupt | muxStateEarly_1 &
    auto_in_1_a_bits_corrupt | muxStateEarly_2 & auto_in_2_a_bits_corrupt; // @[Mux.scala 27:73]
  assign auto_out_d_ready = requestDOI_0_0 & auto_in_0_d_ready | requestDOI_0_1 & auto_in_1_d_ready | requestDOI_0_2 &
    auto_in_2_d_ready; // @[Mux.scala 27:73]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign monitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[8:0]; // @[Xbar.scala 228:69]
  assign monitor_1_clock = clock;
  assign monitor_1_reset = reset;
  assign monitor_1_io_in_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign monitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_opcode = auto_in_1_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_param = auto_in_1_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_size = auto_in_1_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_source = auto_in_1_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_mask = auto_in_1_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_ready = auto_in_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
  assign monitor_1_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_2_clock = clock;
  assign monitor_2_reset = reset;
  assign monitor_2_io_in_a_ready = auto_out_a_ready & allowed_2; // @[Arbiter.scala 123:31]
  assign monitor_2_io_in_a_valid = auto_in_2_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_opcode = auto_in_2_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_param = auto_in_2_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_size = auto_in_2_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_source = auto_in_2_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_address = auto_in_2_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_mask = auto_in_2_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_a_bits_corrupt = auto_in_2_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_d_ready = auto_in_2_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_2_io_in_d_valid = auto_out_d_valid & requestDOI_0_2; // @[Xbar.scala 179:40]
  assign monitor_2_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_2_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 1'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      beatsLeft <= 1'h0;
    end else begin
      beatsLeft <= beatsLeft - _beatsLeft_T_2;
    end
    if (reset) begin // @[Arbiter.scala 23:23]
      readys_mask <= 3'h7; // @[Arbiter.scala 23:23]
    end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
      readys_mask <= _readys_mask_T_6; // @[Arbiter.scala 28:12]
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_2 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_2 <= earlyWinner_2;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Arbiter.scala 22:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2)) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~(auto_in_0_a_valid | auto_in_1_a_valid | auto_in_2_a_valid) | (prefixOR_2 | earlyWinner_2))
          ) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(auto_in_0_a_valid | auto_in_1_a_valid | auto_in_2_a_valid) | (prefixOR_2 | earlyWinner_2)) & _readys_T_3
          ) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(_T_16 | _T_15)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_16 | _T_15) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  readys_mask = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  state_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_1 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  state_2 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_9(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [8:0]  io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [8:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [319:0] _RAND_10;
  reg [1279:0] _RAND_11;
  reg [1279:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [319:0] _RAND_16;
  reg [1279:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 9'h13f; // @[Parameters.scala 57:20]
  wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_15 = {{29'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_15; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
  wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire [32:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [32:0] _T_36 = $signed(_T_12) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_163 = 2'h3 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_170 = _T_163 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_181 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_185 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_193 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_214 = _source_ok_T_4 & _T_170; // @[Monitor.scala 115:71]
  wire  _T_232 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_267 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_268 = io_in_a_bits_mask & _T_267; // @[Monitor.scala 127:31]
  wire  _T_269 = _T_268 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_273 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_303 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_311 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_341 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_349 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_379 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_391 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 9'h13f; // @[Parameters.scala 57:20]
  wire  _T_395 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_399 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
  wire  _T_415 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_443 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_489 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_507 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [8:0] source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_537 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_538 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_542 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_546 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_550 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_554 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [8:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_561 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_562 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_570 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_574 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [319:0] inflight; // @[Monitor.scala 611:27]
  reg [1279:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [1279:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [10:0] _GEN_21 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T = {{1'd0}, _GEN_21}; // @[Monitor.scala 634:69]
  wire [1279:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [1279:0] _GEN_60 = {{1264'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [1279:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_60; // @[Monitor.scala 634:97]
  wire [1279:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[1279:1]}; // @[Monitor.scala 634:152]
  wire [1279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [1279:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_60; // @[Monitor.scala 638:91]
  wire [1279:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[1279:1]}; // @[Monitor.scala 638:144]
  wire  _T_591 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [511:0] _a_set_T = 512'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [10:0] _GEN_71 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [11:0] _a_opcodes_set_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [4098:0] _GEN_305 = {{4095'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [4098:0] _a_opcodes_set_T_1 = _GEN_305 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [4097:0] _GEN_306 = {{4095'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [4097:0] _a_sizes_set_T_1 = _GEN_306 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [319:0] _T_593 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_595 = ~_T_593[0]; // @[Monitor.scala 658:17]
  wire [511:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_T : 512'h0; // @[Monitor.scala 652:72 653:28]
  wire [4098:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 4099'h0; // @[Monitor.scala 652:72 656:28]
  wire [4097:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 4098'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_606 = ~_T_395; // @[Monitor.scala 675:75]
  wire [511:0] _d_clr_T = 512'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [4110:0] _GEN_307 = {{4095'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [4110:0] _d_opcodes_clr_T_5 = _GEN_307 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [511:0] _GEN_22 = _d_first_T & d_first_1 & ~_T_395 ? _d_clr_T : 512'h0; // @[Monitor.scala 675:91 676:21]
  wire [4110:0] _GEN_23 = _d_first_T & d_first_1 & ~_T_395 ? _d_opcodes_clr_T_5 : 4111'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_608 = io_in_d_valid & d_first_1; // @[Monitor.scala 680:26]
  wire  _T_611 = io_in_d_valid & d_first_1 & _T_606; // @[Monitor.scala 680:71]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = io_in_a_valid & a_first_1 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [319:0] _T_612 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_614 = _T_612[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_619 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_620 = io_in_d_bits_opcode == _GEN_32 | _T_619; // @[Monitor.scala 685:77]
  wire  _T_624 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_631 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_632 = io_in_d_bits_opcode == _GEN_48 | _T_631; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_75 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_636 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_646 = _T_608 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_606; // @[Monitor.scala 694:116]
  wire  _T_647 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_648 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [319:0] a_set = _GEN_16[319:0];
  wire [319:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [319:0] d_clr = _GEN_22[319:0];
  wire [319:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [319:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [1279:0] a_opcodes_set = _GEN_19[1279:0];
  wire [1279:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [1279:0] d_opcodes_clr = _GEN_23[1279:0];
  wire [1279:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [1279:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [1279:0] a_sizes_set = _GEN_20[1279:0];
  wire [1279:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [1279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_657 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [319:0] inflight_1; // @[Monitor.scala 723:35]
  reg [1279:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [1279:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [1279:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_60; // @[Monitor.scala 747:93]
  wire [1279:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[1279:1]}; // @[Monitor.scala 747:146]
  wire  _T_677 = ~inflight_1[0]; // @[Monitor.scala 766:17]
  wire [511:0] _GEN_67 = _d_first_T & d_first_2 & _T_395 ? _d_clr_T : 512'h0; // @[Monitor.scala 783:90 784:21]
  wire [4110:0] _GEN_69 = _d_first_T & d_first_2 & _T_395 ? _d_opcodes_clr_T_5 : 4111'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_690 = io_in_d_valid & d_first_2 & _T_395; // @[Monitor.scala 789:71]
  wire [319:0] _T_691 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_697 = io_in_d_bits_size == 2'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_701 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [319:0] d_clr_1 = _GEN_67[319:0];
  wire [319:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [319:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [1279:0] d_sizes_clr_1 = _GEN_69[1279:0];
  wire [1279:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [1279:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_721 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 320'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 1280'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 1280'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 320'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 1280'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_170) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_170 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_214) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_214 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~_T_214) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_214 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~_T_303) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_303 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~_T_341) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_341 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_391) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_391 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_395 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_395 & _T_2 & ~_T_399) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_399 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_395 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_399) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_399 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_443 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_443 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_443 & _T_2 & ~_T_399) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_399 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_443 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_489 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_507 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_507 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_507 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_507 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_507 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_538 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_542) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_542 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_546 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_550 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_554) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_554 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_561 & _T_2 & ~_T_562) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_562 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_561 & _T_2 & ~_T_570) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_570 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_561 & _T_2 & ~_T_574) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_574 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_591 & ~reset & ~_T_595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_595 & (_T_591 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & _T_2 & ~_T_614) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_614 & (_T_611 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & same_cycle_resp & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_611 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & same_cycle_resp & _T_2 & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_611 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & ~same_cycle_resp & _T_2 & ~_T_632) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_632 & (_T_611 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_611 & ~same_cycle_resp & _T_2 & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & (_T_611 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_646 & _T_2 & ~_T_648) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_648 & (_T_646 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_657) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_657 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_690 & _T_2 & ~_T_691[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_691[0] & (_T_690 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_690 & _T_2 & ~_T_701) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701 & (_T_690 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_647 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_721) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:70:35)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_721 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[8:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[8:0];
  _RAND_10 = {10{`RANDOM}};
  inflight = _RAND_10[319:0];
  _RAND_11 = {40{`RANDOM}};
  inflight_opcodes = _RAND_11[1279:0];
  _RAND_12 = {40{`RANDOM}};
  inflight_sizes = _RAND_12[1279:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {10{`RANDOM}};
  inflight_1 = _RAND_16[319:0];
  _RAND_17 = {40{`RANDOM}};
  inflight_sizes_1 = _RAND_17[1279:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFIFOFixer(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [1:0]  auto_in_a_bits_size,
  input  [8:0]  auto_in_a_bits_source,
  input  [31:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_size,
  output [8:0]  auto_in_d_bits_source,
  output [63:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [8:0]  auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [8:0]  auto_out_d_bits_source,
  input  [63:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_91;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
  reg [31:0] _RAND_94;
  reg [31:0] _RAND_95;
  reg [31:0] _RAND_96;
  reg [31:0] _RAND_97;
  reg [31:0] _RAND_98;
  reg [31:0] _RAND_99;
  reg [31:0] _RAND_100;
  reg [31:0] _RAND_101;
  reg [31:0] _RAND_102;
  reg [31:0] _RAND_103;
  reg [31:0] _RAND_104;
  reg [31:0] _RAND_105;
  reg [31:0] _RAND_106;
  reg [31:0] _RAND_107;
  reg [31:0] _RAND_108;
  reg [31:0] _RAND_109;
  reg [31:0] _RAND_110;
  reg [31:0] _RAND_111;
  reg [31:0] _RAND_112;
  reg [31:0] _RAND_113;
  reg [31:0] _RAND_114;
  reg [31:0] _RAND_115;
  reg [31:0] _RAND_116;
  reg [31:0] _RAND_117;
  reg [31:0] _RAND_118;
  reg [31:0] _RAND_119;
  reg [31:0] _RAND_120;
  reg [31:0] _RAND_121;
  reg [31:0] _RAND_122;
  reg [31:0] _RAND_123;
  reg [31:0] _RAND_124;
  reg [31:0] _RAND_125;
  reg [31:0] _RAND_126;
  reg [31:0] _RAND_127;
  reg [31:0] _RAND_128;
  reg [31:0] _RAND_129;
  reg [31:0] _RAND_130;
  reg [31:0] _RAND_131;
  reg [31:0] _RAND_132;
  reg [31:0] _RAND_133;
  reg [31:0] _RAND_134;
  reg [31:0] _RAND_135;
  reg [31:0] _RAND_136;
  reg [31:0] _RAND_137;
  reg [31:0] _RAND_138;
  reg [31:0] _RAND_139;
  reg [31:0] _RAND_140;
  reg [31:0] _RAND_141;
  reg [31:0] _RAND_142;
  reg [31:0] _RAND_143;
  reg [31:0] _RAND_144;
  reg [31:0] _RAND_145;
  reg [31:0] _RAND_146;
  reg [31:0] _RAND_147;
  reg [31:0] _RAND_148;
  reg [31:0] _RAND_149;
  reg [31:0] _RAND_150;
  reg [31:0] _RAND_151;
  reg [31:0] _RAND_152;
  reg [31:0] _RAND_153;
  reg [31:0] _RAND_154;
  reg [31:0] _RAND_155;
  reg [31:0] _RAND_156;
  reg [31:0] _RAND_157;
  reg [31:0] _RAND_158;
  reg [31:0] _RAND_159;
  reg [31:0] _RAND_160;
  reg [31:0] _RAND_161;
  reg [31:0] _RAND_162;
  reg [31:0] _RAND_163;
  reg [31:0] _RAND_164;
  reg [31:0] _RAND_165;
  reg [31:0] _RAND_166;
  reg [31:0] _RAND_167;
  reg [31:0] _RAND_168;
  reg [31:0] _RAND_169;
  reg [31:0] _RAND_170;
  reg [31:0] _RAND_171;
  reg [31:0] _RAND_172;
  reg [31:0] _RAND_173;
  reg [31:0] _RAND_174;
  reg [31:0] _RAND_175;
  reg [31:0] _RAND_176;
  reg [31:0] _RAND_177;
  reg [31:0] _RAND_178;
  reg [31:0] _RAND_179;
  reg [31:0] _RAND_180;
  reg [31:0] _RAND_181;
  reg [31:0] _RAND_182;
  reg [31:0] _RAND_183;
  reg [31:0] _RAND_184;
  reg [31:0] _RAND_185;
  reg [31:0] _RAND_186;
  reg [31:0] _RAND_187;
  reg [31:0] _RAND_188;
  reg [31:0] _RAND_189;
  reg [31:0] _RAND_190;
  reg [31:0] _RAND_191;
  reg [31:0] _RAND_192;
  reg [31:0] _RAND_193;
  reg [31:0] _RAND_194;
  reg [31:0] _RAND_195;
  reg [31:0] _RAND_196;
  reg [31:0] _RAND_197;
  reg [31:0] _RAND_198;
  reg [31:0] _RAND_199;
  reg [31:0] _RAND_200;
  reg [31:0] _RAND_201;
  reg [31:0] _RAND_202;
  reg [31:0] _RAND_203;
  reg [31:0] _RAND_204;
  reg [31:0] _RAND_205;
  reg [31:0] _RAND_206;
  reg [31:0] _RAND_207;
  reg [31:0] _RAND_208;
  reg [31:0] _RAND_209;
  reg [31:0] _RAND_210;
  reg [31:0] _RAND_211;
  reg [31:0] _RAND_212;
  reg [31:0] _RAND_213;
  reg [31:0] _RAND_214;
  reg [31:0] _RAND_215;
  reg [31:0] _RAND_216;
  reg [31:0] _RAND_217;
  reg [31:0] _RAND_218;
  reg [31:0] _RAND_219;
  reg [31:0] _RAND_220;
  reg [31:0] _RAND_221;
  reg [31:0] _RAND_222;
  reg [31:0] _RAND_223;
  reg [31:0] _RAND_224;
  reg [31:0] _RAND_225;
  reg [31:0] _RAND_226;
  reg [31:0] _RAND_227;
  reg [31:0] _RAND_228;
  reg [31:0] _RAND_229;
  reg [31:0] _RAND_230;
  reg [31:0] _RAND_231;
  reg [31:0] _RAND_232;
  reg [31:0] _RAND_233;
  reg [31:0] _RAND_234;
  reg [31:0] _RAND_235;
  reg [31:0] _RAND_236;
  reg [31:0] _RAND_237;
  reg [31:0] _RAND_238;
  reg [31:0] _RAND_239;
  reg [31:0] _RAND_240;
  reg [31:0] _RAND_241;
  reg [31:0] _RAND_242;
  reg [31:0] _RAND_243;
  reg [31:0] _RAND_244;
  reg [31:0] _RAND_245;
  reg [31:0] _RAND_246;
  reg [31:0] _RAND_247;
  reg [31:0] _RAND_248;
  reg [31:0] _RAND_249;
  reg [31:0] _RAND_250;
  reg [31:0] _RAND_251;
  reg [31:0] _RAND_252;
  reg [31:0] _RAND_253;
  reg [31:0] _RAND_254;
  reg [31:0] _RAND_255;
  reg [31:0] _RAND_256;
  reg [31:0] _RAND_257;
  reg [31:0] _RAND_258;
  reg [31:0] _RAND_259;
  reg [31:0] _RAND_260;
  reg [31:0] _RAND_261;
  reg [31:0] _RAND_262;
  reg [31:0] _RAND_263;
  reg [31:0] _RAND_264;
  reg [31:0] _RAND_265;
  reg [31:0] _RAND_266;
  reg [31:0] _RAND_267;
  reg [31:0] _RAND_268;
  reg [31:0] _RAND_269;
  reg [31:0] _RAND_270;
  reg [31:0] _RAND_271;
  reg [31:0] _RAND_272;
  reg [31:0] _RAND_273;
  reg [31:0] _RAND_274;
  reg [31:0] _RAND_275;
  reg [31:0] _RAND_276;
  reg [31:0] _RAND_277;
  reg [31:0] _RAND_278;
  reg [31:0] _RAND_279;
  reg [31:0] _RAND_280;
  reg [31:0] _RAND_281;
  reg [31:0] _RAND_282;
  reg [31:0] _RAND_283;
  reg [31:0] _RAND_284;
  reg [31:0] _RAND_285;
  reg [31:0] _RAND_286;
  reg [31:0] _RAND_287;
  reg [31:0] _RAND_288;
  reg [31:0] _RAND_289;
  reg [31:0] _RAND_290;
  reg [31:0] _RAND_291;
  reg [31:0] _RAND_292;
  reg [31:0] _RAND_293;
  reg [31:0] _RAND_294;
  reg [31:0] _RAND_295;
  reg [31:0] _RAND_296;
  reg [31:0] _RAND_297;
  reg [31:0] _RAND_298;
  reg [31:0] _RAND_299;
  reg [31:0] _RAND_300;
  reg [31:0] _RAND_301;
  reg [31:0] _RAND_302;
  reg [31:0] _RAND_303;
  reg [31:0] _RAND_304;
  reg [31:0] _RAND_305;
  reg [31:0] _RAND_306;
  reg [31:0] _RAND_307;
  reg [31:0] _RAND_308;
  reg [31:0] _RAND_309;
  reg [31:0] _RAND_310;
  reg [31:0] _RAND_311;
  reg [31:0] _RAND_312;
  reg [31:0] _RAND_313;
  reg [31:0] _RAND_314;
  reg [31:0] _RAND_315;
  reg [31:0] _RAND_316;
  reg [31:0] _RAND_317;
  reg [31:0] _RAND_318;
  reg [31:0] _RAND_319;
  reg [31:0] _RAND_320;
  reg [31:0] _RAND_321;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  stalls_a_sel = auto_in_a_bits_source <= 9'h13f; // @[Parameters.scala 57:20]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg  flight_0; // @[FIFOFixer.scala 71:27]
  reg  flight_1; // @[FIFOFixer.scala 71:27]
  reg  flight_2; // @[FIFOFixer.scala 71:27]
  reg  flight_3; // @[FIFOFixer.scala 71:27]
  reg  flight_4; // @[FIFOFixer.scala 71:27]
  reg  flight_5; // @[FIFOFixer.scala 71:27]
  reg  flight_6; // @[FIFOFixer.scala 71:27]
  reg  flight_7; // @[FIFOFixer.scala 71:27]
  reg  flight_8; // @[FIFOFixer.scala 71:27]
  reg  flight_9; // @[FIFOFixer.scala 71:27]
  reg  flight_10; // @[FIFOFixer.scala 71:27]
  reg  flight_11; // @[FIFOFixer.scala 71:27]
  reg  flight_12; // @[FIFOFixer.scala 71:27]
  reg  flight_13; // @[FIFOFixer.scala 71:27]
  reg  flight_14; // @[FIFOFixer.scala 71:27]
  reg  flight_15; // @[FIFOFixer.scala 71:27]
  reg  flight_16; // @[FIFOFixer.scala 71:27]
  reg  flight_17; // @[FIFOFixer.scala 71:27]
  reg  flight_18; // @[FIFOFixer.scala 71:27]
  reg  flight_19; // @[FIFOFixer.scala 71:27]
  reg  flight_20; // @[FIFOFixer.scala 71:27]
  reg  flight_21; // @[FIFOFixer.scala 71:27]
  reg  flight_22; // @[FIFOFixer.scala 71:27]
  reg  flight_23; // @[FIFOFixer.scala 71:27]
  reg  flight_24; // @[FIFOFixer.scala 71:27]
  reg  flight_25; // @[FIFOFixer.scala 71:27]
  reg  flight_26; // @[FIFOFixer.scala 71:27]
  reg  flight_27; // @[FIFOFixer.scala 71:27]
  reg  flight_28; // @[FIFOFixer.scala 71:27]
  reg  flight_29; // @[FIFOFixer.scala 71:27]
  reg  flight_30; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_30 = flight_0 | flight_1 | flight_2 | flight_3 | flight_4 | flight_5 | flight_6 | flight_7 | flight_8
     | flight_9 | flight_10 | flight_11 | flight_12 | flight_13 | flight_14 | flight_15 | flight_16 | flight_17 |
    flight_18 | flight_19 | flight_20 | flight_21 | flight_22 | flight_23 | flight_24 | flight_25 | flight_26 |
    flight_27 | flight_28 | flight_29 | flight_30; // @[FIFOFixer.scala 80:44]
  reg  flight_31; // @[FIFOFixer.scala 71:27]
  reg  flight_32; // @[FIFOFixer.scala 71:27]
  reg  flight_33; // @[FIFOFixer.scala 71:27]
  reg  flight_34; // @[FIFOFixer.scala 71:27]
  reg  flight_35; // @[FIFOFixer.scala 71:27]
  reg  flight_36; // @[FIFOFixer.scala 71:27]
  reg  flight_37; // @[FIFOFixer.scala 71:27]
  reg  flight_38; // @[FIFOFixer.scala 71:27]
  reg  flight_39; // @[FIFOFixer.scala 71:27]
  reg  flight_40; // @[FIFOFixer.scala 71:27]
  reg  flight_41; // @[FIFOFixer.scala 71:27]
  reg  flight_42; // @[FIFOFixer.scala 71:27]
  reg  flight_43; // @[FIFOFixer.scala 71:27]
  reg  flight_44; // @[FIFOFixer.scala 71:27]
  reg  flight_45; // @[FIFOFixer.scala 71:27]
  reg  flight_46; // @[FIFOFixer.scala 71:27]
  reg  flight_47; // @[FIFOFixer.scala 71:27]
  reg  flight_48; // @[FIFOFixer.scala 71:27]
  reg  flight_49; // @[FIFOFixer.scala 71:27]
  reg  flight_50; // @[FIFOFixer.scala 71:27]
  reg  flight_51; // @[FIFOFixer.scala 71:27]
  reg  flight_52; // @[FIFOFixer.scala 71:27]
  reg  flight_53; // @[FIFOFixer.scala 71:27]
  reg  flight_54; // @[FIFOFixer.scala 71:27]
  reg  flight_55; // @[FIFOFixer.scala 71:27]
  reg  flight_56; // @[FIFOFixer.scala 71:27]
  reg  flight_57; // @[FIFOFixer.scala 71:27]
  reg  flight_58; // @[FIFOFixer.scala 71:27]
  reg  flight_59; // @[FIFOFixer.scala 71:27]
  reg  flight_60; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_60 = _stalls_T_30 | flight_31 | flight_32 | flight_33 | flight_34 | flight_35 | flight_36 | flight_37
     | flight_38 | flight_39 | flight_40 | flight_41 | flight_42 | flight_43 | flight_44 | flight_45 | flight_46 |
    flight_47 | flight_48 | flight_49 | flight_50 | flight_51 | flight_52 | flight_53 | flight_54 | flight_55 |
    flight_56 | flight_57 | flight_58 | flight_59 | flight_60; // @[FIFOFixer.scala 80:44]
  reg  flight_61; // @[FIFOFixer.scala 71:27]
  reg  flight_62; // @[FIFOFixer.scala 71:27]
  reg  flight_63; // @[FIFOFixer.scala 71:27]
  reg  flight_64; // @[FIFOFixer.scala 71:27]
  reg  flight_65; // @[FIFOFixer.scala 71:27]
  reg  flight_66; // @[FIFOFixer.scala 71:27]
  reg  flight_67; // @[FIFOFixer.scala 71:27]
  reg  flight_68; // @[FIFOFixer.scala 71:27]
  reg  flight_69; // @[FIFOFixer.scala 71:27]
  reg  flight_70; // @[FIFOFixer.scala 71:27]
  reg  flight_71; // @[FIFOFixer.scala 71:27]
  reg  flight_72; // @[FIFOFixer.scala 71:27]
  reg  flight_73; // @[FIFOFixer.scala 71:27]
  reg  flight_74; // @[FIFOFixer.scala 71:27]
  reg  flight_75; // @[FIFOFixer.scala 71:27]
  reg  flight_76; // @[FIFOFixer.scala 71:27]
  reg  flight_77; // @[FIFOFixer.scala 71:27]
  reg  flight_78; // @[FIFOFixer.scala 71:27]
  reg  flight_79; // @[FIFOFixer.scala 71:27]
  reg  flight_80; // @[FIFOFixer.scala 71:27]
  reg  flight_81; // @[FIFOFixer.scala 71:27]
  reg  flight_82; // @[FIFOFixer.scala 71:27]
  reg  flight_83; // @[FIFOFixer.scala 71:27]
  reg  flight_84; // @[FIFOFixer.scala 71:27]
  reg  flight_85; // @[FIFOFixer.scala 71:27]
  reg  flight_86; // @[FIFOFixer.scala 71:27]
  reg  flight_87; // @[FIFOFixer.scala 71:27]
  reg  flight_88; // @[FIFOFixer.scala 71:27]
  reg  flight_89; // @[FIFOFixer.scala 71:27]
  reg  flight_90; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_90 = _stalls_T_60 | flight_61 | flight_62 | flight_63 | flight_64 | flight_65 | flight_66 | flight_67
     | flight_68 | flight_69 | flight_70 | flight_71 | flight_72 | flight_73 | flight_74 | flight_75 | flight_76 |
    flight_77 | flight_78 | flight_79 | flight_80 | flight_81 | flight_82 | flight_83 | flight_84 | flight_85 |
    flight_86 | flight_87 | flight_88 | flight_89 | flight_90; // @[FIFOFixer.scala 80:44]
  reg  flight_91; // @[FIFOFixer.scala 71:27]
  reg  flight_92; // @[FIFOFixer.scala 71:27]
  reg  flight_93; // @[FIFOFixer.scala 71:27]
  reg  flight_94; // @[FIFOFixer.scala 71:27]
  reg  flight_95; // @[FIFOFixer.scala 71:27]
  reg  flight_96; // @[FIFOFixer.scala 71:27]
  reg  flight_97; // @[FIFOFixer.scala 71:27]
  reg  flight_98; // @[FIFOFixer.scala 71:27]
  reg  flight_99; // @[FIFOFixer.scala 71:27]
  reg  flight_100; // @[FIFOFixer.scala 71:27]
  reg  flight_101; // @[FIFOFixer.scala 71:27]
  reg  flight_102; // @[FIFOFixer.scala 71:27]
  reg  flight_103; // @[FIFOFixer.scala 71:27]
  reg  flight_104; // @[FIFOFixer.scala 71:27]
  reg  flight_105; // @[FIFOFixer.scala 71:27]
  reg  flight_106; // @[FIFOFixer.scala 71:27]
  reg  flight_107; // @[FIFOFixer.scala 71:27]
  reg  flight_108; // @[FIFOFixer.scala 71:27]
  reg  flight_109; // @[FIFOFixer.scala 71:27]
  reg  flight_110; // @[FIFOFixer.scala 71:27]
  reg  flight_111; // @[FIFOFixer.scala 71:27]
  reg  flight_112; // @[FIFOFixer.scala 71:27]
  reg  flight_113; // @[FIFOFixer.scala 71:27]
  reg  flight_114; // @[FIFOFixer.scala 71:27]
  reg  flight_115; // @[FIFOFixer.scala 71:27]
  reg  flight_116; // @[FIFOFixer.scala 71:27]
  reg  flight_117; // @[FIFOFixer.scala 71:27]
  reg  flight_118; // @[FIFOFixer.scala 71:27]
  reg  flight_119; // @[FIFOFixer.scala 71:27]
  reg  flight_120; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_120 = _stalls_T_90 | flight_91 | flight_92 | flight_93 | flight_94 | flight_95 | flight_96 | flight_97
     | flight_98 | flight_99 | flight_100 | flight_101 | flight_102 | flight_103 | flight_104 | flight_105 | flight_106
     | flight_107 | flight_108 | flight_109 | flight_110 | flight_111 | flight_112 | flight_113 | flight_114 |
    flight_115 | flight_116 | flight_117 | flight_118 | flight_119 | flight_120; // @[FIFOFixer.scala 80:44]
  reg  flight_121; // @[FIFOFixer.scala 71:27]
  reg  flight_122; // @[FIFOFixer.scala 71:27]
  reg  flight_123; // @[FIFOFixer.scala 71:27]
  reg  flight_124; // @[FIFOFixer.scala 71:27]
  reg  flight_125; // @[FIFOFixer.scala 71:27]
  reg  flight_126; // @[FIFOFixer.scala 71:27]
  reg  flight_127; // @[FIFOFixer.scala 71:27]
  reg  flight_128; // @[FIFOFixer.scala 71:27]
  reg  flight_129; // @[FIFOFixer.scala 71:27]
  reg  flight_130; // @[FIFOFixer.scala 71:27]
  reg  flight_131; // @[FIFOFixer.scala 71:27]
  reg  flight_132; // @[FIFOFixer.scala 71:27]
  reg  flight_133; // @[FIFOFixer.scala 71:27]
  reg  flight_134; // @[FIFOFixer.scala 71:27]
  reg  flight_135; // @[FIFOFixer.scala 71:27]
  reg  flight_136; // @[FIFOFixer.scala 71:27]
  reg  flight_137; // @[FIFOFixer.scala 71:27]
  reg  flight_138; // @[FIFOFixer.scala 71:27]
  reg  flight_139; // @[FIFOFixer.scala 71:27]
  reg  flight_140; // @[FIFOFixer.scala 71:27]
  reg  flight_141; // @[FIFOFixer.scala 71:27]
  reg  flight_142; // @[FIFOFixer.scala 71:27]
  reg  flight_143; // @[FIFOFixer.scala 71:27]
  reg  flight_144; // @[FIFOFixer.scala 71:27]
  reg  flight_145; // @[FIFOFixer.scala 71:27]
  reg  flight_146; // @[FIFOFixer.scala 71:27]
  reg  flight_147; // @[FIFOFixer.scala 71:27]
  reg  flight_148; // @[FIFOFixer.scala 71:27]
  reg  flight_149; // @[FIFOFixer.scala 71:27]
  reg  flight_150; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_150 = _stalls_T_120 | flight_121 | flight_122 | flight_123 | flight_124 | flight_125 | flight_126 |
    flight_127 | flight_128 | flight_129 | flight_130 | flight_131 | flight_132 | flight_133 | flight_134 | flight_135
     | flight_136 | flight_137 | flight_138 | flight_139 | flight_140 | flight_141 | flight_142 | flight_143 |
    flight_144 | flight_145 | flight_146 | flight_147 | flight_148 | flight_149 | flight_150; // @[FIFOFixer.scala 80:44]
  reg  flight_151; // @[FIFOFixer.scala 71:27]
  reg  flight_152; // @[FIFOFixer.scala 71:27]
  reg  flight_153; // @[FIFOFixer.scala 71:27]
  reg  flight_154; // @[FIFOFixer.scala 71:27]
  reg  flight_155; // @[FIFOFixer.scala 71:27]
  reg  flight_156; // @[FIFOFixer.scala 71:27]
  reg  flight_157; // @[FIFOFixer.scala 71:27]
  reg  flight_158; // @[FIFOFixer.scala 71:27]
  reg  flight_159; // @[FIFOFixer.scala 71:27]
  reg  flight_160; // @[FIFOFixer.scala 71:27]
  reg  flight_161; // @[FIFOFixer.scala 71:27]
  reg  flight_162; // @[FIFOFixer.scala 71:27]
  reg  flight_163; // @[FIFOFixer.scala 71:27]
  reg  flight_164; // @[FIFOFixer.scala 71:27]
  reg  flight_165; // @[FIFOFixer.scala 71:27]
  reg  flight_166; // @[FIFOFixer.scala 71:27]
  reg  flight_167; // @[FIFOFixer.scala 71:27]
  reg  flight_168; // @[FIFOFixer.scala 71:27]
  reg  flight_169; // @[FIFOFixer.scala 71:27]
  reg  flight_170; // @[FIFOFixer.scala 71:27]
  reg  flight_171; // @[FIFOFixer.scala 71:27]
  reg  flight_172; // @[FIFOFixer.scala 71:27]
  reg  flight_173; // @[FIFOFixer.scala 71:27]
  reg  flight_174; // @[FIFOFixer.scala 71:27]
  reg  flight_175; // @[FIFOFixer.scala 71:27]
  reg  flight_176; // @[FIFOFixer.scala 71:27]
  reg  flight_177; // @[FIFOFixer.scala 71:27]
  reg  flight_178; // @[FIFOFixer.scala 71:27]
  reg  flight_179; // @[FIFOFixer.scala 71:27]
  reg  flight_180; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_180 = _stalls_T_150 | flight_151 | flight_152 | flight_153 | flight_154 | flight_155 | flight_156 |
    flight_157 | flight_158 | flight_159 | flight_160 | flight_161 | flight_162 | flight_163 | flight_164 | flight_165
     | flight_166 | flight_167 | flight_168 | flight_169 | flight_170 | flight_171 | flight_172 | flight_173 |
    flight_174 | flight_175 | flight_176 | flight_177 | flight_178 | flight_179 | flight_180; // @[FIFOFixer.scala 80:44]
  reg  flight_181; // @[FIFOFixer.scala 71:27]
  reg  flight_182; // @[FIFOFixer.scala 71:27]
  reg  flight_183; // @[FIFOFixer.scala 71:27]
  reg  flight_184; // @[FIFOFixer.scala 71:27]
  reg  flight_185; // @[FIFOFixer.scala 71:27]
  reg  flight_186; // @[FIFOFixer.scala 71:27]
  reg  flight_187; // @[FIFOFixer.scala 71:27]
  reg  flight_188; // @[FIFOFixer.scala 71:27]
  reg  flight_189; // @[FIFOFixer.scala 71:27]
  reg  flight_190; // @[FIFOFixer.scala 71:27]
  reg  flight_191; // @[FIFOFixer.scala 71:27]
  reg  flight_192; // @[FIFOFixer.scala 71:27]
  reg  flight_193; // @[FIFOFixer.scala 71:27]
  reg  flight_194; // @[FIFOFixer.scala 71:27]
  reg  flight_195; // @[FIFOFixer.scala 71:27]
  reg  flight_196; // @[FIFOFixer.scala 71:27]
  reg  flight_197; // @[FIFOFixer.scala 71:27]
  reg  flight_198; // @[FIFOFixer.scala 71:27]
  reg  flight_199; // @[FIFOFixer.scala 71:27]
  reg  flight_200; // @[FIFOFixer.scala 71:27]
  reg  flight_201; // @[FIFOFixer.scala 71:27]
  reg  flight_202; // @[FIFOFixer.scala 71:27]
  reg  flight_203; // @[FIFOFixer.scala 71:27]
  reg  flight_204; // @[FIFOFixer.scala 71:27]
  reg  flight_205; // @[FIFOFixer.scala 71:27]
  reg  flight_206; // @[FIFOFixer.scala 71:27]
  reg  flight_207; // @[FIFOFixer.scala 71:27]
  reg  flight_208; // @[FIFOFixer.scala 71:27]
  reg  flight_209; // @[FIFOFixer.scala 71:27]
  reg  flight_210; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_210 = _stalls_T_180 | flight_181 | flight_182 | flight_183 | flight_184 | flight_185 | flight_186 |
    flight_187 | flight_188 | flight_189 | flight_190 | flight_191 | flight_192 | flight_193 | flight_194 | flight_195
     | flight_196 | flight_197 | flight_198 | flight_199 | flight_200 | flight_201 | flight_202 | flight_203 |
    flight_204 | flight_205 | flight_206 | flight_207 | flight_208 | flight_209 | flight_210; // @[FIFOFixer.scala 80:44]
  reg  flight_211; // @[FIFOFixer.scala 71:27]
  reg  flight_212; // @[FIFOFixer.scala 71:27]
  reg  flight_213; // @[FIFOFixer.scala 71:27]
  reg  flight_214; // @[FIFOFixer.scala 71:27]
  reg  flight_215; // @[FIFOFixer.scala 71:27]
  reg  flight_216; // @[FIFOFixer.scala 71:27]
  reg  flight_217; // @[FIFOFixer.scala 71:27]
  reg  flight_218; // @[FIFOFixer.scala 71:27]
  reg  flight_219; // @[FIFOFixer.scala 71:27]
  reg  flight_220; // @[FIFOFixer.scala 71:27]
  reg  flight_221; // @[FIFOFixer.scala 71:27]
  reg  flight_222; // @[FIFOFixer.scala 71:27]
  reg  flight_223; // @[FIFOFixer.scala 71:27]
  reg  flight_224; // @[FIFOFixer.scala 71:27]
  reg  flight_225; // @[FIFOFixer.scala 71:27]
  reg  flight_226; // @[FIFOFixer.scala 71:27]
  reg  flight_227; // @[FIFOFixer.scala 71:27]
  reg  flight_228; // @[FIFOFixer.scala 71:27]
  reg  flight_229; // @[FIFOFixer.scala 71:27]
  reg  flight_230; // @[FIFOFixer.scala 71:27]
  reg  flight_231; // @[FIFOFixer.scala 71:27]
  reg  flight_232; // @[FIFOFixer.scala 71:27]
  reg  flight_233; // @[FIFOFixer.scala 71:27]
  reg  flight_234; // @[FIFOFixer.scala 71:27]
  reg  flight_235; // @[FIFOFixer.scala 71:27]
  reg  flight_236; // @[FIFOFixer.scala 71:27]
  reg  flight_237; // @[FIFOFixer.scala 71:27]
  reg  flight_238; // @[FIFOFixer.scala 71:27]
  reg  flight_239; // @[FIFOFixer.scala 71:27]
  reg  flight_240; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_240 = _stalls_T_210 | flight_211 | flight_212 | flight_213 | flight_214 | flight_215 | flight_216 |
    flight_217 | flight_218 | flight_219 | flight_220 | flight_221 | flight_222 | flight_223 | flight_224 | flight_225
     | flight_226 | flight_227 | flight_228 | flight_229 | flight_230 | flight_231 | flight_232 | flight_233 |
    flight_234 | flight_235 | flight_236 | flight_237 | flight_238 | flight_239 | flight_240; // @[FIFOFixer.scala 80:44]
  reg  flight_241; // @[FIFOFixer.scala 71:27]
  reg  flight_242; // @[FIFOFixer.scala 71:27]
  reg  flight_243; // @[FIFOFixer.scala 71:27]
  reg  flight_244; // @[FIFOFixer.scala 71:27]
  reg  flight_245; // @[FIFOFixer.scala 71:27]
  reg  flight_246; // @[FIFOFixer.scala 71:27]
  reg  flight_247; // @[FIFOFixer.scala 71:27]
  reg  flight_248; // @[FIFOFixer.scala 71:27]
  reg  flight_249; // @[FIFOFixer.scala 71:27]
  reg  flight_250; // @[FIFOFixer.scala 71:27]
  reg  flight_251; // @[FIFOFixer.scala 71:27]
  reg  flight_252; // @[FIFOFixer.scala 71:27]
  reg  flight_253; // @[FIFOFixer.scala 71:27]
  reg  flight_254; // @[FIFOFixer.scala 71:27]
  reg  flight_255; // @[FIFOFixer.scala 71:27]
  reg  flight_256; // @[FIFOFixer.scala 71:27]
  reg  flight_257; // @[FIFOFixer.scala 71:27]
  reg  flight_258; // @[FIFOFixer.scala 71:27]
  reg  flight_259; // @[FIFOFixer.scala 71:27]
  reg  flight_260; // @[FIFOFixer.scala 71:27]
  reg  flight_261; // @[FIFOFixer.scala 71:27]
  reg  flight_262; // @[FIFOFixer.scala 71:27]
  reg  flight_263; // @[FIFOFixer.scala 71:27]
  reg  flight_264; // @[FIFOFixer.scala 71:27]
  reg  flight_265; // @[FIFOFixer.scala 71:27]
  reg  flight_266; // @[FIFOFixer.scala 71:27]
  reg  flight_267; // @[FIFOFixer.scala 71:27]
  reg  flight_268; // @[FIFOFixer.scala 71:27]
  reg  flight_269; // @[FIFOFixer.scala 71:27]
  reg  flight_270; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_270 = _stalls_T_240 | flight_241 | flight_242 | flight_243 | flight_244 | flight_245 | flight_246 |
    flight_247 | flight_248 | flight_249 | flight_250 | flight_251 | flight_252 | flight_253 | flight_254 | flight_255
     | flight_256 | flight_257 | flight_258 | flight_259 | flight_260 | flight_261 | flight_262 | flight_263 |
    flight_264 | flight_265 | flight_266 | flight_267 | flight_268 | flight_269 | flight_270; // @[FIFOFixer.scala 80:44]
  reg  flight_271; // @[FIFOFixer.scala 71:27]
  reg  flight_272; // @[FIFOFixer.scala 71:27]
  reg  flight_273; // @[FIFOFixer.scala 71:27]
  reg  flight_274; // @[FIFOFixer.scala 71:27]
  reg  flight_275; // @[FIFOFixer.scala 71:27]
  reg  flight_276; // @[FIFOFixer.scala 71:27]
  reg  flight_277; // @[FIFOFixer.scala 71:27]
  reg  flight_278; // @[FIFOFixer.scala 71:27]
  reg  flight_279; // @[FIFOFixer.scala 71:27]
  reg  flight_280; // @[FIFOFixer.scala 71:27]
  reg  flight_281; // @[FIFOFixer.scala 71:27]
  reg  flight_282; // @[FIFOFixer.scala 71:27]
  reg  flight_283; // @[FIFOFixer.scala 71:27]
  reg  flight_284; // @[FIFOFixer.scala 71:27]
  reg  flight_285; // @[FIFOFixer.scala 71:27]
  reg  flight_286; // @[FIFOFixer.scala 71:27]
  reg  flight_287; // @[FIFOFixer.scala 71:27]
  reg  flight_288; // @[FIFOFixer.scala 71:27]
  reg  flight_289; // @[FIFOFixer.scala 71:27]
  reg  flight_290; // @[FIFOFixer.scala 71:27]
  reg  flight_291; // @[FIFOFixer.scala 71:27]
  reg  flight_292; // @[FIFOFixer.scala 71:27]
  reg  flight_293; // @[FIFOFixer.scala 71:27]
  reg  flight_294; // @[FIFOFixer.scala 71:27]
  reg  flight_295; // @[FIFOFixer.scala 71:27]
  reg  flight_296; // @[FIFOFixer.scala 71:27]
  reg  flight_297; // @[FIFOFixer.scala 71:27]
  reg  flight_298; // @[FIFOFixer.scala 71:27]
  reg  flight_299; // @[FIFOFixer.scala 71:27]
  reg  flight_300; // @[FIFOFixer.scala 71:27]
  wire  _stalls_T_300 = _stalls_T_270 | flight_271 | flight_272 | flight_273 | flight_274 | flight_275 | flight_276 |
    flight_277 | flight_278 | flight_279 | flight_280 | flight_281 | flight_282 | flight_283 | flight_284 | flight_285
     | flight_286 | flight_287 | flight_288 | flight_289 | flight_290 | flight_291 | flight_292 | flight_293 |
    flight_294 | flight_295 | flight_296 | flight_297 | flight_298 | flight_299 | flight_300; // @[FIFOFixer.scala 80:44]
  reg  flight_301; // @[FIFOFixer.scala 71:27]
  reg  flight_302; // @[FIFOFixer.scala 71:27]
  reg  flight_303; // @[FIFOFixer.scala 71:27]
  reg  flight_304; // @[FIFOFixer.scala 71:27]
  reg  flight_305; // @[FIFOFixer.scala 71:27]
  reg  flight_306; // @[FIFOFixer.scala 71:27]
  reg  flight_307; // @[FIFOFixer.scala 71:27]
  reg  flight_308; // @[FIFOFixer.scala 71:27]
  reg  flight_309; // @[FIFOFixer.scala 71:27]
  reg  flight_310; // @[FIFOFixer.scala 71:27]
  reg  flight_311; // @[FIFOFixer.scala 71:27]
  reg  flight_312; // @[FIFOFixer.scala 71:27]
  reg  flight_313; // @[FIFOFixer.scala 71:27]
  reg  flight_314; // @[FIFOFixer.scala 71:27]
  reg  flight_315; // @[FIFOFixer.scala 71:27]
  reg  flight_316; // @[FIFOFixer.scala 71:27]
  reg  flight_317; // @[FIFOFixer.scala 71:27]
  reg  flight_318; // @[FIFOFixer.scala 71:27]
  reg  flight_319; // @[FIFOFixer.scala 71:27]
  wire  stalls_0 = stalls_a_sel & a_first & (_stalls_T_300 | flight_301 | flight_302 | flight_303 | flight_304 |
    flight_305 | flight_306 | flight_307 | flight_308 | flight_309 | flight_310 | flight_311 | flight_312 | flight_313
     | flight_314 | flight_315 | flight_316 | flight_317 | flight_318 | flight_319); // @[FIFOFixer.scala 80:26]
  wire  _bundleIn_0_a_ready_T = ~stalls_0; // @[FIFOFixer.scala 88:50]
  wire  bundleIn_0_a_ready = auto_out_a_ready & ~stalls_0; // @[FIFOFixer.scala 88:33]
  wire  _a_first_T = bundleIn_0_a_ready & auto_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  _d_first_T = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 52:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_first = ~d_first_counter; // @[Edges.scala 230:25]
  wire  d_first = d_first_first & auto_out_d_bits_opcode != 3'h6; // @[FIFOFixer.scala 67:42]
  wire  _GEN_322 = a_first & _a_first_T ? 9'h0 == auto_in_a_bits_source | flight_0 : flight_0; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_323 = a_first & _a_first_T ? 9'h1 == auto_in_a_bits_source | flight_1 : flight_1; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_324 = a_first & _a_first_T ? 9'h2 == auto_in_a_bits_source | flight_2 : flight_2; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_325 = a_first & _a_first_T ? 9'h3 == auto_in_a_bits_source | flight_3 : flight_3; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_326 = a_first & _a_first_T ? 9'h4 == auto_in_a_bits_source | flight_4 : flight_4; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_327 = a_first & _a_first_T ? 9'h5 == auto_in_a_bits_source | flight_5 : flight_5; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_328 = a_first & _a_first_T ? 9'h6 == auto_in_a_bits_source | flight_6 : flight_6; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_329 = a_first & _a_first_T ? 9'h7 == auto_in_a_bits_source | flight_7 : flight_7; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_330 = a_first & _a_first_T ? 9'h8 == auto_in_a_bits_source | flight_8 : flight_8; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_331 = a_first & _a_first_T ? 9'h9 == auto_in_a_bits_source | flight_9 : flight_9; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_332 = a_first & _a_first_T ? 9'ha == auto_in_a_bits_source | flight_10 : flight_10; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_333 = a_first & _a_first_T ? 9'hb == auto_in_a_bits_source | flight_11 : flight_11; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_334 = a_first & _a_first_T ? 9'hc == auto_in_a_bits_source | flight_12 : flight_12; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_335 = a_first & _a_first_T ? 9'hd == auto_in_a_bits_source | flight_13 : flight_13; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_336 = a_first & _a_first_T ? 9'he == auto_in_a_bits_source | flight_14 : flight_14; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_337 = a_first & _a_first_T ? 9'hf == auto_in_a_bits_source | flight_15 : flight_15; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_338 = a_first & _a_first_T ? 9'h10 == auto_in_a_bits_source | flight_16 : flight_16; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_339 = a_first & _a_first_T ? 9'h11 == auto_in_a_bits_source | flight_17 : flight_17; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_340 = a_first & _a_first_T ? 9'h12 == auto_in_a_bits_source | flight_18 : flight_18; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_341 = a_first & _a_first_T ? 9'h13 == auto_in_a_bits_source | flight_19 : flight_19; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_342 = a_first & _a_first_T ? 9'h14 == auto_in_a_bits_source | flight_20 : flight_20; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_343 = a_first & _a_first_T ? 9'h15 == auto_in_a_bits_source | flight_21 : flight_21; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_344 = a_first & _a_first_T ? 9'h16 == auto_in_a_bits_source | flight_22 : flight_22; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_345 = a_first & _a_first_T ? 9'h17 == auto_in_a_bits_source | flight_23 : flight_23; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_346 = a_first & _a_first_T ? 9'h18 == auto_in_a_bits_source | flight_24 : flight_24; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_347 = a_first & _a_first_T ? 9'h19 == auto_in_a_bits_source | flight_25 : flight_25; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_348 = a_first & _a_first_T ? 9'h1a == auto_in_a_bits_source | flight_26 : flight_26; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_349 = a_first & _a_first_T ? 9'h1b == auto_in_a_bits_source | flight_27 : flight_27; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_350 = a_first & _a_first_T ? 9'h1c == auto_in_a_bits_source | flight_28 : flight_28; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_351 = a_first & _a_first_T ? 9'h1d == auto_in_a_bits_source | flight_29 : flight_29; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_352 = a_first & _a_first_T ? 9'h1e == auto_in_a_bits_source | flight_30 : flight_30; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_353 = a_first & _a_first_T ? 9'h1f == auto_in_a_bits_source | flight_31 : flight_31; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_354 = a_first & _a_first_T ? 9'h20 == auto_in_a_bits_source | flight_32 : flight_32; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_355 = a_first & _a_first_T ? 9'h21 == auto_in_a_bits_source | flight_33 : flight_33; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_356 = a_first & _a_first_T ? 9'h22 == auto_in_a_bits_source | flight_34 : flight_34; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_357 = a_first & _a_first_T ? 9'h23 == auto_in_a_bits_source | flight_35 : flight_35; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_358 = a_first & _a_first_T ? 9'h24 == auto_in_a_bits_source | flight_36 : flight_36; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_359 = a_first & _a_first_T ? 9'h25 == auto_in_a_bits_source | flight_37 : flight_37; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_360 = a_first & _a_first_T ? 9'h26 == auto_in_a_bits_source | flight_38 : flight_38; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_361 = a_first & _a_first_T ? 9'h27 == auto_in_a_bits_source | flight_39 : flight_39; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_362 = a_first & _a_first_T ? 9'h28 == auto_in_a_bits_source | flight_40 : flight_40; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_363 = a_first & _a_first_T ? 9'h29 == auto_in_a_bits_source | flight_41 : flight_41; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_364 = a_first & _a_first_T ? 9'h2a == auto_in_a_bits_source | flight_42 : flight_42; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_365 = a_first & _a_first_T ? 9'h2b == auto_in_a_bits_source | flight_43 : flight_43; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_366 = a_first & _a_first_T ? 9'h2c == auto_in_a_bits_source | flight_44 : flight_44; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_367 = a_first & _a_first_T ? 9'h2d == auto_in_a_bits_source | flight_45 : flight_45; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_368 = a_first & _a_first_T ? 9'h2e == auto_in_a_bits_source | flight_46 : flight_46; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_369 = a_first & _a_first_T ? 9'h2f == auto_in_a_bits_source | flight_47 : flight_47; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_370 = a_first & _a_first_T ? 9'h30 == auto_in_a_bits_source | flight_48 : flight_48; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_371 = a_first & _a_first_T ? 9'h31 == auto_in_a_bits_source | flight_49 : flight_49; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_372 = a_first & _a_first_T ? 9'h32 == auto_in_a_bits_source | flight_50 : flight_50; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_373 = a_first & _a_first_T ? 9'h33 == auto_in_a_bits_source | flight_51 : flight_51; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_374 = a_first & _a_first_T ? 9'h34 == auto_in_a_bits_source | flight_52 : flight_52; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_375 = a_first & _a_first_T ? 9'h35 == auto_in_a_bits_source | flight_53 : flight_53; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_376 = a_first & _a_first_T ? 9'h36 == auto_in_a_bits_source | flight_54 : flight_54; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_377 = a_first & _a_first_T ? 9'h37 == auto_in_a_bits_source | flight_55 : flight_55; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_378 = a_first & _a_first_T ? 9'h38 == auto_in_a_bits_source | flight_56 : flight_56; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_379 = a_first & _a_first_T ? 9'h39 == auto_in_a_bits_source | flight_57 : flight_57; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_380 = a_first & _a_first_T ? 9'h3a == auto_in_a_bits_source | flight_58 : flight_58; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_381 = a_first & _a_first_T ? 9'h3b == auto_in_a_bits_source | flight_59 : flight_59; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_382 = a_first & _a_first_T ? 9'h3c == auto_in_a_bits_source | flight_60 : flight_60; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_383 = a_first & _a_first_T ? 9'h3d == auto_in_a_bits_source | flight_61 : flight_61; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_384 = a_first & _a_first_T ? 9'h3e == auto_in_a_bits_source | flight_62 : flight_62; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_385 = a_first & _a_first_T ? 9'h3f == auto_in_a_bits_source | flight_63 : flight_63; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_386 = a_first & _a_first_T ? 9'h40 == auto_in_a_bits_source | flight_64 : flight_64; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_387 = a_first & _a_first_T ? 9'h41 == auto_in_a_bits_source | flight_65 : flight_65; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_388 = a_first & _a_first_T ? 9'h42 == auto_in_a_bits_source | flight_66 : flight_66; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_389 = a_first & _a_first_T ? 9'h43 == auto_in_a_bits_source | flight_67 : flight_67; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_390 = a_first & _a_first_T ? 9'h44 == auto_in_a_bits_source | flight_68 : flight_68; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_391 = a_first & _a_first_T ? 9'h45 == auto_in_a_bits_source | flight_69 : flight_69; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_392 = a_first & _a_first_T ? 9'h46 == auto_in_a_bits_source | flight_70 : flight_70; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_393 = a_first & _a_first_T ? 9'h47 == auto_in_a_bits_source | flight_71 : flight_71; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_394 = a_first & _a_first_T ? 9'h48 == auto_in_a_bits_source | flight_72 : flight_72; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_395 = a_first & _a_first_T ? 9'h49 == auto_in_a_bits_source | flight_73 : flight_73; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_396 = a_first & _a_first_T ? 9'h4a == auto_in_a_bits_source | flight_74 : flight_74; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_397 = a_first & _a_first_T ? 9'h4b == auto_in_a_bits_source | flight_75 : flight_75; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_398 = a_first & _a_first_T ? 9'h4c == auto_in_a_bits_source | flight_76 : flight_76; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_399 = a_first & _a_first_T ? 9'h4d == auto_in_a_bits_source | flight_77 : flight_77; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_400 = a_first & _a_first_T ? 9'h4e == auto_in_a_bits_source | flight_78 : flight_78; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_401 = a_first & _a_first_T ? 9'h4f == auto_in_a_bits_source | flight_79 : flight_79; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_402 = a_first & _a_first_T ? 9'h50 == auto_in_a_bits_source | flight_80 : flight_80; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_403 = a_first & _a_first_T ? 9'h51 == auto_in_a_bits_source | flight_81 : flight_81; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_404 = a_first & _a_first_T ? 9'h52 == auto_in_a_bits_source | flight_82 : flight_82; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_405 = a_first & _a_first_T ? 9'h53 == auto_in_a_bits_source | flight_83 : flight_83; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_406 = a_first & _a_first_T ? 9'h54 == auto_in_a_bits_source | flight_84 : flight_84; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_407 = a_first & _a_first_T ? 9'h55 == auto_in_a_bits_source | flight_85 : flight_85; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_408 = a_first & _a_first_T ? 9'h56 == auto_in_a_bits_source | flight_86 : flight_86; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_409 = a_first & _a_first_T ? 9'h57 == auto_in_a_bits_source | flight_87 : flight_87; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_410 = a_first & _a_first_T ? 9'h58 == auto_in_a_bits_source | flight_88 : flight_88; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_411 = a_first & _a_first_T ? 9'h59 == auto_in_a_bits_source | flight_89 : flight_89; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_412 = a_first & _a_first_T ? 9'h5a == auto_in_a_bits_source | flight_90 : flight_90; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_413 = a_first & _a_first_T ? 9'h5b == auto_in_a_bits_source | flight_91 : flight_91; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_414 = a_first & _a_first_T ? 9'h5c == auto_in_a_bits_source | flight_92 : flight_92; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_415 = a_first & _a_first_T ? 9'h5d == auto_in_a_bits_source | flight_93 : flight_93; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_416 = a_first & _a_first_T ? 9'h5e == auto_in_a_bits_source | flight_94 : flight_94; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_417 = a_first & _a_first_T ? 9'h5f == auto_in_a_bits_source | flight_95 : flight_95; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_418 = a_first & _a_first_T ? 9'h60 == auto_in_a_bits_source | flight_96 : flight_96; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_419 = a_first & _a_first_T ? 9'h61 == auto_in_a_bits_source | flight_97 : flight_97; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_420 = a_first & _a_first_T ? 9'h62 == auto_in_a_bits_source | flight_98 : flight_98; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_421 = a_first & _a_first_T ? 9'h63 == auto_in_a_bits_source | flight_99 : flight_99; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_422 = a_first & _a_first_T ? 9'h64 == auto_in_a_bits_source | flight_100 : flight_100; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_423 = a_first & _a_first_T ? 9'h65 == auto_in_a_bits_source | flight_101 : flight_101; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_424 = a_first & _a_first_T ? 9'h66 == auto_in_a_bits_source | flight_102 : flight_102; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_425 = a_first & _a_first_T ? 9'h67 == auto_in_a_bits_source | flight_103 : flight_103; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_426 = a_first & _a_first_T ? 9'h68 == auto_in_a_bits_source | flight_104 : flight_104; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_427 = a_first & _a_first_T ? 9'h69 == auto_in_a_bits_source | flight_105 : flight_105; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_428 = a_first & _a_first_T ? 9'h6a == auto_in_a_bits_source | flight_106 : flight_106; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_429 = a_first & _a_first_T ? 9'h6b == auto_in_a_bits_source | flight_107 : flight_107; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_430 = a_first & _a_first_T ? 9'h6c == auto_in_a_bits_source | flight_108 : flight_108; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_431 = a_first & _a_first_T ? 9'h6d == auto_in_a_bits_source | flight_109 : flight_109; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_432 = a_first & _a_first_T ? 9'h6e == auto_in_a_bits_source | flight_110 : flight_110; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_433 = a_first & _a_first_T ? 9'h6f == auto_in_a_bits_source | flight_111 : flight_111; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_434 = a_first & _a_first_T ? 9'h70 == auto_in_a_bits_source | flight_112 : flight_112; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_435 = a_first & _a_first_T ? 9'h71 == auto_in_a_bits_source | flight_113 : flight_113; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_436 = a_first & _a_first_T ? 9'h72 == auto_in_a_bits_source | flight_114 : flight_114; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_437 = a_first & _a_first_T ? 9'h73 == auto_in_a_bits_source | flight_115 : flight_115; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_438 = a_first & _a_first_T ? 9'h74 == auto_in_a_bits_source | flight_116 : flight_116; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_439 = a_first & _a_first_T ? 9'h75 == auto_in_a_bits_source | flight_117 : flight_117; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_440 = a_first & _a_first_T ? 9'h76 == auto_in_a_bits_source | flight_118 : flight_118; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_441 = a_first & _a_first_T ? 9'h77 == auto_in_a_bits_source | flight_119 : flight_119; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_442 = a_first & _a_first_T ? 9'h78 == auto_in_a_bits_source | flight_120 : flight_120; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_443 = a_first & _a_first_T ? 9'h79 == auto_in_a_bits_source | flight_121 : flight_121; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_444 = a_first & _a_first_T ? 9'h7a == auto_in_a_bits_source | flight_122 : flight_122; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_445 = a_first & _a_first_T ? 9'h7b == auto_in_a_bits_source | flight_123 : flight_123; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_446 = a_first & _a_first_T ? 9'h7c == auto_in_a_bits_source | flight_124 : flight_124; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_447 = a_first & _a_first_T ? 9'h7d == auto_in_a_bits_source | flight_125 : flight_125; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_448 = a_first & _a_first_T ? 9'h7e == auto_in_a_bits_source | flight_126 : flight_126; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_449 = a_first & _a_first_T ? 9'h7f == auto_in_a_bits_source | flight_127 : flight_127; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_450 = a_first & _a_first_T ? 9'h80 == auto_in_a_bits_source | flight_128 : flight_128; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_451 = a_first & _a_first_T ? 9'h81 == auto_in_a_bits_source | flight_129 : flight_129; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_452 = a_first & _a_first_T ? 9'h82 == auto_in_a_bits_source | flight_130 : flight_130; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_453 = a_first & _a_first_T ? 9'h83 == auto_in_a_bits_source | flight_131 : flight_131; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_454 = a_first & _a_first_T ? 9'h84 == auto_in_a_bits_source | flight_132 : flight_132; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_455 = a_first & _a_first_T ? 9'h85 == auto_in_a_bits_source | flight_133 : flight_133; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_456 = a_first & _a_first_T ? 9'h86 == auto_in_a_bits_source | flight_134 : flight_134; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_457 = a_first & _a_first_T ? 9'h87 == auto_in_a_bits_source | flight_135 : flight_135; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_458 = a_first & _a_first_T ? 9'h88 == auto_in_a_bits_source | flight_136 : flight_136; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_459 = a_first & _a_first_T ? 9'h89 == auto_in_a_bits_source | flight_137 : flight_137; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_460 = a_first & _a_first_T ? 9'h8a == auto_in_a_bits_source | flight_138 : flight_138; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_461 = a_first & _a_first_T ? 9'h8b == auto_in_a_bits_source | flight_139 : flight_139; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_462 = a_first & _a_first_T ? 9'h8c == auto_in_a_bits_source | flight_140 : flight_140; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_463 = a_first & _a_first_T ? 9'h8d == auto_in_a_bits_source | flight_141 : flight_141; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_464 = a_first & _a_first_T ? 9'h8e == auto_in_a_bits_source | flight_142 : flight_142; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_465 = a_first & _a_first_T ? 9'h8f == auto_in_a_bits_source | flight_143 : flight_143; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_466 = a_first & _a_first_T ? 9'h90 == auto_in_a_bits_source | flight_144 : flight_144; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_467 = a_first & _a_first_T ? 9'h91 == auto_in_a_bits_source | flight_145 : flight_145; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_468 = a_first & _a_first_T ? 9'h92 == auto_in_a_bits_source | flight_146 : flight_146; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_469 = a_first & _a_first_T ? 9'h93 == auto_in_a_bits_source | flight_147 : flight_147; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_470 = a_first & _a_first_T ? 9'h94 == auto_in_a_bits_source | flight_148 : flight_148; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_471 = a_first & _a_first_T ? 9'h95 == auto_in_a_bits_source | flight_149 : flight_149; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_472 = a_first & _a_first_T ? 9'h96 == auto_in_a_bits_source | flight_150 : flight_150; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_473 = a_first & _a_first_T ? 9'h97 == auto_in_a_bits_source | flight_151 : flight_151; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_474 = a_first & _a_first_T ? 9'h98 == auto_in_a_bits_source | flight_152 : flight_152; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_475 = a_first & _a_first_T ? 9'h99 == auto_in_a_bits_source | flight_153 : flight_153; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_476 = a_first & _a_first_T ? 9'h9a == auto_in_a_bits_source | flight_154 : flight_154; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_477 = a_first & _a_first_T ? 9'h9b == auto_in_a_bits_source | flight_155 : flight_155; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_478 = a_first & _a_first_T ? 9'h9c == auto_in_a_bits_source | flight_156 : flight_156; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_479 = a_first & _a_first_T ? 9'h9d == auto_in_a_bits_source | flight_157 : flight_157; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_480 = a_first & _a_first_T ? 9'h9e == auto_in_a_bits_source | flight_158 : flight_158; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_481 = a_first & _a_first_T ? 9'h9f == auto_in_a_bits_source | flight_159 : flight_159; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_482 = a_first & _a_first_T ? 9'ha0 == auto_in_a_bits_source | flight_160 : flight_160; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_483 = a_first & _a_first_T ? 9'ha1 == auto_in_a_bits_source | flight_161 : flight_161; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_484 = a_first & _a_first_T ? 9'ha2 == auto_in_a_bits_source | flight_162 : flight_162; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_485 = a_first & _a_first_T ? 9'ha3 == auto_in_a_bits_source | flight_163 : flight_163; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_486 = a_first & _a_first_T ? 9'ha4 == auto_in_a_bits_source | flight_164 : flight_164; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_487 = a_first & _a_first_T ? 9'ha5 == auto_in_a_bits_source | flight_165 : flight_165; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_488 = a_first & _a_first_T ? 9'ha6 == auto_in_a_bits_source | flight_166 : flight_166; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_489 = a_first & _a_first_T ? 9'ha7 == auto_in_a_bits_source | flight_167 : flight_167; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_490 = a_first & _a_first_T ? 9'ha8 == auto_in_a_bits_source | flight_168 : flight_168; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_491 = a_first & _a_first_T ? 9'ha9 == auto_in_a_bits_source | flight_169 : flight_169; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_492 = a_first & _a_first_T ? 9'haa == auto_in_a_bits_source | flight_170 : flight_170; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_493 = a_first & _a_first_T ? 9'hab == auto_in_a_bits_source | flight_171 : flight_171; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_494 = a_first & _a_first_T ? 9'hac == auto_in_a_bits_source | flight_172 : flight_172; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_495 = a_first & _a_first_T ? 9'had == auto_in_a_bits_source | flight_173 : flight_173; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_496 = a_first & _a_first_T ? 9'hae == auto_in_a_bits_source | flight_174 : flight_174; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_497 = a_first & _a_first_T ? 9'haf == auto_in_a_bits_source | flight_175 : flight_175; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_498 = a_first & _a_first_T ? 9'hb0 == auto_in_a_bits_source | flight_176 : flight_176; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_499 = a_first & _a_first_T ? 9'hb1 == auto_in_a_bits_source | flight_177 : flight_177; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_500 = a_first & _a_first_T ? 9'hb2 == auto_in_a_bits_source | flight_178 : flight_178; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_501 = a_first & _a_first_T ? 9'hb3 == auto_in_a_bits_source | flight_179 : flight_179; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_502 = a_first & _a_first_T ? 9'hb4 == auto_in_a_bits_source | flight_180 : flight_180; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_503 = a_first & _a_first_T ? 9'hb5 == auto_in_a_bits_source | flight_181 : flight_181; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_504 = a_first & _a_first_T ? 9'hb6 == auto_in_a_bits_source | flight_182 : flight_182; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_505 = a_first & _a_first_T ? 9'hb7 == auto_in_a_bits_source | flight_183 : flight_183; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_506 = a_first & _a_first_T ? 9'hb8 == auto_in_a_bits_source | flight_184 : flight_184; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_507 = a_first & _a_first_T ? 9'hb9 == auto_in_a_bits_source | flight_185 : flight_185; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_508 = a_first & _a_first_T ? 9'hba == auto_in_a_bits_source | flight_186 : flight_186; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_509 = a_first & _a_first_T ? 9'hbb == auto_in_a_bits_source | flight_187 : flight_187; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_510 = a_first & _a_first_T ? 9'hbc == auto_in_a_bits_source | flight_188 : flight_188; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_511 = a_first & _a_first_T ? 9'hbd == auto_in_a_bits_source | flight_189 : flight_189; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_512 = a_first & _a_first_T ? 9'hbe == auto_in_a_bits_source | flight_190 : flight_190; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_513 = a_first & _a_first_T ? 9'hbf == auto_in_a_bits_source | flight_191 : flight_191; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_514 = a_first & _a_first_T ? 9'hc0 == auto_in_a_bits_source | flight_192 : flight_192; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_515 = a_first & _a_first_T ? 9'hc1 == auto_in_a_bits_source | flight_193 : flight_193; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_516 = a_first & _a_first_T ? 9'hc2 == auto_in_a_bits_source | flight_194 : flight_194; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_517 = a_first & _a_first_T ? 9'hc3 == auto_in_a_bits_source | flight_195 : flight_195; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_518 = a_first & _a_first_T ? 9'hc4 == auto_in_a_bits_source | flight_196 : flight_196; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_519 = a_first & _a_first_T ? 9'hc5 == auto_in_a_bits_source | flight_197 : flight_197; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_520 = a_first & _a_first_T ? 9'hc6 == auto_in_a_bits_source | flight_198 : flight_198; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_521 = a_first & _a_first_T ? 9'hc7 == auto_in_a_bits_source | flight_199 : flight_199; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_522 = a_first & _a_first_T ? 9'hc8 == auto_in_a_bits_source | flight_200 : flight_200; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_523 = a_first & _a_first_T ? 9'hc9 == auto_in_a_bits_source | flight_201 : flight_201; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_524 = a_first & _a_first_T ? 9'hca == auto_in_a_bits_source | flight_202 : flight_202; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_525 = a_first & _a_first_T ? 9'hcb == auto_in_a_bits_source | flight_203 : flight_203; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_526 = a_first & _a_first_T ? 9'hcc == auto_in_a_bits_source | flight_204 : flight_204; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_527 = a_first & _a_first_T ? 9'hcd == auto_in_a_bits_source | flight_205 : flight_205; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_528 = a_first & _a_first_T ? 9'hce == auto_in_a_bits_source | flight_206 : flight_206; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_529 = a_first & _a_first_T ? 9'hcf == auto_in_a_bits_source | flight_207 : flight_207; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_530 = a_first & _a_first_T ? 9'hd0 == auto_in_a_bits_source | flight_208 : flight_208; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_531 = a_first & _a_first_T ? 9'hd1 == auto_in_a_bits_source | flight_209 : flight_209; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_532 = a_first & _a_first_T ? 9'hd2 == auto_in_a_bits_source | flight_210 : flight_210; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_533 = a_first & _a_first_T ? 9'hd3 == auto_in_a_bits_source | flight_211 : flight_211; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_534 = a_first & _a_first_T ? 9'hd4 == auto_in_a_bits_source | flight_212 : flight_212; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_535 = a_first & _a_first_T ? 9'hd5 == auto_in_a_bits_source | flight_213 : flight_213; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_536 = a_first & _a_first_T ? 9'hd6 == auto_in_a_bits_source | flight_214 : flight_214; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_537 = a_first & _a_first_T ? 9'hd7 == auto_in_a_bits_source | flight_215 : flight_215; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_538 = a_first & _a_first_T ? 9'hd8 == auto_in_a_bits_source | flight_216 : flight_216; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_539 = a_first & _a_first_T ? 9'hd9 == auto_in_a_bits_source | flight_217 : flight_217; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_540 = a_first & _a_first_T ? 9'hda == auto_in_a_bits_source | flight_218 : flight_218; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_541 = a_first & _a_first_T ? 9'hdb == auto_in_a_bits_source | flight_219 : flight_219; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_542 = a_first & _a_first_T ? 9'hdc == auto_in_a_bits_source | flight_220 : flight_220; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_543 = a_first & _a_first_T ? 9'hdd == auto_in_a_bits_source | flight_221 : flight_221; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_544 = a_first & _a_first_T ? 9'hde == auto_in_a_bits_source | flight_222 : flight_222; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_545 = a_first & _a_first_T ? 9'hdf == auto_in_a_bits_source | flight_223 : flight_223; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_546 = a_first & _a_first_T ? 9'he0 == auto_in_a_bits_source | flight_224 : flight_224; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_547 = a_first & _a_first_T ? 9'he1 == auto_in_a_bits_source | flight_225 : flight_225; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_548 = a_first & _a_first_T ? 9'he2 == auto_in_a_bits_source | flight_226 : flight_226; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_549 = a_first & _a_first_T ? 9'he3 == auto_in_a_bits_source | flight_227 : flight_227; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_550 = a_first & _a_first_T ? 9'he4 == auto_in_a_bits_source | flight_228 : flight_228; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_551 = a_first & _a_first_T ? 9'he5 == auto_in_a_bits_source | flight_229 : flight_229; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_552 = a_first & _a_first_T ? 9'he6 == auto_in_a_bits_source | flight_230 : flight_230; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_553 = a_first & _a_first_T ? 9'he7 == auto_in_a_bits_source | flight_231 : flight_231; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_554 = a_first & _a_first_T ? 9'he8 == auto_in_a_bits_source | flight_232 : flight_232; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_555 = a_first & _a_first_T ? 9'he9 == auto_in_a_bits_source | flight_233 : flight_233; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_556 = a_first & _a_first_T ? 9'hea == auto_in_a_bits_source | flight_234 : flight_234; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_557 = a_first & _a_first_T ? 9'heb == auto_in_a_bits_source | flight_235 : flight_235; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_558 = a_first & _a_first_T ? 9'hec == auto_in_a_bits_source | flight_236 : flight_236; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_559 = a_first & _a_first_T ? 9'hed == auto_in_a_bits_source | flight_237 : flight_237; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_560 = a_first & _a_first_T ? 9'hee == auto_in_a_bits_source | flight_238 : flight_238; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_561 = a_first & _a_first_T ? 9'hef == auto_in_a_bits_source | flight_239 : flight_239; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_562 = a_first & _a_first_T ? 9'hf0 == auto_in_a_bits_source | flight_240 : flight_240; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_563 = a_first & _a_first_T ? 9'hf1 == auto_in_a_bits_source | flight_241 : flight_241; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_564 = a_first & _a_first_T ? 9'hf2 == auto_in_a_bits_source | flight_242 : flight_242; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_565 = a_first & _a_first_T ? 9'hf3 == auto_in_a_bits_source | flight_243 : flight_243; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_566 = a_first & _a_first_T ? 9'hf4 == auto_in_a_bits_source | flight_244 : flight_244; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_567 = a_first & _a_first_T ? 9'hf5 == auto_in_a_bits_source | flight_245 : flight_245; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_568 = a_first & _a_first_T ? 9'hf6 == auto_in_a_bits_source | flight_246 : flight_246; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_569 = a_first & _a_first_T ? 9'hf7 == auto_in_a_bits_source | flight_247 : flight_247; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_570 = a_first & _a_first_T ? 9'hf8 == auto_in_a_bits_source | flight_248 : flight_248; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_571 = a_first & _a_first_T ? 9'hf9 == auto_in_a_bits_source | flight_249 : flight_249; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_572 = a_first & _a_first_T ? 9'hfa == auto_in_a_bits_source | flight_250 : flight_250; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_573 = a_first & _a_first_T ? 9'hfb == auto_in_a_bits_source | flight_251 : flight_251; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_574 = a_first & _a_first_T ? 9'hfc == auto_in_a_bits_source | flight_252 : flight_252; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_575 = a_first & _a_first_T ? 9'hfd == auto_in_a_bits_source | flight_253 : flight_253; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_576 = a_first & _a_first_T ? 9'hfe == auto_in_a_bits_source | flight_254 : flight_254; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_577 = a_first & _a_first_T ? 9'hff == auto_in_a_bits_source | flight_255 : flight_255; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_578 = a_first & _a_first_T ? 9'h100 == auto_in_a_bits_source | flight_256 : flight_256; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_579 = a_first & _a_first_T ? 9'h101 == auto_in_a_bits_source | flight_257 : flight_257; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_580 = a_first & _a_first_T ? 9'h102 == auto_in_a_bits_source | flight_258 : flight_258; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_581 = a_first & _a_first_T ? 9'h103 == auto_in_a_bits_source | flight_259 : flight_259; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_582 = a_first & _a_first_T ? 9'h104 == auto_in_a_bits_source | flight_260 : flight_260; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_583 = a_first & _a_first_T ? 9'h105 == auto_in_a_bits_source | flight_261 : flight_261; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_584 = a_first & _a_first_T ? 9'h106 == auto_in_a_bits_source | flight_262 : flight_262; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_585 = a_first & _a_first_T ? 9'h107 == auto_in_a_bits_source | flight_263 : flight_263; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_586 = a_first & _a_first_T ? 9'h108 == auto_in_a_bits_source | flight_264 : flight_264; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_587 = a_first & _a_first_T ? 9'h109 == auto_in_a_bits_source | flight_265 : flight_265; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_588 = a_first & _a_first_T ? 9'h10a == auto_in_a_bits_source | flight_266 : flight_266; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_589 = a_first & _a_first_T ? 9'h10b == auto_in_a_bits_source | flight_267 : flight_267; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_590 = a_first & _a_first_T ? 9'h10c == auto_in_a_bits_source | flight_268 : flight_268; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_591 = a_first & _a_first_T ? 9'h10d == auto_in_a_bits_source | flight_269 : flight_269; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_592 = a_first & _a_first_T ? 9'h10e == auto_in_a_bits_source | flight_270 : flight_270; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_593 = a_first & _a_first_T ? 9'h10f == auto_in_a_bits_source | flight_271 : flight_271; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_594 = a_first & _a_first_T ? 9'h110 == auto_in_a_bits_source | flight_272 : flight_272; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_595 = a_first & _a_first_T ? 9'h111 == auto_in_a_bits_source | flight_273 : flight_273; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_596 = a_first & _a_first_T ? 9'h112 == auto_in_a_bits_source | flight_274 : flight_274; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_597 = a_first & _a_first_T ? 9'h113 == auto_in_a_bits_source | flight_275 : flight_275; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_598 = a_first & _a_first_T ? 9'h114 == auto_in_a_bits_source | flight_276 : flight_276; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_599 = a_first & _a_first_T ? 9'h115 == auto_in_a_bits_source | flight_277 : flight_277; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_600 = a_first & _a_first_T ? 9'h116 == auto_in_a_bits_source | flight_278 : flight_278; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_601 = a_first & _a_first_T ? 9'h117 == auto_in_a_bits_source | flight_279 : flight_279; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_602 = a_first & _a_first_T ? 9'h118 == auto_in_a_bits_source | flight_280 : flight_280; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_603 = a_first & _a_first_T ? 9'h119 == auto_in_a_bits_source | flight_281 : flight_281; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_604 = a_first & _a_first_T ? 9'h11a == auto_in_a_bits_source | flight_282 : flight_282; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_605 = a_first & _a_first_T ? 9'h11b == auto_in_a_bits_source | flight_283 : flight_283; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_606 = a_first & _a_first_T ? 9'h11c == auto_in_a_bits_source | flight_284 : flight_284; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_607 = a_first & _a_first_T ? 9'h11d == auto_in_a_bits_source | flight_285 : flight_285; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_608 = a_first & _a_first_T ? 9'h11e == auto_in_a_bits_source | flight_286 : flight_286; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_609 = a_first & _a_first_T ? 9'h11f == auto_in_a_bits_source | flight_287 : flight_287; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_610 = a_first & _a_first_T ? 9'h120 == auto_in_a_bits_source | flight_288 : flight_288; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_611 = a_first & _a_first_T ? 9'h121 == auto_in_a_bits_source | flight_289 : flight_289; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_612 = a_first & _a_first_T ? 9'h122 == auto_in_a_bits_source | flight_290 : flight_290; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_613 = a_first & _a_first_T ? 9'h123 == auto_in_a_bits_source | flight_291 : flight_291; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_614 = a_first & _a_first_T ? 9'h124 == auto_in_a_bits_source | flight_292 : flight_292; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_615 = a_first & _a_first_T ? 9'h125 == auto_in_a_bits_source | flight_293 : flight_293; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_616 = a_first & _a_first_T ? 9'h126 == auto_in_a_bits_source | flight_294 : flight_294; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_617 = a_first & _a_first_T ? 9'h127 == auto_in_a_bits_source | flight_295 : flight_295; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_618 = a_first & _a_first_T ? 9'h128 == auto_in_a_bits_source | flight_296 : flight_296; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_619 = a_first & _a_first_T ? 9'h129 == auto_in_a_bits_source | flight_297 : flight_297; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_620 = a_first & _a_first_T ? 9'h12a == auto_in_a_bits_source | flight_298 : flight_298; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_621 = a_first & _a_first_T ? 9'h12b == auto_in_a_bits_source | flight_299 : flight_299; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_622 = a_first & _a_first_T ? 9'h12c == auto_in_a_bits_source | flight_300 : flight_300; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_623 = a_first & _a_first_T ? 9'h12d == auto_in_a_bits_source | flight_301 : flight_301; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_624 = a_first & _a_first_T ? 9'h12e == auto_in_a_bits_source | flight_302 : flight_302; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_625 = a_first & _a_first_T ? 9'h12f == auto_in_a_bits_source | flight_303 : flight_303; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_626 = a_first & _a_first_T ? 9'h130 == auto_in_a_bits_source | flight_304 : flight_304; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_627 = a_first & _a_first_T ? 9'h131 == auto_in_a_bits_source | flight_305 : flight_305; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_628 = a_first & _a_first_T ? 9'h132 == auto_in_a_bits_source | flight_306 : flight_306; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_629 = a_first & _a_first_T ? 9'h133 == auto_in_a_bits_source | flight_307 : flight_307; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_630 = a_first & _a_first_T ? 9'h134 == auto_in_a_bits_source | flight_308 : flight_308; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_631 = a_first & _a_first_T ? 9'h135 == auto_in_a_bits_source | flight_309 : flight_309; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_632 = a_first & _a_first_T ? 9'h136 == auto_in_a_bits_source | flight_310 : flight_310; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_633 = a_first & _a_first_T ? 9'h137 == auto_in_a_bits_source | flight_311 : flight_311; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_634 = a_first & _a_first_T ? 9'h138 == auto_in_a_bits_source | flight_312 : flight_312; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_635 = a_first & _a_first_T ? 9'h139 == auto_in_a_bits_source | flight_313 : flight_313; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_636 = a_first & _a_first_T ? 9'h13a == auto_in_a_bits_source | flight_314 : flight_314; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_637 = a_first & _a_first_T ? 9'h13b == auto_in_a_bits_source | flight_315 : flight_315; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_638 = a_first & _a_first_T ? 9'h13c == auto_in_a_bits_source | flight_316 : flight_316; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_639 = a_first & _a_first_T ? 9'h13d == auto_in_a_bits_source | flight_317 : flight_317; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_640 = a_first & _a_first_T ? 9'h13e == auto_in_a_bits_source | flight_318 : flight_318; // @[FIFOFixer.scala 71:27 72:37]
  wire  _GEN_641 = a_first & _a_first_T ? 9'h13f == auto_in_a_bits_source | flight_319 : flight_319; // @[FIFOFixer.scala 71:27 72:37]
  TLMonitor_9 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_in_a_ready = auto_out_a_ready & ~stalls_0; // @[FIFOFixer.scala 88:33]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid & _bundleIn_0_a_ready_T; // @[FIFOFixer.scala 87:33]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready & ~stalls_0; // @[FIFOFixer.scala 88:33]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_0 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h0 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_0 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_0 <= _GEN_322;
      end
    end else begin
      flight_0 <= _GEN_322;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_1 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h1 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_1 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_1 <= _GEN_323;
      end
    end else begin
      flight_1 <= _GEN_323;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_2 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h2 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_2 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_2 <= _GEN_324;
      end
    end else begin
      flight_2 <= _GEN_324;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_3 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h3 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_3 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_3 <= _GEN_325;
      end
    end else begin
      flight_3 <= _GEN_325;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_4 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h4 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_4 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_4 <= _GEN_326;
      end
    end else begin
      flight_4 <= _GEN_326;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_5 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h5 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_5 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_5 <= _GEN_327;
      end
    end else begin
      flight_5 <= _GEN_327;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_6 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h6 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_6 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_6 <= _GEN_328;
      end
    end else begin
      flight_6 <= _GEN_328;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_7 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h7 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_7 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_7 <= _GEN_329;
      end
    end else begin
      flight_7 <= _GEN_329;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_8 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h8 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_8 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_8 <= _GEN_330;
      end
    end else begin
      flight_8 <= _GEN_330;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_9 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h9 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_9 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_9 <= _GEN_331;
      end
    end else begin
      flight_9 <= _GEN_331;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_10 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_10 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_10 <= _GEN_332;
      end
    end else begin
      flight_10 <= _GEN_332;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_11 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_11 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_11 <= _GEN_333;
      end
    end else begin
      flight_11 <= _GEN_333;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_12 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_12 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_12 <= _GEN_334;
      end
    end else begin
      flight_12 <= _GEN_334;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_13 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_13 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_13 <= _GEN_335;
      end
    end else begin
      flight_13 <= _GEN_335;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_14 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_14 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_14 <= _GEN_336;
      end
    end else begin
      flight_14 <= _GEN_336;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_15 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_15 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_15 <= _GEN_337;
      end
    end else begin
      flight_15 <= _GEN_337;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_16 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h10 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_16 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_16 <= _GEN_338;
      end
    end else begin
      flight_16 <= _GEN_338;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_17 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h11 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_17 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_17 <= _GEN_339;
      end
    end else begin
      flight_17 <= _GEN_339;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_18 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h12 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_18 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_18 <= _GEN_340;
      end
    end else begin
      flight_18 <= _GEN_340;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_19 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h13 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_19 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_19 <= _GEN_341;
      end
    end else begin
      flight_19 <= _GEN_341;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_20 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h14 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_20 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_20 <= _GEN_342;
      end
    end else begin
      flight_20 <= _GEN_342;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_21 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h15 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_21 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_21 <= _GEN_343;
      end
    end else begin
      flight_21 <= _GEN_343;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_22 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h16 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_22 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_22 <= _GEN_344;
      end
    end else begin
      flight_22 <= _GEN_344;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_23 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h17 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_23 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_23 <= _GEN_345;
      end
    end else begin
      flight_23 <= _GEN_345;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_24 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h18 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_24 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_24 <= _GEN_346;
      end
    end else begin
      flight_24 <= _GEN_346;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_25 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h19 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_25 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_25 <= _GEN_347;
      end
    end else begin
      flight_25 <= _GEN_347;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_26 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h1a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_26 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_26 <= _GEN_348;
      end
    end else begin
      flight_26 <= _GEN_348;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_27 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h1b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_27 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_27 <= _GEN_349;
      end
    end else begin
      flight_27 <= _GEN_349;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_28 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h1c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_28 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_28 <= _GEN_350;
      end
    end else begin
      flight_28 <= _GEN_350;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_29 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h1d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_29 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_29 <= _GEN_351;
      end
    end else begin
      flight_29 <= _GEN_351;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_30 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h1e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_30 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_30 <= _GEN_352;
      end
    end else begin
      flight_30 <= _GEN_352;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_31 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h1f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_31 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_31 <= _GEN_353;
      end
    end else begin
      flight_31 <= _GEN_353;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_32 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h20 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_32 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_32 <= _GEN_354;
      end
    end else begin
      flight_32 <= _GEN_354;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_33 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h21 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_33 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_33 <= _GEN_355;
      end
    end else begin
      flight_33 <= _GEN_355;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_34 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h22 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_34 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_34 <= _GEN_356;
      end
    end else begin
      flight_34 <= _GEN_356;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_35 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h23 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_35 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_35 <= _GEN_357;
      end
    end else begin
      flight_35 <= _GEN_357;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_36 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h24 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_36 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_36 <= _GEN_358;
      end
    end else begin
      flight_36 <= _GEN_358;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_37 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h25 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_37 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_37 <= _GEN_359;
      end
    end else begin
      flight_37 <= _GEN_359;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_38 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h26 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_38 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_38 <= _GEN_360;
      end
    end else begin
      flight_38 <= _GEN_360;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_39 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h27 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_39 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_39 <= _GEN_361;
      end
    end else begin
      flight_39 <= _GEN_361;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_40 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h28 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_40 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_40 <= _GEN_362;
      end
    end else begin
      flight_40 <= _GEN_362;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_41 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h29 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_41 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_41 <= _GEN_363;
      end
    end else begin
      flight_41 <= _GEN_363;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_42 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h2a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_42 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_42 <= _GEN_364;
      end
    end else begin
      flight_42 <= _GEN_364;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_43 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h2b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_43 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_43 <= _GEN_365;
      end
    end else begin
      flight_43 <= _GEN_365;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_44 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h2c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_44 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_44 <= _GEN_366;
      end
    end else begin
      flight_44 <= _GEN_366;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_45 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h2d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_45 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_45 <= _GEN_367;
      end
    end else begin
      flight_45 <= _GEN_367;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_46 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h2e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_46 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_46 <= _GEN_368;
      end
    end else begin
      flight_46 <= _GEN_368;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_47 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h2f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_47 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_47 <= _GEN_369;
      end
    end else begin
      flight_47 <= _GEN_369;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_48 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h30 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_48 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_48 <= _GEN_370;
      end
    end else begin
      flight_48 <= _GEN_370;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_49 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h31 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_49 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_49 <= _GEN_371;
      end
    end else begin
      flight_49 <= _GEN_371;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_50 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h32 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_50 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_50 <= _GEN_372;
      end
    end else begin
      flight_50 <= _GEN_372;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_51 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h33 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_51 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_51 <= _GEN_373;
      end
    end else begin
      flight_51 <= _GEN_373;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_52 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h34 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_52 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_52 <= _GEN_374;
      end
    end else begin
      flight_52 <= _GEN_374;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_53 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h35 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_53 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_53 <= _GEN_375;
      end
    end else begin
      flight_53 <= _GEN_375;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_54 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h36 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_54 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_54 <= _GEN_376;
      end
    end else begin
      flight_54 <= _GEN_376;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_55 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h37 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_55 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_55 <= _GEN_377;
      end
    end else begin
      flight_55 <= _GEN_377;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_56 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h38 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_56 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_56 <= _GEN_378;
      end
    end else begin
      flight_56 <= _GEN_378;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_57 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h39 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_57 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_57 <= _GEN_379;
      end
    end else begin
      flight_57 <= _GEN_379;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_58 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h3a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_58 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_58 <= _GEN_380;
      end
    end else begin
      flight_58 <= _GEN_380;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_59 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h3b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_59 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_59 <= _GEN_381;
      end
    end else begin
      flight_59 <= _GEN_381;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_60 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h3c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_60 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_60 <= _GEN_382;
      end
    end else begin
      flight_60 <= _GEN_382;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_61 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h3d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_61 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_61 <= _GEN_383;
      end
    end else begin
      flight_61 <= _GEN_383;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_62 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h3e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_62 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_62 <= _GEN_384;
      end
    end else begin
      flight_62 <= _GEN_384;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_63 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h3f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_63 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_63 <= _GEN_385;
      end
    end else begin
      flight_63 <= _GEN_385;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_64 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h40 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_64 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_64 <= _GEN_386;
      end
    end else begin
      flight_64 <= _GEN_386;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_65 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h41 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_65 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_65 <= _GEN_387;
      end
    end else begin
      flight_65 <= _GEN_387;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_66 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h42 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_66 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_66 <= _GEN_388;
      end
    end else begin
      flight_66 <= _GEN_388;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_67 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h43 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_67 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_67 <= _GEN_389;
      end
    end else begin
      flight_67 <= _GEN_389;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_68 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h44 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_68 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_68 <= _GEN_390;
      end
    end else begin
      flight_68 <= _GEN_390;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_69 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h45 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_69 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_69 <= _GEN_391;
      end
    end else begin
      flight_69 <= _GEN_391;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_70 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h46 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_70 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_70 <= _GEN_392;
      end
    end else begin
      flight_70 <= _GEN_392;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_71 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h47 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_71 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_71 <= _GEN_393;
      end
    end else begin
      flight_71 <= _GEN_393;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_72 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h48 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_72 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_72 <= _GEN_394;
      end
    end else begin
      flight_72 <= _GEN_394;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_73 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h49 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_73 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_73 <= _GEN_395;
      end
    end else begin
      flight_73 <= _GEN_395;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_74 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h4a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_74 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_74 <= _GEN_396;
      end
    end else begin
      flight_74 <= _GEN_396;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_75 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h4b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_75 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_75 <= _GEN_397;
      end
    end else begin
      flight_75 <= _GEN_397;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_76 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h4c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_76 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_76 <= _GEN_398;
      end
    end else begin
      flight_76 <= _GEN_398;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_77 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h4d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_77 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_77 <= _GEN_399;
      end
    end else begin
      flight_77 <= _GEN_399;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_78 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h4e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_78 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_78 <= _GEN_400;
      end
    end else begin
      flight_78 <= _GEN_400;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_79 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h4f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_79 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_79 <= _GEN_401;
      end
    end else begin
      flight_79 <= _GEN_401;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_80 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h50 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_80 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_80 <= _GEN_402;
      end
    end else begin
      flight_80 <= _GEN_402;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_81 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h51 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_81 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_81 <= _GEN_403;
      end
    end else begin
      flight_81 <= _GEN_403;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_82 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h52 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_82 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_82 <= _GEN_404;
      end
    end else begin
      flight_82 <= _GEN_404;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_83 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h53 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_83 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_83 <= _GEN_405;
      end
    end else begin
      flight_83 <= _GEN_405;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_84 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h54 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_84 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_84 <= _GEN_406;
      end
    end else begin
      flight_84 <= _GEN_406;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_85 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h55 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_85 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_85 <= _GEN_407;
      end
    end else begin
      flight_85 <= _GEN_407;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_86 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h56 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_86 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_86 <= _GEN_408;
      end
    end else begin
      flight_86 <= _GEN_408;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_87 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h57 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_87 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_87 <= _GEN_409;
      end
    end else begin
      flight_87 <= _GEN_409;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_88 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h58 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_88 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_88 <= _GEN_410;
      end
    end else begin
      flight_88 <= _GEN_410;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_89 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h59 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_89 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_89 <= _GEN_411;
      end
    end else begin
      flight_89 <= _GEN_411;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_90 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h5a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_90 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_90 <= _GEN_412;
      end
    end else begin
      flight_90 <= _GEN_412;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_91 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h5b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_91 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_91 <= _GEN_413;
      end
    end else begin
      flight_91 <= _GEN_413;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_92 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h5c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_92 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_92 <= _GEN_414;
      end
    end else begin
      flight_92 <= _GEN_414;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_93 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h5d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_93 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_93 <= _GEN_415;
      end
    end else begin
      flight_93 <= _GEN_415;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_94 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h5e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_94 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_94 <= _GEN_416;
      end
    end else begin
      flight_94 <= _GEN_416;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_95 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h5f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_95 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_95 <= _GEN_417;
      end
    end else begin
      flight_95 <= _GEN_417;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_96 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h60 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_96 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_96 <= _GEN_418;
      end
    end else begin
      flight_96 <= _GEN_418;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_97 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h61 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_97 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_97 <= _GEN_419;
      end
    end else begin
      flight_97 <= _GEN_419;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_98 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h62 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_98 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_98 <= _GEN_420;
      end
    end else begin
      flight_98 <= _GEN_420;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_99 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h63 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_99 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_99 <= _GEN_421;
      end
    end else begin
      flight_99 <= _GEN_421;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_100 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h64 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_100 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_100 <= _GEN_422;
      end
    end else begin
      flight_100 <= _GEN_422;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_101 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h65 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_101 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_101 <= _GEN_423;
      end
    end else begin
      flight_101 <= _GEN_423;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_102 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h66 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_102 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_102 <= _GEN_424;
      end
    end else begin
      flight_102 <= _GEN_424;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_103 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h67 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_103 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_103 <= _GEN_425;
      end
    end else begin
      flight_103 <= _GEN_425;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_104 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h68 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_104 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_104 <= _GEN_426;
      end
    end else begin
      flight_104 <= _GEN_426;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_105 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h69 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_105 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_105 <= _GEN_427;
      end
    end else begin
      flight_105 <= _GEN_427;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_106 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h6a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_106 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_106 <= _GEN_428;
      end
    end else begin
      flight_106 <= _GEN_428;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_107 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h6b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_107 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_107 <= _GEN_429;
      end
    end else begin
      flight_107 <= _GEN_429;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_108 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h6c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_108 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_108 <= _GEN_430;
      end
    end else begin
      flight_108 <= _GEN_430;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_109 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h6d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_109 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_109 <= _GEN_431;
      end
    end else begin
      flight_109 <= _GEN_431;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_110 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h6e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_110 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_110 <= _GEN_432;
      end
    end else begin
      flight_110 <= _GEN_432;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_111 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h6f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_111 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_111 <= _GEN_433;
      end
    end else begin
      flight_111 <= _GEN_433;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_112 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h70 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_112 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_112 <= _GEN_434;
      end
    end else begin
      flight_112 <= _GEN_434;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_113 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h71 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_113 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_113 <= _GEN_435;
      end
    end else begin
      flight_113 <= _GEN_435;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_114 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h72 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_114 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_114 <= _GEN_436;
      end
    end else begin
      flight_114 <= _GEN_436;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_115 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h73 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_115 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_115 <= _GEN_437;
      end
    end else begin
      flight_115 <= _GEN_437;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_116 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h74 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_116 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_116 <= _GEN_438;
      end
    end else begin
      flight_116 <= _GEN_438;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_117 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h75 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_117 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_117 <= _GEN_439;
      end
    end else begin
      flight_117 <= _GEN_439;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_118 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h76 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_118 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_118 <= _GEN_440;
      end
    end else begin
      flight_118 <= _GEN_440;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_119 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h77 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_119 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_119 <= _GEN_441;
      end
    end else begin
      flight_119 <= _GEN_441;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_120 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h78 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_120 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_120 <= _GEN_442;
      end
    end else begin
      flight_120 <= _GEN_442;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_121 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h79 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_121 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_121 <= _GEN_443;
      end
    end else begin
      flight_121 <= _GEN_443;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_122 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h7a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_122 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_122 <= _GEN_444;
      end
    end else begin
      flight_122 <= _GEN_444;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_123 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h7b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_123 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_123 <= _GEN_445;
      end
    end else begin
      flight_123 <= _GEN_445;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_124 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h7c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_124 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_124 <= _GEN_446;
      end
    end else begin
      flight_124 <= _GEN_446;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_125 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h7d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_125 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_125 <= _GEN_447;
      end
    end else begin
      flight_125 <= _GEN_447;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_126 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h7e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_126 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_126 <= _GEN_448;
      end
    end else begin
      flight_126 <= _GEN_448;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_127 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h7f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_127 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_127 <= _GEN_449;
      end
    end else begin
      flight_127 <= _GEN_449;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_128 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h80 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_128 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_128 <= _GEN_450;
      end
    end else begin
      flight_128 <= _GEN_450;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_129 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h81 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_129 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_129 <= _GEN_451;
      end
    end else begin
      flight_129 <= _GEN_451;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_130 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h82 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_130 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_130 <= _GEN_452;
      end
    end else begin
      flight_130 <= _GEN_452;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_131 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h83 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_131 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_131 <= _GEN_453;
      end
    end else begin
      flight_131 <= _GEN_453;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_132 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h84 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_132 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_132 <= _GEN_454;
      end
    end else begin
      flight_132 <= _GEN_454;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_133 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h85 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_133 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_133 <= _GEN_455;
      end
    end else begin
      flight_133 <= _GEN_455;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_134 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h86 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_134 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_134 <= _GEN_456;
      end
    end else begin
      flight_134 <= _GEN_456;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_135 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h87 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_135 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_135 <= _GEN_457;
      end
    end else begin
      flight_135 <= _GEN_457;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_136 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h88 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_136 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_136 <= _GEN_458;
      end
    end else begin
      flight_136 <= _GEN_458;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_137 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h89 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_137 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_137 <= _GEN_459;
      end
    end else begin
      flight_137 <= _GEN_459;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_138 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h8a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_138 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_138 <= _GEN_460;
      end
    end else begin
      flight_138 <= _GEN_460;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_139 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h8b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_139 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_139 <= _GEN_461;
      end
    end else begin
      flight_139 <= _GEN_461;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_140 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h8c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_140 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_140 <= _GEN_462;
      end
    end else begin
      flight_140 <= _GEN_462;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_141 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h8d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_141 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_141 <= _GEN_463;
      end
    end else begin
      flight_141 <= _GEN_463;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_142 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h8e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_142 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_142 <= _GEN_464;
      end
    end else begin
      flight_142 <= _GEN_464;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_143 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h8f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_143 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_143 <= _GEN_465;
      end
    end else begin
      flight_143 <= _GEN_465;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_144 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h90 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_144 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_144 <= _GEN_466;
      end
    end else begin
      flight_144 <= _GEN_466;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_145 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h91 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_145 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_145 <= _GEN_467;
      end
    end else begin
      flight_145 <= _GEN_467;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_146 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h92 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_146 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_146 <= _GEN_468;
      end
    end else begin
      flight_146 <= _GEN_468;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_147 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h93 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_147 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_147 <= _GEN_469;
      end
    end else begin
      flight_147 <= _GEN_469;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_148 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h94 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_148 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_148 <= _GEN_470;
      end
    end else begin
      flight_148 <= _GEN_470;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_149 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h95 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_149 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_149 <= _GEN_471;
      end
    end else begin
      flight_149 <= _GEN_471;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_150 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h96 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_150 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_150 <= _GEN_472;
      end
    end else begin
      flight_150 <= _GEN_472;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_151 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h97 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_151 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_151 <= _GEN_473;
      end
    end else begin
      flight_151 <= _GEN_473;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_152 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h98 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_152 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_152 <= _GEN_474;
      end
    end else begin
      flight_152 <= _GEN_474;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_153 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h99 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_153 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_153 <= _GEN_475;
      end
    end else begin
      flight_153 <= _GEN_475;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_154 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h9a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_154 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_154 <= _GEN_476;
      end
    end else begin
      flight_154 <= _GEN_476;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_155 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h9b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_155 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_155 <= _GEN_477;
      end
    end else begin
      flight_155 <= _GEN_477;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_156 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h9c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_156 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_156 <= _GEN_478;
      end
    end else begin
      flight_156 <= _GEN_478;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_157 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h9d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_157 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_157 <= _GEN_479;
      end
    end else begin
      flight_157 <= _GEN_479;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_158 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h9e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_158 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_158 <= _GEN_480;
      end
    end else begin
      flight_158 <= _GEN_480;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_159 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h9f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_159 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_159 <= _GEN_481;
      end
    end else begin
      flight_159 <= _GEN_481;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_160 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha0 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_160 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_160 <= _GEN_482;
      end
    end else begin
      flight_160 <= _GEN_482;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_161 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha1 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_161 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_161 <= _GEN_483;
      end
    end else begin
      flight_161 <= _GEN_483;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_162 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha2 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_162 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_162 <= _GEN_484;
      end
    end else begin
      flight_162 <= _GEN_484;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_163 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha3 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_163 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_163 <= _GEN_485;
      end
    end else begin
      flight_163 <= _GEN_485;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_164 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha4 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_164 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_164 <= _GEN_486;
      end
    end else begin
      flight_164 <= _GEN_486;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_165 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha5 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_165 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_165 <= _GEN_487;
      end
    end else begin
      flight_165 <= _GEN_487;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_166 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha6 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_166 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_166 <= _GEN_488;
      end
    end else begin
      flight_166 <= _GEN_488;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_167 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha7 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_167 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_167 <= _GEN_489;
      end
    end else begin
      flight_167 <= _GEN_489;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_168 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha8 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_168 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_168 <= _GEN_490;
      end
    end else begin
      flight_168 <= _GEN_490;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_169 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'ha9 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_169 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_169 <= _GEN_491;
      end
    end else begin
      flight_169 <= _GEN_491;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_170 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'haa == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_170 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_170 <= _GEN_492;
      end
    end else begin
      flight_170 <= _GEN_492;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_171 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hab == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_171 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_171 <= _GEN_493;
      end
    end else begin
      flight_171 <= _GEN_493;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_172 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hac == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_172 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_172 <= _GEN_494;
      end
    end else begin
      flight_172 <= _GEN_494;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_173 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'had == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_173 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_173 <= _GEN_495;
      end
    end else begin
      flight_173 <= _GEN_495;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_174 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hae == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_174 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_174 <= _GEN_496;
      end
    end else begin
      flight_174 <= _GEN_496;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_175 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'haf == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_175 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_175 <= _GEN_497;
      end
    end else begin
      flight_175 <= _GEN_497;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_176 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb0 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_176 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_176 <= _GEN_498;
      end
    end else begin
      flight_176 <= _GEN_498;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_177 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb1 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_177 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_177 <= _GEN_499;
      end
    end else begin
      flight_177 <= _GEN_499;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_178 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb2 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_178 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_178 <= _GEN_500;
      end
    end else begin
      flight_178 <= _GEN_500;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_179 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb3 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_179 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_179 <= _GEN_501;
      end
    end else begin
      flight_179 <= _GEN_501;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_180 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb4 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_180 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_180 <= _GEN_502;
      end
    end else begin
      flight_180 <= _GEN_502;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_181 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb5 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_181 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_181 <= _GEN_503;
      end
    end else begin
      flight_181 <= _GEN_503;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_182 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb6 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_182 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_182 <= _GEN_504;
      end
    end else begin
      flight_182 <= _GEN_504;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_183 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb7 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_183 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_183 <= _GEN_505;
      end
    end else begin
      flight_183 <= _GEN_505;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_184 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb8 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_184 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_184 <= _GEN_506;
      end
    end else begin
      flight_184 <= _GEN_506;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_185 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hb9 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_185 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_185 <= _GEN_507;
      end
    end else begin
      flight_185 <= _GEN_507;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_186 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hba == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_186 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_186 <= _GEN_508;
      end
    end else begin
      flight_186 <= _GEN_508;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_187 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hbb == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_187 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_187 <= _GEN_509;
      end
    end else begin
      flight_187 <= _GEN_509;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_188 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hbc == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_188 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_188 <= _GEN_510;
      end
    end else begin
      flight_188 <= _GEN_510;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_189 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hbd == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_189 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_189 <= _GEN_511;
      end
    end else begin
      flight_189 <= _GEN_511;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_190 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hbe == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_190 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_190 <= _GEN_512;
      end
    end else begin
      flight_190 <= _GEN_512;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_191 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hbf == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_191 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_191 <= _GEN_513;
      end
    end else begin
      flight_191 <= _GEN_513;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_192 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc0 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_192 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_192 <= _GEN_514;
      end
    end else begin
      flight_192 <= _GEN_514;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_193 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc1 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_193 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_193 <= _GEN_515;
      end
    end else begin
      flight_193 <= _GEN_515;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_194 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc2 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_194 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_194 <= _GEN_516;
      end
    end else begin
      flight_194 <= _GEN_516;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_195 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc3 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_195 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_195 <= _GEN_517;
      end
    end else begin
      flight_195 <= _GEN_517;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_196 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc4 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_196 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_196 <= _GEN_518;
      end
    end else begin
      flight_196 <= _GEN_518;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_197 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc5 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_197 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_197 <= _GEN_519;
      end
    end else begin
      flight_197 <= _GEN_519;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_198 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc6 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_198 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_198 <= _GEN_520;
      end
    end else begin
      flight_198 <= _GEN_520;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_199 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc7 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_199 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_199 <= _GEN_521;
      end
    end else begin
      flight_199 <= _GEN_521;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_200 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc8 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_200 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_200 <= _GEN_522;
      end
    end else begin
      flight_200 <= _GEN_522;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_201 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hc9 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_201 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_201 <= _GEN_523;
      end
    end else begin
      flight_201 <= _GEN_523;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_202 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hca == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_202 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_202 <= _GEN_524;
      end
    end else begin
      flight_202 <= _GEN_524;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_203 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hcb == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_203 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_203 <= _GEN_525;
      end
    end else begin
      flight_203 <= _GEN_525;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_204 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hcc == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_204 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_204 <= _GEN_526;
      end
    end else begin
      flight_204 <= _GEN_526;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_205 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hcd == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_205 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_205 <= _GEN_527;
      end
    end else begin
      flight_205 <= _GEN_527;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_206 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hce == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_206 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_206 <= _GEN_528;
      end
    end else begin
      flight_206 <= _GEN_528;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_207 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hcf == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_207 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_207 <= _GEN_529;
      end
    end else begin
      flight_207 <= _GEN_529;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_208 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd0 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_208 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_208 <= _GEN_530;
      end
    end else begin
      flight_208 <= _GEN_530;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_209 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd1 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_209 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_209 <= _GEN_531;
      end
    end else begin
      flight_209 <= _GEN_531;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_210 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd2 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_210 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_210 <= _GEN_532;
      end
    end else begin
      flight_210 <= _GEN_532;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_211 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd3 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_211 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_211 <= _GEN_533;
      end
    end else begin
      flight_211 <= _GEN_533;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_212 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd4 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_212 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_212 <= _GEN_534;
      end
    end else begin
      flight_212 <= _GEN_534;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_213 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd5 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_213 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_213 <= _GEN_535;
      end
    end else begin
      flight_213 <= _GEN_535;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_214 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd6 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_214 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_214 <= _GEN_536;
      end
    end else begin
      flight_214 <= _GEN_536;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_215 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd7 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_215 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_215 <= _GEN_537;
      end
    end else begin
      flight_215 <= _GEN_537;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_216 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd8 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_216 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_216 <= _GEN_538;
      end
    end else begin
      flight_216 <= _GEN_538;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_217 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hd9 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_217 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_217 <= _GEN_539;
      end
    end else begin
      flight_217 <= _GEN_539;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_218 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hda == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_218 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_218 <= _GEN_540;
      end
    end else begin
      flight_218 <= _GEN_540;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_219 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hdb == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_219 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_219 <= _GEN_541;
      end
    end else begin
      flight_219 <= _GEN_541;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_220 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hdc == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_220 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_220 <= _GEN_542;
      end
    end else begin
      flight_220 <= _GEN_542;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_221 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hdd == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_221 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_221 <= _GEN_543;
      end
    end else begin
      flight_221 <= _GEN_543;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_222 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hde == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_222 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_222 <= _GEN_544;
      end
    end else begin
      flight_222 <= _GEN_544;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_223 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hdf == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_223 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_223 <= _GEN_545;
      end
    end else begin
      flight_223 <= _GEN_545;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_224 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he0 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_224 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_224 <= _GEN_546;
      end
    end else begin
      flight_224 <= _GEN_546;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_225 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he1 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_225 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_225 <= _GEN_547;
      end
    end else begin
      flight_225 <= _GEN_547;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_226 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he2 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_226 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_226 <= _GEN_548;
      end
    end else begin
      flight_226 <= _GEN_548;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_227 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he3 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_227 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_227 <= _GEN_549;
      end
    end else begin
      flight_227 <= _GEN_549;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_228 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he4 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_228 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_228 <= _GEN_550;
      end
    end else begin
      flight_228 <= _GEN_550;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_229 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he5 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_229 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_229 <= _GEN_551;
      end
    end else begin
      flight_229 <= _GEN_551;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_230 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he6 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_230 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_230 <= _GEN_552;
      end
    end else begin
      flight_230 <= _GEN_552;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_231 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he7 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_231 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_231 <= _GEN_553;
      end
    end else begin
      flight_231 <= _GEN_553;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_232 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he8 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_232 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_232 <= _GEN_554;
      end
    end else begin
      flight_232 <= _GEN_554;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_233 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'he9 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_233 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_233 <= _GEN_555;
      end
    end else begin
      flight_233 <= _GEN_555;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_234 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hea == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_234 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_234 <= _GEN_556;
      end
    end else begin
      flight_234 <= _GEN_556;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_235 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'heb == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_235 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_235 <= _GEN_557;
      end
    end else begin
      flight_235 <= _GEN_557;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_236 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hec == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_236 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_236 <= _GEN_558;
      end
    end else begin
      flight_236 <= _GEN_558;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_237 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hed == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_237 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_237 <= _GEN_559;
      end
    end else begin
      flight_237 <= _GEN_559;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_238 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hee == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_238 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_238 <= _GEN_560;
      end
    end else begin
      flight_238 <= _GEN_560;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_239 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hef == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_239 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_239 <= _GEN_561;
      end
    end else begin
      flight_239 <= _GEN_561;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_240 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf0 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_240 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_240 <= _GEN_562;
      end
    end else begin
      flight_240 <= _GEN_562;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_241 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf1 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_241 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_241 <= _GEN_563;
      end
    end else begin
      flight_241 <= _GEN_563;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_242 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf2 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_242 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_242 <= _GEN_564;
      end
    end else begin
      flight_242 <= _GEN_564;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_243 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf3 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_243 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_243 <= _GEN_565;
      end
    end else begin
      flight_243 <= _GEN_565;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_244 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf4 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_244 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_244 <= _GEN_566;
      end
    end else begin
      flight_244 <= _GEN_566;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_245 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf5 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_245 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_245 <= _GEN_567;
      end
    end else begin
      flight_245 <= _GEN_567;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_246 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf6 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_246 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_246 <= _GEN_568;
      end
    end else begin
      flight_246 <= _GEN_568;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_247 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf7 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_247 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_247 <= _GEN_569;
      end
    end else begin
      flight_247 <= _GEN_569;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_248 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf8 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_248 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_248 <= _GEN_570;
      end
    end else begin
      flight_248 <= _GEN_570;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_249 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hf9 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_249 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_249 <= _GEN_571;
      end
    end else begin
      flight_249 <= _GEN_571;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_250 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hfa == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_250 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_250 <= _GEN_572;
      end
    end else begin
      flight_250 <= _GEN_572;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_251 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hfb == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_251 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_251 <= _GEN_573;
      end
    end else begin
      flight_251 <= _GEN_573;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_252 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hfc == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_252 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_252 <= _GEN_574;
      end
    end else begin
      flight_252 <= _GEN_574;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_253 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hfd == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_253 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_253 <= _GEN_575;
      end
    end else begin
      flight_253 <= _GEN_575;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_254 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hfe == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_254 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_254 <= _GEN_576;
      end
    end else begin
      flight_254 <= _GEN_576;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_255 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'hff == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_255 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_255 <= _GEN_577;
      end
    end else begin
      flight_255 <= _GEN_577;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_256 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h100 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_256 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_256 <= _GEN_578;
      end
    end else begin
      flight_256 <= _GEN_578;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_257 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h101 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_257 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_257 <= _GEN_579;
      end
    end else begin
      flight_257 <= _GEN_579;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_258 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h102 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_258 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_258 <= _GEN_580;
      end
    end else begin
      flight_258 <= _GEN_580;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_259 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h103 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_259 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_259 <= _GEN_581;
      end
    end else begin
      flight_259 <= _GEN_581;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_260 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h104 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_260 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_260 <= _GEN_582;
      end
    end else begin
      flight_260 <= _GEN_582;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_261 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h105 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_261 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_261 <= _GEN_583;
      end
    end else begin
      flight_261 <= _GEN_583;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_262 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h106 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_262 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_262 <= _GEN_584;
      end
    end else begin
      flight_262 <= _GEN_584;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_263 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h107 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_263 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_263 <= _GEN_585;
      end
    end else begin
      flight_263 <= _GEN_585;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_264 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h108 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_264 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_264 <= _GEN_586;
      end
    end else begin
      flight_264 <= _GEN_586;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_265 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h109 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_265 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_265 <= _GEN_587;
      end
    end else begin
      flight_265 <= _GEN_587;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_266 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h10a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_266 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_266 <= _GEN_588;
      end
    end else begin
      flight_266 <= _GEN_588;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_267 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h10b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_267 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_267 <= _GEN_589;
      end
    end else begin
      flight_267 <= _GEN_589;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_268 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h10c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_268 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_268 <= _GEN_590;
      end
    end else begin
      flight_268 <= _GEN_590;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_269 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h10d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_269 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_269 <= _GEN_591;
      end
    end else begin
      flight_269 <= _GEN_591;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_270 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h10e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_270 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_270 <= _GEN_592;
      end
    end else begin
      flight_270 <= _GEN_592;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_271 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h10f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_271 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_271 <= _GEN_593;
      end
    end else begin
      flight_271 <= _GEN_593;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_272 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h110 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_272 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_272 <= _GEN_594;
      end
    end else begin
      flight_272 <= _GEN_594;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_273 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h111 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_273 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_273 <= _GEN_595;
      end
    end else begin
      flight_273 <= _GEN_595;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_274 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h112 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_274 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_274 <= _GEN_596;
      end
    end else begin
      flight_274 <= _GEN_596;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_275 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h113 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_275 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_275 <= _GEN_597;
      end
    end else begin
      flight_275 <= _GEN_597;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_276 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h114 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_276 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_276 <= _GEN_598;
      end
    end else begin
      flight_276 <= _GEN_598;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_277 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h115 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_277 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_277 <= _GEN_599;
      end
    end else begin
      flight_277 <= _GEN_599;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_278 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h116 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_278 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_278 <= _GEN_600;
      end
    end else begin
      flight_278 <= _GEN_600;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_279 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h117 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_279 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_279 <= _GEN_601;
      end
    end else begin
      flight_279 <= _GEN_601;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_280 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h118 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_280 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_280 <= _GEN_602;
      end
    end else begin
      flight_280 <= _GEN_602;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_281 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h119 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_281 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_281 <= _GEN_603;
      end
    end else begin
      flight_281 <= _GEN_603;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_282 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h11a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_282 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_282 <= _GEN_604;
      end
    end else begin
      flight_282 <= _GEN_604;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_283 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h11b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_283 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_283 <= _GEN_605;
      end
    end else begin
      flight_283 <= _GEN_605;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_284 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h11c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_284 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_284 <= _GEN_606;
      end
    end else begin
      flight_284 <= _GEN_606;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_285 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h11d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_285 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_285 <= _GEN_607;
      end
    end else begin
      flight_285 <= _GEN_607;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_286 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h11e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_286 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_286 <= _GEN_608;
      end
    end else begin
      flight_286 <= _GEN_608;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_287 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h11f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_287 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_287 <= _GEN_609;
      end
    end else begin
      flight_287 <= _GEN_609;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_288 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h120 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_288 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_288 <= _GEN_610;
      end
    end else begin
      flight_288 <= _GEN_610;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_289 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h121 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_289 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_289 <= _GEN_611;
      end
    end else begin
      flight_289 <= _GEN_611;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_290 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h122 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_290 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_290 <= _GEN_612;
      end
    end else begin
      flight_290 <= _GEN_612;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_291 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h123 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_291 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_291 <= _GEN_613;
      end
    end else begin
      flight_291 <= _GEN_613;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_292 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h124 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_292 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_292 <= _GEN_614;
      end
    end else begin
      flight_292 <= _GEN_614;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_293 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h125 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_293 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_293 <= _GEN_615;
      end
    end else begin
      flight_293 <= _GEN_615;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_294 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h126 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_294 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_294 <= _GEN_616;
      end
    end else begin
      flight_294 <= _GEN_616;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_295 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h127 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_295 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_295 <= _GEN_617;
      end
    end else begin
      flight_295 <= _GEN_617;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_296 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h128 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_296 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_296 <= _GEN_618;
      end
    end else begin
      flight_296 <= _GEN_618;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_297 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h129 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_297 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_297 <= _GEN_619;
      end
    end else begin
      flight_297 <= _GEN_619;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_298 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h12a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_298 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_298 <= _GEN_620;
      end
    end else begin
      flight_298 <= _GEN_620;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_299 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h12b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_299 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_299 <= _GEN_621;
      end
    end else begin
      flight_299 <= _GEN_621;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_300 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h12c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_300 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_300 <= _GEN_622;
      end
    end else begin
      flight_300 <= _GEN_622;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_301 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h12d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_301 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_301 <= _GEN_623;
      end
    end else begin
      flight_301 <= _GEN_623;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_302 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h12e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_302 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_302 <= _GEN_624;
      end
    end else begin
      flight_302 <= _GEN_624;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_303 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h12f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_303 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_303 <= _GEN_625;
      end
    end else begin
      flight_303 <= _GEN_625;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_304 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h130 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_304 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_304 <= _GEN_626;
      end
    end else begin
      flight_304 <= _GEN_626;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_305 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h131 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_305 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_305 <= _GEN_627;
      end
    end else begin
      flight_305 <= _GEN_627;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_306 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h132 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_306 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_306 <= _GEN_628;
      end
    end else begin
      flight_306 <= _GEN_628;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_307 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h133 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_307 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_307 <= _GEN_629;
      end
    end else begin
      flight_307 <= _GEN_629;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_308 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h134 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_308 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_308 <= _GEN_630;
      end
    end else begin
      flight_308 <= _GEN_630;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_309 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h135 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_309 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_309 <= _GEN_631;
      end
    end else begin
      flight_309 <= _GEN_631;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_310 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h136 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_310 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_310 <= _GEN_632;
      end
    end else begin
      flight_310 <= _GEN_632;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_311 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h137 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_311 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_311 <= _GEN_633;
      end
    end else begin
      flight_311 <= _GEN_633;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_312 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h138 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_312 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_312 <= _GEN_634;
      end
    end else begin
      flight_312 <= _GEN_634;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_313 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h139 == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_313 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_313 <= _GEN_635;
      end
    end else begin
      flight_313 <= _GEN_635;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_314 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h13a == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_314 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_314 <= _GEN_636;
      end
    end else begin
      flight_314 <= _GEN_636;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_315 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h13b == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_315 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_315 <= _GEN_637;
      end
    end else begin
      flight_315 <= _GEN_637;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_316 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h13c == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_316 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_316 <= _GEN_638;
      end
    end else begin
      flight_316 <= _GEN_638;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_317 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h13d == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_317 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_317 <= _GEN_639;
      end
    end else begin
      flight_317 <= _GEN_639;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_318 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h13e == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_318 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_318 <= _GEN_640;
      end
    end else begin
      flight_318 <= _GEN_640;
    end
    if (reset) begin // @[FIFOFixer.scala 71:27]
      flight_319 <= 1'h0; // @[FIFOFixer.scala 71:27]
    end else if (d_first & _d_first_T) begin // @[FIFOFixer.scala 73:37]
      if (9'h13f == auto_out_d_bits_source) begin // @[FIFOFixer.scala 73:64]
        flight_319 <= 1'h0; // @[FIFOFixer.scala 73:64]
      end else begin
        flight_319 <= _GEN_641;
      end
    end else begin
      flight_319 <= _GEN_641;
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  flight_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  flight_1 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  flight_2 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  flight_3 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  flight_4 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  flight_5 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  flight_6 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  flight_7 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  flight_8 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  flight_9 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  flight_10 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  flight_11 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  flight_12 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  flight_13 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  flight_14 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  flight_15 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  flight_16 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  flight_17 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  flight_18 = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  flight_19 = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  flight_20 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  flight_21 = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  flight_22 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  flight_23 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  flight_24 = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  flight_25 = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  flight_26 = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  flight_27 = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  flight_28 = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  flight_29 = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  flight_30 = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  flight_31 = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  flight_32 = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  flight_33 = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  flight_34 = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  flight_35 = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  flight_36 = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  flight_37 = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  flight_38 = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  flight_39 = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  flight_40 = _RAND_41[0:0];
  _RAND_42 = {1{`RANDOM}};
  flight_41 = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  flight_42 = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  flight_43 = _RAND_44[0:0];
  _RAND_45 = {1{`RANDOM}};
  flight_44 = _RAND_45[0:0];
  _RAND_46 = {1{`RANDOM}};
  flight_45 = _RAND_46[0:0];
  _RAND_47 = {1{`RANDOM}};
  flight_46 = _RAND_47[0:0];
  _RAND_48 = {1{`RANDOM}};
  flight_47 = _RAND_48[0:0];
  _RAND_49 = {1{`RANDOM}};
  flight_48 = _RAND_49[0:0];
  _RAND_50 = {1{`RANDOM}};
  flight_49 = _RAND_50[0:0];
  _RAND_51 = {1{`RANDOM}};
  flight_50 = _RAND_51[0:0];
  _RAND_52 = {1{`RANDOM}};
  flight_51 = _RAND_52[0:0];
  _RAND_53 = {1{`RANDOM}};
  flight_52 = _RAND_53[0:0];
  _RAND_54 = {1{`RANDOM}};
  flight_53 = _RAND_54[0:0];
  _RAND_55 = {1{`RANDOM}};
  flight_54 = _RAND_55[0:0];
  _RAND_56 = {1{`RANDOM}};
  flight_55 = _RAND_56[0:0];
  _RAND_57 = {1{`RANDOM}};
  flight_56 = _RAND_57[0:0];
  _RAND_58 = {1{`RANDOM}};
  flight_57 = _RAND_58[0:0];
  _RAND_59 = {1{`RANDOM}};
  flight_58 = _RAND_59[0:0];
  _RAND_60 = {1{`RANDOM}};
  flight_59 = _RAND_60[0:0];
  _RAND_61 = {1{`RANDOM}};
  flight_60 = _RAND_61[0:0];
  _RAND_62 = {1{`RANDOM}};
  flight_61 = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  flight_62 = _RAND_63[0:0];
  _RAND_64 = {1{`RANDOM}};
  flight_63 = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  flight_64 = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  flight_65 = _RAND_66[0:0];
  _RAND_67 = {1{`RANDOM}};
  flight_66 = _RAND_67[0:0];
  _RAND_68 = {1{`RANDOM}};
  flight_67 = _RAND_68[0:0];
  _RAND_69 = {1{`RANDOM}};
  flight_68 = _RAND_69[0:0];
  _RAND_70 = {1{`RANDOM}};
  flight_69 = _RAND_70[0:0];
  _RAND_71 = {1{`RANDOM}};
  flight_70 = _RAND_71[0:0];
  _RAND_72 = {1{`RANDOM}};
  flight_71 = _RAND_72[0:0];
  _RAND_73 = {1{`RANDOM}};
  flight_72 = _RAND_73[0:0];
  _RAND_74 = {1{`RANDOM}};
  flight_73 = _RAND_74[0:0];
  _RAND_75 = {1{`RANDOM}};
  flight_74 = _RAND_75[0:0];
  _RAND_76 = {1{`RANDOM}};
  flight_75 = _RAND_76[0:0];
  _RAND_77 = {1{`RANDOM}};
  flight_76 = _RAND_77[0:0];
  _RAND_78 = {1{`RANDOM}};
  flight_77 = _RAND_78[0:0];
  _RAND_79 = {1{`RANDOM}};
  flight_78 = _RAND_79[0:0];
  _RAND_80 = {1{`RANDOM}};
  flight_79 = _RAND_80[0:0];
  _RAND_81 = {1{`RANDOM}};
  flight_80 = _RAND_81[0:0];
  _RAND_82 = {1{`RANDOM}};
  flight_81 = _RAND_82[0:0];
  _RAND_83 = {1{`RANDOM}};
  flight_82 = _RAND_83[0:0];
  _RAND_84 = {1{`RANDOM}};
  flight_83 = _RAND_84[0:0];
  _RAND_85 = {1{`RANDOM}};
  flight_84 = _RAND_85[0:0];
  _RAND_86 = {1{`RANDOM}};
  flight_85 = _RAND_86[0:0];
  _RAND_87 = {1{`RANDOM}};
  flight_86 = _RAND_87[0:0];
  _RAND_88 = {1{`RANDOM}};
  flight_87 = _RAND_88[0:0];
  _RAND_89 = {1{`RANDOM}};
  flight_88 = _RAND_89[0:0];
  _RAND_90 = {1{`RANDOM}};
  flight_89 = _RAND_90[0:0];
  _RAND_91 = {1{`RANDOM}};
  flight_90 = _RAND_91[0:0];
  _RAND_92 = {1{`RANDOM}};
  flight_91 = _RAND_92[0:0];
  _RAND_93 = {1{`RANDOM}};
  flight_92 = _RAND_93[0:0];
  _RAND_94 = {1{`RANDOM}};
  flight_93 = _RAND_94[0:0];
  _RAND_95 = {1{`RANDOM}};
  flight_94 = _RAND_95[0:0];
  _RAND_96 = {1{`RANDOM}};
  flight_95 = _RAND_96[0:0];
  _RAND_97 = {1{`RANDOM}};
  flight_96 = _RAND_97[0:0];
  _RAND_98 = {1{`RANDOM}};
  flight_97 = _RAND_98[0:0];
  _RAND_99 = {1{`RANDOM}};
  flight_98 = _RAND_99[0:0];
  _RAND_100 = {1{`RANDOM}};
  flight_99 = _RAND_100[0:0];
  _RAND_101 = {1{`RANDOM}};
  flight_100 = _RAND_101[0:0];
  _RAND_102 = {1{`RANDOM}};
  flight_101 = _RAND_102[0:0];
  _RAND_103 = {1{`RANDOM}};
  flight_102 = _RAND_103[0:0];
  _RAND_104 = {1{`RANDOM}};
  flight_103 = _RAND_104[0:0];
  _RAND_105 = {1{`RANDOM}};
  flight_104 = _RAND_105[0:0];
  _RAND_106 = {1{`RANDOM}};
  flight_105 = _RAND_106[0:0];
  _RAND_107 = {1{`RANDOM}};
  flight_106 = _RAND_107[0:0];
  _RAND_108 = {1{`RANDOM}};
  flight_107 = _RAND_108[0:0];
  _RAND_109 = {1{`RANDOM}};
  flight_108 = _RAND_109[0:0];
  _RAND_110 = {1{`RANDOM}};
  flight_109 = _RAND_110[0:0];
  _RAND_111 = {1{`RANDOM}};
  flight_110 = _RAND_111[0:0];
  _RAND_112 = {1{`RANDOM}};
  flight_111 = _RAND_112[0:0];
  _RAND_113 = {1{`RANDOM}};
  flight_112 = _RAND_113[0:0];
  _RAND_114 = {1{`RANDOM}};
  flight_113 = _RAND_114[0:0];
  _RAND_115 = {1{`RANDOM}};
  flight_114 = _RAND_115[0:0];
  _RAND_116 = {1{`RANDOM}};
  flight_115 = _RAND_116[0:0];
  _RAND_117 = {1{`RANDOM}};
  flight_116 = _RAND_117[0:0];
  _RAND_118 = {1{`RANDOM}};
  flight_117 = _RAND_118[0:0];
  _RAND_119 = {1{`RANDOM}};
  flight_118 = _RAND_119[0:0];
  _RAND_120 = {1{`RANDOM}};
  flight_119 = _RAND_120[0:0];
  _RAND_121 = {1{`RANDOM}};
  flight_120 = _RAND_121[0:0];
  _RAND_122 = {1{`RANDOM}};
  flight_121 = _RAND_122[0:0];
  _RAND_123 = {1{`RANDOM}};
  flight_122 = _RAND_123[0:0];
  _RAND_124 = {1{`RANDOM}};
  flight_123 = _RAND_124[0:0];
  _RAND_125 = {1{`RANDOM}};
  flight_124 = _RAND_125[0:0];
  _RAND_126 = {1{`RANDOM}};
  flight_125 = _RAND_126[0:0];
  _RAND_127 = {1{`RANDOM}};
  flight_126 = _RAND_127[0:0];
  _RAND_128 = {1{`RANDOM}};
  flight_127 = _RAND_128[0:0];
  _RAND_129 = {1{`RANDOM}};
  flight_128 = _RAND_129[0:0];
  _RAND_130 = {1{`RANDOM}};
  flight_129 = _RAND_130[0:0];
  _RAND_131 = {1{`RANDOM}};
  flight_130 = _RAND_131[0:0];
  _RAND_132 = {1{`RANDOM}};
  flight_131 = _RAND_132[0:0];
  _RAND_133 = {1{`RANDOM}};
  flight_132 = _RAND_133[0:0];
  _RAND_134 = {1{`RANDOM}};
  flight_133 = _RAND_134[0:0];
  _RAND_135 = {1{`RANDOM}};
  flight_134 = _RAND_135[0:0];
  _RAND_136 = {1{`RANDOM}};
  flight_135 = _RAND_136[0:0];
  _RAND_137 = {1{`RANDOM}};
  flight_136 = _RAND_137[0:0];
  _RAND_138 = {1{`RANDOM}};
  flight_137 = _RAND_138[0:0];
  _RAND_139 = {1{`RANDOM}};
  flight_138 = _RAND_139[0:0];
  _RAND_140 = {1{`RANDOM}};
  flight_139 = _RAND_140[0:0];
  _RAND_141 = {1{`RANDOM}};
  flight_140 = _RAND_141[0:0];
  _RAND_142 = {1{`RANDOM}};
  flight_141 = _RAND_142[0:0];
  _RAND_143 = {1{`RANDOM}};
  flight_142 = _RAND_143[0:0];
  _RAND_144 = {1{`RANDOM}};
  flight_143 = _RAND_144[0:0];
  _RAND_145 = {1{`RANDOM}};
  flight_144 = _RAND_145[0:0];
  _RAND_146 = {1{`RANDOM}};
  flight_145 = _RAND_146[0:0];
  _RAND_147 = {1{`RANDOM}};
  flight_146 = _RAND_147[0:0];
  _RAND_148 = {1{`RANDOM}};
  flight_147 = _RAND_148[0:0];
  _RAND_149 = {1{`RANDOM}};
  flight_148 = _RAND_149[0:0];
  _RAND_150 = {1{`RANDOM}};
  flight_149 = _RAND_150[0:0];
  _RAND_151 = {1{`RANDOM}};
  flight_150 = _RAND_151[0:0];
  _RAND_152 = {1{`RANDOM}};
  flight_151 = _RAND_152[0:0];
  _RAND_153 = {1{`RANDOM}};
  flight_152 = _RAND_153[0:0];
  _RAND_154 = {1{`RANDOM}};
  flight_153 = _RAND_154[0:0];
  _RAND_155 = {1{`RANDOM}};
  flight_154 = _RAND_155[0:0];
  _RAND_156 = {1{`RANDOM}};
  flight_155 = _RAND_156[0:0];
  _RAND_157 = {1{`RANDOM}};
  flight_156 = _RAND_157[0:0];
  _RAND_158 = {1{`RANDOM}};
  flight_157 = _RAND_158[0:0];
  _RAND_159 = {1{`RANDOM}};
  flight_158 = _RAND_159[0:0];
  _RAND_160 = {1{`RANDOM}};
  flight_159 = _RAND_160[0:0];
  _RAND_161 = {1{`RANDOM}};
  flight_160 = _RAND_161[0:0];
  _RAND_162 = {1{`RANDOM}};
  flight_161 = _RAND_162[0:0];
  _RAND_163 = {1{`RANDOM}};
  flight_162 = _RAND_163[0:0];
  _RAND_164 = {1{`RANDOM}};
  flight_163 = _RAND_164[0:0];
  _RAND_165 = {1{`RANDOM}};
  flight_164 = _RAND_165[0:0];
  _RAND_166 = {1{`RANDOM}};
  flight_165 = _RAND_166[0:0];
  _RAND_167 = {1{`RANDOM}};
  flight_166 = _RAND_167[0:0];
  _RAND_168 = {1{`RANDOM}};
  flight_167 = _RAND_168[0:0];
  _RAND_169 = {1{`RANDOM}};
  flight_168 = _RAND_169[0:0];
  _RAND_170 = {1{`RANDOM}};
  flight_169 = _RAND_170[0:0];
  _RAND_171 = {1{`RANDOM}};
  flight_170 = _RAND_171[0:0];
  _RAND_172 = {1{`RANDOM}};
  flight_171 = _RAND_172[0:0];
  _RAND_173 = {1{`RANDOM}};
  flight_172 = _RAND_173[0:0];
  _RAND_174 = {1{`RANDOM}};
  flight_173 = _RAND_174[0:0];
  _RAND_175 = {1{`RANDOM}};
  flight_174 = _RAND_175[0:0];
  _RAND_176 = {1{`RANDOM}};
  flight_175 = _RAND_176[0:0];
  _RAND_177 = {1{`RANDOM}};
  flight_176 = _RAND_177[0:0];
  _RAND_178 = {1{`RANDOM}};
  flight_177 = _RAND_178[0:0];
  _RAND_179 = {1{`RANDOM}};
  flight_178 = _RAND_179[0:0];
  _RAND_180 = {1{`RANDOM}};
  flight_179 = _RAND_180[0:0];
  _RAND_181 = {1{`RANDOM}};
  flight_180 = _RAND_181[0:0];
  _RAND_182 = {1{`RANDOM}};
  flight_181 = _RAND_182[0:0];
  _RAND_183 = {1{`RANDOM}};
  flight_182 = _RAND_183[0:0];
  _RAND_184 = {1{`RANDOM}};
  flight_183 = _RAND_184[0:0];
  _RAND_185 = {1{`RANDOM}};
  flight_184 = _RAND_185[0:0];
  _RAND_186 = {1{`RANDOM}};
  flight_185 = _RAND_186[0:0];
  _RAND_187 = {1{`RANDOM}};
  flight_186 = _RAND_187[0:0];
  _RAND_188 = {1{`RANDOM}};
  flight_187 = _RAND_188[0:0];
  _RAND_189 = {1{`RANDOM}};
  flight_188 = _RAND_189[0:0];
  _RAND_190 = {1{`RANDOM}};
  flight_189 = _RAND_190[0:0];
  _RAND_191 = {1{`RANDOM}};
  flight_190 = _RAND_191[0:0];
  _RAND_192 = {1{`RANDOM}};
  flight_191 = _RAND_192[0:0];
  _RAND_193 = {1{`RANDOM}};
  flight_192 = _RAND_193[0:0];
  _RAND_194 = {1{`RANDOM}};
  flight_193 = _RAND_194[0:0];
  _RAND_195 = {1{`RANDOM}};
  flight_194 = _RAND_195[0:0];
  _RAND_196 = {1{`RANDOM}};
  flight_195 = _RAND_196[0:0];
  _RAND_197 = {1{`RANDOM}};
  flight_196 = _RAND_197[0:0];
  _RAND_198 = {1{`RANDOM}};
  flight_197 = _RAND_198[0:0];
  _RAND_199 = {1{`RANDOM}};
  flight_198 = _RAND_199[0:0];
  _RAND_200 = {1{`RANDOM}};
  flight_199 = _RAND_200[0:0];
  _RAND_201 = {1{`RANDOM}};
  flight_200 = _RAND_201[0:0];
  _RAND_202 = {1{`RANDOM}};
  flight_201 = _RAND_202[0:0];
  _RAND_203 = {1{`RANDOM}};
  flight_202 = _RAND_203[0:0];
  _RAND_204 = {1{`RANDOM}};
  flight_203 = _RAND_204[0:0];
  _RAND_205 = {1{`RANDOM}};
  flight_204 = _RAND_205[0:0];
  _RAND_206 = {1{`RANDOM}};
  flight_205 = _RAND_206[0:0];
  _RAND_207 = {1{`RANDOM}};
  flight_206 = _RAND_207[0:0];
  _RAND_208 = {1{`RANDOM}};
  flight_207 = _RAND_208[0:0];
  _RAND_209 = {1{`RANDOM}};
  flight_208 = _RAND_209[0:0];
  _RAND_210 = {1{`RANDOM}};
  flight_209 = _RAND_210[0:0];
  _RAND_211 = {1{`RANDOM}};
  flight_210 = _RAND_211[0:0];
  _RAND_212 = {1{`RANDOM}};
  flight_211 = _RAND_212[0:0];
  _RAND_213 = {1{`RANDOM}};
  flight_212 = _RAND_213[0:0];
  _RAND_214 = {1{`RANDOM}};
  flight_213 = _RAND_214[0:0];
  _RAND_215 = {1{`RANDOM}};
  flight_214 = _RAND_215[0:0];
  _RAND_216 = {1{`RANDOM}};
  flight_215 = _RAND_216[0:0];
  _RAND_217 = {1{`RANDOM}};
  flight_216 = _RAND_217[0:0];
  _RAND_218 = {1{`RANDOM}};
  flight_217 = _RAND_218[0:0];
  _RAND_219 = {1{`RANDOM}};
  flight_218 = _RAND_219[0:0];
  _RAND_220 = {1{`RANDOM}};
  flight_219 = _RAND_220[0:0];
  _RAND_221 = {1{`RANDOM}};
  flight_220 = _RAND_221[0:0];
  _RAND_222 = {1{`RANDOM}};
  flight_221 = _RAND_222[0:0];
  _RAND_223 = {1{`RANDOM}};
  flight_222 = _RAND_223[0:0];
  _RAND_224 = {1{`RANDOM}};
  flight_223 = _RAND_224[0:0];
  _RAND_225 = {1{`RANDOM}};
  flight_224 = _RAND_225[0:0];
  _RAND_226 = {1{`RANDOM}};
  flight_225 = _RAND_226[0:0];
  _RAND_227 = {1{`RANDOM}};
  flight_226 = _RAND_227[0:0];
  _RAND_228 = {1{`RANDOM}};
  flight_227 = _RAND_228[0:0];
  _RAND_229 = {1{`RANDOM}};
  flight_228 = _RAND_229[0:0];
  _RAND_230 = {1{`RANDOM}};
  flight_229 = _RAND_230[0:0];
  _RAND_231 = {1{`RANDOM}};
  flight_230 = _RAND_231[0:0];
  _RAND_232 = {1{`RANDOM}};
  flight_231 = _RAND_232[0:0];
  _RAND_233 = {1{`RANDOM}};
  flight_232 = _RAND_233[0:0];
  _RAND_234 = {1{`RANDOM}};
  flight_233 = _RAND_234[0:0];
  _RAND_235 = {1{`RANDOM}};
  flight_234 = _RAND_235[0:0];
  _RAND_236 = {1{`RANDOM}};
  flight_235 = _RAND_236[0:0];
  _RAND_237 = {1{`RANDOM}};
  flight_236 = _RAND_237[0:0];
  _RAND_238 = {1{`RANDOM}};
  flight_237 = _RAND_238[0:0];
  _RAND_239 = {1{`RANDOM}};
  flight_238 = _RAND_239[0:0];
  _RAND_240 = {1{`RANDOM}};
  flight_239 = _RAND_240[0:0];
  _RAND_241 = {1{`RANDOM}};
  flight_240 = _RAND_241[0:0];
  _RAND_242 = {1{`RANDOM}};
  flight_241 = _RAND_242[0:0];
  _RAND_243 = {1{`RANDOM}};
  flight_242 = _RAND_243[0:0];
  _RAND_244 = {1{`RANDOM}};
  flight_243 = _RAND_244[0:0];
  _RAND_245 = {1{`RANDOM}};
  flight_244 = _RAND_245[0:0];
  _RAND_246 = {1{`RANDOM}};
  flight_245 = _RAND_246[0:0];
  _RAND_247 = {1{`RANDOM}};
  flight_246 = _RAND_247[0:0];
  _RAND_248 = {1{`RANDOM}};
  flight_247 = _RAND_248[0:0];
  _RAND_249 = {1{`RANDOM}};
  flight_248 = _RAND_249[0:0];
  _RAND_250 = {1{`RANDOM}};
  flight_249 = _RAND_250[0:0];
  _RAND_251 = {1{`RANDOM}};
  flight_250 = _RAND_251[0:0];
  _RAND_252 = {1{`RANDOM}};
  flight_251 = _RAND_252[0:0];
  _RAND_253 = {1{`RANDOM}};
  flight_252 = _RAND_253[0:0];
  _RAND_254 = {1{`RANDOM}};
  flight_253 = _RAND_254[0:0];
  _RAND_255 = {1{`RANDOM}};
  flight_254 = _RAND_255[0:0];
  _RAND_256 = {1{`RANDOM}};
  flight_255 = _RAND_256[0:0];
  _RAND_257 = {1{`RANDOM}};
  flight_256 = _RAND_257[0:0];
  _RAND_258 = {1{`RANDOM}};
  flight_257 = _RAND_258[0:0];
  _RAND_259 = {1{`RANDOM}};
  flight_258 = _RAND_259[0:0];
  _RAND_260 = {1{`RANDOM}};
  flight_259 = _RAND_260[0:0];
  _RAND_261 = {1{`RANDOM}};
  flight_260 = _RAND_261[0:0];
  _RAND_262 = {1{`RANDOM}};
  flight_261 = _RAND_262[0:0];
  _RAND_263 = {1{`RANDOM}};
  flight_262 = _RAND_263[0:0];
  _RAND_264 = {1{`RANDOM}};
  flight_263 = _RAND_264[0:0];
  _RAND_265 = {1{`RANDOM}};
  flight_264 = _RAND_265[0:0];
  _RAND_266 = {1{`RANDOM}};
  flight_265 = _RAND_266[0:0];
  _RAND_267 = {1{`RANDOM}};
  flight_266 = _RAND_267[0:0];
  _RAND_268 = {1{`RANDOM}};
  flight_267 = _RAND_268[0:0];
  _RAND_269 = {1{`RANDOM}};
  flight_268 = _RAND_269[0:0];
  _RAND_270 = {1{`RANDOM}};
  flight_269 = _RAND_270[0:0];
  _RAND_271 = {1{`RANDOM}};
  flight_270 = _RAND_271[0:0];
  _RAND_272 = {1{`RANDOM}};
  flight_271 = _RAND_272[0:0];
  _RAND_273 = {1{`RANDOM}};
  flight_272 = _RAND_273[0:0];
  _RAND_274 = {1{`RANDOM}};
  flight_273 = _RAND_274[0:0];
  _RAND_275 = {1{`RANDOM}};
  flight_274 = _RAND_275[0:0];
  _RAND_276 = {1{`RANDOM}};
  flight_275 = _RAND_276[0:0];
  _RAND_277 = {1{`RANDOM}};
  flight_276 = _RAND_277[0:0];
  _RAND_278 = {1{`RANDOM}};
  flight_277 = _RAND_278[0:0];
  _RAND_279 = {1{`RANDOM}};
  flight_278 = _RAND_279[0:0];
  _RAND_280 = {1{`RANDOM}};
  flight_279 = _RAND_280[0:0];
  _RAND_281 = {1{`RANDOM}};
  flight_280 = _RAND_281[0:0];
  _RAND_282 = {1{`RANDOM}};
  flight_281 = _RAND_282[0:0];
  _RAND_283 = {1{`RANDOM}};
  flight_282 = _RAND_283[0:0];
  _RAND_284 = {1{`RANDOM}};
  flight_283 = _RAND_284[0:0];
  _RAND_285 = {1{`RANDOM}};
  flight_284 = _RAND_285[0:0];
  _RAND_286 = {1{`RANDOM}};
  flight_285 = _RAND_286[0:0];
  _RAND_287 = {1{`RANDOM}};
  flight_286 = _RAND_287[0:0];
  _RAND_288 = {1{`RANDOM}};
  flight_287 = _RAND_288[0:0];
  _RAND_289 = {1{`RANDOM}};
  flight_288 = _RAND_289[0:0];
  _RAND_290 = {1{`RANDOM}};
  flight_289 = _RAND_290[0:0];
  _RAND_291 = {1{`RANDOM}};
  flight_290 = _RAND_291[0:0];
  _RAND_292 = {1{`RANDOM}};
  flight_291 = _RAND_292[0:0];
  _RAND_293 = {1{`RANDOM}};
  flight_292 = _RAND_293[0:0];
  _RAND_294 = {1{`RANDOM}};
  flight_293 = _RAND_294[0:0];
  _RAND_295 = {1{`RANDOM}};
  flight_294 = _RAND_295[0:0];
  _RAND_296 = {1{`RANDOM}};
  flight_295 = _RAND_296[0:0];
  _RAND_297 = {1{`RANDOM}};
  flight_296 = _RAND_297[0:0];
  _RAND_298 = {1{`RANDOM}};
  flight_297 = _RAND_298[0:0];
  _RAND_299 = {1{`RANDOM}};
  flight_298 = _RAND_299[0:0];
  _RAND_300 = {1{`RANDOM}};
  flight_299 = _RAND_300[0:0];
  _RAND_301 = {1{`RANDOM}};
  flight_300 = _RAND_301[0:0];
  _RAND_302 = {1{`RANDOM}};
  flight_301 = _RAND_302[0:0];
  _RAND_303 = {1{`RANDOM}};
  flight_302 = _RAND_303[0:0];
  _RAND_304 = {1{`RANDOM}};
  flight_303 = _RAND_304[0:0];
  _RAND_305 = {1{`RANDOM}};
  flight_304 = _RAND_305[0:0];
  _RAND_306 = {1{`RANDOM}};
  flight_305 = _RAND_306[0:0];
  _RAND_307 = {1{`RANDOM}};
  flight_306 = _RAND_307[0:0];
  _RAND_308 = {1{`RANDOM}};
  flight_307 = _RAND_308[0:0];
  _RAND_309 = {1{`RANDOM}};
  flight_308 = _RAND_309[0:0];
  _RAND_310 = {1{`RANDOM}};
  flight_309 = _RAND_310[0:0];
  _RAND_311 = {1{`RANDOM}};
  flight_310 = _RAND_311[0:0];
  _RAND_312 = {1{`RANDOM}};
  flight_311 = _RAND_312[0:0];
  _RAND_313 = {1{`RANDOM}};
  flight_312 = _RAND_313[0:0];
  _RAND_314 = {1{`RANDOM}};
  flight_313 = _RAND_314[0:0];
  _RAND_315 = {1{`RANDOM}};
  flight_314 = _RAND_315[0:0];
  _RAND_316 = {1{`RANDOM}};
  flight_315 = _RAND_316[0:0];
  _RAND_317 = {1{`RANDOM}};
  flight_316 = _RAND_317[0:0];
  _RAND_318 = {1{`RANDOM}};
  flight_317 = _RAND_318[0:0];
  _RAND_319 = {1{`RANDOM}};
  flight_318 = _RAND_319[0:0];
  _RAND_320 = {1{`RANDOM}};
  flight_319 = _RAND_320[0:0];
  _RAND_321 = {1{`RANDOM}};
  d_first_counter = _RAND_321[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_10(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [5:0]  io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [5:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [63:0] _RAND_10;
  reg [159:0] _RAND_11;
  reg [159:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [63:0] _RAND_16;
  reg [159:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 6'h27; // @[Parameters.scala 57:20]
  wire [11:0] _is_aligned_mask_T_1 = 12'h1f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [4:0] is_aligned_mask = ~_is_aligned_mask_T_1[4:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_15 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_15; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire [32:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [32:0] _T_36 = $signed(_T_12) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_165 = 3'h3 <= io_in_a_bits_size & io_in_a_bits_size <= 3'h5; // @[Parameters.scala 92:37]
  wire  _T_172 = _T_165 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 6'h27; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire [1:0] a_first_beats1_decode = is_aligned_mask[4:3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [1:0] a_first_counter; // @[Edges.scala 228:27]
  wire [1:0] a_first_counter1 = a_first_counter - 2'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 2'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [5:0] source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [11:0] _d_first_beats1_decode_T_1 = 12'h1f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [4:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[4:0]; // @[package.scala 234:46]
  wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[4:3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [1:0] d_first_counter; // @[Edges.scala 228:27]
  wire [1:0] d_first_counter1 = d_first_counter - 2'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 2'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [5:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [39:0] inflight; // @[Monitor.scala 611:27]
  reg [159:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [159:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [1:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [1:0] a_first_counter1_1 = a_first_counter_1 - 2'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala 230:25]
  reg [1:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [1:0] d_first_counter1_1 = d_first_counter_1 - 2'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala 230:25]
  wire [7:0] _GEN_21 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [8:0] _a_opcode_lookup_T = {{1'd0}, _GEN_21}; // @[Monitor.scala 634:69]
  wire [159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [159:0] _GEN_60 = {{144'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [159:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_60; // @[Monitor.scala 634:97]
  wire [159:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[159:1]}; // @[Monitor.scala 634:152]
  wire [159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [159:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_60; // @[Monitor.scala 638:91]
  wire [159:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[159:1]}; // @[Monitor.scala 638:144]
  wire  _T_597 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [63:0] _a_set_T = 64'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [7:0] _GEN_71 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [8:0] _a_opcodes_set_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [514:0] _GEN_305 = {{511'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [514:0] _a_opcodes_set_T_1 = _GEN_305 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [514:0] _GEN_306 = {{511'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [514:0] _a_sizes_set_T_1 = _GEN_306 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [39:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [63:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_T : 64'h0; // @[Monitor.scala 652:72 653:28]
  wire [514:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 515'h0; // @[Monitor.scala 652:72 656:28]
  wire [514:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 515'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_612 = ~_T_401; // @[Monitor.scala 675:75]
  wire [63:0] _d_clr_T = 64'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [526:0] _GEN_307 = {{511'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [526:0] _d_opcodes_clr_T_5 = _GEN_307 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [63:0] _GEN_22 = _d_first_T & d_first_1 & ~_T_401 ? _d_clr_T : 64'h0; // @[Monitor.scala 675:91 676:21]
  wire [526:0] _GEN_23 = _d_first_T & d_first_1 & ~_T_401 ? _d_opcodes_clr_T_5 : 527'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_614 = io_in_d_valid & d_first_1; // @[Monitor.scala 680:26]
  wire  _T_617 = io_in_d_valid & d_first_1 & _T_612; // @[Monitor.scala 680:71]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = io_in_a_valid & a_first_1 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [39:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_75 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_614 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_612; // @[Monitor.scala 694:116]
  wire  _T_653 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [39:0] a_set = _GEN_16[39:0];
  wire [39:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [39:0] d_clr = _GEN_22[39:0];
  wire [39:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [39:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [159:0] a_opcodes_set = _GEN_19[159:0];
  wire [159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [159:0] d_opcodes_clr = _GEN_23[159:0];
  wire [159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [159:0] a_sizes_set = _GEN_20[159:0];
  wire [159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [39:0] inflight_1; // @[Monitor.scala 723:35]
  reg [159:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [1:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [1:0] d_first_counter1_2 = d_first_counter_2 - 2'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala 230:25]
  wire [159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [159:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_60; // @[Monitor.scala 747:93]
  wire [159:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[159:1]}; // @[Monitor.scala 747:146]
  wire  _T_683 = ~inflight_1[0]; // @[Monitor.scala 766:17]
  wire [63:0] _GEN_67 = _d_first_T & d_first_2 & _T_401 ? _d_clr_T : 64'h0; // @[Monitor.scala 783:90 784:21]
  wire [526:0] _GEN_69 = _d_first_T & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 527'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 789:71]
  wire [39:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_703 = io_in_d_bits_size == 3'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [39:0] d_clr_1 = _GEN_67[39:0];
  wire [39:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [39:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [159:0] d_sizes_clr_1 = _GEN_69[159:0];
  wire [159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [159:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 2'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 2'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 2'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 2'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 40'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 160'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 160'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 2'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 2'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 2'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 2'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 40'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 160'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 2'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 2'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_617 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_617 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_617 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_617 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_617 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_617 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_617 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_617 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_617 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_617 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_683 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_703 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:71:71)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[5:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[5:0];
  _RAND_10 = {2{`RANDOM}};
  inflight = _RAND_10[39:0];
  _RAND_11 = {5{`RANDOM}};
  inflight_opcodes = _RAND_11[159:0];
  _RAND_12 = {5{`RANDOM}};
  inflight_sizes = _RAND_12[159:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {2{`RANDOM}};
  inflight_1 = _RAND_16[39:0];
  _RAND_17 = {5{`RANDOM}};
  inflight_sizes_1 = _RAND_17[159:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[1:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_full,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [5:0]  io_enq_bits_source,
  input  [31:0] io_enq_bits_address,
  input  [7:0]  io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [5:0]  io_deq_bits_source,
  output [31:0] io_deq_bits_address,
  output [7:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [5:0] saved_source; // @[Repeater.scala 20:18]
  reg [31:0] saved_address; // @[Repeater.scala 20:18]
  reg [7:0] saved_mask; // @[Repeater.scala 20:18]
  reg  saved_corrupt; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign io_full = full; // @[Repeater.scala 26:11]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[5:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[7:0];
  _RAND_7 = {1{`RANDOM}};
  saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [5:0]  auto_in_a_bits_source,
  input  [31:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [5:0]  auto_in_d_bits_source,
  output [63:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [8:0]  auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [8:0]  auto_out_d_bits_source,
  input  [63:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [5:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [5:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [5:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [31:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [5:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [31:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [1:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [1:0] dFragnum = auto_out_d_bits_source[1:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 2'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 2'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
  wire [4:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
  wire [4:0] _GEN_7 = {{2'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [4:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [5:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 6'h1; // @[package.scala 232:40]
  wire [5:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 33:92]
  wire [5:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [5:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [1:0] dFirst_size_hi = _dFirst_size_T_6[5:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{2'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 33:92]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _GEN_9 = {{1'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [1:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [11:0] _aOrigOH1_T_1 = 12'h1f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [4:0] aOrigOH1 = ~_aOrigOH1_T_1[4:0]; // @[package.scala 234:46]
  wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
  wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [1:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 2'h0; // @[Fragmenter.scala 292:29]
  wire [1:0] _old_gennum1_T_2 = gennum - 2'h1; // @[Fragmenter.scala 293:79]
  wire [1:0] old_gennum1 = aFirst ? aOrigOH1[4:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [1:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [1:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 19:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 19:16 20:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 52:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [4:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
  wire [4:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [4:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [4:0] _GEN_10 = {{2'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [4:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [4:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 5'h7; // @[Fragmenter.scala 304:111]
  wire [4:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [31:0] _GEN_11 = {{27'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [6:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 33:92]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_10 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[8:3]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 33:92]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[8:3]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 2'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 2'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[2]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 2'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 20:18]
      aToggle_r <= dToggle; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Fragmenter.scala 202:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLWidthWidget(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [5:0]  auto_in_a_bits_source,
  input  [31:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [5:0]  auto_in_d_bits_source,
  output [63:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [5:0]  auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [5:0]  auto_out_d_bits_source,
  input  [63:0] auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_11(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [4:0]  io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [2:0]  io_in_c_bits_size,
  input  [4:0]  io_in_c_bits_source,
  input  [31:0] io_in_c_bits_address,
  input         io_in_c_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [4:0]  io_in_d_bits_source,
  input  [2:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt,
  input         io_in_e_valid,
  input  [2:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [95:0] _RAND_20;
  reg [95:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [95:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 5'h13; // @[Parameters.scala 57:20]
  wire [11:0] _is_aligned_mask_T_1 = 12'h1f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [4:0] is_aligned_mask = ~_is_aligned_mask_T_1[4:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_27 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_27; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire [32:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_34 = 3'h3 <= io_in_a_bits_size & io_in_a_bits_size <= 3'h5; // @[Parameters.scala 92:37]
  wire [32:0] _T_39 = $signed(_T_12) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_40 = $signed(_T_39) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_41 = _T_34 & _T_40; // @[Parameters.scala 670:56]
  wire  _T_43 = _source_ok_T_4 & _T_41; // @[Monitor.scala 82:72]
  wire  _T_47 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_59 = _T_47 & _T_40; // @[Monitor.scala 83:78]
  wire  _T_73 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_77 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_78 = _T_77 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_82 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_86 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_143 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_156 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_191 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_195 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_203 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_244 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_281 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_282 = io_in_a_bits_mask & _T_281; // @[Monitor.scala 127:31]
  wire  _T_283 = _T_282 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_287 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_317 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_325 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_355 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_363 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_393 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_405 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 5'h13; // @[Parameters.scala 57:20]
  wire  _T_409 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_413 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_417 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_421 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_425 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_429 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_440 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_444 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_457 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_477 = _T_425 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_486 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_503 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_521 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire [32:0] _T_550 = {1'b0,$signed(32'h0)}; // @[Parameters.scala 137:49]
  wire [32:0] _address_ok_T_3 = $signed(_T_550) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _source_ok_T_16 = io_in_c_bits_source <= 5'h13; // @[Parameters.scala 57:20]
  wire [11:0] _is_aligned_mask_T_7 = 12'h1f << io_in_c_bits_size; // @[package.scala 234:77]
  wire [4:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[4:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_33 = {{27'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_33; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala 20:24]
  wire [32:0] _address_ok_T_6 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 137:49]
  wire [32:0] _address_ok_T_8 = $signed(_address_ok_T_6) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_810 = ~_source_ok_T_16; // @[Monitor.scala 63:7]
  wire  _T_820 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_827 = io_in_c_bits_size >= 3'h3; // @[Monitor.scala 245:30]
  wire  _T_834 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_838 = ~io_in_c_bits_corrupt; // @[Monitor.scala 248:18]
  wire  _T_842 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_860 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_874 = 3'h3 <= io_in_c_bits_size & io_in_c_bits_size <= 3'h5; // @[Parameters.scala 92:37]
  wire  _T_881 = _T_874 & _address_ok_T_9; // @[Parameters.scala 670:56]
  wire  _T_883 = _source_ok_T_16 & _T_881; // @[Monitor.scala 260:78]
  wire  _T_887 = 3'h4 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_899 = _T_887 & _address_ok_T_9; // @[Monitor.scala 261:78]
  wire  _T_921 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_978 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_988 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_996 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_1010 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire [1:0] a_first_beats1_decode = is_aligned_mask[4:3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [1:0] a_first_counter; // @[Edges.scala 228:27]
  wire [1:0] a_first_counter1 = a_first_counter - 2'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 2'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [4:0] source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_1032 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1033 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1037 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1041 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1045 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1049 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [11:0] _d_first_beats1_decode_T_1 = 12'h1f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [4:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[4:0]; // @[package.scala 234:46]
  wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[4:3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [1:0] d_first_counter; // @[Edges.scala 228:27]
  wire [1:0] d_first_counter1 = d_first_counter - 2'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 2'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [4:0] source_1; // @[Monitor.scala 538:22]
  reg [2:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1056 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1057 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1061 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1065 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1069 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1073 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1077 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 52:35]
  wire [1:0] c_first_beats1_decode = is_aligned_mask_2[4:3]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  reg [1:0] c_first_counter; // @[Edges.scala 228:27]
  wire [1:0] c_first_counter1 = c_first_counter - 2'h1; // @[Edges.scala 229:28]
  wire  c_first = c_first_counter == 2'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [2:0] size_3; // @[Monitor.scala 514:22]
  reg [4:0] source_3; // @[Monitor.scala 515:22]
  reg [31:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_1108 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_1109 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_1113 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_1117 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_1121 = io_in_c_bits_source == source_3; // @[Monitor.scala 521:32]
  wire  _T_1125 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg [19:0] inflight; // @[Monitor.scala 611:27]
  reg [79:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [79:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [1:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [1:0] a_first_counter1_1 = a_first_counter_1 - 2'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala 230:25]
  reg [1:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [1:0] d_first_counter1_1 = d_first_counter_1 - 2'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala 230:25]
  wire [6:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [7:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [79:0] _GEN_74 = {{64'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [79:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_74; // @[Monitor.scala 634:97]
  wire [79:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala 634:152]
  wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [79:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_74; // @[Monitor.scala 638:91]
  wire [79:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala 638:144]
  wire  _T_1134 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [31:0] _a_set_T = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [6:0] _GEN_87 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [7:0] _a_opcodes_set_T = {{1'd0}, _GEN_87}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [258:0] _GEN_497 = {{255'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [258:0] _a_opcodes_set_T_1 = _GEN_497 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [258:0] _GEN_498 = {{255'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [258:0] _a_sizes_set_T_1 = _GEN_498 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [19:0] _T_1136 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1138 = ~_T_1136[0]; // @[Monitor.scala 658:17]
  wire [31:0] _GEN_28 = _a_first_T & a_first_1 ? _a_set_T : 32'h0; // @[Monitor.scala 652:72 653:28]
  wire [258:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 259'h0; // @[Monitor.scala 652:72 656:28]
  wire [258:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 259'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1149 = ~_T_409; // @[Monitor.scala 675:75]
  wire [31:0] _d_clr_T = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [270:0] _GEN_499 = {{255'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [270:0] _d_opcodes_clr_T_5 = _GEN_499 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [31:0] _GEN_34 = _d_first_T & d_first_1 & ~_T_409 ? _d_clr_T : 32'h0; // @[Monitor.scala 675:91 676:21]
  wire [270:0] _GEN_35 = _d_first_T & d_first_1 & ~_T_409 ? _d_opcodes_clr_T_5 : 271'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_1151 = io_in_d_valid & d_first_1; // @[Monitor.scala 680:26]
  wire  _T_1154 = io_in_d_valid & d_first_1 & _T_1149; // @[Monitor.scala 680:71]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = io_in_a_valid & a_first_1 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [19:0] _T_1155 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1157 = _T_1155[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_1162 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_1163 = io_in_d_bits_opcode == _GEN_44 | _T_1162; // @[Monitor.scala 685:77]
  wire  _T_1167 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_1174 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_1175 = io_in_d_bits_opcode == _GEN_60 | _T_1174; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_91 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1179 = _GEN_91 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1189 = _T_1151 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1149; // @[Monitor.scala 694:116]
  wire  _T_1190 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_1191 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [19:0] a_set = _GEN_28[19:0];
  wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [19:0] d_clr = _GEN_34[19:0];
  wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [79:0] a_opcodes_set = _GEN_31[79:0];
  wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [79:0] d_opcodes_clr = _GEN_35[79:0];
  wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [79:0] a_sizes_set = _GEN_32[79:0];
  wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1200 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [19:0] inflight_1; // @[Monitor.scala 723:35]
  reg [79:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [1:0] c_first_counter_1; // @[Edges.scala 228:27]
  wire [1:0] c_first_counter1_1 = c_first_counter_1 - 2'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala 230:25]
  reg [1:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [1:0] d_first_counter1_2 = d_first_counter_2 - 2'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala 230:25]
  wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [79:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_74; // @[Monitor.scala 747:93]
  wire [79:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala 747:146]
  wire  _T_1216 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_1217 = _c_first_T & c_first_1 & _T_1216; // @[Monitor.scala 760:38]
  wire [31:0] _c_set_T = 32'h1 << io_in_c_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [3:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 4'h1; // @[Monitor.scala 763:59]
  wire [6:0] _GEN_95 = {io_in_c_bits_source, 2'h0}; // @[Monitor.scala 765:77]
  wire [7:0] _c_sizes_set_T = {{1'd0}, _GEN_95}; // @[Monitor.scala 765:77]
  wire [3:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_1216 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 760:72 763:28]
  wire [258:0] _GEN_501 = {{255'd0}, c_sizes_set_interm}; // @[Monitor.scala 765:52]
  wire [258:0] _c_sizes_set_T_1 = _GEN_501 << _c_sizes_set_T; // @[Monitor.scala 765:52]
  wire [19:0] _T_1218 = inflight_1 >> io_in_c_bits_source; // @[Monitor.scala 766:26]
  wire  _T_1220 = ~_T_1218[0]; // @[Monitor.scala 766:17]
  wire [31:0] _GEN_73 = _c_first_T & c_first_1 & _T_1216 ? _c_set_T : 32'h0; // @[Monitor.scala 760:72 761:28]
  wire [258:0] _GEN_77 = _c_first_T & c_first_1 & _T_1216 ? _c_sizes_set_T_1 : 259'h0; // @[Monitor.scala 760:72 765:28]
  wire [31:0] _GEN_79 = _d_first_T & d_first_2 & _T_409 ? _d_clr_T : 32'h0; // @[Monitor.scala 783:90 784:21]
  wire [270:0] _GEN_81 = _d_first_T & d_first_2 & _T_409 ? _d_opcodes_clr_T_5 : 271'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_1231 = io_in_d_valid & d_first_2; // @[Monitor.scala 789:26]
  wire  _T_1233 = io_in_d_valid & d_first_2 & _T_409; // @[Monitor.scala 789:71]
  wire  _same_cycle_resp_T_8 = io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:113]
  wire  same_cycle_resp_1 = io_in_c_valid & c_first_1 & _T_1216 & io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:88]
  wire [19:0] _T_1234 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_1236 = _T_1234[0] | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_1240 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1244 = _GEN_91 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_1253 = _T_1231 & c_first_1 & io_in_c_valid & _same_cycle_resp_T_8 & _T_409; // @[Monitor.scala 799:116]
  wire  _T_1255 = _T_1190 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire [19:0] c_set = _GEN_73[19:0];
  wire [19:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala 809:35]
  wire [19:0] d_clr_1 = _GEN_79[19:0];
  wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [79:0] c_sizes_set = _GEN_77[79:0];
  wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [79:0] d_sizes_clr_1 = _GEN_81[79:0];
  wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1264 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [7:0] inflight_2; // @[Monitor.scala 823:27]
  reg [1:0] d_first_counter_3; // @[Edges.scala 228:27]
  wire [1:0] d_first_counter1_3 = d_first_counter_3 - 2'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala 230:25]
  wire  _T_1276 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_1277 = _d_first_T & d_first_3 & _T_1276; // @[Monitor.scala 829:38]
  wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [7:0] _T_1278 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_1280 = ~_T_1278[0]; // @[Monitor.scala 831:14]
  wire [7:0] d_set = _d_first_T & d_first_3 & _T_1276 ? _d_set_T : 8'h0; // @[Monitor.scala 829:72 830:13]
  wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [7:0] _T_1287 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [7:0] _T_1288 = _T_1287 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [7:0] e_clr = io_in_e_valid ? _e_clr_T : 8'h0; // @[Monitor.scala 835:73 836:13]
  wire [7:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [7:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [7:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 2'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 2'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 2'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 2'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 2'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter <= c_first_beats1_decode;
        end else begin
          c_first_counter <= 2'h0;
        end
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      source_3 <= io_in_c_bits_source; // @[Monitor.scala 528:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 20'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 80'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 80'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 2'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 2'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 2'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 2'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 20'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 80'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 2'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter_1 <= c_first_beats1_decode;
        end else begin
          c_first_counter_1 <= 2'h0;
        end
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 2'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 2'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 8'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 2'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_3 <= d_first_beats1_decode;
        end else begin
          d_first_counter_3 <= 2'h0;
        end
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_43) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_43 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_59) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_59 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_73 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_82) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_82 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & ~_T_43) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_43 & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & ~_T_59) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_59 & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & ~_T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_73 & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & ~_T_143) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_143 & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_86 & ~reset & ~_T_82) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_82 & (io_in_a_valid & _T_86 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_156 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_156 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_156 & ~reset & ~_T_41) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_41 & (io_in_a_valid & _T_156 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_156 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_156 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_156 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_156 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_156 & ~reset & ~_T_191) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_191 & (io_in_a_valid & _T_156 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_156 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_156 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_156 & ~reset & ~_T_82) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_82 & (io_in_a_valid & _T_156 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_203 & ~reset & ~_T_43) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_43 & (io_in_a_valid & _T_203 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_203 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_203 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_203 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_203 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_203 & ~reset & ~_T_191) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_191 & (io_in_a_valid & _T_203 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_203 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_203 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_244 & ~reset & ~_T_43) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_43 & (io_in_a_valid & _T_244 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_244 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_244 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_244 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_244 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_244 & ~reset & ~_T_191) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_191 & (io_in_a_valid & _T_244 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_244 & ~reset & ~_T_283) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_283 & (io_in_a_valid & _T_244 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_317) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_317 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_355 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_4 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_393) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_393 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_82) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_82 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_409 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_409 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_409 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_409 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_409 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_409 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_409 & _T_2 & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_d_valid & _T_409 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_409 & _T_2 & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_d_valid & _T_409 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_429 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_429 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_429 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_429 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_429 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_429 & _T_2 & ~_T_440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_440 & (io_in_d_valid & _T_429 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_429 & _T_2 & ~_T_444) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_444 & (io_in_d_valid & _T_429 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_429 & _T_2 & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_d_valid & _T_429 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_429 & _T_2 & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_d_valid & _T_429 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_457 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_457 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_457 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_457 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_457 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_457 & _T_2 & ~_T_440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_440 & (io_in_d_valid & _T_457 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_457 & _T_2 & ~_T_444) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_444 & (io_in_d_valid & _T_457 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_457 & _T_2 & ~_T_477) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_477 & (io_in_d_valid & _T_457 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_457 & _T_2 & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_d_valid & _T_457 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_486 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_486 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_486 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_486 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_486 & _T_2 & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_d_valid & _T_486 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_486 & _T_2 & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_d_valid & _T_486 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_503 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_503 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_503 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_503 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_503 & _T_2 & ~_T_477) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_477 & (io_in_d_valid & _T_503 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_503 & _T_2 & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_d_valid & _T_503 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_820 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_820 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_820 & ~reset & _T_810) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_16 & (io_in_c_valid & _T_820 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_820 & ~reset & ~_T_827) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_827 & (io_in_c_valid & _T_820 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_820 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_820 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_820 & ~reset & ~_T_834) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_834 & (io_in_c_valid & _T_820 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_820 & ~reset & ~_T_838) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_838 & (io_in_c_valid & _T_820 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_842 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_842 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_842 & ~reset & _T_810) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_16 & (io_in_c_valid & _T_842 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_842 & ~reset & ~_T_827) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_827 & (io_in_c_valid & _T_842 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_842 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_842 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_842 & ~reset & ~_T_834) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_834 & (io_in_c_valid & _T_842 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_860 & ~reset & ~_T_883) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_883 & (io_in_c_valid & _T_860 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_860 & ~reset & ~_T_899) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_899 & (io_in_c_valid & _T_860 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_860 & ~reset & _T_810) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_16 & (io_in_c_valid & _T_860 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_860 & ~reset & ~_T_827) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_827 & (io_in_c_valid & _T_860 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_860 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_860 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_860 & ~reset & ~_T_834) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_834 & (io_in_c_valid & _T_860 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_860 & ~reset & ~_T_838) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_838 & (io_in_c_valid & _T_860 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_921 & ~reset & ~_T_883) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_883 & (io_in_c_valid & _T_921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_921 & ~reset & ~_T_899) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_899 & (io_in_c_valid & _T_921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_921 & ~reset & _T_810) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_16 & (io_in_c_valid & _T_921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_921 & ~reset & ~_T_827) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_827 & (io_in_c_valid & _T_921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_921 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_921 & ~reset & ~_T_834) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_834 & (io_in_c_valid & _T_921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_978 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_978 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_978 & ~reset & _T_810) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_16 & (io_in_c_valid & _T_978 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_978 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_978 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_978 & ~reset & ~_T_988) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_988 & (io_in_c_valid & _T_978 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_978 & ~reset & ~_T_838) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_838 & (io_in_c_valid & _T_978 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_996 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_996 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_996 & ~reset & _T_810) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_16 & (io_in_c_valid & _T_996 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_996 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_996 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_996 & ~reset & ~_T_988) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_988 & (io_in_c_valid & _T_996 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1010 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1010 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1010 & ~reset & _T_810) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_16 & (io_in_c_valid & _T_1010 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1010 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1010 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1010 & ~reset & ~_T_988) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_988 & (io_in_c_valid & _T_1010 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1010 & ~reset & ~_T_838) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck is corrupt (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_838 & (io_in_c_valid & _T_1010 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1032 & ~reset & ~_T_1033) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1033 & (_T_1032 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1032 & ~reset & ~_T_1037) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1037 & (_T_1032 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1032 & ~reset & ~_T_1041) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1041 & (_T_1032 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1032 & ~reset & ~_T_1045) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1045 & (_T_1032 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1032 & ~reset & ~_T_1049) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1049 & (_T_1032 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1056 & _T_2 & ~_T_1057) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1057 & (_T_1056 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1056 & _T_2 & ~_T_1061) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1061 & (_T_1056 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1056 & _T_2 & ~_T_1065) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1065 & (_T_1056 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1056 & _T_2 & ~_T_1069) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1069 & (_T_1056 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1056 & _T_2 & ~_T_1073) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1073 & (_T_1056 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1056 & _T_2 & ~_T_1077) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1077 & (_T_1056 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1108 & ~reset & ~_T_1109) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1109 & (_T_1108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1108 & ~reset & ~_T_1113) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1113 & (_T_1108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1108 & ~reset & ~_T_1117) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1117 & (_T_1108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1108 & ~reset & ~_T_1121) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel source changed within multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1121 & (_T_1108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1108 & ~reset & ~_T_1125) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1125 & (_T_1108 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1134 & ~reset & ~_T_1138) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1138 & (_T_1134 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1154 & _T_2 & ~_T_1157) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1157 & (_T_1154 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1154 & same_cycle_resp & _T_2 & ~_T_1163) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1163 & (_T_1154 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1154 & same_cycle_resp & _T_2 & ~_T_1167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1167 & (_T_1154 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1154 & ~same_cycle_resp & _T_2 & ~_T_1175) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1175 & (_T_1154 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1154 & ~same_cycle_resp & _T_2 & ~_T_1179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1179 & (_T_1154 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1189 & _T_2 & ~_T_1191) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1191 & (_T_1189 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1200) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1200 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1217 & ~reset & ~_T_1220) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1220 & (_T_1217 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1233 & _T_2 & ~_T_1236) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1236 & (_T_1233 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1233 & same_cycle_resp_1 & _T_2 & ~_T_1240) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1240 & (_T_1233 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1233 & ~same_cycle_resp_1 & _T_2 & ~_T_1244) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1244 & (_T_1233 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1253 & _T_2 & ~_T_1255) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1255 & (_T_1253 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1264) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1264 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1277 & _T_2 & ~_T_1280) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1280 & (_T_1277 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_e_valid & ~reset & ~_T_1288[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at Rift2Link.scala:72:56)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1288[0] & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[4:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[4:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[2:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  c_first_counter = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  opcode_3 = _RAND_14[2:0];
  _RAND_15 = {1{`RANDOM}};
  param_3 = _RAND_15[2:0];
  _RAND_16 = {1{`RANDOM}};
  size_3 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  source_3 = _RAND_17[4:0];
  _RAND_18 = {1{`RANDOM}};
  address_2 = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight = _RAND_19[19:0];
  _RAND_20 = {3{`RANDOM}};
  inflight_opcodes = _RAND_20[79:0];
  _RAND_21 = {3{`RANDOM}};
  inflight_sizes = _RAND_21[79:0];
  _RAND_22 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_22[1:0];
  _RAND_23 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_23[1:0];
  _RAND_24 = {1{`RANDOM}};
  watchdog = _RAND_24[31:0];
  _RAND_25 = {1{`RANDOM}};
  inflight_1 = _RAND_25[19:0];
  _RAND_26 = {3{`RANDOM}};
  inflight_sizes_1 = _RAND_26[79:0];
  _RAND_27 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_27[1:0];
  _RAND_28 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_28[1:0];
  _RAND_29 = {1{`RANDOM}};
  watchdog_1 = _RAND_29[31:0];
  _RAND_30 = {1{`RANDOM}};
  inflight_2 = _RAND_30[7:0];
  _RAND_31 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_31[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IDPool(
  input        clock,
  input        reset,
  input        io_free_valid,
  input  [2:0] io_free_bits,
  input        io_alloc_ready,
  output       io_alloc_valid,
  output [2:0] io_alloc_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [7:0] bitmap; // @[IDPool.scala 18:23]
  reg [2:0] select; // @[IDPool.scala 19:23]
  reg  valid; // @[IDPool.scala 20:23]
  wire [7:0] _taken_T = 8'h1 << io_alloc_bits; // @[OneHot.scala 64:12]
  wire [7:0] taken = io_alloc_ready ? _taken_T : 8'h0; // @[IDPool.scala 25:19]
  wire [7:0] _given_T = 8'h1 << io_free_bits; // @[OneHot.scala 64:12]
  wire [7:0] given = io_free_valid ? _given_T : 8'h0; // @[IDPool.scala 26:19]
  wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala 27:27]
  wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala 27:25]
  wire [7:0] bitmap1 = _bitmap1_T_1 | given; // @[IDPool.scala 27:35]
  wire [2:0] _select1_T_8 = bitmap1[6] ? 3'h6 : 3'h7; // @[Mux.scala 47:70]
  wire [2:0] _select1_T_9 = bitmap1[5] ? 3'h5 : _select1_T_8; // @[Mux.scala 47:70]
  wire [2:0] _select1_T_10 = bitmap1[4] ? 3'h4 : _select1_T_9; // @[Mux.scala 47:70]
  wire [2:0] _select1_T_11 = bitmap1[3] ? 3'h3 : _select1_T_10; // @[Mux.scala 47:70]
  wire [2:0] _select1_T_12 = bitmap1[2] ? 3'h2 : _select1_T_11; // @[Mux.scala 47:70]
  wire  _valid1_T = |bitmap; // @[IDPool.scala 29:28]
  wire [1:0] _valid1_T_9 = bitmap[0] + bitmap[1]; // @[Bitwise.scala 51:90]
  wire [1:0] _valid1_T_11 = bitmap[2] + bitmap[3]; // @[Bitwise.scala 51:90]
  wire [2:0] _valid1_T_13 = _valid1_T_9 + _valid1_T_11; // @[Bitwise.scala 51:90]
  wire [1:0] _valid1_T_15 = bitmap[4] + bitmap[5]; // @[Bitwise.scala 51:90]
  wire [1:0] _valid1_T_17 = bitmap[6] + bitmap[7]; // @[Bitwise.scala 51:90]
  wire [2:0] _valid1_T_19 = _valid1_T_15 + _valid1_T_17; // @[Bitwise.scala 51:90]
  wire [3:0] _valid1_T_21 = _valid1_T_13 + _valid1_T_19; // @[Bitwise.scala 51:90]
  wire  _valid1_T_26 = |bitmap & ~(_valid1_T_21 == 4'h1 & io_alloc_ready); // @[IDPool.scala 29:32]
  wire  valid1 = _valid1_T_26 | io_free_valid; // @[IDPool.scala 30:17]
  wire  _GEN_1 = io_alloc_ready | io_free_valid ? valid1 : valid; // @[IDPool.scala 33:42 35:12 20:23]
  wire  _T_2 = ~io_alloc_valid & io_free_valid; // @[IDPool.scala 39:44]
  wire [7:0] _T_7 = _bitmap1_T_1 >> io_free_bits; // @[IDPool.scala 44:47]
  wire  _T_12 = ~reset; // @[IDPool.scala 44:10]
  reg  REG; // @[IDPool.scala 51:36]
  wire  _T_22 = io_alloc_valid & REG; // @[IDPool.scala 51:26]
  wire [2:0] _T_31 = bitmap[6] ? 3'h6 : 3'h7; // @[Mux.scala 47:70]
  wire [2:0] _T_32 = bitmap[5] ? 3'h5 : _T_31; // @[Mux.scala 47:70]
  wire [2:0] _T_33 = bitmap[4] ? 3'h4 : _T_32; // @[Mux.scala 47:70]
  wire [2:0] _T_34 = bitmap[3] ? 3'h3 : _T_33; // @[Mux.scala 47:70]
  wire [2:0] _T_35 = bitmap[2] ? 3'h2 : _T_34; // @[Mux.scala 47:70]
  wire [2:0] _T_36 = bitmap[1] ? 3'h1 : _T_35; // @[Mux.scala 47:70]
  wire [2:0] _T_37 = bitmap[0] ? 3'h0 : _T_36; // @[Mux.scala 47:70]
  assign io_alloc_valid = valid; // @[IDPool.scala 22:18]
  assign io_alloc_bits = select; // @[IDPool.scala 23:18]
  always @(posedge clock) begin
    if (reset) begin // @[IDPool.scala 18:23]
      bitmap <= 8'hff; // @[IDPool.scala 18:23]
    end else if (io_alloc_ready | io_free_valid) begin // @[IDPool.scala 33:42]
      bitmap <= bitmap1; // @[IDPool.scala 34:12]
    end
    if (reset) begin // @[IDPool.scala 19:23]
      select <= 3'h0; // @[IDPool.scala 19:23]
    end else if (io_alloc_ready | ~io_alloc_valid & io_free_valid) begin // @[IDPool.scala 39:63]
      if (bitmap1[0]) begin // @[Mux.scala 47:70]
        select <= 3'h0;
      end else if (bitmap1[1]) begin // @[Mux.scala 47:70]
        select <= 3'h1;
      end else begin
        select <= _select1_T_12;
      end
    end
    valid <= reset | _GEN_1; // @[IDPool.scala 20:{23,23}]
    REG <= io_alloc_ready | _T_2; // @[IDPool.scala 51:52]
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_free_valid | ~_T_7[0])) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IDPool.scala:44 assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))\n"); // @[IDPool.scala 44:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_free_valid | ~_T_7[0]) & ~reset) begin
          $fatal; // @[IDPool.scala 44:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_12 & ~(valid == _valid1_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IDPool.scala:48 assert (valid === bitmap.orR)\n"); // @[IDPool.scala 48:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(valid == _valid1_T) & _T_12) begin
          $fatal; // @[IDPool.scala 48:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_22 & _T_12 & ~(select == _T_37)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n"
            ); // @[IDPool.scala 52:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(select == _T_37) & (_T_22 & _T_12)) begin
          $fatal; // @[IDPool.scala 52:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  bitmap = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  select = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  valid = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  REG = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_31(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_size,
  input  [4:0]  io_enq_bits_source,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [4:0]  io_deq_bits_source,
  output        io_deq_bits_denied,
  output [63:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_param [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [4:0] ram_source [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [4:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [4:0] ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_denied [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_en; // @[Decoupled.scala 275:95]
  reg [63:0] ram_data [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_param_MPORT_data = 2'h0;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
  assign ram_denied_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_denied_MPORT_data = 1'h0;
  assign ram_denied_MPORT_addr = enq_ptr_value;
  assign ram_denied_MPORT_mask = 1'h1;
  assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = 64'h0;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_corrupt_MPORT_data = 1'h0;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
      ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[4:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_denied[initvar] = _RAND_4[0:0];
  _RAND_5 = {2{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_5[63:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  enq_ptr_value = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  deq_ptr_value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  maybe_full = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLCacheCork(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [4:0]  auto_in_a_bits_source,
  input  [31:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [2:0]  auto_in_c_bits_size,
  input  [4:0]  auto_in_c_bits_source,
  input  [31:0] auto_in_c_bits_address,
  input  [63:0] auto_in_c_bits_data,
  input         auto_in_c_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [4:0]  auto_in_d_bits_source,
  output [2:0]  auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [63:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_in_e_valid,
  input  [2:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [5:0]  auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [5:0]  auto_out_d_bits_source,
  input  [63:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_c_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  wire  pool_clock; // @[CacheCork.scala 117:26]
  wire  pool_reset; // @[CacheCork.scala 117:26]
  wire  pool_io_free_valid; // @[CacheCork.scala 117:26]
  wire [2:0] pool_io_free_bits; // @[CacheCork.scala 117:26]
  wire  pool_io_alloc_ready; // @[CacheCork.scala 117:26]
  wire  pool_io_alloc_valid; // @[CacheCork.scala 117:26]
  wire [2:0] pool_io_alloc_bits; // @[CacheCork.scala 117:26]
  wire  q_clock; // @[Decoupled.scala 377:21]
  wire  q_reset; // @[Decoupled.scala 377:21]
  wire  q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] q_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [4:0] q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire  q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [4:0] q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire  q_io_deq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  q_1_clock; // @[Decoupled.scala 377:21]
  wire  q_1_reset; // @[Decoupled.scala 377:21]
  wire  q_1_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  q_1_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] q_1_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] q_1_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [4:0] q_1_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire  q_1_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  q_1_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] q_1_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] q_1_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] q_1_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [4:0] q_1_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire  q_1_io_deq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] q_1_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  q_1_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  isPut = auto_in_a_bits_opcode == 3'h0 | auto_in_a_bits_opcode == 3'h1; // @[CacheCork.scala 66:54]
  wire  _toD_T = auto_in_a_bits_opcode == 3'h6; // @[CacheCork.scala 67:37]
  wire  _toD_T_3 = auto_in_a_bits_opcode == 3'h7; // @[CacheCork.scala 68:37]
  wire  toD = auto_in_a_bits_opcode == 3'h6 & auto_in_a_bits_param == 3'h2 | _toD_T_3; // @[CacheCork.scala 67:97]
  wire  a_d_ready = q_1_io_enq_ready; // @[CacheCork.scala 65:23 Decoupled.scala 381:17]
  reg [1:0] beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = beatsLeft == 2'h0; // @[Arbiter.scala 88:28]
  wire  a_a_valid = auto_in_a_valid & ~toD; // @[CacheCork.scala 71:33]
  wire  _c_a_valid_T = auto_in_c_bits_opcode == 3'h7; // @[CacheCork.scala 92:53]
  wire  c_a_valid = auto_in_c_valid & auto_in_c_bits_opcode == 3'h7; // @[CacheCork.scala 92:33]
  wire [1:0] _readys_T = {a_a_valid,c_a_valid}; // @[Cat.scala 33:92]
  wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_T_3 = _readys_T | _readys_T_1[1:0]; // @[package.scala 244:43]
  wire [2:0] _readys_T_5 = {_readys_T_3, 1'h0}; // @[Arbiter.scala 16:78]
  wire [1:0] _readys_T_7 = ~_readys_T_5[1:0]; // @[Arbiter.scala 16:61]
  wire  readys__1 = _readys_T_7[1]; // @[Arbiter.scala 95:86]
  reg  state__1; // @[Arbiter.scala 116:26]
  wire  allowed__1 = idle ? readys__1 : state__1; // @[Arbiter.scala 121:24]
  wire  out_1_ready = auto_out_a_ready & allowed__1; // @[Arbiter.scala 123:31]
  wire [5:0] _a_a_bits_source_T = {auto_in_a_bits_source, 1'h0}; // @[CacheCork.scala 73:45]
  wire [5:0] _GEN_69 = {{5'd0}, isPut}; // @[CacheCork.scala 73:50]
  wire [5:0] _a_a_bits_source_T_2 = _a_a_bits_source_T | _GEN_69; // @[CacheCork.scala 73:50]
  wire [5:0] _a_a_bits_source_T_4 = _a_a_bits_source_T | 6'h1; // @[CacheCork.scala 79:52]
  wire [2:0] a_a_bits_opcode = _toD_T | _toD_T_3 ? 3'h4 : auto_in_a_bits_opcode; // @[CacheCork.scala 72:18 76:86 77:27]
  wire [2:0] a_a_bits_param = _toD_T | _toD_T_3 ? 3'h0 : auto_in_a_bits_param; // @[CacheCork.scala 72:18 76:86 78:27]
  wire [5:0] a_a_bits_source = _toD_T | _toD_T_3 ? _a_a_bits_source_T_4 : _a_a_bits_source_T_2; // @[CacheCork.scala 73:25 76:86 79:27]
  wire [5:0] c_a_bits_a_source = {auto_in_c_bits_source, 1'h0}; // @[CacheCork.scala 94:41]
  wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount = auto_in_c_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _c_a_bits_a_mask_sizeOH_T_1 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] c_a_bits_a_mask_sizeOH = _c_a_bits_a_mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _c_a_bits_a_mask_T = auto_in_c_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  c_a_bits_a_mask_size = c_a_bits_a_mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  c_a_bits_a_mask_bit = auto_in_c_bits_address[2]; // @[Misc.scala 209:26]
  wire  c_a_bits_a_mask_nbit = ~c_a_bits_a_mask_bit; // @[Misc.scala 210:20]
  wire  c_a_bits_a_mask_acc = _c_a_bits_a_mask_T | c_a_bits_a_mask_size & c_a_bits_a_mask_nbit; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_acc_1 = _c_a_bits_a_mask_T | c_a_bits_a_mask_size & c_a_bits_a_mask_bit; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_size_1 = c_a_bits_a_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  c_a_bits_a_mask_bit_1 = auto_in_c_bits_address[1]; // @[Misc.scala 209:26]
  wire  c_a_bits_a_mask_nbit_1 = ~c_a_bits_a_mask_bit_1; // @[Misc.scala 210:20]
  wire  c_a_bits_a_mask_eq_2 = c_a_bits_a_mask_nbit & c_a_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_2 = c_a_bits_a_mask_acc | c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_2; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_3 = c_a_bits_a_mask_nbit & c_a_bits_a_mask_bit_1; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_3 = c_a_bits_a_mask_acc | c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_3; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_4 = c_a_bits_a_mask_bit & c_a_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_4 = c_a_bits_a_mask_acc_1 | c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_4; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_5 = c_a_bits_a_mask_bit & c_a_bits_a_mask_bit_1; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_5 = c_a_bits_a_mask_acc_1 | c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_5; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_size_2 = c_a_bits_a_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  c_a_bits_a_mask_bit_2 = auto_in_c_bits_address[0]; // @[Misc.scala 209:26]
  wire  c_a_bits_a_mask_nbit_2 = ~c_a_bits_a_mask_bit_2; // @[Misc.scala 210:20]
  wire  c_a_bits_a_mask_eq_6 = c_a_bits_a_mask_eq_2 & c_a_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_6 = c_a_bits_a_mask_acc_2 | c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_6; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_7 = c_a_bits_a_mask_eq_2 & c_a_bits_a_mask_bit_2; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_7 = c_a_bits_a_mask_acc_2 | c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_7; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_8 = c_a_bits_a_mask_eq_3 & c_a_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_8 = c_a_bits_a_mask_acc_3 | c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_8; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_9 = c_a_bits_a_mask_eq_3 & c_a_bits_a_mask_bit_2; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_9 = c_a_bits_a_mask_acc_3 | c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_9; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_10 = c_a_bits_a_mask_eq_4 & c_a_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_10 = c_a_bits_a_mask_acc_4 | c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_10; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_11 = c_a_bits_a_mask_eq_4 & c_a_bits_a_mask_bit_2; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_11 = c_a_bits_a_mask_acc_4 | c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_11; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_12 = c_a_bits_a_mask_eq_5 & c_a_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_12 = c_a_bits_a_mask_acc_5 | c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_12; // @[Misc.scala 214:29]
  wire  c_a_bits_a_mask_eq_13 = c_a_bits_a_mask_eq_5 & c_a_bits_a_mask_bit_2; // @[Misc.scala 213:27]
  wire  c_a_bits_a_mask_acc_13 = c_a_bits_a_mask_acc_5 | c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] c_a_bits_a_mask = {c_a_bits_a_mask_acc_13,c_a_bits_a_mask_acc_12,c_a_bits_a_mask_acc_11,
    c_a_bits_a_mask_acc_10,c_a_bits_a_mask_acc_9,c_a_bits_a_mask_acc_8,c_a_bits_a_mask_acc_7,c_a_bits_a_mask_acc_6}; // @[Cat.scala 33:92]
  wire  _c_d_valid_T = auto_in_c_bits_opcode == 3'h6; // @[CacheCork.scala 103:53]
  wire  _T_9 = ~reset; // @[CacheCork.scala 106:16]
  wire  c_d_ready = q_io_enq_ready; // @[CacheCork.scala 102:23 Decoupled.scala 381:17]
  wire  readys__0 = _readys_T_7[0]; // @[Arbiter.scala 95:86]
  reg  state__0; // @[Arbiter.scala 116:26]
  wire  allowed__0 = idle ? readys__0 : state__0; // @[Arbiter.scala 121:24]
  wire  out_ready = auto_out_a_ready & allowed__0; // @[Arbiter.scala 123:31]
  reg [1:0] d_first_counter; // @[Edges.scala 228:27]
  wire  d_first = d_first_counter == 2'h0; // @[Edges.scala 230:25]
  reg [1:0] beatsLeft_1; // @[Arbiter.scala 87:30]
  wire  idle_1 = beatsLeft_1 == 2'h0; // @[Arbiter.scala 88:28]
  wire  out_5_earlyValid = q_1_io_deq_valid; // @[ReadyValidCancel.scala 68:19 69:20]
  wire  out_4_earlyValid = q_io_deq_valid; // @[ReadyValidCancel.scala 68:19 69:20]
  wire [2:0] _readys_T_10 = {out_5_earlyValid,out_4_earlyValid,auto_out_d_valid}; // @[Cat.scala 33:92]
  wire [3:0] _readys_T_11 = {_readys_T_10, 1'h0}; // @[package.scala 244:48]
  wire [2:0] _readys_T_13 = _readys_T_10 | _readys_T_11[2:0]; // @[package.scala 244:43]
  wire [4:0] _readys_T_14 = {_readys_T_13, 2'h0}; // @[package.scala 244:48]
  wire [2:0] _readys_T_16 = _readys_T_13 | _readys_T_14[2:0]; // @[package.scala 244:43]
  wire [3:0] _readys_T_18 = {_readys_T_16, 1'h0}; // @[Arbiter.scala 16:78]
  wire [2:0] _readys_T_20 = ~_readys_T_18[2:0]; // @[Arbiter.scala 16:61]
  wire  readys_1_0 = _readys_T_20[0]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_1_0 = readys_1_0 & auto_out_d_valid; // @[Arbiter.scala 97:79]
  reg  state_1_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1_0 = idle_1 ? earlyWinner_1_0 : state_1_0; // @[Arbiter.scala 117:30]
  wire [2:0] _GEN_66 = auto_out_d_bits_opcode == 3'h1 & auto_out_d_bits_source[0] ? 3'h5 : auto_out_d_bits_opcode; // @[CacheCork.scala 132:13 152:76 153:27]
  wire [2:0] d_d_bits_opcode = auto_out_d_bits_opcode == 3'h0 & ~auto_out_d_bits_source[0] ? 3'h6 : _GEN_66; // @[CacheCork.scala 156:73 157:27]
  wire [2:0] _T_141 = muxStateEarly_1_0 ? d_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire  readys_1_1 = _readys_T_20[1]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_1_1 = readys_1_1 & out_4_earlyValid; // @[Arbiter.scala 97:79]
  reg  state_1_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1_1 = idle_1 ? earlyWinner_1_1 : state_1_1; // @[Arbiter.scala 117:30]
  wire [2:0] out_4_bits_opcode = q_io_deq_bits_opcode; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_142 = muxStateEarly_1_1 ? out_4_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_144 = _T_141 | _T_142; // @[Mux.scala 27:73]
  wire  readys_1_2 = _readys_T_20[2]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_1_2 = readys_1_2 & out_5_earlyValid; // @[Arbiter.scala 97:79]
  reg  state_1_2; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1_2 = idle_1 ? earlyWinner_1_2 : state_1_2; // @[Arbiter.scala 117:30]
  wire [2:0] out_5_bits_opcode = q_1_io_deq_bits_opcode; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_143 = muxStateEarly_1_2 ? out_5_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] sink_ACancel_1_bits_opcode = _T_144 | _T_143; // @[Mux.scala 27:73]
  wire  d_grant = sink_ACancel_1_bits_opcode == 3'h5 | sink_ACancel_1_bits_opcode == 3'h4; // @[CacheCork.scala 123:54]
  wire  _in_d_ready_T_3 = pool_io_alloc_valid | ~d_first | ~d_grant; // @[CacheCork.scala 126:70]
  wire  in_d_ready = auto_in_d_ready & (pool_io_alloc_valid | ~d_first | ~d_grant); // @[CacheCork.scala 126:34]
  wire  _sink_ACancel_earlyValid_T_6 = auto_out_d_valid | out_4_earlyValid | out_5_earlyValid; // @[Arbiter.scala 125:56]
  wire  _sink_ACancel_earlyValid_T_11 = state_1_0 & auto_out_d_valid | state_1_1 & out_4_earlyValid | state_1_2 &
    out_5_earlyValid; // @[Mux.scala 27:73]
  wire  sink_ACancel_1_earlyValid = idle_1 ? auto_out_d_valid | out_4_earlyValid | out_5_earlyValid :
    _sink_ACancel_earlyValid_T_11; // @[Arbiter.scala 125:29]
  wire  _d_first_T = in_d_ready & sink_ACancel_1_earlyValid; // @[Decoupled.scala 52:35]
  wire [2:0] _T_131 = muxStateEarly_1_0 ? auto_out_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_4_bits_size = q_io_deq_bits_size; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_132 = muxStateEarly_1_1 ? out_4_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_134 = _T_131 | _T_132; // @[Mux.scala 27:73]
  wire [2:0] out_5_bits_size = q_1_io_deq_bits_size; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_133 = muxStateEarly_1_2 ? out_5_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] sink_ACancel_1_bits_size = _T_134 | _T_133; // @[Mux.scala 27:73]
  wire [11:0] _d_first_beats1_decode_T_1 = 12'h1f << sink_ACancel_1_bits_size; // @[package.scala 234:77]
  wire [4:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[4:0]; // @[package.scala 234:46]
  wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[4:3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = sink_ACancel_1_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [1:0] d_first_counter1 = d_first_counter - 2'h1; // @[Edges.scala 229:28]
  wire  bundleIn_0_d_valid = sink_ACancel_1_earlyValid & _in_d_ready_T_3; // @[CacheCork.scala 125:34]
  wire  _pool_io_alloc_ready_T = auto_in_d_ready & bundleIn_0_d_valid; // @[Decoupled.scala 52:35]
  reg [2:0] bundleIn_0_d_bits_sink_r; // @[Reg.scala 19:16]
  wire [4:0] d_d_bits_source = auto_out_d_bits_source[5:1]; // @[CacheCork.scala 133:46]
  wire [11:0] _decode_T_1 = 12'h1f << auto_in_c_bits_size; // @[package.scala 234:77]
  wire [4:0] _decode_T_3 = ~_decode_T_1[4:0]; // @[package.scala 234:46]
  wire [1:0] decode = _decode_T_3[4:3]; // @[Edges.scala 219:59]
  wire [11:0] _decode_T_5 = 12'h1f << auto_in_a_bits_size; // @[package.scala 234:77]
  wire [4:0] _decode_T_7 = ~_decode_T_5[4:0]; // @[package.scala 234:46]
  wire [1:0] decode_1 = _decode_T_7[4:3]; // @[Edges.scala 219:59]
  wire  opdata_1 = ~a_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire [1:0] _T_24 = opdata_1 ? decode_1 : 2'h0; // @[Edges.scala 220:14]
  wire  latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
  wire  earlyWinner__0 = readys__0 & c_a_valid; // @[Arbiter.scala 97:79]
  wire  earlyWinner__1 = readys__1 & a_a_valid; // @[Arbiter.scala 97:79]
  wire  _T_35 = c_a_valid | a_a_valid; // @[Arbiter.scala 107:36]
  wire  _T_36 = ~(c_a_valid | a_a_valid); // @[Arbiter.scala 107:15]
  wire [1:0] maskedBeats_0 = earlyWinner__0 ? decode : 2'h0; // @[Arbiter.scala 111:73]
  wire [1:0] maskedBeats_1 = earlyWinner__1 ? _T_24 : 2'h0; // @[Arbiter.scala 111:73]
  wire [1:0] initBeats = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala 112:44]
  wire  muxStateEarly__0 = idle ? earlyWinner__0 : state__0; // @[Arbiter.scala 117:30]
  wire  muxStateEarly__1 = idle ? earlyWinner__1 : state__1; // @[Arbiter.scala 117:30]
  wire  _sink_ACancel_earlyValid_T_3 = state__0 & c_a_valid | state__1 & a_a_valid; // @[Mux.scala 27:73]
  wire  sink_ACancel_earlyValid = idle ? _T_35 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_out_a_ready & sink_ACancel_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [1:0] _GEN_70 = {{1'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
  wire [1:0] _beatsLeft_T_4 = beatsLeft - _GEN_70; // @[Arbiter.scala 113:52]
  wire [63:0] _T_52 = muxStateEarly__0 ? auto_in_c_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_53 = muxStateEarly__1 ? auto_in_a_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_55 = muxStateEarly__0 ? c_a_bits_a_mask : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_56 = muxStateEarly__1 ? auto_in_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_58 = muxStateEarly__0 ? auto_in_c_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_59 = muxStateEarly__1 ? auto_in_a_bits_address : 32'h0; // @[Mux.scala 27:73]
  wire [5:0] _T_61 = muxStateEarly__0 ? c_a_bits_a_source : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _T_62 = muxStateEarly__1 ? a_a_bits_source : 6'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_64 = muxStateEarly__0 ? auto_in_c_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_65 = muxStateEarly__1 ? auto_in_a_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [11:0] _decode_T_9 = 12'h1f << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [4:0] _decode_T_11 = ~_decode_T_9[4:0]; // @[package.scala 234:46]
  wire [1:0] decode_2 = _decode_T_11[4:3]; // @[Edges.scala 219:59]
  wire  opdata_2 = d_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  latch_1 = idle_1 & in_d_ready; // @[Arbiter.scala 89:24]
  wire  prefixOR_2 = earlyWinner_1_0 | earlyWinner_1_1; // @[Arbiter.scala 104:53]
  wire  _T_90 = ~_sink_ACancel_earlyValid_T_6; // @[Arbiter.scala 107:15]
  wire [1:0] _GEN_71 = {{1'd0}, _d_first_T}; // @[Arbiter.scala 113:52]
  wire [1:0] _beatsLeft_T_10 = beatsLeft_1 - _GEN_71; // @[Arbiter.scala 113:52]
  wire  allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala 121:24]
  wire  allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala 121:24]
  wire  allowed_1_2 = idle_1 ? readys_1_2 : state_1_2; // @[Arbiter.scala 121:24]
  wire  out_4_bits_corrupt = q_io_deq_bits_corrupt; // @[ReadyValidCancel.scala 68:19 71:14]
  wire  out_5_bits_corrupt = q_1_io_deq_bits_corrupt; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [63:0] _T_111 = muxStateEarly_1_0 ? auto_out_d_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] out_4_bits_data = q_io_deq_bits_data; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [63:0] _T_112 = muxStateEarly_1_1 ? out_4_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] out_5_bits_data = q_1_io_deq_bits_data; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [63:0] _T_113 = muxStateEarly_1_2 ? out_5_bits_data : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _T_114 = _T_111 | _T_112; // @[Mux.scala 27:73]
  wire  out_4_bits_denied = q_io_deq_bits_denied; // @[ReadyValidCancel.scala 68:19 71:14]
  wire  out_5_bits_denied = q_1_io_deq_bits_denied; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [4:0] _T_126 = muxStateEarly_1_0 ? d_d_bits_source : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] out_4_bits_source = q_io_deq_bits_source; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [4:0] _T_127 = muxStateEarly_1_1 ? out_4_bits_source : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] out_5_bits_source = q_1_io_deq_bits_source; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [4:0] _T_128 = muxStateEarly_1_2 ? out_5_bits_source : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] _T_129 = _T_126 | _T_127; // @[Mux.scala 27:73]
  wire [1:0] out_4_bits_param = q_io_deq_bits_param; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [1:0] _T_137 = muxStateEarly_1_1 ? out_4_bits_param : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] out_5_bits_param = q_1_io_deq_bits_param; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [1:0] _T_138 = muxStateEarly_1_2 ? out_5_bits_param : 2'h0; // @[Mux.scala 27:73]
  TLMonitor_11 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_c_ready(monitor_io_in_c_ready),
    .io_in_c_valid(monitor_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_io_in_c_bits_size),
    .io_in_c_bits_source(monitor_io_in_c_bits_source),
    .io_in_c_bits_address(monitor_io_in_c_bits_address),
    .io_in_c_bits_corrupt(monitor_io_in_c_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt),
    .io_in_e_valid(monitor_io_in_e_valid),
    .io_in_e_bits_sink(monitor_io_in_e_bits_sink)
  );
  IDPool pool ( // @[CacheCork.scala 117:26]
    .clock(pool_clock),
    .reset(pool_reset),
    .io_free_valid(pool_io_free_valid),
    .io_free_bits(pool_io_free_bits),
    .io_alloc_ready(pool_io_alloc_ready),
    .io_alloc_valid(pool_io_alloc_valid),
    .io_alloc_bits(pool_io_alloc_bits)
  );
  Queue_31 q ( // @[Decoupled.scala 377:21]
    .clock(q_clock),
    .reset(q_reset),
    .io_enq_ready(q_io_enq_ready),
    .io_enq_valid(q_io_enq_valid),
    .io_enq_bits_opcode(q_io_enq_bits_opcode),
    .io_enq_bits_size(q_io_enq_bits_size),
    .io_enq_bits_source(q_io_enq_bits_source),
    .io_deq_ready(q_io_deq_ready),
    .io_deq_valid(q_io_deq_valid),
    .io_deq_bits_opcode(q_io_deq_bits_opcode),
    .io_deq_bits_param(q_io_deq_bits_param),
    .io_deq_bits_size(q_io_deq_bits_size),
    .io_deq_bits_source(q_io_deq_bits_source),
    .io_deq_bits_denied(q_io_deq_bits_denied),
    .io_deq_bits_data(q_io_deq_bits_data),
    .io_deq_bits_corrupt(q_io_deq_bits_corrupt)
  );
  Queue_31 q_1 ( // @[Decoupled.scala 377:21]
    .clock(q_1_clock),
    .reset(q_1_reset),
    .io_enq_ready(q_1_io_enq_ready),
    .io_enq_valid(q_1_io_enq_valid),
    .io_enq_bits_opcode(q_1_io_enq_bits_opcode),
    .io_enq_bits_size(q_1_io_enq_bits_size),
    .io_enq_bits_source(q_1_io_enq_bits_source),
    .io_deq_ready(q_1_io_deq_ready),
    .io_deq_valid(q_1_io_deq_valid),
    .io_deq_bits_opcode(q_1_io_deq_bits_opcode),
    .io_deq_bits_param(q_1_io_deq_bits_param),
    .io_deq_bits_size(q_1_io_deq_bits_size),
    .io_deq_bits_source(q_1_io_deq_bits_source),
    .io_deq_bits_denied(q_1_io_deq_bits_denied),
    .io_deq_bits_data(q_1_io_deq_bits_data),
    .io_deq_bits_corrupt(q_1_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = toD ? a_d_ready : out_1_ready; // @[CacheCork.scala 69:26]
  assign auto_in_c_ready = _c_d_valid_T ? c_d_ready : out_ready; // @[CacheCork.scala 107:26]
  assign auto_in_d_valid = sink_ACancel_1_earlyValid & _in_d_ready_T_3; // @[CacheCork.scala 125:34]
  assign auto_in_d_bits_opcode = _T_144 | _T_143; // @[Mux.scala 27:73]
  assign auto_in_d_bits_param = _T_137 | _T_138; // @[Mux.scala 27:73]
  assign auto_in_d_bits_size = _T_134 | _T_133; // @[Mux.scala 27:73]
  assign auto_in_d_bits_source = _T_129 | _T_128; // @[Mux.scala 27:73]
  assign auto_in_d_bits_sink = d_first ? pool_io_alloc_bits : bundleIn_0_d_bits_sink_r; // @[package.scala 79:42]
  assign auto_in_d_bits_denied = muxStateEarly_1_1 & out_4_bits_denied | muxStateEarly_1_2 & out_5_bits_denied; // @[Mux.scala 27:73]
  assign auto_in_d_bits_data = _T_114 | _T_113; // @[Mux.scala 27:73]
  assign auto_in_d_bits_corrupt = muxStateEarly_1_1 & out_4_bits_corrupt | muxStateEarly_1_2 & out_5_bits_corrupt; // @[Mux.scala 27:73]
  assign auto_out_a_valid = idle ? _T_35 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign auto_out_a_bits_opcode = muxStateEarly__1 ? a_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  assign auto_out_a_bits_param = muxStateEarly__1 ? a_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  assign auto_out_a_bits_size = _T_64 | _T_65; // @[Mux.scala 27:73]
  assign auto_out_a_bits_source = _T_61 | _T_62; // @[Mux.scala 27:73]
  assign auto_out_a_bits_address = _T_58 | _T_59; // @[Mux.scala 27:73]
  assign auto_out_a_bits_mask = _T_55 | _T_56; // @[Mux.scala 27:73]
  assign auto_out_a_bits_data = _T_52 | _T_53; // @[Mux.scala 27:73]
  assign auto_out_a_bits_corrupt = muxStateEarly__0 & auto_in_c_bits_corrupt | muxStateEarly__1 & auto_in_a_bits_corrupt
    ; // @[Mux.scala 27:73]
  assign auto_out_d_ready = in_d_ready & allowed_1_0; // @[Arbiter.scala 123:31]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = toD ? a_d_ready : out_1_ready; // @[CacheCork.scala 69:26]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_ready = _c_d_valid_T ? c_d_ready : out_ready; // @[CacheCork.scala 107:26]
  assign monitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = sink_ACancel_1_earlyValid & _in_d_ready_T_3; // @[CacheCork.scala 125:34]
  assign monitor_io_in_d_bits_opcode = _T_144 | _T_143; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_param = _T_137 | _T_138; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_size = _T_134 | _T_133; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_source = _T_129 | _T_128; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_sink = d_first ? pool_io_alloc_bits : bundleIn_0_d_bits_sink_r; // @[package.scala 79:42]
  assign monitor_io_in_d_bits_denied = muxStateEarly_1_1 & out_4_bits_denied | muxStateEarly_1_2 & out_5_bits_denied; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_corrupt = muxStateEarly_1_1 & out_4_bits_corrupt | muxStateEarly_1_2 & out_5_bits_corrupt; // @[Mux.scala 27:73]
  assign monitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign pool_clock = clock;
  assign pool_reset = reset;
  assign pool_io_free_valid = auto_in_e_valid; // @[Decoupled.scala 52:35]
  assign pool_io_free_bits = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign pool_io_alloc_ready = _pool_io_alloc_ready_T & d_first & d_grant; // @[CacheCork.scala 124:55]
  assign q_clock = clock;
  assign q_reset = reset;
  assign q_io_enq_valid = auto_in_c_valid & auto_in_c_bits_opcode == 3'h6; // @[CacheCork.scala 103:33]
  assign q_io_enq_bits_opcode = 3'h6; // @[Edges.scala 642:17 643:15]
  assign q_io_enq_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign q_io_enq_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign q_io_deq_ready = in_d_ready & allowed_1_1; // @[Arbiter.scala 123:31]
  assign q_1_clock = clock;
  assign q_1_reset = reset;
  assign q_1_io_enq_valid = auto_in_a_valid & toD; // @[CacheCork.scala 83:33]
  assign q_1_io_enq_bits_opcode = 3'h4; // @[Edges.scala 614:17 615:15]
  assign q_1_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign q_1_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign q_1_io_deq_ready = in_d_ready & allowed_1_2; // @[Arbiter.scala 123:31]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 2'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      beatsLeft <= initBeats;
    end else begin
      beatsLeft <= _beatsLeft_T_4;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state__1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state__1 <= earlyWinner__1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state__0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state__0 <= earlyWinner__0;
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 2'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 2'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft_1 <= 2'h0; // @[Arbiter.scala 87:30]
    end else if (latch_1) begin // @[Arbiter.scala 113:23]
      if (earlyWinner_1_0) begin // @[Arbiter.scala 111:73]
        if (opdata_2) begin // @[Edges.scala 220:14]
          beatsLeft_1 <= decode_2;
        end else begin
          beatsLeft_1 <= 2'h0;
        end
      end else begin
        beatsLeft_1 <= 2'h0;
      end
    end else begin
      beatsLeft_1 <= _beatsLeft_T_10;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1_0 <= earlyWinner_1_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1_1 <= earlyWinner_1_1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1_2 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1_2 <= earlyWinner_1_2;
    end
    if (d_first) begin // @[Reg.scala 20:18]
      bundleIn_0_d_bits_sink_r <= pool_io_alloc_bits; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~auto_in_c_valid | _c_d_valid_T | _c_a_valid_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at CacheCork.scala:106 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n"
            ); // @[CacheCork.scala 106:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~auto_in_c_valid | _c_d_valid_T | _c_a_valid_T) & ~reset) begin
          $fatal; // @[CacheCork.scala 106:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & _T_9) begin
          $fatal; // @[CacheCork.scala 114:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~earlyWinner__0 | ~earlyWinner__1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~earlyWinner__0 | ~earlyWinner__1) & _T_9) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(c_a_valid | a_a_valid) | (earlyWinner__0 | earlyWinner__1))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(c_a_valid | a_a_valid) | (earlyWinner__0 | earlyWinner__1)) & _T_9) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(_T_36 | _T_35)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_36 | _T_35) & _T_9) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~((~earlyWinner_1_0 | ~earlyWinner_1_1) & (~prefixOR_2 | ~earlyWinner_1_2))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~((~earlyWinner_1_0 | ~earlyWinner_1_1) & (~prefixOR_2 | ~earlyWinner_1_2)) & _T_9) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~_sink_ACancel_earlyValid_T_6 | (prefixOR_2 | earlyWinner_1_2))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_sink_ACancel_earlyValid_T_6 | (prefixOR_2 | earlyWinner_1_2)) & _T_9) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(_T_90 | _sink_ACancel_earlyValid_T_6)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_90 | _sink_ACancel_earlyValid_T_6) & _T_9) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  state__1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  state__0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  d_first_counter = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  beatsLeft_1 = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  state_1_0 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  state_1_1 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  state_1_2 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  bundleIn_0_d_bits_sink_r = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_12(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input         io_in_d_bits_source,
  input  [4:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire [10:0] _is_aligned_mask_T_1 = 11'hf << io_in_a_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask = ~_is_aligned_mask_T_1[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_62 = {{28'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_62; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
  wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_22 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire [32:0] _T_27 = $signed(_T_7) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_28 = $signed(_T_27) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_29 = _T_22 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_31 = _source_ok_T & _T_29; // @[Monitor.scala 82:72]
  wire  _T_60 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_64 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_65 = _T_64 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_69 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_73 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_122 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_135 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_146 = io_in_a_bits_size <= 3'h4; // @[Parameters.scala 92:42]
  wire  _T_154 = _T_146 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_165 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_169 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_177 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_195 = _source_ok_T & _T_154; // @[Monitor.scala 115:71]
  wire  _T_213 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_245 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_246 = io_in_a_bits_mask & _T_245; // @[Monitor.scala 127:31]
  wire  _T_247 = _T_246 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_251 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_259 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
  wire  _T_267 = _T_259 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_269 = _source_ok_T & _T_267; // @[Monitor.scala 131:74]
  wire  _T_279 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_287 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_315 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_323 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_351 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_363 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
  wire  _T_367 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_371 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_375 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_379 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_383 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_387 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_398 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_402 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_415 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_435 = _T_383 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_444 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_461 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_479 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_beats1_decode = is_aligned_mask[3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala 220:14]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_509 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_510 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_514 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_518 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_522 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_526 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _d_first_beats1_decode_T_1 = 11'hf << io_in_d_bits_size; // @[package.scala 234:77]
  wire [3:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  d_first_beats1_decode = _d_first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala 220:14]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg  source_1; // @[Monitor.scala 538:22]
  reg [4:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_533 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_534 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_538 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_542 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_546 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_550 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_554 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [2:0] _GEN_64 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_64}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_68 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_68 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_73 = {{12'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_560 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_563 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_75 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_75}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_355 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_355 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [18:0] _GEN_356 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [18:0] _a_sizes_set_T_1 = _GEN_356 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire  _T_567 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [18:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_571 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_573 = ~_T_367; // @[Monitor.scala 671:74]
  wire  _T_574 = io_in_d_valid & d_first_1 & ~_T_367; // @[Monitor.scala 671:71]
  wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_367 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _GEN_357 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_opcodes_clr_T_5 = _GEN_357 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_573 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_573 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_560 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire  _T_586 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_591 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_592 = io_in_d_bits_opcode == _GEN_32 | _T_591; // @[Monitor.scala 685:77]
  wire  _T_596 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_603 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_604 = io_in_d_bits_opcode == _GEN_48 | _T_603; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_79 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_608 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_618 = _T_571 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_573; // @[Monitor.scala 694:116]
  wire  _T_619 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_620 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set_wo_ready = _GEN_15[0];
  wire  d_clr_wo_ready = _GEN_21[0];
  wire  _T_627 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_636 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_81 = {{12'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_81 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_662 = io_in_d_valid & d_first_2 & _T_367; // @[Monitor.scala 779:71]
  wire [1:0] _GEN_66 = io_in_d_valid & d_first_2 & _T_367 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 779:89 780:22]
  wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_367 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire  _T_670 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_676 = io_in_d_bits_size == 3'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_680 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  d_clr_wo_ready_1 = _GEN_66[0];
  wire [3:0] d_sizes_clr_1 = _GEN_69[3:0];
  wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= a_first_beats1;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= a_first_beats1;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= d_first_beats1;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_60) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_60 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_65) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_65 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_60) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_60 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_122) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_122 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_65) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_65 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_73 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_73 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_154) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_154 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_135 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_135 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_165) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_165 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_213 & ~reset & ~_T_247) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_247 & (io_in_a_valid & _T_213 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_279) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_279 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_251 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_251 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_315) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_315 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_287 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_287 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_195) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_195 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_351) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_351 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_169) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_169 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_323 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_323 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_363) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_363 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_367 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_367 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_398) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_398 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_387 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_387 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_398) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_398 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_415 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_415 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_461 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_461 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_375) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_375 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_479 & _T_2 & ~_T_383) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_383 & (io_in_d_valid & _T_479 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_510) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_510 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_514) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_514 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_518) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_518 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_522) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_522 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & ~reset & ~_T_526) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_526 & (_T_509 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_534) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_534 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_538 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_542) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_542 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_546 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_550 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_533 & _T_2 & ~_T_554) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_554 & (_T_533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_563 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_563 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & _T_2 & ~_T_586) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_586 & (_T_574 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & same_cycle_resp & _T_2 & ~_T_592) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_592 & (_T_574 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & same_cycle_resp & _T_2 & ~_T_596) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & (_T_574 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & ~same_cycle_resp & _T_2 & ~_T_604) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_604 & (_T_574 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_574 & ~same_cycle_resp & _T_2 & ~_T_608) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_608 & (_T_574 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_618 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_618 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_662 & _T_2 & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & (_T_662 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_676 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_662 & _T_2 & ~_T_680) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:76:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_680 & (_T_662 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_619 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~d_clr_wo_ready_1 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[4:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[3:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_19[3:0];
  _RAND_20 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_20[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_33(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input         io_enq_bits_source,
  input  [31:0] io_enq_bits_address,
  input  [7:0]  io_enq_bits_mask,
  input  [63:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output        io_deq_bits_source,
  output [31:0] io_deq_bits_address,
  output [7:0]  io_deq_bits_mask,
  output [63:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_source [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_address [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 275:95]
  reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 275:95]
  reg [63:0] ram_data [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = enq_ptr_value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = enq_ptr_value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[7:0];
  _RAND_6 = {2{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[63:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  enq_ptr_value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  deq_ptr_value = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_34(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [1:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input         io_enq_bits_source,
  input  [4:0]  io_enq_bits_sink,
  input         io_enq_bits_denied,
  input  [63:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output        io_deq_bits_source,
  output [4:0]  io_deq_bits_sink,
  output        io_deq_bits_denied,
  output [63:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_param [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_source [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg [4:0] ram_sink [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [4:0] ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [4:0] ram_sink_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_denied [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_denied_MPORT_en; // @[Decoupled.scala 275:95]
  reg [63:0] ram_data [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
  assign ram_sink_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_sink_MPORT_data = io_enq_bits_sink;
  assign ram_sink_MPORT_addr = enq_ptr_value;
  assign ram_sink_MPORT_mask = 1'h1;
  assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
  assign ram_denied_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_denied_MPORT_data = io_enq_bits_denied;
  assign ram_denied_MPORT_addr = enq_ptr_value;
  assign ram_denied_MPORT_mask = 1'h1;
  assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
      ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
      ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_sink[initvar] = _RAND_4[4:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_denied[initvar] = _RAND_5[0:0];
  _RAND_6 = {2{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[63:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  enq_ptr_value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  deq_ptr_value = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input         auto_in_a_bits_source,
  input  [31:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [63:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output        auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [4:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [63:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 377:21]
  wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 377:21]
  wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [4:0] bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [4:0] bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  TLMonitor_12 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Queue_33 bundleOut_0_a_q ( // @[Decoupled.scala 377:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_34 bundleIn_0_d_q ( // @[Decoupled.scala 377:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 381:17]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_13(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_b_ready,
  input         io_in_b_valid,
  input  [2:0]  io_in_b_bits_opcode,
  input  [1:0]  io_in_b_bits_param,
  input  [2:0]  io_in_b_bits_size,
  input         io_in_b_bits_source,
  input  [31:0] io_in_b_bits_address,
  input  [7:0]  io_in_b_bits_mask,
  input         io_in_b_bits_corrupt,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [2:0]  io_in_c_bits_size,
  input         io_in_c_bits_source,
  input  [31:0] io_in_c_bits_address,
  input         io_in_c_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input         io_in_d_bits_source,
  input  [4:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt,
  input         io_in_e_ready,
  input         io_in_e_valid,
  input  [4:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire [10:0] _is_aligned_mask_T_1 = 11'hf << io_in_a_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask = ~_is_aligned_mask_T_1[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_74 = {{28'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_74; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire  _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
  wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_22 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire [32:0] _T_27 = $signed(_T_7) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_28 = $signed(_T_27) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_29 = _T_22 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_31 = _source_ok_T & _T_29; // @[Monitor.scala 82:72]
  wire  _T_61 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_65 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_66 = _T_65 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_70 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_74 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_124 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_137 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_148 = io_in_a_bits_size <= 3'h4; // @[Parameters.scala 92:42]
  wire  _T_156 = _T_148 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_167 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_171 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_179 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_197 = _source_ok_T & _T_156; // @[Monitor.scala 115:71]
  wire  _T_215 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_247 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_248 = io_in_a_bits_mask & _T_247; // @[Monitor.scala 127:31]
  wire  _T_249 = _T_248 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_253 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_261 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
  wire  _T_269 = _T_261 & _T_28; // @[Parameters.scala 670:56]
  wire  _T_271 = _source_ok_T & _T_269; // @[Monitor.scala 131:74]
  wire  _T_281 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_289 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_317 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_325 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_353 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_365 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
  wire  _T_369 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_373 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_377 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_381 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_385 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_389 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_400 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_404 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_417 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_437 = _T_385 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_446 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_463 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_481 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _T_498 = io_in_b_bits_opcode <= 3'h6; // @[Bundles.scala 40:24]
  wire  _T_502 = ~io_in_b_bits_source; // @[Parameters.scala 46:9]
  wire  _T_503 = ~_T_502; // @[Monitor.scala 63:7]
  wire [32:0] _T_505 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 137:49]
  wire [32:0] _address_ok_T_3 = $signed(_T_505) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 33'sh0; // @[Parameters.scala 137:67]
  wire [10:0] _is_aligned_mask_T_4 = 11'hf << io_in_b_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask_1 = ~_is_aligned_mask_T_4[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_76 = {{28'd0}, is_aligned_mask_1}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T_1 = io_in_b_bits_address & _GEN_76; // @[Edges.scala 20:16]
  wire  is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount_1 = io_in_b_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH_1 = _mask_sizeOH_T_4[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T_1 = io_in_b_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size_3 = mask_sizeOH_1[2]; // @[Misc.scala 208:26]
  wire  mask_bit_3 = io_in_b_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit_3 = ~mask_bit_3; // @[Misc.scala 210:20]
  wire  mask_acc_14 = _mask_T_1 | mask_size_3 & mask_nbit_3; // @[Misc.scala 214:29]
  wire  mask_acc_15 = _mask_T_1 | mask_size_3 & mask_bit_3; // @[Misc.scala 214:29]
  wire  mask_size_4 = mask_sizeOH_1[1]; // @[Misc.scala 208:26]
  wire  mask_bit_4 = io_in_b_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_4 = ~mask_bit_4; // @[Misc.scala 210:20]
  wire  mask_eq_16 = mask_nbit_3 & mask_nbit_4; // @[Misc.scala 213:27]
  wire  mask_acc_16 = mask_acc_14 | mask_size_4 & mask_eq_16; // @[Misc.scala 214:29]
  wire  mask_eq_17 = mask_nbit_3 & mask_bit_4; // @[Misc.scala 213:27]
  wire  mask_acc_17 = mask_acc_14 | mask_size_4 & mask_eq_17; // @[Misc.scala 214:29]
  wire  mask_eq_18 = mask_bit_3 & mask_nbit_4; // @[Misc.scala 213:27]
  wire  mask_acc_18 = mask_acc_15 | mask_size_4 & mask_eq_18; // @[Misc.scala 214:29]
  wire  mask_eq_19 = mask_bit_3 & mask_bit_4; // @[Misc.scala 213:27]
  wire  mask_acc_19 = mask_acc_15 | mask_size_4 & mask_eq_19; // @[Misc.scala 214:29]
  wire  mask_size_5 = mask_sizeOH_1[0]; // @[Misc.scala 208:26]
  wire  mask_bit_5 = io_in_b_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_5 = ~mask_bit_5; // @[Misc.scala 210:20]
  wire  mask_eq_20 = mask_eq_16 & mask_nbit_5; // @[Misc.scala 213:27]
  wire  mask_acc_20 = mask_acc_16 | mask_size_5 & mask_eq_20; // @[Misc.scala 214:29]
  wire  mask_eq_21 = mask_eq_16 & mask_bit_5; // @[Misc.scala 213:27]
  wire  mask_acc_21 = mask_acc_16 | mask_size_5 & mask_eq_21; // @[Misc.scala 214:29]
  wire  mask_eq_22 = mask_eq_17 & mask_nbit_5; // @[Misc.scala 213:27]
  wire  mask_acc_22 = mask_acc_17 | mask_size_5 & mask_eq_22; // @[Misc.scala 214:29]
  wire  mask_eq_23 = mask_eq_17 & mask_bit_5; // @[Misc.scala 213:27]
  wire  mask_acc_23 = mask_acc_17 | mask_size_5 & mask_eq_23; // @[Misc.scala 214:29]
  wire  mask_eq_24 = mask_eq_18 & mask_nbit_5; // @[Misc.scala 213:27]
  wire  mask_acc_24 = mask_acc_18 | mask_size_5 & mask_eq_24; // @[Misc.scala 214:29]
  wire  mask_eq_25 = mask_eq_18 & mask_bit_5; // @[Misc.scala 213:27]
  wire  mask_acc_25 = mask_acc_18 | mask_size_5 & mask_eq_25; // @[Misc.scala 214:29]
  wire  mask_eq_26 = mask_eq_19 & mask_nbit_5; // @[Misc.scala 213:27]
  wire  mask_acc_26 = mask_acc_19 | mask_size_5 & mask_eq_26; // @[Misc.scala 214:29]
  wire  mask_eq_27 = mask_eq_19 & mask_bit_5; // @[Misc.scala 213:27]
  wire  mask_acc_27 = mask_acc_19 | mask_size_5 & mask_eq_27; // @[Misc.scala 214:29]
  wire [7:0] mask_1 = {mask_acc_27,mask_acc_26,mask_acc_25,mask_acc_24,mask_acc_23,mask_acc_22,mask_acc_21,mask_acc_20}; // @[Cat.scala 33:92]
  wire  _T_513 = io_in_b_bits_opcode == 3'h6; // @[Monitor.scala 167:25]
  wire  _T_514 = 3'h4 == io_in_b_bits_size; // @[Parameters.scala 91:48]
  wire  _T_526 = _T_514 & _address_ok_T_4; // @[Monitor.scala 168:75]
  wire  _T_532 = ~_address_ok_T_4; // @[Monitor.scala 49:11]
  wire  _T_538 = ~is_aligned_1; // @[Monitor.scala 49:11]
  wire  _T_539 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_543 = io_in_b_bits_mask == mask_1; // @[Monitor.scala 173:27]
  wire  _T_546 = ~_T_543; // @[Monitor.scala 49:11]
  wire  _T_547 = ~io_in_b_bits_corrupt; // @[Monitor.scala 174:15]
  wire  _T_550 = ~_T_547; // @[Monitor.scala 49:11]
  wire  _T_551 = io_in_b_bits_opcode == 3'h4; // @[Monitor.scala 177:25]
  wire  _T_576 = io_in_b_bits_param == 2'h0; // @[Monitor.scala 182:31]
  wire  _T_588 = io_in_b_bits_opcode == 3'h0; // @[Monitor.scala 187:25]
  wire  _T_621 = io_in_b_bits_opcode == 3'h1; // @[Monitor.scala 196:25]
  wire [7:0] _T_650 = ~mask_1; // @[Monitor.scala 202:33]
  wire [7:0] _T_651 = io_in_b_bits_mask & _T_650; // @[Monitor.scala 202:31]
  wire  _T_652 = _T_651 == 8'h0; // @[Monitor.scala 202:40]
  wire  _T_656 = io_in_b_bits_opcode == 3'h2; // @[Monitor.scala 205:25]
  wire  _T_689 = io_in_b_bits_opcode == 3'h3; // @[Monitor.scala 214:25]
  wire  _T_722 = io_in_b_bits_opcode == 3'h5; // @[Monitor.scala 223:25]
  wire  _source_ok_T_2 = ~io_in_c_bits_source; // @[Parameters.scala 46:9]
  wire [10:0] _is_aligned_mask_T_7 = 11'hf << io_in_c_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_80 = {{28'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_80; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala 20:24]
  wire [32:0] _address_ok_T_6 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 137:49]
  wire [32:0] _address_ok_T_8 = $signed(_address_ok_T_6) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_760 = ~_source_ok_T_2; // @[Monitor.scala 63:7]
  wire  _T_770 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_777 = io_in_c_bits_size >= 3'h3; // @[Monitor.scala 245:30]
  wire  _T_784 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_788 = ~io_in_c_bits_corrupt; // @[Monitor.scala 248:18]
  wire  _T_792 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_810 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_817 = 3'h4 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_824 = _T_817 & _address_ok_T_9; // @[Parameters.scala 670:56]
  wire  _T_826 = _source_ok_T_2 & _T_824; // @[Monitor.scala 260:78]
  wire  _T_864 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_914 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_924 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_932 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_946 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_beats1_decode = is_aligned_mask[3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala 220:14]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_968 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_969 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_973 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_977 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_981 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_985 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _d_first_beats1_decode_T_1 = 11'hf << io_in_d_bits_size; // @[package.scala 234:77]
  wire [3:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  d_first_beats1_decode = _d_first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala 220:14]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg  source_1; // @[Monitor.scala 538:22]
  reg [4:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_992 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_993 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_997 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1001 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1005 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1009 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1013 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  wire  _b_first_T = io_in_b_ready & io_in_b_valid; // @[Decoupled.scala 52:35]
  reg  b_first_counter; // @[Edges.scala 228:27]
  wire  b_first_counter1 = b_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  b_first = ~b_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_2; // @[Monitor.scala 407:22]
  reg [1:0] param_2; // @[Monitor.scala 408:22]
  reg [2:0] size_2; // @[Monitor.scala 409:22]
  reg  source_2; // @[Monitor.scala 410:22]
  reg [31:0] address_1; // @[Monitor.scala 411:22]
  wire  _T_1020 = io_in_b_valid & ~b_first; // @[Monitor.scala 412:19]
  wire  _T_1021 = io_in_b_bits_opcode == opcode_2; // @[Monitor.scala 413:32]
  wire  _T_1025 = io_in_b_bits_param == param_2; // @[Monitor.scala 414:32]
  wire  _T_1029 = io_in_b_bits_size == size_2; // @[Monitor.scala 415:32]
  wire  _T_1033 = io_in_b_bits_source == source_2; // @[Monitor.scala 416:32]
  wire  _T_1037 = io_in_b_bits_address == address_1; // @[Monitor.scala 417:32]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 52:35]
  wire  c_first_beats1_decode = is_aligned_mask_2[3]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  wire  c_first_beats1 = c_first_beats1_opdata & c_first_beats1_decode; // @[Edges.scala 220:14]
  reg  c_first_counter; // @[Edges.scala 228:27]
  wire  c_first_counter1 = c_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  c_first = ~c_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [2:0] size_3; // @[Monitor.scala 514:22]
  reg  source_3; // @[Monitor.scala 515:22]
  reg [31:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_1044 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_1045 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_1049 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_1053 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_1057 = io_in_c_bits_source == source_3; // @[Monitor.scala 521:32]
  wire  _T_1061 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [2:0] _GEN_86 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_86}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_87 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_90 = {{12'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_90 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1067 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_27 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1070 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_92 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_92}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_634 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_634 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [18:0] _GEN_635 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [18:0] _a_sizes_set_T_1 = _GEN_635 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire  _T_1074 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
  wire [1:0] _GEN_28 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [18:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1078 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1080 = ~_T_369; // @[Monitor.scala 671:74]
  wire  _T_1081 = io_in_d_valid & d_first_1 & ~_T_369; // @[Monitor.scala 671:71]
  wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_33 = io_in_d_valid & d_first_1 & ~_T_369 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _GEN_636 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_opcodes_clr_T_5 = _GEN_636 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_34 = _d_first_T & d_first_1 & _T_1080 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_35 = _d_first_T & d_first_1 & _T_1080 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1067 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire  _T_1093 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_1098 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_1099 = io_in_d_bits_opcode == _GEN_44 | _T_1098; // @[Monitor.scala 685:77]
  wire  _T_1103 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_1110 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_1111 = io_in_d_bits_opcode == _GEN_60 | _T_1110; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_96 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1115 = _GEN_96 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1125 = _T_1078 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1080; // @[Monitor.scala 694:116]
  wire  _T_1126 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_1127 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set_wo_ready = _GEN_27[0];
  wire  d_clr_wo_ready = _GEN_33[0];
  wire  _T_1134 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire  a_set = _GEN_28[0];
  wire  d_clr = _GEN_34[0];
  wire [3:0] a_opcodes_set = _GEN_31[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_35[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_32[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1143 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg  inflight_1; // @[Monitor.scala 723:35]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  c_first_counter_1; // @[Edges.scala 228:27]
  wire  c_first_counter1_1 = c_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = ~c_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_98 = {{12'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_98 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1153 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_1154 = io_in_c_valid & c_first_1 & _T_1153; // @[Monitor.scala 756:37]
  wire [1:0] _c_set_wo_ready_T = 2'h1 << io_in_c_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_72 = io_in_c_valid & c_first_1 & _T_1153 ? _c_set_wo_ready_T : 2'h0; // @[Monitor.scala 756:71 757:22]
  wire  _T_1160 = _c_first_T & c_first_1 & _T_1153; // @[Monitor.scala 760:38]
  wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [3:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 4'h1; // @[Monitor.scala 763:59]
  wire [2:0] _GEN_100 = {io_in_c_bits_source, 2'h0}; // @[Monitor.scala 765:77]
  wire [3:0] _c_sizes_set_T = {{1'd0}, _GEN_100}; // @[Monitor.scala 765:77]
  wire [3:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_1153 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 760:72 763:28]
  wire [18:0] _GEN_638 = {{15'd0}, c_sizes_set_interm}; // @[Monitor.scala 765:52]
  wire [18:0] _c_sizes_set_T_1 = _GEN_638 << _c_sizes_set_T; // @[Monitor.scala 765:52]
  wire  _T_1163 = ~(inflight_1 >> io_in_c_bits_source); // @[Monitor.scala 766:17]
  wire [1:0] _GEN_73 = _c_first_T & c_first_1 & _T_1153 ? _c_set_wo_ready_T : 2'h0; // @[Monitor.scala 760:72 761:28]
  wire [18:0] _GEN_77 = _c_first_T & c_first_1 & _T_1153 ? _c_sizes_set_T_1 : 19'h0; // @[Monitor.scala 760:72 765:28]
  wire  _T_1167 = io_in_d_valid & d_first_2; // @[Monitor.scala 779:26]
  wire  _T_1169 = io_in_d_valid & d_first_2 & _T_369; // @[Monitor.scala 779:71]
  wire [1:0] _GEN_78 = io_in_d_valid & d_first_2 & _T_369 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 779:89 780:22]
  wire [1:0] _GEN_79 = _d_first_T & d_first_2 & _T_369 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 783:90 784:21]
  wire [30:0] _GEN_81 = _d_first_T & d_first_2 & _T_369 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire  _same_cycle_resp_T_8 = io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:113]
  wire  same_cycle_resp_1 = _T_1154 & io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:88]
  wire  _T_1179 = inflight_1 >> io_in_d_bits_source | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_1183 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1187 = _GEN_96 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_1196 = _T_1167 & c_first_1 & io_in_c_valid & _same_cycle_resp_T_8 & _T_369; // @[Monitor.scala 799:116]
  wire  _T_1198 = _T_1126 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire  c_set_wo_ready = _GEN_72[0];
  wire  _T_1202 = |c_set_wo_ready; // @[Monitor.scala 804:28]
  wire  d_clr_wo_ready_1 = _GEN_78[0];
  wire  _T_1203 = c_set_wo_ready != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire  c_set = _GEN_73[0];
  wire  d_clr_1 = _GEN_79[0];
  wire [3:0] c_sizes_set = _GEN_77[3:0];
  wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [3:0] d_sizes_clr_1 = _GEN_81[3:0];
  wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1212 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [31:0] inflight_2; // @[Monitor.scala 823:27]
  reg  d_first_counter_3; // @[Edges.scala 228:27]
  wire  d_first_counter1_3 = d_first_counter_3 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = ~d_first_counter_3; // @[Edges.scala 230:25]
  wire  _T_1224 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_1225 = _d_first_T & d_first_3 & _T_1224; // @[Monitor.scala 829:38]
  wire [31:0] _d_set_T = 32'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [31:0] _T_1226 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_1228 = ~_T_1226[0]; // @[Monitor.scala 831:14]
  wire [31:0] d_set = _d_first_T & d_first_3 & _T_1224 ? _d_set_T : 32'h0; // @[Monitor.scala 829:72 830:13]
  wire  _T_1232 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala 52:35]
  wire [31:0] _e_clr_T = 32'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [31:0] _T_1235 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [31:0] _T_1236 = _T_1235 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [31:0] e_clr = _T_1232 ? _e_clr_T : 32'h0; // @[Monitor.scala 835:73 836:13]
  wire [31:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [31:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [31:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= a_first_beats1;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      b_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_b_first_T) begin // @[Edges.scala 234:17]
      if (b_first) begin // @[Edges.scala 235:21]
        b_first_counter <= 1'h0;
      end else begin
        b_first_counter <= b_first_counter1;
      end
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      opcode_2 <= io_in_b_bits_opcode; // @[Monitor.scala 420:15]
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      param_2 <= io_in_b_bits_param; // @[Monitor.scala 421:15]
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      size_2 <= io_in_b_bits_size; // @[Monitor.scala 422:15]
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      source_2 <= io_in_b_bits_source; // @[Monitor.scala 423:15]
    end
    if (_b_first_T & b_first) begin // @[Monitor.scala 419:32]
      address_1 <= io_in_b_bits_address; // @[Monitor.scala 424:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        c_first_counter <= c_first_beats1;
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      source_3 <= io_in_c_bits_source; // @[Monitor.scala 528:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= a_first_beats1;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 1'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= (inflight_1 | c_set) & ~d_clr_1; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        c_first_counter_1 <= c_first_beats1;
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= d_first_beats1;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 32'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        d_first_counter_3 <= d_first_beats1;
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_29) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_29 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_61) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_61 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_66) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_66 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_29) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_29 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_61) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_61 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_124) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_124 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_66) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_66 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_74 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_74 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~_T_156) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_156 & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~_T_167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_167 & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_137 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_137 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & ~_T_197) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_197 & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & ~_T_167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_167 & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_179 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_179 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & ~_T_197) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_197 & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & ~_T_167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_167 & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_215 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_215 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & ~_T_271) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_271 & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & ~_T_281) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_281 & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_253 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_253 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & ~_T_271) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_271 & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & ~_T_317) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_317 & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_289 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_197) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_197 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_353) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_353 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_171 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_325 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_325 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_365) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_365 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_T_373) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_373 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_381 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_369 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_369 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_373) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_373 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_400) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_400 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_404) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_404 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_381 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_389 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_373) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_373 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_400) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_400 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_404) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_404 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_417 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_417 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_381 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_463 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_463 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_463 & _T_2 & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_d_valid & _T_463 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_463 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_463 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_463 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_463 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_381 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & ~reset & ~_T_498) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel has invalid opcode (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_498 & (io_in_b_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_513 & _T_2 & ~_T_526) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_526 & (io_in_b_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_513 & _T_2 & ~_address_ok_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_513 & _T_2 & _T_503) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries source that is not first source (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_502 & (io_in_b_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_513 & _T_2 & ~is_aligned_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_513 & _T_2 & ~_T_539) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_539 & (io_in_b_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_513 & _T_2 & ~_T_543) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_543 & (io_in_b_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_513 & _T_2 & ~_T_547) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_547 & (io_in_b_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_551 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_b_valid & _T_551 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_551 & ~reset & _T_532) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_551 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_551 & ~reset & _T_503) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get carries source that is not first source (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_502 & (io_in_b_valid & _T_551 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_551 & ~reset & _T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_551 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_551 & ~reset & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (io_in_b_valid & _T_551 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_551 & ~reset & _T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_543 & (io_in_b_valid & _T_551 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_551 & ~reset & _T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_547 & (io_in_b_valid & _T_551 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_588 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_b_valid & _T_588 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_588 & ~reset & _T_532) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_588 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_588 & ~reset & _T_503) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_502 & (io_in_b_valid & _T_588 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_588 & ~reset & _T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_588 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_588 & ~reset & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (io_in_b_valid & _T_588 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_588 & ~reset & _T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_543 & (io_in_b_valid & _T_588 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_621 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_b_valid & _T_621 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_621 & ~reset & _T_532) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_621 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_621 & ~reset & _T_503) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_502 & (io_in_b_valid & _T_621 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_621 & ~reset & _T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_621 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_621 & ~reset & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (io_in_b_valid & _T_621 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_621 & ~reset & ~_T_652) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_652 & (io_in_b_valid & _T_621 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_656 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_b_valid & _T_656 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_656 & ~reset & _T_532) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_656 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_656 & ~reset & _T_503) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_502 & (io_in_b_valid & _T_656 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_656 & ~reset & _T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_656 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & _T_656 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_656 & ~reset & _T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_543 & (io_in_b_valid & _T_656 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_689 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_b_valid & _T_689 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_689 & ~reset & _T_532) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_689 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_689 & ~reset & _T_503) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical carries source that is not first source (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_502 & (io_in_b_valid & _T_689 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_689 & ~reset & _T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_689 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_b_valid & _T_689 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_689 & ~reset & _T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_543 & (io_in_b_valid & _T_689 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_722 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_b_valid & _T_722 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_722 & ~reset & _T_532) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_722 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_722 & ~reset & _T_503) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint carries source that is not first source (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_502 & (io_in_b_valid & _T_722 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_722 & ~reset & _T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_722 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_722 & ~reset & _T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint contains invalid mask (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_543 & (io_in_b_valid & _T_722 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_722 & ~reset & _T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_547 & (io_in_b_valid & _T_722 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_c_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~_T_784) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_784 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_770 & ~reset & ~_T_788) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_788 & (io_in_c_valid & _T_770 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_792 & ~reset & ~_T_784) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_784 & (io_in_c_valid & _T_792 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_826) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_826 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_824) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_824 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_784) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_784 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_810 & ~reset & ~_T_788) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_788 & (io_in_c_valid & _T_810 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~_T_826) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_826 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~_T_824) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_824 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_864 & ~reset & ~_T_784) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_784 & (io_in_c_valid & _T_864 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & ~_T_924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_924 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_914 & ~reset & ~_T_788) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_788 & (io_in_c_valid & _T_914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_932 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_932 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_932 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_932 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_932 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_932 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_932 & ~reset & ~_T_924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_924 & (io_in_c_valid & _T_932 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & _T_760) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_2 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & ~_T_924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_924 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_946 & ~reset & ~_T_788) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck is corrupt (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_788 & (io_in_c_valid & _T_946 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_969) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_969 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_973) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_973 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_977) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_977 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_981) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_981 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_968 & ~reset & ~_T_985) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_985 & (_T_968 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_993) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_993 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_997) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_997 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_1001) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1001 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_1005) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1005 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_1009) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1009 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_992 & _T_2 & ~_T_1013) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1013 & (_T_992 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1020 & ~reset & ~_T_1021) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1021 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1020 & ~reset & ~_T_1025) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel param changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1025 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1020 & ~reset & ~_T_1029) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel size changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1029 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1020 & ~reset & ~_T_1033) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel source changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1033 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1020 & ~reset & ~_T_1037) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1037 & (_T_1020 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1045) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1045 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1049) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1049 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1053) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1053 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1057) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel source changed within multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1057 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1061) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1061 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1070 & ~reset & ~_T_1074) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1074 & (_T_1070 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & _T_2 & ~_T_1093) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1093 & (_T_1081 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & same_cycle_resp & _T_2 & ~_T_1099) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1099 & (_T_1081 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & same_cycle_resp & _T_2 & ~_T_1103) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1103 & (_T_1081 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & ~same_cycle_resp & _T_2 & ~_T_1111) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1111 & (_T_1081 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1081 & ~same_cycle_resp & _T_2 & ~_T_1115) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1115 & (_T_1081 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1125 & _T_2 & ~_T_1127) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1127 & (_T_1125 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1134) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1134 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1143) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1143 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1160 & ~reset & ~_T_1163) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1163 & (_T_1160 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1169 & _T_2 & ~_T_1179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1179 & (_T_1169 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1169 & same_cycle_resp_1 & _T_2 & ~_T_1183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1183 & (_T_1169 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1169 & ~same_cycle_resp_1 & _T_2 & ~_T_1187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1187 & (_T_1169 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1196 & _T_2 & ~_T_1198) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1198 & (_T_1196 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1202 & _T_2 & ~_T_1203) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' and 'D' concurrent, despite minlatency 4 (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1203 & (_T_1202 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1212) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1212 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1225 & _T_2 & ~_T_1228) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1228 & (_T_1225 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1232 & ~reset & ~_T_1236[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at Rift2Link.scala:77:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1236[0] & (_T_1232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[4:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  b_first_counter = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  opcode_2 = _RAND_14[2:0];
  _RAND_15 = {1{`RANDOM}};
  param_2 = _RAND_15[1:0];
  _RAND_16 = {1{`RANDOM}};
  size_2 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  source_2 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  address_1 = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  c_first_counter = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  opcode_3 = _RAND_20[2:0];
  _RAND_21 = {1{`RANDOM}};
  param_3 = _RAND_21[2:0];
  _RAND_22 = {1{`RANDOM}};
  size_3 = _RAND_22[2:0];
  _RAND_23 = {1{`RANDOM}};
  source_3 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  address_2 = _RAND_24[31:0];
  _RAND_25 = {1{`RANDOM}};
  inflight = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  inflight_opcodes = _RAND_26[3:0];
  _RAND_27 = {1{`RANDOM}};
  inflight_sizes = _RAND_27[3:0];
  _RAND_28 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  watchdog = _RAND_30[31:0];
  _RAND_31 = {1{`RANDOM}};
  inflight_1 = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_32[3:0];
  _RAND_33 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  watchdog_1 = _RAND_35[31:0];
  _RAND_36 = {1{`RANDOM}};
  inflight_2 = _RAND_36[31:0];
  _RAND_37 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_37[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_37(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [1:0]  io_enq_bits_param,
  input  [31:0] io_enq_bits_address,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output        io_deq_bits_source,
  output [31:0] io_deq_bits_address,
  output [7:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_param [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_source [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_address [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 275:95]
  reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_opcode_MPORT_data = 3'h6;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = 3'h4;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_source_MPORT_data = 1'h0;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = enq_ptr_value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_mask_MPORT_data = 8'hff;
  assign ram_mask_MPORT_addr = enq_ptr_value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_corrupt_MPORT_data = 1'h0;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  enq_ptr_value = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  deq_ptr_value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  maybe_full = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_38(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input         io_enq_bits_source,
  input  [31:0] io_enq_bits_address,
  input  [63:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output        io_deq_bits_source,
  output [31:0] io_deq_bits_address,
  output [63:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_source [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_address [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 275:95]
  reg [63:0] ram_data [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = enq_ptr_value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = enq_ptr_value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = enq_ptr_value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = enq_ptr_value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = enq_ptr_value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = enq_ptr_value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[31:0];
  _RAND_5 = {2{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_5[63:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  enq_ptr_value = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  deq_ptr_value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  maybe_full = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_39(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input  [4:0] io_enq_bits_sink,
  output       io_deq_valid,
  output [4:0] io_deq_bits_sink
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [4:0] ram_sink [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [4:0] ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [4:0] ram_sink_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_sink_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
  assign ram_sink_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_sink_MPORT_data = io_enq_bits_sink;
  assign ram_sink_MPORT_addr = enq_ptr_value;
  assign ram_sink_MPORT_mask = 1'h1;
  assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
      ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (io_deq_valid) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != io_deq_valid) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_sink[initvar] = _RAND_0[4:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  enq_ptr_value = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  deq_ptr_value = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_1(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input         auto_in_a_bits_source,
  input  [31:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [31:0] auto_in_b_bits_address,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [2:0]  auto_in_c_bits_size,
  input         auto_in_c_bits_source,
  input  [31:0] auto_in_c_bits_address,
  input  [63:0] auto_in_c_bits_data,
  input         auto_in_c_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output        auto_in_d_bits_source,
  output [4:0]  auto_in_d_bits_sink,
  output [63:0] auto_in_d_bits_data,
  output        auto_in_e_ready,
  input         auto_in_e_valid,
  input  [4:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output        auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_param,
  input  [31:0] auto_out_b_bits_address,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [2:0]  auto_out_c_bits_size,
  output        auto_out_c_bits_source,
  output [31:0] auto_out_c_bits_address,
  output [63:0] auto_out_c_bits_data,
  output        auto_out_c_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [4:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [63:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt,
  output        auto_out_e_valid,
  output [4:0]  auto_out_e_bits_sink
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_b_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_b_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_b_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_b_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_b_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 377:21]
  wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 377:21]
  wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [4:0] bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [4:0] bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_b_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [31:0] bundleIn_0_b_q_io_enq_bits_address; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_b_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_b_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_b_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleIn_0_b_q_io_deq_bits_address; // @[Decoupled.scala 377:21]
  wire [7:0] bundleIn_0_b_q_io_deq_bits_mask; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_c_q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_c_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_c_q_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_c_q_io_enq_bits_address; // @[Decoupled.scala 377:21]
  wire [63:0] bundleOut_0_c_q_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_c_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_c_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_c_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_c_q_io_deq_bits_address; // @[Decoupled.scala 377:21]
  wire [63:0] bundleOut_0_c_q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_c_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_e_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_e_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_e_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_e_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [4:0] bundleOut_0_e_q_io_enq_bits_sink; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_e_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [4:0] bundleOut_0_e_q_io_deq_bits_sink; // @[Decoupled.scala 377:21]
  TLMonitor_13 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_b_ready(monitor_io_in_b_ready),
    .io_in_b_valid(monitor_io_in_b_valid),
    .io_in_b_bits_opcode(monitor_io_in_b_bits_opcode),
    .io_in_b_bits_param(monitor_io_in_b_bits_param),
    .io_in_b_bits_size(monitor_io_in_b_bits_size),
    .io_in_b_bits_source(monitor_io_in_b_bits_source),
    .io_in_b_bits_address(monitor_io_in_b_bits_address),
    .io_in_b_bits_mask(monitor_io_in_b_bits_mask),
    .io_in_b_bits_corrupt(monitor_io_in_b_bits_corrupt),
    .io_in_c_ready(monitor_io_in_c_ready),
    .io_in_c_valid(monitor_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_io_in_c_bits_size),
    .io_in_c_bits_source(monitor_io_in_c_bits_source),
    .io_in_c_bits_address(monitor_io_in_c_bits_address),
    .io_in_c_bits_corrupt(monitor_io_in_c_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt),
    .io_in_e_ready(monitor_io_in_e_ready),
    .io_in_e_valid(monitor_io_in_e_valid),
    .io_in_e_bits_sink(monitor_io_in_e_bits_sink)
  );
  Queue_33 bundleOut_0_a_q ( // @[Decoupled.scala 377:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_34 bundleIn_0_d_q ( // @[Decoupled.scala 377:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  Queue_37 bundleIn_0_b_q ( // @[Decoupled.scala 377:21]
    .clock(bundleIn_0_b_q_clock),
    .reset(bundleIn_0_b_q_reset),
    .io_enq_ready(bundleIn_0_b_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_b_q_io_enq_valid),
    .io_enq_bits_param(bundleIn_0_b_q_io_enq_bits_param),
    .io_enq_bits_address(bundleIn_0_b_q_io_enq_bits_address),
    .io_deq_ready(bundleIn_0_b_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_b_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_b_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_b_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_b_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_b_q_io_deq_bits_source),
    .io_deq_bits_address(bundleIn_0_b_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleIn_0_b_q_io_deq_bits_mask),
    .io_deq_bits_corrupt(bundleIn_0_b_q_io_deq_bits_corrupt)
  );
  Queue_38 bundleOut_0_c_q ( // @[Decoupled.scala 377:21]
    .clock(bundleOut_0_c_q_clock),
    .reset(bundleOut_0_c_q_reset),
    .io_enq_ready(bundleOut_0_c_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_c_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_c_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_c_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_c_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_c_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_c_q_io_enq_bits_address),
    .io_enq_bits_data(bundleOut_0_c_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_c_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_c_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_c_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_c_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_c_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_c_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_c_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_c_q_io_deq_bits_address),
    .io_deq_bits_data(bundleOut_0_c_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_c_q_io_deq_bits_corrupt)
  );
  Queue_39 bundleOut_0_e_q ( // @[Decoupled.scala 377:21]
    .clock(bundleOut_0_e_q_clock),
    .reset(bundleOut_0_e_q_reset),
    .io_enq_ready(bundleOut_0_e_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_e_q_io_enq_valid),
    .io_enq_bits_sink(bundleOut_0_e_q_io_enq_bits_sink),
    .io_deq_valid(bundleOut_0_e_q_io_deq_valid),
    .io_deq_bits_sink(bundleOut_0_e_q_io_deq_bits_sink)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_b_valid = bundleIn_0_b_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_b_bits_address = bundleIn_0_b_q_io_deq_bits_address; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_c_ready = bundleOut_0_c_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_e_ready = bundleOut_0_e_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_b_ready = bundleIn_0_b_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 381:17]
  assign auto_out_c_valid = bundleOut_0_c_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_opcode = bundleOut_0_c_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_param = bundleOut_0_c_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_size = bundleOut_0_c_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_source = bundleOut_0_c_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_address = bundleOut_0_c_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_data = bundleOut_0_c_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_corrupt = bundleOut_0_c_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 381:17]
  assign auto_out_e_valid = bundleOut_0_e_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 43:15]
  assign auto_out_e_bits_sink = bundleOut_0_e_q_io_deq_bits_sink; // @[Nodes.scala 1207:84 Buffer.scala 43:15]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_valid = bundleIn_0_b_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_opcode = bundleIn_0_b_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_param = bundleIn_0_b_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_size = bundleIn_0_b_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_source = bundleIn_0_b_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_address = bundleIn_0_b_q_io_deq_bits_address; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_mask = bundleIn_0_b_q_io_deq_bits_mask; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_corrupt = bundleIn_0_b_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_c_ready = bundleOut_0_c_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign monitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_e_ready = bundleOut_0_e_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign monitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_b_q_clock = clock;
  assign bundleIn_0_b_q_reset = reset;
  assign bundleIn_0_b_q_io_enq_valid = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_q_io_enq_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_q_io_enq_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_q_io_deq_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_clock = clock;
  assign bundleOut_0_c_q_reset = reset;
  assign bundleOut_0_c_q_io_enq_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_data = auto_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_deq_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_e_q_clock = clock;
  assign bundleOut_0_e_q_reset = reset;
  assign bundleOut_0_e_q_io_enq_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_e_q_io_enq_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_14(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [31:0] io_in_a_bits_address,
  input  [7:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input         io_in_d_bits_source,
  input  [4:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [10:0] _is_aligned_mask_T_1 = 11'hf << io_in_a_bits_size; // @[package.scala 234:77]
  wire [3:0] is_aligned_mask = ~_is_aligned_mask_T_1[3:0]; // @[package.scala 234:46]
  wire [31:0] _GEN_62 = {{28'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_62; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
  wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
  wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire  mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
  wire  mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
  wire  mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
  wire  mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
  wire  mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
  wire  mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
  wire  mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
  wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 33:92]
  wire [32:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_32 = 3'h4 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire [32:0] _T_37 = $signed(_T_12) & 33'sh100000000; // @[Parameters.scala 137:52]
  wire  _T_38 = $signed(_T_37) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _T_39 = _T_32 & _T_38; // @[Parameters.scala 670:56]
  wire  _T_70 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [7:0] _T_74 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_75 = _T_74 == 8'h0; // @[Monitor.scala 88:31]
  wire  _T_79 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_83 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_137 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_150 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_166 = io_in_a_bits_size <= 3'h4; // @[Parameters.scala 92:42]
  wire  _T_174 = _T_166 & _T_38; // @[Parameters.scala 670:56]
  wire  _T_185 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_189 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_197 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_238 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [7:0] _T_275 = ~mask; // @[Monitor.scala 127:33]
  wire [7:0] _T_276 = io_in_a_bits_mask & _T_275; // @[Monitor.scala 127:31]
  wire  _T_277 = _T_276 == 8'h0; // @[Monitor.scala 127:40]
  wire  _T_281 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_294 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
  wire  _T_302 = _T_294 & _T_38; // @[Parameters.scala 670:56]
  wire  _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_355 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_363 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_396 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_408 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_412 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_416 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
  wire  _T_420 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_424 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_428 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_432 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_443 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_447 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_460 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_480 = _T_428 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_489 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_506 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_524 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire  a_first_beats1_decode = is_aligned_mask[3]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala 220:14]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [31:0] address; // @[Monitor.scala 388:22]
  wire  _T_554 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_555 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_559 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_563 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_567 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_571 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [10:0] _d_first_beats1_decode_T_1 = 11'hf << io_in_d_bits_size; // @[package.scala 234:77]
  wire [3:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[3:0]; // @[package.scala 234:46]
  wire  d_first_beats1_decode = _d_first_beats1_decode_T_3[3]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala 220:14]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg  source_1; // @[Monitor.scala 538:22]
  reg [4:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_578 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_579 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_583 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_587 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_591 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_595 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_599 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [1:0] inflight; // @[Monitor.scala 611:27]
  reg [7:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [2:0] _GEN_64 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_64}; // @[Monitor.scala 634:69]
  wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_68 = {{8'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_68 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_73 = {{8'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_605 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_608 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_75 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_75}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_325 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_325 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [18:0] _GEN_326 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [18:0] _a_sizes_set_T_1 = _GEN_326 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [1:0] _T_610 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_612 = ~_T_610[0]; // @[Monitor.scala 658:17]
  wire [1:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [18:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_616 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_618 = ~_T_412; // @[Monitor.scala 671:74]
  wire  _T_619 = io_in_d_valid & d_first_1 & ~_T_412; // @[Monitor.scala 671:71]
  wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_412 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _GEN_327 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_opcodes_clr_T_5 = _GEN_327 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1:0] d_clr = _d_first_T & d_first_1 & _T_618 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_618 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_605 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [1:0] _T_629 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_631 = _T_629[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_636 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_32 | _T_636; // @[Monitor.scala 685:77]
  wire  _T_641 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_48 | _T_648; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_79 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_653 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_663 = _T_616 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_618; // @[Monitor.scala 694:116]
  wire  _T_664 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_665 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_672 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [7:0] a_opcodes_set = _GEN_19[7:0];
  wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [7:0] d_opcodes_clr = _GEN_23[7:0];
  wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [7:0] a_sizes_set = _GEN_20[7:0];
  wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_681 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [1:0] inflight_1; // @[Monitor.scala 723:35]
  reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_81 = {{8'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_81 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_701 = ~inflight_1[0]; // @[Monitor.scala 766:17]
  wire  _T_707 = io_in_d_valid & d_first_2 & _T_412; // @[Monitor.scala 779:71]
  wire [1:0] d_clr_wo_ready_1 = io_in_d_valid & d_first_2 & _T_412 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 779:89 780:22]
  wire [1:0] d_clr_1 = _d_first_T & d_first_2 & _T_412 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 783:90 784:21]
  wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_412 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire [1:0] _T_715 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_721 = io_in_d_bits_size == 3'h0; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_725 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_741 = 2'h0 != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [1:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
  wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= a_first_beats1;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 2'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 8'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= a_first_beats1;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 2'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= d_first_beats1;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_39) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_39 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_75) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_75 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_39) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_39 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h0 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_70) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_70 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_137) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_137 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_75) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_75 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_83 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_83 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_150 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_238 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_238 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_238 & ~reset & ~_T_185) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_185 & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_238 & ~reset & ~_T_277) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_277 & (io_in_a_valid & _T_238 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_281 & ~reset & ~_T_302) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_302 & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_281 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_281 & ~reset & ~_T_314) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_314 & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_281 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_281 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_322 & ~reset & ~_T_302) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_302 & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_322 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_322 & ~reset & ~_T_355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_355 & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_322 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_322 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_396) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_396 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_189) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_189 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_363 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_412 & _T_2 & ~_T_416) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_416 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_412 & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_412 & _T_2 & ~_T_424) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_424 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_412 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_412 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_416) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_416 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_443) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_443 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_447) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_447 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_424) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_424 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_432 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_432 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_416) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_416 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_443) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_443 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_447) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_447 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_480) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_480 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_460 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_460 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_489 & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_489 & _T_2 & ~_T_424) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_424 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_489 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_506 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_506 & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_506 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_506 & _T_2 & ~_T_480) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_480 & (io_in_d_valid & _T_506 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_506 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_506 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & (io_in_d_valid & _T_524 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_524 & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_524 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_524 & _T_2 & ~_T_424) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_424 & (io_in_d_valid & _T_524 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_524 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_524 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~1'h1 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_555) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_555 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_559) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_559 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_563) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_563 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_554 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_554 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_587 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_595 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_578 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_578 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~reset & ~_T_612) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_612 & (_T_608 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & _T_2 & ~_T_631) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_631 & (_T_619 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & same_cycle_resp & _T_2 & ~_T_637) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_637 & (_T_619 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & same_cycle_resp & _T_2 & ~_T_641) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_641 & (_T_619 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_619 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_619 & ~same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_619 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_663 & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_663 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_672) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_672 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_681) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_681 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701 & 1'h0) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_707 & _T_2 & ~_T_715[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_715[0] & (_T_707 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_721 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_707 & _T_2 & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (_T_707 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_664 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_741 & 1'h0) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Rift2Link.scala:78:32)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[4:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[7:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[1:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[7:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_2(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input         auto_in_a_bits_source,
  input  [31:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output        auto_in_d_bits_source,
  output [63:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output        auto_out_a_bits_source,
  output [31:0] auto_out_a_bits_address,
  output [7:0]  auto_out_a_bits_mask,
  output [63:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input         auto_out_d_bits_source,
  input  [4:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [63:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [4:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 377:21]
  wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 377:21]
  wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 377:21]
  wire [4:0] bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 377:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 377:21]
  wire [4:0] bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 377:21]
  wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 377:21]
  TLMonitor_14 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Queue_33 bundleOut_0_a_q ( // @[Decoupled.scala 377:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_34 bundleIn_0_d_q ( // @[Decoupled.scala 377:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 381:17]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module Rift2LinkA(
  input         clock,
  input         reset,
  input         io_rtc_clock,
  output        io_dm_hartIsInReset,
  input         io_dm_hartResetReq,
  input         io_dm_hartHaltReq,
  input         io_aclint_msi,
  input         io_aclint_mti,
  input         io_aclint_ssi,
  input         io_aclint_sti,
  input         io_plic_mei,
  input         io_plic_sei,
  output        io_hspi_clk,
  input         io_hspi_rx_enable,
  input  [15:0] io_hspi_rx_data,
  output        io_hspi_tx_enable,
  output [15:0] io_hspi_tx_data,
  output        io_hspi_oen
);
  wire  i_rift2Core_clock; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_reset; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_prefetch_clinet_out_a_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_prefetch_clinet_out_a_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_prefetch_clinet_out_a_bits_param; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_prefetch_clinet_out_a_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_prefetch_clinet_out_a_bits_source; // @[Rift2Link.scala 47:31]
  wire [31:0] i_rift2Core_auto_prefetch_clinet_out_a_bits_address; // @[Rift2Link.scala 47:31]
  wire [7:0] i_rift2Core_auto_prefetch_clinet_out_a_bits_mask; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_prefetch_clinet_out_a_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_prefetch_clinet_out_a_bits_corrupt; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_prefetch_clinet_out_d_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_mmu_client_out_a_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_mmu_client_out_a_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_mmu_client_out_a_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_mmu_client_out_a_bits_param; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_mmu_client_out_a_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_mmu_client_out_a_bits_source; // @[Rift2Link.scala 47:31]
  wire [31:0] i_rift2Core_auto_mmu_client_out_a_bits_address; // @[Rift2Link.scala 47:31]
  wire [7:0] i_rift2Core_auto_mmu_client_out_a_bits_mask; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_mmu_client_out_a_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_mmu_client_out_a_bits_corrupt; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_mmu_client_out_d_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_mmu_client_out_d_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_mmu_client_out_d_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_mmu_client_out_d_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_mmu_client_out_d_bits_source; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_mmu_client_out_d_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_periph_client_out_a_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_periph_client_out_a_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_periph_client_out_a_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_periph_client_out_a_bits_param; // @[Rift2Link.scala 47:31]
  wire [1:0] i_rift2Core_auto_periph_client_out_a_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_periph_client_out_a_bits_source; // @[Rift2Link.scala 47:31]
  wire [31:0] i_rift2Core_auto_periph_client_out_a_bits_address; // @[Rift2Link.scala 47:31]
  wire [7:0] i_rift2Core_auto_periph_client_out_a_bits_mask; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_periph_client_out_a_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_periph_client_out_a_bits_corrupt; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_periph_client_out_d_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_periph_client_out_d_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_periph_client_out_d_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_periph_client_out_d_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_system_client_out_a_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_system_client_out_a_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_system_client_out_a_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_system_client_out_a_bits_param; // @[Rift2Link.scala 47:31]
  wire [1:0] i_rift2Core_auto_system_client_out_a_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_system_client_out_a_bits_source; // @[Rift2Link.scala 47:31]
  wire [31:0] i_rift2Core_auto_system_client_out_a_bits_address; // @[Rift2Link.scala 47:31]
  wire [7:0] i_rift2Core_auto_system_client_out_a_bits_mask; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_system_client_out_a_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_system_client_out_a_bits_corrupt; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_system_client_out_d_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_system_client_out_d_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_system_client_out_d_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_system_client_out_d_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_a_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_a_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_dcache_client_out_a_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_dcache_client_out_a_bits_param; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_dcache_client_out_a_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_a_bits_source; // @[Rift2Link.scala 47:31]
  wire [31:0] i_rift2Core_auto_dcache_client_out_a_bits_address; // @[Rift2Link.scala 47:31]
  wire [7:0] i_rift2Core_auto_dcache_client_out_a_bits_mask; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_dcache_client_out_a_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_a_bits_corrupt; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_b_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_b_valid; // @[Rift2Link.scala 47:31]
  wire [31:0] i_rift2Core_auto_dcache_client_out_b_bits_address; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_c_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_c_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_dcache_client_out_c_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_dcache_client_out_c_bits_param; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_dcache_client_out_c_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_c_bits_source; // @[Rift2Link.scala 47:31]
  wire [31:0] i_rift2Core_auto_dcache_client_out_c_bits_address; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_dcache_client_out_c_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_c_bits_corrupt; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_d_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_d_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_dcache_client_out_d_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_dcache_client_out_d_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_d_bits_source; // @[Rift2Link.scala 47:31]
  wire [4:0] i_rift2Core_auto_dcache_client_out_d_bits_sink; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_dcache_client_out_d_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_e_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_dcache_client_out_e_valid; // @[Rift2Link.scala 47:31]
  wire [4:0] i_rift2Core_auto_dcache_client_out_e_bits_sink; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_icache_client_out_a_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_icache_client_out_a_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_icache_client_out_a_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_icache_client_out_a_bits_param; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_icache_client_out_a_bits_size; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_icache_client_out_a_bits_source; // @[Rift2Link.scala 47:31]
  wire [31:0] i_rift2Core_auto_icache_client_out_a_bits_address; // @[Rift2Link.scala 47:31]
  wire [7:0] i_rift2Core_auto_icache_client_out_a_bits_mask; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_icache_client_out_a_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_icache_client_out_a_bits_corrupt; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_icache_client_out_d_ready; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_auto_icache_client_out_d_valid; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_icache_client_out_d_bits_opcode; // @[Rift2Link.scala 47:31]
  wire [2:0] i_rift2Core_auto_icache_client_out_d_bits_size; // @[Rift2Link.scala 47:31]
  wire [63:0] i_rift2Core_auto_icache_client_out_d_bits_data; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_dm_hartIsInReset; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_dm_hartResetReq; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_dm_hartHaltReq; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_rtc_clock; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_aclint_msi; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_aclint_mti; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_aclint_ssi; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_aclint_sti; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_plic_mei; // @[Rift2Link.scala 47:31]
  wire  i_rift2Core_io_plic_sei; // @[Rift2Link.scala 47:31]
  wire  sifiveCache_clock; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_reset; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_a_ready; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_a_valid; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_a_bits_opcode; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_a_bits_param; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_a_bits_size; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_a_bits_source; // @[Rift2Link.scala 49:54]
  wire [31:0] sifiveCache_auto_in_a_bits_address; // @[Rift2Link.scala 49:54]
  wire [7:0] sifiveCache_auto_in_a_bits_mask; // @[Rift2Link.scala 49:54]
  wire [63:0] sifiveCache_auto_in_a_bits_data; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_a_bits_corrupt; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_b_ready; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_b_valid; // @[Rift2Link.scala 49:54]
  wire [1:0] sifiveCache_auto_in_b_bits_param; // @[Rift2Link.scala 49:54]
  wire [31:0] sifiveCache_auto_in_b_bits_address; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_c_ready; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_c_valid; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_c_bits_opcode; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_c_bits_param; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_c_bits_size; // @[Rift2Link.scala 49:54]
  wire [31:0] sifiveCache_auto_in_c_bits_address; // @[Rift2Link.scala 49:54]
  wire [63:0] sifiveCache_auto_in_c_bits_data; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_c_bits_corrupt; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_d_ready; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_d_valid; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_d_bits_opcode; // @[Rift2Link.scala 49:54]
  wire [1:0] sifiveCache_auto_in_d_bits_param; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_d_bits_size; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_in_d_bits_source; // @[Rift2Link.scala 49:54]
  wire [4:0] sifiveCache_auto_in_d_bits_sink; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_d_bits_denied; // @[Rift2Link.scala 49:54]
  wire [63:0] sifiveCache_auto_in_d_bits_data; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_d_bits_corrupt; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_in_e_valid; // @[Rift2Link.scala 49:54]
  wire [4:0] sifiveCache_auto_in_e_bits_sink; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_a_ready; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_a_valid; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_a_bits_opcode; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_a_bits_param; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_a_bits_size; // @[Rift2Link.scala 49:54]
  wire [4:0] sifiveCache_auto_out_a_bits_source; // @[Rift2Link.scala 49:54]
  wire [31:0] sifiveCache_auto_out_a_bits_address; // @[Rift2Link.scala 49:54]
  wire [7:0] sifiveCache_auto_out_a_bits_mask; // @[Rift2Link.scala 49:54]
  wire [63:0] sifiveCache_auto_out_a_bits_data; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_a_bits_corrupt; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_c_ready; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_c_valid; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_c_bits_opcode; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_c_bits_param; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_c_bits_size; // @[Rift2Link.scala 49:54]
  wire [4:0] sifiveCache_auto_out_c_bits_source; // @[Rift2Link.scala 49:54]
  wire [31:0] sifiveCache_auto_out_c_bits_address; // @[Rift2Link.scala 49:54]
  wire [63:0] sifiveCache_auto_out_c_bits_data; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_c_bits_corrupt; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_d_ready; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_d_valid; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_d_bits_opcode; // @[Rift2Link.scala 49:54]
  wire [1:0] sifiveCache_auto_out_d_bits_param; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_d_bits_size; // @[Rift2Link.scala 49:54]
  wire [4:0] sifiveCache_auto_out_d_bits_source; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_d_bits_sink; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_d_bits_denied; // @[Rift2Link.scala 49:54]
  wire [63:0] sifiveCache_auto_out_d_bits_data; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_d_bits_corrupt; // @[Rift2Link.scala 49:54]
  wire  sifiveCache_auto_out_e_valid; // @[Rift2Link.scala 49:54]
  wire [2:0] sifiveCache_auto_out_e_bits_sink; // @[Rift2Link.scala 49:54]
  wire  chipLinkMst_clock; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_reset; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_auto_chip_link_master_in_a_ready; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_auto_chip_link_master_in_a_valid; // @[Rift2Link.scala 57:31]
  wire [2:0] chipLinkMst_auto_chip_link_master_in_a_bits_opcode; // @[Rift2Link.scala 57:31]
  wire [2:0] chipLinkMst_auto_chip_link_master_in_a_bits_param; // @[Rift2Link.scala 57:31]
  wire [1:0] chipLinkMst_auto_chip_link_master_in_a_bits_size; // @[Rift2Link.scala 57:31]
  wire [9:0] chipLinkMst_auto_chip_link_master_in_a_bits_source; // @[Rift2Link.scala 57:31]
  wire [31:0] chipLinkMst_auto_chip_link_master_in_a_bits_address; // @[Rift2Link.scala 57:31]
  wire [7:0] chipLinkMst_auto_chip_link_master_in_a_bits_mask; // @[Rift2Link.scala 57:31]
  wire [63:0] chipLinkMst_auto_chip_link_master_in_a_bits_data; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_auto_chip_link_master_in_a_bits_corrupt; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_auto_chip_link_master_in_d_ready; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_auto_chip_link_master_in_d_valid; // @[Rift2Link.scala 57:31]
  wire [2:0] chipLinkMst_auto_chip_link_master_in_d_bits_opcode; // @[Rift2Link.scala 57:31]
  wire [1:0] chipLinkMst_auto_chip_link_master_in_d_bits_size; // @[Rift2Link.scala 57:31]
  wire [9:0] chipLinkMst_auto_chip_link_master_in_d_bits_source; // @[Rift2Link.scala 57:31]
  wire [63:0] chipLinkMst_auto_chip_link_master_in_d_bits_data; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_io_hspi_clk; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_io_hspi_rx_enable; // @[Rift2Link.scala 57:31]
  wire [15:0] chipLinkMst_io_hspi_rx_data; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_io_hspi_tx_enable; // @[Rift2Link.scala 57:31]
  wire [15:0] chipLinkMst_io_hspi_tx_data; // @[Rift2Link.scala 57:31]
  wire  chipLinkMst_io_hspi_oen; // @[Rift2Link.scala 57:31]
  wire  xbar_clock; // @[Xbar.scala 142:26]
  wire  xbar_reset; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_3_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_3_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_3_a_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_3_a_bits_size; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_3_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_in_3_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_auto_in_3_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_in_3_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_3_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_3_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_a_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_2_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_2_a_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_2_a_bits_size; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_in_2_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_auto_in_2_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_in_2_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_d_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_2_d_bits_opcode; // @[Xbar.scala 142:26]
  wire [1:0] xbar_auto_in_2_d_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_2_d_bits_size; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_d_bits_source; // @[Xbar.scala 142:26]
  wire [4:0] xbar_auto_in_2_d_bits_sink; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_d_bits_denied; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_in_2_d_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_2_d_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_a_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_1_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_1_a_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_1_a_bits_size; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_in_1_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_auto_in_1_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_in_1_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_b_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_b_valid; // @[Xbar.scala 142:26]
  wire [1:0] xbar_auto_in_1_b_bits_param; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_in_1_b_bits_address; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_c_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_c_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_1_c_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_1_c_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_1_c_bits_size; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_c_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_in_1_c_bits_address; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_in_1_c_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_c_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_d_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_1_d_bits_opcode; // @[Xbar.scala 142:26]
  wire [1:0] xbar_auto_in_1_d_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_1_d_bits_size; // @[Xbar.scala 142:26]
  wire [4:0] xbar_auto_in_1_d_bits_sink; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_d_bits_denied; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_in_1_d_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_d_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_1_e_valid; // @[Xbar.scala 142:26]
  wire [4:0] xbar_auto_in_1_e_bits_sink; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_0_a_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_0_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_0_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_0_a_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_0_a_bits_size; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_0_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_in_0_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_auto_in_0_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_in_0_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_0_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_0_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_0_d_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_0_d_bits_opcode; // @[Xbar.scala 142:26]
  wire [1:0] xbar_auto_in_0_d_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_in_0_d_bits_size; // @[Xbar.scala 142:26]
  wire [4:0] xbar_auto_in_0_d_bits_sink; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_0_d_bits_denied; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_in_0_d_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_in_0_d_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_a_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_a_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_a_bits_size; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_out_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_auto_out_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_out_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_b_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_b_valid; // @[Xbar.scala 142:26]
  wire [1:0] xbar_auto_out_b_bits_param; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_out_b_bits_address; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_c_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_c_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_c_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_c_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_c_bits_size; // @[Xbar.scala 142:26]
  wire [31:0] xbar_auto_out_c_bits_address; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_out_c_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_c_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_d_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_d_bits_opcode; // @[Xbar.scala 142:26]
  wire [1:0] xbar_auto_out_d_bits_param; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_d_bits_size; // @[Xbar.scala 142:26]
  wire [2:0] xbar_auto_out_d_bits_source; // @[Xbar.scala 142:26]
  wire [4:0] xbar_auto_out_d_bits_sink; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_d_bits_denied; // @[Xbar.scala 142:26]
  wire [63:0] xbar_auto_out_d_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_d_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_auto_out_e_valid; // @[Xbar.scala 142:26]
  wire [4:0] xbar_auto_out_e_bits_sink; // @[Xbar.scala 142:26]
  wire  xbar_1_clock; // @[Xbar.scala 142:26]
  wire  xbar_1_reset; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_2_a_ready; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_2_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_2_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_2_a_bits_param; // @[Xbar.scala 142:26]
  wire [1:0] xbar_1_auto_in_2_a_bits_size; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_2_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_1_auto_in_2_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_1_auto_in_2_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_1_auto_in_2_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_2_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_2_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_2_d_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_2_d_bits_opcode; // @[Xbar.scala 142:26]
  wire [63:0] xbar_1_auto_in_2_d_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_1_a_ready; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_1_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_1_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_1_a_bits_param; // @[Xbar.scala 142:26]
  wire [1:0] xbar_1_auto_in_1_a_bits_size; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_1_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_1_auto_in_1_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_1_auto_in_1_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_1_auto_in_1_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_1_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_1_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_1_d_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_1_d_bits_opcode; // @[Xbar.scala 142:26]
  wire [63:0] xbar_1_auto_in_1_d_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_0_a_ready; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_0_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_0_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_0_a_bits_param; // @[Xbar.scala 142:26]
  wire [1:0] xbar_1_auto_in_0_a_bits_size; // @[Xbar.scala 142:26]
  wire [8:0] xbar_1_auto_in_0_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_1_auto_in_0_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_1_auto_in_0_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_1_auto_in_0_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_0_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_0_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_in_0_d_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_in_0_d_bits_opcode; // @[Xbar.scala 142:26]
  wire [1:0] xbar_1_auto_in_0_d_bits_size; // @[Xbar.scala 142:26]
  wire [8:0] xbar_1_auto_in_0_d_bits_source; // @[Xbar.scala 142:26]
  wire [63:0] xbar_1_auto_in_0_d_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_out_a_ready; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_out_a_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_out_a_bits_opcode; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_out_a_bits_param; // @[Xbar.scala 142:26]
  wire [1:0] xbar_1_auto_out_a_bits_size; // @[Xbar.scala 142:26]
  wire [9:0] xbar_1_auto_out_a_bits_source; // @[Xbar.scala 142:26]
  wire [31:0] xbar_1_auto_out_a_bits_address; // @[Xbar.scala 142:26]
  wire [7:0] xbar_1_auto_out_a_bits_mask; // @[Xbar.scala 142:26]
  wire [63:0] xbar_1_auto_out_a_bits_data; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_out_a_bits_corrupt; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_out_d_ready; // @[Xbar.scala 142:26]
  wire  xbar_1_auto_out_d_valid; // @[Xbar.scala 142:26]
  wire [2:0] xbar_1_auto_out_d_bits_opcode; // @[Xbar.scala 142:26]
  wire [1:0] xbar_1_auto_out_d_bits_size; // @[Xbar.scala 142:26]
  wire [9:0] xbar_1_auto_out_d_bits_source; // @[Xbar.scala 142:26]
  wire [63:0] xbar_1_auto_out_d_bits_data; // @[Xbar.scala 142:26]
  wire  fixer_clock; // @[FIFOFixer.scala 144:27]
  wire  fixer_reset; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_a_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_a_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_a_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_a_bits_param; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_a_bits_size; // @[FIFOFixer.scala 144:27]
  wire [8:0] fixer_auto_in_a_bits_source; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_in_a_bits_address; // @[FIFOFixer.scala 144:27]
  wire [7:0] fixer_auto_in_a_bits_mask; // @[FIFOFixer.scala 144:27]
  wire [63:0] fixer_auto_in_a_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_a_bits_corrupt; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_d_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_d_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_d_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_d_bits_size; // @[FIFOFixer.scala 144:27]
  wire [8:0] fixer_auto_in_d_bits_source; // @[FIFOFixer.scala 144:27]
  wire [63:0] fixer_auto_in_d_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_a_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_a_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_a_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_a_bits_param; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_a_bits_size; // @[FIFOFixer.scala 144:27]
  wire [8:0] fixer_auto_out_a_bits_source; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_out_a_bits_address; // @[FIFOFixer.scala 144:27]
  wire [7:0] fixer_auto_out_a_bits_mask; // @[FIFOFixer.scala 144:27]
  wire [63:0] fixer_auto_out_a_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_a_bits_corrupt; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_d_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_d_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_d_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_d_bits_size; // @[FIFOFixer.scala 144:27]
  wire [8:0] fixer_auto_out_d_bits_source; // @[FIFOFixer.scala 144:27]
  wire [63:0] fixer_auto_out_d_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [5:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [5:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [8:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [8:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [5:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [5:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [5:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [5:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  cork_clock; // @[CacheCork.scala 177:26]
  wire  cork_reset; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_a_ready; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_a_valid; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_a_bits_opcode; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_a_bits_param; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_a_bits_size; // @[CacheCork.scala 177:26]
  wire [4:0] cork_auto_in_a_bits_source; // @[CacheCork.scala 177:26]
  wire [31:0] cork_auto_in_a_bits_address; // @[CacheCork.scala 177:26]
  wire [7:0] cork_auto_in_a_bits_mask; // @[CacheCork.scala 177:26]
  wire [63:0] cork_auto_in_a_bits_data; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_a_bits_corrupt; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_c_ready; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_c_valid; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_c_bits_opcode; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_c_bits_param; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_c_bits_size; // @[CacheCork.scala 177:26]
  wire [4:0] cork_auto_in_c_bits_source; // @[CacheCork.scala 177:26]
  wire [31:0] cork_auto_in_c_bits_address; // @[CacheCork.scala 177:26]
  wire [63:0] cork_auto_in_c_bits_data; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_c_bits_corrupt; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_d_ready; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_d_valid; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_d_bits_opcode; // @[CacheCork.scala 177:26]
  wire [1:0] cork_auto_in_d_bits_param; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_d_bits_size; // @[CacheCork.scala 177:26]
  wire [4:0] cork_auto_in_d_bits_source; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_d_bits_sink; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_d_bits_denied; // @[CacheCork.scala 177:26]
  wire [63:0] cork_auto_in_d_bits_data; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_d_bits_corrupt; // @[CacheCork.scala 177:26]
  wire  cork_auto_in_e_valid; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_in_e_bits_sink; // @[CacheCork.scala 177:26]
  wire  cork_auto_out_a_ready; // @[CacheCork.scala 177:26]
  wire  cork_auto_out_a_valid; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_out_a_bits_opcode; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_out_a_bits_param; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_out_a_bits_size; // @[CacheCork.scala 177:26]
  wire [5:0] cork_auto_out_a_bits_source; // @[CacheCork.scala 177:26]
  wire [31:0] cork_auto_out_a_bits_address; // @[CacheCork.scala 177:26]
  wire [7:0] cork_auto_out_a_bits_mask; // @[CacheCork.scala 177:26]
  wire [63:0] cork_auto_out_a_bits_data; // @[CacheCork.scala 177:26]
  wire  cork_auto_out_a_bits_corrupt; // @[CacheCork.scala 177:26]
  wire  cork_auto_out_d_ready; // @[CacheCork.scala 177:26]
  wire  cork_auto_out_d_valid; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_out_d_bits_opcode; // @[CacheCork.scala 177:26]
  wire [2:0] cork_auto_out_d_bits_size; // @[CacheCork.scala 177:26]
  wire [5:0] cork_auto_out_d_bits_source; // @[CacheCork.scala 177:26]
  wire [63:0] cork_auto_out_d_bits_data; // @[CacheCork.scala 177:26]
  wire  buffer_clock; // @[Buffer.scala 68:28]
  wire  buffer_reset; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [4:0] buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
  wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_clock; // @[Buffer.scala 68:28]
  wire  buffer_1_reset; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_b_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_b_valid; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_b_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_c_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_c_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_c_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_c_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_c_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_c_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_c_bits_address; // @[Buffer.scala 68:28]
  wire [63:0] buffer_1_auto_in_c_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_c_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [4:0] buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_e_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_e_valid; // @[Buffer.scala 68:28]
  wire [4:0] buffer_1_auto_in_e_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_b_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_b_valid; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_b_bits_param; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_b_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_c_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_c_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_c_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_c_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_c_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_c_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_c_bits_address; // @[Buffer.scala 68:28]
  wire [63:0] buffer_1_auto_out_c_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_c_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [4:0] buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
  wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_e_valid; // @[Buffer.scala 68:28]
  wire [4:0] buffer_1_auto_out_e_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_2_clock; // @[Buffer.scala 68:28]
  wire  buffer_2_reset; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_2_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [7:0] buffer_2_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [63:0] buffer_2_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [63:0] buffer_2_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_2_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [7:0] buffer_2_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [63:0] buffer_2_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_2_auto_out_d_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [4:0] buffer_2_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
  wire [63:0] buffer_2_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  Rift2Core i_rift2Core ( // @[Rift2Link.scala 47:31]
    .clock(i_rift2Core_clock),
    .reset(i_rift2Core_reset),
    .auto_prefetch_clinet_out_a_valid(i_rift2Core_auto_prefetch_clinet_out_a_valid),
    .auto_prefetch_clinet_out_a_bits_opcode(i_rift2Core_auto_prefetch_clinet_out_a_bits_opcode),
    .auto_prefetch_clinet_out_a_bits_param(i_rift2Core_auto_prefetch_clinet_out_a_bits_param),
    .auto_prefetch_clinet_out_a_bits_size(i_rift2Core_auto_prefetch_clinet_out_a_bits_size),
    .auto_prefetch_clinet_out_a_bits_source(i_rift2Core_auto_prefetch_clinet_out_a_bits_source),
    .auto_prefetch_clinet_out_a_bits_address(i_rift2Core_auto_prefetch_clinet_out_a_bits_address),
    .auto_prefetch_clinet_out_a_bits_mask(i_rift2Core_auto_prefetch_clinet_out_a_bits_mask),
    .auto_prefetch_clinet_out_a_bits_data(i_rift2Core_auto_prefetch_clinet_out_a_bits_data),
    .auto_prefetch_clinet_out_a_bits_corrupt(i_rift2Core_auto_prefetch_clinet_out_a_bits_corrupt),
    .auto_prefetch_clinet_out_d_ready(i_rift2Core_auto_prefetch_clinet_out_d_ready),
    .auto_mmu_client_out_a_ready(i_rift2Core_auto_mmu_client_out_a_ready),
    .auto_mmu_client_out_a_valid(i_rift2Core_auto_mmu_client_out_a_valid),
    .auto_mmu_client_out_a_bits_opcode(i_rift2Core_auto_mmu_client_out_a_bits_opcode),
    .auto_mmu_client_out_a_bits_param(i_rift2Core_auto_mmu_client_out_a_bits_param),
    .auto_mmu_client_out_a_bits_size(i_rift2Core_auto_mmu_client_out_a_bits_size),
    .auto_mmu_client_out_a_bits_source(i_rift2Core_auto_mmu_client_out_a_bits_source),
    .auto_mmu_client_out_a_bits_address(i_rift2Core_auto_mmu_client_out_a_bits_address),
    .auto_mmu_client_out_a_bits_mask(i_rift2Core_auto_mmu_client_out_a_bits_mask),
    .auto_mmu_client_out_a_bits_data(i_rift2Core_auto_mmu_client_out_a_bits_data),
    .auto_mmu_client_out_a_bits_corrupt(i_rift2Core_auto_mmu_client_out_a_bits_corrupt),
    .auto_mmu_client_out_d_ready(i_rift2Core_auto_mmu_client_out_d_ready),
    .auto_mmu_client_out_d_valid(i_rift2Core_auto_mmu_client_out_d_valid),
    .auto_mmu_client_out_d_bits_opcode(i_rift2Core_auto_mmu_client_out_d_bits_opcode),
    .auto_mmu_client_out_d_bits_size(i_rift2Core_auto_mmu_client_out_d_bits_size),
    .auto_mmu_client_out_d_bits_source(i_rift2Core_auto_mmu_client_out_d_bits_source),
    .auto_mmu_client_out_d_bits_data(i_rift2Core_auto_mmu_client_out_d_bits_data),
    .auto_periph_client_out_a_ready(i_rift2Core_auto_periph_client_out_a_ready),
    .auto_periph_client_out_a_valid(i_rift2Core_auto_periph_client_out_a_valid),
    .auto_periph_client_out_a_bits_opcode(i_rift2Core_auto_periph_client_out_a_bits_opcode),
    .auto_periph_client_out_a_bits_param(i_rift2Core_auto_periph_client_out_a_bits_param),
    .auto_periph_client_out_a_bits_size(i_rift2Core_auto_periph_client_out_a_bits_size),
    .auto_periph_client_out_a_bits_source(i_rift2Core_auto_periph_client_out_a_bits_source),
    .auto_periph_client_out_a_bits_address(i_rift2Core_auto_periph_client_out_a_bits_address),
    .auto_periph_client_out_a_bits_mask(i_rift2Core_auto_periph_client_out_a_bits_mask),
    .auto_periph_client_out_a_bits_data(i_rift2Core_auto_periph_client_out_a_bits_data),
    .auto_periph_client_out_a_bits_corrupt(i_rift2Core_auto_periph_client_out_a_bits_corrupt),
    .auto_periph_client_out_d_ready(i_rift2Core_auto_periph_client_out_d_ready),
    .auto_periph_client_out_d_valid(i_rift2Core_auto_periph_client_out_d_valid),
    .auto_periph_client_out_d_bits_opcode(i_rift2Core_auto_periph_client_out_d_bits_opcode),
    .auto_periph_client_out_d_bits_data(i_rift2Core_auto_periph_client_out_d_bits_data),
    .auto_system_client_out_a_ready(i_rift2Core_auto_system_client_out_a_ready),
    .auto_system_client_out_a_valid(i_rift2Core_auto_system_client_out_a_valid),
    .auto_system_client_out_a_bits_opcode(i_rift2Core_auto_system_client_out_a_bits_opcode),
    .auto_system_client_out_a_bits_param(i_rift2Core_auto_system_client_out_a_bits_param),
    .auto_system_client_out_a_bits_size(i_rift2Core_auto_system_client_out_a_bits_size),
    .auto_system_client_out_a_bits_source(i_rift2Core_auto_system_client_out_a_bits_source),
    .auto_system_client_out_a_bits_address(i_rift2Core_auto_system_client_out_a_bits_address),
    .auto_system_client_out_a_bits_mask(i_rift2Core_auto_system_client_out_a_bits_mask),
    .auto_system_client_out_a_bits_data(i_rift2Core_auto_system_client_out_a_bits_data),
    .auto_system_client_out_a_bits_corrupt(i_rift2Core_auto_system_client_out_a_bits_corrupt),
    .auto_system_client_out_d_ready(i_rift2Core_auto_system_client_out_d_ready),
    .auto_system_client_out_d_valid(i_rift2Core_auto_system_client_out_d_valid),
    .auto_system_client_out_d_bits_opcode(i_rift2Core_auto_system_client_out_d_bits_opcode),
    .auto_system_client_out_d_bits_data(i_rift2Core_auto_system_client_out_d_bits_data),
    .auto_dcache_client_out_a_ready(i_rift2Core_auto_dcache_client_out_a_ready),
    .auto_dcache_client_out_a_valid(i_rift2Core_auto_dcache_client_out_a_valid),
    .auto_dcache_client_out_a_bits_opcode(i_rift2Core_auto_dcache_client_out_a_bits_opcode),
    .auto_dcache_client_out_a_bits_param(i_rift2Core_auto_dcache_client_out_a_bits_param),
    .auto_dcache_client_out_a_bits_size(i_rift2Core_auto_dcache_client_out_a_bits_size),
    .auto_dcache_client_out_a_bits_source(i_rift2Core_auto_dcache_client_out_a_bits_source),
    .auto_dcache_client_out_a_bits_address(i_rift2Core_auto_dcache_client_out_a_bits_address),
    .auto_dcache_client_out_a_bits_mask(i_rift2Core_auto_dcache_client_out_a_bits_mask),
    .auto_dcache_client_out_a_bits_data(i_rift2Core_auto_dcache_client_out_a_bits_data),
    .auto_dcache_client_out_a_bits_corrupt(i_rift2Core_auto_dcache_client_out_a_bits_corrupt),
    .auto_dcache_client_out_b_ready(i_rift2Core_auto_dcache_client_out_b_ready),
    .auto_dcache_client_out_b_valid(i_rift2Core_auto_dcache_client_out_b_valid),
    .auto_dcache_client_out_b_bits_address(i_rift2Core_auto_dcache_client_out_b_bits_address),
    .auto_dcache_client_out_c_ready(i_rift2Core_auto_dcache_client_out_c_ready),
    .auto_dcache_client_out_c_valid(i_rift2Core_auto_dcache_client_out_c_valid),
    .auto_dcache_client_out_c_bits_opcode(i_rift2Core_auto_dcache_client_out_c_bits_opcode),
    .auto_dcache_client_out_c_bits_param(i_rift2Core_auto_dcache_client_out_c_bits_param),
    .auto_dcache_client_out_c_bits_size(i_rift2Core_auto_dcache_client_out_c_bits_size),
    .auto_dcache_client_out_c_bits_source(i_rift2Core_auto_dcache_client_out_c_bits_source),
    .auto_dcache_client_out_c_bits_address(i_rift2Core_auto_dcache_client_out_c_bits_address),
    .auto_dcache_client_out_c_bits_data(i_rift2Core_auto_dcache_client_out_c_bits_data),
    .auto_dcache_client_out_c_bits_corrupt(i_rift2Core_auto_dcache_client_out_c_bits_corrupt),
    .auto_dcache_client_out_d_ready(i_rift2Core_auto_dcache_client_out_d_ready),
    .auto_dcache_client_out_d_valid(i_rift2Core_auto_dcache_client_out_d_valid),
    .auto_dcache_client_out_d_bits_opcode(i_rift2Core_auto_dcache_client_out_d_bits_opcode),
    .auto_dcache_client_out_d_bits_size(i_rift2Core_auto_dcache_client_out_d_bits_size),
    .auto_dcache_client_out_d_bits_source(i_rift2Core_auto_dcache_client_out_d_bits_source),
    .auto_dcache_client_out_d_bits_sink(i_rift2Core_auto_dcache_client_out_d_bits_sink),
    .auto_dcache_client_out_d_bits_data(i_rift2Core_auto_dcache_client_out_d_bits_data),
    .auto_dcache_client_out_e_ready(i_rift2Core_auto_dcache_client_out_e_ready),
    .auto_dcache_client_out_e_valid(i_rift2Core_auto_dcache_client_out_e_valid),
    .auto_dcache_client_out_e_bits_sink(i_rift2Core_auto_dcache_client_out_e_bits_sink),
    .auto_icache_client_out_a_ready(i_rift2Core_auto_icache_client_out_a_ready),
    .auto_icache_client_out_a_valid(i_rift2Core_auto_icache_client_out_a_valid),
    .auto_icache_client_out_a_bits_opcode(i_rift2Core_auto_icache_client_out_a_bits_opcode),
    .auto_icache_client_out_a_bits_param(i_rift2Core_auto_icache_client_out_a_bits_param),
    .auto_icache_client_out_a_bits_size(i_rift2Core_auto_icache_client_out_a_bits_size),
    .auto_icache_client_out_a_bits_source(i_rift2Core_auto_icache_client_out_a_bits_source),
    .auto_icache_client_out_a_bits_address(i_rift2Core_auto_icache_client_out_a_bits_address),
    .auto_icache_client_out_a_bits_mask(i_rift2Core_auto_icache_client_out_a_bits_mask),
    .auto_icache_client_out_a_bits_data(i_rift2Core_auto_icache_client_out_a_bits_data),
    .auto_icache_client_out_a_bits_corrupt(i_rift2Core_auto_icache_client_out_a_bits_corrupt),
    .auto_icache_client_out_d_ready(i_rift2Core_auto_icache_client_out_d_ready),
    .auto_icache_client_out_d_valid(i_rift2Core_auto_icache_client_out_d_valid),
    .auto_icache_client_out_d_bits_opcode(i_rift2Core_auto_icache_client_out_d_bits_opcode),
    .auto_icache_client_out_d_bits_size(i_rift2Core_auto_icache_client_out_d_bits_size),
    .auto_icache_client_out_d_bits_data(i_rift2Core_auto_icache_client_out_d_bits_data),
    .io_dm_hartIsInReset(i_rift2Core_io_dm_hartIsInReset),
    .io_dm_hartResetReq(i_rift2Core_io_dm_hartResetReq),
    .io_dm_hartHaltReq(i_rift2Core_io_dm_hartHaltReq),
    .io_rtc_clock(i_rift2Core_io_rtc_clock),
    .io_aclint_msi(i_rift2Core_io_aclint_msi),
    .io_aclint_mti(i_rift2Core_io_aclint_mti),
    .io_aclint_ssi(i_rift2Core_io_aclint_ssi),
    .io_aclint_sti(i_rift2Core_io_aclint_sti),
    .io_plic_mei(i_rift2Core_io_plic_mei),
    .io_plic_sei(i_rift2Core_io_plic_sei)
  );
  InclusiveCache sifiveCache ( // @[Rift2Link.scala 49:54]
    .clock(sifiveCache_clock),
    .reset(sifiveCache_reset),
    .auto_in_a_ready(sifiveCache_auto_in_a_ready),
    .auto_in_a_valid(sifiveCache_auto_in_a_valid),
    .auto_in_a_bits_opcode(sifiveCache_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(sifiveCache_auto_in_a_bits_param),
    .auto_in_a_bits_size(sifiveCache_auto_in_a_bits_size),
    .auto_in_a_bits_source(sifiveCache_auto_in_a_bits_source),
    .auto_in_a_bits_address(sifiveCache_auto_in_a_bits_address),
    .auto_in_a_bits_mask(sifiveCache_auto_in_a_bits_mask),
    .auto_in_a_bits_data(sifiveCache_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(sifiveCache_auto_in_a_bits_corrupt),
    .auto_in_b_ready(sifiveCache_auto_in_b_ready),
    .auto_in_b_valid(sifiveCache_auto_in_b_valid),
    .auto_in_b_bits_param(sifiveCache_auto_in_b_bits_param),
    .auto_in_b_bits_address(sifiveCache_auto_in_b_bits_address),
    .auto_in_c_ready(sifiveCache_auto_in_c_ready),
    .auto_in_c_valid(sifiveCache_auto_in_c_valid),
    .auto_in_c_bits_opcode(sifiveCache_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(sifiveCache_auto_in_c_bits_param),
    .auto_in_c_bits_size(sifiveCache_auto_in_c_bits_size),
    .auto_in_c_bits_address(sifiveCache_auto_in_c_bits_address),
    .auto_in_c_bits_data(sifiveCache_auto_in_c_bits_data),
    .auto_in_c_bits_corrupt(sifiveCache_auto_in_c_bits_corrupt),
    .auto_in_d_ready(sifiveCache_auto_in_d_ready),
    .auto_in_d_valid(sifiveCache_auto_in_d_valid),
    .auto_in_d_bits_opcode(sifiveCache_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(sifiveCache_auto_in_d_bits_param),
    .auto_in_d_bits_size(sifiveCache_auto_in_d_bits_size),
    .auto_in_d_bits_source(sifiveCache_auto_in_d_bits_source),
    .auto_in_d_bits_sink(sifiveCache_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(sifiveCache_auto_in_d_bits_denied),
    .auto_in_d_bits_data(sifiveCache_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(sifiveCache_auto_in_d_bits_corrupt),
    .auto_in_e_valid(sifiveCache_auto_in_e_valid),
    .auto_in_e_bits_sink(sifiveCache_auto_in_e_bits_sink),
    .auto_out_a_ready(sifiveCache_auto_out_a_ready),
    .auto_out_a_valid(sifiveCache_auto_out_a_valid),
    .auto_out_a_bits_opcode(sifiveCache_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(sifiveCache_auto_out_a_bits_param),
    .auto_out_a_bits_size(sifiveCache_auto_out_a_bits_size),
    .auto_out_a_bits_source(sifiveCache_auto_out_a_bits_source),
    .auto_out_a_bits_address(sifiveCache_auto_out_a_bits_address),
    .auto_out_a_bits_mask(sifiveCache_auto_out_a_bits_mask),
    .auto_out_a_bits_data(sifiveCache_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(sifiveCache_auto_out_a_bits_corrupt),
    .auto_out_c_ready(sifiveCache_auto_out_c_ready),
    .auto_out_c_valid(sifiveCache_auto_out_c_valid),
    .auto_out_c_bits_opcode(sifiveCache_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(sifiveCache_auto_out_c_bits_param),
    .auto_out_c_bits_size(sifiveCache_auto_out_c_bits_size),
    .auto_out_c_bits_source(sifiveCache_auto_out_c_bits_source),
    .auto_out_c_bits_address(sifiveCache_auto_out_c_bits_address),
    .auto_out_c_bits_data(sifiveCache_auto_out_c_bits_data),
    .auto_out_c_bits_corrupt(sifiveCache_auto_out_c_bits_corrupt),
    .auto_out_d_ready(sifiveCache_auto_out_d_ready),
    .auto_out_d_valid(sifiveCache_auto_out_d_valid),
    .auto_out_d_bits_opcode(sifiveCache_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(sifiveCache_auto_out_d_bits_param),
    .auto_out_d_bits_size(sifiveCache_auto_out_d_bits_size),
    .auto_out_d_bits_source(sifiveCache_auto_out_d_bits_source),
    .auto_out_d_bits_sink(sifiveCache_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(sifiveCache_auto_out_d_bits_denied),
    .auto_out_d_bits_data(sifiveCache_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(sifiveCache_auto_out_d_bits_corrupt),
    .auto_out_e_valid(sifiveCache_auto_out_e_valid),
    .auto_out_e_bits_sink(sifiveCache_auto_out_e_bits_sink)
  );
  ChipLinkMaster chipLinkMst ( // @[Rift2Link.scala 57:31]
    .clock(chipLinkMst_clock),
    .reset(chipLinkMst_reset),
    .auto_chip_link_master_in_a_ready(chipLinkMst_auto_chip_link_master_in_a_ready),
    .auto_chip_link_master_in_a_valid(chipLinkMst_auto_chip_link_master_in_a_valid),
    .auto_chip_link_master_in_a_bits_opcode(chipLinkMst_auto_chip_link_master_in_a_bits_opcode),
    .auto_chip_link_master_in_a_bits_param(chipLinkMst_auto_chip_link_master_in_a_bits_param),
    .auto_chip_link_master_in_a_bits_size(chipLinkMst_auto_chip_link_master_in_a_bits_size),
    .auto_chip_link_master_in_a_bits_source(chipLinkMst_auto_chip_link_master_in_a_bits_source),
    .auto_chip_link_master_in_a_bits_address(chipLinkMst_auto_chip_link_master_in_a_bits_address),
    .auto_chip_link_master_in_a_bits_mask(chipLinkMst_auto_chip_link_master_in_a_bits_mask),
    .auto_chip_link_master_in_a_bits_data(chipLinkMst_auto_chip_link_master_in_a_bits_data),
    .auto_chip_link_master_in_a_bits_corrupt(chipLinkMst_auto_chip_link_master_in_a_bits_corrupt),
    .auto_chip_link_master_in_d_ready(chipLinkMst_auto_chip_link_master_in_d_ready),
    .auto_chip_link_master_in_d_valid(chipLinkMst_auto_chip_link_master_in_d_valid),
    .auto_chip_link_master_in_d_bits_opcode(chipLinkMst_auto_chip_link_master_in_d_bits_opcode),
    .auto_chip_link_master_in_d_bits_size(chipLinkMst_auto_chip_link_master_in_d_bits_size),
    .auto_chip_link_master_in_d_bits_source(chipLinkMst_auto_chip_link_master_in_d_bits_source),
    .auto_chip_link_master_in_d_bits_data(chipLinkMst_auto_chip_link_master_in_d_bits_data),
    .io_hspi_clk(chipLinkMst_io_hspi_clk),
    .io_hspi_rx_enable(chipLinkMst_io_hspi_rx_enable),
    .io_hspi_rx_data(chipLinkMst_io_hspi_rx_data),
    .io_hspi_tx_enable(chipLinkMst_io_hspi_tx_enable),
    .io_hspi_tx_data(chipLinkMst_io_hspi_tx_data),
    .io_hspi_oen(chipLinkMst_io_hspi_oen)
  );
  TLXbar xbar ( // @[Xbar.scala 142:26]
    .clock(xbar_clock),
    .reset(xbar_reset),
    .auto_in_3_a_valid(xbar_auto_in_3_a_valid),
    .auto_in_3_a_bits_opcode(xbar_auto_in_3_a_bits_opcode),
    .auto_in_3_a_bits_param(xbar_auto_in_3_a_bits_param),
    .auto_in_3_a_bits_size(xbar_auto_in_3_a_bits_size),
    .auto_in_3_a_bits_source(xbar_auto_in_3_a_bits_source),
    .auto_in_3_a_bits_address(xbar_auto_in_3_a_bits_address),
    .auto_in_3_a_bits_mask(xbar_auto_in_3_a_bits_mask),
    .auto_in_3_a_bits_data(xbar_auto_in_3_a_bits_data),
    .auto_in_3_a_bits_corrupt(xbar_auto_in_3_a_bits_corrupt),
    .auto_in_3_d_ready(xbar_auto_in_3_d_ready),
    .auto_in_2_a_ready(xbar_auto_in_2_a_ready),
    .auto_in_2_a_valid(xbar_auto_in_2_a_valid),
    .auto_in_2_a_bits_opcode(xbar_auto_in_2_a_bits_opcode),
    .auto_in_2_a_bits_param(xbar_auto_in_2_a_bits_param),
    .auto_in_2_a_bits_size(xbar_auto_in_2_a_bits_size),
    .auto_in_2_a_bits_source(xbar_auto_in_2_a_bits_source),
    .auto_in_2_a_bits_address(xbar_auto_in_2_a_bits_address),
    .auto_in_2_a_bits_mask(xbar_auto_in_2_a_bits_mask),
    .auto_in_2_a_bits_data(xbar_auto_in_2_a_bits_data),
    .auto_in_2_a_bits_corrupt(xbar_auto_in_2_a_bits_corrupt),
    .auto_in_2_d_ready(xbar_auto_in_2_d_ready),
    .auto_in_2_d_valid(xbar_auto_in_2_d_valid),
    .auto_in_2_d_bits_opcode(xbar_auto_in_2_d_bits_opcode),
    .auto_in_2_d_bits_param(xbar_auto_in_2_d_bits_param),
    .auto_in_2_d_bits_size(xbar_auto_in_2_d_bits_size),
    .auto_in_2_d_bits_source(xbar_auto_in_2_d_bits_source),
    .auto_in_2_d_bits_sink(xbar_auto_in_2_d_bits_sink),
    .auto_in_2_d_bits_denied(xbar_auto_in_2_d_bits_denied),
    .auto_in_2_d_bits_data(xbar_auto_in_2_d_bits_data),
    .auto_in_2_d_bits_corrupt(xbar_auto_in_2_d_bits_corrupt),
    .auto_in_1_a_ready(xbar_auto_in_1_a_ready),
    .auto_in_1_a_valid(xbar_auto_in_1_a_valid),
    .auto_in_1_a_bits_opcode(xbar_auto_in_1_a_bits_opcode),
    .auto_in_1_a_bits_param(xbar_auto_in_1_a_bits_param),
    .auto_in_1_a_bits_size(xbar_auto_in_1_a_bits_size),
    .auto_in_1_a_bits_source(xbar_auto_in_1_a_bits_source),
    .auto_in_1_a_bits_address(xbar_auto_in_1_a_bits_address),
    .auto_in_1_a_bits_mask(xbar_auto_in_1_a_bits_mask),
    .auto_in_1_a_bits_data(xbar_auto_in_1_a_bits_data),
    .auto_in_1_a_bits_corrupt(xbar_auto_in_1_a_bits_corrupt),
    .auto_in_1_b_ready(xbar_auto_in_1_b_ready),
    .auto_in_1_b_valid(xbar_auto_in_1_b_valid),
    .auto_in_1_b_bits_param(xbar_auto_in_1_b_bits_param),
    .auto_in_1_b_bits_address(xbar_auto_in_1_b_bits_address),
    .auto_in_1_c_ready(xbar_auto_in_1_c_ready),
    .auto_in_1_c_valid(xbar_auto_in_1_c_valid),
    .auto_in_1_c_bits_opcode(xbar_auto_in_1_c_bits_opcode),
    .auto_in_1_c_bits_param(xbar_auto_in_1_c_bits_param),
    .auto_in_1_c_bits_size(xbar_auto_in_1_c_bits_size),
    .auto_in_1_c_bits_source(xbar_auto_in_1_c_bits_source),
    .auto_in_1_c_bits_address(xbar_auto_in_1_c_bits_address),
    .auto_in_1_c_bits_data(xbar_auto_in_1_c_bits_data),
    .auto_in_1_c_bits_corrupt(xbar_auto_in_1_c_bits_corrupt),
    .auto_in_1_d_ready(xbar_auto_in_1_d_ready),
    .auto_in_1_d_valid(xbar_auto_in_1_d_valid),
    .auto_in_1_d_bits_opcode(xbar_auto_in_1_d_bits_opcode),
    .auto_in_1_d_bits_param(xbar_auto_in_1_d_bits_param),
    .auto_in_1_d_bits_size(xbar_auto_in_1_d_bits_size),
    .auto_in_1_d_bits_sink(xbar_auto_in_1_d_bits_sink),
    .auto_in_1_d_bits_denied(xbar_auto_in_1_d_bits_denied),
    .auto_in_1_d_bits_data(xbar_auto_in_1_d_bits_data),
    .auto_in_1_d_bits_corrupt(xbar_auto_in_1_d_bits_corrupt),
    .auto_in_1_e_valid(xbar_auto_in_1_e_valid),
    .auto_in_1_e_bits_sink(xbar_auto_in_1_e_bits_sink),
    .auto_in_0_a_ready(xbar_auto_in_0_a_ready),
    .auto_in_0_a_valid(xbar_auto_in_0_a_valid),
    .auto_in_0_a_bits_opcode(xbar_auto_in_0_a_bits_opcode),
    .auto_in_0_a_bits_param(xbar_auto_in_0_a_bits_param),
    .auto_in_0_a_bits_size(xbar_auto_in_0_a_bits_size),
    .auto_in_0_a_bits_source(xbar_auto_in_0_a_bits_source),
    .auto_in_0_a_bits_address(xbar_auto_in_0_a_bits_address),
    .auto_in_0_a_bits_mask(xbar_auto_in_0_a_bits_mask),
    .auto_in_0_a_bits_data(xbar_auto_in_0_a_bits_data),
    .auto_in_0_a_bits_corrupt(xbar_auto_in_0_a_bits_corrupt),
    .auto_in_0_d_ready(xbar_auto_in_0_d_ready),
    .auto_in_0_d_valid(xbar_auto_in_0_d_valid),
    .auto_in_0_d_bits_opcode(xbar_auto_in_0_d_bits_opcode),
    .auto_in_0_d_bits_param(xbar_auto_in_0_d_bits_param),
    .auto_in_0_d_bits_size(xbar_auto_in_0_d_bits_size),
    .auto_in_0_d_bits_sink(xbar_auto_in_0_d_bits_sink),
    .auto_in_0_d_bits_denied(xbar_auto_in_0_d_bits_denied),
    .auto_in_0_d_bits_data(xbar_auto_in_0_d_bits_data),
    .auto_in_0_d_bits_corrupt(xbar_auto_in_0_d_bits_corrupt),
    .auto_out_a_ready(xbar_auto_out_a_ready),
    .auto_out_a_valid(xbar_auto_out_a_valid),
    .auto_out_a_bits_opcode(xbar_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(xbar_auto_out_a_bits_param),
    .auto_out_a_bits_size(xbar_auto_out_a_bits_size),
    .auto_out_a_bits_source(xbar_auto_out_a_bits_source),
    .auto_out_a_bits_address(xbar_auto_out_a_bits_address),
    .auto_out_a_bits_mask(xbar_auto_out_a_bits_mask),
    .auto_out_a_bits_data(xbar_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(xbar_auto_out_a_bits_corrupt),
    .auto_out_b_ready(xbar_auto_out_b_ready),
    .auto_out_b_valid(xbar_auto_out_b_valid),
    .auto_out_b_bits_param(xbar_auto_out_b_bits_param),
    .auto_out_b_bits_address(xbar_auto_out_b_bits_address),
    .auto_out_c_ready(xbar_auto_out_c_ready),
    .auto_out_c_valid(xbar_auto_out_c_valid),
    .auto_out_c_bits_opcode(xbar_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(xbar_auto_out_c_bits_param),
    .auto_out_c_bits_size(xbar_auto_out_c_bits_size),
    .auto_out_c_bits_address(xbar_auto_out_c_bits_address),
    .auto_out_c_bits_data(xbar_auto_out_c_bits_data),
    .auto_out_c_bits_corrupt(xbar_auto_out_c_bits_corrupt),
    .auto_out_d_ready(xbar_auto_out_d_ready),
    .auto_out_d_valid(xbar_auto_out_d_valid),
    .auto_out_d_bits_opcode(xbar_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(xbar_auto_out_d_bits_param),
    .auto_out_d_bits_size(xbar_auto_out_d_bits_size),
    .auto_out_d_bits_source(xbar_auto_out_d_bits_source),
    .auto_out_d_bits_sink(xbar_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(xbar_auto_out_d_bits_denied),
    .auto_out_d_bits_data(xbar_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(xbar_auto_out_d_bits_corrupt),
    .auto_out_e_valid(xbar_auto_out_e_valid),
    .auto_out_e_bits_sink(xbar_auto_out_e_bits_sink)
  );
  TLXbar_1 xbar_1 ( // @[Xbar.scala 142:26]
    .clock(xbar_1_clock),
    .reset(xbar_1_reset),
    .auto_in_2_a_ready(xbar_1_auto_in_2_a_ready),
    .auto_in_2_a_valid(xbar_1_auto_in_2_a_valid),
    .auto_in_2_a_bits_opcode(xbar_1_auto_in_2_a_bits_opcode),
    .auto_in_2_a_bits_param(xbar_1_auto_in_2_a_bits_param),
    .auto_in_2_a_bits_size(xbar_1_auto_in_2_a_bits_size),
    .auto_in_2_a_bits_source(xbar_1_auto_in_2_a_bits_source),
    .auto_in_2_a_bits_address(xbar_1_auto_in_2_a_bits_address),
    .auto_in_2_a_bits_mask(xbar_1_auto_in_2_a_bits_mask),
    .auto_in_2_a_bits_data(xbar_1_auto_in_2_a_bits_data),
    .auto_in_2_a_bits_corrupt(xbar_1_auto_in_2_a_bits_corrupt),
    .auto_in_2_d_ready(xbar_1_auto_in_2_d_ready),
    .auto_in_2_d_valid(xbar_1_auto_in_2_d_valid),
    .auto_in_2_d_bits_opcode(xbar_1_auto_in_2_d_bits_opcode),
    .auto_in_2_d_bits_data(xbar_1_auto_in_2_d_bits_data),
    .auto_in_1_a_ready(xbar_1_auto_in_1_a_ready),
    .auto_in_1_a_valid(xbar_1_auto_in_1_a_valid),
    .auto_in_1_a_bits_opcode(xbar_1_auto_in_1_a_bits_opcode),
    .auto_in_1_a_bits_param(xbar_1_auto_in_1_a_bits_param),
    .auto_in_1_a_bits_size(xbar_1_auto_in_1_a_bits_size),
    .auto_in_1_a_bits_source(xbar_1_auto_in_1_a_bits_source),
    .auto_in_1_a_bits_address(xbar_1_auto_in_1_a_bits_address),
    .auto_in_1_a_bits_mask(xbar_1_auto_in_1_a_bits_mask),
    .auto_in_1_a_bits_data(xbar_1_auto_in_1_a_bits_data),
    .auto_in_1_a_bits_corrupt(xbar_1_auto_in_1_a_bits_corrupt),
    .auto_in_1_d_ready(xbar_1_auto_in_1_d_ready),
    .auto_in_1_d_valid(xbar_1_auto_in_1_d_valid),
    .auto_in_1_d_bits_opcode(xbar_1_auto_in_1_d_bits_opcode),
    .auto_in_1_d_bits_data(xbar_1_auto_in_1_d_bits_data),
    .auto_in_0_a_ready(xbar_1_auto_in_0_a_ready),
    .auto_in_0_a_valid(xbar_1_auto_in_0_a_valid),
    .auto_in_0_a_bits_opcode(xbar_1_auto_in_0_a_bits_opcode),
    .auto_in_0_a_bits_param(xbar_1_auto_in_0_a_bits_param),
    .auto_in_0_a_bits_size(xbar_1_auto_in_0_a_bits_size),
    .auto_in_0_a_bits_source(xbar_1_auto_in_0_a_bits_source),
    .auto_in_0_a_bits_address(xbar_1_auto_in_0_a_bits_address),
    .auto_in_0_a_bits_mask(xbar_1_auto_in_0_a_bits_mask),
    .auto_in_0_a_bits_data(xbar_1_auto_in_0_a_bits_data),
    .auto_in_0_a_bits_corrupt(xbar_1_auto_in_0_a_bits_corrupt),
    .auto_in_0_d_ready(xbar_1_auto_in_0_d_ready),
    .auto_in_0_d_valid(xbar_1_auto_in_0_d_valid),
    .auto_in_0_d_bits_opcode(xbar_1_auto_in_0_d_bits_opcode),
    .auto_in_0_d_bits_size(xbar_1_auto_in_0_d_bits_size),
    .auto_in_0_d_bits_source(xbar_1_auto_in_0_d_bits_source),
    .auto_in_0_d_bits_data(xbar_1_auto_in_0_d_bits_data),
    .auto_out_a_ready(xbar_1_auto_out_a_ready),
    .auto_out_a_valid(xbar_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(xbar_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(xbar_1_auto_out_a_bits_param),
    .auto_out_a_bits_size(xbar_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(xbar_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(xbar_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(xbar_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(xbar_1_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(xbar_1_auto_out_a_bits_corrupt),
    .auto_out_d_ready(xbar_1_auto_out_d_ready),
    .auto_out_d_valid(xbar_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(xbar_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(xbar_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(xbar_1_auto_out_d_bits_source),
    .auto_out_d_bits_data(xbar_1_auto_out_d_bits_data)
  );
  TLFIFOFixer fixer ( // @[FIFOFixer.scala 144:27]
    .clock(fixer_clock),
    .reset(fixer_reset),
    .auto_in_a_ready(fixer_auto_in_a_ready),
    .auto_in_a_valid(fixer_auto_in_a_valid),
    .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fixer_auto_in_a_bits_param),
    .auto_in_a_bits_size(fixer_auto_in_a_bits_size),
    .auto_in_a_bits_source(fixer_auto_in_a_bits_source),
    .auto_in_a_bits_address(fixer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fixer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fixer_auto_in_d_ready),
    .auto_in_d_valid(fixer_auto_in_d_valid),
    .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fixer_auto_in_d_bits_size),
    .auto_in_d_bits_source(fixer_auto_in_d_bits_source),
    .auto_in_d_bits_data(fixer_auto_in_d_bits_data),
    .auto_out_a_ready(fixer_auto_out_a_ready),
    .auto_out_a_valid(fixer_auto_out_a_valid),
    .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fixer_auto_out_a_bits_param),
    .auto_out_a_bits_size(fixer_auto_out_a_bits_size),
    .auto_out_a_bits_source(fixer_auto_out_a_bits_source),
    .auto_out_a_bits_address(fixer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fixer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fixer_auto_out_d_ready),
    .auto_out_d_valid(fixer_auto_out_d_valid),
    .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fixer_auto_out_d_bits_size),
    .auto_out_d_bits_source(fixer_auto_out_d_bits_source),
    .auto_out_d_bits_data(fixer_auto_out_d_bits_data)
  );
  TLFragmenter fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  TLWidthWidget widget ( // @[WidthWidget.scala 219:28]
    .auto_in_a_ready(widget_auto_in_a_ready),
    .auto_in_a_valid(widget_auto_in_a_valid),
    .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(widget_auto_in_a_bits_param),
    .auto_in_a_bits_size(widget_auto_in_a_bits_size),
    .auto_in_a_bits_source(widget_auto_in_a_bits_source),
    .auto_in_a_bits_address(widget_auto_in_a_bits_address),
    .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
    .auto_in_a_bits_data(widget_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
    .auto_in_d_ready(widget_auto_in_d_ready),
    .auto_in_d_valid(widget_auto_in_d_valid),
    .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(widget_auto_in_d_bits_size),
    .auto_in_d_bits_source(widget_auto_in_d_bits_source),
    .auto_in_d_bits_data(widget_auto_in_d_bits_data),
    .auto_out_a_ready(widget_auto_out_a_ready),
    .auto_out_a_valid(widget_auto_out_a_valid),
    .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(widget_auto_out_a_bits_param),
    .auto_out_a_bits_size(widget_auto_out_a_bits_size),
    .auto_out_a_bits_source(widget_auto_out_a_bits_source),
    .auto_out_a_bits_address(widget_auto_out_a_bits_address),
    .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
    .auto_out_a_bits_data(widget_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
    .auto_out_d_ready(widget_auto_out_d_ready),
    .auto_out_d_valid(widget_auto_out_d_valid),
    .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(widget_auto_out_d_bits_size),
    .auto_out_d_bits_source(widget_auto_out_d_bits_source),
    .auto_out_d_bits_data(widget_auto_out_d_bits_data)
  );
  TLCacheCork cork ( // @[CacheCork.scala 177:26]
    .clock(cork_clock),
    .reset(cork_reset),
    .auto_in_a_ready(cork_auto_in_a_ready),
    .auto_in_a_valid(cork_auto_in_a_valid),
    .auto_in_a_bits_opcode(cork_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(cork_auto_in_a_bits_param),
    .auto_in_a_bits_size(cork_auto_in_a_bits_size),
    .auto_in_a_bits_source(cork_auto_in_a_bits_source),
    .auto_in_a_bits_address(cork_auto_in_a_bits_address),
    .auto_in_a_bits_mask(cork_auto_in_a_bits_mask),
    .auto_in_a_bits_data(cork_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(cork_auto_in_a_bits_corrupt),
    .auto_in_c_ready(cork_auto_in_c_ready),
    .auto_in_c_valid(cork_auto_in_c_valid),
    .auto_in_c_bits_opcode(cork_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(cork_auto_in_c_bits_param),
    .auto_in_c_bits_size(cork_auto_in_c_bits_size),
    .auto_in_c_bits_source(cork_auto_in_c_bits_source),
    .auto_in_c_bits_address(cork_auto_in_c_bits_address),
    .auto_in_c_bits_data(cork_auto_in_c_bits_data),
    .auto_in_c_bits_corrupt(cork_auto_in_c_bits_corrupt),
    .auto_in_d_ready(cork_auto_in_d_ready),
    .auto_in_d_valid(cork_auto_in_d_valid),
    .auto_in_d_bits_opcode(cork_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(cork_auto_in_d_bits_param),
    .auto_in_d_bits_size(cork_auto_in_d_bits_size),
    .auto_in_d_bits_source(cork_auto_in_d_bits_source),
    .auto_in_d_bits_sink(cork_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(cork_auto_in_d_bits_denied),
    .auto_in_d_bits_data(cork_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(cork_auto_in_d_bits_corrupt),
    .auto_in_e_valid(cork_auto_in_e_valid),
    .auto_in_e_bits_sink(cork_auto_in_e_bits_sink),
    .auto_out_a_ready(cork_auto_out_a_ready),
    .auto_out_a_valid(cork_auto_out_a_valid),
    .auto_out_a_bits_opcode(cork_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(cork_auto_out_a_bits_param),
    .auto_out_a_bits_size(cork_auto_out_a_bits_size),
    .auto_out_a_bits_source(cork_auto_out_a_bits_source),
    .auto_out_a_bits_address(cork_auto_out_a_bits_address),
    .auto_out_a_bits_mask(cork_auto_out_a_bits_mask),
    .auto_out_a_bits_data(cork_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(cork_auto_out_a_bits_corrupt),
    .auto_out_d_ready(cork_auto_out_d_ready),
    .auto_out_d_valid(cork_auto_out_d_valid),
    .auto_out_d_bits_opcode(cork_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(cork_auto_out_d_bits_size),
    .auto_out_d_bits_source(cork_auto_out_d_bits_source),
    .auto_out_d_bits_data(cork_auto_out_d_bits_data)
  );
  TLBuffer buffer ( // @[Buffer.scala 68:28]
    .clock(buffer_clock),
    .reset(buffer_reset),
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
  );
  TLBuffer_1 buffer_1 ( // @[Buffer.scala 68:28]
    .clock(buffer_1_clock),
    .reset(buffer_1_reset),
    .auto_in_a_ready(buffer_1_auto_in_a_ready),
    .auto_in_a_valid(buffer_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
    .auto_in_b_ready(buffer_1_auto_in_b_ready),
    .auto_in_b_valid(buffer_1_auto_in_b_valid),
    .auto_in_b_bits_address(buffer_1_auto_in_b_bits_address),
    .auto_in_c_ready(buffer_1_auto_in_c_ready),
    .auto_in_c_valid(buffer_1_auto_in_c_valid),
    .auto_in_c_bits_opcode(buffer_1_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(buffer_1_auto_in_c_bits_param),
    .auto_in_c_bits_size(buffer_1_auto_in_c_bits_size),
    .auto_in_c_bits_source(buffer_1_auto_in_c_bits_source),
    .auto_in_c_bits_address(buffer_1_auto_in_c_bits_address),
    .auto_in_c_bits_data(buffer_1_auto_in_c_bits_data),
    .auto_in_c_bits_corrupt(buffer_1_auto_in_c_bits_corrupt),
    .auto_in_d_ready(buffer_1_auto_in_d_ready),
    .auto_in_d_valid(buffer_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
    .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
    .auto_in_e_ready(buffer_1_auto_in_e_ready),
    .auto_in_e_valid(buffer_1_auto_in_e_valid),
    .auto_in_e_bits_sink(buffer_1_auto_in_e_bits_sink),
    .auto_out_a_ready(buffer_1_auto_out_a_ready),
    .auto_out_a_valid(buffer_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
    .auto_out_b_ready(buffer_1_auto_out_b_ready),
    .auto_out_b_valid(buffer_1_auto_out_b_valid),
    .auto_out_b_bits_param(buffer_1_auto_out_b_bits_param),
    .auto_out_b_bits_address(buffer_1_auto_out_b_bits_address),
    .auto_out_c_ready(buffer_1_auto_out_c_ready),
    .auto_out_c_valid(buffer_1_auto_out_c_valid),
    .auto_out_c_bits_opcode(buffer_1_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(buffer_1_auto_out_c_bits_param),
    .auto_out_c_bits_size(buffer_1_auto_out_c_bits_size),
    .auto_out_c_bits_source(buffer_1_auto_out_c_bits_source),
    .auto_out_c_bits_address(buffer_1_auto_out_c_bits_address),
    .auto_out_c_bits_data(buffer_1_auto_out_c_bits_data),
    .auto_out_c_bits_corrupt(buffer_1_auto_out_c_bits_corrupt),
    .auto_out_d_ready(buffer_1_auto_out_d_ready),
    .auto_out_d_valid(buffer_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
    .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
    .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
    .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt),
    .auto_out_e_valid(buffer_1_auto_out_e_valid),
    .auto_out_e_bits_sink(buffer_1_auto_out_e_bits_sink)
  );
  TLBuffer_2 buffer_2 ( // @[Buffer.scala 68:28]
    .clock(buffer_2_clock),
    .reset(buffer_2_reset),
    .auto_in_a_ready(buffer_2_auto_in_a_ready),
    .auto_in_a_valid(buffer_2_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_2_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_2_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_2_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_2_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_2_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_2_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_2_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_2_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_2_auto_in_d_ready),
    .auto_in_d_valid(buffer_2_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_2_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_2_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_2_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_2_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_2_auto_out_a_ready),
    .auto_out_a_valid(buffer_2_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_2_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_2_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_2_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_2_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_2_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_2_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_2_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_2_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_2_auto_out_d_ready),
    .auto_out_d_valid(buffer_2_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_2_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(buffer_2_auto_out_d_bits_param),
    .auto_out_d_bits_size(buffer_2_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_2_auto_out_d_bits_source),
    .auto_out_d_bits_sink(buffer_2_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(buffer_2_auto_out_d_bits_denied),
    .auto_out_d_bits_data(buffer_2_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(buffer_2_auto_out_d_bits_corrupt)
  );
  assign io_dm_hartIsInReset = i_rift2Core_io_dm_hartIsInReset; // @[Rift2Link.scala 110:17]
  assign io_hspi_clk = chipLinkMst_io_hspi_clk; // @[Rift2Link.scala 118:17]
  assign io_hspi_tx_enable = chipLinkMst_io_hspi_tx_enable; // @[Rift2Link.scala 116:16]
  assign io_hspi_tx_data = chipLinkMst_io_hspi_tx_data; // @[Rift2Link.scala 116:16]
  assign io_hspi_oen = chipLinkMst_io_hspi_oen; // @[Rift2Link.scala 120:17]
  assign i_rift2Core_clock = clock;
  assign i_rift2Core_reset = reset;
  assign i_rift2Core_auto_mmu_client_out_a_ready = buffer_2_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_mmu_client_out_d_valid = buffer_2_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_mmu_client_out_d_bits_opcode = buffer_2_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_mmu_client_out_d_bits_size = buffer_2_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_mmu_client_out_d_bits_source = buffer_2_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_mmu_client_out_d_bits_data = buffer_2_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_periph_client_out_a_ready = xbar_1_auto_in_2_a_ready; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_periph_client_out_d_valid = xbar_1_auto_in_2_d_valid; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_periph_client_out_d_bits_opcode = xbar_1_auto_in_2_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_periph_client_out_d_bits_data = xbar_1_auto_in_2_d_bits_data; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_system_client_out_a_ready = xbar_1_auto_in_1_a_ready; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_system_client_out_d_valid = xbar_1_auto_in_1_d_valid; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_system_client_out_d_bits_opcode = xbar_1_auto_in_1_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_system_client_out_d_bits_data = xbar_1_auto_in_1_d_bits_data; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_a_ready = buffer_1_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_b_valid = buffer_1_auto_in_b_valid; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_b_bits_address = buffer_1_auto_in_b_bits_address; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_c_ready = buffer_1_auto_in_c_ready; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_d_valid = buffer_1_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_d_bits_size = buffer_1_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_d_bits_source = buffer_1_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_d_bits_data = buffer_1_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_dcache_client_out_e_ready = buffer_1_auto_in_e_ready; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_icache_client_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_icache_client_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_icache_client_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_icache_client_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign i_rift2Core_auto_icache_client_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign i_rift2Core_io_dm_hartResetReq = io_dm_hartResetReq; // @[Rift2Link.scala 110:17]
  assign i_rift2Core_io_dm_hartHaltReq = io_dm_hartHaltReq; // @[Rift2Link.scala 110:17]
  assign i_rift2Core_io_rtc_clock = io_rtc_clock; // @[Rift2Link.scala 122:37]
  assign i_rift2Core_io_aclint_msi = io_aclint_msi; // @[Rift2Link.scala 112:34]
  assign i_rift2Core_io_aclint_mti = io_aclint_mti; // @[Rift2Link.scala 112:34]
  assign i_rift2Core_io_aclint_ssi = io_aclint_ssi; // @[Rift2Link.scala 112:34]
  assign i_rift2Core_io_aclint_sti = io_aclint_sti; // @[Rift2Link.scala 112:34]
  assign i_rift2Core_io_plic_mei = io_plic_mei; // @[Rift2Link.scala 113:32]
  assign i_rift2Core_io_plic_sei = io_plic_sei; // @[Rift2Link.scala 113:32]
  assign sifiveCache_clock = clock;
  assign sifiveCache_reset = reset;
  assign sifiveCache_auto_in_a_valid = xbar_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_a_bits_opcode = xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_a_bits_param = xbar_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_a_bits_size = xbar_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_a_bits_source = xbar_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_a_bits_address = xbar_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_a_bits_mask = xbar_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_a_bits_data = xbar_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_a_bits_corrupt = xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_b_ready = xbar_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_c_valid = xbar_auto_out_c_valid; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_c_bits_opcode = xbar_auto_out_c_bits_opcode; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_c_bits_param = xbar_auto_out_c_bits_param; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_c_bits_size = xbar_auto_out_c_bits_size; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_c_bits_address = xbar_auto_out_c_bits_address; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_c_bits_data = xbar_auto_out_c_bits_data; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_c_bits_corrupt = xbar_auto_out_c_bits_corrupt; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_d_ready = xbar_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_e_valid = xbar_auto_out_e_valid; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_in_e_bits_sink = xbar_auto_out_e_bits_sink; // @[LazyModule.scala 296:16]
  assign sifiveCache_auto_out_a_ready = cork_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_c_ready = cork_auto_in_c_ready; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_valid = cork_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_bits_opcode = cork_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_bits_param = cork_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_bits_size = cork_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_bits_source = cork_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_bits_sink = cork_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_bits_denied = cork_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_bits_data = cork_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign sifiveCache_auto_out_d_bits_corrupt = cork_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign chipLinkMst_clock = clock;
  assign chipLinkMst_reset = reset;
  assign chipLinkMst_auto_chip_link_master_in_a_valid = xbar_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_a_bits_opcode = xbar_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_a_bits_param = xbar_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_a_bits_size = xbar_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_a_bits_source = xbar_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_a_bits_address = xbar_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_a_bits_mask = xbar_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_a_bits_data = xbar_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_a_bits_corrupt = xbar_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign chipLinkMst_auto_chip_link_master_in_d_ready = xbar_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign chipLinkMst_io_hspi_rx_enable = io_hspi_rx_enable; // @[Rift2Link.scala 117:35]
  assign chipLinkMst_io_hspi_rx_data = io_hspi_rx_data; // @[Rift2Link.scala 117:35]
  assign xbar_clock = clock;
  assign xbar_reset = reset;
  assign xbar_auto_in_3_a_valid = i_rift2Core_auto_prefetch_clinet_out_a_valid; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_a_bits_opcode = i_rift2Core_auto_prefetch_clinet_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_a_bits_param = i_rift2Core_auto_prefetch_clinet_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_a_bits_size = i_rift2Core_auto_prefetch_clinet_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_a_bits_source = i_rift2Core_auto_prefetch_clinet_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_a_bits_address = i_rift2Core_auto_prefetch_clinet_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_a_bits_mask = i_rift2Core_auto_prefetch_clinet_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_a_bits_data = i_rift2Core_auto_prefetch_clinet_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_a_bits_corrupt = i_rift2Core_auto_prefetch_clinet_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_3_d_ready = i_rift2Core_auto_prefetch_clinet_out_d_ready; // @[LazyModule.scala 298:16]
  assign xbar_auto_in_2_a_valid = buffer_2_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_a_bits_opcode = buffer_2_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_a_bits_param = buffer_2_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_a_bits_size = buffer_2_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_a_bits_source = buffer_2_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_a_bits_address = buffer_2_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_a_bits_mask = buffer_2_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_a_bits_data = buffer_2_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_a_bits_corrupt = buffer_2_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_2_d_ready = buffer_2_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_b_ready = buffer_1_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_c_valid = buffer_1_auto_out_c_valid; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_c_bits_opcode = buffer_1_auto_out_c_bits_opcode; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_c_bits_param = buffer_1_auto_out_c_bits_param; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_c_bits_size = buffer_1_auto_out_c_bits_size; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_c_bits_source = buffer_1_auto_out_c_bits_source; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_c_bits_address = buffer_1_auto_out_c_bits_address; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_c_bits_data = buffer_1_auto_out_c_bits_data; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_c_bits_corrupt = buffer_1_auto_out_c_bits_corrupt; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_e_valid = buffer_1_auto_out_e_valid; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_1_e_bits_sink = buffer_1_auto_out_e_bits_sink; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign xbar_auto_in_0_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_a_ready = sifiveCache_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_b_valid = sifiveCache_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_b_bits_param = sifiveCache_auto_in_b_bits_param; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_b_bits_address = sifiveCache_auto_in_b_bits_address; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_c_ready = sifiveCache_auto_in_c_ready; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_valid = sifiveCache_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_bits_opcode = sifiveCache_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_bits_param = sifiveCache_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_bits_size = sifiveCache_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_bits_source = sifiveCache_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_bits_sink = sifiveCache_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_bits_denied = sifiveCache_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_bits_data = sifiveCache_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign xbar_auto_out_d_bits_corrupt = sifiveCache_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign xbar_1_clock = clock;
  assign xbar_1_reset = reset;
  assign xbar_1_auto_in_2_a_valid = i_rift2Core_auto_periph_client_out_a_valid; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_a_bits_opcode = i_rift2Core_auto_periph_client_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_a_bits_param = i_rift2Core_auto_periph_client_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_a_bits_size = i_rift2Core_auto_periph_client_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_a_bits_source = i_rift2Core_auto_periph_client_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_a_bits_address = i_rift2Core_auto_periph_client_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_a_bits_mask = i_rift2Core_auto_periph_client_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_a_bits_data = i_rift2Core_auto_periph_client_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_a_bits_corrupt = i_rift2Core_auto_periph_client_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_2_d_ready = i_rift2Core_auto_periph_client_out_d_ready; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_valid = i_rift2Core_auto_system_client_out_a_valid; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_bits_opcode = i_rift2Core_auto_system_client_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_bits_param = i_rift2Core_auto_system_client_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_bits_size = i_rift2Core_auto_system_client_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_bits_source = i_rift2Core_auto_system_client_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_bits_address = i_rift2Core_auto_system_client_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_bits_mask = i_rift2Core_auto_system_client_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_bits_data = i_rift2Core_auto_system_client_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_a_bits_corrupt = i_rift2Core_auto_system_client_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_1_d_ready = i_rift2Core_auto_system_client_out_d_ready; // @[LazyModule.scala 298:16]
  assign xbar_1_auto_in_0_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_in_0_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_out_a_ready = chipLinkMst_auto_chip_link_master_in_a_ready; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_out_d_valid = chipLinkMst_auto_chip_link_master_in_d_valid; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_out_d_bits_opcode = chipLinkMst_auto_chip_link_master_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_out_d_bits_size = chipLinkMst_auto_chip_link_master_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_out_d_bits_source = chipLinkMst_auto_chip_link_master_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign xbar_1_auto_out_d_bits_data = chipLinkMst_auto_chip_link_master_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign fixer_clock = clock;
  assign fixer_reset = reset;
  assign fixer_auto_in_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_a_ready = xbar_1_auto_in_0_a_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_valid = xbar_1_auto_in_0_d_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_opcode = xbar_1_auto_in_0_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_size = xbar_1_auto_in_0_d_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_source = xbar_1_auto_in_0_d_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_data = xbar_1_auto_in_0_d_bits_data; // @[LazyModule.scala 296:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_valid = cork_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_bits_opcode = cork_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_bits_param = cork_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_bits_size = cork_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_bits_source = cork_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_bits_address = cork_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_bits_mask = cork_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_bits_data = cork_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign widget_auto_in_a_bits_corrupt = cork_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign widget_auto_in_d_ready = cork_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign widget_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign cork_clock = clock;
  assign cork_reset = reset;
  assign cork_auto_in_a_valid = sifiveCache_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign cork_auto_in_a_bits_opcode = sifiveCache_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign cork_auto_in_a_bits_param = sifiveCache_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign cork_auto_in_a_bits_size = sifiveCache_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign cork_auto_in_a_bits_source = sifiveCache_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign cork_auto_in_a_bits_address = sifiveCache_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign cork_auto_in_a_bits_mask = sifiveCache_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign cork_auto_in_a_bits_data = sifiveCache_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign cork_auto_in_a_bits_corrupt = sifiveCache_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign cork_auto_in_c_valid = sifiveCache_auto_out_c_valid; // @[LazyModule.scala 298:16]
  assign cork_auto_in_c_bits_opcode = sifiveCache_auto_out_c_bits_opcode; // @[LazyModule.scala 298:16]
  assign cork_auto_in_c_bits_param = sifiveCache_auto_out_c_bits_param; // @[LazyModule.scala 298:16]
  assign cork_auto_in_c_bits_size = sifiveCache_auto_out_c_bits_size; // @[LazyModule.scala 298:16]
  assign cork_auto_in_c_bits_source = sifiveCache_auto_out_c_bits_source; // @[LazyModule.scala 298:16]
  assign cork_auto_in_c_bits_address = sifiveCache_auto_out_c_bits_address; // @[LazyModule.scala 298:16]
  assign cork_auto_in_c_bits_data = sifiveCache_auto_out_c_bits_data; // @[LazyModule.scala 298:16]
  assign cork_auto_in_c_bits_corrupt = sifiveCache_auto_out_c_bits_corrupt; // @[LazyModule.scala 298:16]
  assign cork_auto_in_d_ready = sifiveCache_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign cork_auto_in_e_valid = sifiveCache_auto_out_e_valid; // @[LazyModule.scala 298:16]
  assign cork_auto_in_e_bits_sink = sifiveCache_auto_out_e_bits_sink; // @[LazyModule.scala 298:16]
  assign cork_auto_out_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign cork_auto_out_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign cork_auto_out_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign cork_auto_out_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign cork_auto_out_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign cork_auto_out_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_clock = clock;
  assign buffer_reset = reset;
  assign buffer_auto_in_a_valid = i_rift2Core_auto_icache_client_out_a_valid; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_opcode = i_rift2Core_auto_icache_client_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_param = i_rift2Core_auto_icache_client_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_size = i_rift2Core_auto_icache_client_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_source = i_rift2Core_auto_icache_client_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_address = i_rift2Core_auto_icache_client_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_mask = i_rift2Core_auto_icache_client_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_data = i_rift2Core_auto_icache_client_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_corrupt = i_rift2Core_auto_icache_client_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_d_ready = i_rift2Core_auto_icache_client_out_d_ready; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_a_ready = xbar_auto_in_0_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = xbar_auto_in_0_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = xbar_auto_in_0_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_param = xbar_auto_in_0_d_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_size = xbar_auto_in_0_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_sink = xbar_auto_in_0_d_bits_sink; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_denied = xbar_auto_in_0_d_bits_denied; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = xbar_auto_in_0_d_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_corrupt = xbar_auto_in_0_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign buffer_1_clock = clock;
  assign buffer_1_reset = reset;
  assign buffer_1_auto_in_a_valid = i_rift2Core_auto_dcache_client_out_a_valid; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_opcode = i_rift2Core_auto_dcache_client_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_param = i_rift2Core_auto_dcache_client_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_size = i_rift2Core_auto_dcache_client_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_source = i_rift2Core_auto_dcache_client_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_address = i_rift2Core_auto_dcache_client_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_mask = i_rift2Core_auto_dcache_client_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_data = i_rift2Core_auto_dcache_client_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_corrupt = i_rift2Core_auto_dcache_client_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_b_ready = i_rift2Core_auto_dcache_client_out_b_ready; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_valid = i_rift2Core_auto_dcache_client_out_c_valid; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_opcode = i_rift2Core_auto_dcache_client_out_c_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_param = i_rift2Core_auto_dcache_client_out_c_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_size = i_rift2Core_auto_dcache_client_out_c_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_source = i_rift2Core_auto_dcache_client_out_c_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_address = i_rift2Core_auto_dcache_client_out_c_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_data = i_rift2Core_auto_dcache_client_out_c_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_corrupt = i_rift2Core_auto_dcache_client_out_c_bits_corrupt; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_d_ready = i_rift2Core_auto_dcache_client_out_d_ready; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_e_valid = i_rift2Core_auto_dcache_client_out_e_valid; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_e_bits_sink = i_rift2Core_auto_dcache_client_out_e_bits_sink; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_out_a_ready = xbar_auto_in_1_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_b_valid = xbar_auto_in_1_b_valid; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_b_bits_param = xbar_auto_in_1_b_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_b_bits_address = xbar_auto_in_1_b_bits_address; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_c_ready = xbar_auto_in_1_c_ready; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_valid = xbar_auto_in_1_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_opcode = xbar_auto_in_1_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_param = xbar_auto_in_1_d_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_size = xbar_auto_in_1_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_sink = xbar_auto_in_1_d_bits_sink; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_denied = xbar_auto_in_1_d_bits_denied; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_data = xbar_auto_in_1_d_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_corrupt = xbar_auto_in_1_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign buffer_2_clock = clock;
  assign buffer_2_reset = reset;
  assign buffer_2_auto_in_a_valid = i_rift2Core_auto_mmu_client_out_a_valid; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_a_bits_opcode = i_rift2Core_auto_mmu_client_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_a_bits_param = i_rift2Core_auto_mmu_client_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_a_bits_size = i_rift2Core_auto_mmu_client_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_a_bits_source = i_rift2Core_auto_mmu_client_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_a_bits_address = i_rift2Core_auto_mmu_client_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_a_bits_mask = i_rift2Core_auto_mmu_client_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_a_bits_data = i_rift2Core_auto_mmu_client_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_a_bits_corrupt = i_rift2Core_auto_mmu_client_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_in_d_ready = i_rift2Core_auto_mmu_client_out_d_ready; // @[LazyModule.scala 298:16]
  assign buffer_2_auto_out_a_ready = xbar_auto_in_2_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_valid = xbar_auto_in_2_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_opcode = xbar_auto_in_2_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_param = xbar_auto_in_2_d_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_size = xbar_auto_in_2_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_source = xbar_auto_in_2_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_sink = xbar_auto_in_2_d_bits_sink; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_denied = xbar_auto_in_2_d_bits_denied; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_data = xbar_auto_in_2_d_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_corrupt = xbar_auto_in_2_d_bits_corrupt; // @[LazyModule.scala 296:16]
endmodule